© 2004 California Micro Devices Corp. All rights reserved.
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 1
CM1209
4,6 & 8 Channel ESD Protection Arrays
with Zener Supply Clamp
Features
• Four, six or eight channels of ESD protection for
high data rate signals
• Zener diode protects supply rail and eliminates the
need for external by-pass capacitors
•+15 kV contact, +15 kV air ESD protection per
channel (IEC 61000-4-2 standard)
• Low loading capacitance of 6pF typical
• Low supply current
• Available in miniature MSOP and SOIC packages
• Lead-free versions available
Applications
• ESD protection for a variety of electronic equip-
ment
•Set Top Boxes
• Digital TVs
• I/O & VGA Port protection
• Desktop and Notebook computers
•PDAs
• Cellular Phones
Product Description
The CM1209 family of diode arrays are designed to
provide either 4, 6 or 8 channels of ESD protection for
electronic components or sub-systems. Each channel
consists of a pair of diodes which steer the ESD cur-
rent pulse either to the positive (VP) or negative (VN)
supply. In addition, there is an integral Zener diode
between VP and VN to suppress any voltage distur-
bance due to these ESD current pulses. The CM1209
devices will protect against ESD pulses up to 15kV
contact discharge per the International Standard
IEC61000-4-2.
These devices are particularly well-suited for portable
electronics (e.g. cellular phones, PDAs, notebook com-
puters) because of its small package footprint, high
ESD protection level, and low loading capacitance.
They are also suitable for protecting video output lines
and I/O ports in computers, set top boxes, digital TVs
and peripheral equipment.
The CM1209 family of devices is optionally available
with lead-free finishing.
1234
87
6
5
VP
VN
12345
10 9
8
76
VP
VN
1234
87 56
VP
VN
Electrical Schematics
CM1209-04 CM1209-06 CM1209-08
4-Channel 6-Channel 8-Channel
© 2004 California Micro Devices Corp. All rights reserved.
2430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 01/09/04
CM1209
PIN DESCRIPTIONS
CM1209-04 CM1209-06 CM1209-08
NAME PIN NO. PIN NO PIN NO TYPE DESCRIPTION
CH 1 1 1 1 I/O ESD Channel 1
CH 2 2 2 2 I/O ESD Channel 2
CH 3 7 4 3 I/O ESD Channel 3
CH 4 8 5 4 I/O ESD Channel 4
CH 5 6 6 I/O ESD Channel 5
CH 6 8 7 I/O ESD Channel 6
CH 7 9 I/O ESD Channel 7
CH 8 10 I/O ESD Channel 8
VN3,4,5 3 5 GND Negative voltage supply rail or ground reference
rail.
VP6 7 8 Supply Positive voltage supply rail.
PACKAGE / PINOUT DIAGRAMS
Note: These drawings are not to scale.
8-pin SOIC/MSOP
1
2
3
4
8
7
6
5
CH 1
CH 2
VN
CH 3
CH 6
VP
CH 5
CH 4
TOP VIEW
CM1209-06SN/SM
8-pin MSOP
1
2
3
4
8
7
6
5
CH 1
CH 2
VN
VN
CH 4
CH 3
VP
VN
TOP VIEW
CM1209-04MS/MR 10-pin MSOP
1
2
3
4
10
9
8
7
CH 1
CH 2
VN
CH 3
CH 8
CH 7
VP
CH 6
TOP VIEW
CM1209-08MS/MR
56
CH 4
CH 5
CM1209-06MS/MR
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 3
CM1209
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
Note 1: Only one diode conducting at a time.
PART NUMBERING INFORMATION
# of Channels Pins Package
Standard Finish Lead-free Finish
Ordering Part
Number1Part Marking
Ordering Part
Number1Part Marking
4 8 MSOP-8 CM1209-04MS 0904 CM1209-04MR 0914
6 8 SOIC-8 CM1209-06SN CM1209-06S CM1209-06SM CM1209-06SM
6 8 MSOP-8 CM1209-06MS 0906 CM1209-06MR 0916
8 10 MSOP-10 CM1209-08MS 0908 CM1209-08MR 0918
ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING UNITS
Supply Voltage (VP - VN)6.0V
Diode Forward DC Current (Note 1) 20 mA
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -65 to +150 °C
DC Voltage at any channel input (VN - 0.5) to (VP + 0.5) V
Package Power Rating
SOIC Package
MSOP Package
350
200
mW
mW
STANDARD OPERATING CONDITIONS
PARAMETER RATING UNITS
Operating Temperature Range -40 to +85 °C
Operating Supply Voltage (VP - VN)0 to 5.5V
© 2004 California Micro Devices Corp. All rights reserved.
4430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 01/09/04
CM1209
Specifications (cont’d)
Note 1: All parameters specified at TA=-40 to +85°C unless otherwise noted.
Note 2: These parameters guaranteed by design and characterization.
Note 3: From I/O pins to VP or VN only.
Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded.
Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded.
Note 6: These measurements performed with no external capacitor on VP
..
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IPSupply Current (VP-VN)=5.5V; TA=25°C 10 µA
VF ESD Diode Forward Voltage IF = 20mA; TA=25°C 0.65 0.95 V
VZBD Zener Clamp Reverse Breakdown
Voltage
At 1mA; TA=25°C 7 V
ILEAK Channel Leakage Current TA=25°C +0.1 +1.0 µA
CIN Channel Input Capacitance At 1 MHz, VP=5V, via 10K;
VN=0V, VIN=2.5V;
Notes 2 and 6
68pF
VESD ESD Protection
Peak Discharge Voltage at any
channel input and VP rail
Contact discharge per
IEC 61000-4-2 standard
Air discharge per
IEC 61000-4-2 standard
Notes 2, 3, 5, and 6
Notes 2, 3, 5, and 6
+
15
+
15
kV
kV
VCL Channel Clamp Voltage
Positive Transients
Negative Transients
At 8kV ESD HBM;
TA=25°C; Notes 2, 4 and 6
+12.5
- 5.1
V
V
ZPOS Dynamic Resistance of Channel Input
for Positive Transients
I = 1A; TA=25°C; See
Figure 2; Note 6 applies
0.70 Ω
ZNEG Dynamic Resistance of Channel Input
for Negative Transients
I = 1A; TA=25°C; See
Figure 2; Note 6 applies
0.45 Ω
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 5
CM1209
Performance Information
Figure 1. Typical Variation of Channel Input
Capacitance (CIN) vs. Channel Input Voltage (VIN)
(VP = 5V via 10K resistor, VN = 0V)
Figure 2. IV Curve for CM1209
Application Information
Figure 3. Application Example Using the CM1209-06 for I/O Port Protection
0
2
4
6
8
10
012345
Vin
Cin (pF)
Slope = I/Z
POS
Slope = I/Z
NEG
Current [I]
Voltage [V]
V
ZBD
CM1209-06
I/O Port
Buffers Connector
Expansion
Typical ESD Protection
124568
73
0.22
µ
F
*
* Optional capacitor should be placed as close as
possible to the V
P
pin on all CM1209 devices.
Refer to ’Design Considerations’ text.
© 2004 California Micro Devices Corp. All rights reserved.
6430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 01/09/04
CM1209
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 4, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L1 and L2. The volt-
age VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt
+ L2 x d(IESD ) / dt
where IESD is the ESD current pulse, and VSUPPLY is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(IESD)/dt can be approximated by
∆IESD/∆t, or 30/(1x10-9). So just 10nH of series induc-
tance (L1 and L2 combined) will lead to a 300V incre-
ment in VCL!
Similarly for negative ESD pulses, parasitic series
inductance from the VN pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
The CM1209 has an integrated Zener diode between
VP and VN. This greatly reduces the effect of supply rail
inductance L2 on VCL by clamping VP at the breakdown
voltage of the Zener diode. However, for the lowest
possible VCL, especially when VP is biased at a voltage
significantly below the Zener breakdown voltage, it is
recommended that a 0.22µF ceramic chip capacitor be
connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the VP pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See California Micro Devices Application Note AP209,
“Design Considerations for ESD Protection", under
Applications at www.calmicro.com.
Figure 4. Application of Positive ESD Pulse between Input Channel and Ground
N
L
2
L
1
V
P
V
PATH OF ESD CURRENT PULSE I
ONE
CHANNEL
OF
CM1209
CHANNEL
INPUT
GROUND RAIL
CHASSIS GROUND
POSITIVE SUPPLY RAIL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
LINE BEING
PROTECTED
ESD
0.22µFD1
2
D
0A
20A
VCL
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 7
CM1209
Mechanical Details
CM1209 devices are packaged in 8-pin and 10-pin
MSOP and 8-pin SOIC packages. Dimensions for
these packages are presented on the following pages.
For complete information on the MSOP-8/-10 or SOIC-
8 packages, see the specific California Micro Devices
Package Information document.
MSOP-8 Mechanical Specifications
* This is an approximate number which may vary.
Package Dimensions for MSOP-8
PACKAGE DIMENSIONS
Package MSOP
Pins 8
Dimensions Millimeters Inches
Min Max Min Max
A0.87 1.17 0.034 0.046
A1 0.05 0.25 0.002 0.010
B0.30 (typ) 0.012 (typ)
C0.18 0.007
D2.90 3.10 0.114 0.122
E2.90 3.10 0.114 0.122
e0.65 BSC 0.025 BSC
H4.78 4.98 0.188 0.196
L0.52 0.54 0.017 0.025
# per tube 80 pieces*
# per tape
and reel
4000 pieces
Controlling dimension: inches
Mechanical Package Diagrams
E
D
H
1234
8765
L
END VIEW
C
e
B
A
A1
SEATING
PLANE
SIDE VIEW
TOP VIEW
Pin 1
Marking
© 2004 California Micro Devices Corp. All rights reserved.
8430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 01/09/04
CM1209
Mechanical Details (cont’d)
MSOP-10 Mechanical Specifications
* This is an approximate number which may vary.
Package Dimensions for MSOP-10
PACKAGE DIMENSIONS
Package MSOP
Pins 10
Dimensions Millimeters Inches
Min Max Min Max
A0.75 0.95 0.028 0.038
A1 0.05 0.15 0.002 0.006
B0.18 0.40 0.006 0.016
C0.18 0.007
D2.90 3.10 0.114 0.122
E2.90 3.10 0.114 0.122
e0.50 BSC 0.0196 BSC
H4.76 5.00 0.187 0.197
L0.40 0.70 0.0137 0.029
# per tube 80 pieces*
# per tape
and reel
4000
Controlling dimension: inches
Mechanical Package Diagrams
E
D
H
1234
10 9 8 7
L
END VIEW
C
e
B
A
A1
SEATING
PLANE
SIDE VIEW
TOP VIEW
6
5
Pin 1
Marking
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲www.calmicro.com 9
CM1209
Mechanical Details (cont’d)
SOIC-8 Mechanical Specifications
* This is an approximate number which may vary.
Package Dimensions for SOIC-8
PACKAGE DIMENSIONS
Package SOIC
Pins 8
Dimensions Millimeters Inches
Min Max Min Max
A1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B0.33 0.51 0.013 0.020
C0.19 0.25 0.007 0.010
D4.80 5.00 0.189 0.197
E3.80 4.19 0.150 0.165
e1.27 BSC 0.050 BSC
H5.80 6.20 0.228 0.244
L0.40 1.27 0.016 0.050
# per tube 100 pcs*
# per tape
and reel
2500 pcs
Controlling dimension: inches
Mechanical Package Diagrams
E
D
H
1234
8765
L
END VIEW
C
e
B
A
A1
SEATING
PLANE
SIDE VIEW
TOP VIEW
Pin 1
Marking
