Order N umb e r: 300641-004US
Notice: The Int e l ® 6300ESB I/O Con troller Hub m ay contain des ign def ec ts or e rrors known a s errata wh ich
may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Intel® 6300ESB I/O Controller Hub
Datasheet
Novem b er 20 07
Intel® 6300ESB I/O Controller Hub
DS November 2007
2Order Number: 300641-0 04US
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEPRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECT UAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® 6300ESB I/O Controller Hub may contain design defects or errors known as errata w hich may cause the product to deviate from published
specifications.which may cause the product to deviate from published specifications. which may cause the p r oduct to deviate from published
specification s. Current characterized errata are av ailab le on request.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from futur e changes to them.
The Intel® 6300ESB I/O Controller Hub may contain design defects or errors known as errata w hich may cause the product to deviate from published
specification s. Current characterized errata are av ailab le on request.
Contact your local I ntel sales office or your distributor to obtain the latest specifications and before p lacing your product order.
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Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 3
—Intel® 6300ESB ICH
Intel® 6300ESB I/O Control ler Hub
Product Features
8-Bit Hub Interface
266 Mbyte/ s maximum throughput
Parallel Ter mina tion scheme for lon ger
tr ace lengths
Supports Low e r Voltages as p e r H ub
Interface 1.5 spe c
PCI-X B us I/F
Support s PCI-X Rev 1.0 S pec ifi cation at
66 MHz
Supports PCI Rev 2.2 Specification at 33
MHz
Support external master devices on PCI
4 @ PCI 33 MHz
2 @ PCI 64/66 MHz
4 @ PCI-X 64/66 MHz (two slots and
two soldered down devices)
S uppo r t for 64-bit addr es sing on PCI-X
using DAC protocol
PCI Bus I/F
Support s PCI 32b/33 M Hz
120 Mbyte/ s throughp ut
Supports PCI Rev 2.2 Specification at 33
MHz
Supp orts 4 exte rn a l master d e vices @
33 MHz
S uppo r t for 44-bit addr es sing on PCI
using DAC p rotocol.
4 slots supported
Integrated IDE Controller
Supports “Native Mode” Register and
Interrupts
Supports faster PIO timi ngs for non-
data cycles
Independent timing of up to four d riv es,
with separate Primary and Secondary
IDE cab le conne ctions
Supports U ltra 100 DMA Mode T ransf ers
up to 100 Mbytes/s for reads from disk;
88.88 Mby tes/s for wr ite s to disk , as
well as Ultra66 and Ultra33 DMA mod es.
PIO Mode four tr an sf ers up to 14
Mbytes/s
Integrated Serial A TA Host Controllers
Independent DMA operation on two
ports
Data transfer rates up to 150 Mbyte/s
Alt e r na t e De v i ce I D and R A I D C la ss
Code o ption fo r support of Soft RAID
Power Managem ent Logic
ACPI 1.0 compliant
ACPI-defined power states S1 (Stop
Grant), S3 (STR), S4 (STD), S5 (SO FF)
ACPI Power Management Timer
—SMI# Generation
—PCI PME#
Sup po rts T HRM TR IP# inp ut,
SYS_RESER# input and SLP_S4#
output
Support for APM-based legacy power
management for non- ACPI
implementations
External G lue Inte gratio n
Integrated Pull-up, Pull-down and Series
Termination re sistor s on IDE, CPU I/F
Int egr ate d Pull -down an d Serie s
res ist ors on USB
Enhanced Hub I/F buffers improve routing
flexi bi lity (Not available with a ll Me mory
Controller Hubs)
Firmware Hub (FWH) I/F sup por ts BIOS
Memory size up to 8 Mbytes
Low Pin Count (LPC) I/F
N e w: N o I SA/ X-Bu s su p port
A llows connections of de vices suc h as
Super I/O , microcontrollers, customers
ASICs
S u p ports two M a st e r/ D M A device s
Memory siz e up to 8 Mbytes
Enhanced DMA Contro ller
Two cascaded 8237 D MA controllers
—Supports LPC DMA
S upports D M A Collection B u ffe r to
provide
Type- F DMA perfor m a nce for al l DMA
channels
Re al -T ime C lock
256-byte battery-back e d CMOS RAM
Syst em TCO Reduct ion Circuits
Timers to generate SMI# and Reset
upon detection of sy st e m hang
Int errupt capabilit y t o OS- spec i fic
ma na geab ility extension an d OS
capability to call TCO BIOS Timers to
detect improper CPU reset
Alert On Lan (AOL) to enable heartbeats
and system event reporting via LAN
controller
—Supports CPU BIST
Su p ports ability to disable exte rn al
devices
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
4Order Number: 300641-004US
USB
Include s on e E HCI US B 2 ho st
controllers, a total of four ports (shared
with the UHCI p orts)
Two UHCI Host Controllers for a total of
four ports (shared with EHCI ports)
New: supports a USB 2.0 High -spe ed
Debug Port
Supports wake-up from sleeping states
S1-S4
Suppor t s legac y K eyboard/Mous e
software with USB-based keyboard and
mouse
SMBus
Flexible SMBus/SMLink architecture to
optimize f or ASF and eliminate board
requ ire me nts of SMBus 2.0 compliance
Supports SM B us 2.0 Specifica tion
Host interface allows CPU to
communicate via SMBus
Sla ve interface allows an extern al
Micr ocon troller to a ccess s ys tem
resources
Compatible with most 2-wire
components that are also I2C
compatible
AC'97 Link for Audio and Telephony
CODECs
New: Thi rd AC_SDATA_IN Li ne fo r th r ee
codec support
AC’97 2.2 compliant
New: Independent bus master logic for
8 channe ls (PCM In/Out, Mic 1 Input,
Mic 2 Input , Mod em In/Out, S /PD IF
Out)
Separate independent PCI functions for
Audio and Modem
Support for up four to six channels of
PCM aud io out p u t (full AC3 d e cod e )
Support for 20-bit sample
Suppor t for AC P I device stat es - D0 a nd
D3
Int er rup t Controller
Sup p orts up to 12 PCI int errup t pin s;
four are not shared
Two cascad ed 82C59 with 15 inter rupts
Suppor ts PCI sche me for delivering
int er rup ts a s write cycles (MS I)
Integrated I/O APIC capability with 24
interrupts
Supports Serial Interrupt Protocol
Supports Front-Side Message Interrupt
Delivery
New: M ultimed ia Timers based on 82C54
Inc ludes three timer comparators
System ti me r, Refr esh re ques t, S peak er
tone output
One-shot and per iod ic interrupts
supported
New: Watchdog Timer
Two-Sta ge Wat chdog with ind e pende nt
count values for each stage
First stage generates an I N T or SMI
Second stage drives external pin active
until cleared by a system reset or power
cycle
Configuration option for write-once
enabling (count values can still change)
Co nfi gurable granular ity f r o m 1 µ s t o 10
min
New: Integrated 16550 comp atib le UARTs
Enable/di sa bl e per UARTs
Seria l inte rru p ts
Can disable when external SIO used
New: Port 60/64 Emulation
Programmable interrupt genera tion on
writes
Positive decode to Port 60/64 emulation
registers
GPIO
Four GPOs capabl e of directly driving
LEDs
Two GPOs maintain state durin g and
afte r reset
1.5 V operation with 3.3 V I/O. 5 V
tolerance on many buffers, includ ing IDE.
Pac k a g e 37. 5 x 37 .5 mm 68 9 BGA
Process P859.6
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 5
—Intel® 6300ESB ICH
System Block Diagrams
Figure 1. Workstation/PC Model
B2475-02
CPU
Graphics
SM Bus
Memory
1GB to 4 GB
Hublink 1.5
AGP
HL 1.5
PCI
Intel
®
875P MCH
Intel
®
6300ESB
I/O
Controller
Hub
GBE
PCI-X
GBE / SCSI
LPC
FWH / SIO IDE Hard Disk
SATA Hard Disk
SATA Hard Disk
IDE Hard Disk /
CD-DVD
USB 2.0
Legacy Peripherals
AC'97
GPIO
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
6Order Number: 300641-004US
Figure 2. Low to Mid-Range Communication Appliance Model (Diskless)
B2476-02
CPU
Memory
256 MB
to 1GB
Hublink
Processor System Bus
HL 1.5
GBE
PCI-X
GBE /
2D Graphics
Hard Disk
SIO
GPIO's
SM Bus
Intel
®
875P MCH
Intel
®
6300ESB
I/O
Controller
Hub
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 7
—Intel® 6300ESB ICH
Figure 3. Value Server, Ultra-Dense Server and Low-End Server Blade
B2477-03
CPU
SM Bus
Memory
1GB to 2 GB
Processor System Bus
Hublink 1.5
HL 1.5
GBE
PCI
2D Graphics
PCI-X
GBE
LPC
BMC
IDE Hard Disk
Hard Disk
SATA Hard Disk
SATA Hard Disk
IDE
USB 2.0
GPIO
Intel
®
E7210 MCH
Intel
®
6300ESB
I/O
Controller
Hub
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
8Order Number: 300641-004US
Contents
1Introduction............................................................................................................49
1.1 About This Document.........................................................................................49
2 Intel
® 6300ESB ICH and System Clock Domains .....................................................53
3 Signal Description....................................................................................................55
3.1 Hub Interface to Host Controller ..........................................................................55
3.2 Firmware Hub Interface..................................................... .................................56
3.3 PCI Interface.....................................................................................................57
3.4 PCI-X Interface ........................................................................ .........................60
3.5 SATA Interface..................................................................................................64
3.6 IDE In terface ....................................................................................................64
3.7 LPC I/F.................................................... .........................................................66
3.8 Interrupt Interface................................. ............................................................66
3.9 USB Interface....................................................................................................67
3.10 Power Management Interface..............................................................................68
3.11 CPU Interface....................................................................................................69
3.12 SMBus Interface................................................................................................71
3.13 System Management Interface ............................................................................71
3.14 Real Time Clock Interface ................................................................ ...................71
3.15 Other Clocks .....................................................................................................72
3.16 Miscellaneous Signals.........................................................................................72
3.17 AC’97 Link ........................................................................................................73
3.18 Universal Asynchronous Receive and Transmit (UART0,1) .......................................73
3.19 General Purpose I/O............................................................... ............................74
3.20 Power and Ground .............................................................................................76
3.21 Pin Straps.........................................................................................................77
3.21.1 Functional Straps....................................................................................77
3.22 Revision and Device ID Table ..............................................................................78
4Intel
® 6300ESB ICH Power Planes and Pin States....................................................79
4.1 Power Planes.....................................................................................................79
4.2 Integrated Pull-Ups and Pull-Downs........................................ ..............................80
4.3 IDE Integrated Series Termination Resistors..........................................................81
4.4 Output and I/O Signals Planes and States.............................................................81
4.5 Power Planes for Input Signals ............................................................................83
5 Functional Description .............................................................................................91
5.1 Hub Interface to PCI Bridge (D30:F0).......... ............. ............................................91
5.1.1 PCI Bus Interface....................................................................................91
5.1.2 PCI-to-PCI Bridge Model..........................................................................92
5.1.3 IDSEL to Device Number Mapping.............................................................92
5.1.4 SERR# Functionality................................................................................ 92
5.1.5 Parity Error Detection....................... .......................................................95
5.1.6 Standard PCI Bus Configuration Mechanism................................................96
5.1.6.1 Type 0 to Type 0 Forwarding ......................................................96
5.1.6.2 Type 1 to Type 0 Conversion.......................................................96
5.1.7 PCI Dual Address Cycle (DAC) Support.................. ....................................97
5.2 LPC Bridge (with System and Management Functions) (D31:F0)...............................97
5.2.1 LPC Cycle Types ............................................................................ .........98
5.2.1.1 Start Field De finition..................................................................98
5.2.1.2 Cycle Type/Direction (CYCTYPE + DIR)...................................... ...99
5.2.1.3 SIZE........................................................................................99
5.2.1.4 SYNC.......................................................................................99
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 9
Contents—Intel® 6300ESB ICH
5.2.1.5 SYNC Time-Out ...................................................................... 100
5.2.1.6 SYNC Error Indication.............................................................. 100
5.2.1.7 LFRAME# Usage ................................. .................................... 101
5.2.1.8 I/O Cycl es.............................................................................. 102
5.2.1.9 Bus Master Cycles................................................................... 102
5.2.1.10 LPC Power Management..................... ...................................... 102
5.2.1.11 Configuration and Intel® 6300ESB ICH Implications .................... 102
5.3 DMA Operation (D31:F0).................................................................................. 103
5.3.1 DMA Overview ..................................................................................... 103
5.3.2 Channel Priority ................................................................................... 104
5.3.2.1 Fixed Priority.......................................................................... 104
5.3.2.2 Rotating Priority ..................................................................... 104
5.3.3 Address Compatibility Mode................................................................... 104
5.3.4 Summary of DMA Transfer Sizes ............................................................ 105
5.3.4.1 Address Shifting When Programmed for 16-Bit I/O Count by Words105
5.3.5 Autoinitialize........................................................................................ 105
5.3.6 Software Commands................................................. ............................ 106
5.3.6.1 Clear Byte Pointer Flip-Flop...................................................... 106
5.3.6.2 DMA Master Clear .... ............................................................... 106
5.3.6.3 Clear Mask Register ................................................................ 106
5.4 LPC DMA........................................................................................................ 106
5.4.1 Ass erting DMA Requests........................................................................ 106
5.4.2 Abandoning DMA Requests .................................................................... 107
5.4.3 General Flow of DMA Transfers............................................................... 108
5.4.4 Terminal Count (TC)............................................................................. 108
5.4.5 Verify Mode......................................................................................... 108
5.4.6 DMA Request Deassertion...................................................................... 108
5.4.7 SYNC Field/LDRQ# Rules....................................................................... 109
5.5 8254 Timers (D31:F0) ..................................................................................... 110
5.5.1 Counter 0, System Timer ...................................................................... 110
5.5.2 Counter 1, Refresh Request Signal.......................................................... 110
5.5.3 Counter 2, Speaker Tone....................................................................... 110
5.5.4 Timer Programming.............................................................................. 110
5.5.5 Reading from the Interval Timer............................................................. 111
5.5.5.1 Simple Read ........................................................................... 112
5.5.5.2 Counter Latch Command.......................................................... 112
5.5.5.3 Read Back Command .............................................................. 113
5.6 8259 Interrupt Controllers (PIC) (D31:F0) ................. ......................................... 113
5.6.1 Interrupt Handling................................................................................ 114
5.6.1.1 Generating Interrupts.............................................................. 114
5.6.1.2 Acknowledging Interrupts ........................................................ 115
5.6.1.3 Hardware/ Software Interrupt Sequence ..................................... 115
5.6.2 Initialization Command Words (ICWx)..................................................... 115
5.6.2.1 ICW1 .................................................................................... 116
5.6.2.2 ICW2 .................................................................................... 116
5.6.2.3 ICW3 .................................................................................... 116
5.6.2.4 ICW4 .................................................................................... 116
5.6.3 Operation Command Words (OCW)......................................................... 116
5.6.4 Modes of Operation .................................................. ............................ 117
5.6.4.1 Fully Nested Mode................................................................... 117
5.6.4.2 Special Fully-Nested Mode........................................................ 117
5.6.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 117
5.6.4.4 Specific Rotation Mode (Specific Priority).................................... 117
5.6.4.5 Poll Mode............................................................................... 118
5.6.4.6 Cascade Mode ........................................................................ 118
5.6.4.7 Edge and Level Triggered Mode ................................................ 118
5.6.4.8 End of Interrupt Operations...................................................... 118
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
10 Order Number: 300641-004US
5.6.4.9 Norm al End of Interrupt ...........................................................119
5.6.4.10 Automatic End of Interrupt Mode...............................................119
5.6.5 Ma sking Interrupts................................................................................119
5.6.5.1 Masking on an Individual Interrupt Request ................................119
5.6.5.2 Special Mask Mode ........................................................... .......119
5.6.6 Steering PCI Interrupts..........................................................................119
5.6.7 Special Handling of IRQ1 and IRQ12........................................................120
5.7 Advanced Interrupt Controller (APIC) (D29:F5)....................................................121
5.7.1 Interrupt Handling................................................................................121
5.7.2 SMI/NMI/INIT/ExtINT Delivery Modes......................................................121
5.7.3 Boot Interrupt......................................................................................122
5.7.4 Interrupt Mapping.................................................. ...............................123
5.7.5 APIC Bus Functional Description..............................................................124
5.7.5.1 APIC Bus Arbitration................................................................125
5.7.5.2 Bus Message Formats ..............................................................126
5.7.6 PCI Message-Based Inte rrupts................................................................132
5.7.6.1 Theory of Operation.................................................................132
5.7.6.2 Registers and Bits Associated with PCI Interrupt Delivery .............133
5.7.7 Processor System Bus Interrupt Delivery .................................................133
5.7.7.1 Theory of Operation.................................................................133
5.7.7.2 Edge-Triggered Operation.........................................................134
5.7.7.3 Level-Triggered Operation ........................................................134
5.7.7.4 Registers Associated with Processor System Bus Interrupt Delivery134
5.7.7.5 Interrupt Message Format ........................................................134
5.8 Serial Interrupt (D31:F0) ..................................................................................135
5.8.1 Start Frame .........................................................................................136
5.8.2 Data Frames ........................................................................................136
5.8.3 Stop Frame.............................................................................. ............137
5.8.4 Specific Interrupts Not Supported via SERIRQ...........................................137
5.8.5 Data Frame Format...............................................................................137
5.9 Real Time Clock (D31:F0).................................................................................138
5.9.1 RTC Overview ......................................................................................138
5.9.1.1 Update Cycles.........................................................................139
5.9.1.2 Interrupts ..............................................................................139
5.9.1.3 Lockable RAM Ranges ..............................................................139
5.9.1.4 Century Rollover ................... ..................................................139
5.9.1.5 Clearing Battery-Backed RTC RAM .............................................140
5.10 Processor Interface (D31:F0) ............................................................................141
5.10.1 Processor Interface Signals ....................................................................141
5.10.1.1 A20M# ..................................................................................141
5.10.1.2 INIT#....................................................................................141
5.10.1.3 FERR#/IGNNE# (Coprocessor Error)..........................................142
5.10.1.4 NMI.......................................................................................143
5.10.1.5 STPCLK# and CPUSLP# Signals .................................................143
5.10.2 Dual Processor Issues ...........................................................................143
5.10.2.1 Signal Differences ...................................................................143
5.10.2.2 Dual Processor Power Management............................................143
5.11 Power Management (D31:F0)............................................. ...............................145
5.11.1 Features..............................................................................................145
5.11.2 Intel® 6300ESB ICH Power States and Transition Rules .............................146
5.11.3 System Power Planes ............................................................. ...............148
5.11.4 Intel® 6300ESB ICH Power Planes ..........................................................148
5.11.5 SMI#/SCI Generation............................................................................149
5.11.6 Dynamic Processor Clock Control ............................................................152
5.11.6.1 Throttling Using STPCLK#.........................................................153
5.11.6.2 Transition Rules among S0/Cx and Throttling States ....................153
Intel® 63 00ESB I/O Controller Hub
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Contents—Intel® 6300ESB ICH
5.11.6.3 STPCLK# Implementation Notes ............................................... 154
5.11.7 Sleep States........................................................................................ 155
5.11.7.1 Sleep State Overview.............................................................. 155
5.11.7.2 Initiating Sleep Sta te............................................................... 155
5.11.7.3 Exiting Sleep States ................................................................ 156
5.11.7.4 Sx-G3-Sx, Handling Power Failures ........................................... 157
5.11.8 Thermal Management ........................................................................... 158
5.11.8.1 THRM# Signal ........................................................................ 158
5.11.8.2 THRM# Initiated Passive Cooling............................................... 158
5.11.8.3 THRM# Override Software Bit................................................... 159
5.11.8.4 Processor Initiated Passive Cooling (Via Programmed
Duty Cycle on STPCLK#).. ........................................................ 159
5.11.8.5 Active Cooling ........................................................................ 159
5.11.9 Event Input Signal Usage ...................................................................... 159
5.11.9.1 PWRBTN# - Power Button........................................................ 159
5.11.9.2 RI# - Ring Indicate ................................................................. 160
5.11.9.3 PME# - PCI Power Management Event....................................... 161
5.11.9.4 SYS_RESET# Signal................................................................ 161
5.11.9.5 THRMTRIP# Signal.................................................................. 161
5.11.10ALT Access Mode.................................................................................. 162
5.11.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 163
5.11.10.2Programmable Interrupt Controller (PIC) Reserved Bits................ 164
5.11.10.3Read-Only Registers with Write Paths in ALT Access Mode............ 165
5.11.11System Power Supplies, Planes, and Signals ................... ......................... 165
5.11.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 165
5.11.11.2PWROK Signal........................................................................ 165
5.11.11.3VRMPWRGD Signal.................................................................. 166
5.11.11.4Controlling Leakage and Power Consumption during Low-Power States
167
5.11.12Clock Generators.................................................................................. 167
5.11.13Legacy Power Management Theory of Operation....................................... 168
5.11.13.1Overview............................................................................... 168
5.11.13.2APM Feature Notes.................................................................. 168
5.12 System Management (D31:F0).......................................................................... 168
5.12.1 Overview of System Management Functions............................................. 168
5.12.2 TCO Signal Usa ge ................................................................................. 169
5.12.2.1 Intruder# Signal............................................................ ......... 169
5.12.2.2 Pin Straps.............................................................................. 169
5.12.2.3 SMLINK Signals............. ........................... ........................... ... 169
5.12.3 TCO Theory of Operation....................................................................... 170
5.12.3.1 Overview............................................................................... 170
5.12.3.2 Detecting a System Lockup...................................................... 170
5.12.3.3 Handling an OS Loc kup............................................................ 170
5.12.3.4 Handling an Intruder ............................................................... 171
5.12.3.5 Detecting Improper FWH Programming...................................... 171
5.12.3.6 Handling an ECC Error or Other Memory Error ............................ 171
5.12.4 Heartbeat and Event Reporting through SMLink/SMbus ............................. 172
5.12.4.1 Overview............................................................................... 172
5.13 General Purpose I/O............................... ......................................................... 176
5.13.1 GPIO Mapping..................................... ................................................. 176
5.13.2 Power Wells......................................................................................... 178
5.13.3 SMI# and SCI Routing ... ....................................................................... 178
5.13.4 Triggering ........................................................................................... 178
5.14 IDE Controller (D31:F1) ................................................................................... 178
5.14.1 Overview ............................................................................................ 178
5.14.2 PIO Transfers ..................................... ................................................. 179
5.14.2.1 Overview............................................................................... 179
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
12 Order Number: 300641-004US
5.14.2.2 IDE Port Decode......................................................................179
5.14.2.3 IDE Legacy Mode and Native Mode ............................................179
5.14.2.4 PIO IDE Timing Modes .............................................................180
5.14.2.5 IOR DY Masking.......................................................................181
5.14.2.6 PIO 32-Bit IDE Data Port Accesses........... ..................................181
5.14.2.7 PIO IDE Data Port Prefetching and Posting..................................181
5.14.3 Bus Master F unction ..............................................................................182
5.14.3.1 Physical Region Descriptor Format.............................................182
5.14.3.2 Line Buffer ...................... .......................................................183
5.14.3.3 Bus Master IDE Timings ...........................................................183
5.14.3.4 Interrupts ..............................................................................183
5.14.3.5 Bus Master IDE Operation ........................................................184
5.14.3.6 Error Conditions............................................................... .......185
5.14.3.7 8237-Like Protocol ..................................................................185
5.14.4 Ultra ATA/33 Protocol............................................................................186
5.14.4.1 Signal Desc riptions..................................................................186
5.14.4.2 Operation...............................................................................187
5.14.4.3 CRC Calculation ......................................................................187
5.14.5 Ultra ATA/66 Protocol............................................................................188
5.14.6 Ultra ATA/100 Protocol..........................................................................188
5.14.7 Ultra ATA/33/66/100 Timing ..................................................................188
5.15 SATA Host Controller (D31:F2)..........................................................................189
5.15.1 Overview.............................................................................................189
5.15.2 Theory of Operation..............................................................................189
5.15.2.1 Standard ATA Emulation...........................................................189
5.15.2.2 48-bit LBA Operation (Logical Block Addressing)..........................189
5.15.3 Hot Plug Operation................................................................................189
5.15.4 Power Management Operation................................. ...............................189
5.15.4.1 Power State Mappings.... ..........................................................190
5.15.4.2 Power State Transitions............................................................191
5.15.4.3 SMI Trapping (APM).................................................................191
5.15.5 SATA Interrupts....................................................................................192
5.15.6 SATALED#...........................................................................................192
5.16 Multimedia Event Timers...................................................................................192
5.16.1 Overview.............................................................................................192
5.16.2 Timer Accuracy ....................................................................................193
5.16.3 Interrupt Mapping.................................................................................193
5.16.4 Periodic vs. Non-Periodic Modes..............................................................193
5.16.5 Enabling the Timers ..............................................................................195
5.16.6 Interrupt Levels....................................................................................195
5.16.7 Handling Interrupts...............................................................................195
5.16.8 Issues Related to 64-bit Timers with 32-bit Processors...............................195
5.17 USB UHCI Controllers (D29:F0 and F1).......... .....................................................196
5.17.1 Overview.............................................................................................196
5.17.2 Data Structures in Main Memory.............................................................196
5.17.2.1 Frame List Pointer ...................................................................196
5.17.2.2 Transfer Descriptors (TD).........................................................197
5.17.2.3 Queue Head (QH)....................................................................201
5.17.3 Data Transfers to/from Main Memory ......................................................202
5.17.3.1 Executing the Schedule............................................................202
5.17.3.2 Processing Transfer Descriptors.................................................203
5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction 204
5.17.3.4 Transfer Queuing ....................................................................204
5.17.4 Data Encoding and Bit Stuffing ...............................................................208
5.17.5 Bus Protocol.........................................................................................208
5.17.5.1 Bit Ordering............................................................................208
5.17.5.2 SYNC Field .............................................................................208
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Contents—Intel® 6300ESB ICH
5.17.5.3 Packet Field Formats ............................................................... 208
5.17.5.4 Address Fields........................................................................ 210
5.17.5.5 Frame Number Field................................................................ 211
5.17.5.6 Data Field.............................................................................. 211
5.17.5.7 Cyclic Redund ancy Che ck (CRC)................................................ 211
5.17.6 Packet Formats.................................................................................... 211
5.17.6.1 Token Packets........................................................................ 211
5.17.6.2 Start of Frame Packets ............................................................ 212
5.17.6.3 Data Packets.......................................................................... 212
5.17.6.4 Handshake Packets................................................................. 213
5.17.6.5 Handshake Responses............................................................. 213
5.17.7 USB Interrupts ..................................................................................... 214
5.17.7.1 Overview............................................................................... 214
5.17.7.2 Transaction Ba sed Interrup ts.................................................... 214
5.17.7.3 Non-Transaction Based Interrupts............................................. 216
5.17.8 USB Power Management ....................................................................... 216
5.17.9 USB Legacy Keyboa rd O peration ............................................................ 217
5.18 USB EHCI Controller (D29:F7)........................................................................... 221
5.18.1 Overview ............................................................................................ 221
5.18.2 EHC Initialization.................................................................................. 221
5.18.2.1 Power On............................................................................... 222
5.18.2.2 BIOS Initialization................................................................ ... 222
5.18.2.3 Driver Initialization ................................................................. 222
5.18.2.4 EHC Resets............................................................................ 222
5.18.3 Data Structures in Ma in Memory............................................................. 223
5.18.4 USB 2.0 Enhanced Host Controller DMA.. ................................................. 224
5.18.4.1 Periodic List Execution............................................................. 224
5.18.4.2 Asy nchronous List Execution .................................................... 226
5.18.5 Data Encoding and Bit Stuffing............................................................... 227
5.18.6 Packet Formats.................................................................................... 227
5.18.7 USB EHCI Interrupts and Error Conditions ............................................... 227
5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads.............................. 228
5.18.8 USB EHCI Power Management................................................................ 228
5.18.8.1 Pause Feature ........................................................................ 228
5.18.8.2 Suspend Feature..................................................................... 229
5.18.8.3 ACPI Device States ................................................................. 229
5.18.8.4 ACPI System States ................................................................ 229
5.18.8.5 Low-power system Considerations ............................................. 229
5.18.9 In teraction with Classic Host Controllers.................................................. 230
5.18.9.1 Port-Routing Logic .................................................................. 230
5.18.9.2 Device Connects..................................................................... 231
5.18.9.3 Device Disconnects ............................. .................................... 231
5.18.9.4 Effect of Resets on Port-Routing Logic........................................ 232
5.18.10USB 2.0 Legacy Keyboard Operati on....................................................... 232
5.18.11USB 2.0 EHCI Based Debug Port.................................................... ......... 232
5.18.11.1Overview............................................................................... 233
5.18.11.2Theory of Operation ................................................................ 233
5.19 SMBus Controller Functional Description (D31:F3) ............................................... 237
5.19.1 Overview ............................................................................................ 237
5.19.2 Host Controller..................................................................................... 238
5.19.2.1 Command Protocols ................................................................ 239
5.19.2.2 I2C Behavior .......................................................................... 249
5.19.2.3 Heartbeat for Use with the External LAN Controller...................... 249
5.19.3 Bus Arbitration..................................................................................... 249
5.19.4 Bus Timing.......................................................................................... 249
5.19.4.1 Clock Stretching ..................................................................... 249
5.19.4.2 Bus Time Out (Intel® 6300ESB ICH as SMBus Master)................. 250
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
14 Order Number: 300641-004US
5.19.5 Interrupts/SMI#...................................................................................250
5.19.6 SMBALERT#.........................................................................................251
5.19.7 SMBus CRC Generation and Checking......................................................251
5.19.8 SMBus Slave Interface...........................................................................251
5.19.8.1 Format of Slave Write Cycle......................................................252
5.19.8.2 Format of Read Command........................................................254
5.19.8.3 Format of Host Notify Command................................................256
5.20 AC’97 Controller Functional Description (Audio D31:F5, Modem D31:F6) .................257
5.20.1 Overview.............................................................................................257
5.20.1.1 PCI Power Management ...........................................................260
5.20.2 AC-Link Overview .................................................................................260
5.20.2.1 AC-link Output Frame (SDOUT).................................................263
5.20.2.2 Output Slot 0: Tag Phase .........................................................263
5.20.2.3 Output Slot 1: Command Address Port.......................................264
5.20.2.4 Output Slot 2: Command Data Port ...........................................264
5.20.2.5 Output Slot 3: PCM Playback Left Channel ..................................264
5.20.2.6 Output Slot 4: PCM Playback Right Channel ................................264
5.20.2.7 Output Slot 5: Modem Codec ................................ ....................264
5.20.2.8 Output Slot 6: PCM Playback Center Front Channel......................265
5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear Channels.......265
5.20.2.10Output Slot 9: Play back Sub Woofer Channel ..............................265
5.20.2.11Output Slots 10-11: Reserved............ .......................................265
5.20.2.12Output Slot 12: I/O Control ......................................................265
5.20.2.13AC-Link Input Frame (SDIN).....................................................265
5.20.2.14Input Slot 0: Tag Phase ...........................................................267
5.20.2.15Input Slot 1: Status Address Port/Slot Request Bits .....................267
5.20.2.16Input Slot 2: Status Data Port...................................................268
5.20.2.17Input Slot 3: PCM Record Left Channel.......................................268
5.20.2.18Input Slot 4: PCM Record Right Channel.....................................268
5.20.2.19Input Slot 5: Modem Line.........................................................268
5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data.............268
5.20.2.21Input Slots 7-11: Reserved.......................................................268
5.20.2.22Input Slot 12: I/O Status .........................................................268
5.20.2.23Reg ister Access.......................................................................269
5.20.3 AC-Link Low Power Mode.......................................................................270
5.20.3.1 External Wake Event................................................................270
5.20.4 AC‘97 Cold Reset..................................................................................271
5.20.5 AC‘97 Warm Reset................................................................................271
5.20.6 System Reset.......................................................................................273
5.20.7 Hardware Assist to Determine AC_SDIN Used Per Codec............................273
5.20.8 Software Mapping of AC_SDIN to DMA Engine ..........................................274
6 R egi ster and Memory Mapping...............................................................................275
6.1 PCI Devices and Functions ................................................................................275
6.2 PCI Configuration Map......................................................................................277
6.3 I/O Map..........................................................................................................278
6.3.1 Fixed I/O Address Ranges......................................................................278
6.3.2 Variable I/O Decode Ranges...................................................................281
6.4 Memory Map...................................................................................................283
6.4.1 Boot-Block Update Scheme....................................................................285
7 H ub In terface to PC I B ridge Re giste r s (D30:F0).....................................................287
7.1 PCI Configuration Registers (D30:F0) .................................................................287
7.1.1 Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0)....................288
7.1.2 Offset 02 - 03h: DID—Device ID Register (HUB-PCID30:F0) ....................288
7.1.3 Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)...................289
7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) ..
290
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Contents—Intel® 6300ESB ICH
7.1.5 Offset 08h: RID—Revision Identification Register
(HUB-PCID30:F0).............................................................................. 291
7.1.6 Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0).................. 291
7.1.7 Offset 0Bh: BCC—Base-Class Code Register
(HUB-PCID30:F0).............................................................................. 291
7.1.8 Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0) ..
292
7.1.9 Offset 0Eh: HEADTYP—Header Type Register
(HUB-PCID30:F0).............................................................................. 292
7.1.10 Offset 18h: PBUS_NUM—Primary Bu s Num ber Register (HUB-PCI—D30:F0) . 292
7.1.11 Offset 19h: S BUS_NUM—Secondary Bus Number Register (HUB-PCI—D30:F0)...
293
7.1.12 Of fset 1A: SUB_BUS_NUM—Subordinate Bus Number Regis ter (HUB-PCI—
D30:F0)293
7.1.1 3 O ffset 1Bh: S MLT—Second ary Master La tency Ti mer Reg ister (H UB-PCI—D30 :F0)
293
7.1.14 Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI— D30:F0) ...................... 294
7.1.15 Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCID30:F0) ........................ 295
7.1.16 Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—D30:F0) ... 295
7.1.17 Offset 20 - 21h: MEMBASE—Memory Base Register
(HUB-PCID30:F0).............................................................................. 296
7.1.18 Offset 22 - 23h: MEMLIM—Memory Limit Register
(HUB-PCID30:F0).............................................................................. 297
7.1.19 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory
Base Register (HUB-PCI—D30:F0).......................................................... 298
7.1.20 Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory
Limit Register (HUB-PCI—D30:F0).......................................................... 299
7.1.21 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—
D30:F0)299
7.1.22 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register
(HUB-PCID30:F0).............................................................................. 300
7.1.23 Offset 3Ch: INT_LINE—Inter rupt Line Register
(HUB-PCID30:F0).............................................................................. 300
7.1.24 Of fset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0). 301
7.1.25 Offset 40 - 43h: HI_CMD—Hub Interface Command Control
Register (HUB-PCI—D30:F0).............. .................................................... 304
7.1.26 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device
Hiding Register (HUB-P CID30:F0).................................................. ...... 305
7.1.27 Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—
D30:F0)306
7.1.28 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0)
307
7.1.29 Offset 70h: MTT—Multi-Transaction Timer Register
(HUB-PCID30:F0).............................................................................. 308
7.1.30 Offset 82h: PCI_MAST_STSPCI Master Status Register (HUB-PCI—D30:F0)309
7.1.31 Offset 90h: ERR_CMD—Error Command Register
(HUB-PCID30:F0).............................................................................. 309
7.1.32 Offset 92h: ERR_STS—Error Status Register
(HUB-PCID30:F0).............................................................................. 310
7.1.33 Offset F8h - FBh: MANID— Manufacturer’s ID .......................................... 310
8 LPC I/F Bridge Registers (D31:F0) ........................................................................ 311
8.1 PCI Configuration Registers (D31:F0)........................................................ ......... 311
8.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F0) ..................... 312
8.1.2 Offset 02 - 03h: DIDDevice ID Register (LPC I/F—D31:F0)...................... 313
8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)................................................................................ 313
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
16 Order Number: 300641-004US
8.1.4 Offset 06 - 07h: PCISTA—PCI Device Status
(LPC I/F—D31:F0) ................................................................................314
8.1.5 Offset 08h: RID—Revision ID Register (LPC I/FD31:F0)...........................315
8.1.6 Offset 09h: PI—Programming Interface (LPC I/F—D31:F0).........................315
8.1.7 Offset 0Ah: SCC—Sub-Class Code Register
(LPC I/F—D31:F0) ................................................................................315
8.1.8 Offset 0Bh: BCC—Base-Class Code Register
(LPC I/F—D31:F0) ................................................................................316
8.1.9 Offset 0Eh: HEADTYP—Header Type Register
(LPC I/F—D31:F0) ................................................................................316
8.1.10 Offset 40 - 43h: PMBASE—ACPI Base Address
(LPC I/F—D31:F0) ................................................................................317
8.1.11 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)...........................317
8.1.12 Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31: F0) ........................................319
8.1.13 Offset 54h: TCO_CNTL—TCO Control (LPC I/F—D31:F0) ............................320
8.1.14 Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address
(LPC I/F—D31:F0) ................................................................................321
8.1.15 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)..........................321
8.1.16 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D]
Routing Control (LPC I/F—D31:F0)..........................................................322
8.1.17 Offset 64h: SERIRQ_CNTL—Serial IRQ Control
(LPC I/F—D31:F0) ................................................................................323
8.1.18 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing
Control (LPC I/F—D31:F0) .....................................................................324
8.1.19 Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—D31:F0).
325
8.1.20 Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0).
325
8.1.21 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)326
8.1.22 Offset D0h - D3h: GEN_CNTL—General Control Register
(LPC I/F—D31:F0) ................................................................................327
8.1.23 Offset D4h: GEN_STAGeneral Status (LPC I/FD31:F0)..........................329
8.1.24 Offset D5h: BACK_CNTL—Backed Up Control
(LPC I/F—D31:F0) ................................................................................330
8.1.25 Offset D8h: RTC_CONF—RTC Configuration Register
(LPC I/F—D31:F0) ................................................................................331
8.1.26 Offset E0h: COM_DEC—LPC I/F Communication Port
Decode Ranges (LPC I/F—D31:F0)..........................................................332
8.1.27 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC I/F
D31:F0)333
8.1.28 Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0) ....334
8.1.29 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0).
335
8.1.30 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0)
336
8.1.31 Offset E6h - E7h: LPC_EN—LPC I/F Enables
(LPC I/F—D31:F0) ................................................................................337
8.1.32 Offset E8h: FWH_SEL1—FWH Select 1 Register
(LPC I/F—D31:F0) ................................................................................339
8.1.33 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode
Range 2 (LPC I/F—D31:F0)....................................................................340
8.1.34 Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register
(LPC I/F—D31:F0) ................................................................................341
8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) .
342
8.1.36 Offset F2h: FUNC_DIS—Function Disable Register
(LPC I/F—D31:F0) ................................................................................343
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Contents—Intel® 6300ESB ICH
8.1.37 Offset F4: ETR1—PCI-X Extended Features Register
(LPC I/F—D31:F0)................................................................................ 345
8.1.38 Offset F8h: Manufacturer’s ID................................................................ 345
8.2 DMA I/O Registers............................................................. .............................. 346
8.2.1 DMABASE_CA—DMA Base and Current Address Registers .......................... 348
8.2.2 DMABASE_CC—DMA Base and Current Count Registers............................. 349
8.2.3 DMAMEM_LP—DMA Memory Low Page Registers....................................... 350
8.2.4 DMACMD—DMA Command Register ........................................................ 350
8.2.5 DMASTA—DMA Status Register .............................................................. 351
8.2.6 DMA_WRSMSK—DMA Write Single Mask Register...................................... 352
8.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 352
8.2.8 DMA Clear Byte Pointer Register............................................................. 353
8.2.9 DMA Master Clear Register .................................................................... 354
8.2.10 DMA_CLMSK—DMA Clear Mask Register .................................................. 354
8.2.11 DMA_WRMSK—DMA Write All Mask Register ............................................ 355
8.3 Timer I/O Registers......................................................................................... 355
8.3.1 TCW —Timer Control Word Register........................................................ 356
8.3.1.1 RDBK_CMD—Read Back Command........ .................................... 357
8.3.1.2 LTCH_CMD—Counter Latch Command ....................................... 357
8.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 358
8.3.3 Counter Access Ports Register................................................................ 360
8.4 8259 Interrupt Controller (PIC) Registers ........................................................... 360
8.4.1 Interrupt Controller I/O MAP.................................................................. 360
8.4.2 ICW1—Initialization Command Word 1 Register........................................ 361
8.4.3 ICW2—Initialization Command Word 2 Register........................................ 362
8.4.4 ICW3—Master Controller Initialization Command Word 3 Register............... 363
8.4.5 ICW3—Slave Controller Initialization Command Word 3 Register................. 363
8.4.6 ICW4—Initialization Command Word 4 Register........................................ 364
8.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register.................... 364
8.4.8 OCW2—Operational Control Word 2 Register............................................ 365
8.4.9 OCW3—Operational Control Word 3 Register............................................ 366
8.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................... 367
8.4.11 ELCR2—Slave Controller Edge/Level Triggered Register............................. 367
8.5 Advanced Interrupt Controller (APIC0) ............................................................... 368
8.5.1 APIC Register Map................................................................................ 368
8.5.2 IND—Index Register............................................................................. 369
8.5.3 DAT—Data Register.............................................................................. 369
8.5.4 Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register............................. 370
8.5.5 Offset FEC0 - EOIR: EOI Regist er ........................................................... 370
8.5.6 Offset 00h: ID—Identification Register .................................................... 371
8.5.7 Offset 01h: VER—Version Register.......................................................... 372
8.5.8 Offset 02h: ARBID—Arbitration ID Register............................. ................. 372
8.5.9 Offset 03h: BOOT_CONFIG—Boot Configuration Register ........................... 373
8.5.10 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table 373
8.6 Real Time Clock Registers........................................................ ......................... 375
8.6.1 I/O Register Address Map...................................................................... 375
8.6.2 Indexed Registers ................................................................................ 376
8.6.2.1 RTC_REGA—Register A............................................................ 377
8.6.2.2 RTC_REGB—Register B (General Configuration) .......................... 378
8.6.2.3 RTC_REGC—Register C (Flag Register) ...................................... 380
8.6.3 RTC_REGD Register D (Flag Register).................................................... 380
8.7 CPU Interface Registers.................................................................................... 381
8.7.1 NMI_SC—NMI Status and Control Re gister............................................... 381
8.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ................................... 382
8.7.3 PORT92—Fast A20 and Init Register ....................................................... 382
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
18 Order Number: 300641-004US
8.7.4 COPROC_ERR—Coprocessor Err or Register...............................................383
8.7.5 RST_CNT—Reset Control Register...........................................................383
8.8 Power Management Registers (D31:F0)....................................................... .......384
8.8.1 Power Management PCI Configuration Registers (D31:F0)..........................384
8.8.1.1 Offset A0h: GEN_PMCON_1— General PM Configuration 1 Register
(PM—D31:F0).........................................................................385
8.8.1.2 Offset A2h: GEN_PMCON_2— General PM Configuration 2 Register
(PM—D31:F0).........................................................................386
8.8.1.3 Offset A4h: GEN_PMCON_3— General PM Configuration 3
Register (PM—D31:F0)........ .....................................................387
8.8.1.4 Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0)....388
8.8.1.5 Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register
(PM—D31:F0).........................................................................389
8.8.1.6 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register
(PM—D31:F0).........................................................................390
8.8.1.7 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7]
Trap Range Register for Devices 4-7 (PMD31:F 0)......................390
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
for Devices 4-7 (PM—D31:F0)...................................................391
8.8.2 APM I/O Decode .................................................................... ...............392
8.8.2.1 APM_CNT—Advanced Power Management Control Port Register.....392
8.8.2.2 APM_STS—Advanced Power Management Status Port Register ......392
8.8.3 Power Management I/O Registers ...........................................................393
8.8.3.1 PM1_STS—Power Management 1 Status R egister.........................394
8.8.3.2 PM1_EN—Power Management 1 Enable Register................... .......396
8.8.3.3 PM1_CNT—Power Management 1 Control....................................397
8.8.3.4 PM1_TMR—Power Management 1 Timer Register.........................398
8.8.3.5 PROC_CNT—Proce ssor Control Register......................................398
8.8.3.6 LV2—Le vel 2 Register ..............................................................400
8.8.3.7 GPE0_STS—General Purpose Event 0 Status Register...................400
8.8.3.8 GPE0_EN—General Purpose Event 0 Enables Register.................. .404
8.8.3.9 SMI_EN—SMI Control and Enable Register..................................405
8.8.3.10 SMI_STS—SMI Status Register..................................................407
8.8.3.11 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register...................410
8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register..................411
8.8.3.13 MON_SMI—Device Monitor SMI Status and Enable Register...........411
8.8.3.14 DEVACT_STS—Device Activity Status Register.............................412
8.8.3.15 DEVTRAP_EN— Device Trap Enable Register ...............................414
8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker......................... .........415
8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker........................................415
8.9 System Management TCO Registers (D31:F0)....... ...............................................416
8.9.1 TCO Register I/O Map............................................................................416
8.9.2 TCO1_RLD—TCO Timer Reload and Current Value.....................................417
8.9.3 TCO1_TMR—TCO Timer Initial Value........................................................417
8.9.4 TCO1_DAT_IN—TCO Data In Register......................................................418
8.9.5 TCO1_DAT_OUT—TCO Data Out Register.................................................418
8.9.6 TCO1_STS—TCO1 Status Register...........................................................419
8.9.7 TCO2_STS—TCO2 Status Register...........................................................421
8.9.8 TCO1_CNT—TCO1 Control Register .........................................................422
8.9.9 TCO2_CNT—TCO2 Control Register .........................................................423
8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................423
8.9.11 Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Regist er ..............424
8.9.12 Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation Register...424
8.10 General Purpose I/O Registers (D31:F0) .............................................................425
8.10.1 GPIO Register I/O Address Map ............................................... ...............425
8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register ...........426
8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register....426
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 19
Contents—Intel® 6300ESB ICH
8.10.4 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register.. 427
8.10.5 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register............... 429
8.10.6 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register................. 430
8.10.7 Offset GPIOBASE + 30h: GPIO_USE_SEL 2—GPIO Use Select 2 Register........ 431
8.10.8 Offs et GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register432
8.10.9 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level fo r Input or Output 2 Register ...
432
9 IDE Controller Registers (D31:F1) ......................................................................... 435
9.1 PCI Configuration Registers (IDE—D31:F1)......................................................... 435
9.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) ..................... 436
9.1.2 Offset 02 - 03h: DIDDevice ID Register (LPC I/F—D31:F1)...................... 436
9.1.3 Offset 04h - 05h: CMD—Command Register (IDE—D31:F1) ....................... 437
9.1.4 Offset 06 - 07h: STS—Device Status Register (IDED31:F1)..................... 438
9.1.5 Offset 08h: RID—Revision ID Register (IDE—D31:F1) ............................... 439
9.1.6 Offset 09h: PI—Programming Interface (IDE—D31:F1).............................. 439
9.1.7 Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1) ..................................... 440
9.1.8 Offset 0Bh: BCC—Base Class Code (IDE—D31:F1).................................... 441
9.1.9 Offset 0Dh: MLT—Master Latency Timer (IDED31:F1)............................. 441
9.1.10 Offset 10h - 13h: PCMD_BAR—Primary Command Block
Base Address Register (IDE— D31:F1)..................................................... 441
9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
Address Regi ster (IDE—D31:F1) ............................................................. 442
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
Base Address Register (IDE D31:F1)....................................................... 442
9.1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block
Base Address Register (IDE D31:F1)....................................................... 443
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1)..
443
9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting Base Address................... 444
9.1.16 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID
(IDE—D31:F1)..................................................................................... 445
9.1.17 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1)......................... 446
9.1.18 Offset 3Ch: INTR_LN—Interrupt Line Register
(IDE—D31:F1)..................................................................................... 446
9.1.19 Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)...................... 447
9.1.20 IDE_TIM—IDE Timing Register (IDE—D31:F1).......................................... 447
9.1.21 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1) ...
451
9.1.22 Of fset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1). 452
9.1.23 Offset 4A - 4Bh: SDMA_TIMSynchronous DMA Timing Register (IDE—D31:F1).
453
9.1.24 IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)..................................................................................... 455
9.2 Bus Master IDE I/O Registers (D31:F1).............................................................. 455
9.2.1 BMIC[P,S]—Bus Master IDE Command Register........................................ 456
9.2.2 BMIS[P,S]—Bus Master IDE Status Register............................................. 457
9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register .................... 459
10 USB UHCI Controllers Registers............................................................................. 461
10.1 PCI Configuration Registers (D29:F0/F1)............................................................ 461
10.1.1 Offset 00 - 01h: VID—Vendor Identification Register
(USBD29:F0/F1)................................................................................ 462
10.1.2 Offset 02 - 03h: DID—Device Identification Register
(USBD29:F0/F1)................................................................................ 462
10.1.3 Offset 04 - 05h: CMD—Command Register
(USBD29:F0/F1)................................................................................ 463
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
20 Order Number: 300641-004US
10.1.4 Offset 06 - 07h: STA—Device Status Register
(USB—D29:F0/F1)................................................................................464
10.1.5 Offset 08h: RID—Re vision Identification Register
(USB—D29:F0/F1)................................................................................464
10.1.6 Offset 09h: PI—Programming Interface (USB—D29:F0/F1).........................465
10.1.7 Offset 0Ah: SCC—Sub Class Code Register
(USB—D29:F0/F1)................................................................................465
10.1.8 Offset 0Bh: BCC—Base Class Code Register
(USB—D29:F0/F1)................................................................................465
10.1.9 Offset 0Dh: MLT—Master Latency Timer...................................................465
10.1.10Offset 0Eh: HTYPE—Header Type Register
(USB—D29:F0/F1)................................................................................466
10.1.11Offset 20 - 23h: BASE—Base Address Register
(USB—D29:F0/F1)................................................................................467
10.1.12Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(USB—D29:F0/F1)................................................................................467
10.1.13Offset 2Eh-2Fh: SID—Subsystem ID (USB—D29:F0/F1).............................468
10.1.14Offset 3Ch: INTR_LN—Interrupt Line Register
(USB—D29:F0/F1)................................................................................468
10.1.15Offset 3Dh: INTR_PN—Interrupt Pin Register
(USB—D29:F0/F1)................................................................................469
10.1.16Offset 60h: USB_RELNUM—USB Release Number Register
(USB—D29:F0/F1)................................................................................469
10.1.17Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/
Mouse Control Register (USB—D29:F0/F1)...............................................469
10.1.18Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/F1)......472
10.2 USB I/O Registers............................................................................................473
10.2.1 Offset 00 - 01h: USBCMD—USB Command Register ..................................473
10.2.2 Offset 02 - 03h: USBSTA—USB Status Register.........................................478
10.2.3 Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register...................479
10.2.4 Offset Base + (06 - 07h): FRNUM—Frame Number Register........................481
10.2.5 Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address ...............481
10.2.6 Offset Base + OCh: SOFMOD—Start of Frame Modify Register ........... .........482
10.2.7 PORTSC[0,1]—Port Status and Control Regist er........................................483
11 USB EH CI Con troller Register s
(D29:F7)485
11.1 USB EHCI Configuration Registers (D29:F7) ........................................................485
11.1.1 Offset 04 - 05h: Command Register........................................................486
11.1.2 Offset 06 - 07h: Device Status ...............................................................487
11.1.3 Offset 08h: RID—Revision ID Register.....................................................489
11.1.4 Offset 09h: Programming Interface.........................................................489
11.1.5 Offset 0Ah: Sub Class Code....................................................................489
11.1.6 Offset 0Bh: Base Class Code ................... ...............................................490
11.1.7 Offset 0Dh: Master Latency Timer................. ..........................................490
11.1.8 Offset 10 - 13h: Memory Base Address....................................................490
11.1.9 Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID.....................................491
11.1.10Offset 2E - 2Fh: SID—USB EHCI Subsystem ID.........................................491
11.1.11Offset 34h: Capabilities Pointer...............................................................491
11.1.12Offset 3Ch: Interrupt Line.......................................................... ............492
11.1.13Offset 3Dh: Interrupt Pin.......................................................................492
11.1.14Offset 50h: PCI Power Management Capability ID .....................................492
11.1.15Offset 51h: Next Item Pointer #1.................. ..........................................493
11.1.16Offset 52 - 53h: Power Management Capabilities ......................................493
11.1.17Offset 54 - 55h: Power Management Control/Status...... ............................494
11.1.18Offset 58h: Debug Port Capability ID.......................................................495
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Contents—Intel® 6300ESB ICH
11.1.19Offset 59h: Next Item Pointer #2........................................................... 496
11.1.20Offset 5Ah - 5Bh: Debug Port Base Offset................................................ 496
11.1.21Offset 60h: Serial Bus Release Number ................................................... 496
11.1.22Offset 61h: Frame Length Adjustment..................................................... 496
11 .1.23Offset 62 - 63h: Port Wake Capability .... ................................................. 497
11.1.24Offset 64 - 65h: Classic USB Override ..................................................... 498
11.1.25Offset 68 - 6Bh: USB EHCI Legacy Support Extended Capability ................. 499
11 .1.26Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status........... 500
11.1.27Offset 70 - 73h: Intel Specific USB EHCI SMI ........................................... 501
11.1.28Offset 80h: Access Control .................................................................... 503
11.1.29HS_ Ref_V_USB HS Reference Voltage Register........................................ 503
11.2 Memory-Mapped I/O Registe rs.......................................................................... 503
11.2.1 Host Controller Capability Registers ........................................................ 504
11.2.1.1 Offset 00h: CAPLENGTH—Capability Registers Length .................. 504
11.2.1.2 Offset 02 - 03h: HCIVERSION—Hos t Controller Interface Version
Number505
11.2.1.3 Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters ..
505
11.2.1.4 Offset 08 - 0Bh: HCCPARAMS—Host Controller Capability Parameters ..
507
11.2.2 Host Controller Operational Registers...................................................... 508
11.2.2.1 Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB
EHCI Command Register.......................................................... 509
11.2.2.2 Offset CAPLENGTH + 04 - 07h: USB EHCI STSUSB EHCI Status . 512
11.2.2.3 Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR— USB
EHCI Interrupt Enable ............................................................. 514
11.2.2.4 Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index............... 514
11.2.2.5 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data
Structure Segment Register ..................................................... 515
11.2.2.6 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
List Base Address........................ ............................................ 516
11.2.2.7 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
Asynchronous List Address.............................................. ......... 516
11.2.2.8 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register.
517
11.2.2.9 PORTSC- Port N Status and Control........................................... 517
11.2.3 USB 2.0-Based Debug Port Register........................................................ 522
11.2.3.1 Offset 00h: Control/Status Register........................................... 522
11.2.3.2 Offset 04h: USB PIDs Re gister.................................................. 525
11.2.3.3 Offset 08h: Data Buffer Bytes 7:0............................................. 525
11.2.3.4 Offset 10h: Config Register ...................................................... 526
12 SMBUS Co ntroller Regist ers
(D31:F3)527
12.1 PCI Configuration Registers (SMBUS—D31:F3).................................................... 527
12.1.1 Offset 00 - 01h: VID—Vendor Identification Register (SMBUS—D31:F3)....... 527
12.1.2 Offset 02 - 03h: DID—Device Identification Register (SMBUS—D31:F3)....... 528
12.1.3 Offset 04 - 05h: CMD—Command Register
(SMBUS—D31:F3)................................................................................ 528
12.1.4 Offset 06 - 07h: STA—Device Status Register
(SMBUS—D31:F3)................................................................................ 529
12.1.5 Offset 08h: RID—Revision ID Register (SMBUS—D31:F3) .......................... 529
12 .1.6 Offset 09h: PI—Programming Interface (SMBUS—D31:F3)......................... 530
12.1.7 Offset 0Ah: SCCSub Class Code Register
(SMBUS—D31:F3)................................................................................ 530
12.1.8 Offset 0Bh: BCC—Base Class Code Regist er
(SMBUS—D31:F3)................................................................................ 530
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
22 Order Number: 300641-004US
12.1.9 Offset 20 - 23h: SMB_BASE—SMBUS Base Address
Register (SMBUS—D31:F3)........................................................ ............531
12.1.10Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(SMBUS—D31:F2/F4)............................................................................531
12.1.11Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/F4).......................532
12.1.12Offset 3Ch: INTR_LN—Interrupt Line Register
(SMBUS—D31:F3) ................................................................................532
12.1.13Offset 3Dh: INTR_PN—Interrupt Pin Register
(SMBUS—D31:F3) ................................................................................532
12.1.14Offset 40h: HOSTC—Host Configuration Register
(SMBUS—D31:F3) ................................................................................533
12.2 SMBUS I/O Registers........................................................................................533
12.2.1 Offset 00h: HST_STS—Host Status Register.............................................534
12.2.2 Offset 02h: HST_CNT—Host Control Register............................................537
12.2.3 Offset 03h: HST_CMD—Host Command Register.......................................539
12.2.4 Offset 04h: XMIT_SLVA—Transmit Slave Address Register .........................539
12.2.5 Offset 05h: HST_D0—Data 0 Register......................................................540
12.2.6 Offset 06h: HST_D1—Data 1 Register......................................................540
12.2.7 Offset 07h: Host_BLOCK_DB—Host Block Data Byte Register......................541
12.2.8 Offset 08h: PEC—Packet Error Check Register ..........................................542
12.2.9 Offset 09h: RCV_SLVA—Receive Slave Address Register ............................542
12.2.10Offset 0Ah: SLV_DATA—Receive Slave Data Register.................................543
12.2.11Offset 0Ch: AUX_STS—Auxiliary Status Register.......................................543
12.2.12Offset 0Dh: AUX_CTL—Auxiliary Control Register......................................544
12.2.13Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control Register........................544
12.2.14Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register.........................545
12.2.15Offset 10h: SLV_STS—Slave Status Register ............................................545
12.2.16Offset 11H: SLV_CMD—Slave Command Register......................................546
12.2.17Offset 14h: NOTIFY_DADDR—Notify Device Address..................................547
12.2.18Offset 16h: NOTIFY_DLOW—Notify Data Low Byte Register ........................548
12.2.19Offset 17h: NOTIFY_DHIGH—Notify Data High Byte Register ......................548
13 AC ’97 Audi o Cont roll er Reg is t ers (D31 : F 5) ............................................................549
13.1 AC’97 Audio PCI Configuration Space (D31:F5)....................................................549
13.1.1 Offset 00 - 01h: VID—Vendor Identification Register (Audio—D31:F5).........551
13.1.2 Offset 02 - 03h: DID—Device Id entification Register (Audio—D31:F5)..........551
13.1.3 Offset 04 - 05h: PCICMD—PCI Command Register
(Audio—D31:F5)...................................................................................552
13.1.4 Offset 06 - 07h: PCISTS—PCI Device Status Register (Audio—D31:F5) ........552
13.1.5 Offset 08h: RID—Re vision Identification Register
(Audio—D31:F5)...................................................................................554
13.1.6 Offset 09h: PI—Programming Interface Register
(Audio—D31:F5)...................................................................................554
13.1.7 Offset 0Ah: SCC—Sub Class Code Register
(Audio—D31:F5)...................................................................................554
13.1.8 Offset 0Bh: BCC—Base Class Code Register
(Audio—D31:F5)...................................................................................555
13.1.9 Offset 0Eh: HEDT—Header Type Register (Audio—D31:F5).........................555
13.1.10Offset 10 - 13h: NAMBAR—Native Audio
Mixer Base Address Register (Audio—D31:F5) ..........................................555
13.1.11Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering
Base Address Register (Audio—D31:F5)...................................................556
13.1.12Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—D31:F5)......557
13.1.13Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register (Audio—D31:F5)....
558
13.1.14Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio—D31:F5) .....559
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Contents—Intel® 6300ESB ICH
13.1.15Offset 2E - 2Fh: SID—Subsystem ID Register
(Audio—D31:F5) .................................................................................. 559
13.1.16Offset 34h: CAP_PTR—Capabilities Pointer
(Audio—D31:F5) .................................................................................. 560
13.1.17Offset 3Ch: INTR_LN—Interrupt Line Register
(Audio—D31:F5) .................................................................................. 560
13.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register
(Audio—D31:F5) .................................................................................. 561
13.1.19Offset 40h: PCID—Programmable Codec ID Register
(Audio—D31:F5) .................................................................................. 561
13.1.20Offset 41h: CFG—Configuration Register (Audio—D31:F5) ......................... 562
13.1.21Offset 50h: PID—PCI Power Management Capability ID Register (Audio—D31:F5)
562
13.1.22Offset 52h: PC—Power Management Capabilities Register (Audio—D31:F5).. 563
13.1.23Offset 54h: PCS—Power Management Control and Status Register (Audio—
D31:F5)563
13.2 AC’97 Audio I/O Space (D31:F5) ....................................................................... 564
13.2.1 x_BDBAR—Buffer Descriptor Base Address Register .................................. 568
13.2.2 x_CIV Current Index Value Register...................................................... 568
13.2.3 x_LVI—Last Valid Index Register............................................................ 569
13.2.4 x_SR—Status Register .......................................................................... 569
13.2.5 x_PICB—Position In Current Buffer Register............................................. 571
13.2.6 x_PIV—Prefetched Index Value Register.................................................. 571
13.2.7 x_CR—Control Register......................................................................... 572
13.2.8 GLOB_CNT—Global Control Register........................................................ 572
13.2.9 GLOB_STA—Global Status Register......................................................... 574
13.2.10CASCodec Access Semaphore Register ................................................. 578
13.2.11SDM—SDATA_IN Map Register............................................................... 578
14 AC’97 Modem Controller Registers (D31:F6).......................................................... 581
14.1 AC’97 Modem PCI Configuration Space (D31:F6)................................................. 581
14.1.1 Offset 00 - 01h: VID—Vendor Identification Register (Modem—D31:F6) ...... 582
14.1.2 Offset 02 - 03h: DID—Device Identification Register (Modem—D31:F6)....... 582
14.1.3 Offset 04 - 05h: PCICMD—PCI Command Register (Modem—D31:F6).......... 583
14.1.4 Offset 06 - 07h: PCISTA—Device Status Register
(Modem—D31:F6)................................................................................ 584
14.1.5 Offset 08h: RID—Revision Identification Register
(Modem—D31:F6)................................................................................ 585
14.1.6 Offset 09h: PI—Programming Interface Register
(Modem—D31:F6)................................................................................ 585
14.1.7 Offset 0Ah: SCCSub Class Code Register
(Modem—D31:F6)................................................................................ 585
14.1.8 Offset 0Bh: BCC—Base Class Code Regist er
(Modem—D31:F6)................................................................................ 586
14.1.9 Offset 0Eh: HEDT—Header Type Register (Modem—D31:F6)...................... 586
14.1. 10Offse t 1 0 - 13h : MMB AR—Modem Mixer Ba se Addres s Reg ister (Mo dem—D31:F6)
586
14.1.11Offset 14 - 17h: MBAR—Modem Base Address Register (Modem—D31:F6)... 587
14.1.12Offset 2C - 2Dh: SVID—Subsystem Vendor ID
(Modem—D31:F6)................................................................................ 588
14 .1.13Offset 2E - 2Fh: SID—Subsystem ID (Modem—D31:F6) ............................ 588
14.1.14Offset 34h: CAP_PTR—Capabilities Pointer
(Modem—D31:F6)................................................................................ 589
14.1.15Offset 3Ch: INTR_LN—Interrupt Line Register
(Modem—D31:F6)................................................................................ 589
14 .1.16Offset 3Dh: INT_PIN—Interrupt Pin (Modem—D31:F6).............................. 590
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
24 Order Number: 300641-004US
14.1.17Offset 50h: PID—PCI Power Management Capability ID Register (Modem—
D31:F6)590
14.1.18Offset 52h: PC—Power Management Capabilities Register (Modem—D31:F6) 591
14.1.19Offset 54h: PCS—Power Management Control and Status Register (Modem
D31:F6)591
14.2 AC’97 Modem I/O Space (D31:F6) ........................... ..........................................593
14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register.............................595
14.2.2 x_CIV—Current Index Value Register ......................................................595
14.2.3 x_LVI—Last Valid Index Register.............................................................596
14.2.4 x_SR—Status Register ...........................................................................596
14.2.5 x_PICB—Position in Current Buffer Register..............................................597
14.2.6 x_PIV—Prefetch Index Value Register. .....................................................599
14.2.7 x_CR—Control Register..........................................................................599
14.2.8 GLOB_CNT—Global Control Register........................................................600
14.2.9 GLOB_STA—Global Status Register ................................................ .........601
14.2.10CAS—Co dec Access Semaphore Register..................................................604
15 M u ltimedia Timer Registers ...................................................................................605
15.1 Memory Mapped Registers ................................................................................605
15.1.1 Behavioral Rules...................................................................................605
15.1.2 Offset 000-007h: General Capabilities and ID Register...............................606
15.1.3 Offset 010-017h: General Config Register................................................607
15.1.4 Offset 020-027h: General Interrupt Status Register...................................608
15.1.5 Offset 0F0 - 0f7h: Main Counter Value.....................................................609
15.1.6 Timer n Config and Capabilities...............................................................609
15.1.7 Timer n Comparator Value.....................................................................613
16 Watc hdog Ti mer (WD T) (D29:F4) ..........................................................................615
16.1 Product Features ........................................... ..................................................615
16.2 Product Overview .................................................................. ..........................616
16.3 Signal Descriptions .......... ................................................................................617
16.4 Device 29: Function 4 Configuration Registers.....................................................617
16.4.1 Config uration Registers .........................................................................617
16.4.2 Memory Mapped Registers ...................... ...............................................618
16.4.3 Offset 00h: VID—Vendor Identification Register........................................618
16.4.4 Offset 02h: DID—Device Identification Register ........................................619
16.4.5 Offset 04 - 05h: COM—Command Register...............................................619
16.4.6 Offset 06h - 07h: DS—Device Status Register...........................................620
16.4.7 Offset 08h: RID—Revision Identification Register ......................................621
16.4.8 Offset 09h: PI—Programming Interface Register................... ....................622
16.4.9 Offset 0Ah: SCC—Sub Class Code Register...............................................622
16.4.10Offset 0Bh: BCC—Base Code Class Re gister..............................................622
16.4.11Offset 0Eh: HEDT—Header Type Register.................................................622
16.4.12 O ffset 10h: BAR—Base Address Register..................................................623
16.4.13 O ffset 2Dh - 2Ch: SVID—Subsystem Vendor ID........................................623
16.4.14Offset 2Eh - 2Fh: SID—Subsystem ID............ ..........................................624
16.4.15Offset 60 - 61h: WDT Configuration Register............................................625
16.4.16Offset 68h: WDT Lock Register...............................................................625
16.4.17Offset F8 - FBh: Manufacturer’s ID..........................................................627
16.4.18Offset Base + 00h: Preload Value 1 Register ............................................627
16.4.19Offset Base + 04h: Preload Value 2 Register ............................................628
16.4.20Offset Base + 08h: General Interrupt Status Register................................628
16.4.21Offset Base + 0Ch: Reload Register.........................................................629
16.5 Theory Of Operation.........................................................................................629
16.5.1 RTC Well and WDT_TOUT# Functionality..................................................629
16.5.2 Register Unlocking Sequence..................................................................629
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Contents—Intel® 6300ESB ICH
16.5.3 Reload Sequence.................................................................................. 630
16.5.4 Low Power State .................................................................................. 630
17 APIC1 Configuration Registers
(D29:F5)631
17.1 APIC 1 Configuration Registers (D29:F5)............................................................. 631
17.1.1 Offset 00 - 03h: VID_DID—Vendor/ID Register
(APIC1—D29:F5).................................................................................. 632
17.1.2 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—D29:F5) ... 632
17.1.3 Offset 06 - 07h: APIC1STA—APIC1 Devi ce Status
(APIC1—D29:F5).................................................................................. 633
17 .1.4 Offset 08h: RID—Revision ID Register (APIC1—D29:F5)............................ 634
17 .1.5 Offset 09 - 0Bh: CC—Class Co de Register (APIC1—D29:F5) ....................... 634
17.1.6 Offset 0C - 0Fh: HEADTYP—Header Type Register
(APIC1—D29:F5).................................................................................. 635
17.1.7 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers
(APIC1—D29:F5).................................................................................. 635
17.1.8 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer
(APIC1—D29:F5).................................................................................. 636
17.1.9 Offset 3Ch: ILINE—Interrupt Line (APIC1—D 29:F5) .................................. 636
17 .1.10Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5) ..................................... 636
17.1.11Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register (APIC1—D29:F5)
637
17.1.12Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—D29:F5) ...... 637
17.1.13Offset 50 - 51h: XID—PCI-X Identifiers Register
(APIC1—D29:F5).................................................................................. 639
17.1.14Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5) ......................... 639
17.2 Advanced Interrupt Controller (APIC)................................................................. 640
17.2.1 APIC1 Direct Register Map..................................................................... 640
17.2.2 IND—Index Register ....................................................................... ...... 640
17.2.3 DAT—Data Register.............................................................................. 641
17.2.4 IRQPAIRQ Pin Assertion Register ......................................................... 641
17.2.5 EOIR—EOI Register .............................................................................. 642
17.2.6 Offset 00h: ID—Identification Register .................................................... 643
17.2.7 Offset 01h: VER—Version Register.......................................................... 643
17.2.8 Offset 03h: BOOT_CONFIG—Boot Configuration Register ........................... 644
17.2.9 Redirection Table ................................................................................. 644
18 PCI-X Overview (D28:F0) ...................................................................................... 647
18.1 I/O Window Addressing.................................................................................... 647
18.2 Memory Window Addressing ............................................................................. 648
18.2.1 Memory Base and Limit Address Registers ............................................... 648
18.2.2 Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit Registers..
648
18.3 VGA Addressing .............................................................................................. 649
18.4 Configuration Addressing.................................................... .............................. 650
18.4.1 Type 0 Accesses to the Intel® 6300ESB ICH ............................................ 650
18.4.2 Type 1 to Type 0 Transl ation .................................................................. 650
18.4.3 Type 1 to Type 1 Forwarding ................................................................. 651
18 .4.4 Type 1 to Special Cycle Forwarding......................................................... 651
18.5 Transaction Ordering ................................ ........................... ............................ 652
18.5.1 Comparison of Rules vs. a PCI – PCI Bridge ............................................. 652
18.5.2 Other Notes..................................................... .................................... 652
18.6 Device 28 – Hub Interface to PCI-X Bridge.......................................................... 653
18.6.1 Configuration Space Registers................................................................ 653
18.6.1.1 Register Summary.................................................................. 653
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
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26 Order Number: 300641-004US
18.6.1.2 Offset 00: ID—Identifiers .........................................................654
18.6.1.3 Offset 04: CMD—Command ......................................................655
18.6.1.4 Offset 06: PSTS—Primary Status...............................................656
18.6.1.5 Offset 08: RID—Revision ID......................................................658
18.6.1.6 Offset 09: CC—Class Code........................................................659
18.6.1.7 Offset 0C: CLS—Cache Line Size ...............................................659
18.6.1.8 Offset 0D: PLT—Primary Latency Timer ......................................660
18.6.1.9 Offset 0E: HTYPE—Header Type ................................................660
18.6.1.10Offset 18: BNUM—Bus Numbers................................................661
18.6.1.11Offset 1B: SLT—Secondary Latency Timer ..................................661
18.6.1.12Offset 1C: IOBL—I/O Base and Limit..........................................662
18.6.1.13Offset 1E: SSTS—Secondary Status...........................................663
18.6.1.14Offset 20: MBL—Memory Ba se and Limit ....................................664
18.6.1.15Offset 24: PMBL—Prefetchable Memory Base and Limit.................665
18.6.1.16Offset 28: PMBU32—Prefetchable Memory Base Upper 32 Bits.......665
18.6.1.17Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits.......666
18.6.1.18Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits.................666
18.6.1.19Offset 34: CAPP—Capabiliti es List Pointe r ...................................667
18.6.1.20Offset 3C: INTR—Interrupt Information......................................667
18.6.1.21Offset 3E: BCTRL—Bridge Control..............................................667
18.6.1.22Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration.671
18.6.1.23Offset 42: MTT—Multi-Transaction Timer............. .......................673
18.6.1.24Offset 44: STRP—PCI Strap Status ............................................674
18.6.1.25Offset 50: PX_CAPID—PCI-X Capabilities Identifier ......................674
18.6.1.26Offset 51: PX_NXTP—Next Item Pointer .....................................674
18.6.1.27Offset 52: PX_SSTS—PCI-X Secondary Status.............................675
18.6.1.28Offset 54: PX_BSTS - PCI- X Bridge Status..................................676
18.6.1.29Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control ....678
18.6.1.30Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control 678
18.6.1.31Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration....680
18.6.1.32Offset E4: PCR - PCI Compensation Register...............................681
18.6.1.33Offset F0: HCCR - Hub Interface Command/Control Register.........682
18.6.1.34Offset F8h – Offset FFh: Prefetch Control Registers......................682
18.6.1.35Offset F8h: PC33 - Prefetch Control – 33 MHz .............................683
18.6.1.36Offset FAh: PC66 - Prefetch Control – 66 MHz .............................683
18.7 PCI Mode in the PCI-X Interface.........................................................................684
18.7.1 Summary of Changes............................................................................684
18.7.2 Transaction Types.................................................................................684
18.7.3 Detection of 64-Bit Environment.............................................................685
18.7.4 Data Bus.............................................................................................685
18.7.5 Write Transactions................................................................................685
18.7.5.1 Posted ...................................................................................685
18.7.5.2 Non-Posted ............................................................................686
18.7.5.3 Fast Back-to-Back ...................................................................686
18.7.6 Read Transactions ....................................................................... .........686
18.7.6.1 Prefetchable ...........................................................................686
18.7.6.2 Delayed .................................................................................686
18.7.7 Transaction Termination ........................................................................686
18.7.7.1 Normal Master Termination.......................................................686
18.7.7.2 Master Ab ort Termination.........................................................686
18.7.7.3 Target Termination Received by the Intel® 6300ESB ICH..............687
18.7.7.4 Target Termination Initiated by the Intel® 6300ESB ICH ..............687
18.7.8 LOCK Cycles ........................................................................................687
18.7.9 Error Handling......................................................................................687
18.7.9.1 Data Parity Errors....................................................................689
18.7.9.2 System Errors.........................................................................690
18.8 PCI-X Interface ...............................................................................................691
18.8.1 Command Encoding ............................... ...............................................691
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18.8.2 Attributes............................................................................................ 691
18.8.3 Special Notes for Burst Transactions ....................................................... 692
18.8.4 Device Select Timing ............................................................................ 692
18.8.5 Wait States ......................................................................................... 692
18.8.6 Split Transactions................................................................................. 693
18.8.6.1 Completer Attributes............................................................... 693
18.8.6.2 Requirements for Accepting Split Completions ............................ 693
18.8.6.3 Split Completion Messa ges....................................................... 693
18.8.6.4 Arbitration Among Multiple Split Completions.............................. 693
18.8.7 Transaction Termination as a PCI-X Target .............................................. 694
18.8.7.1 Retry .................................................................................... 694
18.8.7.2 Split Resp onse........................................................................ 694
18.8.7.3 Master-Abort.......................................................................... 694
18.8.8 Arbitration........................................................................................... 694
18.8.9 Bridge Buffer Requirements................................................................... 694
18.8.10Locked Transactions ...................... ........................... ............................ 694
18.8.11Error Support ...................................................................................... 695
18.8.11.1General ................................................................................. 695
18.8.11.2Special Parity Error Rule for Split Response ................................ 695
18.9 Transaction Termination Translation between Interfaces....................................... 695
18.9.1 Behavior of Hub Interface Initiated Cycles to PCI/PCI-X
Receiving Imme diate Terminations ......................................................... 695
18.9.2 Behavior of Hub Interface Initiated Cycles to PCI-X Receiving Split Terminations.
696
18.9.3 Hub Interface Action on Immediate Responses to P CI-X Split Completions ... 697
18.9.4 Behavior of PCI/PCI-X Initiated Cycles to Hub Interface............................. 698
18.10 Delayed/Split Transactions ............................................................................... 698
18.10.1Number Supported............................................................................... 698
18.10.2Prefetch Algorithm................................................................................ 699
18.10.2.1Parameters............................................................................ 699
18.10.2.2Algorithm (Single Device Only)................................................. 699
18.10.3Algorithm (Multiple PCI-X Devices Requesting)......................................... 700
18.10.4Accesses From Multiple Agents to Same 4K Page...................................... 700
18.11 Internal Bus/Device Communication .................................................................. 700
18 .12 Data Return Behavior of Hub Interface Initiated Reads......................................... 701
18.13 Performance Targets........................................................................................ 701
18.13.1Introduction ........................................................................................ 701
18.13.2Definitions and Assumptions.................................................................. 701
18.13.3Active Master Clock Counts.................................................................... 702
19 Serial I/O Unit ....................................................................................................... 703
19.1 Features ........................................................................................................ 703
19.2 Pin Description................................................................................................ 704
19.2.1 Universal Asynchronous Receive And Transmit (UART0, UART1) ................. 704
19.3 Functional Description...................................................................................... 706
19.3.1 Host Processor Interface (LPC).............. ........................... ...................... 706
19.4 LPC Interface.................................................................................................. 706
19.4.1 LPC Cycl es .......................................................................................... 706
19.4.1.1 I/O Read an d Write Cycles ....................................................... 706
19.4.2 Reset Policy.......................... ............................................................... 707
19.4.3 LPC Transfers ...................................................................................... 707
19.4.3.1 I/O Transfers ......................................................................... 707
19.5 Logical Device 4 and 5: Serial Ports (UARTs)....................................................... 707
19.5.1 Overview ............................................................................................ 707
19.5.1.1 UART Feature List ................................................................... 708
19.5.1.2 UART Operational Description................................................... 709
Intel® 6300ESB ICH—Contents
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19.5.1.3 Internal Register Descriptions ...................................................710
19.5.1.4 FIFO Operation .......................................................................723
19.6 Logical Device 7 (07H): Port 60/64 Emulation......................................................724
19.6.1 Feature List ............ ........................... ........................... .......................724
19.6.2 Overview.............................................................................................724
19.6.2.1 Port 60H Emulation (SCR60).....................................................725
19.6.2.2 Port 64H Emulation (SCR64).....................................................725
19.7 Serial IRQ.......................................................................................................725
19.7.1 Timing Diagrams For SIU_SERIRQ Cycle ..................................................725
19.7.1.1 SIU_SERIRQ Cycle Control ........................................ ...............726
19.7.1.2 SIU_SERIRQ Data Frame..........................................................727
19.7.1.3 Stop Cycle Control...................................................................727
19.7.1.4 Latency..................................................................................728
19.7.1.5 EOI/ISR Read Latency..............................................................728
19.7.1.6 Reset and Initialization.............................................................728
19.8 Configuration ..................................................................................................728
19.8.1 Config uration Port Ad dress Se lection .......................................................728
19.8.2 Primary Configuration Ad dress De coder ...................................................728
19.8.2.1 Entering the Configuration State ...............................................729
19.8.2.2 Exiting the Configuration State..................................................729
19.8.2.3 Configuration Sequence ...........................................................729
19.8.2.4 Configuration Mode .................................................................729
19.8.3 SIU Configuration Registers Summary.....................................................730
19.8.3.1 Global Control/Configuration Registers [00h — 2Fh].....................731
19.8.3.2 Logical Device Configuration Registers [30h — FFh] .....................731
20 S er ial ATA Controller Registers
(D31:F2)737
20.1 PCI Configuration Registers (SATA–D31:F2)........................................................737
20.1.1 Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2) ........................738
20.1.2 Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2).........................739
20.1.3 Offset 04h - 05h: CMD—Command Register (SATA–D31:F2).......................739
20.1.4 Offset 06 - 07h: STS—Device Status Register
(SATA–D31:F2)....................................................................................741
20.1.5 Offset 09h: PI—Programming Interface (SATA–D31:F2)............ .................742
20.1.6 Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2) ....................................742
20.1.7 Offset 0Bh: BCC—Base Class Code (SATA–D31:F2)....................... ............743
20.1.8 Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2)............................743
20.1.9 Offset 10h - 13h: PCMD_BAR—Primary Command Block
Base Address Register (SATA–D31:F2) ....... .............................................744
20.1.10Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
Address Register (SATA–D31:F2)............................................................744
20.1.11Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
Base Address Register (IDE D31:F1) .......................................................745
20.1.12Offset 14h - 17h: SCNL_BAR—Secondary Control Block
Base Address Register (IDE D31:F1) .......................................................745
20.1.13Offset 20h - 23h: BAR—Legacy Bus Master Base Address
Register (SATA–D31:F2)............................................ ............................746
20.1.14Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(SATA–D31:F2)....................................................................................746
20.1.15Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)...............................747
20.1.16Offset 34h: CAP—Capabilities Pointer Register
(SATA–D31:F2)....................................................................................747
20.1.17Offset 3Ch: INTR_LN—Interrupt Line Register
(SATA–D31:F2)....................................................................................747
20.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register
(SATA–D31:F2)....................................................................................748
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20.1.19Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register
(SATA–D31:F2).................................................................................... 748
20.1.20IDE_TIMS—Secondary IDE Timing Register (SATA–D31:F2)....................... 750
20.1.21Offset 44h: SIDETIM—Slave IDE Timing Register
(SATA–D31:F2).................................................................................... 750
20.1.22Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2)751
20.1.23Offset 4A - 4Bh: SDMA_TIMSynchronous DMA Timing Register (SATA–D31:F2)
752
20.1.24Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2)... 754
20.1.25Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–D31:F2) 755
20.1.26Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–D31:F2) ... 755
20.1.27Offset 74 - 75h: PMCS—PCI Power Management Control and Status (SATA–
D31:F2)756
20.1.28Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers (SATA–D31:F2)....
757
20.1.29Offset 82 - 83h: MC—Message Si gnaled Interrupt Message Control (SATA–
D31:F2)757
20.1.30Offset 84 - 87h: MA—Message Signaled Interrupt Message Address (SATA
D31:F2)758
20.1.31Offset 88 - 89h: MD—Message Signaled Interrupt Message Data (SATA–D31:F2)
759
20.1.32Offset 90h: MAP—Address Map (SATA–D31:F2)........................................ 759
20.1.33Offset 92h: PCS—Port St atus and Control (SATA–D31:F2) ......................... 760
20.1.34Offset A0h: SRI—SATA Registers Index (SATA–D31:F2) ............................ 760
20.1.35Offset A4h - A7h: SRD—SATA Registers Data
(SATA–D31:F2).................................................................................... 761
20.1.36STTT—SATA TX Termination Test Register A
(SATA–D31:F2).................................................................................... 762
20.1.37STOT — SATA TX Output Test Register (SATA–D31:F2).... ......................... 762
20.1.38Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–D31:F2) 763
20.1.39Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–D31:F2) 763
20.1.40Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–D31:F2).. 763
20.1.41Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)765
20.1.42Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)766
20.2 Bus Master IDE I/O Registers (D31:F2).............................................................. 766
20.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2).......................... 767
20.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................... 768
20.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)....... 769
21 Packag e Information ............................................................................................. 771
21.1 Ball Location................................................................................................... 771
22 Electrical Characteristics ....................................................................................... 789
22.1 Absolute Maximum Ratings............................................................................... 789
22.2 Functional Operatin g R ange.............................................................................. 789
22.3 DC Characteristics........................................................................................... 790
22.4 AC Characteristics ............................................................................. .............. 796
22.5 Timing Diagrams and Test Conditions................................................................. 813
22.5.1 PCI-X ................................................................................................. 813
22.5.2 System Clocks and General Timing ......................................................... 815
22.5.3 IDE and Ultra ATA Timing...................................................................... 817
22.5.4 USB.................................................................................................... 820
22.5.5 SMBus ................................................................................................ 821
22.5.6 Power and Reset ............................................................................... ... 822
22.5.7 AC’97 and Miscellaneous ....................................................................... 824
23 Testability ............................................................................................................. 825
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
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23.1 Test Mode Description......................................................................................825
23.2 Tri-State Mode ................................................................................................826
23.3 XOR Chain Mode..............................................................................................826
23.3.1 XOR Chain Testability Algorithm Example............................................. ....826
Index.....................................................................................................................835
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Contents—Intel® 6300ESB ICH
Figures
1 Workstation/PC Model.................................................................................................5
2 Low to Mid-Range Communication Appliance Model (Diskless)..........................................6
3 Value Server, Ultra-Dense Server and Low-End Server Blade .................................... .......7
4 Conceptual System Clock Diagram .............................................................................54
5 Power Plane Usage Model..........................................................................................80
6 Primary Device Status Register Error Reporting Logic............................................... .....93
7 Secondary Status Register Error Reporting Logic..........................................................94
8 NMI# Generation Logic........................................................................................... ..95
9 Typi cal Timing for LFRAME# .................................................................................... 101
10 Abort Mechanism ................................................................................................... 101
11 Intel® 6300ESB ICH DMA Controller......................................................................... 103
12 DMA Request Assertion Through LDRQ# ................................................................... 107
13 Port 60 Read Clearing IRQ1 AND IRQ12 Latch................................... ......................... 120
14 Coprocessor Error Timing Diagram .................................. ......................................... 142
15 Latching Processor I/F Signals with STOPCLK#........................................................... 154
16 Physical Region Descriptor Table Entry...................................................................... 182
17 SATA Power States.............................................................................. ................... 190
18 Transfer De scriptor ................................................................................................ 197
19 Example Queue Conditions..................................................... ................................. 205
20 USB Data Encoding ................................................................................................ 208
21 USB Legacy Keyboard Flow Diagram......................................................................... 219
22 Intel® 6300ESB ICH-USB Port Connections................................................................ 230
23 Intel® 6300ESB ICH Based AC’97 Controller Connection to Companion Codec(s) ............ 260
24 AC’97 2.2 Controller-Codec Connection ..................................................................... 261
25 AC-Link Protocol .............................................................................................. ...... 262
26 AC-Link Powerdown Timing ...................... ............................................ ................... 270
27 SDIN Wake Si gnali ng.............................................................................................. 271
28 Intel® 6300ESB ICH Device Diagram.................................................. ...................... 277
29 WDT Block Diagram ................................................................... ............................ 616
30 Intel® 6300ESB I/O Controller Hub Appearance to Software ........................................ 650
31 Type ‘1’ to Type ‘0’ Translation .......................................... ...................................... 651
32 SIU Block Diagram ................................................................................................ 704
33 Example UART Data Frame...................................................................................... 709
34 Start Frame Timing with Source Sampled a Low Pulse on IRQ1 .................................... 725
35 Stop Frame Timing with Host Using 17 SIU_SERIRQ Sampling Period............................ 726
36 Ball Diagram (Top View - Left Side).......................................................................... 771
37 Ball Diagram (Top View - Right Side)............................................................. ........... 772
38 Mechanical Drawing................................................................................................ 773
39 PCI-X 3.3V Clock ....................................................... ............................................ 813
40 Clock Uncertainty (PXPCLK[0:4]).............................................................................. 813
41 PCI-X Output Timing .............................................................................................. 814
42 PCI-X Input Timing ................................................................................................ 814
43 PCI-X RST# Timing for switching to PCI-X Mode Pull-ups............................................. 815
44 Clock Timing ......................................................................................................... 815
45 Valid Delay from Rising Clock Edge........................................................................... 816
46 Setup and Hold Times............................................................................................. 816
47 Float Delay................................................................ ............................................ 816
48 Pulse Width........................................................................................................... 816
49 Output Enable Delay........................................................... .................................... 817
50 IDE PIO Mode........................................................................................................ 817
51 IDE Multiword DMA ................................................................................................ 818
52 Ultra ATA Mode (Drive Initiating a Burst Read).................................................. ......... 818
53 Ultra ATA Mode (Sustained Burst) ............................................................................ 819
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
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32 Order Number: 300641-004US
54 Ultra ATA Mode (Pausing a DMA Burst)....................................................... ...............819
55 Ultra ATA Mode (Terminating a DMA Burst)................................................................820
56 USB Rise and Fall Times..........................................................................................820
57 USB Jitter..............................................................................................................821
58 USB EOP Width ......................................................................................................821
59 SMBus Transaction .................................................................................................821
60 SMBus Timeout.................................................... ........................... .......................822
61 Power Sequencing and Reset Signal Timings ..............................................................822
62 G3 (Mechanical Off) to S0 Timings............................................................................823
63 S0 to S1 to S0 Timing.............................................................................................823
64 S0 to S5 to S0 Timings............................................................................................824
65 AC’97 Data Input and Output Timings .......................................................................824
66 Test Mode Entry (XOR Chain Example)......................................................................826
67 Example XOR Chain Circuitry ........... ........................................................................826
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Contents—Intel® 6300ESB ICH
Tables
1 Industry Specifications..............................................................................................49
2Intel
® 6300ESB ICH Clock Domains...................................... ......................................53
3 Hub Interface Signals ...............................................................................................55
4 Firmware Hub Interface Signals .................................................................................56
5 PCI Interface Signals........................................................................................ ........57
6 PCI-X Interface Signals.................................... .........................................................60
7 SATA Interface Signals .............................................................................................64
8 IDE Interface Signals................................................................................................64
9 LPC Interface Signals.................................................. ..............................................66
10 Interrupt Signals ......................................................................................................66
11 USB Interface Signals...............................................................................................67
12 Power Management Interface Signals..........................................................................68
13 CPU Interface Signals ...............................................................................................69
14 SM Bus Interface Signals ..........................................................................................71
15 System Management Interface Signals........................................................................71
16 Real Time Clock Interface ..........................................................................................71
17 Other Clocks ...........................................................................................................72
18 Miscellaneous Signals .............. ........................... ......................................................72
19 AC’97 Link Signals.................................................................... ................................73
20 Universal Asynchro nous Receive and Transmit (UART0, 1).............................................73
21 General Purpose I/O Signals.......... ....................................................... .....................75
22 Power and Ground Signals........... ..............................................................................76
23 Functional Strap Definitions............................................................................ ...........77
24 Revision and Device ID Table.......................................... ...........................................78
25 Intel® 6300ESB I/O Controller Hub Power Planes .........................................................79
26 Integrated Pull-Up and Pull-Down Resistors .................................................................80
27 IDE Series Termination Resistors................................................................... .............81
28 Power Plane and States for Output and I/O Signal for Desktop Configurations ..................83
29 Po wer Plane for Input Signals for Desktop Configurations ..............................................90
30 Type 0 Configuration Cycle Device Number Translation .................................................96
31 LPC Cycle Types Supported ............................................................................ ...........98
32 Start Field Bit Definitions ..........................................................................................98
33 Cycle Type Bit Definitions..........................................................................................99
34 Transfer Size Bit De finition........................................................................................99
35 SYNC Bit Definition...................................................................................................99
36 Response to Sync Failures....................................................................................... 100
37 Fixed Priority......................................................................................................... 104
38 DMA Transfer Size.................................................................................................. 105
39 Address Shifting in 16-bit I/O DMA Transfers............................................................. 105
40 Counter Operating M odes........................................................................................ 111
41 Interrupt Controller Core Connections....................................................................... 113
42 Interrupt Status Registers....................................................................................... 114
43 Content of Interrupt Vector Byte.............................................................................. 115
44 Interrupt Mapping in Non-APIC ................................................................................ 123
45 APIC Interrupt Mapping, APIC0 Agent....................................................................... 124
46 APIC Interrupt Mapping, APIC1 Agent....................................................................... 125
47 Arbitration Cycles............................................... ........................... ......................... 126
48 APIC Message Formats ........................................................................................... 126
49 EOI Message .................................. ....................................................................... 127
50 Short Message....................................................................................................... 128
51 APIC Bus Status Cycle Definition............................... ............................................... 129
52 Lowest Priority Message (Without Focus Processor)..................................................... 130
53 Remote Read Message............................................................................................ 131
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54 Interrupt Message Address Format ............................ ...............................................134
55 Interrupt Message Data Format................................................................................135
56 Stop Frame Explanation .......... ................................................................................137
57 Data Frame Format.................................................................................................137
58 Configuration Bits Reset By RTCRST# Assertion..........................................................140
59 INIT# Going Active.................................................................................................141
60 NMI Sources..........................................................................................................143
61 DP Signal Differences..............................................................................................143
62 General Power States for Systems Using Intel® 6300ESB ICH ......................................146
63 State Transition Rul es for Intel® 6300ESB I/O Controller Hub...................... .................147
64 System Power Plane ...............................................................................................148
65 Causes of SCI ........................................................................................................149
66 Causes of SMI#......................................................................................................150
67 Causes of TCO SM I#...............................................................................................151
68 Break Events .........................................................................................................152
69 Sleep Types...........................................................................................................156
70 Causes of Wake Events ...........................................................................................156
71 Transitions Due to Power Failure...............................................................................158
72 Transitions Due to Power Button...............................................................................160
73 Transitions Due to RI# Signal ........ ........................... ...............................................161
74 Write Only Registers with Read Paths in ALT Access Mode............................................163
75 PIC Reserved Bits Return Values...............................................................................165
76 Register Write Accesses in ALT Access Mode...............................................................165
77 Intel® 6300ESB ICH Clock Inputs.............................................................................167
78 Event Transiti ons that Cause Messages......................................................................172
79 GPIO Implementation .............................................................................................176
80 IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)...........................180
81 IDE Transaction Timings (PCI Clocks)........... .............................................................181
82 Interrupt/Active Bit Interaction Definition ..................................................................185
83 UltraATA/33 Control Signal Redefinitions .................................... ...............................186
84 SATA MSI vs. PCI IRQ Actions................................ ..................................................192
85 Legacy Routing ......................................................................................................193
86 Frame List Pointer Bit Description .............................................................................196
87 TD Link Pointer ......................................................................................................197
88 TD Control and Status.............................................................................................198
89 TD Token ..............................................................................................................200
90 TD Buffer Pointer....................................................................................................201
91 Queue Head Block ..................................................................................................201
92 Queue Head Link Pointer .........................................................................................201
93 Queue Element Link Pointer.....................................................................................201
94 Command Register, Status Register and TD Status Bit Interaction.................................204
95 Queue Advance Crit eria........... ................................................................................206
96 USB Schedule List Traversal Decision Table................................................................207
97 PID Format............................................................................................................209
98 PID Types .............................................................................................................210
99 Address Field.........................................................................................................210
100 Endpoint Field........................................................................................................211
101 Token Format ........................................................................................................212
102 SOF Packet............................................................................................................212
103 Data Packet Format ................................................................................................212
104 Bits Maintained in Low Power States ................................................................ .........216
105 USB Legacy Keyboard/Mouse Control Register Bit Implementation ................................217
106 USB Legacy Keyboard State Transitions.....................................................................220
107 UHCI vs. EHCI ........................................................................... ............................221
108 EHC Resets......... ...................................................................................................223
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109 Read Policies for Periodic DMA ................................................................................. 224
110 Write Policies for Periodic DMA................................................................................. 225
111 Read Policies for Asynchronous DMA......................................................................... 226
112 Write Policies for Asynchronous DMA ........................................................................ 227
113 Effect of Resets on Port-Routing Log ic....................................................................... 232
114 USB Debug Port Behavior....................................................................... ................. 233
115 Quick Protocol ................................................... ........................... ......................... 239
116 Send/Receive Byte Protocol without PEC ................................................................... 239
117 Send/Receive Byte Protocol with PEC.... ........................................... ......................... 240
118 Write Byte/Word Protocol without PEC ...................................................................... 240
119 Write Byte/Word Protocol with PEC........................................................................... 240
120 Read Byte/Word Protocol without PEC....................................................................... 242
121 Read Byte/Word Protocol with PEC ........................................................................... 242
122 Process Call Protocol without PEC............................................................................. 243
123 Process Call Protocol with PEC ................................................................................. 243
124 Block Read/Write Protocol without PEC...................................................................... 245
125 Block Read/Write Protocol with PEC.......................................................................... 245
126 I2C Bl ock Read Protocol .......................................................................................... 246
127 Block Write-Block Read Process Call Protocol With/Without PEC.................................... 248
128 Enable for SMBALERT#........................................................................................... 250
129 Enables for SMBus Slave Write and SMBus Host Events............................................... 250
130 Enables for the Host Notify Command....................................................................... 251
131 Slave Write Cycle Format....................................................................... ................. 252
132 Slave Write Registers ................................................................. ............................ 253
133 Command Types.................................................................................................... 253
134 Read Cycle Format................................................................................................. 254
135 Data Values for Slave Read Registers........................................................................ 255
136 Host Notify Format................................................................................................. 257
137 Features Supported by Intel® 6300ESB ICH .............................................................. 258
138 AC’97 Signals ... ..................................................................................................... 262
139 Input Slot 1 Bit Definitions ...................................................................................... 267
140 Output Tag Slot 0 .................................................................................................. 269
141 AC-link State during PXPCIRST#................................................................ .............. 273
142 PCI Devices and Functions.............................................................................. ......... 276
143 Fixed I/O Ranges Decoded by Intel® 6300ESB I/O Controller Hub .... ............................ 278
144 Variable I/O Decode Ranges................................................................................. ... 281
145 Memory Decode Ranges from CPU Perspective..................................................... ...... 283
146 PCI Configuration Registers (D30:F0) ....................................................................... 287
147 Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0) ..................................... 288
148 Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0) ..................................... 288
149 Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0).................................... 289
150 Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0)............... 290
151 Offset 08h: RID—Revision Identification Register (HUB-PCI—D30:F0) ........................... 291
152 Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0) ................................... 291
153 Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0) .................................. 291
154 Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0).............. 292
155 Offset 0Eh: HEADTYP—Header Type Register (HUB-PCI—D30:F0)................................. 292
156 Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—D30:F0)................... 292
157 Offset 19h: SBUS_NUM—Secondary Bus Number Register (HUB-PCI—D30:F0)............... 293
158 Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—D30:F0) ........ 293
159 Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0) .......... 294
160 Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0)........................................ 294
161 Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0) .......................................... 295
162 Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—D30:F0) ..................... 295
163 Offset 20 - 21h: MEMBASE—Memory Base Register (HUB-PCI—D30:F0)........................ 297
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
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36 Order Number: 300641-004US
164 Offset 22 - 23h: MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)...........................297
165 Offset 24h - 25h: PREF_MEM_BASEPrefetchable Memory Base Register (HUB -PCI—D30:F0)
298
166 Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory Limit Register (HUB-PCI—D30:F0)...
299
167 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—D30:F0) .........299
168 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-PCI—D30:F0) ...........300
169 Offset 3Ch: INT_LINEInterrupt Line Register (HUB-PCI—D30:F0) ...............................300
170 Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)...................301
171 Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register (HUB-PCI—D30:F0).304
172 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register (HUB-PCI—D30:F0) ..
305
173 Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—D30:F0)...306
174 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0).............307
175 Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0).........................308
176 Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0) .................309
177 Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)............................309
178 Offset 92h: ERR_STS—Error Status Register (HUB-PCI—D30:F0)..................................310
179 Offset F8h - FBh: MANID— Manufacturer’s ID.............................................................310
180 PCI Configuration Registers (D31:F0)........................................................................311
181 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F0) .......................................312
182 Offset 02 - 03h: DIDDevi ce ID Register (LPC I/F—D31:F0)........................................313
183 Offset 04 - 05h: PCICMD—PCI COMMAND Regi ster (LPC I/F—D31:F0)...........................313
184 Offset 06 - 07h: PCISTA—PCI Device Status (LPC I/F—D31:F0)....................................314
185 Offset 08h: RID—Revision ID Register (LPC I/F—D31:F0) ............................................315
186 Offset 09h: PI—Programming Interface (LPC I/F—D31:F0)...........................................315
187 Offset 0Ah: SCC—Sub-Class Code Register (LPC I/F—D31:F0)......................................315
188 Offset 0Bh: BCC—Base-C lass Code Register (LPC I/F—D31:F0).....................................316
189 Offset 0Eh: HEADTYP—Header Type Register (LPC I/F—D31:F0)...................................316
190 Offset 40 - 43h: PMBASE—ACPI Base Address (LPC I/FD31:F0) .......... .......................317
191 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) ............................................317
192 Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0)..........................................................319
193 Offset 54h: TCO_CNTLTCO Control (LPC I/FD31:F0) ..............................................320
194 Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address (LPC I/FD31:F0) ..........................321
195 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0) ...........................................321
196 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0) ..322
197 Offset 64h: SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0).................................323
198 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/F—D31:F0)...324
199 Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—D31:F0)..............325
200 Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0)..............326
201 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)..................326
202 Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/FD31:F0)....................327
203 Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)............................................329
204 Offset D5h: BACK_CNTL—Backed Up C ontrol (LPC I/F—D31:F0) ...................................330
205 Offset D8h: RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0).........................331
206 Offset E0h: COM_DEC—LPC I/F Communication Port Decode Ranges (LPC I/F—D31:F0) ..332
207 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC I/F—D31:F0) .......333
208 Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0)......................334
209 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0)..............335
210 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0).........336
211 Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—D31:F0).....................................337
212 Offset E8h: FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)................................339
213 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/F—D31:F0) ........340
214 Offset EEh - EFh: FW H_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)........................341
215 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0)..............342
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Contents—Intel® 6300ESB ICH
2 16 Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)............................ 343
217 Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0) ................... ...... 345
218 Offset F8h: Manufacturer’s ID.................................................................................. 345
219 DMABASE_CA—DMA Base and Current Address Registers............................................ 346
220 DMABASE_CA—DMA Base and Current Address Registers............................................ 348
221 DMABASE_CC—DMA Base and Current Count Registers............................................... 349
222 DMABASE_CC—DMA Base and Current Count Registers............................................... 350
223 DMACMD—DMA Command Register.......................................................................... 350
224 DMASTA—DMA Status Register ................................................................................ 351
225 DMA_WRSMSK—DMA Write Single Mask Register ....................................................... 352
226 DMACH_MODE—DMA Channel Mode Register............................................................. 352
227 DMA Clear Byte Pointer Register .............................................................................. 353
228 DMA Master Clear Register...................................................................................... 354
229 DMA_CLMSK—DMA Clear Mask Register........................................ ............................ 354
230 DMA_WRMSK—DMA Write All Mask Register .......... .................................................... 355
231 Timer I/O Register s................................................................................................ 355
232 TCW Ti mer Control Word Register.......................................................................... 356
233 RDBK_CMD—Read Back Command........................................................................... 357
234 LTCH_CMD—Counter Latch Command....................................................................... 358
235 SBYTE_FMT—Interval Timer Status Byte Format Register ............................................ 359
236 Counter Acce ss Ports Register .................................................................................. 360
237 PIC Registers......................................................................................................... 360
238 ICW1—Initialization Command Word 1 Register.................................................... ...... 361
239 ICW2—Initialization Command Word 2 Register.................................................... ...... 362
240 ICW3—Master Controller Initialization Command Word 3 Register................................. 363
241 ICW3—Slave Controller Initialization Command Word 3 Register .................................. 363
242 ICW4—Initialization Command Word 4 Register.................................................... ...... 364
243 OCW1—Operational Control Word 1 (Interrupt Mask) Register...................................... 364
244 OCW2—Operational Control Word 2 Register.............................................................. 365
245 OCW3—Operational Control Word 3 Register.............................................................. 366
246 ELCR1—Master Controller Edge/Level Triggered Regist er............................................. 367
247 ELCR2—Slave Controller Edge/Level Triggered Register............................................... 367
248 APIC Direct Registers.............................................................................................. 368
249 API C Indirect Registers........................................................................................... 369
250 IND—Index Register............................................................................................... 369
251 DAT—Data Register................................................................................................ 370
2 52 Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register .............................................. 370
253 Offset FEC0 - EOIR: EO I Register ............................................................................. 371
254 Offset 00h: ID—Identification Register...................................................................... 371
255 Offset 01h: VER—Vers ion Register............................................................................ 372
256 Offset 02h: ARBID—Arbitration ID Register ........... .................................................... 372
257 Offset 02h: ARBID—Arbitration ID Register ........... .................................................... 373
258 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table.................. 373
259 Delivery Mode Encoding.......................................................................................... 375
260 RTC I/O Registers .................................................................................................. 376
261 RTC (Standard) RAM Bank................................... .................................................... 376
262 RTC_REGD—Register D (Flag Register) ..................................................................... 377
263 RTC_REGB—Regi ster B (General Configuration) ......................................................... 378
264 RTC_REGC—Register C (Flag Register)...................................................................... 380
265 RTC_REGD—Register D (Flag Register) ..................................................................... 380
266 NMI_SC— NMI Status and Control Register............................. .................................... 381
267 NMI_EN—N MI Enable (and Real Time Clock Index) ..................................................... 382
268 PORT92—Fast A20 and Init Register ......................................................................... 382
269 COPROC_ERR—Coprocessor Error Register ................................................................ 383
270 RST_CNT—Reset Control Register ........ .................................................................... 383
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271 Power Management PCI Configuration Registers (D31:F0)............................................384
272 Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0) ............385
273 Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0) ............386
274 Offset A4h: GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0) ............387
275 Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0)...................................388
276 Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register (PM—D31:F0).... .................389
277 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register (PM—D31:F0)..............390
278 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range
Register for Devices 4-7 (PM—D31:F0)......................................................................391
279 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register for Devices 4-7 (PM—
D31:F0)391
280 APM Register Map............................................................................... ....................392
281 APM_CNT—Advanced Power Management Control Port Register ............................. .......392
282 APM_STS—Advanced Power Management Status Port Register .....................................392
283 ACPI and Legacy I/O Register Map............................................................................393
284 PM1_STS—Power Management 1 Status Register........................................................394
285 PM1_EN—Power Management 1 Enable Register .........................................................396
286 PM1_CNT—Power Management 1 Control...................................................................397
287 PM1_TMR—Power Management 1 Timer Register ........................................................398
288 PROC_CNT—Processor Control Register .....................................................................398
289 LV2—Level 2 Register .............................................................................................400
290 GPE0_STS—General Purpose Event 0 Status Register..................................................401
291 GPE0_EN—General Purpose Event 0 Enables Register..................................................404
292 SMI_EN—SMI Control and Enable Register.................................................................405
293 SMI_STS—SMI Status Register.................................................................................408
294 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register ................... ...............................410
295 ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................................................411
296 MON_SMI—Device Monitor SMI Status and Enable Register..........................................411
297 DEVACT_STS—Device Activity Status Register............................................................412
298 DEVTRAP_EN— Device Trap Enable Register ..............................................................414
299 BUS_ADDR_TRACK— Bus Address Tracker.................................................................415
300 BUS_CYC_TRACK— Bus Cycle Tracker................ ...................................................... .416
301 TCO I/O Register Map ........................ .....................................................................416
302 TCO1_RLD—TCO Timer Reload and Current Value.......................................................417
303 TCO1_TMR—TCO Timer Initial Value .........................................................................417
304 TCO1_DAT_IN—TCO Data In Register .......................................................................418
305 TCO1_DAT_OUT—TCO Data Out Register...................................................................418
306 TCO1_STS—TCO1 Status Register ............................................................................419
307 TCO2_STS—TCO2 Status Register ............................................................................421
308 TCO1_CNT—TCO1 Control Register........... ................................................................422
309 TCO2_CNT—TCO2 Control Register........... ................................................................423
310 TCO_MESSAGE1 and TCO_MESSAGE2 Register s.........................................................423
311 Off set TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register ................................424
312 Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation Register.....................424
313 Registers to Control GPIO........................................................................................425
314 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register .............................426
315 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register......................426
316 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register....................427
317 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register.................................429
318 Offset GPIOBASE + 2Ch: GPI_INVGPIO Signal Invert Register ...................................430
319 Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register..........................431
320 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register .................432
321 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2 Register ...............432
322 PCI Configuration Map (IDE-D31:F1).........................................................................435
323 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) .......................................436
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Contents—Intel® 6300ESB ICH
3 24 Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1) ....................................... 436
325 Offset 04h - 05h: CMD—Command Register (IDED31:F1) ......................................... 437
326 Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)....................................... 438
327 Offset 08h: RID—Revision ID Register (IDED31:F1)................................................. 439
328 Offset 09h: PI—Programming Interface (IDE—D31:F1) ............................................... 439
329 Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1)....................................................... 440
330 Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)...................................................... 441
3 31 Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1) .............................................. 441
3 32 Off s et 10h - 13 h: PCM D_BA R—P rimary Com mand Bl oc k Ba se Add ress Re g iste r ( IDE—D31 : F1)
441
333 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ...
442
334 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE
D31:F1)442
335 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .
443
336 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1) ............. 443
337 Offset 24h - 27h: CPBA – IDE Command Posting Base Address .................................... 444
338 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID (IDED31:F1) ............................. 445
339 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1)........................................... 446
340 Offset 3Ch: INTR_LN—Interrupt Line Register (IDE—D31:F1) ...................................... 446
341 Offset 3Dh: INTR_PN— Interrupt Pin Register (IDED31:F1)........................................ 447
342 IDE_TIM—IDE Timing Register (IDE—D31:F1) ........................................................... 448
343 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDED31:F1) ............... 451
344 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1) .................. 452
345 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) ............ 453
346 IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)....................................... 455
347 Bus Master IDE I/O Registers .................................................................................. 455
348 BMIC[P,S]—Bus Master IDE Command Register ........................ ................................. 456
349 BMIS[P,S]—Bus Master IDE Status Register................................... ............................ 457
350 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register...................................... 459
351 PCI Configuration Map (USBD29:F0/F1) ................................................................. 461
352 Offset 00 - 01h: VID—Vendor Identification Register (USBD29:F0/F1)....... ................. 462
353 Offset 02 - 03h: DID—Device Identification Register (USBD29:F0/F1) ........................ 462
3 54 Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)...................................... 463
355 Offset 06 - 07h: STA—Device Status Register (USB—D29:F0/F1) ................................. 464
356 Offset 08h: RID—Revision Identification Register (USB—D29:F0/F1)............................. 464
357 Offset 09h: PI—Programming Interface (USB—D29:F0/F1).......................................... 465
358 Offset 0Ah: SCC—Sub Class Code Register (USBD29:F0/F1) ..................................... 465
359 Offset 0Bh: BCC—Base Class Code Register (USB—D29:F0/F1).................................... 465
360 Offset 0Dh: MLT—Master Latency Timer.................................................................... 466
361 Offset 0Eh: HTYPE—Header Type Register (USB—D29:F0/F1) ...................................... 466
362 Offset 20 - 23h: BASE—Base Address Register (USB—D29:F0/F1)................................ 467
363 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (USB—D29:F0/F1).............................. 467
364 Offset 2Eh-2Fh: SIDSubsystem ID (USB—D 29:F0/F1).............................................. 468
365 Offset 3Ch: INTR_LN—Interrupt Line Register (USB—D29:F0/F1) ................................. 468
366 Offset 3Dh: INTR_PN—Interrupt Pin Register (USB—D29:F0/F1) .................................. 469
367 Offset 60h: USB_RELNUM—USB Release Number Register (USB—D29:F0/F1) ................ 469
368 Offset C0 - C1h: USB _LEGKEY—USB Legacy Keyboard/ Mouse Control Register (USB—D29:F0/
F1)470
369 Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/F1) ....................... 472
370 USB I/O Registers................... ............................................................................... 473
371 Offset 00 - 01h: USBCMD—USB Command Register.................................................... 474
372 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation ................. 477
373 Offset 02 - 03h: USBSTA—USB Status Register.......................................................... 478
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
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40 Order Number: 300641-004US
374 Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register.....................................479
375 Offset Base + (06 - 07h): FRNUM—Frame Number Register .........................................481
376 Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address.................. ...............481
377 Offset Base + OCh: SOFMOD—Start of Frame Modify Register......................................482
378 PORTSC[0,1]—Port Status and C ontrol Register..........................................................483
379 Offset 04 - 05h: Command Register..........................................................................486
380 Offset 06 - 07h: Device Status .................................................................................487
381 Offset 08h: RID—Revision ID Register.......................................................................489
382 Offset 09h: Programming Interface...........................................................................489
383 Offset 0Ah: Sub Class Code .....................................................................................489
384 Offset 0Bh: Base Class Code....................................................................................490
385 Offset 0Dh: Master Latency Timer.............................................................................490
386 Offset 10 - 13h: Memory Base Address......................................................................490
387 Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID........................... ............................491
388 Offset 2E - 2Fh: SID—USB EHCI Subsystem ID ..........................................................491
389 Offset 34h: Capabilities Pointer ................................................................................491
390 Offset 3Ch: Interrupt Line........................................................................................492
391 Offset 3Dh: Interrupt Pin.........................................................................................492
392 Offset 50h: PCI Power Management Capability ID.......................................................492
393 Offset 51h: Next Item Pointer #1 .............................................................................493
394 Offset 52 - 53h: Power Management Capabilities ........................................................493
395 Offset 54 - 55h: Power Management Control/Status....................................................494
396 Offset 58h: Debug Port Capability ID.........................................................................495
397 Offset 59h: Next Item Pointer #2 .............................................................................496
398 Offset 5Ah - 5Bh: Debug Port Base Offset........... .......................................................496
399 Offset 60h: Serial Bus Release Number ................ .....................................................496
400 Offset 61h: Frame Length Adjustment..................... ..................................................497
401 Offset 62 - 63h: Port Wake Capability ........................................ ...............................498
402 Offset 64-65h: CUO - Classic USB Override................................................................499
403 Offset 68 - 6Bh: USB EHCI Legacy Support Extended Capability ...................................499
404 Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status.............................500
405 Offset 70 - 73h: Intel Specific USB EHCI SMI .............................................................501
406 Offset 80h: Access Control..................... ..................................................................503
407 HS_ Ref_V_USB HS Reference Voltage Register..........................................................503
408 Offset 00h: CAPLENGTH—Capability Registers Length..................................................504
409 Offset 02 - 03h: HCIVERSION—Host Controller Interface Version Number......................505
410 Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters............................505
411 Offset 08 - 0Bh: HCCPARAMS—Host Controller Capability Parameters............................507
412 Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command Register...............509
413 Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status .................................512
414 Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI Interrupt Enable..................514
415 Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index...............................................515
416 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data Structure Segment Register
516
417 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame List Base Address ...516
418 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current Asynchronous List Address ....517
419 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register ..........................517
420 PORTSC- Port N Status and Control...........................................................................518
421 Offset 00h: Control/Status Register ................................................................... .......522
422 Offset 04h: USB PIDs Register .................................................................................525
423 Offset 08h: Data Buffer Bytes 7:0.............................................................................525
424 Offset 10h: Config Register.................................................................................. ....526
425 Offset 00 - 01h: VID—Vendor Identification Register (SMBUS—D31:F3).........................527
426 Offset 02 - 03h: DIDDevi ce Identification Register (SMBUS—D31:F3).........................528
427 Offset 04 - 05h: CMD—Command Register (SMBUS—D31:F3) ............................... .......528
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 41
Contents—Intel® 6300ESB ICH
428 Offset 06 - 07h: STA—Device Status Register (SMBUS—D31:F3).................................. 529
429 Offset 08h: RID—Revision ID Register (SMBUS—D31:F3)............................................ 529
430 Offset 09h: PI—Programming Interface (SMBUS—D31:F3) .......................................... 530
431 Offset 0Ah: SCC—Sub Class Code Register (SMBU S—D31:F3)...................................... 530
432 Offset 0Bh: BCC—Base Class Code Register (SMBUS—D31:F3) .................................... 530
433 Offset 20 - 23h: SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3).............. 531
434 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4).......................... 531
4 35 Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/F4)........................................ 532
436 Offset 3Ch: INTR_LN—Interrupt Line Register (SMBUS—D31:F3).................................. 532
437 Offset 3Dh: INTR_PN— Interrupt Pin Register (SMBUSD31:F3)................................... 532
438 Offset 40h: HOSTC—Host Configuration Register (SMBUS—D31:F3) ............................. 533
439 SMB I/O Registers.................................................................................................. 533
440 Offset 00h: HST_STS—Host Status Register ........................ ........................... ........... 535
441 Offset 02h: HST_CNT—Host Control Register............................................................. 537
442 Offset 03h: HST_CMD—Host Command Register ........................................................ 539
443 Offset 04h: XMIT_SLVA—Transmit Slave Address Register........................................... 539
444 Offset 05h: HST_D0—Data 0 Register....................................................................... 540
445 Offset 06h: HST_D1—Data 1 Register....................................................................... 540
446 Offset 07h: Host_BLOCK_DB—Host Block Data Byte Register....................................... 541
447 Offset 08h: PEC—Packet Error Check Register............................................................ 542
448 Offset 09h: RCV_SLVA—Receive Slave Address Register.............................................. 542
449 Offset 0Ah: SLV_DA TA—Receive Slave Data Reg ister.................................................. 543
450 Offset 0Ch: AUX_STSAuxiliary Status Register ........................................................ 543
451 Offset 0Dh: AUX_CTL—Auxiliary Control Register ....................................................... 544
452 Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control Register......................................... 544
453 Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register.......................................... 545
454 Offset 10h: SLV_STSSlave Status Register ............................... .............................. 546
455 Offse t 11H: SLV_CMD—Slave Command Register ....................................................... 546
456 Offset 14h: NOTIFY_DADDR—Notify Device Address ................................................... 547
4 57 Offset 16h: NOTIFY_DLOW—Notify Data Low Byte Register ......................................... 548
458 Offset 17h: NOTIFY_DHIGH—Notify Data High Byte Register........................................ 548
459 PCI Configuration Map (Audio—D31:F5).................................................................... 549
460 Offset 00 - 01h: VIDVendor Identification Regist er (Audio—D31:F5) .......................... 551
4 61 Offset 02 - 03h: DID—Device Identification Register (Audio—D31:F5)........................... 551
462 Offset 04 - 05h: PCICMD—PCI Command Register (Audio—D31:F5).............................. 552
463 Offset 06 - 07h: PCISTS—PCI Device Status Register (Audio—D31:F5).......................... 553
464 Offset 08h: RID—Revision Identification R egister (Audio—D31:F5) ............................... 554
465 Offset 09h: PI—Programming Interface Register (Audio—D31:F5) ................................ 554
466 Offset 0Ah: SCC—Sub Class Code Register (Audio—D31:F5)........................................ 554
467 Offset 0Bh: BCC—Base Class Code Register (Audio—D31:F5)....................................... 555
468 Offset 0Eh: HEDT—Header Type Register (Audio—D31:F5) .......................................... 555
46 9 Offset 10 - 13h: NAMBAR—Native Audio Mixer Base Address Register (Audio—D31:F5)... 556
470 Offset 14 - 17h: NABMBAR—Native Audio Bus Masterin g Base Address Register (Audio
D31:F5)557
471 Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—D31:F5)....................... 557
472 Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register (Audio—D31:F5)................ 558
473 Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio—D31:F5)....................... 559
4 74 Offset 2E - 2Fh: SID—Subsystem ID Register (Audio—D31:F5).................................... 559
475 Offset 34h: CAP_PTR—Capabilities Pointer (AudioD31:F5)......................................... 560
4 76 Offset 3Ch: INTR_LN—Interrupt Line Register (Audio—D31:F5).................................... 560
477 Offset 3Dh: INTR_PN— Interrupt Pin Register (Audio—D31:F5)..................................... 561
478 Offset 40h: PCID—Programmable Codec ID Reg ister (Audio—D31:F5)........................... 561
479 Offset 41h: CFG—Configuration Register (Audio—D31:F5)........................................... 562
480 Offset 50h: PID—P CI Power Management Capability ID Register (Audio—D31:F5)........... 562
481 Offset 52h: PC—Power Management Capabilities Register (Audio—D31:F5).................... 563
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
42 Order Number: 300641-004US
482 Offset 54h: PCS—Power Management Control and Status Register (Audio—D31:F5) ........563
483 Intel® 6300ESB I/O Controller Hub Audio Mixer Register Configuration..........................565
484 Native Audio Bus Master Control Registers.................................................................566
485 x_BDBAR—Buffer Descriptor Base Address Register ....................................................568
486 x_CIV—Current Index Value Register ........................................................................569
487 x_LVI—Last Valid Index Register ..............................................................................569
488 x_SR—Status Register ............................................................................................570
489 x_PICB—Position In Current Buffer Register...............................................................571
490 x_PIV—Prefetched Index Value Register ....................................................................571
491 x_CR—Control Register ...........................................................................................572
492 GLOB_CNT—Global Control Registe r..........................................................................573
493 GLOB_STA—Global Status Regi ster...........................................................................575
494 CAS—Codec Access Semaphore Register ...................................................................578
495 SDM—SDATA_IN Map Register.................................................................................578
496 PCI Configuration Map (Modem—D31:F6) ..................................................................581
497 Offset 00 - 01h: VID—Vendor Identification Register (Modem—D31:F6).........................582
498 Offset 02 - 03h: DIDDevice Identification Register (Modem—D31:F6).........................582
499 Offset 04 - 05h: PCICMD—PCI Command Register (Modem—D31:F6)............................583
500 Offset 06 - 07h: PCISTA—Device Status Register (Modem—D31:F6) .............................584
501 Offset 08h: RID—Revision Identification Register (Modem—D31:F6)..............................585
502 Offset 09h: PI—Programming Interface Register (Modem—D31:F6)...............................585
503 Offset 0Ah: SCC—Sub Class Code Register (Modem—D31:F6)............... .......................585
504 Offset 0Bh: BCC—Base Class Code Register (Modem—D31:F6)...... ...............................586
505 Offset 0Eh: HEDT—Header Type Register (Modem—D31:F6) ........................................586
506 Offset 10 - 13h: MMBAR—Modem Mixer Base Address Regist er (Modem—D31:F6) ..........587
507 Offset 14 - 17h: MBAR—Modem Base Address Register (Modem—D31:F6) .....................587
508 Offset 2C - 2Dh: SVID—Subsystem Vendor ID (Modem—D31:F6) .................................588
509 Offset 2E - 2Fh: SID—Subsystem ID (Modem—D31:F6)...............................................589
510 Offset 34h: CAP_PTR—Capabilities Pointer (Modem—D31:F6).......................................589
511 Offset 3Ch: INTR_LN—Interrupt Line Register (Modem—D31:F6).............. ....................589
512 Offset 3Dh: INT_PIN—Interrupt Pin (Modem—D31:F6) ................................................590
513 Offset 50h: PID—PCI Power Management Capability ID Register (Modem—D31:F6).........590
514 Offset 52h: PC—Power Management Capabilities Register (Modem—D31:F6)..................591
515 Offset 54h: PCS—Power Management Control and Status Register (Modem—D31:F6)......591
516 Intel® 6300ESB I/O Controller Hub Modem Mixer Register Configur ation........................593
517 Modem Registers............................... .....................................................................594
518 x_BDBAR—Buffer Descriptor List Base Address Register...............................................595
519 x_CIV—Current Index Value Register ........................................................................595
520 x_LVI—Last Valid Index Register ..............................................................................596
521 x_SR—Status Register ............................................................................................596
522 x_PICB—Position in Current Buffer Register ...............................................................597
523 x_PIV—Prefetch Index Value Register........................................................................599
524 x_CR—Control Register ...........................................................................................599
525 GLOB_CNT—Global Control Registe r..........................................................................600
526 GLOB_STA—Global Status Regi ster...........................................................................602
527 CAS—Codec Access Semaphore Register ...................................................................604
528 Memory-Mapped Registers .......................................................................................605
529 Offset 000-007h: General Capabilities and ID Register ................................. ...............606
530 Offset 010-017h: General Config Register................... ...............................................607
531 Offset 020-027h: General Interrupt Status Register ....................................................608
532 Offset 0F0 - 0f7h: Main Counter Value.......................................................................609
533 Timer n Config and Capabilities ................................................................................610
534 Timer n Comparator Value.......................................................................................613
535 WDT Interface........................................................................................................617
536 Configuration Registers ...........................................................................................617
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Contents—Intel® 6300ESB ICH
537 Memory Mapped Registers....................................................................................... 618
538 Offset 00h: VID—Vendor Identification Register ......................................................... 618
539 Offset 02h: DID—Device Identification Register.......................................................... 619
540 Offset 04 - 05h: COM—Command Register ................................................................ 619
541 Offset 06h - 07h: DS—Device Status Register..... ....................................................... 620
542 Offset 08h: RID—Revision Identification R egister.... .................................................... 621
543 Offset 09h: PI—Programming Interface Register ........................................................ 622
544 Offset 0Ah: SCC—Sub Class Code Register................................................................ 622
545 Offset 0Bh: BCC—Base Code Class Register........... .................................................... 622
546 Offset 0Eh: HEDT—Header Type Register .................................................................. 623
547 Offset 10h: BAR—Base Address Register ................................................................... 623
548 Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID ......................................................... 624
549 Offset 2Eh - 2Fh: SID—Subsystem ID....................................................................... 624
550 Offset 60 - 61h: WDT Configuration Register ............................................................. 625
551 Offset 68h: WDT Lock Register ....................................................................... ......... 626
552 Offset F8 - FBh: Manufacturer’s ID .......................................... ................................. 627
553 Offset Base + 00h: Preload Value 1 Register.............................................................. 627
554 Offset Base + 04h: Preload Value 2 Register.............................................................. 628
555 Offset Base + 08h: General Interrupt Status Register ................................................. 628
556 Offset Base + 0Ch: Reload Register.......................................................................... 629
557 APIC1 Configuration Map (D29:F5)........................................................................... 631
558 Offset 00 - 03h: VID_DID—Vendor/ID Register (APIC1—D29:F5) ................................. 632
559 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—D29:F5)..................... 632
560 Offset 06 - 07h: APIC1STAAPIC1 Device Status (APIC1—D29:F5).............................. 633
561 Offset 08h: RID—Revision ID Register (APIC1—D29:F5).............................................. 634
562 Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5)......................................... 634
563 Offset 0C - 0Fh: HEADTYP—Header Type Register (APIC1—D29:F5).............................. 635
564 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers (APIC1—D29:F5)............................. 635
565 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer (APIC1—D29:F5)............................... 636
566 Offse t 3Ch: ILINE—Interrupt Line (APIC1—D29:F5).................................................... 636
567 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)....................................................... 636
5 68 Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register (APIC1—D29:F5)........... 637
569 Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—D29:F5)........................ 638
570 Offset 50 - 51h: XID—PCI-X Identifiers Regi ster (APIC1—D29:F5)................................ 639
571 Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5) ........................................... 639
572 API C1 Direct Registers............................................................................................ 640
573 API C Indirect Registers........................................................................................... 640
574 IND—Index Register............................................................................................... 641
575 DAT—Data Register................................................................................................ 641
576 IRQPA—IRQ Pin Assertion Register........................................................................... 642
577 EOIR—EOI Regi ster................................................................................................ 642
578 Offset 00h: ID—Identification Register...................................................................... 643
579 Offset 01h: VER—Vers ion Register............................................................................ 643
580 Offset 03h: BOOT_CONFIG—Boot Configuration Register............................................. 644
581 Redirection Table .................................................................. ................................. 644
582 Configuration Addressing ........................................................................................ 650
583 Comparison of Rules vs. A PCI – PCI Bridg e............................................................... 652
584 Configuration Space Register Summary..................................................................... 653
585 Offset 00: ID—Identifiers............................................................................... ......... 654
586 Offset 04: CMD—Command..................................................................................... 655
587 Offset 06: PSTS—Primary Status.......... .................................................................... 657
588 Offset 08: RID—Revision ID .................................................................................... 658
589 Offset 09: CC—Class Code ...................................................................................... 659
590 Offset 0C: CLSCache Line Size .............................................................................. 659
591 Offse t 0D: PLT—Primary Latency Timer..................................................................... 660
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
44 Order Number: 300641-004US
592 Offset 0E: HTYPE—Header Type ...............................................................................660
593 Offset 18: BNUM—Bus Numbers...............................................................................661
594 Offset 1B: SLT—Secondary Latency Timer..................................................................661
595 Offset 1C: IOBL—I/O Base and Limit.........................................................................662
596 Offset 1E: SSTS—Secondary Status..........................................................................663
597 Offset 20: MBL—Memory Base and Limit....................................................................664
598 Offset 24: PMBL—Prefetchable Memory Base and Limit......... ............. ..........................665
599 Offset 28: PMBU32—Prefetchable Memory Base Upper 3 2 Bits..................... .................665
600 Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits......................................666
601 Offset 30: IOBLU16—I/O Base and Li mit Upper 16 Bits................................................666
602 Offset 34: CAPP—Capabilities List Pointer ..................................................................667
603 Offset 3C: IN TR—Interrupt Information ...................... ...............................................667
604 Offset 3E: BCTRL—Bridge Control.............................................................................668
605 Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration............................... .671
606 Offset 42: MTT—Multi-Transaction Timer ...................................................................673
607 Offset 44: STRPPCI Strap Status............................. ...............................................674
608 Offset 50: PX_CAPID—PCI-X Capabilities Ident ifier......................................................674
609 Offset 51: PX_NXTP—Next Item Pointer................... ..................................................674
610 Offset 52: PX_SSTS—PCI-X Secondary Status............................................................675
611 Offset 54: PX_BSTS - PCI-X Bridge Status ....... ..........................................................676
612 Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control ...................................678
613 Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control ...............................679
614 Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration...................................680
615 Offset E4: PCR - PCI Compensation Register ..............................................................681
616 Offset F0: HCCR - Hub Interface Command/Control Register ........................................682
617 Offset F8h: PC33 - Prefetch Control – 33 MHz ............................................................683
618 Offset FAh: PC66 - Prefetch Control – 66 MHz ............................................................683
619 Intel® 6300ESB I/O Controller Hub PCI Transactions...................................................684
620 PCI-X Interface Command Encoding..........................................................................691
621 Intel® 6300ESB ICH Implementation of Requester Attribute Fields................................692
622 DEVSEL# Timing....................................................................................................692
623 Intel® 6300ESB ICH Implementation Completer Attribute Fields .... ...............................693
624 Split Completion Messages...................................................................................... .693
625 Immediate Terminations of Completion Required Cycles to PCI/PCI-X............................695
626 Immediate Terminations of Poste d Write Cycles to PCI/PCI-X .......................................696
627 Split Terminations of Completion Required Cycles to PCI-X...........................................696
628 Hub Interface Response to PCI-X Split Completion Terminations of Completion Required Cycles
697
629 Terminations of Completion Required Cycles to Hub Interface.......................................698
630 Universal Asynchronous Receive And Transmit (UART0, UART1)....................................704
631 Address Map..........................................................................................................706
632 Supported LPC Cycle Types......................................................................................706
633 I/O Sync Bits Description.........................................................................................707
634 UART Clock Divider Support.....................................................................................708
635 Baud Rate Examples...............................................................................................708
636 SIU Signal Reset States...........................................................................................710
637 Internal Register Descriptions ........................................... .......................................710
638 Receive Buffer Register (RBR)..................................................................................711
639 Transmit Holding Register (THR) ..............................................................................711
640 Interrupt Enable Register (IER) ...................................................... ..........................712
641 Interrupt Conditions................................................................................................713
642 Interrupt Identification Register (IIR)........................................................................713
643 Interrupt Identification Register Decode .... ................................................................714
644 FIFO Control Register (FCR).....................................................................................714
645 Line Control Register (LCR)................. .....................................................................716
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Contents—Intel® 6300ESB ICH
646 Line Status Register (LSR) .................... ............................ ........................... ........... 718
647 Modem Control Register (MCR) ....................... ......................................................... 720
648 Modem Status Register (MSR) ................................................................................. 721
649 Scratch Pad Register (SCR) ..................................................................................... 722
650 Divisor Latch Register Low (DLL)............... ............................................................... 722
651 Divisor Latch Register High (DLH) ............................................................................ 723
652 Scratch Pad Register P60 (SCR60)............................................................................ 725
653 Scratch Pad Register P64 (SCR64)............................................................................ 725
654 SIU_SERIRQ Sampli ng Periods................................................................................. 727
655 Configuration Registers Summary ............................................................................ 730
656 Global Control Registers.......................................................................................... 731
657 Logical Device 4 (Serial Port 0)................................................................................ 732
658 Logical Device 5 (Serial Port 1)................................................................................ 734
659 Logical Device 7 (Port Emulation)............................................................................. 735
660 PCI Configuration Map (SATA–D31:F2) ..................................................................... 737
661 Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2).......................................... 738
662 Offset 02 - 03h: DID—Device ID Register (SATAD31:F2) .......................................... 739
663 Offset 04h - 05h: CMD—Command Register (SATA–D31:F2)........................................ 739
664 Offset 06 - 07h: STS—Device Stat us Register (SATA–D31:F2) ..................................... 741
665 Offset 09h: PI—Programming Interface (SATA–D31:F2) .............................................. 742
666 Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2)...................................................... 742
667 Offset 0Bh: BCC—Base Class Code (SATA–D31:F2) .................................................... 743
668 Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2) ............................................. 743
669 Offset 10h - 13h: PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2)
744
670 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) ..
744
671 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base Address Register (IDE
D31:F1)745
672 Offset 14h - 17h: SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) .
745
673 Offset 20h - 23h: BAR—Legacy Bus Master Base Address Register (SATA–D31:F2) ......... 746
674 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SATA–D31:F2).................................. 746
675 Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)................................................ 747
676 Offset 34h: CAP—Capabilities Pointer Register (SAT A–D31:F2).................................... 747
6 77 Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2) ..................................... 747
678 Offset 3Dh: INTR_PN—Interrupt Pin Register (SATA–D31:F2) ...................................... 748
679 Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA–D31:F2) ..................... 748
680 Offset 44h: SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................. 750
681 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2)................. 751
682 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2) ........... 752
683 Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2)..................... 754
684 Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–D31:F2).................. 755
685 Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–D31:F2)..................... 755
6 86 Offset 74 - 75h: PMCS—PCI Power Management Control and Status (SATA–D31:F2)....... 756
687 Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers (SATA–D31:F2)................ 757
688 Offset 82 - 83h: MC—Message Signaled Interrupt Message Control (SATA–D31:F2)........ 757
689 Offset 84 - 87h: MA—Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 758
690 Offset 88 - 89h: MD—Message Signaled Interrupt Message Data (SATA–D31:F2) ........... 759
691 Offset 90h: MAP—Address Map (SATA–D31:F2) ......................................................... 759
692 Offset 92h: PCS—Port Status and Control (SATA–D31:F2)........................................... 760
693 Offset A0h: SRI—SATA Registers Index (SATA–D31:F2).............................................. 760
694 Offset A4h - A7h: SRD—SATA Registers Data (SATA–D31:F2).. .................................... 761
695 STTT—SATA TX Termination Test Register A (SATAD31:F2) ....................................... 762
696 STOT — SATA TX Output Test Register (SATA–D31:F2)............................................... 762
Intel® 6300ESB ICH—Contents
Intel® 6300ESB I/O Controller Hub
DS November 2007
46 Order Number: 300641-004US
697 Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–D31:F2) .............. ....763
698 Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–D31:F2) .............. ....763
699 Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ....................763
700 Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2).................765
701 Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Regist er (SATA–D31:F2).................766
702 Bus Master IDE I/O Registers...................................................................................766
703 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .. ..........................................767
704 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) .................................................768
705 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2).........................769
706 Signal List (Alphabetical List) ...................................................................................774
707 Signal List (by Location)..........................................................................................781
708 DC Current Characteristics (Preliminary)....................................................................790
709 DC Characteristic Input Signal Association .................................................................790
710 DC Input Characteristics..........................................................................................791
711 DC Characteristic Output Signal Association ...............................................................793
712 DC Output Characteristics........................................................................................794
713 Other DC Characteristics ....................................................... ..................................794
714 Clock Timings ........................................................................................................796
715 PCI-X Interface Timings ..................... .....................................................................799
716 PCI Interface Timing...............................................................................................800
717 IDE PIO and Multiword DMA ModeTiming ...................................................................801
718 Ultra ATA Timing (Mode 0, Mode 1, Mode 2)...............................................................802
719 Ultra ATA Timing (Mode 3, Mode 4, Mode 5)...............................................................804
720 Universal Serial Bus Timing......................................................................................806
721 SATA Interface Timings...........................................................................................808
722 SMBus Timing................................................... .....................................................808
723 AC’97 Timing .........................................................................................................809
724 LPC Timing ............................................................................................................809
725 Miscellaneous Timings.............................................................................................809
726 UART Timings ........................................................................................................810
727 Power Sequencing an d Reset Signal Timings ......... .....................................................811
728 Power Management Timings................ ...................................................... ...............812
729 Clock Uncertainty Parameters ..................................................................................813
730 PCI-X Measurement Condition Parameters .................................................................815
731 Test Mode Selection................................................................................................825
732 XOR Test Pattern Example.......................................................................................827
733 XOR Chain #1 (RTCRST# asserted for 4 PCI clocks
while PWROK active)...............................................................................................827
734 XOR Chain #2 (RTCRST# asserted for 5 PCI clocks
while PWROK active)...............................................................................................828
735 XOR Chain #3 (RTCRST# asserted for 6 PCI clocks
while PWROK active)...............................................................................................829
736 XOR Chain #4 (RTCRST# asserted for 7 PCI clocks
while PWROK active)...............................................................................................831
737 XOR Chain #5 (RTCRST# asserted for 59 PCI clocks
while PWROK active)...............................................................................................831
738 XOR Chain #6 (RTCRST# asserted for 52 PCI clocks wh ile PWROK active)......................834
739 XOR Chain #7 (RTCRST# asserted for 60 PCI clocks wh ile PWROK active)......................834
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Contents—Intel® 6300ESB ICH
Revision History
Date Revision Description
November
2007 004
I ncluded S p ec if ica tion Chan g es fro m sp e cif ication up date, version 0 11
Figure 61: U pdat ed t o repl ace V_C PU_I O with VccH I
I ncluded S p ecification s Clarifications from specifica tion update, version 01 1
Table 727 and Table 728: Updated t175, t176 & t184 timing def initions
to clarify which Vcc supplies a pp ly t o e a ch
Section 5.11.1 and 5 .11.6: Clarified wording regarding support of C2
sta te for dual pr ocesso rs, dual core and pr ocesso rs with Hyp erThrea ding
Technology.
Table 191: Re move incorrect references to TCO in Note
Section 5.7.1: Remove d refe re nces to three wire APIC bus. 63 00ES B
does not supp ort this feature.
Table 31: M oved Note 1 re fernces f rom I/O to M em ory cycles
Table 727: Ch anged N ote 2 to re qu ire that 3.3V and 1. 5V rails mu st
power up or down together
Removed all references to Processor Speed Strapping. Processors used
in conjunction with 6300ESB do not use this feature.
Table 319: Modified regi ster defintions to reflect that signals are
configured as native functions after a full reset.
Section 19.1: Add Note to indi cate that S I Us are not completely 16550
compatible.
Table 635: Ad d ed % er ror ra te s.
Section 5.10.2.2: Ch a nged to cla rify where mu ltiple proces sor or
multip le core configur ations can generate Stop Gr ant cycles in the MCH
suppo r t s it.
I ncluded D ocumentation Cha nges 2 to 13 fro m sp e cif ica tion update, version
011
Table 568: Revised to allow bit column to align corre ctly.
Section 22.2: Added Case temperature under Bias value
Changed all references to PCIRST# to PXPCIRST#
Table 317: Ch anged re g ister d e ult value to 00000000h
Figure 5: Correct typo in diagram
Table 28: Chan g e G P IO[21] Afte r Reset value to logic ‘1
Corrected Prod uct Features sectio n to show that PC I-X Rev 1.0 is
supported
Table 22: Correct V5REF definition
Table 573: Co rre ct ind e xes for Rese rved Registe rs
Table 581: Revised naming and definitions for bits 10:8 and 7:0. Added
Note at bot t om of tab le .
Table 728: Revised ‘SLP_S5# inactive to SLP_S 4#’ p a ramete r timing
values
Table 313: Remove d GPO_TTL re gister list ing . This register was not re le vant
to 6300ESB
Table 29, Figure 61 and Figure 62: Removed refer ences to LAN_RST and
RSM_PWROK signals wh ich do not e xist in 6300ES B
Table 731, Figure 66: Updated t o correct tim i ng requir em ent s for ente ring
test mode.
Section 5.7 and Section 8.5: Removed PCI register refer ences for APIC0.
APIC0 regis te rs a re purely mem ory mapp e d.
Intel® 6300ESB ICH—Contents
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Change Bars
A change bar to left of text, a table row or a figure heading indicates
thi s it em is either new or m odified from th e previous versio n of the
document.
December
2004 003
Included changes from previous spec updates
Updat ed Sec t ion 22.1
Updat ed Sec t ion 22.2
Updated DC Characteristics Section 22.3
-Up dated AC Chara cteristics Sect ion 22.4
June 2004 002 Clarified WDT Reload reg iste r b it d e ta ils; listed USB HS re fere nce voltage
register bits.
February 2004 001 Initial re lease of this docume nt.
Date Revision Description
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1—Intel® 6300ESB ICH
Introduction 1
1. 1 Abo ut This Do cument
This datasheet is intended for Original Equipment Manufacturers (OEMs) and BIOS
vend ors cre ating produ cts ba sed on the Intel ® 6300E SB I/O Control le r Hub (ICH ). Thi s
manual assumes a working knowledge of the vocabulary and principles of USB, IDE,
AC’97, SMBus, PCI, ACPI, and LPC. Although some details of these features are
described herein, refer to the individual industry specifications listed in Table 1 for the
complete details.
Tabl e 1. Indu s try Spec ifi cat io ns
Specification Location
Low Pin Count Interface Specification, Revision
1.0 (LPC) http://developer.intel.com/design/chipsets/
industry/lpc.htm
Audio Codec ‘97 Component Specification,
V ersion 2.2 (AC’97) http://www.intel.com/labs/media/audio/
index.htm
PCI-X Speci fic ation , Revis ion 1.0 http://www.pcisig.com/specifications/pcix_20/
pci_x/
System Management Bu s Specification,
Version 2.0 (SMBus) http://www.smbus.org/specs/
PCI Local B us S pecification, Revision 2.2 (PC I) http://pcisig.com/specs.htm
Unive rsa l S erial Bus Revisio n 2. 0/1 .0
Specification (USB) http://www.usb.org
Advanced Configuration and Power Interface,
Version 1.0b (ACPI) http://www.teleport.com/~acpi/
Enhanced Host Controll er Interface
Specification for Universal Serial Bus, Revision
0.96 (EHCI )
http://developer.intel.com/technology/usb/
ehcispec.htm
SATA 1.0 S p e cif ication http://www.serial a ta.org /collateral/ind e x .shtml
Other Ind ustry Specif ica tions http://www.intel.com/design/motherbd/bv/
bv_industryspecs.htm
Intel® 6300ESB ICH—1
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This document contains these chapters:
Chapter 1, “Introdu ction” i ntr oduces th e Inte l® 63 00ESB ICH and pro vide s infor mation
on manual organization.
Ch ap t e r 3, “S ig na l Desc r i ption provides a detaile d description of each Intel® 6300ESB
ICH signal. Signals are arranged according to interface. Details are provided about the
drive characteristics (Input/Output, Open Drain, etc.) of all signals.
Chapter 2, “Intel® 6300ESB ICH and System Clock Domains” provides a list of each
cl ock dom ain assoc iate d with the In tel® 6300E SB IC H in an Int el® 6 300ES B I CH-b ase d
system.
Ch apter 4 , “Inte l® 630 0ESB IC H P ower Pl anes and Pin Sta te s” provides a complete list
o f si gn al s, t he ir as so ci at ed p owe r we l l, the i r lo gic l ev el i n e ac h su sp en d s ta te , a nd their
logic level before and after reset.
Chapter 5, “Functional Description” provides a detailed description of the functions in
th e In t e l ® 6300ESB ICH. All PCI buses, devices, and functions in this manual are
abbreviated using the following nomenclature; Bus:Device:Function. This manual
abbreviates buses as B0 and B1, devices as D8, D29, D30 and D31 and functions as F0,
F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 5 is abbreviated as
D31:F5, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus
number will not be used, and may be considered to be Bus 0. Note that the Intel®
6300ESB ICH’s external PCI bus is typically Bus 1, but may be assigned a different
number depending upon system configuration.
Chapter 6, “Register and Memory Mapping” provides an overview of the registers, fixed
I/O ranges, variable I/O ranges, and memory ranges decoded by the Intel® 6300ESB
ICH.
Chapter 7, “Hub Interface to PCI Bridge Registe rs (D30:F0)” provides a detailed
description of all registers that reside in the Hub Interface to PCI bridge. This bridge
resides at Device 30, Function 0 (D30:F0).
Chapter 8, “LPC I/F Bridge Registers (D31:F0)” provides a detailed description of all
registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0
(D31:F0). This function contains registers for many different units within the Intel®
6300ESB ICH including DMA, Timers, Interrupts, CPU Interface, GPIO, Power
Management, System Management and RTC.
Chapter 9, “IDE Controller Registers (D31:F1)” provides a detailed description of all
registers that reside in th e IDE con troller. This c ontroller resides at Device 31, Function
1 (D31:F1).
Chapter 10, “USB UHCI Controllers Registers” provides a detailed description of all
registers that reside in the three UHCI host controllers. These controllers reside at
Device 29, Functions 0, 1 and 2 (D29:F0/F1/F2).
Chapter 11, “USB EHCI Controller Registers (D29:F7)” provides a detailed description
of all registers that reside in the EHCI host controller. This controller resides at Device
29, Function 7 (D29:F7).
Chapter 12, “SMBUS Controller Registers (D31:F3)” provides a detailed description of
all registers that reside in the SMBus controller. This controller resides at Device 31,
Function 3 (D31:F3).
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Chapt er 13, “ AC’97 Audio C ontroll er R egisters (D31:F5) provides a detailed description
of all registers that reside in the audio controller. This controller resides at Device 31,
Function 5 (D31:F5). Note that this section of the EDS does not include the native
audio mixer reg isters. Accesses to the mix er registers are forwarded over th e AC-li nk to
the codec where the registers reside.
Chapter 14, “AC’97 Modem Controller Registers (D31:F6)” provides a detailed
description of al l registers that reside in the mo dem controller. This controller resides at
Device 31, Function 6 (D31:F6). Note that this section of the EDS does not include the
modem mixer re gisters. Accesses to the mixer registers are forwarded over the AC-link
to the codec where the registers reside.
Chapter 15, “Multimedia Timer Registers” provides a detailed description of all registers
that reside in the multimedia event timer memory mapped register space.
Chapter 16, “Watchdog Timer (WDT) (D29:F4)” provides a detailed description of the
configuration registers in the WDT controller. These registers reside at Device 29,
Function 4 (D29:F4).
Chapter 17, “APIC1 Configuration Registers (D29:F5)” provides a detailed description
of the configuration registers in the APIC1 controller. These registers reside at Device
29,
Function 5 (D29:F5).
Chapter 18, “PCI-X Overview (D28:F0) provides a detailed description of the
configuration registers of the PCI-X controller. These registers reside at Device 28,
Function 0 (D28:F0).
Chapter 19, “Serial I/O Unit describes the SIU, its features, LPC interface, serial ports
and Port 60/64 Emu lation along with a description of the registers in the SIU. These
registers reside at Device 31, Function 0 (D31:F0).
Chapter 20, “Serial ATA Controller Registers (D31:F2)” provides a detailed description
of th e regi ster s that r esid e in the S A T A con trol ler wh ich en comp asse s a PCI devi ce. Th is
controller resides at Device 31, Function 2 (D31:F2).
Chapter 21, “Package Information” provides ballout information, signal lists and
mechanical drawings.
Chapter 22, “Electrical Characteristics” provides AC and DC characteristi cs and AC
timings.
Chapter 23, “Testability provides information on test modes and scan chains.
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2—Intel® 6300ESB ICH
Intel® 6300ESB ICH and System
Clock Domains 2
Warning:This sect ion is provided for background purposes and should not be
considered by implem ent ers and validator s as part of the behavioral definition
of the Inte l ® 6300 ESB ICH.
Table 2 presents the Intel® 6300ESB ICH clock domains. Figure 4 s h ow s the assu me d
conne c tion of th e v ariou s sys te m com ponen ts, in cl udi ng the cloc k gener ator i n de skto p
systems. For complete details of the system clocking solution, refer to the system’s
clock generator component specification.
Tabl e 2. Inte l® 6300ESB ICH Clock Domains
Clock
Domain Frequency Source Usage
Hub
Interface 66.66 MHz Main Clock
Generator Hub Interf ace, CPU I/ F, AGP. Shu t o ff durin g S3 or
below.
PCI 33.33 MHz Main Clock
Generator
The Intel® 6300ESB ICH, PCI, LPC I/F. This
remains on during S0-S1 states, and may b e shut
off during S3-S5. The PCI clock to peripherals
may b e sh ut of f usi ng the CLKRUN# prot ocols.
USB/SIO 48.00 MHz Main Clock
Generator USB 1.0 Controllers in the Intel® 630 0ES B ICH,
External Super I/O. Shut off in S3 or below.
USB2.0 48.00 MHz Internal USB 2.0 logic close to the pins. Shut off when the
48 MHz clock input is sh ut of f (S1 f or low p owe r,
as we ll as S3 or below)
OSC 14.31818 M
Hz Main Clock
Generator
Used by ACPI timer. Also used by the Multimedia
Timers Logic. Shut off in S1 for low power, as well
as S3 or below.
AC’97 12.288 MHz AC’97 Code c AC’97 Link. Generated by AC’97 CODEC. May be
shut off by codec in D3, as well as S1 for low
power, and S3 or below.
RTC 32.768 KHz Intel®
6300ESB ICH
RTC, Power Manag eme nt. The Int el® 6300ES B
ICH has its own oscillator.
Always running, even in G3 state.
PCI-X 66 MHz External
UART 14.7456,
48 MHz
Main Clock
Generator
and/or
discr et e c loc k
circuit.
UART clock inpu t.
NOTE: S ome clock chips prov id e a 14.318x MHz
clock outp ut. The Intel® 6300 ESB ICH’s
UART clock must use a 14.74 56 MH z
freque ncy; mos t cloc k chips do not
provide this frequency. An option will be to
use the 48.0 MHz clock.
SATA 100 MHz Main Clock
Generator 1.5 GHz cloc k ge ne rated internal to the Inte l®
6300ESB ICH for use by SA TA phy.
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Figure 4. Conceptual System Clock Diagram
Intel®
6300ESB
ICH
PCI Clocks
(33 MHz)
Clock
Gen. 14.31818 MH
z
48 MHz
32 kH z
XTAL SUSCLK# (32 kHz)
AC’97 Codec(s)
12.288 MHz
66 MHz
33 MHz
14.31818 MHz
48 MHz
100 MHz Diff. Pair
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3—Intel® 6300ESB ICH
Signal Description 3
This section provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.
The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when at the high voltage level.
The following notations are used to describe the signal type:
IIn p ut P in
O Output Pin
OD Open Drain Output Pin
I/O Bi-directional Input/Output Pin
3.1 Hub Interface to Host Controller
Table 3. Hub Interface Signals
Name Type Description
HI[11:0] I/O Hub Inte r face Signals
HI_S TBS I/O
Hu b I n terf ace Strobe Second: One of two diffe rent i al strob e
signals used to transm it and rece ive da ta throug h the H ub Inter fac e.
Hub Interface 1.5 mode this signal is not differential and is the second
of the tw o strob e sig n als.
HI_S TBF I/O
Hu b I n terf ace Strobe Fi rst: One of two differe ntia l strobe sig n als
used to transmit and rece iv e data thro ugh the Hu b Interf a ce.
Hub Interface 1.5 mode this signal is not dif ferential and is the first of
the t wo strobe signals.
HICOMP I/O
Hub Interface Compensation: Used for Hub Interface buffer
compensation.
NOTE: Th e Int e l ® 6300ES B ICH will only support RCO M P, not the
ZCOM P mode.
HICLK IHub In terfac e Clock: 66 MHz clock input for Hub Interface. It is also
used for some othe r interna l u nits. This cl ock will stop during S3-S5
states.
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3.2 Firmware Hub Interface
HIREF IHub Interf ace Vol tage Referen ce. Analog in put, expec ted
voltage 350mV
HI_VSWING I
Hub In terf ace Vol tage S wing : An alog input used to control the
voltage swing and impedance strength of Hub Interface pins.
Expected voltage is 800 mV.
NOTES:
1. Refer to the platform design guide for expected voltages.
2. Refer to the platform design guide for res istor values and routing
guidelines for each Hub Interface mode.
NOTES:
1. The Hub Interface signals are all in a separate power plane, called the Hub Interface plane.
2. During the S3, S4, and S5 states, power to the Hub Interface is assumed to be off. During S0
and S1 states, power to the Hub Interface must be on.
Table 4. Firmware Hub Interface Signals
Name Type Description
FWH[3:0] /
LAD[3:0] I/O Firmware Hu b Signal s . Mu xe d with LPC address s ignals. Int e rna l
pull-ups are provided.
FWH[4] /
LFRAME# I/O Firmware Hub Sig nals. Muxed with LPC LFRAME# signal. LFRAME#:
Indicates the start of an LPC cycle, or an ab or t.
NOTE: All L P C/FW H signals a re in the core well.
Table 3. Hub Interface Signals
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3. 3 PCI Interface
Table 5. PCI Interface Signals (Sheet 1 of 3)
Signal
Name Type Description
AD[31:0] I/O PCI Addr e ss/D a t a: A D[31:0] signals are multiple xed . D u ring th e first
clock of a tran sa ction, AD[ 31:0] contain the phy sical addre ss (32 bit s).
After the first clock, AD[31:0] conta in d ata .
C/
BE[3:0]# I/O
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed. During the address phase of a transaction , C/
BE[3:0]# define the bus command. During the data phase C/BE[3:0]#
are used as Byte Enables. All co mmand encoding not s hown are reserved.
C/BE[3:0]# Command Type Com me nt
0 0 0 0 Interrupt Ackn owle d g e
0 0 0 1 Special Cycle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 1 0 Memory Read
0 1 1 1 Memory Write
1 0 1 0 Conf ig uration Read
1 0 1 1 Configuration Write
1 1 0 0 Memory Read Multip le
1 1 0 1 DAC Mode Address to be latched (target only)
1 1 1 0 Memory Read Line
1 1 1 1 Memory Write and Invalidate
The Intel® 6300ES B ICH will not use rese rv e d values, a nd wi ll n ot
respo nd if a PCI mast er gener ates a cycl e using a reserv ed v alue. See PC I
section for deta ils on how the se command s are su pported de pending on
the Intel® 6300ESB ICH’s role in the PCI cyc le (targ et or initia tor).
As a target, the Intel® 6300E SB ICH can support DAC mode ad dr essing
for 44 bits.
DEVSEL# I/O
Device Select: The I nte l® 6300ESB ICH asserts DEVSEL# to c laim a PCI
tran saction. As an output, the Inte l® 6300ESB ICH asserts DEVSEL#
when a PCI master peripheral attempts an access to an internal Intel®
6300E SB ICH addr ess or an add ress de stined for H ub Inter face (main
memo ry or AGP). A s an inp u t, D E VSEL # ind icate s th e res po nse to an
Intel® 6300ESB I CH-in itiated transac tion on the PCI b u s. D E VSEL# is tri-
stated from the leading edge of PXPCIRST#. DEVSEL# remains tri-stated
by the Intel® 6300ESB ICH until d riven as a target.
FRAME# I/O
Cycle Fr ame: FRAME# is dri ven by the curre nt Ini tiator to ind icate the
beginning and duration of an access. While FRAME# is asserted data
tran sf ers continue. When FRAM E# is ne ga te d the transaction is in the
final data phase. FRA ME# is an input to the Intel® 6300ESB ICH when it
is the Target. FRAME# is an outp ut whe n the Intel® 6300ESB ICH is the
initiato r. FRA M E# remains tri-stated by the Inte l® 6300ESB ICH until
driven as an in itiator.
IRDY# I/O
Initiator Ready: IRDY# indicate s the Int el® 6300ESB ICH s ability , as an
Initiator, to complete the current data phase of the transaction. It is used
in conjunction with TRDY#. A data phase is completed on any c lock both
IRDY# and TRDY# are sampled asserted. Duri ng a write, IRDY# indicates
the Intel® 6300ESB ICH has valid data p resent on A D[31:0]. Durin g a
read, it ind icates the Intel® 6300ESB ICH is pre pared to latch data.
IRDY# is an input to the Intel® 6300ESB ICH when the Intel® 6300 ESB
ICH is the Target and an output when the Intel® 6300ESB ICH is an
Initiato r. IRDY# re ma ins tri-sta te d by the Intel ® 6300ESB ICH until
driven as an in itiator.
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TRDY# I/O
Targ et Rea dy: TR DY# indicates the Intel® 6300ESB ICH’s ability to
comp le te the current data phase of th e transaction. TRDY# is used in
conj unction with IRDY#. A data phase is co mp le te d wh en both T RDY #
and IRDY# are sampled asserted. During a read, T RDY# indicates that
the Intel® 6300ESB ICH, as a Target, has placed valid data on AD[31:0].
During a write, it indic a te s the Intel® 63 00ES B ICH, as a Target is
prep are d to latch d ata. TRDY# is an input to the Intel® 6300ESB ICH
whe n the Intel® 6300ESB ICH is the Initiator and an output whe n th e
Intel® 6300E S B ICH is a Targ e t. TRD Y# is tri-stated from the leading
edg e of PXPCIRS T #. TRDY# remains tri-stated by the Intel® 6300ESB
ICH until driven a s a targ e t.
STOP# I/O
Stop: S TOP# indicat es that the Intel® 6300ESB ICH, as a Target, is
reque sting an ini tia tor to stop the curre n t tra nsa ction. As an In itiator,
STOP# causes the Intel® 6 300ES B ICH to stop the current transaction.
STOP# is an output when the Intel® 6300ESB ICH is a Target and an
input when the Intel® 6300ESB ICH is an Initiat or. STOP# is tr i-stated
fro m th e leading edge of PX PCIRST#, and remains tri-sta te d un til dr iven
by the Intel® 6300ESB ICH as a slave.
PAR I/O
Calcu lated/Checked Parity: PAR is “even” parity an d is ca lculated o n
36 bits – AD[31:0] plus C/BE[3:0]#. “Even” parity m ean s that the
number of1”s within the 36 bits plus PAR are c ounted and the sum is
al ways even. PAR is always calculated o n 36 bi ts re g a rd le ss of th e valid
byte ena bles. PAR is gener a ted fo r addres s and data pha ses, and is only
ensured t o be v alid one PCI clock after the c or respo nding addr ess or data
phase. PAR is dri ven a nd tri-sta ted identically to the AD[ 31:0] line s,
except that PAR is delayed by exactly one PCI clock. PAR is an output
during the address phase (delayed one clock) for all Intel® 6300ESB ICH
initiated transactions. It is also an output during the data phase (delayed
one clock) when the Intel® 6 300ES B ICH is the Initiator o f a PCI write
transaction, and when it is the Target of a read transaction.
The I n t e l ® 6300ESB ICH c hecks parity on the data phase when it is the
Initiator of PCI read trans actions and w hen it is the Target of PCI write
t rans a ctions. It al so checks parity on the a d dress ph ase w he n it is t he
target of PCI transitions. If a parity error is detected, the Intel® 6300ES B
ICH will set the a ppropriate in te rna l status bits, an d ha s the option to
generate an NMI# or SMI#.
PERR# I/O
Pari ty Er ror : Driven by an external PCI device when it receives data that
has a parity e rror. Driven b y the Intel® 6300ES B ICH whe n it detects a
parity error. The Intel® 6300ESB ICH can e ither g e nerate an NMI# or
SMI# upon detecting a parity error (eithe r detected internally or reported
via PERR# signal) when serving as an initiator.
REQ[0:3]# IPCI Requests: Sup p orts up to 4 ex ter nal masters on the PCI bus.
GNT[0:3]# OPCI Grants: Supports up to 4 external masters on the PCI bus.
PCICLK I
NOT E: P CI Clock: 33 MHz clock. PCICLK provides timing fo r a ll
t ransa ctions on the PCI Bu s, a s well a s man y un its inside the
Intel® 6300ES B ICH .
This clock c an be st opped in S1 or S 3, S4, o r S5 st ates. T his si gnal
is not
5 V toleran t .
Table 5. PCI Interface Signals (Sheet 2 of 3)
Signal
Name Type Description
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 59
3—Intel® 6300ESB ICH
PLOCK# I/O
PCI Lock: Indicates an exclusive bus operation and may require multiple
tran sactions to comple te . The Inte l® 6300ESB ICH ICH asserts PLOCK#
when it is d oing n on-e xc lu siv e t ransa ctions on PCI. PLOCK# is ignored
when PCI masters are granted the bus.
SERR# I/OD
System E rror: SERR# can be pulsed active by any PCI device that
detects a syste m error con d ition. Up on sa mplin g SE RR# active, t he
Intel® 6300ESB ICH can be programmed to generate an NMI or SMI#.
Implemented as I/O open drain. This allows the Intel® 6300ESB ICH to
drive these signals due to internal sources.
PME# I/OD
PCI Power Management Event: Driven by PCI peri pherals to wake t he
syste m from low-power states S1 -S5. I f ca n a lso cause an SCI from the
S0 state. Note tha t in som e cases the Intel® 6300ESB ICH may drive
PME# acti ve (low) due to an inte rnal wake event. It will not dri ve PME#
high (bu t it may be pulled up using the i nte rnal pull- u p resi s tor) .
NOTE: PM E# is in the Resume powe r plane and has an inte rn al pull-u p
resistor.
NOTE: PME# is also used in the PCI-X segm en t.
Table 5. PCI Interface Signals (Sheet 3 of 3)
Signal
Name Type Description
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
60 Order Number: 300641-004US
3.4 PCI-X Interface
Table 6. PCI-X Interface Signals (Sheet 1 of 4)
Name Type Description
PXAD[31:0] I/O
PCI-X Add ress/ Data: These signals are a multiplexed address and
data bus. During the address phase or phases of a transaction, the
in itiator drives a physica l addre ss on PX AD[31:0]. During the data
phases of a transac tion , the in itiator drives wr ite data, or the target
drives read dat a. The Intel® 6300ESB ICH will dr ive all 0’s on
PXAD[31:0] during the address phase of all PCI-X Special Cyc les.
PXAD[63:32
]I/O
PC-X Address/Data: These signals are a multiplex ed address and
data bus. This bus provides an additional 32 bits to the PCI-X bus.
During the data phases of a transaction, the initiator drives the upper
32 bits of 64-b it write d a ta, or the target drives the upper 32 bits of
64-bit read data, when PX REQ64# and PXA CK64# are both asserted.
When not driven PXAD[63:32] are pulled up to a valid logic level
t hrou g h e xte rnal resistors.
NOTE: When not driven PXAD[63:32] are pulled up to a valid logic
leve l th rough exter n a l re sistors.
PXC/
BE#[3:0] I/O
Bus Command and Byte Enables: T he command and byte enable
signals are multiplexed on the same PCI-X pins. During the address
phase of a transaction, PXC/BE#[3:0] define the bus command .
During the data phase PXC/BE[3:0]# define the Byte Enables.
PXC/ B E#[3 : 0] Comm and Ty pe
0 0 0 0 In te rrup t Ack n owledge
0 0 0 1 Spe cial Cy cle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 1 0 Mem ory Read
0 1 1 1 Memory Write
1 0 1 0 Conf iguration Read
1 0 1 1 Conf ig uration Write
1 1 0 0 Mem ory Read Multip le
1 1 1 0 Mem ory Read Line
1 1 1 1 Mem ory Write and Invalidate
All command encodings not shown are reserved. The Intel® 6300ESB
ICH does not de c ode re s erved values, a nd theref o re w il l not r espond
when a PCI-X master generates a cycle using one of the reserved
values.
PXC/
BE#[7:4] I/O
Bus Command and Byte enables upper 4 bits: These signals are
a mul t ipl exed co m mand fiel d and byte en abl e field. F o r both reads
an d write transactions, the initiator w ill d rive b yte e na b le s f or th e
PXAD[63:32] data bits on PXC/BE#[7:4] during the data phases
when PXREQ6 4# an d PXACK64# are bo th asserted. When not drive n,
PXC/BE#[7:4] are p u lle d up to a valid log ic le vel through exte rna l
resistors.
PXDEVSEL# I/O
Device Se lect: Th e Intel® 6300ESB ICH asserts PXDEVSEL# to
claim a PCI tra nsaction. As an output, the Intel® 6300ESB ICH
asserts DEVSEL# when a PCI master peripheral attempts an access
to an internal Intel ® 6300ESB ICH address or an address destined for
th e Hub Inte rf a ce (ma in memory or A G P). A s an in pu t, DEV S EL#
indicates the re sponse to an Intel® 6300ESB ICH-initiated transaction
on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PXPC IRS T#. PXDEV SEL# remains tri-stated by the Inte l® 6300ESB
ICH until driven b y a Ta rget devi ce .
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 61
3—Intel® 6300ESB ICH
PXFRAME# I/O
Cycle Frame: The current Initia tor drives PXFRAM E# to indicate the
beginning and duratio n of a PCI transa ction. While the in itiator
asserts PX FRA ME#, d a ta tran sfer s cont inue . W he n the init iator
negates PXF RA ME#, the transactio n is in the final data
phase.PX FRA ME# is an input to the Inte l® 6300ES B ICH whe n the
Intel® 6300ESB ICH is the targ e t, and PXFRAME# is an outpu t from
the Intel® 6300ESB ICH when the Intel® 6300ESB ICH is the
Initiato r. PX FRA ME # re mains tri- state d by the Intel® 6300ESB ICH
until driv en by an Init ia tor.
PXIRDY# I/O
Initiator Ready: PXIRDY # indi cates the Intel® 6300ESB ICH's
ability, as an Initiator, to complete the current data phase of the
tra nsacti on. It is used in conjuncti on with PX TRDY# . A data phase is
completed on any clock both PXIRDY# and PXTRDY# are sampled
asserted. During a write, PXIRDY# indicates the Intel® 6300ESB ICH
has valid data present on PXAD[31:0]. During a re ad, it indicates the
Intel® 6300ES B ICH is prepared to latch data. PX IRD Y# is an input to
the Intel® 6300ESB ICH when the Intel® 6300ESB ICH is the Target
and an output from the In tel® 6300ESB ICH when the Intel®
6300E SB ICH is an Initiator. PX IRD Y# remains tri-stated by the
Intel® 6300ESB ICH until d riven by an Initi ator.
PXTRDY# I/O
Target Ready: PXTRD Y# indic a te s the Inte l® 6300ESB ICH's ability
as a Targ e t to complete the curre nt d a ta phase of the transaction
PXTRDY# is use d in co n junction with IR DY#. A data phase is
completed when both PXTRDY# and PXIRDY # are sampled asserted.
During a read, PXTRDY# indicates that the Intel® 6300ES B ICH, as a
Target, has placed valid data on PXAD [31:0]. During a write ,
PXTRDY# indic a tes the Intel® 6300ESB ICH, as a Target is prepared
to latch data PXTRDY # is an input to the Intel® 6300 ESB ICH whe n
the Intel® 6300ESB ICH is the Initiator and an output from the Intel®
6300E SB ICH when the Inte l® 6300ES B ICH is a Ta rg e t. PXTRDY# is
tri-stated from the leading edge of PXPCIRST#. PXTRDY# remains
tri -stat ed by the Intel® 6300ESB ICH until driven by a targ et .
PXSTOP# I/O
Stop: PX S TOP# indicate s that the Intel® 6300ESB ICH , as a Target,
is requesting the Initiator to stop the current transaction. PXSTOP#
c a uses th e Intel® 6300ESB ICH, as an Initiator, to stop the current
tr ansaction. PXSTOP# is an output when the Intel® 6300ESB ICH is a
Target and an input when the Intel® 6300 ESB ICH is an Initiator.
PXSTOP# is tri-sta te d from the leading edge of PXPCIRST#.
PXSTOP# remains tri-stated until driven by the Inte l® 6300 ESB ICH.
PXPAR I/O
Calculated/Checked Parit y: PXPAR uses “even” parity calc ulate d
on 36 bits, PXAD [31:0] plus PXC/BE[3:0]#. “Even” parity means that
the Intel® 6300ESB ICH counts the number of “1”s within the 36 bits
plus PXPAR and the sum is always even. The Intel® 6300ESB ICH
al w ays c alculates PXPAR on 36 bits regardles s of t he valid byte
enables. The Intel® 6300ESB ICH generates PX PAR for address and
data phases and o nl y ensur es P XPAR t o be val id o ne P C I clo ck a fter
the corresponding address or data phase. The Intel® 6300ESB ICH
drives and tri-states PXPAR identically to the PXAD[31:0] lines except
that the In te l® 6300ES B ICH delays PAR by exactly one PXPCI clock.
PXPAR is an output during the address phase (delayed one clock) for
all Intel® 6300ESB ICH initiate d transactio ns. PX PAR is an output
during the data phase (delayed one clock) when the Intel® 6300ESB
ICH is the Initia tor of a PCI-X write transa ction, and when it is the
Target of a read transaction. The Intel® 6300ES B ICH checks parity
when it is the Target of a PC-X write transaction. When a parity error
is detected, the Inte l® 6300 ESB ICH will set the appropriate internal
status bits, and has the opti on to generate an NMI# or SMI#.
Table 6. PCI-X Interface Signals (Sheet 2 of 4)
Name Type Description
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
62 Order Number: 300641-004US
PXPERR# I/O
Pari ty Error: An external PCI-X device drives PXPERR # whe n it
rece ives da ta tha t has a p a rity error. The Intel® 6300ESB ICH drives
PXPERR# when it detec ts a parity error. The Int el® 6300ESB ICH may
either generate an NMI# or SMI# upon detecting a par ity error
(either det ect ed i nte rnally o r repor ted vi a the PXPER R# sig nal) when
serving as an initiator.
PXREQ[1:0]
#
PXREQ[2]#
/GPIO[0]
PXREQ[3]#
/ GPIO[1]
I
PCI -X R eq ue st s: Suppor ts up to four master s on t he PCI- X bus . The
Intel® 6300ESB ICH accepts four re q ue st inp uts, PXREQ[3:0]# into
its interna l b us arbite r. The Intel® 6300ES B ICH re quest input to the
arbiter is an internal signal.
NOTE: When oper ating in PCI 64 b/66MHz , o nly t wo ext ern al m asters
should be used,PXREQ0, PXREQ1.
PXREQ[2]# is muxed with GP IO[0]
PXREQ[3]# is muxed with GP IO[1]
PXGNT[1:0]
#
PXGNT[2]#
/
GPIO[16]
PXGNT[3]#
/
GPIO[17]
O
PCI-X Gra n ts: Supports up to 4 masters on th e PCI-X bus.
PXGN T[ 2]# is muxed with GPIO[16]
PXGN T[ 3]# is muxed with GPIO[17]
NOTE: When oper ating i n PCI 64 b/66 MHz, onl y tw o external masters
should b e used: PXG N T0, PXG NT1.
PXPCLKI I
PCI-X Clock In: This sign a l is conne cted to an ou tput of the low
skew PCI clock buffer tree(PXPCLKO [4]. It is used by the PLL to
synchronize the PCI clock driven from PX PCLKO[4] to the clock used
for the internal PCI-X logic.
PXPCLKO[4:
0] OPCI -X C l oc k Ou t pu t: 33/66 MHz clock for a PCI de vice. PXPCLKO[4]
is connecte d to the PXPCLKI input. In PCI 64/66 mode PXPCLKO(1:0)
are e ns ure d to be drive n.
PXPCICLK IPCI-X Clock: PXPCICLK is the clock f or the inte rnal PCI-X circuitry.
66Mhz primar y inp u t cloc k.
PXRCOMP I/O Impedance Compensati on: Used to determine the impe dance
betwee n the Inte l® 6300ES B ICH and the PCI-X slots.
RASERR# OD
RAS Error: Th is pi n i ndi cat es that a RAS er r or ha s be en logged. This
is an active low signal that is a logical OR of all the RAS error events.
If one of t hes e erro rs is ac ti ve, the pin is low. If no ne ar e activ e, th en
the pin is high.
PXPCIRST# O
PCI/PCI-X Reset: The Intel® 6300 ESB ICH ass e rts PXPCIRS T# to
re se t d e v i ces that reside on t he P C I -X bus. The In t e l® 6300ESB ICH
as se rts P XPC IR S T# du ring power-up an d when S/W initiates a hard
rese t seq uen ce throug h the RC (CF9h) re giste r. T he Intel® 6300ESB
ICH driv es PXPCIRST# inactive a minimum of 1 ms after PWROK is
driv en active. The Intel® 6300ESB ICH drive s PXPCIRS T # activ e a
minimum of 1 ms when initiated through the RC (CF9h) register.
NOTE: PXPCIRST# is in the Resume power plane . This sig na l also
causes the legacy PCI bus and external PCI-X bus to reset
PXPLOCK# I/O
PCI-X Loc k: Indicates an exclu sive bus op e ratio n an d may re quire
multiple transacti ons to co mp le te . The Intel® 6 300ES B ICH asserts
PXPLOCK# when it performs exclusive transactions on the PCI-X b us.
PLOCK # is ignored when PCI -X mas t er s are grant ed the bus.
The I n t e l ® 6300ESB ICH do es not propagat e locked tr an sact io n
upstream.
Table 6. PCI-X Interface Signals (Sheet 3 of 4)
Name Type Description
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 63
3—Intel® 6300ESB ICH
PXSERR# I/OD
System E rror: PXSERR# may be pulsed active by any PC-X device
that detects a sy st e m error con d ition exce p t In tel® 6300ESB ICH.
The I n t el® 6300ESB ICH sam ples PXSERR# as an input and
conditionally fo rwards it to the Hub Inter face. Upon samp lin g
PXSERR# activ e , the Intel® 6300ESB ICH may be programm ed to
generate an NMI or SMI#.
PME# I/OD
PCI Power Ma na gem en t E ven t: PCI-X peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion may
also be enabled to generate a SCI from the S0 state. In some cases
the Intel® 6300ESB ICH may drive PME# activ e due to an inte rnal
wak e event. T he Intel® 6300ES B ICH will not drive PME# high, but it
will be pulled up to VccS us3_3 by an inte rna l p ull-u p re sistor.
NOTE: PM E# is in the Resume powe r plane and has an inte rna l p u ll-
up re sistor.
PME# co n trol log ic is in the prim ary PCI bus logic and not th e PCI-X
bridge
PXM66EN I
66MH z E nable : This in put signal from the PCI-X Bu s indicates th e
speed o f the P CI -X Bus. When i t i s hig h, t he Bu s speed i s 66 MHz and
when it is low, the bu s sp e e d is 33 M Hz. This signal will be used to
generate appropriate clock (33 or 66MHz) on the PCI- X Bus.
PXPCIXCAP IPCI-X Capable: Indicates wh eth er al l devic es on t he P CI -X bus are
PCI-X de vices, so that the Intel® 6300ESB ICH may switch into PCI-X
mode
PXPAR64 I/O
PCI-X interface u pper 32-bits parity : This carries the even parity
of the 36 bits of PXAD[ 63:32] and PXC/BE#[7 :4] fo r bo th address
and dat a phases .
When not driven, PXP AR64 is pulle d up to a valid logic level through
external re sis tors
PXREQ64# I/O
PCI- X int erf ace reque st 6 4- bit transf er : This is asserted by the
initiato r to in d ica te that the initia tor is requ e sting a 64-bit data
tra nsfe r. It has the same timing as PX FRA ME#. W he n the Intel®
6300ES B ICH is the initiator, this sig nal is an output. When the Intel®
6300E SB ICH is the targ e t this s ign al is an inpu t
PXACK64# I/O
PCI-X interface acknowledge 64-bit transfer: This is asserted by
the target only whe n PXREQ64# is asserted by the initiator, to
indicate the ta rg e t’s ability to tran sf e r data using 64 bits. It ha s the
same timing as PXDEVSEL#
PCIXSBRST
#OPCI-X Secondary Bus Reset: The I n t e l ® 6300ES B ICH asserts
PCIXSB RS T# to reset devices that re side on the PCI-X bus. The
Intel® 6300ESB ICH asserts PCIXSBRST# when the PXPCIRST# pin is
asserted or when SBR bit is set.
Table 6. PCI-X Interface Signals (Sheet 4 of 4)
Name Type Description
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
64 Order Number: 300641-004US
3.5 SATA Interface
3.6 IDE Interface
Table 7. SATA Interface Signals
Name Type Description
SATA0TXP
SATA0TXN OSerial ATA 0 Differential Transmit Pair: Outbound high speed
diffe rential signals to Port 0.
SATA0RXP
SATA0RXN ISerial ATA 0 Differential Receive Pair: Inb ound high spe ed
differential signals from Port 0.
SATA1TXP
SATA1TXN OSerial ATA 1 Differential Transmit Pair: Outbound high speed
diffe rential signals to Port 1.
SATA1RXP
SATA1RXN ISerial ATA 1 Differential Receive Pair: Inb ound high spe ed
differential signals from Port 1.
SATACLKP,
SATACLKN iDiffe rential SATA Clock: 100 MH z clo ck input from the Clock
Generator
SATALED# OD Serial AT A LED#: Output indicate s Se ria l ATA Dr ive activ ity whe n it
is dri ven low
SATARBIASP
SATARBIASN ISerial ATA Resist or B ia s: Analog connection point for a externa l
resistor to ground .
Table 8. IDE Interface Signals (Sheet 1 of 2)
Name Type Description
PDCS1#,
SDCS1# OPrimar y an d Second ar y ID E Device Chip Selec ts for 100 Range:
For ATA command register block. This output signal is connected to
the correspon d in g sig n al on th e pr ima ry or second a ry IDE con nector.
PDCS3#,
SDCS3# OPrimary and Seco ndary IDE Device Chip Select for 300 Range:
For ATA control re gis ter b lock . This output signal is conne cte d to the
co rre sp on d in g sig n a l on t he primary or seconda ry I DE connector.
PDA[2:0],
SDA[2:0] O
P r imary an d S eco nd ary I D E Device Address: Th ese ou t put
signals are connected to the corresponding signals on the primary or
second ary IDE conn ectors. They are used to indica te wh ich byt e in
either the ATA command block or control block is being addressed.
PDD[15:0],
SDD[15:0] I/O
P r imary an d S eco nd ary I D E Device Data: Th e se signa ls dire ct ly
drive the corresponding signals on the primary or secondary IDE
connector. There is a weak internal pull-down resistor on PDD[7] and
SDD[7].
PDDREQ,
SDDREQ I
P r imary an d S eco nd ary I D E Device DMA Reques t: These input
signals are directly driven fr om the DRQ signals on the primary or
secondary IDE connector. It is asserted by the IDE device to request a
data transfer, and used in conjunc tion with th e PCI bus master ID E
function and are no t associated with any AT compatible DMA channel.
There is a weak internal pull-down resistor on these signals.
NOTES:
1. The IDE signals are 5V tolerant.
2.The IDE signals have integrated series terminating resistors.
3. All signal s may be tri-stated or drive n low for mobile swap b ays.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 65
3—Intel® 6300ESB ICH
PDDACK#,
SDDACK# O
Pri mar y and Seco nd ar y IDE Device DM A Acknowledge: Thes e
signal s dire ctl y dr i ve th e DAK# sign al s on the pri ma ry and secon dar y
IDE conn ectors. Each is asserte d by the Intel® 6300ESB ICH to
in dicate to IDE DMA slave devices th at a given data transf er cycle
(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This
signal is used in conjunction with the PCI bus master IDE function and
are not associated with any AT-compatible DMA channel.
PDIOR# /
(PDWSTB /
PRDMARDY#)
SDIO R# /
(SDWSTB /
SRDMARDY#)
O
Primary and Secon dary Disk I/O Read (PIO and Non-Ultra
DMA): This is the command t o the IDE device that it may drive data
on to the P DD or S DD line s. D a ta is latched by the Intel® 6300ESB
ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE device is
selected eithe r by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the P DA or SDA lines, or the IDE
DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing to
dis k, the Intel® 6300ES B ICH dr ives valid data on risi ng and fal ling
edg e s of PDWST B or S DWSTB.
Primary and Secondary Disk DMA Ready (Ultra DMA Reads
from Disk): This is the DMA ready for re ads from disk. When reading
from disk, the Intel® 6300ESB ICH deasserts PRDMARDY# or
SRD MA RDY # to p a use bu rst d ata transf er s.
PDIOW# /
(PDSTOP)
SDIOW# /
(SDSTOP)
O
Primary and Secondary Dis k I/O Write (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may latch data
from the PDD or S DD line s. D ata is latched by the IDE device on the
deass e rtion ed ge of PDIO W # or S DIO W# . The IDE dev ice is selected
eithe r by the ATA regist er file ch ip selects (PDCS 1 # or S DCS1#,
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
acknowledge (PDDAK # or SDDAK#).
Pri mar y and Seco ndar y Disk Stop (Ultra DM A ): the Intel®
6300ESB ICH asserts this signa l to term ina te a bur st.
PIORDY /
(PD RSTB /
PWDMARDY#)
SIORDY /
(SDRSTB /
SWDMARDY#)
I
Primary and Secon dary I/O Channel Ready (PIO): This signal
will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or
SDIOW# on writes) longer than the minimum width. It adds wait
state s to PIO transf ers.
Primary and Secondary Dis k Read Strobe (Ultra DMA Reads
from Disk): When reading from disk, the Intel® 6300ES B ICH
latches data on rising and falling edges of th is signal from the disk.
Pri mar y and Seco ndar y Disk DMA Ready (Ultr a DMA Writ es to
Disk): When writing to disk, this is deass erted by t he disk to pause
burst data transfers .
Table 8. IDE Interface Si gnals (Sheet 2 of 2)
Name Type Description
NOTES:
1. The IDE signals are 5V tolerant.
2. The IDE signa ls h a ve in te grated series terminating resi stors.
3. All sign als ma y be tri-stated or driven low for m ob ile swa p bays .
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
66 Order Number: 300641-004US
3.7 LPC I/ F
3.8 Interrupt Interface
Table 9. LPC Interface Signals
Name Typ
eDescription
LAD[3:0]
/ FWH[3:0] I/O LPC Mu ltiplexed C o mm an d, A dd r es s, Da t a: Internal pull-ups are
provided.
LFRAME#
/
FWH[4] I/O LPC Frame: Indicates the start of an LPC cycle, or an abort.
LDRQ[1:0
]# ILPC Serial DMA/Master Request Inputs: U s ed by LPC devi c es , s uch as
Sup er I/O chip s, to reque st DMA or b us ma ster access.
NOTE: All L P C/FW H signals a re in the core well
Table 10. Interrupt Signals (Sheet 1 of 2)
Name Type Description
SERIRQ I/O Serial I n terrupt Re quest: This pin implemen ts the se ria l interrup t
protocol.
PIRQ[D:A]# I
PCI Int err upt Re ques ts: In No n-APIC Mode the PIRQx# signals
may be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
se parate Route Co n trol Regis te r.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fas hion :
P IRQ[A ]# IRQ16
P IRQ[B ]# IRQ17
PIRQ[C]# IRQ18
P IRQ[D ]# IRQ19
This frees the legacy i nterrupts. These signals are 5V tolerant.
NOTE: The I nte rrup t sig na ls ar e 5V tolera nt e xcep t f or PXIRQ [3:0]# / GPIO[36:33]
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 67
3—Intel® 6300ESB ICH
3. 9 USB Interf ace
PIRQ[H:E]# /
GPIO[5:2] I
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
may be routed to inte rrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
describe d in the Interrupt Steerin g sec tion . Ea ch PIRQx# line ha s a
separat e Route Control Register. These signals are 5 V tolerant.
In APIC mode, these signals are connected to the internal I/O APIC
in the fol lowin g f a shion:
PIRQ[E] IRQ[20]
PIRQ[F] IRQ[21]
PIRQ[G] IRQ[22]
PIRQ[H] IRQ[23]
NOTE: When not connected as interrupts on the board, these pins
must be programmed as GPI. This ensures proper interrupt
delivery from internal sources regardless of the board
termi na tion on these p ins.
IRQ[14-15] I
Int err upt Reques t 1 4–15: T hese interrup t inputs are connec ted to
the IDE dr ives. IRQ 14 is used by the dr ives conn ected to the Pri mar y
controlle r and IRQ15 is used by the drive s connected to the
Secondary controller. These signals are 5 V tolerant.
PXIRQ[3:0]#
/
GPIO[36:33] I
PCI- X Bus Interru pt Requ est: The PIRQ# lines fr om PCI-X
interru pts , IN TA , IN TB, IN TC, INTD], may be route d to the se
interru pt lines. PXIRQ[3:0 ]# are conne ct ed to an I/Ox APIC that
resides on the PC I-X bus.
Table 11. USB Interface Signals
Name Type Description
USBP0P,
USBP0N,
USBP1P,
USBP1N,
USBP2P,
USBP2N,
USBP3P,
USBP3N
I/O
Universal Serial Bus Port 3:0 Differentials: Bus Data/
Addres s /Com mand Bu s.
NOTE: No external resistors are required on these signals. The
Intel® 6300ESB ICH inte g rate s 15 kΩ pull-downs and
provid e s an outp u t d river impedanc e of 45 Ω wh ich
requ ires no externa l se rie s re sistor
OC[3:0]# IOvercu rrent In dicat ors: These signals set corresponding bits in
th e USB controllers to indicate tha t a n overcurrent condition ha s
occurred.
USBRBIAS OUSB Resistor Bias: Analog connection point for an external
res i stor to grou nd. USBRBIAS should be conne cted to
USB RBIAS # a s close to th e resisto r a s po ssible.
USBRBIAS# IUSB Resist or B ia s C om plement : Anal og connection point for
an ex terna l re sis tor to g round. USBRBIA S # should be connected
to USBRBIAS as close to the resistor as possible.
NOTES:
1. The USB sig n als a re a ll in the RE S UM E we ll.
2. Since OC[3:0]# are in the 5 V tolerant resume well, the external biasing resistors are not
required.
3. All 4 ports support both USB1.0 and USB2.0 signaling.
Table 10. Interrupt Signals (Sheet 2 of 2)
Name Type Description
NOTE: The Interrupt signals are 5V tolerant except for PXIRQ [3:0]# / GPIO[36:33]
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
68 Order Number: 300641-004US
3.10 Power Managem ent Interfa ce
Table 12. P ower Management Interface Signals (Sheet 1 of 2)
Name Type Description
THRM# IThermal Alarm: Ac t ive l o w signa l ge ne r at ed by external h ard w are to
start the Hard ware clock throttling mode . M ay also gene rate an SMI#
or SCI.
THRMTRIP
#IT h ermal Trip: When low, indic ate s that a the rmal trip from the
processor occurre d , a nd corrective acti on will be taken. This input
buffer has the sa me cha rac teristics a s th e F E RR # input buf f er.
SLP_S3# OS3 Sleep Control: Powe r plane control. Shuts off powe r to all non-
criti ca l sy st e ms when in th e S3 (S u spend To RA M) sta te.
SLP_S4# OS4 Sleep Control: Power pla ne control. Shu ts p owe r to n on-critica l
systems when in the S4 (Suspend to Disk ) or S5 (Soft Off) state.
SLP_S5# OS5 Sleep Control: P ower plane control.
The signal is used to shut power off to all non-critical systems when in
the S5 (Soft Off) state.
PWROK I
Pow er OK : When asserted, PWROK is an indic ation to the Inte l®
6300ESB ICH that core power and PCICLK have been stable for at
least 1 ms . PWR OK may be dr iven asy nch ronously. When PW ROK is
low, the Intel® 6300ESB ICH asserts PXPCIRST#.
Traditional designs have a reset button logically ORed with the PWROK
signal from the power supply and the processor’s voltage regulator
module. W he n this is done with the Intel® 6300ESB ICH , the
PWROK_FL R b it will be se t. The Inte l® 6300ESB ICH tre ats this
internally as though the RSMRST# signal had gone active . However, it
is not treated as a ful l pow er failure. When PWRO K goes in activ e and
then active (but RSMRS T# stays high), the Intel® 6300ESB ICH wi ll
reboot (regardless of the state of the AFTERG3 bit). When RSMRST#
also g oes low before PWROK goes high, then this is a full power failure
and the reboot policy is controlled by the AFTERG3 bit. PWROK must
deassert for a minimum of 100 µse cond s (s imulation and analysis
shows 3 RT C clock periods are req uired) in order to fully reset the core
power well and properly generate the PXPCIRST# output.
PWRBTN# I
Power Button: The Power Button will cause SMI# or SCI to ind icate a
syst em request to go to a sleep state. When th e sys tem is already in a
sleep stat e , this signal will ca use a wake e vent. W h e n PW RBTN# is
pressed for more t ha n 4 se conds, t his w ill c au se a n u ncondit ion al
trans ition (power butt on overrid e ) to the S 5 state with only the
PWRBTN# available as a wake event. Override will occur even when
the system is in the S1-S4 s tates. This signal has an internal pull-up
resistor.
RI# IRing Indi cate: From the modem interface. May be e nabled as a w ake
event, an d th is is p re se rved across power failures.
SYS_RESET
#ISystem Reset: Thi s pin forc e s an inte rn al re se t a f te r b ei n g
debounced.
RSMRST# IResume Well Reset: Used fo r reset t ing th e resum e power pl a n e
logic. An e xternal RC circuit is required to ensure that the resume well
power is valid pr ior to RS M RS T# going high.
NOTE: The se sig n als ar e all in the RESUME well, exce p t THRM # which is in the core well;
PWRO K an d RSMRS T# which are in the RTC well.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 69
3—Intel® 6300ESB ICH
3.11 CPU Interface
SUS_STAT#
/ LPCPD # O
Suspen d St atus: This signal is asserted by the Intel® 6300ESB ICH
to indicate that the system will be entering a low powe r state soon.
This ma y be mon itored by devices w ith me mory tha t n eed to switch
from nor mal r efres h to suspend r efr es h mode. I t may also be used by
other peripherals as an indication that they should isolate their
out put s that ma y be going to po we re d-of f planes. T hi s sig nal i s call ed
LPCPD# on the LPC I/F.
SUSCLK OSu spend Clock: Output of the RTC generator circuit (32.768 KHz).
SUSCLK will have a duty cy cle tha t ma y be as low a s 30% or as h igh
as 70%.
VRMPWRG
DIVoltage Regulator Power Good: Not implem e nte d in the Intel®
6300ES B ICH. Pull this inpu t hig h to Vcc.
Table 13. CPU Interface Signals (Sheet 1 of 2)
Name Type Description
A20M# O
Mask A20 : A20M# will go activ e base d on either se tting th e
appropriate bit in the Port 92h register, or based on the A20GATE
inpu t bei n g acti ve.
Speed Strap: During the reset sequen ce, the Inte l® 6300ESB ICH
drives A20M# high when the corresponding bit is set in the
FREQ_ST RP regi ster.
CPUSLP# O
CPU Sleep: Th is si gnal puts th e proc e ssor in to a state that saves
substantial pow er compared to Stop-Grant state. However, during
that time, no sno op s occ u r. T he Intel® 6300ESB ICH may optionally
assert the CPUSLP# signal when going to the S1 state. It will go
active for all other sleep states.
FERR# I
Numeric Co proce s s or Error: This sign al is tie d to the coprocessor
error signal on th e proces sor. F ERR # is onl y us ed when th e In tel®
6300ESB ICH cop rocessor error re p orting function is enab led in the
General Control Register (D31:F0:Offse t D0.bit 5). When FERR# is
asserted, the Intel® 6300ES B ICH generate s an internal IRQ13 to its
interrupt controller unit . It is also used to g a te the IGNN E# sig nal to
ensure that IGNNE# is not asserted to the processor unless FERR# is
active . FERR# requires an external weak pull -up to ensure a high leve l
when the copr oc esso r error functi o n is disable d.
FERR# may optionally be used in some states for notification by th e
processor of pending interrupt events.
NOTES:
1. The CPU I/F signals (except RCIN#, A20GA T E, and FERR#) are on a separate power well. This
saves the e xternal pull-up re sistors that we re n e e ded on previous ch ips e t s.
2. RCIN# and A20GATE, and FERR# are on in the Core power well.
Table 12. Power Management Interface Signals (Sheet 2 of 2)
Name Type Description
NOTE: These signals are all in the RESUME well, except THRM# which is in the core well;
PWROK and RSMRST# which are in th e RTC well .
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
70 Order Number: 300641-004US
IGNNE# O
Ignore Numeric Error: This signal is connected to the ignore error
pin on the CPU. IGNNE# is only used when the Intel® 6300ESB ICH
cop roce ssor error rep ortin g function is enabl ed in the General Con trol
Register (D31:F0:Offset D0.bit 5). When FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h)
causes the IGNNE# to be asserted. IGNNE# remains asserted until
FER R# is neg ate d. If FERR# is not asserted when the Coprocessor
Err or Reg ister is written, the IGNNE# signal is not as se rt e d .
INIT# O
Initialization: INIT# is asserted by the Intel® 6300ESB ICH for 16
PCI clocks to res e t the proc e sso r. Th e Intel ® 6300ESB ICH may be
conf igu re d to support CPU BIST. In that ca se, IN IT# wil l be active
wh en PXPCIR ST # is ac tive.
INTR OCPU Interrupt: INTR is asserted by the Intel® 6300ESB ICH to signal
the processor that an inter rup t request is pending and needs to be
serv iced. It is an asynchronous output and normally driven low.
NMI O
Non-Maskable Interrupt: NMI is used to force a non-Maskable
inter rupt to the proce ss or. The Intel® 6300ESB ICH may generate an
NMI when ei ther SE RR# or IOCHK# is asserted. The proc essor de tects
an NMI when it detects a rising edge on NMI. NMI is reset by setting
the correspond ing NMI sourc e enab le /d isa b le b it in th e NMI Sta tus
and Control Register.
SMI# OSystem Ma nage ment Int err upt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the Intel® 6300 ESB ICH in
res po n se to one of many e na b le d hard wa re or software events.
STPCLK# O
Stop Clock Request: STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the Intel® 6300ESB ICH in response to
on e of many h ard war e or softwa re eve nts. W he n the pr oce ss or
sa mp le s S TPCL K # asserted , it re sp on d s b y sto ppin g its int er n al clock.
Th is signal will n ot be conne cte d to the processo r in iA64 syste ms,
sin ce th e processor h a s no corresp on d in g in p u t signal.
RCIN# I
Keyb o ard C o ntroller Reset CPU: The keyb oa rd controller may
gener ate INIT# to the processor. This saves the external OR gate with
the Intel® 6300ESB ICH’s other sources of INIT#. W he n the Intel®
6300ESB ICH detects the assertion of this signal, INIT# is generated
for 16 PC I clocks.
Note that the Inte l® 6300ESB ICH will ignore RCIN # assertion during
transitions to the S1, S3, S4 and S5 state s.
A20GATE IA20 Gate: From the keyboard controller. Acts as an alternative
me thod to force th e A 2 0M# signa l act i v e. Saves the exte rnal OR gat e
needed with va rious other chips ets.
Table 13. CPU Int erface Signals (Sheet 2 of 2)
Name Type Description
NOTES:
1. The CPU I/F s ig nals (except RCIN#, A 20GATE, and FERR#) are on a separate power well. This
save s th e exte rn a l pull-u p resistors t ha t were nee ded on pr evious chip se ts.
2. RCIN# and A20GATE, and FERR# are on in the Core power well.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 71
3—Intel® 6300ESB ICH
3. 12 SMBus In terface
3. 13 System Ma nagement Interface
3.14 Real Time Cl o ck Interfa ce
Ta ble 14 . S M Bu s In t e rf a ce Si gn als
Name Type Description
SMBDATA I/OD SMBus Dat a: External p u ll-up is re quired.
SMBCLK I/OD SMBus Clock: External pull-up is required.
SMBALERT
#/ GPIO[11] ISMBus Aler t: This signal is used to wake the system or generate SMI#.
When not used for SMBALERT#, it may be used as a GPIO (GPIO[11]).
NOTE: The S M B us I/F sig n als ar e all in the RES UM E we ll.
Table 15. System Management Interface Signals
Name Type Description
INTRUDER
#I
Intruder Detect: Det e cts if the sy ste m case ha s b een op ened . M ay be
set to disable the system when box is detected open.
This signal’s status is readable, so it may be used like a GPI when the
In trude r switch is not nee d ed.
SMLINK[1:
0] I/OD
System Management Li nk: SMBus link to optiona l external system
ma na g e me n t ASIC or LAN Con troller. Exte rn al p u ll-up s a re re q u ire d .
No te tha t SML IN K[0] corresponds to a SMBus Clo ck signa l, an d
SMLINK[1 ] corresp onds to a SM B u s D a t a signal.
NOTE: IN TRUDER# is in the RTC we ll. The S M LINK signal is in the RESU M E we ll.
Table 16. Real Time Clock Interface
Name Type Description
RTCX1 Special Crystal In put 1: Connected to the 32.768 KH z crys tal. W he n no
exte rnal crystal is used, then RTCX1 may be driven with the d esire d
clo ck rate.
RTCX2 Special Crystal In put 2: Connected to the 32.768 KH z crys tal. W he n no
exte rnal crystal is used, then RTCX2 should b e left fl oating .
Vbias IBias Voltage for Oscillator: Sets the proper biasing for the oscillator.
Expected voltage 2 00 mV.
NOTE: An external Crystal/Resistor/Capacitor circuit is re q u ire d for pro per op e ration of the
oscillator.
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
72 Order Number: 300641-004US
3.15 Other Cl o cks
3.1 6 Miscellaneous Signals
Table 17. Other Clocks
Name Type Description
CLK14 IOscillator Cloc k: Used f or 8254 timers. Runs at 14.31818 MHz. This
clock is permitted to stop during S3 (or lower) s tates in desktop
con fi gurations or S1 (or lower) state s in mobile con f ig u ratio ns.
CLK48 I48 MHz Clock: Used to run t he U SB controllers. Runs at 48 MHz. This
clock is permitted to stop during S3 (or lower) s tates in desktop
con fi gurations or S1 (or lower) state s in mobile con f ig u ratio ns.
HICLK I66 MHz Clock: Used to run the H ub In terf a ce. Runs at 66 M Hz. T his
clock is permitted to stop during S3 (or lower) s tates in desktop
con fi gurations or S1 (or lower) state s in mobile con f ig u ratio ns.
Table 18. Miscellaneous Signals
Name Typ
eDescription
SPKR O
Speaker: The SPKR sig na l is the output of counte r 2 and is inte rnally
ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal
drives a n exte rn al speaker drive r dev ice , which in turn drives the
system sp e a ker. Upon PXPCIRS T#, its outp u t st at e is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional
str a p. See Section 3.21.1, “Functional Straps for mo re deta ils.
There is a weak integrated pull-do w n resist or on SPKR pin .
RTCRST# I
RTC Res e t: Wh en asserted, this sign al re sets registe r b its in the RTC
well and se ts the RTC_PWR _S TS bit (bit 2 in G EN _PM CON3 registe r).
NOTES:
1. Clearing CMOS in an Intel® 6300E SB ICH-b ase d p latform may be
done by using a jum per on RTCRS T# or GPI, or us ing SAFEMOD E
strap. Imp le mentations should not attempt to clear CMOS by using a
jump er to pull VccRTC low.
2. Unless entering the XOR Cha in Tes t Mod e , the RTCRS T# inpu t must
always be high when all other RTC power planes are on
WDT_TOUT#
/ GP I O[ 32] O
Watch dog Timer Timeout: Dr iv e n acti v e to i ndicate the sec ond stage
of the WDT has overflowed. This signal will toggl e states for each
overflow in periodic mode. In non-periodic mode, t his signal will go
act ive low an d re ma in in this st ate u ntil a sy ste m reset or po we r cyc le .
This sig n al is mu xed with G PIO[32].
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 73
3—Intel® 6300ESB ICH
3. 17 AC’97 Link
3.18 Universal Asyn chron ous Receive and
Transmit (UART0,1)
Tab l e 19 . AC ’9 7 Lin k Sign a ls
Name Type Description
AC_RST# OAC 97 R e set: Mas te r H/W re set to e xternal Code c(s).
AC_SYNC OAC’ 97 Sync: 48 KHz fixed rate s ample sync to the Codec(s).
AC_BIT_CLK IAC’97 Bi t Clock: 12.288 MHz serial data clock generate d by the
external Codec(s). T his signal has an i ntegrated p ull-down resistor 3.
AC_SDOUT OAC’97 Serial Data Out: Serial TDM data output to the Codec(s).
AC_SDIN[2:0] IAC’97 Serial Da ta In 2:0: Serial TDM da ta input fro m the three
Codec(s). Integrated pull-dow n resistors, which are alw ays enabled.
NOTES:
1. These signal s are in the RESUME w ell, e xcept A C_S YNC, AC_BIT _CLK, and AC_SDATA_OUT,
which ar e in the core well.
2. See S ecti on 4.2, “I nteg r at ed Pu l l-Ups and Pu ll-Down s for de tails ab out whe n the integra ted
pull-down resistors are enabled on AC _S YNC, AC_B IT_CLK, and AC_SD ATA_OUT.
3. An integrate d pull-down resistor on AC_B IT_CLK is enabled when eithe r:
- The ACLINK Shutoff bit in the AC’97 Global Control Register (See Section 13.2.8,
“GLOB_CN TGlob al Control Register) is set to ‘1’, or
- Both Funct ion 5 and Function 6 of D evic e 31 are disabled. Other w ise, the in tegr at ed pul l-
down resistor is d isa b led.
Table 20. Universal Asynchronous Receive and Transmit (UART0, 1) (Sheet 1 of
2)
Signal Name Type Description
UART_CLK IInput clock to the SIU. This clock is passed to the baud clock
gen eratio n logi c of eac h UART in the SIU.
SIU0_RXD
SIU1_RXD IS ERIAL INPUTs for UART0 and UART1: Serial data input from
device pin to the receive port.
SIU0_TXD
SIU1_TXD OSERIAL OUTPUT for UART0, 1: S e ria l d ata output to the
communication peripheral/modem or data set. Upon reset, the TXD
pins will be se t to MARKING cond ition (logic ‘1’ state ).
SIU0_CTS
SIU1_CTS I
CLEAR TO SEND: A ctiv e lo w, th is pin ind icate s that data may be
exchanged betw een the Intel® 6300ESB ICH and external interfac e.
These pins have no effect on the transmitter.
NOTE: These pins could be used as Modem S tatus Input whose
co nd ition m ay be test ed by th e process or by readi ng bit 4 (CT S)
of the Modem Status register (MSR). Bit 4 is the complement of
the CTS# signal. Bit 0 (DCTS) of the MSR indicates whether the
CT S# input has changed state sin ce the previo us reading of th e
MSR. When the CTS bit of the MSR changes state, an interrupt
is generated when the Modem Status Interrupt is enabled.
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
74 Order Number: 300641-004US
3.19 General P urp o se I/O
Note: Alternative signal definition is for pin strap selected feature muxing. GPIOs muxing is
based on GPIO configurations.
SIU0_DSR
SIU1_DSR I
DATA SET READY for UART 0, 1: Active low, th is p in ind ica te s th at
the external ag e nt is re ad y to communicate wit h the Intel® 6300ESB
ICH UARTS. These pins have no effect on the transmitter.
NOTE: These pins could be used as Modem Status Input whose
condition may be tested by the processor by reading bit 5
(DSR) of the Modem Status register. Bit 5 is the comple ment of
the DSR# signal. Bit 1 (DDSR) of the Modem status register
(MS R) in dicates wh e th e r the DS R # in p u t h a s cha n g ed state
sin c e th e pr evio us r eadi ng o f th e MSR . When t he DSR bi t o f th e
MSR changes stat e, an inte rru p t is generated when th e Mode m
Status Interrupt is enabled.
SIU0_DCD
SIU1_DCD I
DA TA CARRI ER DE TECT f or UA R T 0, 1: Active low, this pin indicates
that dat a carrier has been detected by the external agent.
NOTE: These pins are Modem Status Input whose condition may be
tested by the processor by reading bit 7 (DCD) of the Modem
Status register (MSR). Bit 7 is the complement of the DCD#
signal. Bit 3 (DDCD ) of the MSR indic a tes whe ther the DC D#
inp ut has changed state s ince th e previ ou s read ing of the MSR.
When the DCD bit of the M SR cha ng e s state, a n inte rrupt is
generated when the Mod e m S tatus Inter rup t is ena bled.
SIU0_RI#
SIU1_RI# I
RING INDICATOR for UART 0, 1: Active low, this pin indicate s that a
telephone ringing si gnal has been received by the external agent.
NOTE: These pins are Modem Status Input whose condition may be
tested by the processor by reading bit 6 (RI) of the Modem
Status register (MSR). Bit 6 is the complement of the RI#
signal. Bit 2 (TERI) of the MS R indicates whe ther the RI# input
has tran sitioned back to an ina ctive state . W he n the RI bit of
the MSR changes from a 1 to 0, an interrupt is generated when
the Modem Status Interrupt is enab le d .
SIU0_DTR#
SIU1_DTR# O
DATA TERMINA L READY for UART 0, 1: When low these pins
informs the modem or data set that the Intel® 6300ESB ICH UART 0, 1
are ready to establish a communication link. The DTR#x(x=0,1) output
signals may be set to an active low by programming the DTRx (x-0,1)
(bit0) of the Modem control register to a logic ‘1. A Reset operation
sets this sign al to its inactive state (logic ‘1’). LOOP m ode op e ration
holds this signa l in it s ina ctive state.
SIU0_RTS#
SIU1_RTS# O
REQUE ST TO SEND fo r UART 0, 1: When low these pins informs the
modem or data set that the Intel® 6300ESB ICH UART 0, 1are ready to
establish a communi cation link. The RTS#x, where x = 0,1, ou tpu t
signals may be set to an active low by programming the RTS#x (bit1)
of the Mod e m control reg ist e r to a logic ‘1’. A Reset operation se ts this
signal to its ina ctive stat e (lo gi c ‘1’ ). LOOP mod e ope rat ion holds this
signal in its ina ctive stat e.
Table 20. Universal Asynchr onous Receive and Transmit (UART0, 1) (Sheet 2 of
2)
Signal Name T y pe Descr iptio n
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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3—Intel® 6300ESB ICH
Tab l e 21 . G en e ral Pu r pos e I/O Sig n als (She e t 1 of 2)
Signal Name Type Description
GPIO[0]/
PXREQ[2]# IFixed as Inpu t only. M ain power well. May ins te ad be use d as
PXREQ[2]#.
GPIO[1]/
PXREQ[3]# IFixed a s Inp ut only. M ain pow e r we ll. Ma y ins te ad be use d as
PXREQ[3]#.
GPIO[5:2]/
PIRQ[H:E]# IFixed as Inp ut only. M ain pow e r well. M a y ins te ad be use d as
PIRQ[H:E]#.
GPIO[6] IFixed as Inp ut only. M ain pow e r we ll. (3.3 V tole rant, not 5 V
tolerant)
GPIO[7] IFixed as Inp ut only. M ain pow e r we ll. (3.3 V tole rant, not 5 V
tolerant)
GPIO[8] IFixed as Input only. Resume power well. Unmuxed. The GPI_INV bit
cor respo ndin g to G P IO[8] mu st b e s et in ord er to achieve the cor rect
polarity in the General Pu rpose Event 0 Status Register.
GPIO[9:10] I R es er ved . These GPIO are not impl em ent ed.
GPIO[11] IFixed as Input o nly. Resume power well. May instead be used for
SMBAlert#.
GPIO[12:13] I Fixed a s Inp ut on ly. Resume p owe r we ll.
GPIO[14:15] I R es erved. These GP IO are not im plem ent ed.
GPIO[16] OFixed as Output only. M ain p owe r we ll. Ma y inste a d be use d as
PXGNT[2]#.
GPIO[17] OFixed as Output only. M ain p owe r we ll. Ma y inste a d be use d as
PXGNT[3]#.
GPIO[18] O Fixed as Outp ut only. M a in p owe r we ll.
GPIO[19] O Fixed as Outp ut only. M a in p owe r we ll.
GPIO[20] O Fixed as Outp ut only. M a in p owe r we ll.
GPIO[21] O Fixed as Outp ut only. M a in p owe r we ll.
GPIO[23] O Fixed as Outp ut only. M a in p owe r we ll.
GPIO[24] I/O May be input or output. R esume power we ll. Unmuxed.
GPIO[25] I/O May be input or output. R esume power we ll. Unmuxed.
GPIO[26] I/O Reserved. This GPIO is not implemented.
GPIO[27:28] I/O May be input or output. Resume power well. Unmuxed.
GPIO[29:31] O Res er ved. These GPIO are not implement ed.
GPIO[32] OFixed as Output only. Core p owe r we ll. May instead be u sed f or
WDT_TOUT#.
GPIO[33:36] I/O May be input or output. Core power well. May instead be used fo r
PXIRQ[0:3]#.
GPIO[37:39] I/O May be input or output. Core power well. GPIO[37,39] are unmuxed.
NOTES:
1. GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core we ll.
2. GPIO[8:15] and GPIO[24:31] are in the suspend we ll.
3. Core-well G PIO are 5 V to lerant, except for GPIO[ 7:6] and [32:43].
4. Resume-well GPIO are not 5 V tolerant.
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
76 Order Number: 300641-004US
3.20 Powe r and Gro un d
GPIO[40:43] I/O May be input or output. Core po we r we ll.
NOTE: T hese GP IOs have High Strength Outp ut Capability (for
drivin g LED s).
GPIO[44:55] I/O Reserved. These GPIO are not implemented.
GPIO[56:57] OD Output only. Resume and RTC power wells. Unmuxed.
GPIO[58:63] I/O Reserved. These GPIO are not implemented.
Table 22. Power and Ground Signals (Sheet 1 of 2)
Name Description
VCC3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,
or S5 state s.
VCC1_5 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or
S5 states.
VCCHI 1.5 V supp ly for Hub Inte rf ace 1.5 log ic.
This power may be shut off in S3 , S4, and S5 states.
V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off
in S3, S4, S5 or G3 states.
VCCREF 3.3V refere nce vol ta ge f or PCI-X inputs
VCCA 1.5V supply for Hub Interface PL L.
This power may be shut off in S3 , S4, and S5 states.
HIREF Analog Input. Expected voltages are 350 mV for the Hub Interface 1.5
(Enhanced Hub Inte rf ace ) Parallel Termination.
This p o we r is shut off in S3 , S4 , S5 and G3 states.
VccSus3_3 3.3 V supply for resume well I/O buffers. This power is not expected to be
shut off unless the system is unplugged in desktop config urations.
VCCSUS1_5 1.5 V supply for resume well logic. This power is not expected to be shut off
unless the syste m is u np lu g g ed in desktop con f ig u ration s.
V5REF_Sus Re f e re nce f or 5 V tolerance on res ume we ll in p uts. This power is not
expected to be shut off unless the system is unplugged i n desktop
conf igurations.
VCCRTC
3.3 V (may dro p to 2. 0 V mi n. in G3 st ate ) suppl y for the RTC well. This
power is no t expe cted to be shut off unle ss the RTC battery is removed or
completely drained.
NOTE: Imp le mentations should not a ttempt to clear CMOS by using a
jumper to pull VccRTC low. Clearing CMOS in an Intel® 6300ESB
ICH- ba se d pla t for m ma y be d one by using a jumper on R TCRST# or
GPI, or using SAFEMODE s trap.
Table 21. General Purpose I/O Signals (Sheet 2 of 2)
Signal Name Type Descri ption
NOTES:
1. GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
2. GPIO[8:15] and GPIO[24:31] are in the suspend wel l.
3. C ore -we ll G PIO a re 5 V tolerant, exc ept f or G PIO[7:6] and [32:43].
4. Resume -well G P IO are not 5 V tole rant .
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 77
3—Intel® 6300ESB ICH
3. 21 Pin Straps
3.21 .1 Functional Straps
The following signals are used for static configuration. They are sampled at various
reset points to select configurations, and then revert later to their standard usage. To
invoke the asso ciated mode, the signal should be driven at least four PCI clocks prior to
the time it is sampled.
Note: The Intel® 6300 ESB ICH chan ges the pola rit y of th e “no reboot” st ra p in ord er t o av oid
an audible click due to the pull-up on the SPKR output.
VccPLL 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or
G3 states.
V_CPU_IO Powered by the same supply as the CPU I/O voltage. This supply is used to
drive t he CPU I/F outputs.
0.8 to 1.75 V. The power will be shut in S3, S4, and S5 state s.
Vss Shared Grounds.
Table 22. Power and Ground Signals (Sheet 2 of 2)
Name Description
Table 23. Functional Strap Definitions
Signal Usage When
Sampled Comment
AC_SDOU
TSAFE M O DE Rising Edge
of PWROK
The signal has a weak internal pull-down. When
the signal is samp le d high, the Intel® 6300ES B
ICH wil l set the pro cessor speed str a p pins fo r safe
mode. Refer to processor specifi cation for speed
strapping definition. The status of this strap is
readab le via the SAFE_MODE bit (bit 2, D31: F0,
Offset D4h).
SIU0_DTR
#A16 swap
override Rising Edge
of PWROK
This signal has a weak internal pull-up. The Intel®
6300E S B ICH starts d riv ing it whe n PX PCIRST#
goes high. The status of this strap is readable via
D31: F0, Offset D5h, bit 5).
SPKR NO REBOOT Rising Edge
of PWROK
The signal has a weak internal pull-down. When
the signal is samp le d high, thi s ind icates that the
system is strapped to the “No R eboot” mode (The
Intel® 6300ESB ICH will d isab le the TCO Time r
system reboot feat ure). The st at u s o f this stra p is
readable via the NO_REBOOT bit (bit 1, D31: F0,
Offset D4h).
Intel® 6300ESB ICH—3
Intel® 6300ESB I/O Controller Hub
DS November 2007
78 Order Number: 300641-004US
3.22 Revision and Device ID Table
Table 24. Revision and Device ID Table
Devi ce
Function Description Devi ce
ID A0
Rev ID A1/A2
Rev ID A3
Rev ID Comments
D30,F0 Hub to PCI Bridge 244Eh 08h 09h 0Ah
D31,F0 LPC Bridge 25A1h 00h 01h 02h
D31,F1 IDE 25A2h 00h 01h 02h
D31,F2 SATA Controll er 25A3h 00h 0 1h 02h SATA and R AID
are mutually
exclusive.
D31, F3 SMBus Controller 25A4h 00h 0 1h 02h
D31, F5 AC’97 A udi o 25A6h 0 0h 0 1h 02h
D31, F6 AC’97 Modem 25A7h 0 0h 01h 02h
D29, F0 USB UHCI #1 25A9h 0 0h 0 1h 02h
D29, F1 USB UHCI #2 25AA h 00h 0 1h 02h
D29,F4 WDT 25ABh 00h 01h 02h
D29:F5 IOxAPIC 25ACh 00h 01h 02h
D29, F7 USB EHCI 25ADh 00h 0 1h 02h
D28:F0 H ub inte rf a ce to
PCI-X Bridge 25AEh 00h 01h 02h
D31:F2 RA ID Controller 25B0h 00h 01h SATA and RAI D
are mutually
exclusive.
NOTE: Refer to the latest Intel® 6300ESB I/O Controller Hub Specification Update for the v al u e
of the Revision Id en tification Reg isters.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 79
4—Intel® 6300ESB ICH
Intel® 6300ESB ICH Power Planes
and Pin States 4
4.1 Po w er P lanes
USAGE MODEL ASSUMPTION: The power planes and control are shown in Figure 5.
Tabl e 25 . Inte l® 6300ESB I/O Controller Hub Power Planes
Plane Description
Main I/O
(3.3 V) Vcc3_3: P o were d by the main pow er s uppl y. When t h e syst em i s in t he S3,
S4, S5, or G 3 sta te, this plane is assumed to be shut off.
Main Logic
(1.5 V) Vcc1_5: P o were d by the main pow er s uppl y. When t h e syst em i s in t he S3,
S4, S5, or G 3 sta te, this plane is assumed to be shut off.
Resume I/O
(3.3 V Standby)
VccSUS3_3: Po wered by t he main power supp ly in S0 - S1 stat es. P owere d
by the trickle pow er supply when the system is in the S3, S4, S5, state.
Assum ed to be shut o ff o nl y when in the G3 state ( sy stem i s un plu gged and
AC power is not present ).
Re sume Logic
(1.5 V Standby)
VccSUS1_5: Po wered by t he main power supp ly in S0 - S1 stat es. P owere d
by the trickle pow er supply when the system is in the S3, S4, S5, state.
Assum ed to be shut o ff o nl y when in the G3 state ( sy stem i s un plu gged and
AC power is not present ).
CPU I/F
(0.8 ~ 1.75 V)
V_CPU_IO: Powered by the m ain power supply through the processor
voltage regulator. When the system is in the S3, S4, S5, or G3 state, this
plane is assumed to be shut off.
Hub Interface
Logic
(1.5 V)
VccHI: P o wered by t h e ma i n po we r suppl y. Assum ed t o be 1. 5 V. Whe n the
system is in th e S3, S4, S5, or G3 state, th is p l an e is a ssu med to be sh u t
off.
RTC VccRTC: When other power is available (from the main supply), external
diode cou p ling will p rovide power to re duc e th e drain on th e RTC battery.
Ass ume d to op erate from 3.3 V down to 2.0 V.
Intel® 6300ESB ICH—4
Intel® 6300ESB I/O Controller Hub
DS November 2007
80 Order Number: 300641-004US
4.2 Integrated Pull-Ups and Pull-Dow ns
Figure 5. Power Plane Usage Model
Table 26. Integrated Pull-Up and Pull-Down Resistors
Sig na l Resistor Type Nominal Value N o t e s
AC_BITCLK pull-down 20K 1
AC_RST# pull-down 20K 2
AC_SDIN[2:0] pull-down 20K 3
AC_SDOUT pull-down 20K 2, 8
AC_SYNC pull-down 20K 2, 8
DPRSLPVR pull-down 20K 2
EE_DIN pull-up 20K 3
EE_DOUT pull-up 20K 3
GNT[B :A]# / GNT[5]# / GPIO[17:16] pull-up 20K 3
LAD[3:0]# / FWH[3:0 ]# pull-up 20K 3
LDRQ[1:0] pull-up 20K 3
PME# pull-up 20K 3
PWRBTN# pull-up 20K 3
PDD[7] / SDD[7] pull-down 11.5K 6
NOTES:
1. Simulation data shows that these resistor values may range f rom 10 KΩ to 40 KΩ.
2. Simulation data shows that these resistor values may range from 9 KΩ to 50 KΩ.
3. Simulation data shows that these resistor values may range from 15 KΩ to 35 KΩ
4. Simulation data shows that these resistor values may range from 7.5 KΩ to 16 KΩ.
5. Simulation data shows that these resistor values may range from 45 KΩ to 170 KΩ
6. Simulation data shows that these resistor values may range from 5.7 KΩ to 28.3 KΩ.
7. Simulation data shows that these resistor values may range from 14.25 KΩ to 24.8 KΩ
8. T he pull-up or pull-down on this signal is only enabled at boot/reset for strapping
function.
AT X Power
Supply
DC-DC
FET
Switch
DC-DC DC-DC
Core
Well
Suspend
Well
RTC
Well
Vcc
3.3 V
Vaux
5 V
3.3 V 1.5 V
1.5 V
3.3 V
VccRTC
L ithium Coin Ce ll
2.0 – 3.0V
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 81
4—Intel® 6300ESB ICH
4.3 IDE Integrated Series Term ina tion
Resistors
Table 27 shows the Intel® 6300ESB ICH IDE signals that have integrated series
ter mi na t io n re si sto r s.
4. 4 Output and I/O Sign al s Pl anes and States
Table 28 and Table 29 shows the power plane associated with the output and I/O
signals, as well as the state at various times. Within the table, the following terms are
used:
“High-Z” Tri-state. The Intel® 6300 ESB ICH is not d r iv ing the
sign al high or low.
“High” The Intel® 6300ESB ICH is driving the signal to a logic ‘1’.
“Low The Intel® 6300ESB ICH is driving the signal to a logic ‘0’.
“D e f in e d Dr iven to a le ve l tha t is de fin ed b y t he functio n ( will b e
high or low) .
“Undefined” The In tel® 6300ESB ICH is driving the signal, but the
value is indetermin a t e .
“Running” Clock is t oggling or signal i s tran sitioning because the
func tion is not stopp in g .
PDDREQ / SDDREQ pull-down 11.5K 6
SPKR pull-down 20K 2, 8
U S B [ 3:0] [P,N] pu ll-down 15K 7
Table 26. Integra ted Pull-Up and Pull-Down Resistors
Signal Re sistor Type Nom ina l Val u e Notes
NOTES:
1. Simulation data shows that these resistor values may range from 10 KΩ to 40 KΩ.
2. Simulation data shows that these resistor values may range from 9 KΩ to 50 KΩ.
3. Simulation data shows that these resistor values may range from 15 KΩ to 35 KΩ
4. Simulation data shows that these resistor values may range from 7.5 KΩ to 16 KΩ.
5. Simulation data shows that these resistor values may range from 45 KΩ to 170 KΩ
6. Simulation data shows that these resistor values may range from 5.7 KΩ to 28 .3 KΩ.
7. Simulation data shows that these resistor values may range from 14.25 KΩ to 24.8 K Ω
8. The pull-u p or p u ll-d own on this signal is only e n abled at boot/r es e t for strapping
function.
Table 27. IDE Series Termination Resistors
Signal Integra ted Serie s Termination Resistor Value
PDD[15 :0], S DD[15:0], PDIOW#,
SDIOW#, PDIOR#, PDIOW#, PD REQ,
SDREQ, PDDACK#, SDDACK#,
PIORDY, SIORDY, PDA [2:0],
SDA[2:0], PDCS 1#, SDCS1#,
PDCS3#, S DCS3#, IRQ14, IRQ15]
approxima te ly 33 Ω (See Note)
NOTE: Si mula tion data ind icates that the integ rated se rie s te rmination resistors are a n omin al
33 Ω but may range from 31 Ω to 43 Ω.
Intel® 6300ESB ICH—4
Intel® 6300ESB I/O Controller Hub
DS November 2007
82 Order Number: 300641-004US
“O ff” The po wer pl ane is off, so the Int el® 6300ES B IC H is no t
driving.
Note: The signal levels are the same in S4 and S5.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 83
4—Intel® 6300ESB ICH
4. 5 Pow er P l anes for In put Signals
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 1 of 7)
Signal Name Type Power
Well Resistors Durin g Reset
(Note 2) After Reset
(Note 2)
Hub Interface
H1PD[7:0] I/O C ore Internal Te rmination See table
below See table below
H1PSTRBS I/O Core Internal Te rmination See table
below See table below
H1PSTRBF I/O C ore Interna l Term ina tion See table
below See table below
H1REQM I Core Internal Termination See table
below See table below
H1REQI O Core Internal Termination See table
below See table below
H1 STOP I/O C ore Intern al Term in ation See table
below See table below
H1RCOMP I/O Core Strap Pin External Resistor1See tab le
below See table below
HLCLK I Core None See table
below See table below
H1PAR I/O Core Inte rn al Termination See table
below See table below
VSWING I Core Ex ternal Resistor1Input Only Input Only
HLVREF I Core External Resistor 1Input Only Input Only
PCI-X Interface
PXAD[63:32] I/O Core External Pull-up Z Z
PXAD[31 :0] I/O Core None Z Driven (0 or 1)
PXC/BE[7:4]# I/O Core External Pull-up Z Z
PXC/BE[3:0]# I/O C ore None Z Dr iven (0 or 1)
PXDEVSEL# I/O Core External Pull-up Z Z
PXFRAME# I/O Core External Pull-up Z Z
PXIRDY# I/O Core External Pull-up Z Z
PXIRQ[3:0]#/
GPIO[36:33] I / I/O
NOTE: 9Core External Pull-up Z Z
PXTRD Y# I/O Core External Pull-up Z Z
PXSTOP# I/O Core External Pull-up Z Z
NOTES:
1. The Intel® 6300ESB ICH sets these signals at reset for CPU fre q ue ncy strap.
2. The states of main I/O signals are taken at the times during PXPCIRS T# and imme diately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[16:2 1, 23], and GPIO [32:55] are in the core we ll.
5. GPIO[8:15] and GPIO[24:31] are in the sus pend we ll.
6. Core-well G PIO are 5 V tole rant, excep t for GPIO[7:6] and [32:43 ].
7. Resume- well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. PXIRQ[3: 0] are input only, GPIO[ 36:33] are I/O in GPIO mode
10.PIRQ [H:E] are I/OD, GPIO[5:2] are input on ly.
Intel® 6300ESB ICH—4
Intel® 6300ESB I/O Controller Hub
DS November 2007
84 Order Number: 300641-004US
PXPAR64 I/O Cor e Exte rnal Pull-up Z Z
PXPAR I/O Core None Z Driven (0 or 1)
PXPERR# I/O Core External Pull-up Z Z
PXREQ[0]# I Cor e Ex te rna l Pull-up Input Only Input Only
PXREQ[3:2]#/
GPIO[1:0] I Core External Pu ll-up Input Only Input Only
PXGNT[0:1]# O Core None 1 1
PXGNT[3]#/GPIO[17] O Core None 1 1
PXGNT[2]#/GPIO[16] O Core None H 1
PCICLK I Core None Input Only Input Only
RASERR# OD Core Ex ternal Pull-up 1 1
PXPCIRST# O Suspend None 0 1
PXPLOCK# I/O Core External Pull-up Z Z
PXSERR# I/OD Core External Pull -up Z Z
PXREQ6 4# I/O Core Ex ternal Pull-up H H
PXACK64# I/O Core E x ternal Pull-up H H
PXM66EN I Cor e External 10K Pull Up I nput On ly Input Only
PXPCIXCA P I Cor e External 10K Pull Up I nput On ly In p ut Only
PCI Interfac e
AD[3 1:0] I/O Core Non e Z Drive n ( 0 or 1)
C/BE[3:0]# I/O Cor e N one Z Driv e n (0 or 1)
DEVSEL# I/O Core External Pull -up Z Z
FRAME# I/O Core External Pull-up Z Z
IRDY# I/O Core Exte rna l Pull-up Z Z
TRDY# I/O Core Ex terna l Pull-up Z Z
STOP# I/O Cor e Ex terna l Pull-up Z Z
PA R I/O Core N one Z Dr iv en (0 or 1)
PERR# I/O Core External Pull-up Z Z
REQ[3 :0]# I Cor e Ex te rnal Pull-up Input On ly In p ut Only
GNT[3:0]# O Core None I I
PCICLK I/O Core None Input Only Input Only
PLOCK# I/O Core E x ternal Pull-up Z Z
SERR# I/OD Core Ex ternal Pull-up Z Z
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 2 of 7)
Signal Name Type Power
Well Resistors During Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 630 0 E S B I CH set s th e se sign a ls at re se t f o r CPU fre quen cy st rap.
2. The states of main I/O signals are take n at the times during PXPCIRST# and immediately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[1 6:21, 23], and GPIO[32:55] are in the core well.
5. GPIO [8:15] and GPIO[24:31] are in the suspe nd we ll.
6. Core -we ll G PIO a re 5 V tol erant, exc e pt for GPIO[7:6] and [32:43].
7. Resume-well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. P XIR Q[3:0] are inp u t only, G PIO[36:33] are I/O in GPIO mod e
10.PIRQ[H:E] are I/OD, GPIO[5:2] are inp u t only.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 85
4—Intel® 6300ESB ICH
PME# I/OD Suspend Inte rnal Pull-ups (15K -
35K) HH
LPC Interface
LAD[3:0] I/O Core Intern al Pu ll-up s (15K -
35K) HH
LFRAME# I Core In ternal Pull-up s (15K -
35K) 11
LDRQ[0]#,
LDRQ[1]# I/O Core Intern a l Pull-up s (15K -
35K) HH
USB Interface
USBP[3:0]P/N, I/O Suspend Internal Pull-down and
series re sistor s LL
OC[3:0]# I S uspe nd None Input Only Input Only
USBRBIASP O Suspend Ex tern al Pull-down
(22.6 ohm +/- 1%) Z1 during periodic
Auto Current Cal
USBRBIASN I Suspend
Analog connection point for
sen sing the voltage across
the exter n al USBRBIASP
resistor.
Input Only Input Only
SATA Interface
SATACL KP, SATACLKN I Core Input Only Input O nly
SATA0TXP, SATA0TXN O Core H
SATA0 RXP, SATA0RX N I Core In put O nly In pu t Onl y
SATA1TXP, SATA1TXN O Core
SATA1 RXP, SATA1RX N I Core In put O nly In pu t Onl y
SATALED# OD Core Extern al Pu ll-Up Z Z
SATARBIASP I Core
SATARBIASN I Core
IDE Interfa ce
PDCS1#,
SDCS1# OCore
Interna l S e rie s re sistors
(21 oh ms - 75 ohm s) 11
PDCS3#,
SDCS3# OCore
Interna l S e rie s re sistors
(21 oh ms - 75 ohm s) 11
PDA[2:0],
SDA[2:0] OCore
Interna l S e rie s re sistors
(21 oh ms - 75 ohm s) Driven (0 or 1) Driven (0 or 1)
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 3 of 7)
Signal Name Type Power
Well Resistors Durin g Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 6300ESB ICH sets these signals at reset for CPU fre q ue ncy strap.
2. The states of main I/O signals are taken at the times during PXPCIRS T# and imme diately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[16:2 1, 23], and GPIO [32:55] are in the core we ll.
5. GPIO[8:15] and GPIO[24:31] are in the sus pend we ll.
6. Core-well G PIO are 5 V tole rant, excep t for GPIO[7:6] and [32:43 ].
7. Resume- well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. PXIRQ[3: 0] are input only, GPIO[ 36:33] are I/O in GPIO mode
10.PIRQ [H:E] are I/OD, GPIO[5:2] are input on ly.
Intel® 6300ESB ICH—4
Intel® 6300ESB I/O Controller Hub
DS November 2007
86 Order Number: 300641-004US
PDD[15:0],
SDD[15:0] I/O Core
Internal Pull-downs on
PDD[7] and SD D[7] (5.7K -
28.3K ), Internal S er ie s
resistors
(21 ohms - 75 ohms)
L on bi t 7, Z on
others L on bit 7, Z o n
others
PDDREQ,
SDDREQ ICore
Internal Pull-d owns
(5.7K - 28.3K ), Interna l
Serie s re sistors (21oh ms -
75 ohms)
Inp ut Only Input Only
PDDACK#,
SDDACK# OCore
Internal Series resistors
(21 ohms - 75 ohms) 11
PDIOR# / (PDWSTB /
PRDMARDY#)
SDIOR# / (SDWSTB /
SRDMARDY#)
OCore
Internal Series resistors
(21 ohms - 75 ohms) 11
PDIOW# / (PDSTOP)
SDIOW # / (SDS TOP) OCore
Internal Series resistors
(21 ohms - 75 ohms) 11
PIORDY / (PDRS TB /
PWDMARDY#)
SIORDY / (SDRSTB /
SWDMARDY#)
ICore
Internal Series resistors
(21 ohms - 75 ohms)
External Pull-ups Input Only Input Only
IRQ[14-15] I Core In ternal Series resistors
(21 ohms - 75 ohms)
External Pull-ups Input Only Input Only
Interrupt Pi ns
SERIRQ I/O Core External Pull-up Z Z
PIRQ[A :D]# I Core E x te rnal Pull-up Z Z
PIRQ[E:H ]# /
GPIO[2:5] I/OD / I
NOTE: 10 Core External Pul l- up when used
as PIRQ ZZ
PXIRQ[3:0]#/
GPIO[36:33] I / I/O
NOTE: 9Core External Pull-up Z Z
AC’97 Inte rface
AC_RST# O Suspend Inter nal Pull-d own (9K -
50K) when ACLink is shut 00
AC_SYNC O Core Str ap P i n
In tern al Pull-d own2 du r ing
reset (9K - 50K) L0
AC_BIT_CLK I Core Inte rnal Pull-down2 (10K -
40K) Input Only Input Only
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 4 of 7)
Signal Name Type Power
Well Resistors During Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 630 0 E S B I CH set s th e se sign a ls at re se t f o r CPU fre quen cy st rap.
2. The states of main I/O signals are take n at the times during PXPCIRST# and immediately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[1 6:21, 23], and GPIO[32:55] are in the core well.
5. GPIO [8:15] and GPIO[24:31] are in the suspe nd we ll.
6. Core -we ll G PIO a re 5 V tol erant, exc e pt for GPIO[7:6] and [32:43].
7. Resume-well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. P XIR Q[3:0] are inp u t only, G PIO[36:33] are I/O in GPIO mod e
10.PIRQ[H:E] are I/OD, GPIO[5:2] are inp u t only.
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4—Intel® 6300ESB ICH
AC_SDATA_OUT O Core St r ap Pin
Internal Pull-down2 (9K -
50K) L0
AC_SDATA_IN[2:0] I/O Suspend Inte rnal Pull-d own (9K -
50K) L
Powe r Ma nagement Pins
THRM# I Core N one Input Only Input Only
THRMTRIP # I CPU I/O None Input Only Input Only
SLP_S3# O Suspend None 0 1
SLP_S4# O Suspend None 0 1
SLP_S5# O Suspend None 0 1
SYS_ RES ET# I Susp end None Input Only Input Only
PWRO K I RTC None Input Only Input Only
PWRBTN# I S u spe nd I nternal Pull-Up (15K - 35K) H H
RI# I Susp e nd None Input On ly Input Only
RSMRST # I RTC None Input Only Input Only
SUS_STAT# O Suspend None 0 1 after PWROK
rises
SU SCLK O Suspend None 0 Toggling
VRMPWRG D I C ore None Input Only Input Only
CPU Interface Pins
A20M # O CPU I/O No ne 0 (b efor e
PWROK rising) 1
CPUSL P# O CPU I/O None 1 1
FERR # I CPU I/O External Pu ll-up Input Only Input Only
IGNNE# O CPU I/O None 0 (b efor e
PWROK rising) 1
INIT# O CPU I/O None 1 1
INTR O CPU I/O None 0 (befo re
PWROK rising) 0
NMI O CPU I/O None 0 (b efo re
PWROK rising) 0
SMI# O CPU I/O None 1 1
STPCLK# O CPU I/O None 1 1
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 5 of 7)
Signal Name Type Power
Well Resistors Durin g Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 6300ESB ICH sets these signals at reset for CPU fre q ue ncy strap.
2. The states of main I/O signals are taken at the times during PXPCIRS T# and imme diately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[16:2 1, 23], and GPIO [32:55] are in the core we ll.
5. GPIO[8:15] and GPIO[24:31] are in the sus pend we ll.
6. Core-well G PIO are 5 V tole rant, excep t for GPIO[7:6] and [32:43 ].
7. Resume- well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. PXIRQ[3: 0] are input only, GPIO[ 36:33] are I/O in GPIO mode
10.PIRQ [H:E] are I/OD, GPIO[5:2] are input on ly.
Intel® 6300ESB ICH—4
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88 Order Number: 300641-004US
RCIN# I Core
Dependent upon the driving
agent. External Pull-up
when
open-drain.
Inp ut Only Input Only
A20GATE I Core
Dependent upon the driving
agent. External Pull-up
when
open-drain.
Inp ut Only Input Only
SMBus and System Management Pins
SMBDATA I/OD S uspend External Pull-up Z Z
SMBCLK I/OD Suspend External Pull-up Z Z
SMBALERT#/
GPIO[11] I Suspend Ex ternal Pull -up
(for SMBALERT#) Input Only Input Only
IN TRUDER# I RTC None Input Only Input Only
SMLINK[1:0] I/OD Suspend External Pull-ups Z Z
Real Time Clock Pins
R T C X1 Speci al R T C None Analog Input Analog Input
R T C X2 Speci al R T C None Analog Input Analog Input
Vbi a s I R T C None Analog Input Analog Input
Misc ella ne ous Pins and G PIO
CLK14 I Core None Input Only Input Only
CLK48 I Core None Input Only Input Only
SPKR O Core Strap P i n
Inter nal Pull-d own (9K -
50K) L0
RTCRST# I RTC External RC Circ uit Input Only Input Only
WDT_TOUT#/
GPIO[32] O / I/O Core None 1 1
GPIO[13:12],[8] I Suspend None Inp ut Only Input Only
GPIO[7:6] I Core Inter nal Pull-Up 1 Inp ut Only
GPIO[20:18] O Cor e N one 1 1 until d riv en
GPIO[21] O Core None 0 1
GPIO[23] O Core None 0 0 until d riv en
GPIO[25:24] I/O Suspend None 1 1
GPIO[27:28] I/O Suspend None 1 1
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 6 of 7)
Signal Name Type Power
Well Resistors During Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 630 0 E S B I CH set s th e se sign a ls at re se t f o r CPU fre quen cy st rap.
2. The states of main I/O signals are take n at the times during PXPCIRST# and immediately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[1 6:21, 23], and GPIO[32:55] are in the core well.
5. GPIO [8:15] and GPIO[24:31] are in the suspe nd we ll.
6. Core -we ll G PIO a re 5 V tol erant, exc e pt for GPIO[7:6] and [32:43].
7. Resume-well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. P XIR Q[3:0] are inp u t only, G PIO[36:33] are I/O in GPIO mod e
10.PIRQ[H:E] are I/OD, GPIO[5:2] are inp u t only.
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4—Intel® 6300ESB ICH
Table 29 shows the power plane associated with each input signal, as well as what
device drives the signal at various times. Valid states include:
High
Low
Sta tic: Will be hig h or low, but wil l not chan ge
Driven: Will be high or low, and is allowed to change
Running: For input clocks
GPIO[43:37] I/O Core N one 0 0 until driven
GPIO[57:56] OD RTC/
Suspend Exte rna l p ull u p Driven (0 or 1) Driven (0 or 1)
SIU Interface
UART_CLK I Core N one Input Only Input Only
SIU0_RXD I Core None Input Only Input Only
SIU1 _RX D I/O Core Internal Pull-Up (15K - 35K) H H
SIU0_TXD I/O Core None 1 1
SIU1_TX D I/O C ore Internal Pull-Up (15K - 35K) H 1
SIU 0_CTS# I Core None Input Only Input Only
SIU 1_CTS# I/O C ore Internal Pull-Up (15K - 35K) H H
SIU0_DS R# I Core N one Input Only Input Only
SIU1_DS R# I/O Core Internal Pull-Up (15K - 35K) H H
SIU0_DCD# I Core None Input Only Input Only
SIU1 _DC D# I/O Core Internal Pull-Up (15K - 35K) H H
SIU0_RI# I Core None Input Only Input Only
SIU1_R I# I/O Core Internal Pull-Up (15K - 35K) H H
SIU0 _DTR# O C ore Internal Pull-Up (15K - 35K) 1 1
SIU1 _DTR# I /O Core Internal Pull-Up (15K - 35K) H 1
SIU0_RTS# O Core None 1 1
SIU1_RTS# I/O Core Internal Pull-Up (15K - 35K) H 1
Table 28. Power Plane and States for Output and I/O Signal for Desktop
Configurations (Sheet 7 of 7)
Signal Name Type Power
Well Resistors Durin g Reset
(Note 2) After Reset
(Note 2)
NOTES:
1. The Intel® 6300ESB ICH sets these signals at reset for CPU fre q ue ncy strap.
2. The states of main I/O signals are taken at the times during PXPCIRS T# and imme diately after PXPCIRST#.
3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST#
4. GPIO[0:7], GPIO[16:2 1, 23], and GPIO [32:55] are in the core we ll.
5. GPIO[8:15] and GPIO[24:31] are in the sus pend we ll.
6. Core-well G PIO are 5 V tole rant, excep t for GPIO[7:6] and [32:43 ].
7. Resume- well GPIO are not 5 V tolerant.
8. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
9. PXIRQ[3: 0] are input only, GPIO[ 36:33] are I/O in GPIO mode
10.PIRQ [H:E] are I/OD, GPIO[5:2] are input on ly.
Intel® 6300ESB ICH—4
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90 Order Number: 300641-004US
Table 29. Power Plane for Input Signals for Desktop Configurations
Signal Name Power Well Driver During Reset S1 S3 S5
A20GAT E Main I/O External Microcontroller Static Low Low
AC_BIT_CLK Main I/O AC’97 Codec Low Low Low
AC_SD I N [2:0] Resume I/O AC’97 Code c Low Low Low
APICCLK Main I/O Clock Generator R unning Low Low
CLK14 Main I/O Clock Generator Running Low Low
CLK48 Main I/O Clock Generator Running Low Low
CLK66 Main Logic Clock Generator Running Low Low
FERR# CPU I/O CPU S tatic Low Low
INT RUDER# RTC Exte rna l Sw itch D riv e n Dr iven Driven
IRQ[15:14] Main I/O IDE Static Low Low
LDRQ[0]# Main I/O LPC Devices High Low Low
LDRQ[1]# Main I/O LPC Devices High Low Low
OC[5:0]# Resume I/O Externa l Pull-Ups D riv e n Driven Driven
PCICLK Main I/O Clock Generator Running Low Low
PD DR E Q Main I/O IDE Devi c e Stat ic Low Lo w
PIO R DY Main I /O IDE Devi c e Stat ic Low Lo w
PME# Resume I/O Inter n al P ull-Up Driven Dr iven Driven
PWRBTN# Resume I/O Internal P ull-Up Driven Driven Driven
PWROK RTC Sys t em Powe r Supply Dri ven Low Low
RCIN# Main I/O External Microcontroller High Low Low
REQ[0:5]# Main I/O PCI Master Driven Low Low
REQ[B:A ]# Main I/O PC/PCI Devices Driven Low Low
RI# Resume I/O Seria l Port Buff er Driv e n Dr iven Driven
RSMRST# RTC Ex ternal RC Circuit High High High
RT CRST# RTC Ex ternal RC Circuit High High High
SDDREQ Main I/O IDE Drive Static Low Low
SERR# Main I/O PCI Bus Peripherals High Low Low
SIORDY Main I/O IDE Drive Static Low Low
SMBALERT# Resume I/O External Pull-Up Driven Driven Driven
SYS_RESET# Resume I/O External Circuit Driven Driven Driven
THRM# Main I/O Thermal Sens or Driven Low Low
THRMTRIP# CPU I/O Thermal S ensor D riv en Low Low
USBRB I A S # Res u me I/O E x te rna l Pull-Down Drive n Dr iven Driven
Intel® 63 00ESB I/O Controller Hub
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5—Intel® 6300ESB ICH
Functional Description 5
5.1 Hub Interface to PCI Bridge (D30:F0)
The Hub Interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This
portion of the Intel® 6300ESB ICH implements the buffering and control logic between
PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device.
The PCI decoder in this device must decode the ranges for the Hub Interface. All
register contents will be lost when core well power is removed.
5.1.1 PCI Bus Interface
The Intel® 6300ESB ICH PCI interface provides a 33 MHz, PCI Local Bus Specificat ion,
Rev. 2.2-compliant implementation. All PCI signals are 5 V tolerant. The Intel®
6300ESB ICH integrates a PCI arbiter that supports up to four external PCI bus masters
in addition to the internal Intel® 6300ESB ICH requests.
Most transactions targeted to the Intel® 6300ESB ICH will first appear on the external
PCI bus before being claimed back by the Intel® 6300E SB ICH. The exce ptio ns are I/O
cycles involving USB, IDE, and AC’97. These transactions will complete over the Hub
Interface without appearing on the external PCI bus. Configuration cycles targeting
USB, IDE or AC’97 will appear on the PCI bus. When the Intel® 6300ESB ICH is
programmed for positive decode, the Intel® 6300ESB ICH will claim the cycles
appearing on the external PCI bus in medium decode time. When the Intel® 6300ESB
ICH is programmed for subtractive decode, the Intel® 6300ESB ICH will cla im these
cycles in subtractive time. When the Intel® 6300ESB ICH is programmed for
subtractive d ecode, these cycle s may be claimed by another positive deco de agent out
on PCI. This architecture enables the ability to boot off of a PCI card that positively
decodes the boot cycles. In order to boot off a PCI card it is necessary to keep the
Intel® 6300ESB ICH in subtractive decode mode. When booting off a PCI card, the
BOOT_STS bit (bit 2, TCO2 Status Register) will be set.
When the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the
Intel® 6300ESB ICH will not allow upstream requests to be performed until the cycle
co mpl et io n. Thi s ma y be cri ti c al for is oc hr ono us b use s wh ic h ass ume ce rta in tim in g fo r
their data flow, such as AC’97 or USB. Devices on these buses may suffer from
underrun when the asynchronous traffic is too heavy. Underrun means that the same
data is sent over the bus while the Intel® 6300ESB ICH is not able to issue a request
for the next data. Snoop cycles are not permitted while the processor side bus is
locked.
Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a
short duration (a few microseconds at most). When a system has a very large number
of locked cycles and some that are very long, then t he system will definit ely experience
underruns and overruns. The units most likely to ha ve problems are the AC’97
controller and the USB controllers. Other units could get underruns/overruns, but are
much less likely. The IDE controller (due to its stalling capability on the cable) should
not get any underruns or overruns.
Note: The Intel® 63 00ESB ICH’ s AC ’97, IDE a nd USB Con troll ers cann ot perfo rm p eer-t o-peer
traffic.
Note: Poor perf orming PCI devices that cause long latencies (numerous retries) to Processor-
to-PCI Locked cycles may starve isochronous transfers between USB or AC’97 devices
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and memory. This will result in overrun or underrun, causing reduced quality of the
isochronous data, such as audio.
Note: PCI configuration write cycles, initiated by the processor, with the following
characteristics will be converted to a Special Cycle with the Shutdo wn message type.
Device Number (AD[15:11]) = ‘11111
Function Number (AD[10:8]) = ‘111’
Register Number (AD[7:2]) = ‘000000
Data = 00h
Bus number matches secondary bus number
5.1.2 PCI-to-PCI Bridge Model
From a software perspective, the Intel® 6300ESB ICH contains a PCI-to-PCI bridge.
This bridge connects the Hub Interface to the PCI bus. By using the PCI-to-PCI bridge
software model, the Intel® 6300ESB ICH may have its decode ranges programmed by
existing plug-and-play software such that PCI ranges do not conflict with AGP and
graphics aperture ranges in the Host controller.
5.1.3 IDSEL to Device Numbe r Mapping
When addressing devices on the external PCI bus (with the PCI slots) the Intel®
6300ES B ICH wil l assert o ne addre ss si gnal as an IDSEL. When ac cessin g devic e 0, the
Intel® 6300ESB ICH will assert AD16. When accessing Device 1, the Intel® 6300ESB
ICH will assert AD17. This mapping continues all the way up to device 15 where the
Intel® 6300ESB ICH asserts AD31. Note that the Intel® 6300ESB ICH’s internal
functions (AC’97, IDE, USB, and PCI Bridge) are enumerated like they are on a
separate PCI bus (the Hub Interface) from the external PCI bus.
5.1.4 SERR# Functionality
There are several internal and external sources that may cause SERR#. The Intel®
6300ESB ICH may be programmed to cause a n NMI based on detecting that an SERR#
condition has occurred. The NMI may also be routed to instead cause an SMI#.
Note: N ot e th a t th e In t e l® 6300ESB ICH does not drive the external PCI bus SERR# signal
act iv e onto the PCI bu s. The externa l SERR# si gna l is an i nput into the In te l® 6300ESB
ICH driven only by external PCI devices. The conceptual logic diagrams in Figure 6 and
Figure 7 illustrate all sources of SERR#, along with their respective enable and status
bits.
Figure 8 shows how the Intel® 6300ESB ICH error reporting logic is configured for
NMI# generation.
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5—Intel® 6300ESB ICH
Figure 6. Primary Device Status Register Error Reporting Logic
AND
AND
AND OR
OR
AND
AND
AND
AND
AND
AND
AND
OR AND
D28: 04h.6
HL Parity Error
D28: 3Eh.0
PX PARITY ERROR
D28: (3Eh.11) DTSE
DTT_EN
D28: 3Eh.1
PCI-X SERR Pin
(D28:04h.8)
PX_SERR#_ENABLE
RX TARGET ABORT
SER R_R TA_EN (D30:90h.2)
SERR_RTA
(D30:92h.2)
SERR# Enable (D30:3Eh.1)
Legacy PCI SERR s ignal
Delayed Transaction Timeout
P_SER R_EN (D30:04h.8)
SERR_EN (D30:04h.8)
PCI Address Parity Error
Pre-latch
P_SSE
(To T-Unit)
Master Abort Mode (D30:3Eh.5)
HL-to-PCI Posted Write Master Aborts
SERR_EN (D30:04h.8)
D30:3Eh.0
D30:3Eh.1
P_SSE
(D30:06h.14)
AND
SERR_DTT_EN (D30.3Eh.1)
HL -to-PCI- X Posted Write Master Aborts
Mas ter Abort Mode (D28.3Eh.5) AND
SSE for PCI- X
(D28:06h.14)
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Figure 7. Secondary Status Register Error Reporting Logic
S_SSE
(D31:F0.06h.14)
Pre-latch
S_SSE
(To T-U nit)
OR
AND
SER R_DTT_EN (D31:88h.1)
AND
SER R_R TA_EN (D31:88h.2)
Recei ved Tar get Abor t
SER R# E nable (D 31:F0.04h.8)
South PCI Delaye d Tr a nsa c t ion Timeo ut
AND
IOCHK# via SERIRQ
Receive DO_SERR message from HL
MCHSERR_STS (TCOBASE+04h.bit 12)
ERROR from XL-Unit
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5—Intel® 6300ESB ICH
5.1.5 Parity Error Detection
The Intel® 6300ESB ICH may detect and report different parity errors in the system.
The Intel® 6300ESB ICH may be programmed to cause an NMI (or SMI# when NMI is
routed to SMI#) based on detecting a parity error. The conceptual logic diagram in
Figure 8 details all the parity errors that the Intel® 6300ESB ICH may detect, along
with their respective enable bits, status bits, and the results.
Note: The Intel® 6300ESB ICH does not escalate a data parity mismatch reported by a PCI
device (PERR#) across the P2P bridge.
Note: When NMIs are enabled, and parity error checking on PCI is also enabled, then parity
errors will cause an NMI. Some operating systems will not att empt to recover from this
NMI, since it considers the detection of a PCI error to be a catastrophic event.
Figure 8. NMI# Generation Logic
A9644-01
AND
AND
OR
OR
AND
AND
To NMI#
Output and
Gating Logic
IOCHK from SERIRQ Logic
Port 61.3
S_SSE for PCI-X
Pre-latch S_SSE
Pre-latch P_SSE
HubLink Parity Error Detected
D30_P_PER (D30:04h.6)
PCI Parity Error Detected
D30_S_PER (D30:3Eh.0)
South PCI Parity Error Detected
D31_S_PER (D31:04h.6)
Pre-latch
USBe_SSE TCONMI_STS
Port 70:7
IOCHK_NMI_STS
(Port 61.6)
SERR_NMI_STS
(Port 61.7)
D30_PDPD
(D30:06h:8)
D30_SDPD (D30:1Eh:8)
PCI_SERR_STS
(Port 61.2)
AND
PCI-X PERR_PIN
(D28:3E.0)
AND
D29:F7:06h.14
D31_DPT (D31:06h.8)
PUSERR_NMI
AND
OR
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5.1.6 Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space: Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the Intel® 630 0ESB ICH. The Intel® 6300 ESB
ICH only supports Mechanism #1 as defined in the PCI specification.
Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers
greater than 0 will be sent towards the Intel® 6300ESB ICH from the host controller.
The Intel® 6300ESB ICH compares the non-zero Bus Number with the Secondary Bus
Number and Subordinate Bus number registers of its P2P bridge to determine when the
configuration cycle is meant for Primary PCI or a downstream PCI bus.
5.1.6.1 Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on Hub Interface to any function other
than USB EHCI or AC’97, the Intel® 6300ESB ICH forwards these cycles to PCI and
then reclaims them. The Intel® 6300ESB ICH uses address bits AD[15:13] to
comm unic at e the Int el® 6300ESB ICH device numbers in Type 0 configuration cycles.
When the Type 0 cycle on Hub Interface specifies any device number other than 29, 30
or 31, the Intel® 6300ESB ICH will not set any address bits in the range AD[31:11]
during the corresponding transaction on PCI. Table 30 shows the device number
translation.
The Intel® 6300ESB ICH logic will generate single D-word configuration read and write
cycles on the PCI bus. The Intel® 6300ESB ICH will generate a Type 0 configuration
cycle for configurations to the bus number matching the PCI bus. When the cycle is
targeting a device behind an external bridge, the Intel® 6 300ES B ICH wi ll run a Type 1
cycle on the PCI bus.
5.1.6.2 Type 1 to Type 0 Conversion
When the bus number for the Type 1 configuration cycle matches the PCI (Secondary)
bus number, the Intel® 6300ESB ICH will convert the address as follows:
1. For device numbers 0 through 15, only one bit of the PCI address [31:16] will be
set. When the device number is 0, AD[16] is set; when the device number is 1,
AD[17] is set; etc.
2. The Intel® 6300ESB ICH will always drive 0s on bits AD[15:11] when converting
Type 1 configurations cycles to Type 0 configuration cycles on PCI.
3. Address bits [10:1] will also be passed unchanged to PCI.
4. Address bit [0] will be changed to ‘0’.
Table 30. Type 0 Configuration Cycle Device Number Translation
Device # In Hub Interfa ce Typ e 0
Cycle AD[31:11] During Address Phase of Type 0
Cycle on PCI
0 through 28 0000000000000000_00000b
29 0000000000000000_00100b
30 0000000000000000_01000b
31 0000000000000000_10000b
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5—Intel® 6300ESB ICH
5.1.7 PCI Du al A ddress Cycle (DAC) Support
The Intel® 6300ESB ICH supports DA C forma t on PCI for cycles from PCI initiators to
main memor y . Th is allows PCI maste rs to genera te an address u p to 44 bits. Th e size of
the actual supported memory space will be determined by the Memory Controller and
the processor.
The DAC mode is only supported for PCI adapters and USB EHCI, and is not supported
for any of the internal PCI masters (IDE, USB UHCI, AC’97, 8237 DMA, etc.).
When a PCI master wants to initiate a cycle with an address above 4G, it follows the
following behavioral rules (See PCI Local Bus Specification, Revisi on 2.2, s ec tion 3.9 for
more det a ils ):
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the
DAC encoding on the C/BE# signals. This unique encoding is: 1101.
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low
address.
3. On the second clock, the peripheral drives AD[31:0] with the high address. The
address is right justifi ed: A[43:32] appear on AD[12:0]. The value of AD[31:13] is
expected to be 0, however the Intel® 6300ESB ICH will ignore these bits. C/BE#
indicate the bus command type (Memory Read, Memory Write, etc.)
4. The rest of the cycle proceeds normally.
5. 2 LPC B ri dge (w it h System and Management
Functions) (D31:F0)
The LPC Bridge function of the Intel® 6300ESB ICH resides in PCI Device 31:Function
0. In addition to the LPC bridge function, D31:F0 contains other functional units
including DMA, Interrupt Controllers, Timers, Power Management, System
Management, GPIO, and RTC.
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5.2. 1 LPC Cycle Types
The Intel® 6300ESB ICH implements all of the cycle types described in the Low Pin
Count Interface Specification, Revision 1.0. Table 31 shows the cycle types supported
by the Intel® 6300ESB ICH.
5.2.1.1 Start Field Definition
Table 31. LPC Cycle Types Supported
Cycle Type Comment
Memory Read Sin gle: 1 byte on ly1
Memory Wr it e Singl e: 1 byte on l y1
I/O Read 1 byte only. The Intel® 6300ESB ICH breaks up 16 and 32-bit processor
cycles into multiple 8-bi t t ransfers.
I/O Write 1 byte only. The Intel® 6300ESB ICH breaks up 16 and 32-bit processor
cycles into multiple 8-bi t t ransfers.
DMA Read May be 1, or 2 bytes
DMA Write May be 1, or 2 bytes
Bus Master Read May be 1, 2, or 4 bytes.2
Bus Master Write May be 1, 2, or 4 bytes.2
NOTES:
1. For memory cycles below 16M which do not target enabled FWH ranges, the Intel® 6300ESB
ICH will perform standard LPC memory cycles. It will only attempt 8-bit transfers. When the
cycle appears on PCI as a 16-bit transfer, it w ill appear as two co nsecutive 8-bit tr ansfer s on
LPC. Likewise, when the cycle appears as a 32-bit transfer on PCI, it will appear as four
consecutive 8-bit tr ansfers on LPC. When the cycle is not claimed by any peripheral, it will be
subsequently aborted, and the Intel® 6300ESB ICH will return a value of all 1s to the
proc e ssor. Th is is d one to ma in tain com patibility wit h ISA me mory cycles where pull-up
r es istors would keep th e bus high when no d e vice resp on d s.
2.Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
may be to any address. However, the 2-b yte transf e r mus t be word aligned (i.e.,with an
address where A0=0). A DWORD transfer must be DWORD aligned (i.e., with an address
where A1an d A0 ar e bo th 0).
Table 32. Start Field Bi t Definitions
Bits[3:0]
Encoding Definition
0000 Start of cycle for a gener ic targe t.
0010 Grant for bus maste r 0.
0011 Grant for bus maste r 1.
1101 Start of cycle for f irmware me mory read cycle
1110 Start of c ycle for f irmware memory write cy cle
1111 Stop/Abort: End of a cycle for a target.
NOTE: All other encodings are Reserved.
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5.2.1.2 Cycle Type/Direction (CYCTYPE + DIR)
The Intel® 63 00ES B ICH will alwa ys dr ive bi t 0 of thi s fiel d to zero . P er ipherals runni ng
bus master cycles must also drive bit 0 to 0. The following table shows the valid bit
encodings:
5.2.1.3 SIZE
Bits[3:2] are reserved. The Intel® 6300ESB ICH will always drive them to 00.
Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2,
however, the Intel® 6300ESB ICH will ignore those bits. Bits [1:0] are encoded as
follows:
5.2.1.4 SYNC
Valid values for the SYNC field are:
Table 3 3. Cycle Type Bit Definitions
Bits[3:2
]Bit[1] Definition
00 0 I/O Read
00 1 I/O Write
01 0 Memory Read
01 1 Memory Write
10 0 DMA Read
10 1 DMA Write
11 x Res erved. When a periphera l perform i ng a bus ma s ter cyc le gen erat es
this value, the Intel® 6300ESB ICH will abort the cycle.
Table 34. Transfer Size Bit Definition
Bits[1:0] Size
00 8-bit transf er (1 byte )
01 16-bit transf er (2 byte s)
10 R es er ved . The Intel® 6300ESB ICH will never drive this comb in ation. Whe n a
peripheral running a bus master cycle drives this combination, the Inte l®
6300E SB ICH may abo rt the transfer.
11 32-bit transf er (4 byte s)
Table 35. SYNC Bit Definition (Sheet 1 of 2)
Bits[3:0] Indication
0000 Ready: SYNC achieved with no error . For DMA transfers, this also indicates DMA
request deassertion and no more transfers des ired for that channel.
0101 Sh o rt Wait: Part indicating wait-sta tes. For bus master cy cle s, th e In te l®
630 0ES B ICH will not use this e n coding. It will in ste ad u se th e Long Wait
encoding (see next encoding below).
NOTE: All other combinations are Reserved.
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5.2 . 1.5 SY NC Ti m e-O u t
There are several error cases that may occur on the LPC I/F. The following table
indicates the failing case and the Intel® 6300ESB ICH response:
There may be other peripheral failure conditions, however these are not han dled by the
Intel® 6300ESB ICH.
5.2 .1. 6 SY NC Err o r Indicati on
The SYNC protocol allows the peripheral to report an error through the LAD[3:0] =
‘1010b’ encoding. The intent of this encoding is to give peripherals a method of
communicating errors to aid higher layers with more robust error recovery.
When the Intel® 6300ESB ICH is reading data from a peripheral, data will still be
tr ans ferre d in th e next two nib bles. Thi s data may be inv al id, but i t must be tr ansf erre d
by the peripheral. When the Intel® 6300ESB ICH is writing data to the peripheral, the
data had already been transferred.
In the case of multiple byte cycles, such as for memory and DMA cycles, an error SYNC
terminates the cycle. Therefor e, when the Intel® 6300ESB ICH is transferring four
bytes from a device, and if the de vice returns th e error SYNC in the firs t byte, the other
three bytes will not be transferred.
0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This
encodin g drive n by the Int el® 6300ESB ICH for bus master cycles, rather than
the Short Wait (0101).
1001
Ready More (Used only by peripheral for DMA cycle): SYNC achieved w it h
no error an d more DMA trans fers desire d to contin ue a f te r this tra n sf e r. This
value is valid only on DMA tran sf e rs an d is not a llowed for any other type of
cycle.
1010
Error: Sync achieved wi th error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/IS A bus. It indicates that the data is to be transferred,
but there is a ser ious error in this transfer. For DMA transf e rs, this not only
indica te s a n e rror, but a lso in d icates DMA request deassertion a nd no more
transfers d e si red fo r t ha t chann e l .
Table 35. SYNC Bit Definition (Sheet 2 of 2)
Bits[3:0] Indication
NOTE: All othe r combinat ions are Reserv e d.
Table 36. Response to Sync Failures
Possibl e Sync Fa ilure Intel® 6300ESB I CH
Response
Intel® 6300ESB ICH starts a Memor y, I/O, or D M A cycle, but no
device drives a valid S YN C a f te r 4 consecutiv e cl ocks. This could
occur wh en the proc essor trie s to acc es s an I/O location to which no
device is mapped.
Intel® 6300ESB ICH
aborts the cy cle a f te r
the fourth cloc k .
Intel® 6300ESB ICH d riv es a Mem ory, I/O, or DMA cycle, and a
peripheral drives more than 8 consecutive valid SYNC to insert wait-
states using the Short (‘0101b’) encoding for SYNC. This could occur
when the peripheral is no t ope r at i ng proper l y.
Conti nu e s wa iting
Intel® 6300ESB ICH starts a Memory, I/O, or DMA cycle, and a
peripheral drives an invalid SYNC pattern. This could occur when the
peripheral i s not operating properly or when there is exc essive no ise
on the LPC I/F.
Intel® 6300ESB ICH
aborts the cycle when
the in valid Sy nc is
recognized.
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Upon recognizing the SYNC field indicating an error, the Intel® 6300ESB ICH will tre at
this the same as IOCHK# going active on the ISA bus.
5.2.1.7 LFRAME# Usage
Start of Cycle
Fo r Memory, I/O, and DMA cycles, the Intel® 6300 ESB ICH wi ll assert LFRAM E# for o ne
clock at the beginning of the cycle (Figure 9) During that clock, the Intel® 6300ESB
ICH will drive LAD[3:0] with the proper START field.
Abort Mechanism
When perf ormin g an Abort, the I nte l® 6300ESB ICH will drive LFRAME# active for four
consecutive clocks. On the fourth clock, it will drive LAD[3:0] to ‘1111b’.
The Intel® 6300ESB ICH will perform an abort for the following cases (possible failure
cases):
Intel® 6300ESB ICH starts a Memory, I/O, or DMA cycle, but no device drives a
valid SYNC after four consecutive clocks.
Intel® 6300ESB ICH starts a Memory, I/O, or DMA cycle, and the peripheral drives
an invalid SYNC pattern.
A peripheral drives an illegal address when performing bus master cycles.
A peripheral drives an invalid value.
Figure 9. Typical Timing for LFRAME#
LFRAME#
Start
LCLK
LAD[3:0]
CYCTYPE
ADDR Start
Dir & Size
TAR Sync Data TAR
1 - 8
Clocks 2
Clocks 1 - n
Clocks 2
Clocks 2
Clocks
1
Clock 1
Clock
Figure 10. Abort Mechanism
LFRAME#
Start
LCLK
LAD[3:0]
CYCTYPE
ADDR
Dir & Size
TAR Sync Peripheral must
stop driving
Too many
Syncs causes
timeout
Chipset w ill
drive high
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5.2.1.8 I/O Cycles
F or I/O cycles targeting registers specified in the Intel® 6300ESB ICH’s dec ode r ange s,
th e In t e l ® 6300ESB ICH performs I/O cycles as def ined in the LPC spec. These will be
8-bit transfers. When the processor attempts a 16-bit or 32-bit transfer, the Intel®
6300ESB ICH will break the cycle up into multiple 8-bit transfers to consecutive I/O
addresses.
Note: When the cycle is not claimed by any peripheral (and subsequently aborted), the Intel ®
6300ESB ICH will return a value of all ones (FFh) to the processor. This is to maintain
co mpa ti b ili t y wi th I SA I /O cy c les whe re p ul l-u p re si s tors wou ld ke e p th e bu s hi g h wh en
no device responds.
5.2.1.9 Bus Master Cycles
The Intel® 6300ESB ICH supports Bus Master cycles and requests (using LDRQ#) as
defined in the LPC specificatio n. The Intel® 6300ESB ICH has two LDRQ# inp uts, and
thus supports two separate bus master devices. It uses the associated START fields for
Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).
Note: The Intel® 6300ESB ICH does not support LPC Bus Masters performing I/O cycles. LPC
Bus Masters should only perform memory read or memory write cycles.
5.2.1.10 LPC Power Management
LPCPD# Pr otocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will
drive LDRQ# low or tri-state it. The Intel® 6300ESB ICH will shut off the LDRQ# input
buf f e rs. Af te r d r ivi ng SU S_ STAT# a cti ve , t h e I nt el ® 63 00ES B ICH dr iv es LF RAME# low,
and tri-states (or drive low) LAD[3:0].
The Intel® 6300ESB ICH does not follow one part of the LPC spec that says “LRESET#
is always asserted after LPCPD#”. The exception is the S1-M state. In that case,
LPCPD# (SUSSTAT#) will go active, but LRESET# (PXPCIRST#) will not go active.
5.2 . 1.1 1 C on fi g uratio n and I nt e l® 6300ESB ICH Implications
LPC I/F Decoders
In order to allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the
Intel® 6300ESB ICH includes several decoders. During configuration, the Intel®
6300ESB ICH must be programmed with the same decode ranges as the peripheral.
The decoders are programmed through the Device 31:Function 0 configuration space.
Note: The Intel® 6300ESB ICH cannot accept PCI write cycles from PCI-to-PCI bridges or
de vices with si mil ar cha ract eri stic s (spe cifi call y thos e wit h a R et ry R ead” f eature whic h
is enabled) to an LPC device when there is an outstanding LPC read cycle towards the
same PCI device or bridge. These cycles are not part of normal system operation, but
may be encountered as part of platform validation testing using custom test fixtures.
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Bus Maste r Dev ice M appi ng and STAR T Fields
Bus Masters must have a unique START field. In the case of the Intel® 6300ESB ICH,
which su pport s two LPC bus master s, it wil l dri ve 001 0 for the STAR T field f or gr ants to
bus master #0 (requested through LDRQ[0]#) and 0011 for grants to bus master #1
(requested through LDRQ[1]#.). Thus no registers are needed to config the START
fields for a particular bus master.
BIOS Mappi ng and STAR T Fields
To reduce decoding logic in the FWH, the Intel® 6300ESB ICH will use a unique IDSEL
field for each EPROM. To do t his, the Intel® 630 0ESB ICH ha s c onfi gu ra ti on regi ste rs to
assign a particular BIOS range to a particular IDSEL field.
5. 3 DMA Operatio n (D31:F0)
5.3.1 DMA Overview
The Intel® 6300ESB ICH supports LPC DMA through LPC, similar to ISA DMA.
The DMA controller has registers that are fixed in the lower 64 Kbyte of I/O space. The
DMA controller is configured using registers in the PCI config space. These registers
allow configuration of individual channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 8237 DMA controllers with
seven independently programmable channels (Figure 11). DMA Controller 1 (DMA-1)
corresponds to DMA channels 0-3 and DMA Controller 2 (DMA-2) corresponds to
channels 5-7. DMA channel 4 is used to cascade the two controllers and will default to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to 1.
Each DMA channel is hardwired to the compatible settings for DMA device size:
channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are
hardwired to 16-bit, count-by-words (address shifted) transfers.
The Intel® 6300ESB ICH provides 24-bit addressing in compliance with the ISA -
compatible specification. Each channel includes a 16-bit ISA-Compatible Current
Register which holds the 16 least-significant bits of the 24-bit address, an ISA-
Compatible Page Register which contains the eight next most significant bits of
address.
The DMA controller also features refresh address generation, and autoinitialization
following a DMA termination.
Figure 11. Intel® 6300ESB ICH DMA Controller
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
DMA-1 DMA-2
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5.3.2 Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3
and channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register. See Section 8.2, “DMA I/O Registers for more
information.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service may be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. Please see Section 8.4.9, “OCW3—Operational Control Word 3
Register for detailed register description for Request Register programming
information in the DMA I/O Register (Section 8.2, “DMA I/O Registers).
5.3.2.1 Fixed Priority
The initial fixed priority structure is as described in Table 37.
The fixed priority ordering is zero through seven. In this scheme, channel 0 has the
highest priorit y , and channel 7 has the lowest priority . Channels [3:0] of DMA-1 assume
t he prior ity posi tion of chann el 4 in DMA-2, thus taki ng pri ori ty ov er cha nnel s 5, 6, and
7.
5.3.2.2 Rotating Priority
Ro tat io n allows for “fairness” in priority resolution. The priority c hain rotates so that the
last channel serviced is assigned the lowest prior ity in the channel group (0–3, 5–7).
Channels 0–3 rotate as a gr oup of four. They are always placed between channel 5 and
chan n el 7 in the prio rity list.
Channel 5–7 rotate as part of a group of four. That is, channels (5–7) form the first
t hre e po s it ions in t he rot at ion , while ch an nel g r ou p (0– 3 ) co mp ri se s t he four th po si ti on
in the arbitration.
5.3.3 Address Compatibility Mode
Whenever th e DMA is operating, the addresses do not increment or decrement t hrough
the High and Low Page Registers. Therefore, when a 24-bit address is 01FFFFh and
increments, the next address will be 010000h, not 020000h. Similarly, when a 24-bit
address is 020000h and decrements, the next address will be 02FFFFh, not 01FFFFh.
However, when the DMA is operating in 16 bit mode, the addresses still do not
increment or decrement through the High and Low Page Registers but the page
boundary is now 128K. Therefore, if a 24 bit address is 01FFFEh and increments, the
next address will be 000000h, not 010000h. Similarly, if a 24 bit address is 020000h
and decrements, the next address will be 03FFFEh, not 02FFFEh. This is compatible
with the 8237 and Page Register implementation used in the PC-AT. This mode is set
after CPU R ST is valid.
Table 37. Fixed Priority
Hi gh p rio r ity .....L o w pri o rity
(0, 1, 2, 3) (5, 6, 7)
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5.3.4 Summary of DMA Transfer Sizes
Table 39 lists each of th e DMA device transfer sizes. The column labeled “Current Byte/
Word Coun t R e gist er” indi cate s tha t th e reg iste r co ntent s re pres ents e ithe r th e num ber
of bytes to transfer or the number of 16-bit words to transfer. The column labeled
“Current Address Increment/Decrement” indicates the number added to or taken from
the Current Address register after each DMA transfer cycle. The DMA Channel Mode
Register determines when the Current Address Register will be incremented or
decremented.
5.3.4.1 Address Shifting When Programmed for 16-Bit I/O Cou nt
by Words
The Intel® 6300ESB I CH m ai ntains com pa tibili ty with t he i mplement ation of t he DMA in
the PC-AT which used the 8237. The DMA shifts the addresses for transfers to/from a
16-bit device count-by-words. Note that the least significant bit of the Low Page
Register is dropped in 16-bit shifted mode. When programming the Current Address
Register (when the DMA channel is in this mode), the Current Address must be
programmed to an even address with the address value shifted right by one bit. The
ad dres s sh iftin g is des crib ed in Table 39.
5.3.5 Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following TC. The Base Registers are loaded simultaneously
with the Cu rrent Registers by the microprocessor when the DMA channel is
programmed and remain unchanged throughout the DMA service. The mask bit is not
set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ
is detected.
Tabl e 38 . D MA Tran sfe r Size
DMA Device Date Size And Word Count Cur rent By te/W o rd
Count R egiste r
Current Address
Increment/
Decrement
8-Bit I/O, C ount By Bytes Bytes 1
16-Bit I/ O, Cou n t B y Words (Ad dress
Shifted) Words 1
Table 39. Address Shifting in 16-bit I/O DMA Transfers
Output
Address 8-Bit I/O Programmed
Address (Ch 0–3)
16- Bit I / O P ro gramme d
Addre ss (Ch 5–7)
(Shifted)
A0
A[16:1]
A[23:17]
A0
A[16:1]
A[23:17]
0
A[15:0]
A[23:17]
NOTE: The le ast significa nt bi t o f the Page Registe r is d rop p e d in 16-bit shifte d m od e.
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5.3.6 Software Commands
There are three additional special software commands that the DMA controller may
execute. The three software commands are:
1. Clear Byte Pointer Flip-Flop
2. Master Clear
3. Clear Mask Register
They do not depend on any specific bit pattern on the data bus.
5.3.6.1 Clear Byte Pointer Flip-Flop
This command is executed prior to writing or reading new address or word count
information to/from the DMA controller. This initializes the flip-flop to a known state so
t hat s ub seq ue nt ac ce ss es t o reg ist er co nte nts b y t he mi cr opr oc essor wil l a ddr es s up per
and lower bytes in the correct sequence.
When th e Host p roc essor is rea din g or w ri ti ng DMA reg iste rs, two By te P o inte r f lip- fl ops
are used; one for channels 0–3 and one for channels 4–7. Both of these act
independently. There are separate software commands for clearing each of them (0Ch
for channels 0–3, 0D8h for channels 4–7).
5.3.6.2 DMA Master Clear
This software instruction has the same effect as the hardware reset. The Command,
Status, Request, and Internal First/Last Flip-Flop Registers are cleared and the Mask
Register is set. The DMA controller will enter the idle cycle.
There are two independent master clear commands; 0Dh which acts on channels 0–3,
and 0D A h whic h ac ts on ch ann els 4– 7.
5.3.6.3 Clear Mask Register
This command clears the mask bits of all four channels, enabling them to accept DMA
requests.
I/O port 00Eh is used for channels 03 and I/O port 0DCh is used for channels 4–7.
5.4 LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and
special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment
modes are supported on the LPC interface. Channels 0 – 3 are 8 bit channels. Channels
5 – 7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
5.4.1 Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the
LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own
dedicated LDRQ# signal (they may not be shared between two separate peripherals).
The Intel® 6300ESB ICH has two LDRQ# inputs, allowing at least two devices to
support DMA or bus mastering.
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LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 12 the peripheral
uses the following serial encoding sequence:
Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high
during idle conditions.
The next 3 bits contain the encoded DMA channel number (MSB first).
The next bit (ACT) indicates whether the request for the indicated DMA channel is
active or inactive. The ACT bit will be a 1 (high) to indicate when it is active and 0
(low) when it is inactive. The case where ACT is low will be rare, and is only used to
indi ca te that a previo u s reques t for that chann el is bein g aba ndo ne d.
After the active/inactive indication, the LDRQ# signal must go high for at least 1
clo ck. Afte r tha t one cl ock, LDRQ# signa l may be bro ught l ow to the nex t encodi ng
sequence.
When an ot her DMA c ha nne l al so nee d s to req ue st a tr an sf e r, anot he r sequ en ce may be
sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then
channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the
peripheral may send the encoded request for channel 3. This allows multiple DMA
agents behind an I/O device to request use of the LPC interface, and the I/O device
does not need to self-arbitrate before sending the message.
5.4.2 Aband oning DMA Requests
DMA Requests may be deasserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit set to ‘0’, or normally through a SYNC field during
the DMA transfer. This section describes boundary conditions where the DMA request
needs to be removed prior to a data transf er.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as ‘0’. However, since the DMA request
was seen by the Intel® 6300ESB ICH, there is no ensuring that the cycle has not been
granted and will shortly run on LPC. Therefore, peripherals must take into account that
a DMA cycle may still occur. The peripheral may choose not to respond to this cycle, in
which case the host will abort it, or it may choose to complete the cycle normally with
any random data.
This method of DMA deassertion should be prevented whenever possible, to limit
bound ary conditions both on the Intel® 6300ESB ICH and the peripheral.
Figure 1 2. DMA Request Assertion Through LDRQ#
Start MSB LSB ACT Start
LCLK
LDRQ#
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5.4.3 General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begin s the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. The Intel® 6300ESB ICH starts transfer by asserting ‘0000b’ on LAD[3:0] with
LFRAME# asserted.
2. The Intel® 6300ESB ICH asserts ‘cycle type’ of DMA, direction based on DMA
transfer direction.
3. The Intel® 6300ESB ICH asserts channel number and, when applicable, terminal
count.
4. The Intel® 6300ESB ICH indicates the size of the transfer: 8 or 16 bits.
5. When a DMA read
—The Intel
® 6300ESB ICH dr ives the first 8 bits of d a ta and turn s the bus around .
The peripheral acknowledges the data with a valid SYNC.
When a 16 bit transfer, the p rocess is repeated for the ne x t 8 bits .
6. When a DMA write…
—The Intel
® 6300ESB ICH turns the bus around and waits for data.
The peripheral indicates data ready throug h S YNC and transf ers the first b yte.
When a 16 bit transfer, the p er ip he ral indica tes dat a ready and transfe rs th e next byte.
7. The peripheral turns around the bus.
5.4.4 Terminal Count (TC)
Termin al count i s commu nicated th rough LA D[3] on th e s ame clock that DMA c hannel i s
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an eight bit transfer size (SIZE field is ‘00b’), when the TC bit is set,
t his is the las t by te. O n a 16 bit transfer (SIZE f i eld i s ‘01 b’), when the T C bit is set, th e
second byte is the last byte. The peripheral, therefore, must internalize the T C bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
5.4.5 Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
5.4.6 DMA Request Deassertion
An e nd of tr a nsfer is co mmunic ated to the Intel® 6300ESB ICH th roug h a sp ecial SYNC
field tr ansmitted by the peripheral. An LPC device must not attempt to signal the en d of
a transfer by deasserting LDREQ#. When a DMA transfer is several bytes, such as a
transfer from a demand mode device, the Intel® 6300ESB ICH needs to know when to
deassert the DMA request based on the data currently being transferred.
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The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the Intel® 6300ESB ICH whether this is the last byte of transfer or when
more bytes are requested. To indicate the last byte of transfer, the peripheral uses a
SYNC value of ‘0000b’ (ready with no error), or ‘1010b’ (ready with error). These
encodings tell the Intel® 6300ESB ICH that this is the last piece of data transferred on
a DMA read (Intel® 6300ESB IC H to peripheral), or the byte which follows is the last
piece of data transferred on a DMA write (peripheral to the Intel® 6300ESB ICH).
When the Intel® 6300ESB ICH sees one of these two encodings, it ends the DMA
transfer after this byte and deasserts the DMA request to the 8237. Therefore, when
the Intel ® 6300ES B ICH i ndi cate d a 1 6 bi t tr a nsfe r, the p er ipher al ma y en d the tr a nsfer
after one by te by indicating a SYNC value of ‘0000b’ or ‘1010b. The Intel® 6300ESB
ICH will not attempt to transfer the second byte, and will deassert the DMA request
internally. This also holds true for any byte in a 32 bit transfer. This allows the
peripheral, therefore, to terminate a DMA burst.
When t he per iph er al ind i cate s a ‘0000 b’ o r ‘1010b’ SYNC p at tern on the las t by te of the
indicated size, then the Intel® 6300ESB ICH will only deassert the DMA request to the
8237 since it does not need to end the transfer.
When the peripheral wishes to keep the DMA request active, it uses a SYNC value of
‘100 1b’ (re ady p lus mor e d ata). Thi s tells the 8237 that m ore da ta byte s are reques ted
after the current byte has been transferred, so the Intel® 6300ESB ICH will keep the
DMA request active to the 8237. Therefore, on an 8-bit transfer size, when the
peripheral indicates a SYNC value of ‘1001b to the Intel® 6300ESB ICH, the data will
be transferred and the DMA request will remain active to the 8237. At a later time, the
Intel® 6300 ESB ICH w i ll t hen c om e b ack wi th anoth er STAR TCYCTYPECHANNELSIZE
etc. combination to initiate another transfer to the peripheral.
The peripheral must not assume that the next START indication from the Intel®
6300ESB ICH is another grant to the peripheral when it had indicated a SYNC value of
‘1001b’. On a single mode DMA device, the 8237 will rearbitrate after every transfer.
Only demand mode DMA devices may be ensured that they will receive the next ST ART
in di c ati on fr o m th e In t el® 6300ESB ICH.
Note: Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit
channel (first byte of a 16 bit transfer) is an error condition.
Note: The host will stop the transfer on the LPC bus as indicated, fill the upper byte with
random data on DMA writes (peripheral to memory), and indicate to the 8237 that the
DMA transfer occurred, incrementing the 8237’s address and decrementing its byte
count.
5.4.7 SYNC Field/LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is
ind icat ed th rough t he SYNC f iel d. Thi s is nee ded to al lo w the 8 237, whic h typ ica lly r uns
off a much slower internal clock, to see a message deasserted before it is re-asserted
so that it may arbitrate to the next agent.
Under default operation, the host will only perform 8-bit transfers on 8-bit channels
and 16-bit transfers on 16 bit channels.
The m ethod by w hi ch t his c ommun ic atio n b etween h os t an d pe rip her al thro ug h sys te m
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.
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Th e per ip hera l must no t a ssum e th at the hos t w ill b e a ble t o pe rfor m tr an sfe r s iz es tha t
are larger than the size allowed for the DMA channel, and be willing to accept a SIZE
field that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices which may appear on the LPC bus,
which require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
5.5 825 4 Ti mers (D31:F0)
The Intel® 6300ESB ICH contains three counters which have fixed uses. All registers
and functions associated wit h the 8254 timers are in the core well. The 8254 unit is
clocked by a 14.31818 MHz clock. The 14.31818 MHz clock will stop during the S3-S5
and G3 states.
5.5.1 Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a per iod equa l to th e prod uc t of the co unt er p erio d (83 8 ns) and the ini ti al co unt valu e.
The counter loads the initial count value one counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decre ments the count value by two each counter period. The counter negates IRQ0
when the count value reaches zero. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches zero, reloads the initial count value, and
repeats the cycle, alternately asserting and negating IRQ0.
5.5.2 Counter 1, Refresh Request Signal
Prior to ICH1, typically in ISA platforms, this counter provided the refresh request
signal. Today, it is still typically programmed for Mode 2 operation and only impacts the
period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter
period after being written to the counter I/O address. The REF_TOGGLE bit will have a
square wave behavior (alternate between 0 and 1) and will toggle at a rate based on
the value in the counter.
Programming the counter to anything other than Mode 2 will result in undefined
behavi or for the REF_TOGGL E bit. See Section 8.7.1, “NMI_SC—NMI Status and
Control Register” (D31:F0:61h:bit 4) for REF_TOGGLE bit details.
5.5.3 Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a w rit e to po rt 06 1h ( se e Secti on 8.7. 1, “NMI_S C —N MI Status and C o ntrol R e gis te r”
for more information).
5.5.4 Timer Programming
The counter/timers are programmed in the following fashion:
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1. Write a control word to select a counter.
2. Write an initial count for that counter.
3. Load t he l e ast an d/or mo st s i gn if i ca n t by t es (as req ui r e d by C ontro l Word b it s 5 , 4)
of the 16-bit counter. See Section 8.3, “Timer I/O Registers” for more information.
4. Repeat with other counters.
Only two conventions need to be observed when programming the counters. First, for
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).
A new initial count may be written to a counter at any time without affecting the
counter's programmed mode. Counting will be affect ed as described in the mode
definitions. The new count must follow the programmed count format.
When a counte r is prog r ammed to re ad/wri te two- byte c oun ts, t he fol l owing p re cauti on
app l ies : A prog ra m m ust not tr ans f er co nt ro l b et we en writi n g the fi rs t and se con d by te
to ano the r r ou ti ne whi c h a lso wr it es i nto t hat sa me c ount er. O ther wis e, the c ounter wi ll
be loaded with an incorrect count.
The Control Word Register at port 43h controls the operation of all three counters.
Sev eral co mman ds ar e availa ble :
Control Wo rd Com mand. Specifies which counter to read or write, the operating
mode, and the count format (binary or BCD).
Counter Latch Command. Latches the current count so that it may be read by
the system. The countdown process continues.
Read Back Command. Reads the count value, programmed mode, the current
state of the OUT pins, and the state of the Null Count Flag of the selected counter.
Table 40 list s the six op era t ing mod es for the in te r val cou nte r s.
5.5.5 Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in
progress. There are three methods for reading the counters: a simple read operation,
counter Latch command, and the Read-Back command. Each is explained below.
Table 40. Counte r Operating Modes
Mode Function Description
0 Out signal on end of count (=0) Output is ‘0’. Wh en count goes to 0, outp ut goes
to ‘1’ and stays at ‘1’ until counter is
reprogrammed.
1 Hardware retriggerable one-shot Output i s ‘0’. When count goes to 0, output go es
to ‘1 for one clock peri od .
2Rate generator (divide by n
counter) Output is ‘1’. Output goes to ‘0’ for one clock
time , the n bac k to ‘1’ and count er is reload e d.
3Square wave output
Output is ‘1. Output goes to ‘0’ when counter rolls
over, and counter is reloaded. Output goes to ‘1’
when counter rolls over, and counter is reloaded,
etc.
4 So f t war e tr igg e red st robe Output is ‘1’. Output goes to ‘0’ when count
expires for one clock period.
5 Hardware triggered strobe Output is ‘1’. Output goes to ‘0’ when count
expires for one clock period.
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With the simple read and counter latch command methods, the count must be read
according to the programmed format; specifically, when the count er is progra mmed for
two byte counts, two bytes must be read. The two bytes do not have to be read one
rig ht aft er th e other. R ead, w rite, or prog ram mi ng ope rations for othe r counte rs may be
inserted between them.
5.5.5.1 Simple Read
Th e fi rst meth od is to pe rfor m a s imp le r ead ope ra ti on. The co unter is se lec te d t hroug h
port 40h (counter 0), 41h (counter 1), or 42h (counter 2).
Note: Performing a direct read from the counter will not return a determinate value, because
the counting process is asynchronous to read operations. However, in the case of
counter 2, the count may be stopped by writing to the GATE bit in port 61h.
5.5.5.2 Counter Latch Command
The Counter Latch Command, written to port 43h, latches the count of a specific
counter at the time the command is received. This command is used to ensure that the
count read from the counter is accurate, particularly when reading a two-byte count.
The count value is then read from each counter's Count Register as was programmed
by the Control Register.
Th e coun t i s hel d in t he latch unt il i t is r ead or th e coun te r is repr ogr am med . The co unt
is then unlatched. This allows reading the contents of the counters on the fly without
affecting counting in progress. Multiple Counter Latch Commands may be used to latch
more than one counter. Counter Latch commands do not affect the programmed mode
of the counter in any way.
When a Counter is latched and then, some time later, latched again before the count is
read, the second Counter Latch command is ignored. The count read will be the count
at the time the first Counter Latch command was issued.
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5.5.5.3 Read Back Command
The Read Back command, written to port 43h, latches the count value, prog rammed
mode, and current states of the OUT pin and Null Count flag of the selected counter or
counters. The v alue of the counter and its status may then be read by I/O access to the
counter address.
The Read Back command may be used to latch multiple counter outputs at one time.
This single command is functionally equivalent to several counter latch commands, one
for each counter latched. Each counter's latched count is held until it is read o r
reprogrammed. Once read, a counter is unlatched. The other counters remain latched
until they are read. When multiple count Read Back commands are issued to the same
counter without reading the count, all but the first are ignored.
The Read Back command may additionally be used to latch status information of
selected counters. The status of a counter is accessed by a read from that counter's I/
O port address. When multiple counter status latch operations are performed without
reading the status, all but the first are ignored.
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands.
When multiple count and/or status Read Back commands are issued to the same
counters without any intervening reads, all bu t the first are ignored.
When both count and status of a counter are latched, the first read operation from that
counter will return the latched status, regardless of which was latched first. The next
one or two reads, depending on whether the counter is programmed for one or two
type counts, return the latched count. Subse quent reads return unlatched count.
5. 6 8259 Interrupt Con tro l le rs (P IC) (D3 1: F0)
The Intel® 6300ESB ICH incorp orat es the func tional it y of two 82 59 interrup t contro llers
that provide system interrupts for the ISA compatible interrupts. These interrupts are:
system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse,
and DMA channels. In addition, this interrupt controller may support the PCI based
interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each
8259 core supports eight interrupts, numbered zero through seven. Table 41 sho ws
how the cores are connected.
.
Table 41. Interrupt Controller Core Connections (Sheet 1 of 2 )
8259 8259
Input Typical I nterrup t
Source Co nn e cte d P i n / F u nctio n
Master
0 Internal Internal Timer / Counter 0 output / MMT #0
1 Keyboard IRQ1 via SERIRQ
2 Internal S lave Controller INTR output
3 Serial Port A IRQ3 via SERIRQ, PIRQx
4 Serial Port B IRQ4 via SERIRQ, PIRQx
5 P arallel Port / Generic IRQ5 via SERIRQ, PIRQx
6 Floppy Disk IRQ6 v ia SERIRQ PIRQx,
7 P arallel Port / Generic IRQ7 via SERIRQ PIRQx,
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The Intel® 6300ESB ICH cascades the slave controller onto the master controller
through master controller interrupt input two. This means there are only 15 possible
interrupts for the Intel® 6300ESB ICH PIC.
Interrupts may individually be programmed to be edge or level, except for IRQ0, IRQ2
and IRQ8#.
Note that previous PIIXn devices internally latched IRQ12 and IRQ1 and required a port
60 h read to clear the latch. The Intel® 6300ESB ICH may be programmed to latch
IRQ12 or IRQ1 (see bit 11 and bit 12 in General Control Register, D31:F0, offset D0h).
5.6.1 Interrupt Handling
5.6.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending inte rrupts. Table 42 defines the IRR, ISR and IMR.
Slave
0Internal Re al Time
Clock Internal RT C / MMT #1
1 Generic IRQ9 via SERIRQ, SCI or TCO , PIRQx, Boot
Interrupt
2 Generic IRQ10 via SERIRQ, S CI, or TCO, PIRQx
3 Generic IRQ11 via SERIRQ, SCI, or TCO, PIRQx,
Multimedia Timer #2
4 PS/2 Mouse IRQ12 via SERIR, SCI, or TCO, PIRQx
5 Internal State M achine outp ut b a se d on pr oce ss or FERR#
assertion. See Section 5.8.4, “Specif ic Interrupts
Not Sup po rted via SERIRQ” for more informa tion.
6Primary IDE cableIRQ14 from in p ut sig n al (p rimary IDE in legac y
mode only ) or v ia S ERIRQ PIRQx
7 Secon dar y IDE Cable IRQ15 from input signal (secondary IDE in legacy
mode only ) or v ia S ERIRQ, PIRQx
Table 41. Interrupt Controller Core Connections (Sheet 2 of 2)
8259 8259
Input Typical Interru pt
Source Connected Pin / Function
Table 42. Interrupt Status Registers
Bit Description
IRR In ter rupt Request Register. This bit is set on a low to high transition of the interrupt
line in edge mode, and by an active high level in level mode. This bit is set whether or
not the in terrup t is masked. However, a masked interrupt will not generate IN TR.
ISR Interru pt Serv ice Register. This bit is set, and the corresponding IRR bit cleared,
wh e n an int errup t a ck nowle d g e cycle is se en , an d the vect or re turne d is for tha t
interrupt.
IMR Interrupt Mask Register. This bit de te rmines whe the r a n in te rrup t is masked.
Mas ked inte rru p ts will n ot g en erate IN TR.
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5.6.1.2 Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle which is translated by t he host
bridge into a PCI Interrupt Acknowledge Cycle to the Intel® 6300ESB ICH. The PIC
translates this command into two internal INTA# pulses expected by the 8259 cores.
The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for
priority resolution. On the second INTA# pulse, the master or slave will send the
interrupt vector to the processor with the acknowledged interrupt code. This code is
based upon bits [7:3] of the corresponding ICW2 register, combined with three bits
representing the interrupt within t hat controller.
5.6.1. 3 Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor when an asserted interrupt is not
masked.
3. The p r oce s so r ack n ow l edg e s the I NT R and re s pon ds wi t h an in t e rr up t ac kn ow le d ge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by the Intel® 6300ESB ICH.
4. Upon observing its own interrupt acknowledge cycle on PCI, the Intel® 6300ESB
ICH con verts it in to the two cycles that t he interna l 82 59 pa ir may respo nd to. Ea ch
cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the
casc aded in te rr up t con tro ll er s.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine when it must respond with an interrupt vector during the second INT A#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. When no interrupt request is present because the request was too
short in duration, the PIC will return vector 7 from the master controller.
7. This completes the interrup t cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
5.6.2 Initialization Command Words (ICWx)
Bef ore ope ra ti on may b egi n, eac h 8 259 mus t b e ini ti ali zed . I n t he Int el ® 6 300ESB I C H,
this is a four byte sequence. The four initialization command words are referred to by
their acronyms: ICW1, ICW2, ICW3, and ICW4.
Table 43. Content of Interrupt Vector Byte
Master, Slave In terrupt Bits [7:3] Bits [2:0]
IRQ7,15
ICW2[7:3]
111
IRQ6,14 110
IRQ5,13 101
IRQ4,12 100
IRQ3,11 011
IRQ2,10 010
IRQ1,9 001
IRQ0,8 000
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Th e base add ress f or each 8259 initi ali zat ion comm and word is a fixe d loca tion i n the I/
O memory space: 20h for the master controller, and A0h for the slave controller.
5.6.2.1 ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the Intel® 6300ESB ICH PIC
expects three more byte writes to 21h for the master controller, or A1h for the slave
controller, to complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
t ransition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
5.6.2.2 ICW2
The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
5.6.2.3 ICW3
The third write in the sequence, ICW3, has a different meaning for each controller.
For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the Intel® 6300ESB ICH, IRQ2 is used.
Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits
are set to 0s.
For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller when the cascaded interrupt
won arbitration on the master controller. The slave controller compares this
identification code to the value stor ed in its ICW3, and when it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
5.6.2.4 ICW4
The final write in the sequence, ICW4, must be programmed both controller s. At the
very least, bit 0 must be set to one to indicate that the controllers are operating in an
Intel® Architecture-based system.
5.6.3 Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various
interrupt modes.
OCW1 masks and unmasks interrupt lines.
OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
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OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM),
and enables/disables polled interrupt mode.
5.6.4 Modes of Operation
5.6.4.1 Fully Nested Mode
In this mode, interrupt requests are ordered in priority from zero through seven, with
zero being the highest. When an interrupt is acknowledged, the highest priority request
is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the processor issues an EOI command immediately
before returning from the service routine; or when in AEOI mode, on the trailing edge
of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels will generate another interrupt.
Interrupt priorities may be changed in the rotating priority mode.
5.6.4.2 Special Fully-Nested M ode
This mode will be used in the case of a system where cascading is used, and the
priority has to be conserved within each slave. In this case, the special fully-nested
mode will be pro grammed to the master controller. This mode is similar to the fully-
nested mode with the following exceptions:
When an interrupt request from a certain slave is in service, this slave is not locked
out from the master's priority logic and further interrupt requests from higher
priority interrupts within the slave will be recognized by the master and will initiate
interrupts to the processor. In the normal-nested mode, a slave is masked out
when its request is in service.
When exiting the Interrupt Service routine, software has to check whether the
interrupt serviced was the only one from that slave. This is done by sending a Non-
Specific EOI command to the slave and then reading its ISR. When it is zero, a non-
specific EOI may also be sent to the master.
5.6.4.3 Automatic Rotation Mode (Equ al Priority Devices)
In some applications, there are a number of interrupting devices of equal priority.
Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt will have to wait until each of seven other devices are serviced
at most once.
There are two ways to accomplish automatic rotation using OCW2; the Rotation on
Non-Specific EOI Command (R=1 , SL=0, EOI=1) and the rotate in automatic EOI mode
which is set by (R=1, SL=0, EOI=0).
5.6.4.4 Specific Rotation Mode (Spec i fic Priority)
Software may change interrupt priorities by programming the bottom priority. For
example, when IRQ5 is programmed as the bottom priority device, IRQ6 will be the
highest priority device. The Set Prio rity Command is issued in OCW2 to accomplish this,
where: R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority
device.
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In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes may be executed during an EOI
command by using the R otate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1
and LO-L2=IRQ level to receive bottom priority.
5.6.4.5 Poll Mode
Poll mode may be used to conserve space in the interrupt vector table. Mult iple
interrupts that may be serviced by one interrupt service routine do not need separate
vectors when the service routine uses the poll command. Poll mode may also be used
to expand the number of interrupts. The polling interrupt service routine may call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit when there is a request, and
reads the priority lev el. Interrupts are frozen from the OCW3 writ e to the I/O read. The
byte returned during the I/O read will contain a ‘1’ in bit 7 when there is an interrupt,
and the binary code of the highest priority level in bits 2:0.
5.6.4.6 Cascade Mode
The PIC in the Intel® 6300E SB ICH ha s one mast er 8259 and one sl av e 8259 cascaded
onto the master through IRQ2. This configuration may handle up to 15 separate
priority levels. The master controls the slaves through a three bit internal bus. In the
Intel® 6300ESB ICH, when the master drives 010b on this bus, the slave controller
t ake s responsibil i ty for re tur nin g th e i nte rr up t ve cto r. A n EOI comm and must b e issue d
twice: once for the master and once for the slave.
5.6.4.7 Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In the Intel® 6300ESB ICH, this bit is disabled and a new
register for edge and level triggered mode selection, per interrupt input, is included.
This is the Edge/Level control Registers ELCR1 and ELCR2.
When an ELCR bit is ‘0, an interrupt request will be recognized by a low to high
transition on the corresponding IRQ input. The IRQ input may remain high without
generating another interrupt. When an ELCR bit is ‘1’, an i nterrupt request will be
recognized by a high level on the corresponding IRQ input and there is no need for an
edge detection. The interrupt request must be removed before the EOI command is
issued to prevent a second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. When the IRQ input goes inactive
before this time, a default IRQ7 vector will be returned.
5.6.4.8 End of Interrupt Operations
An EOI may occur in one of two fashions: by a command word write issued to the PIC
before returning fro m a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to one.
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5.6.4.9 N ormal E n d of Interr upt
In Normal EOI, software writes an EOI command before leaving the interrupt service
routine to m ark the interrupt as completed. There are two form s of EOI commands :
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC will
clear the highest ISR bit of those that are set to one. Non-Specific EOI is the normal
mode of operation of the PIC within the Intel® 6300ESB ICH, as the interrupt being
serviced currently is the interrupt entered with the interrupt acknowledge. When the
PIC is operated in modes which preserve the fully nested structure, software may
determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked
will not be cleared by a Non-Specific EOI when the PIC is in the special mask mo de. An
EOI command must be issued for both the master and slave controller.
5.6.4.10 Au tomatic End of Interru pt Mode
In this mode, the PIC will automatically perform a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode may only be used in the master controller and not
the slave controller.
5.6.5 Masking Interrupts
5.6.5.1 Masking on an Individual Interrupt Request
Eac h inter rup t reques t may be mas ked in divi duall y by the Interr upt Mask Registe r
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller will mask all requests for
service from the slave controller.
5.6.5.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked b y a bit set in the Mask
Register. Normally, when an interrupt service routine acknowledges an interrupt
without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower
priority requests. In the special mask mode, any interrupts may be selectively enabled
by loading the Mask Register with the appropriate pattern. The special mask mode is
set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.6.6 Stee ring PCI Interru pts
The Intel® 6300ESB ICH may be programmed to allow PIRQA#-PIRQH# to be
internally routed to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable
thr ough the PIRQ x R oute Con trol regis ters, loc ated at 60-63 h and 68-6Bh in f unction 0.
One or more PIRQx# lines may be routed to the same IRQx input. When interrupt
steering is not required, the Route Registers may be programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI Board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
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sensitive mode. The Intel® 6300ESB ICH will internally invert the PIRQx# line to send
an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the
selected IRQ may no longer be used by an ISA device (through SERIRQ). However,
active low n on-ISA interrupts may share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. The Intel® 6300ESB ICH receives the PIRQ input, like all of the
other external sources, and routes it accordi ngly.
5.6.7 Special Handling of IRQ1 and IRQ12
IRQ1 and IRQ12 interrupts are treated in a slightly different fashion from other
interrupts in the system. In a legacy PC environment, these interrupts were not held
active until serviced, but rather pulsed whenever a key or button was pressed. In
newer systems, this pulsing is no longer done. However, the Intel® 6300ESB ICH must
still handle old keyboard controllers which perform the pulse operation. Therefore, the
Intel® 6300ESB ICH contains logic which may sample and hold these interrupts when
so required.
Two register bits in configuration register D0h in function 0 enable the latching of IRQ1
and 12. IRQ1 may optionally be latched through bit 12, and IRQ12 may optionally be
latched through bit 11. When these bits are set, the corresponding interrupt is held to
t he 8259 unti l a n I/O re ad fr om po rt 60 is se en. Th e port 60 read i s an i ndi cati on to th e
keyboard controller that the interrupt has been serviced.
Another item to note is that on previous components (ICHx), it was always ensured
that the keyboard controller would exist behind the Intel® 6300ESB ICH on the ISA
bus. On Intel® 6300ESB ICH, this is not the case. Ther efore, the clearing of the latch
must be done through a snoop of port 60h. The waveform which performs this snoop is
shown in Figure 13. Note tha t the s igna l which indi cates t hat a port 60 rea d occur red is
only one PCI clock wide. This cannot be a handshake signal because the Intel®
6300ESB ICH is not necessarily responding to the cycle.
Figure 13. Port 60 Read Clearing IRQ1 AND IRQ12 Latch
60 Data
2 E
0ns 50ns 100ns 150ns 200ns 250ns
3
PCICLK
AD
C/BE#
FRAME#
IRDY#
TRDY#
port60read
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5.7 Adv anced Inte rrupt Contro ller (APIC)
(D29:F5)
There are two APICs in the Intel® 6300E SB ICH: APIC 0 and APIC 1 (devi ce 29, f uncti on
5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, only
primary (legacy) PCI devices can write to these registers. APIC1’s direct register are
assigned with base address FEC1xxxxH. To suppo rt legacy devices/drivers o n the PCI-X
segment used with the Intel ICHx, APIC1 has an alternate base address FEC0xxxxH.
This means devices on t he PCI-X segment can only write to the IRQ Pin Assertion
Register (either FEC0_0020H or FEC1_0020H) to generate an interrupt from APIC1.
APIC1 w rit es to a ddre sse s FEC1_00 20 to FEC1 _0027 are claim ed by APIC 1 from PCI - X .
Devic es on the prim ary PCI B us can wri te to IR Q Pi n Ass ert ion Register F EC0_00 20H to
generate an APIC0 interrupt. Devices/drivers on the PCI-X segment have write access
only to the APIC1 IRQ Pin Assertion Register. Devices/drivers on the PCI segment can
access only APIC0 registers. Since the Intel® 6300ESB ICH does not implement Hub
Interface EOI special cycles, the MCH will translate EOI special cycle to a memory write
cycle to EOI register at address FEC0_0040H and passes it to the Intel® 6300E SB ICH.
This memory write cycle will be passed to both APIC0 and APIC1 internally.
From the CPU/MCH point of view, it should always use address FEC0xxxxH to access
APIC0 registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not
respond to CPU/MCUs access to address FEC0xxxxH, other than the EOI cycle stated
above.
5.7.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
Method of Interrupt Transmissi on. Interrupts are handled without the need for
the pr oc ess or to run a n int err upt ac knowle dge cycle. The In tel® 6300 ESB ICH only
supports FSB delivery of interrupts.
Interrupt Priority. The priority o f interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 may be given a higher priority than
interrupt 3.
More Interrupts. The I/O APIC in the Intel® 6300ESB ICH supports a total of 24
interrupts.
Multiple Interr upt Con trollers. Th e I/ O APIC i nt err upt transmis sion pro toc ol ha s
an arbitration phase, which allows for multiple I/O APICs in the system with their
own interrupt vectors. Th e Intel® 6300ESB ICH I/O APIC must arbitrate for the
APIC bus before transmitting its interrupt message.
5.7.2 SMI/NMI /INIT/ExtINT Delivery Modes
These delivery modes are not supported by the Intel® 6300ESB ICH for the following
reasons:
NMI/INIT: This signal has issues with delivery under power manage ment. It cannot be
delivered while the processor is in the Sto p Grant state. In addition, this is a break
event for power management. Breaking on the APIC bus message is more difficult than
breaking on the pin.
SMI: On the 82093 , the I/O APIC could deli ver th e SMI th roug h th e pin SM IOUT# or a s
an APIC bus message. When the message was masked by the OS, then the SMIOUT#
will be used. In other words, there is no way to block the delivery of the SMI#, except
through BIOS. Adding this interrupt to the I/O APIC only increases validation time.
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5.7.3 Boot Interrupt
The Intel® 6300ESB ICHs APIC1 contains a capability to logically OR several of its
interrupt inputs together to generate a single interrupt through PIC. This is necessary
for systems that do not support the APIC, and for boot. The generated interrupt is
routed to IRQ 9.
This interrupt is generated when the following conditions met:
Boot interrupt is enabled in configuration register.
Any of PXIRQ[3:0] or internal interrupt source is asserted.
Boot interrupts are not MASKed in redirection table. (Refer to Bit 16 in the
Redirection Table)
IRQ9 of PIC is enabled with bit 6 set to 0 of the ET R1- Extended Featur es Register,
D: 31:F0 :offse t F4h,bi t 6 or PIRQG# i s assigne d to an enable d IRQx of the PIC with
ET R1 bit 6 s et to 1. See Se ction 8.1. 37, “Offs et F4: ET R1—P CI - X Extend ed F eatures
Register (LPC I/F—D31:F0)” for more information.
To support this function, all internal interrupt sources to APIC1 are level trigger, active
low signals immediately after reset.
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5.7.4 Interrupt Mapping
Only level-triggered interrupts can be shared. PCI interrupts (PIRQs and PXIRQs) are
inherently shared on the board; these should, therefore, be programmed as level-
triggered.
The following tables show the mapping of the various interrupts in Non-APIC and APIC
modes.
There are two APICS within the Intel® 6300ESB ICH supporting 24 APIC interrupts
each. AP IC0 a nd APIC 1 (Device 29 Functi on 5). APIC0 suppo rts PCI me ss ages inter rupt
from external device. Each interrupt has its own unique vector assigned by software.
The interrupt vectors are mapped as follows.
Table 44. Interrupt Mapping in Non-APIC
Non-A PIC Mode
IRQ # Via SERIRQ Direct from
Pin Inte rna l M odule s
0 N o No 82 54 Counte r 0, MMT #0
1YesNo
2 N o No 82 59 #2 cascade only
3YesNoOption for PIRQx
4YesNoOption for PIRQx
5YesNoOption for PIRQx
6YesNoOption for PIRQx
7YesNoOption for PIRQx
8 No No R T C, MMT#1
9 Yes No Option for PIRQx, SCI, TCO, boot interrupt
10 Yes No Op tion f o r PIRQ x , S CI, T CO
11 Yes No Option for PIRQx, SC I , TC O , MMT #2
12 Yes No Op tion f o r PIRQ x
13 No No FERR# Logic
14 Yes Yes3PIRQx, Storage (IDE/SATA ) Primary (legacy mode)
15 Yes Yes3PIRQx, Storage (IDE/SATA) Secondary (legacy
mode)
NOTES:
1. If an interrupt is used for Boot interrupt, PCI IRQ[A:H], SCI, or TCO, it should not be used f or
ISA-style inte rrupts (via SERIRQ or IRQ14/15 pi ns). IRQ9 will be defau lt to bo ot inte rru p t.
2. In non-APIC mode, the PCI interrupts are mapp ed to IRQ3, 4, 5, 6, 7, 9, 10, 11, 12, 1 4, or
15.
3. IRQ 14 and 15 can only be driven directly from the pins when i n Legacy IDE mode.
4. If IRQ11 is used fo r MMT #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of MMT #2. The Intel® 6300ESB ICH does not
prevent s haring o f IRQ 11 .
5. SW: Boot interrupt may optionally be routed to PIRQG # outp ut f or p rog ra mmable PIRQx#
mapping.
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5.7.5 APIC Bus Functional Description
Table 45. APIC Interrupt Mapping, APIC0 Agent
IRQ # Via
SERIRQ Direct
from pin Via PCI
message Internal Modules
0 N o No No Cascad e fr om 8259 #1
1 Yes No No2
2 N o No No 8254 Counter 0, MMT #0 (legacy mode)
3 Yes No No2
4 Yes No No2
5 Yes No No2
6 Yes No No2
7 Yes No No2
8No No NoRTC, MMT #1 (legacy mode)
9 Yes No No2Option for SCI, TCO
10 Yes No No2Option for SCI, TCO
11 Yes No No2Option f or SCI, TCO, MMT #2
12 Yes No No2
13 No No No FERR# logic
14 Yes Yes1No2Storage (IDE/SATA) Primary (legacy mode )
15 Yes Yes1No2Storage ( IDE/SATA) Secondary (legacy mode)
16 PIR Q[A ]# PIRQ[A]# No USB1 U HCI Controller #1
17 PIR Q[B ]# PIRQ[B ]# N o A C’97 Audio, Modem, option f or S M b us
18 PIRQ[C]# PIRQ[C]# No Storage (IDE/SATA) native mode
19 PIRQ[D]# P I RQ[D ]# No USB 1.0 UHCI Controller #2
20 N/A PIRQ[E]# No2Option for SCI, TCO, MMT #0,1,2
21 N/A PIRQ[F]# No2Option for SCI, TCO, MMT #0,1,2
22 N/A PIRQ[G]# No2Option for SCI, TCO, MMT #0,1,2
23 N/A PIRQ[H]# No2USB 2.0 EHCI Controller, option for SCI, TCO,
MMT #0,1,2
NOTES:
1. IRQ 14 a nd 15 m ay only be d riv en directly from the pins whe n in Leg a cy IDE mode.
2. NO from external devices, YES of access from processor
3. In APIC mode, the PCI interr up ts A :H are m appe d to IRQ[16:23].
4. When an interrupt is used for PCI IRQ[A:H], SCI, or TCO, it should not be used for ISA-style
int erru p ts (v ia SERIRQ)
5. Wh e n p rog ra mming the polarity of interna l inte rrupt sources on the APIC, in te rrup t s 0
thr oug h 15 re ce iv e ac tive-high internal in te rru p t sources; inte rrupt s 16 th rough 23 rec e ive
active-low internal interrupt source s
6. When IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other
devices to ensure t he proper o peration of MMT #2. The Int el® 6300ESB ICH does not prevent
sha r ing of I RQ 11 .
7. PC I Message interrupts are not prevented by hardware in these cases. However, the s ystem
must not program these interrupts as edge-triggered (as required for PCI message
interrupts) because the internal and external PIRQs on these inputs must be pr ogr am med in
leve l-trig gered modes.
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5.7.5. 1 APIC Bus Arbitra tion
The I/ O A PIC uses one wire a rbitr ation to w in bus owne rshi p. A rot ating prior it y s cheme
is used for APIC bus arbitration. The winner of the arbitration becomes the lowest
pr io r it y ag e nt a nd a ss u mes an arb it r at i on I D o f ze r o. Al l other ag e nts , ex ce p t t h e ag en t
whose arbitration ID is 15, increment their Arbitr ation IDs by one. The agent whose ID
was 15 will take the winner's arbitration ID and will increment it by one. Arbitr ation IDs
are changed only for messages that are transmitted successfully (except for the Low
Priority messages). A message is transmitted successfully when no CS error or
acceptance error was reported for that message.
An APIC agent may use two different priority schemes: Normal or EOI. EOI has the
highest priority. EOI priority is used to send EOI messag es for level interrupts from a
local APIC to an I/O APIC. When an agent requests the bus with EOI priority, all other
agents requesting the bus with normal priorities will back off.
Table 46. APIC Interrupt Mapping, APIC 1 Agent
APIC Mode
Supported by APIC1 agent
IRQ # Via SERIRQ Di rect fro m
Pin From PCI
Message In terna l Modu le s
0No PXIRQ0Yes
1No PXIRQ1Yes
2No PXIRQ2Yes
3No PXIRQ3Yes
4No No Yes
5No No Yes
6No No Yes
7No No Yes
8No No Yes
9No No Yes
10 No No Yes WDT
11 No No Yes
12 No No Yes
13 No No Yes
14 No No Yes
15 No No Yes
16 No No Yes
17 No No Yes
18 No No Yes
19 No No Yes
20 No No Yes
21 No No Yes
22 No No Yes
23 No No Yes
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When the Intel® 6300ESB ICH detects a bus idle condition on the APIC Bus, and it has
an interrupt to send over the APIC bus, it drives a start cycle to begin arbitration, by
dri vin g bit 0 to a ‘0’ on an AP ICCL K risi ng e dge. It t hen sampl es bi t 1 . When Bi t 1 was a
zero, then a local APIC started arbitration for an EOI message on the same clock edge
that the Intel® 6300ESB ICH started arbitration. The Intel® 6300E SB I CH has thus lost
arbitration and will stop driving the APIC bus.
When the Intel® 6300ESB ICH did not see an EOI message start, it will start
transferring its arbitration ID, located in bits [27:24] of its Arbitration ID register
(ARBID). Starting in Cycle 2, through Cycle 5, it will tri-state bit 0, and drive bit 1 to a
‘0’ when ARBID[27] is a ‘1’. When ARBID[27] is a ‘0’, it will also tri-state bit 1. At the
end of each cycle, the Intel® 6300ESB ICH will sample the state of Bit 1 on the APIC
bus. When the Intel® 6300ESB IC H did not drive Bit 1 (ARBID[27] = ‘0’), and it
samples a ‘0’, then another APIC agent started arbitration for the APIC bus at the same
time as the Intel® 6300ESB ICH, and it has higher priority. The Intel® 6300ESB ICH
will stop drivin g the APIC bus. Table 47 describes the arbitration cycles .
5.7.5.2 Bus Message Formats
After bus arbitration, the winner is granted exclusive use of the bus and will drive its
message. APIC messages come in four formats, determined by the Delivery Mode bits.
These four messages are of different length, and are known by all APICs on the bus
through the transmission of the Delivery Mode bits:
EOI Message f or L eve l Trig ge red Interrupts
EOI messages are used by local APICs to send an EOI cycle occurring for a level
triggered interrupt to an I/O APIC. This message is needed so that the I/O APIC may
differentiate between a new interrupt on the interrupt line versus the same interrupt on
the interrupt line. The target of the EOI is given by the local APIC through the
transmission of the priority vector (V7 through V0) of the interrupt. Upon receiving this
Table 47. Arbitration Cycles
Cy cl e Bit 1 B it 0 Co mm ent
1 EOI 0 Bit 1 = 1: Normal, Bit 1 = 0: EOI
2NOT (ARBID[27])1
Arbitration ID. When the Inte l® 6300ES B ICH samples
a differe n t value tha n it se nt, it lost arbitration .
3NOT (ARBID[26])1
4NOT (ARBID[25])1
5NOT (ARBID[24])1
Table 48. APIC Message Formats
Message # of
Cycles Delivery
Mode Bits Comments
EOI 14 xxx End of Interrupt transmission from Local APIC to I/O
APIC on Level interrupts. EOI is known by the EOI
bit at the start of arbitration
Short 21 001, 010, 100,
101, 111 I/O APIC delivery on Fix ed, NMI, S MI, Reset, ExtIN T,
and Lowest Priority wit h focus pro cessor me ssages
Lowest
Priority 33 001 Transmission of Lo we st Priority inte rrupts when the
status fie ld indicate s that the p rocessor does not
have focus.
Remote Read 39 011 Message from one Local APIC to another to read
registers.
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message, the I/O APIC res ets th e Re mote IRR bit fo r tha t inte rrup t. When the i nterr upt
signal is still active after the IRR bit is reset, the I/O APIC will treat it as a new
interrupt.
Tabl e 49 . EO I Mes sage
Cy cl e Bit 1 Bit 0 C ommen t s
10 0EOI message
2 - 5 AR BID 1 Arb itra tion I D
6NOT(V7)NOT(V6)
Interr up t vector bits V7 - V0 from re d ire ction
table register
7NOT(V5)NOT(V4)
8NOT(V3)NOT(V2)
9NOT(V1)NOT(V0)
10 NOT(C1) NOT(C 0) Che ck Sum from Cyc le s 6 - 9
11 1 1 Postamble
12 NOT(A) NOT( A) Status Cyc le 0
13 NOT(A1 ) NOT (A1) Statu s Cyc le 1
14 1 1 Idle
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Short Mess a g e
Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT and Lowest
Priority with Focus processor interrupts. The Delivery Mode bits (M2–M0) specify the
message. All short messages take 21 cycles including the idle cycle.
Table 50. Short Message
Cycle B it 1 Bit 0 Comments
1 1 0 Normal Arbitrat ion
2 - 5 ARB ID 1 Arbitration ID
6 NOT(DM) NOT(M2) DM1 = De sti na ti on Mo de from bit 11 o f t he r edi r ec t ion
table register
7NOT(M1)NOT(M0)
M2-M0 = Delivery Mode from bits 10:8 of the
redire ction table re gis te r
8 NOT(L) NOT(TM) L = Level, TM = Trigger Mode
9NOT(V7)NOT(V6)
Interr up t vector bits V7 - V0 from re d ire ction table
register
10 NOT(V5) NOT(V4)
11 NOT(V3) NOT(V2)
12 NOT(V1) NOT(V0)
13 NOT(D7) NOT(D6)
Destin ation fiel d from bits 63 :56 of re d ire ction table
register1
14 NOT(D5) NOT(D4)
15 NOT(D3) NOT(D2)
16 NOT(D1) NOT(D0)
17 NOT(C1) N OT(C0) Checksum for Cycle s 6 - 162
18 1 1 Postamble3
19 NOT(A) NOT(A) Status Cycle 0. See Table 51.
20 NOT(A1) N OT(A1) S tatus Cycle 1. See Table 51.
21 1 1 Idle
NOTES:
1. Whe n D M is 0 (p hysical mod e), cy cles 15 and 16 are the APIC ID and cycles 13 and 14 are
sent as ‘1’. When DM is 1 (logical mode ), cyc le s 13 through 16 are the 8-bit Destination field.
The in te rp re tation of the logical mod e 8-bit Destination field is performed by the local units
us ing th e De stina tion Format Register. Sh orth an d s of “all-incl-s e lf and “all- excl-self” both
use phy sical destina tion mode and a destination fie ld c onta inin g A P IC ID value of all one s.
The se nding APIC knows wh e the r it sh ould (incl) or should not ( excl) respond to its own
message.
2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-
7) . The APIC driving the me ssage provides this ch ecksum. This, in e ss e n ce, is the lowe r two
bits of an adder at the end of the message.
3. This cycle allows all APICs to perform various internal computations based on the information
contain ed in the received message. One of t he com putat ions ta kes the chec ks um of th e data
received in cycles 6 through 16 and compares it with the value in cycle 18. When any APIC
computes a different checksum than the one passed in cycle 17, the APIC will signal an error
on the APIC bus (“00”) in cycle 19. Whe n this occurs, all APICs will assume the message was
never se nt and the sender must try sending the message again, which includes re-arbitrating
for the APIC bus. In lowest priority delivery when t he interrupt has a focus processor, the
focus processor will signal this by driving a 01” during cycle 19. This tells all the other APICs
that the interr upt has bee n accepted , the arbitr ati on i s preem pted , and s hort mes sage for mat
is u sed. Cyc l e 19 an d 20 in dic a tes th e s tat us o f the me ss age, i.e., accept ed , ch eck s u m er r or,
retry or error. The fol lowin g table shows the status signal combinat ions and their meanings
for all d e livery modes .
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Lowest Priority without Focus Processor (FP) Me ssa ge
This message format is used to deliver an interrupt in the lowest priority mode in which
it does not have a Focus Process. Cycles 1 through 21 for this message is same as for
the short message discussed above. Status cycle 19 identifies when there is a Focus
processor (10) and a status value of 11 in cycle 20 indicates the need for lowest priority
arbitration.
Table 51. APIC Bus Status Cycle Definition
Delivery Mode A Comments A1 Co mments
Fixed, EOI
11 Che ck sum OK 1 x Err or
01 Accepted
00 Retry
10 Error xx
01 Error xx
00 Checksum Error xx
NMI, SMM, Reset,
ExtINT
11 Che ck sum OK 1 x Err or
01 Accepted
00 Error
10 Error xx
01 Error xx
00 Checksum Error xx
Lowes t Priority
11 Checksum OK: No Focus
Processor 1x Error
01 End and Retry
00 Go for Low P riority Arbitration
10 Error xx
01 Checksum OK: Focus
Processor xx
00 Checksum Error xx
Re mote Read
11 Checksum OK xx
10 Error xx
01 Error xx
00 Checksum Error xx
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Table 52. Lowest Priority Message (Without Focus Processor)
Cycle Bit 1 Bit 0 Comments
1 1 0 Normal Arbitration
2 - 5 ARBID 1 Arbitration ID
6NOT(DM)NOT(M2)
DM = Destination Mode from bit 11 of the redirection
ta ble r eg i s ter.
7NOT(M1)NOT(M0)
M2-M 0 = Deli very Mode fro m bit s 10:8 of the redi re cti o n
ta ble r eg i s ter.
8 NOT(L) NOT(TM) L = Level , TM = Trigger Mode
9NOT(V7)NOT(V6)
Interrupt vector bits V7 - V0 from redirection table
register.
10 NOT(V5) NOT(V4)
11 NOT(V3) NOT(V2)
12 NOT(V1) NOT(V0)
13 NOT(D7) NOT(D6)
Destination field from bits 63:56 o f redirection table
register.
14 NOT(D5) NOT(D4)
15 NOT(D3) NOT(D2)
16 NOT(D1) NOT(D0)
17 NOT(C1) NO T(C0) Checksum for Cycles 6 - 16
18 1 1 Postamble
19 NO T ( A) NO T (A) Sta tu s Cycle 0.
20 N OT(A1) N OT(A1) Status Cycle 1.
21 P7 1
Inverted Processor Priority P7 - P0
22 P6 1
23 P5 1
24 P4 1
25 P3 1
26 P2 1
27 P1 1
28 P0 1
29 ArbID3 1
30 ArbID2 1
31 ArbID1 1
32 ArbID0 1
33 S S Status
34 1 1 Idle
NOTES:
1. Cyc le 21 thro ugh 28 are used t o arbit rate for t he lowest pr iority processor. The proc essor that
takes part in the arbitration drives the processor priority on the bus. Only the local APICs that
have “fre e inte rrupt slots” w ill p articipate in the lowe st priority arbitrat ion.
2. Cyc les 29 through 32 are used to break tie in case two more processors have lowest priority.
The bus arbitration ID's are used to break t he tie.
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Rem ot e Read Message
Remote read message is used when a local APIC wishes to read the register in another
local APIC. The I/O APIC in the Intel® 6300ESB ICH neither generates or responds to
this cycle. The message format is same as short message for the first 21 cycles.
Table 53. Remote Read Message (Sheet 1 of 2)
Cy cl e B it 1 B it 0 Commen t s
1 1 0 Nor ma l A rb itrat ion
2 - 5 ARBID 1 Arbitration I D
6 NOT(DM) NOT(M2) DM = Des tina tion Mode f rom bi t 11 of the re direct ion t able
register.
7NOT(M1)NOT(M0)
M2-M0 = Delivery Mode from bits 10:8 of the redirection
table register.
8 NOT(L) NOT(TM) L = Level, TM = Trigger Mode
9NOT(V7)NOT(V6)
Interr up t vector bits V7 - V0 from re d ire ction table
register.
10 NOT(V5) NOT(V4)
11 NOT(V3) NOT(V2)
12 NOT(V1) NOT(V0)
13 NOT(D7) NOT(D6)
Destin ation fiel d from bits 63 :56 of re d ire ction table
register.
14 NOT(D5) NOT(D4)
15 NOT(D3) NOT(D2)
16 NOT(D1) NOT(D0)
17 NOT(C1) N OT(C0) Chec ksum f or Cy cle s 6 - 16
18 1 1 Postamble
19 NO T(A) NO T(A) Statu s Cyc le 0.
20 NOT(A1) NOT(A1) Status Cycle 1.
21 d31 d30
Remote register data 31-0
22 d29 d28
23 d27 d26
24 d25 d24
25 d23 d22
26 d21 d20
27 d19 d18
28 d17 d16
29 d15 d14
30 d13 d12
31 d11 d10
32 d09 d08
33 d07 d06
34 d05 d04
35 d03 d02
36 d01 d00
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5.7.6 PCI Message-Based Interrupts
5.7.6.1 Theory of Operation
The following scheme is only su pported when the internal I/O(x) APIC is used, rather
than just the 8259.
The Intel® 6300ESB ICH sup port s the ne w method for PCI devic es to del i ver i nterr upts
as write cycles rather than using the traditional PIRQ[A:D] signals. Essentially, the PCI
devices are given a write path directly to a register that will cause the desired interrupt.
This mode is only supported when the Intel® 630 0ESB ICH’s internal I/O APIC is
enabled. Upon recognizing the write from the peripheral, the Intel® 6300ESB ICH will
send the interrupt message to the processor using the I/O APIC’s serial bus.
Th e in ter rupt s as so ciat ed w ith the P CI M essa ge-b ased in ter rupt met hod m us t be s et up
for edge triggered mode, rather than level triggered, since the peripher al only does the
write to indicate the edge.
The following sequence is used:
1. During PCI PnP, the PCI peripheral is first progr ammed with an address
(MESSAGE_ADDRESS) and data value (MESSAGE_DATA) that will be used for the
interrupt message delivery. For the Intel® 6300ESB ICH, the MESSAGE_ADDRESS
is the IRQ Pin Assertion Register, which is mapped to memory location:
FEC0_0020h.
2. To cause the interrupt, the PCI peripheral requests the PCI bus and when granted,
writes the MESSAGE_DATA value to the location indicated by the
MESSAGE_ADDRESS. The MESSAGE_DATA value indicates which interrupt
occurred. This MESSAGE_DATA value is a binary encoded. For example, to indicate
that interrupt 7 should go active, the peripheral will write a binary value of
0000111 . The MES SA GE_DA T A will be a 32-bit value, although only the lower 5 bits
are used.
3. When the PRQ bit in the APIC Version Register is set, the Intel® 6300ESB ICH
positively decodes the cycles (as a slave) in Medium time.
4. The Intel® 6300ESB ICH decodes the binary value written to MESSAGE_ADDRESS
and sets the appropriate IRR bit in the internal I/O APIC. The corresponding
interrupt must be set up for edge-triggered interrupts. The Intel® 6300ESB ICH
supports interrupts 00h through 23h. Binary values outside this range will not
cause any action.
5. After sending the interrupt message to the processor, the Intel® 6300ESB ICH will
automatically clear the interrupt.
37 S S Data Status: 00 = valid, 11 = invalid
38 C C Chec k Sum f or data d31 -d0 0
39 1 1 Idle
NOTE: Cy cl e 21 thro ug h 36 con ta in t he r emo te reg ist er dat a. The sta tu s in fo rmat i on i n cy cle 37
specifies whe n th e data is vali d or invalid. Rem ote re a d c ycle is always success ful
(although the data may be valid or invalid) in that it is never retried. The reason for this
is that Remote Read is a debug feature, and a “hung” remote APIC that is unable to
respo nd should not cause the de bugge r to hang.
Table 53. Remote Read Message (Sheet 2 of 2)
Cycle Bit 1 Bit 0 Comments
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Since they are edge triggered, the interrupts that are allocated to the PCI bus for this
scheme may not be shared with any other interrupt (such as the standard PCI
PIRQ[A:D], those received via SERIRQ#, or the internal level-triggered interrupts such
as SCI or TCO).
The Intel® 6300ESB ICH will ig nore interrupt messages sent by PCI masters that
attempt to use IRQ0, 2, 8, or 13.
5.7.6.2 Registers and Bits Associated with PCI Interrupt Delivery
Capabilities Indication
The capability to support PCI interrupt delivery will be indicated through ACPI
configuration techniques. This involves the BIOS creating a data structure that gets
reported to the ACPI configuration software. The OS reads the PRQ bit in the APIC
Version Register to see when the Intel® 6300ESB ICH is capable of supporting PCI-
based interrupt messages.
Interrupt Me ssage Register
The PCI devices will all write their message into the IRQ Pin Assertion Register, which is
a memory-Mapped register located at the APIC base memory location + 20h.
5.7.7 Processor System Bus Interrupt Delivery
5.7.7.1 Theory of Operation
For processors that support Processor System Bus interrupt delivery, the Intel®
6300ESB ICH has an option to let the integrated I/O APIC behave as an I/O (x) APIC.
In this case, it will deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme. The Intel® 6300ESB ICH is intend ed to
be compatible with the I/O (x) APIC specification, Rev 1.1
This is do ne by the In tel® 6300ESB ICH writing (through the Hub Interface) to a
memory location that is snooped by the processor(s). The processor(s) snoop the cycle
to know which interrupt goes active.
The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by
setting the DT bit in the I/O APIC ID register.
The following sequence is used:
1. When the Intel® 6300ESB ICH detects an interrupt event (active edge for edge-
triggered mode or a change for level-triggered mode), it sets or resets the internal
IRR bit associated with that interrupt.
2. Internally, the Intel® 6300ESB ICH requests to use the bus in a way that
automatically flushes upstream buffers. This may be internally implemented similar
to a DMA devi ce reques t .
3. The Intel® 6300ESB ICH then delivers the message by performing a write cycle to
the appropriate address wit h the appropriate data. The address and data formats
are described below in Section 5.7.7.5, “Interrupt Message Format”.
Note: PSB Interrupt Delivery compatibility with processor clock control depends on the
processor, not the Intel® 6300ESB ICH.
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5.7.7.2 Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
th e i n te r r upt.
5.7.7.3 Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt. When the interrupt is still active after an EOI, another “Assert Message”
is sent to indicate that the interrupt is still active.
5.7.7.4 Registers Associated with Processor System Bus Interrupt
Delivery
Capabilities Indication
The capability to support Processor System Bus interrupt delivery will be indicated
t hrough AC PI con fi gur ation te chni qu es. This invo lves the BIOS c reating a data structu re
that gets reported to the ACPI configuration software.
DT Bit in the Boot Configuration Register
This enables the In tel® 6 300E SB ICH to deli ver in terrupt s as m emory w rit es. Thi s bit i s
ignored when the APIC mode is not enabled.
5.7.7.5 Interrupt Message Format
The Intel® 6300ESB ICH writes the message to PCI (and to the Host Controller) as a
32-bit memory write cycle. It uses the formats shown in Table 54 and Table 55 for the
Address and Data.
The local APIC (in the processor) has a delivery mode option to interpret Processor
System Bus messages as a SMI in which case the processor treats the incoming
interrupt as a SMI instead of as an interrupt. This does not mean that the Intel®
6300ESB ICH has any way to have a SMI source from the Intel® 6300ESB ICH power
management logic cause the I/OAPIC to send an SMI message (there is no way to do
this). The Intel® 6300ESB ICH’s I/OAPIC may only send interrupts due to interrupts
which do not include SMI, NMI or INIT. This means that in IA32/IA64 based platforms,
Processor System Bus interrupt message format delivery modes 010 (SMI/PMI), 100
(NMI), and 101 (INIT) as indicated in this section, must not be used and is not
supported. Only the hardware pin connection is supported by the Intel® 6300ESB ICH.
:
Table 54. Interrupt Message Address Format (Sheet 1 of 2)
Bit Description
31:20 Will always be FEEh
19:12 Destination ID: This will be the same as bits 63:56 of the I/O Redirection Table entry
for the inte rrupt associate d with this message.
11:4 Extended Destination ID: T his will be the same as b its 55:48 of the I/O Redirection
Table entr y for the interrupt assoc iate d wi th this me ssage.
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5.8 Serial Interrupt (D31:F0)
The Intel® 6300E SB ICH su pport s a s eria l IR Q sc heme. T h is a llow s a s ingl e s igna l to be
used to report interrupt requests. The signal used to transmit this information is shared
between the host, the Intel® 6300ESB ICH, and all peripherals that support serial
interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the
sustained tri-state protocol that is used by all PCI signals. This means that when a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and
release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state
signaling in the following fashion:
S - Samp le Phase. Signal driven low
R - Recove ry Phase. Sign al driven high
3
Redirection Hint: Th is b it is used by the p roce ssor host br id ge to a llow the inter rupt
message to be redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:12.
1 = The me ssage will be delivered to an agent with a lower interrupt priority. This may
be derived from bits 10:8 in the Data Field (see below).
The R edirectio n Hint bit w il l b e a 1 when bi ts 10: 8 i n the delivery mode fi eld a s soc ia te d
with corre spond ing inte rrup t are e ncode d as 001 (L owe st Priority). Otherwise, the
Redirectio n Hi nt bit w ill be 0.
2
Destination Mode: This b it is us ed only the Redirection Hi nt bit is set to 1. W h e n the
Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical
destina tion mode is use d , and the re d ire ction is limit ed only to those proc e ssors that
are part of the logical group as based on the logical ID.
1:0 Will always be 00.
Table 55. Interrupt M essage Data Format
Bit Description
31:16 Will always be 0000h.
15 Trigger Mode: 1 = Lev e l, 0 = Edge. Same as the corres po ndi ng bit in the I/O
Redirection Table for that interrupt.
14
Delivery Status: 1 = Assert, 0 = Deassert.
When using edge-triggered interrupts, this bit will always be 1, since only the assertion
is sent.
When usin g le vel- t r igger ed int err u pts , th is bit in di cates the state of the inte rrup t inp u t.
13:12 Will always be 00
11 D estination Mode: 1 = Logical. 0 = Ph ys ica l. Same as th e correspon d i ng bit in the I/
O Redirection Table for that interrupt.
10:8
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table
for that in te rrup t.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Rese rved
011 = Reserved 111 = ExtI NT
7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
Table 5 4. Interrupt Message Address Format (Sheet 2 of 2)
Bit Description
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T - Tu rn-around Phase. Signal released
The Intel® 6300ESB ICH supports a message for 21 serial interrupts. These represent
t he 15 ISA interrupts (IRQ0-1, 2-15), the four PCI interrupts, and the control signals
SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC
interrupts (20-23).
Serial interrupt information is tra nsfer red using t hree types of frames :
Start Frame: SERIRQ line driven low by the Intel® 6300ESB ICH to indicate the
start of IRQ transmission
Data Frames: IRQ information transmitted by peripherals. The Intel® 6300ESB
ICH will support 21 data frames.
Stop Frame: S ERIRQ lin e driv en low by the Inte l ® 6300E SB I CH to in dic ate end of
transmission and next mode of operation.
Note: W he n the IDE pri ma r y and se c ondary con tr ollers ar e co nf ig ur ed for nat ive ID E mode ,
the only way to use the internal IRQ14 and IRQ15 connections to the Interrupt
Controllers is through the Serial Interrupt pin.
5.8.1 Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where the Intel® 6300ESB ICH is solely responsible for
generating the start frame; and Quiet, where a serial IRQ peripher al is responsible for
beginnin g the start frame.
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, the Intel® 6300ESB ICH will assert the start frame.
This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control
Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling
mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. The Intel® 6300ESB ICH senses the line low
and continues to drive it low for the remainder of the Start Frame. Since the first PCI
clock of the start frame was driven by the peripheral in this mode, the Intel® 6300ESB
ICH will drive the SERIRQ line low for 1 PCI clock less than in continuous mode. This
mode of operation allows for a quiet, and therefore lower power, operation.
5.8.2 Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start
counting frames based on the rising edge of SERIRQ. Each of the IRQ/DAT A frames has
exactly 3 phas es of 1 clock each:
Sample Phase. During this phase, the SERIRQ device drives SERIRQ low when the
corresponding interrupt signal is low . When the corresponding interrupt is h igh, the
SERIRQ devices will tri-state the SERIRQ signal. The SERIRQ line will remain high
due to pull-up resistors (there is no internal pull-up resistor on this signal, an
external pull-up resistor is required). A low level during the IRQ0-1 and IRQ2-15
frames indicates that an activ e-high ISA interrupt is not being requested, but a low
level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-
low interrupt is being requested.
Recove ry Phase. During this phase, the device will drive the SERIRQ line high
when in the Sample Phase it was driven low. When it was not driven in the sample
phase, it will be tri-stated in this phase.
Turn-around Phase. The devic e will tri -st ate the SE R IR Q line.
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5.8.3 Stop Frame
After all data frames, a Stop Frame is driven by the Intel® 6300ESB IC H. The SERIRQ
signal is driven low by the Intel® 6300ESB ICH for 2 or 3 PCI clocks. The number of
clocks is determined by the SERIRQ configuration register. The number of clocks
determines the next mode:
5.8.4 Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream which are not supported by
the Intel® 6300ESB ICH. These interrupts are generated internally, and are not
sharable with other devices within the system. These interrupts are:
IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
IRQ8#. RTC interrupt may only be generated internally.
IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
The Intel® 6300ESB ICH will ig nore the state of these interrupts in the serial stream,
and will not adjust their level based on the level seen in the serial stream. In addition,
the interrupts IRQ14 and IRQ15 from the serial stream are treated differently than
their ISA counterparts. T hese two frames are not passed to the Bus Master IDE logic.
The Bus Master IDE logic expects IDE to be behind the Intel® 6300ESB ICH.
5.8.5 Data Frame Format
Table 57 shows the format of the data frames. For the PCI interrupts (A-D), the output
from the Intel® 6300ESB ICH is ANDed with the PCI input signal. This way, the
interrupt may be signaled through both the PCI interrupt input signal and through the
SERIRQ signal (they are shared).
Table 56. Stop Frame Explanation
Stop Frame Width Next Mode
2 PCI clocks Quiet Mode. Any SERIRQ dev ice may in itiate a Start Frame
3 PCI clocks Continuous Mo de. Onl y the host (Int el® 6300ESB ICH) may initiate a
Start Fr ame
Table 57. Data Frame Format (Sh eet 1 of 2)
Data
Frame
#Interrupt Clocks Past
Start
Frame Comment
1IRQ0 2
Ignored. IRQ0 may only be generated through the
inter nal 8524.
2 IRQ1 5 Before Port 60h latch
3SMI# 8
Caus e s SM I# whe n low. Will set the S E RIRQ_SMI_STS
bit, (bit 15).
4IRQ3 11
5IRQ4 14
6IRQ5 17
7IRQ6 20
8IRQ7 23
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5.9 Real Ti me Cloc k (D31:F0)
5.9 .1 RTC Overview
The Real Time Clo ck (R TC) module provides a battery ba cked-up date and time keeping
device with two banks of static RAM with 128 bytes each, although the first bank has
114 bytes for general purpose usage. Three interrupt features are available: time of
day alarm with once a second to once a month range, periodic rates of 122 µs to 500
ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week,
month, and year are counted. Daylight savings compensation is optional. The hour is
represented in twelve or twenty -four hour format, and data may be represented in BCD
or binary format. The design is meant to be functionally compatible with the Motorola*
MS146818B. The time keeping comes from a 32.768 KHz oscillating source, which is
di v ide d to ac hi eve an upda te eve ry se co nd . The lo we r 14 b yt es on th e lo wer RAM bl ock
has very specific functions. The first ten are for time and date information. The next
four (0Ah t o 0Dh) are registers, which configure and report RTC functions. See
Table 290 for more inform ation.
The time and calendar data should match the data mode (BCD or binary) and hour
mode (12 or 24 hour) as selected in register B. It is up to the programmer to make
sure that data stored in these locations is within the reasonable values ranges and
represents a possible date and time. The exceptions to these ranges is to store a value
of C0-FFh in the alarm bytes to indicate a “do not care” situation. All alarm conditions
must match to trigger an Alarm Flag, which could trigger an alarm interrupt when
enabled. The SET bit must be one while programming these locations to avoid clashes
with an update cycle. Access to time and date information is done through the RAM
locations. When a RAM read from the ten time and date bytes is attempted during an
update cycle, the value read will not necessarily represent the true contents of those
locations. Any RAM writes under the same conditions will be ignored.
9IRQ8 26
Igno re d. I RQ 8 # may onl y be generated in t er nal l y o r on
ISA.
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38 Before Port 60h latch
14 IRQ13 41 Ignored. IRQ13 may only be generated from FERR#.
15 IRQ14 44 Do not inclu d e in B M IDE interrupt logic.
16 IRQ15 47 Do not inclu d e in B M IDE interrupt logic.
17 IOCHCK# 50 S a me a s ISA IOCHCK# going active.
18 PCI INT A# 53 Drive PIRQA#
19 PCI INTB# 56 Driv e PIRQB#
20 P CI INTC# 59 Dr ive PIRQC #
21 PCI INTD# 62 Drive PIRQD #
NOTE: SIU_SERIRQ Period 13 is used to transfer IRQ12.
Table 57. Data Frame Format (Sheet 2 of 2)
Data
Frame
#Interrupt Clocks Past
Start
Frame Comment
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Note: The Intel® 6300ESB ICH supports the ability to generate an SMI# based on a century
rollover. See Section 5.9.1.4, “Century Rollover for more information on the century
rollover.
Note: The Intel® 6300ESB ICH does not implement month/year alarms.
5.9.1.1 Update Cycles
An update cycle occurs once a second, when the SET bit of register B is not asserted
and the divide chain is properly configured. During this procedure, the stored time and
date will be incremented, overflow will be checked, a matching alarm condition will be
checked, and the time and date will be rewritt en to the RAM locations. The update cycle
will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle
will not take more than 1984 µs to complete. The time and date RAM locations (0-9)
will be disconnected from the external bus during this time.
To avoid upda te and data corru ption con dition s, ex terna l RAM acce ss to th ese loc at ions
may safely occur at two times. When an upd ated-ended interrupt is detected, almost
999 ms is available to read and write the valid time and date. When the UIP bit of
Register A is detected to be low, there is at least 488 µs before the update cycle begins.
Warning:The overflow c ond i tio ns for lea p ye ar s and da ylig ht saving s a djus tments a re
bas ed on mor e than one date or time item . To ens ure prope r ope ration w hen
adjusting the time, th e new time and data values sho uld be set at lea s t tw o
secon ds before one of these co nditions (leap year, daylight savings time
adjustments) occurs.
5.9.1.2 Interrupts
The real-time clock interrupt is internally routed within the Intel® 6 300ES B I CH bo th t o
the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not
leave the Intel® 6300ESB ICH, nor is it shared with any other interrupt. IRQ8# from
the SERIRQ stream is ignored.
5.9.1.3 Loc kable RAM Ranges
The RTC’ s bat tery-backed RAM suppo rts t wo 8-byte ranges that may be locked through
the configuration space. When the locking bits are set, the corresponding range in the
RAM w ill not be r eadab le or writ able . A wri te cy cl e to th ose lo ca tions will ha ve no ef fec t.
A read cycle to those locations will return an undefined value.
Once a range is locked, the range may be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
5.9.1. 4 Century Rollover
The Intel® 6300ESB ICH will detect a rollover when the Year byte (RTC I/O space,
index offset 09h) transitions form 99 to 00. Upon detecting the rollover, the Intel®
6300ESB ICH will set the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). When the
system is in an S0 state, this will cause an SMI#. The SMI# handler may update
registers in the RTC RAM that are associated with century v alue. When the system is in
a sleep state (S1-S5) when the century rollover occurs, the Intel® 6300ESB ICH will
also set the NEWCENTURY_STS bit, but no SMI# is generated. When the system
resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and
update the century value in the RTC RAM.
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5.9.1.5 Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an Intel® 6300ES B ICH -base d pl atf orm may b e done by usi ng a
jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
Using RTCRST# to clear CMOS:
A jumper on RTCRST# may be used to clear CMOS values, as well as reset to default,
the state of those configuration bits that reside in the RTC power well. When the
RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set
and those configuration bits in the RTC power well will be set to their default state.
BIOS may monitor the state of this bit, and manually clear the RTC CMOS array once
the system is booted. The normal position would cause RTCRST# to be pulled up
through a weak pull-up resistor. Table 58 presents which bits are set to their default
state when RTCRST# is asserted.
Using a GPI to Clear CMOS:
A jumper on a GPI may also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Using the SAFEMODE Strap to Clear CMOS:
A jumper on AC_SDOUT (SAFEMODE strap) may also be used to clear CMOS values.
BIOS would detect the setting of the SAFE_MODE status bit (D31:F0: Offset D4h bit 2)
on system boot-up, and manually clear the CMOS array.
Note: Both the GPI and SAFEMODE strap techniques to clear CMOS require multiple steps to
implement. The system is booted with the jumper in new position, then powered back
down. The jumper is replaced back to the normal position, then the system is rebooted
again. The RTCRST# jumper technique allows the jumper to be moved and then
replaced, all while the system is powered off. Then, once booted, the RTC_PWR_STS
may be detected in the set state.
Table 58. Configuration Bits Reset By RTCRST# Assertion
Bit Name D efault State Register Location Bit(s)
AIE RTC Reg B I/O space 5 0
AF RTC Reg C I/O space 5 0
PWR_FLR GEN_PMCON_3 D31:F0:A4h 1 0
AFTERG3_EN GEN_PMCON_3 D31:F0:A4h 0 0
RTC_PWR_STS GEN_PMCON_3 D31:F0:A4h 2 1
PRBTNOR_ST S PM 1_S TS PMB ase + 00h 11 0
PME_EN GPE0 _EN PMBase + 2Ah 1 1 0
RI_EN GPE0_EN PMBase + 2Ah 8 0
NEW_CENTURY_STS TCO1_STS TCOBase + 04h 7 0
INTRD _DET TCO2_STS TCOBase + 06h 0 0
TOP_SWAP GEN_STS D31:F0:D4h 13 0
RTC_EN PM1_EN PMBase + 02h 10 0
BATLOW_EN GPE0_EN PMB ase + 2A h 1 0 0
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5. 10 Pro ces sor Interface (D31: F0)
The Intel® 6300ESB ICH interfaces to the processor with a variety of signals
Standard Outputs to the processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,
IGNNE#, CPUSLP#
The FERR# input to the In tel® 6300ESB ICH has special buffer requirements. The
Vil threshold is compatible with processors that drive FERR# no higher than 1.3V
+/- 5%.
Most Intel® 6300ESB ICH outputs to the processor use standard buffers. The Intel®
6300ESB ICH has a separate VCC signal which is pulled up at the system level to the
processor vo ltage, and thus determines VOH for the outputs to the processor. Note that
this is different than previous generations of chips, that have used open-drain outputs.
This new method saves up to 12 external pull-up resistors.
The Intel® 6300ESB ICH does not support the processor’s FRC mode.
5.10.1 Processor Interface Signals
This section describes each of the signals that interface between the Intel® 6300ESB
ICH and the processor(s).
5.10.1.1 A20M#
The A20M# signal will be active (low) when both of the following conditions are true:
The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a ‘0’
The A20GATE input signal is a ‘0’
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
5.10.1.2 INIT#
The INIT# signal will be active (low) based on any one of several events described in
Table 59. When any of these events occur, INIT# will be driven low for 16 PCI clocks,
then driven hig h.
The 16-clock counter for INIT# assertion will halt while STPCLK# is active. INIT# will
not go active until after STPCLK# goes inactive.
Table 59. INIT# Going Active (Sheet 1 of 2)
Cause of INIT# Going Active Comm ent
Shut do w n special cycle from proc e ssor.
PORT92 write, wh ere INIT _NOW (b it 0) transitions
from a 0 to a 1.
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5.10.1.3 FERR#/IGNNE# (C oprocessor Error)
The Intel® 6300ESB ICH supports the coprocessor error function with the FERR#/
IGN N E # pin s . T he fu nc t io n i s en ab l e d th r o ug h th e CO P R OC _ERR _ EN bi t (De vice
31:Function 0, Offset D0, bit 13). FERR# is tied directly to the Coprocessor Error signal
of the processor. When FERR# is driven active by the processor, IRQ13 goes active
(internally). When it detects a write to the COPROC_ERR register, the Intel® 6300ESB
ICH negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active
until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.
When COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an
internal IRQ13, nor will the write to F0h generate IGNNE#.
PORT CF9 wr ite, w here RST_ CPU (bit 2) was a 0 and
SY S_ RST(b it 1) tran siti ons f rom 0 to 1.
RCIN# i nput s i gna l goes l o w. RCI N# i s expect ed t o
be driven by the external microcontroller (KBC).
0 to 1 tran sition o n RCIN # must occur
before the Intel® 6300ESB ICH will arm
INIT# to be g enerated again.
NOTE: R CI N # signal is expected t o be
high during S1-M and low during
S3, S4, an d S5 state s. Transition
on the RCIN# signal in those
states (or the transition to those
s t a tes) ma y n o t n e cessa rily cau se
the INIT# signal to be generate d
to the processor
CPU BIST In order to e nte r BIST, the software se ts
CPU_B IST_EN b it an d then doe s a fu ll
processor res et usin g th e CF 9 re gis te r.
Table 59. INIT# Going Active (Sheet 2 of 2)
Cause of INIT# Going Active Comment
Figure 14. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
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5.10.1.4 NMI
Non-Maskable Interrupts (NMIs) may be generated by several sources, as described in
Table 60.
5.10.1.5 STPCLK# and CPUSLP# Signals
The Intel® 6300ESB ICH power management logic controls these active-low signals.
Refer to Section 5.11, “Power Management (D31:F0)” for more information on the
functionality of these signals.
5.10.2 Dual Processor Issues
5.10.2.1 Sig nal Differences
In dual processor designs, some of the processor signals are used differently than in
uniprocessor designs.
5.10.2.2 Dual Processor Power Management
For multiple-CPU (or Multiple-core) configurations in which more than one Stop Grant
cycle may be generated, the MCH is expected to count Stop Grant cycles and only pass
the last one through to the 6300ESB. This prevents the 6300ESB from getting out of
sync with the processor on multiple STPCLK# assertions.
Tabl e 60 . NM I So u rces
Cause of NMI Comme nt
SERR# go e s active (eit her inte rnally,
externa lly thr oug h SER R# sig nal, or
through a message from MCH)
May instead be routed to generat e an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, offset
4E, bit 11).
IOCHK# goes active via SERIRQ# stream
(I SA Sy s t em Erro r)
May instead be routed to generat e an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, offset
4E, bit 11).
D30_PD_STS register (D30:F0:06h), bit 8
(Detec te d parity error on Hub Inte rf a ce) Enabled by D30:F0:04h, bit 6
D30_SECSTS register (D30:F0:1Eh), bit 8
(Detec te d parity error on PCI by No rth
PCI unit) E nabl ed by D30:F0:04h, bit 6
D31F0_D EV _S TS re gi ster (D 31:F0:06h),
bit 8 (Detected parity error on PCI by
South PCI unit)
Table 61. DP Signal Differences
Signal Difference
A20M# / A2 0G ATE Generally not us ed, b ut still sup po rte d by th e Intel® 6300ESB ICH.
STPCLK# Used for S1 State as well as preparation for entry to S3-S5.
Also allows for THERM# base d throttlin g (not throug h AC PI control
metho ds ). S h ould be connected to bot h proce ssors.
FERR# / IGNNE # G e ne rally not us ed, but still sup po rte d by the Intel ® 6300ESB ICH.
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Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI i mple mentations, the BIOS must
indicate that the 6300ESB only supports the C1 state for dual-processor desig ns.
In going to the S1 state, multiple Stop-Grant cycles will be generated by the CPUs. The
Intel 6300ESB also has the option to assert the CPU’s SLP# signal (CPUSLP#). It is
assumed that prior to setting the SLP_EN bit (which causes the transition to the S1
state), the CPUs will not be executing code that is likely to delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
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5. 11 Power M anagement (D31:F0)
5.11.1 Features
ACPI Power and Thermal Management Support
Processo r TH R M TRIP# e me rgency shu tdown
ACPI 24-Bit T ime r
Software initiated throttling of processor performance for Thermal and Power Reduction
Hardware Override to throttle processor performance when system too hot
—SCI and SMI# Generation
PME# Signal for Wake Up from Low-Power states (PME signal shared between both
PCI and PCI-X interfac es)
SYS_Reset# input to eliminate external glue logic
System Clock Cont rol
ACPI C2 sta te : Stop-Grant (in des k top ) or Quickstart (in mob ile) s tate (using S TPCLK #
signa l) halts proces sor’s instruct ion strea m
System Sleeping State Control
ACPI S1 state: Like C2 state (only STPCLK# active, and SLP# optional)
ACPI S3 state - Sus p en d to RAM (S TR)
ACPI S4 state - Susp en d-t o-Disk(STD)
ACPI G2/S 5 state - S oft Off(SOFF)
Power Failure Detection and R ecovery
Supports new outp ut si gnal - SLP_S 4#
Streamlined Legacy Power Management Support for APM-Based Systems
Support for Prescott P rocessor
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5.11.2 Intel® 6300ESB ICH Power States and Transition
Rules
Table 62 show s t h e powe r states de fin ed f or In t el ® 6300 ESB IC H-ba sed pl atform s . The
state names generally match the corresponding ACPI states.
Tab le 62. General Power States for Systems Using Intel® 6300ESB ICH
State/
Substates Legacy Name / D escription
G0/S0/C0
Full On : Processor operating. Individual devices may be shut down to save power.
The different processor operating levels are defined by Cx states, as shown in
Table 63. Within the C0 stat e, the Intel ® 6300ES B ICH may throttle the STPCLK#
signal t o r educ e po w er c o nsum pti o n. The throttl i ng m a y be initiat ed by softw ar e o r
by the T HRM# input signal.
G0/S0/C1 Auto-Halt: Processor has executed a AutoHalt instruction and is not executing
code. The processor snoops the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant: The STPCLK# signal goes active to the processor. The processor
per fo rms a Sto p- Gr ant cy cle , h al ts i ts i nst ru cti on s tr ea m, an d rem ai ns i n th at s ta te
until the STPCLK# signal goes inactive. In the Stop-Grant (desktop) state, the
process or snoops th e bus a n d ma in tains cache cohe re n cy.
NOTE: This state i s not supported for IA64 processors. They should instead use
C1.
G1/S1
Stop-Grant: Similar to G0/S0/C2 state. The Intel® 6300ESB ICH also has the
o pti on to a sse rt the CP US LP# si g na l to further red u ce pr oce ssor power
consumption.
NOTE: The behavior for this state is slightly different when supporting IA64
processors.
G1/S3 Suspend-To-RA M (ST R): The system context is maintained in system DRAM, but
power is shut off t o non-critical circui ts. Memory is retained, and refreshes
con tin ue . A ll clocks stop except RTC clock.
G1/S4 Susp end-To-D is k (STD): The context o f the sys tem is mai ntained on th e disk. A ll
power is then shut off to the system except for the logic required to resume.
G2/S5 Soft Off (SOFF): System contex t is not maintained. All pow er is shut off except
for the log ic required to res tart. A full boot is require d whe n waking .
G3
Mechanical OFF (M OFF): System con te x t not ma intained. All powe r is shut off
except for the RTC. No “Wake” events are possible, because the system does not
have any power. This state occurs when the user removes the batteries, turns off a
me ch an ical switc h, or when the syste m power sup ply is a t a le vel tha t is
insufficient to power the “waking” logic. When system power returns, transition will
dep e nds on the state just prio r to the entry to G3 and the AF TERG3 bit in the
GEN_PMCON3 r eg i s ter ( D31:F0, offse t A4). Refer to Table 71 for mor e det ails .
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Table 63 shows the transitions rules among the various states. Note that transitions
amon g the various states may appear to temporarily transition through intermediate
states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/
C2 states. These intermediate transitions and states are not listed in the table.
Table 63. State Transition Rules for Intel® 6300ESB I/O Controller Hub
Present
State Transiti on Trigger Next State
G0/S0/C0
P rocessor halt instructio n
•Level 2 Read
•SLP_EN bit set
Powe r B utton Ov er rid e
M e cha nical Off/Pow er Failure
•G0/S0/C1
•G0/S0/C2
G1/S x or G 2/S 5state
•G2/S5
•G3
G0/S0/C1
Any Enabled break event
•STPCLK# goes active
Powe r B utton Ov er rid e
Po we r Failure
•G0/S0/C0
•G0/S0/C2
•G2/S5
•G3
G0/S0/C2
Any Enabled break event
STPCLK # goes inacti ve and
prev iou sly in C1
Powe r B utton Ov er rid e
Po we r Failure
•G0/S0/C0
•G0/S0/C1
•G2/S5
•G3
G1/S1,
G1/S3, or
G1/S4
A ny Enabled Wake Event
Powe r B utton Ov er rid e
Po we r Failure
•G0/S0/C0
•G2/S5
•G3
G2/S5 Any Enabled Wa ke Event
Po we r Failure G0/S0/C0
•G3
G3 Power Returns
Optional to go to S0 /C0 (re b oot) or
G2/S5 (stay off until powe r bu tton
pressed or other wake event).
NOTE: Some wake events may be
preserved through power failure.
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5. 11 .3 S yst em Po wer Planes
The system has several independent power planes. These power planes can be shut off
and the voltage set to a zero volt level. The power planes and their control signals are
listed in Table 64.
s
5.11.4 Intel® 6300ESB ICH Power Planes
The Intel® 6300ESB ICH power planes were previously defined in Se ction 4.1, “Power
Planes”.
Althou gh not specific power planes within the Intel® 6300ESB ICH, there are many
interface signals that go to devices that may be powered down. These include:
IDE: Output signals may be tri-stated or driven low and all input buffers may be
shut off
USB: Output signals may be tri-stated and all input buffers may by shut off when
US B wakeu p is no t de sire d .
AC’97: Output signals may be driven low and input buffers may be shut off.
Table 64. System Power Plane
Plane Controlled
By Description
Processor SLP_S3#
signal The SLP_S3# signal may be used to cu t t he processor ’s powe r
completely.
MAIN SLP_S3#
signal
When SL P_S 3# g oe s active, power may be shut off to an y circuit
not require d to wake the syste m f rom the S3 state. Since the S3
state requires th at the memory contex t be preserved, power must
be retained to the main me mory.
The processor, devices on the P CI bus, LPC I/F downstream Hub
Interface and AGP will typically be shut off when the Main power
plane is shut off, although there may be small subsections
powered.
MEMORY SLP_S4#
signal
When the SLP_S 4# goes active, powe r ma y be shut off to any
circuit not required to wake the system from the S4. Since the
memory c ontext does not n eed to be preserv ed in the S4 stat e, t he
power to the me mory may also be shut down.
MEMORY SLP_S5#
signal
When the SLP_S 5# goes active, powe r ma y be shut off to any
circuit not required to wake the system from the S5. Since the
memory c ontext does not n eed to be preserv ed in the S5 stat e, t he
power to the me mory may also be shut down.
DEVICE[n] GPIO Individual subsystems may have their own power plane. Fo r
example, GPIO signals may be used to control the power to disk
drives , a udi o am p lif ie rs, or the display scre e n.
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5.11.5 SMI#/SCI Generation
Upon any SMI# event, the Intel® 6300ESB ICH will assert SMI# to the processor,
which will cause it to enter SMM space. SMI# remains active until the EOS bit is set.
When the EOS bit (bit 1) is set, SMI# will go inactive for a minimum of four PCI clocks.
See Section 8.8.3.9, SMI_EN—SMI Control and Enable Register for details on the SMI
control register.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
sys tem. In no n- AP IC s y stem s (w hi ch is the de faul t), th e SCI IRQ i s rout ed t o o ne of t he
8259 interrupts (IRQ9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI may be routed to interrupts 9, 10, 11, 20, 21, 22,
or 23 The interrupt polarity changes depending on whether it is on an interrupt
shareable with a PIRQ or not. The interrupt will remain asserted until all SCI sources
are removed.
Table 32 shows which events may cause an SCI, and Table 65 shows the causes of an
SMI#. Note that some events may be programmed to cause either an SMI# or SCI. The
us ag e o f t he ev e nt f or SC I ( in s te ad of SM I#) is ty pic al l y as so ci at ed wi t h an AC PI -b as ed
system.
Causes of TCO SCI are discussed in Section 5.12.3,TCO Theory of Operation”.
Table 65. Causes of SCI
Cause Additional Enables1Where Reported
PME# PME_EN = 1 PME_STS
Internal EHCI wake (PME_ B0 ) PME_B0_EN = 1 PME_B0_STS
Power Button Press PWRBTN_EN = 1 PWRBTN _STS
RTC Alarm RTC_EN = 1 RTC_STS
Ring Indicate RI_EN = 1 RI_STS
AC’9 7 wakes AC97_EN = 1 AC97_STS
US B #1 w akes U SB1_E N = 1 U SB1_STS
US B #2 w akes U SB2_E N = 1 U SB2_STS
US B #3 w akes U SB3_E N = 1 U SB3_STS
THRM# pin active (based on
THRM#_POL) THRM_EN = 1 THRM_STS
ACPI Timer overflo w (2.34 seconds) TMROF_EN = 1 TMROF_STS
Any GPI GPI[x]_R oute = 10, GPE[x]_EN
= 1 GPI[x]_STS
TCO SCI Logic 1, 2TCOSCI_EN = 1 TCOSCI_STS
BIOS_R LS writt en to 1 GBL_E N = 1 GBL _S TS
WDT 1st timeout WDT_ENABLE = 1,
WDT_INT_TYPE =01” WDTSCI_STS
NOTES:
1. SCI_EN must be 1 to enable SCI.
2. SCI may be routed to cause Interrupt 9:11 or 20:23 (20:23 only available in APIC mod e ).
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Table 66. Causes of SMI# (Sheet 1 of 2)
Cause Additio nal E nables W he re Repo r ted Sync h
PM E# SCI_EN = 0, PME_EN = 1 PME_STS
Internal EHCI wake (PME_B0) SCI_EN = 0, PME_B0_EN =
1PME_B0_STS
Power Button Press SCI_EN = 0, PWRBTN_EN
= 1 PWRBTN_STS
RTC Alarm SCI_EN = 0, RTC_EN = 1 RTC_STS
Ring Indicate SCI_EN = 0, RI_EN = 1 RI_STS
AC’97 wakes S CI_EN = 0, A C97_EN = 1 AC97_STS
USB #1 wakes SCI_EN = 0, US B 1_EN = 1 USB1_S TS
USB #2 wakes SCI_EN = 0, US B 2_EN = 1 USB2_S TS
USB #3 wakes SCI_EN = 0, US B 3_EN = 1 USB3_S TS
THRM# pin active (based on
THRM#_POL) SCI_EN = 0, THRM _EN = 1 THRM_S TS
ACPI Time r overf low
(2.34 seconds) SCI_EN = 0, TMROF_EN =
1TMROF_STS
Any GPI GPI[x]_Route = 01,
GPE[x]_EN = 1 GPE1_STS,
GPI[x]_STS
TCO SMI Logic (see table
below) TCO_EN = 1 TCO_STS
NMI oc curr ed (and NM Is
mapped to SMI)
Se e NMI se ction fo r cau se s of
NMI
NMI2SMI_EN = 1 TCO_STS,
NMI2SMI_STS
GBL_RLS written to 1 BIOS_EN = 1 BIOS_STS
Writ e to B2h register None APM_STS X
Periodic timer expires PERIODIC_EN = 1 PERIODIC_STS
64 ms time r e x p ire s S W S M I_TMR_EN = 1 SWS M I_TMR_STS
Enha nc ed USB Legacy Suppor t
Event LEGACY_USB2_EN = 1 LEGACY_USB2_STS
Enhance d US B Inte l-Spe cif ic
Event INTEL_USB2_EN = 1 INTEL_USB2_ST S
Clas sic US B Legacy logic
(Port 64/60 R/W, End of pass
through) LEGACY _USB _EN = 1 LEGAC Y_U SB_ ST S X
Classic USB Legacy logic (IRQ) LEGACY_USB_EN = 1 LEGACY_USB_STS
Serial IRQ SMI Reported None SERIRQ_SMI_STS
NOTES:
1. GB L _SM I_EN must be 1 to ena ble SMI.
2. EO S must be written to 1 to re-e nab le SMI for the ne xt one.
3. Some S MI#s are consid er ed “sync h ronou s , in t hat t he pr ocessor s hould r ec ogn ize th e SMI#
prior to completing the instruction (I/O read, I/O write, Memory read, or Memory write) that
should cause the S MI#. This is accomplishe d by having the SMI# sign al go active to the
process or pri o r to the proces sor ob se rving the RD Y# signal that te rminat es the c ycl e. SMI#s
marked with X in the Synch column are treated as Sy nchronous.Synchronous SMI#s are not
pos sib le in IA64 platf orms, since the y do not support the SMI# signal.
4. NMI2S MI_STS is not gated by TCO_EN.
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See S e ction 5. 12.3, “TC O The ory o f Opera t ion” for details on the TCO SMI#
causes.
Device Moni tors matches an
address in its range DEV [n] _ TRA P _EN = 1 DEVMON_STS,
DEV[n]_TRAP_STS X
SMB u s Ho st C on troller SMB_SMI_EN
Hos t Controller en abled
Various bits in the
SMBus Ho s t St atus
Register
SMBus Slave SMI message None SMBUS_SMI_STS
SMBus SMBAL ER T # signa l
active None SMBUS_SMI_STS
SMBus Host Notify message
received HOST_NOTIFY_INTREN SMBUS_SMI_STS,
HOST_NOTIFY_STS
Access to Microcontr olle r
Range (62h/66h) MCSMI_EN MCSMI_STS X
SLP_EN bit written to 1 SMI_ON_SLP_EN = 1 SMI_ON_SLP_EN_S
TS X
WDT 1st timeout WDT_ENABLE = 1,
WDT_IN T_ TYPE = 1 0 WDT_SMI_STS
Table 67. Causes of TCO SMI#
Cause Additional Enables Where Reported
Century Rollover None NEW CEN TU RY_STS
TCO TI M E ROUT None TIME OUT
OS writes to TCO_DAT_IN re giste r None OS_TCO_SMI
Message from MCH None MCHSMI_STS
NMI oc curr ed (a nd NMIs mapp ed t o
SMI)
See NMI section for causes of NMI NM I2SM I_EN = 1 NMI2SMI_STS
NOTE: N MI2SMI_STS is not gated by TCO_EN. See tab le above .
INTRUDER# signal g oes active INTRD_SEL = 10 INTRD_DET
Changes of t he BIOSWP bit fr om 0
to 1 BLD = 1 BIOSWR_STS
Write attempted to BIOS BIOSWP = 1 BIOSWR_STS
Table 66. Causes of SMI# (Sheet 2 of 2)
Cause Additi o nal Enab les Where Rep o rted Syn ch
NOTES:
1. GBL_SMI_EN must be 1 to enable SMI.
2. EOS must be written to 1 to re -e nab le SM I for the next one.
3. Some SMI#s are c onsider ed “syn c hrono us”, in that the pro c esso r sho ul d recogni z e t he SMI#
prior to comple ting th e instruction (I/O read, I/O write, M em ory re ad, or Me mory write) that
should ca u se the SMI #. This is ac complishe d by havin g t he SMI# sign al go ac tive t o th e
proc es sor pr i or to the pro c esso r obser vin g the R DY # signal t hat term inates th e cycle. SMI# s
marke d with X in the Synch column are tr eated as Synchronous. Syn chronous S M I#s a re n ot
possible in IA64 p latf orms , sinc e they do not suppo rt the SMI# signal.
4. NMI2SMI_STS is not gated by TCO_EN.
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5.11.6 Dynamic Processor Clock Control
The Intel® 6300ESB ICH has extensive control for dynamically starting and stopping
sy stem cl ocks. The clock control is used for tr ansiti ons among the va rious S0/ Cx stat es,
and processor throttling. Each dynamic clock control method is described in this
se cti on . Th e va ri ous Sle ep sta te s may al so perf or m typ es of non- dy nami c cl oc k co ntrol .
The Intel® 6300ESB ICH supports the ACPI C0, C1 and C2 states. C3 and C4 are not
supported.
The Dynamic Processor Clock control is handled using the following signal:
STPCLK#: Used to halt proces sor instruction stream.
Note: The Intel® 6300ESB ICH does support THRM# based throttling. The C1 state
(processor auto halt) may be used with either one or two processors, however.
Processors are free to perform their own dynamic clock control; however, this is done
without any coordination by the Intel® 6300ESB ICH.
The C1 state is entered based on the processor performing an auto halt instruction.
The C2 state is entered based on the processor reading the Level 2 register in the
Intel® 6300ESB ICH.
A C1 or C2 state ends due to a break event. Based on the break event, the Intel®
6300ESB ICH returns the system to C0 state. Table 68 lists the possible break events
from C2 states. The break events from C1 are indicated in the processors datasheet.
The Intel® 6300ESB ICH support s the Pending Break Event (PBE) indicati on from the process or us-
ing t he FERR# signal. The following rul es apply:
1. When STPCLK# is detected active by the processor, the FERR# signal from the
processor will be redefined to indicate whether an interrupt is pending. The signal is
active low (i.e., FERR# will be low to indicate a pending interrupt).
2. When th e Intel® 6300ESB ICH asserts STPCLK#, it will latch the current state of
the FERR# signal and continue to present this state to the FERR# state machine
(independent of what the FERR# pin does after the latching).
3. When th e Intel® 6300ESB ICH detects the Stop-Grant cycle, it will start looking at
the FERR# signal as a break event indication . When FERR# is sampled low, a break
event is indicated. This will force a transition to the C0 state.
4. When the processor detects the deassertion of STPCLK#, the processor will start
dr i v in g th e FER R# si g nal w i th t he nat ural v a lu e ( i .e .t he v a lu e it wo ul d do wh en th e
pin was not muxed). The time from STPCLK# inactive to the FERR# signal
transition back to the native function must be less than 120 ns.
Table 68. Break Events
Event Breaks from Comment
Any unmasked interrup t
goes active C2 IRQ[0:15] whe n using the 8259s, IRQ[0:23] fo r
I/O xAPIC0 and I/O xA [IC1. S inc e SCI is an
interrupt, an y SCI will al so be a break even t.
Any internal event that will
cause an NMI or SMI# C2 Many p o ssible sou rce s.
Any internal event that will
cause IN IT# to go active C2 Could be indicated by the keyboard controller
through the RCIN inp ut sig nal.
Process or Pending br eak
eve nt Indi cati o n C2
Only avail able when FERR# enabled for break
even t indic at ion (See FERR# Mux -En in
Section 8.1.22, “Offset D0h - D3h: GEN_CNTL
General Control Register (LPC I/F—D 31:F0)”).
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5. The Intel® 6300ESB ICH waits at least 180 ns to 8 PCI clocks (240 ns) after
deasserting STPCLK# and then starts using the FERR# signal for an indication of a
floating point error. The maximum time that the Intel® 6300ESB ICH may wait is
bounded such that it must have a chance to look at the FERR# signal before
reas serting ST PCLK #. Based on current i mplementa tion, tha t maximum ti me would
be 240 ns (8 PCI clocks). Since the processor has 120-210 ns to revert to the
proper FERR# function, there are 60-30 ns of margin inherent in the timings.
The break event associated with this new mechanism does not need to set any
particular status bit, since the pending interrupt will be serviced by the processor after
returning to th e C0 state.
5.11.6.1 Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The Intel® 6300ES B IC H
asserts STPCLK# to throttle the proce ssor clock and the processor appears to
temporarily en ter a C2 state. After a programmable time, the Intel® 6300ESB ICH
deasserts STPCLK# and the processor appears to return to the C0 state. This allows the
processor to operate at reduced average power, with a corresponding decrease in
performance. Two methods are included to start throttling:
1. Software enables a timer with a programmable duty cycle. The duty cycle is set by
the THTL_DTY field and the throttling is enabled using the THTL_EN field. This is
known as Manual Throttling. The period is fixed t o be in the non-audible range, due
to the nature of switching power supplies.
2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
unconditionally forces throttling, independent of the THTL_EN bit. The throttling
due to Thermal Ov erride has a separate duty cycle (THRM_D TY) which may vary by
field and system. The Thermal Override condition will end when THRM# goes
inactive.
Throttling due to the THRM# signal has higher priority than the software initiated
throttling.
Throttling does not occur when the system is in a C2 state, even when Thermal
override oc curs.
5.11.6.2 Transition Rules among S0/Cx and Throttling States
The follo wing priority rules and assumptions apply among the various S0/Cx and
thr ottling states:
Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
is because the processor may only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN
bit may be internally treated as being disabled (no throttling while going to sleep
state). Note that thermal throttling (based on THRM# signal) cannot be disabled in
an S0 state. However, once the SLP_EN bit is set, the thermal throttling is shut off
(since STPCLK# will be active in S1–S5 states).
When the THTL_EN bit is set, and a Level 2 read then occurs, the system should
immediately go and stay in a C2 state until a break event occurs. A Level 2 read
has higher priority than the software initiated throttling or thermal throttling.
When Therm al Override is causing throttling, and a Level 2 read then occurs, the
system will stay in a C2 state until a break event occurs. A Level 2 read has higher
priority than the Thermal Override.
After an exit from a C2 state (due to a break event), and when the THTL_EN bit is
still set, or when a Thermal Override is still occurring, the system will continue to
throttle STPCLK#. Depending on the time of break event, the first transition on
STPC LK# ac tive may be de layed b y up to one THRM peri od (1024 PCI cl ocks=30 .72
microseconds).
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The Host controller must post Stop-Grant cycles in such a way that the processor
gets an indication of the end of the special cycle prior to the Intel® 6300ESB ICH
observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active
for a sufficient period after the processor observes the response phase.
When in the C1 state and the STPCLK# signal goes active, the processor will
generate a Stop-Grant cycle, and the system should go to the C2 state. When
STPCLK# goes inactive, it should return to the C1 state.
5. 11.6.3 STPCLK# Im plementation Notes
The processor treats STPCLK# like an interrupt and recognizes it on instruction
bo und ari es (no I NTA c ycl es a re ru n) . Whe n it re cogni z es ST PCL K# ac ti ve , th e pr oces so r
stops execution on the next instruction boundary, stops the pre-fetch unit, empties
internal pipelines and write buffers, and generates a Stop-Grant bus cycle before
entering the Stop Grant state. The processor may stop the clock to most of its internal
modules, and no instructions are executed. The processor exits the Stop Grant state
when it is reset, or upon sampling STPCLK# inactive.
Th e proces sor wil l lat ch tr an siti ons on the externa l inte rrup t sig nals (SMI#, NMI, INTR,
and INIT#) while in Stop Grant state. These interrupts are taken after the deassertion
of STPCLK#.
For the Intel® Pentium® 4 processor, the following edge signals must not transition
while STPCLK# is active:
INTR
INIT#
SMI#
NMI
Th ese sig nals shoul d be ru n th rough a tr an spare nt l atch i nt ernal to the In te l® 6300E SB
ICH. While STPCLK# is inactive (HIGH) these signals propagate to the Intel® 6300ESB
I CH's pi ns and on to the p roce s sor a s norm al . Ho wever when STP CLK # i s asse r ted th en
these signals are latched so that they may not change until STPCLK# is deasserted.
This ensures that an edge on these signals is seen while the processor has a valid clock.
These signals need to be latched at least 1 HCLK clock before STPCLK# assertion, and
held 16 HCLK clocks after STPCLK# deassertion.
Figure 15. Latching Processor I/F Signals with STOPCLK#
STPCLK#
T- Latch
SMI#, NMI#, INTR
PCICLK
SMI#, NMI#, INTR pin
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Other Implem entation Notes:
When STPCLK# goes active due to a Lev el read, it must go active prior to the
completion of the associated I/O read. This is to ensure that the STPCLK# is
recognized by the processor prior to it recognizing the end of the I/O cycle. That
will prevent the next instruction from being executed.
The state machine must insure that the STPCLK# signal stays high for a minimum
period of time. When STPCLK# is to go low due to throttling (regular or due to the
THRM# signal), this could be very soon after i t was driven high. The MCH should
ensure that the Stop-Grant cycle coming down the Hub Interface occurs after the
BRDY# is seen by the processor.
Exception: For SMI#s that are caused by a processor I/O cycle, when STPCLK# is
active, the Intel® 6300ESB ICH will still drive SMI# active. This is because the
STPCLK# was obviously too late to be recognized at the instruction boundary. The I/O
cycles that may cause SMI# include: writes to the APM register (B2h), accesses to 60/
64h when “Legacy USB KBC scheme” is used, traps for Monitors 4, 5, 6, and 7, the
SMI# on SLP_EN bit, accesses to 62/66h when the MCSMI_EN bit is set, access to
registers with their associated enable set in the DEVTRAP_EN register, and the
BIOS_STS bit (which is set by the processor writing a 1 to the GLB_RLS bit when the
BIOS_EN bit is also set).
5.11.7 Sleep S tates
5.11.7.1 Sleep State Overview
The Intel® 6300ESB ICH directly supports different sleep states (S1–S5), which are
entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the
Sleep states are based on several assumptions:
Entry t o a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor may only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
Prior to setting the SLP_EN bit, the software will turn off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit will disable thermal throttling (since S1–S5 sleep state has higher priority).
The G3 state cannot be entered through any software mechanism. The G3 state
indicates a complete loss of power.
5.11.7.2 Initiating Sleep S tate
Sleep states (S1–S5) are initiated by:
Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field and then setting the SLP_EN bit. The hardware will then
attempt to gracefully put the system into the corresponding Sleep state by first
going to a C2 state. See Section 5.11.6, “Dynamic Processor Clock Control” for
details on going to the C2 state.
Pressing the PWRBTN# Signal for more than four seconds to cause a Power Button
Override event. In this case the transition to the S5 state will be less graceful, since
there will be no dependencies on observing Stop-Grant cycles from the processor
or on clocks other than the RTC clock.
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Other Assumptions:
Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor may only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
Prior to setting the SLP_EN bit, the software will turn off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit will disable throttling (since S1-S5 sleep state has higher priority).
The G3 state cannot be entered through any software mechanism. The G3 state
indicates a complete loss of power.
Before entering sle ep sta te, an ACPI OS will mask all interrupt s and will turn off a ll bus
master enable bits. For non-ACPI systems, the BIOS will mask interrupts and turn off
all bus master enable bits.
Note: Interrupts might not be masked at the I/O subsystem. Some Operating Systems have
been observed to only mask interrupts inside the processor.
5.11.7.3 Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events will force the
system to a full on state (S0), although some non-critical subsystems might still be
s hut o ff an d ha ve t o be br o ught back manu al ly. F or e xamp le , the h ard d isk may be sh ut
off during a sleep state, and have to be enabled through a GPIO pin before it may be
used.
Upon exit from the Intel® 6300ESB ICH-controlled Sleep states, the WAK_STS bit will
be set.
The poss ib le caus es of Wake Even ts (an d their r estric tio ns) are show n in Table 70.
Table 69. Sleep Types
Sleep
Type Comment
S1 The I n tel® 6300ESB ICH ass e rts the S TPC LK# s ign al. It also has the option to
asse rt CPUS LP# signal. T his will lowe r the pr ocessor’s power cons ump tion. No
sn oop in g is po ssib l e in th is sta te .
S3 The I n tel® 6300ESB ICH asserts SLP_S 3#. The S LP_ S3 # sig nal will control the
power to non-critical circuits. Power will on ly be reta ine d to dev ices need e d to
wake from this sleeping state, as well as to the memory.
S4 The I n t e l® 6300ESB ICH ass er ts SLP_ S3# an d SLP_ S4 #. The S LP_S4# signal will
shut off the po we r to the me mory subsyste m. Only devices ne e ded to wa ke from
this state should be pow ered.
S5 Same power state as S4. The Intel® 6300ESB ICH asserts SLP_S3#, SLP_S4# and
SLP_S5#.
Table 70. Causes of Wake Events (Sheet 1 of 2)
Cause States Can Wake
From How Enabled
RTC A larm S1 S5 Set RTC _E N bit i n PM 1_EN Register
NOTE: When in the S5 state due to a powerbutton over ride, the only wake events are Power
Button, W ake SMBUs Slave Message (01h), and Hard Reset SMBus Slave Messages (03h,
04h).
NOTE: PM E#, RTC , GPI[ 0:n], a nd R I# will b e wake event s fr om S 5 only when it was ente re d
through softwa re setting the SLP_EN and SL P_T YP bits, or if the re is a po we r fai lure .
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5.11.7.4 Sx-G3-Sx, Handling Power Failures
In desktop systems, power failures may occur when the AC power is cut (a real power
failure) or when the system is unplugged. In either case, PWROK and RSMRST# are
assumed to go low. Depending o n when the power failure occurs and how the system is
designed, different transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. When the policy is to not boot, the
system will remain in an S5 state (unless previously in S4). There are only th ree
possible events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When the Intel® 6300ESB ICH exi ts G3
after power returns (RSMRST# goes high), the PWRBTN# signal is already high
(because VCC-standby goes high before RSMRST# goes high) and the
PWRBTN_STS bit is 0.
2. RI#: RI# does not have an int ernal pull-up. Therefore, when this signal is enabled
as a wake event, it is important to keep this signal powered during the power loss
event. When this signal goes low (active), when power returns the RI_STS bit will
be set and the system will interpret that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The Intel® 6300ESB ICH monitors both PWROK and RSMRST# to detect for power
failures. When PWROK goes low, the PWROK_FLR bit is set. When RSMRST# goes low,
PWR_FLR is set.
Power Button S1S5 Always enabled as Wak e event
GPI[0:n] S1S5
GPE0_EN register (after hav ing gone to S5 through
SLP_ EN, but not af ter a po we r fai lure .)
NOTE: GPIs that ar e in the c ore w ell are no t capable
of waking the system from sleep states
where the core well is not powered.
USB S1S5 Set USB 1_EN, USB 2_EN and USB3_EN bits in
GPE0_EN Register
RI# S1S5 Se t RI_EN bit in GPE0_EN Reg ister
AC’97 S1S5 Set AC’ 97_EN bit in GPE0 _EN Reg i ster
Secondary PME# S1S5 Set PME_EN bit in GPE0_EN Register.
SMBALERT# S1S4 SMB_WAK_E N i n t he GP E0 Register. Always enabled
as Wake event
SMBus Slave
Message S1S5
Wake/SMI# command always enabled as a Wake
Event.
NOTE: SMBus Slave Message may wake the system
from S1-S5, as well as from S5 due to Power
Button Ove rrid e .
PME_B0 (internal
USB EHCI controller) S1S5 Set PME_B0_EN bit in GPE0_EN Reg ister.
Table 70. Causes of Wake Events (Sheet 2 of 2)
Cause States Can Wake
From How Enab led
NOTE: When in the S5 state du e to a powe rb utton override, the only wake even ts are Power
Button, Wake SMBUs Slave Message (01h), and Hard Reset SMBus Slave Messages (03h,
04h).
NOTE: PME#, RTC, GPI[0:n], and RI# will be wake events from S5 only when it was entered
throug h softwa re setting the S LP_EN and SLP_TYP bits, or if there is a power f a ilure .
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5.11.8 Th ermal Management
The Intel® 6300ESB ICH has mechanisms to assist with managing thermal problems in
the syst em.
5.11.8.1 THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#
signal going active, the Intel® 6300ESB ICH generates an SMI# or SCI (depending on
SCI_EN).
When the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS
bit will be set. This is an indicator that the thermal threshold has been exceeded. When
the THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will
be generated (depending on the SCI_EN bit being set).
The power management software (BIOS or ACPI) may then take measures to start
reducing the temperature. Examples include shutting off unwanted subsystems, or
halting the processor.
By se tting the THRM _PO L bit to hi gh , another SM I# or SCI may opt ionally be gene rated
when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to
turn off the cooling methods.
Note: THRM# assertion will not cause a TCO event message in S1-M, S3, or S4. The level of
the signal will not be reported in the heartbeat me ssage.
5.11.8.2 THRM# Initiat ed Passive Cooling
When the THRM# signal remains active for some time greater than two seconds and
the Intel® 6300ESB ICH is in the S0/G0/ C0 stat e, then the Intel ® 6300ESB ICH enters
an auto-throttling mode, in which it provides a duty cycle on the STPCLK# signal. This
will reduce the overall power consumption by the system, and should cool the system.
The intended result of the cooling is that the THRM# signal should go back inactive.
For all programmed values (001–111), THRM# going active will result in STPCLK#
act iv e for a mini mum tim e of 12. 5% and a m aximu m of 87. 5%. The peri od is 1024 P CI
clocks. Thus, the STPCLK# signal may be active for as little as 128 PCI clocks or as
much as 896 PCI clocks. The actual slowdown (and cooling) of the processor will
depend on the instruction stream, because the processor is allowed to finish the
current instruction. Furthermore, the Intel® 6300ESB ICH waits for the STOP-GRANT
cycle before starting the count of the time the STPCLK# signal is active.
When THRM# goes inactive, the throttling will stop.
Table 71. Trans itio ns Du e to Po wer Failur e
State at Power Fa ilure A FTER G 3_EN bit Transit ion When Powe r Returns
S0, S1 , S3 1
0S5
S0
S4 1
0S4
S0
S5 1
0S5
S0
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Note: There is a small window where the Intel® 6300ESB ICH may assert STPCLK# for one
more throttling period after THRM# goes inactive. This is due to a sampling delay on
THRM# (the signal is still active internally, but has just gone inactive externally).
In ca se th a t the In t el® 6300ESB ICH is already attempting throttling because the
THTL_EN bit is set, the duty cycle associated with the THRM# signal will have higher
priority.
When the Intel® 6300ESB ICH is in the C2, or S1–S5 states, then no throttling will be
caused by the THRM# signal being active.
5.11.8.3 THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, just as though the
THRM# signal had been active for two seconds. When this bit is set, the Intel®
6300ESB ICH w ill start throttling using the ratio in the THRM_DTY field.
When thi s bit is clear ed the Intel ® 6300ESB ICH will stop throttling, unless the THRM#
signal has been active for two seconds or when the THTL_EN bit is set (indicating that
ACPI s oftware is attempting throttling).
5.11.8.4 Processor Initiated Passive Cooling (Via Programmed
Duty Cycle on STPCLK#)
Using the THTL_EN and THTL_DTY bits, the Intel® 6300ESB ICH may f orce a
programmed duty cycle on the STPCLK# signal. This will reduce the effective
instruction rate of the processor and cut its power consumption and heat generation.
See Section 8.8.3.5, “PROC_CNTProcessor Control Register” for more details on the
progr am ming of thes e bits.
5.11.8.5 Active Coolin g
Active cooling involves fans. The GPIO signals from the Intel® 6300ESB ICH may be
used to turn on/off a fan.
5.11.9 Event Input Signal Usage
The Intel® 6300ESB ICH has various input signals that trigger specific events. This
section describes those signals and how they should be used.
5.11.9.1 PWRBTN# - Power But ton
The Intel® 6300ESB ICH PWRBTN# signal operates as a “Fixed Power Button” as
described in the ACPI specification. PWRBTN# signal has a 16 ms debounce on the
inpu t. The sta te trans itio n des crip tio ns are incl ud ed in the follo wi ng table.
Note: Transitions start as soon as the PWRB TN# is pressed (but after the debounce logic) and
do not depend on when the Power Button is released.
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Power Button Override F unction
Wh en PWRB TN# i s obs er ved acti ve for a t leas t four cons ecuti ve se cond s, the n the sta te
machine should unconditionally transition to the G2/S5 state, regardless of present
state (S0–S4). In this case, the transition to the G2/S5 st ate should not depend on any
particular response from the processor (such as a Stop-Grant cycle), nor any similar
dependency from any other subsystem.
A power button override will force a transition to S5 even when PWROK is not active.
The PWRBTN# status is readable to check when the button is currently being pressed
or has been released. The status is taken after the debounce, and is readable through
th e PW R B TN _ LVL bi t .
Note: The four second PWRBTN# assertion should only be used when a system lock-up has
occurred. The four second timer starts counting when the Intel® 6300ESB ICH is in a
S0 state. When the PWRBTN# signal is asserted and held active when the system is in
a suspend state (S1–S5), the assertion will cause a wake event. Once the system has
resumed to the S0 state, the four second timer will start.
Sleep Bu tton
The ACPI specification defines an optional Sleep button. It differs from the power
button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state,
the Power Button may wake the system, but the Sleep Button cannot.
Although the Intel® 6300ESB ICH does not include a specific signal designated as a
Sleep Button, one of the GPIO signals may be used to create a “Control Method” Sleep
Button. See the ACPI specification for implementation details.
5.11.9.2 RI# - Ring Indicate
The Ring Indicator may cause a wake event (when enabled) from the S1–S5 states.
Table 73 shows when the wake event is generated or ignored in different states. When
in the G0/S0/Cx states, the Intel® 6300ESB ICH will generate an interrupt based on
RI# active, and the interrupt will be set up as a break event.
Table 72. Transitions Due to Power Button
Present
State Event Transition/Action Comment
S0/Cx PWRB T N# goes low SMI# or SCI generated
(depending on SCI_EN) Software will typically initiate
a Sleep state.
S1-S5 PWRB T N# goes low W ake Event. Transitions to
S0 state. Standard wakeup
G3 PWRBTN# pressed No ne No effect since no power.
Not latche d n or dete c t e d.
S0-S4 PWRB TN# held low
for at least four
consec ut ive seco nds
Unconditional transition to
S5 state.
No dependence on processor
(such as Stop-G rant cycles)
or any other subsystem.
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5.11.9.3 PME# - PCI Power Management Event
The PME# signal comes from a PCI device to request that the system be restarted. The
PM E# si g n a l m a y g ener at e an SMI #, SC I, o r o p ti o n al l y a Wake event. The ev e nt o c cur s
when the PME# signal goes from high to low. No event is caused when it goes from low
to high. The Intel® 6300ESB ICH supports only one PME# signal which i s shared
between both the PCI and the PCI-X interfaces.
In the EHCI controller, there is an internal PME_B0 bit. This is separate from the
external PME# signal and may cause the same effect.
5.11.9.4 SYS_RESET# Signal
SYS_RESET# is a new pin on the Intel® 6300ESB ICH that is used to eliminate extra
glue logic on the board. Before the addit ion of this pin, a system reset was activated by
exter nal g lue forc in g the PWROK sign al l ow after the re set bu tton w as pres sed. T his pi n
eliminates the need for that glue. As such, a SYS_RESET# event should look internally
to our chip and externally to the system as when PWROK had gone low.
When the SYS_RESET# pin is detected as active after the 16 ms de bounce logic, the
Intel® 6300ESB ICH will attempt to perform a “graceful” reset, by waiting up to 25 ms
for the SMBus to go idle. When the SMBus is idle when the pin is detected active, the
re se t wi l l o ccu r im me di ate l y, othe r wi se t he cou nte r will start. Wh en at a ny po int dur in g
the count the SMBus goes idle the reset will occur. When, however, the counter expires
and the SMBus is still active, a reset will be forced upon the system even though
activity is still occurring.
Once a reset of this type has occurred, it cannot occur again until SYS_RESET# has
been detected inactive after the debounce logic, and the system is back to a full S0
state as indicated by all of the PWROK inputs being active.
5.11.9.5 THRMTRIP# Signal
When THRMTRIP# goes active, the processor is indicating an overheat condition, and
the Intel® 6300ESB ICH will immediately transition to an S5 state. However, since the
processor has overheated, it will not respond to the Intel® 6300ES B ICH’s STP CLK# pin
wit h a sto p gra nt spe cial cy cl e. Th eref ore, the Inte l® 6300E SB ICH will not w ait for one.
Immediately upon seeing THRMTRIP# low, the Intel® 6300ESB ICH will initiate a
tr an si ti on t o the S 5 s ta te , d ri v e SL P_S 3#, SLP _ S4 #, SLP _S5 # l ow, and s et t he CT S bit.
The transition will look like a power button override.
It is extremely important that when a THRMTRIP# event occurs, the Intel® 6300ESB
ICH power down immediately without following the normal S0 -> S5 path. This path
may be taken in parallel, but the Intel® 6300ESB ICH must immediat ely enter a power
down state. It will do this by driving SLP_S3#, SLP_S4#, and SLP_S5# immediately
after sampling THRMTRIP# active.
Table 73. Transitions Due to RI# Signal
Pre sen t Stat e Eve nt RI_EN Event
S0 RI# Active X Ignored
S1-S5 RI# Active 0
1Ignored
Wak e Event
NOTE: Filtering/Debounce on RI# will not b e done in the Intel® 6300ESB ICH. Can be in modem
or exter na l.
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When the processor is running extremely hot and is heating up, it is possible (although
very unlikely) that components around it, such as the Intel® 6300ESB ICH, are no
longer executing cycles properly. Therefore, when THRMTRIP# fires and the Intel®
6300ESB ICH is relying on state machine logic to perform the power down, the state
machine may not be working and the system will not power down.
The Intel® 6300ESB ICH will follow this flow for THRMTRIP#.
1. At boot (PXPCIRST# low), THRMTRIP# ignored.
2. After power-up (PXPCIRST# high), when THRMTRIP# sampled active, SLP_S3#,
SLP_S4#, and SLP_S5# fire, and normal sequence of sleep machine starts.
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay
active, even when THRMTRIP# is now inactive. This is the equivalent of “latching”
the thermal trip event.
4. When S5 state reached, go to step #1, otherwise stay here. When the Intel®
6300ES B ICH nev er reach es S5, the Inte l® 6300ESB I CH w ill not re boot unti l power
is cycl ed.
A Processor Thermal trip event will:
Set the AFTERG3_EN bit
Clear the PWRBTN_STS bit
Clear all the GPE0_EN and GPE1_EN register bits
Cle ar the SMB_W AK_STS bi t only when SMB_W AK_STS w as set due to SMBus sla ve
receiving message and not set due to SMBAlert.
Note: The THRMTRIP# pin must be glitch free.
5.11.10 ALT Access Mode
Before entering a low power state, several registers from powered down parts may
need to be saved. In the majority of cases, this is not an issue, as registers have read
and write paths. However, several of the ISA compatible registers are either read only
or write only. To get data out of write-only registers, and to restore data into read-only
registers, the Intel® 6300ESB ICH implements an ALT access mode.
When the ALT access mode is entered and exited after reading the registers of the
Intel® 6300ESB ICH timer (8254), the timer starts counting faster (13.5 ms). The
following steps listed below may cause problems:
1. BIOS enters ALT access mode for reading the Intel® 6300ESB ICH timer related
registers.
2. BIOS exits ALT access mode.
3. BIOS continues through the execution of other needed steps and passes control to
th e O S.
After getting control in step #3, when the OS does not reprogram the system timer
again the timer ticks may be happening faster than expected. For example DOS and its
associated software assume that the system timer is running at 54.6 ms and as a result
the timeouts in the software may be happening faster than expected.
For some other OSs, such as DOS, the BIOS should restore the timer back to 54.6 ms
before passing control to the OS. When the BIOS is entering ALT access mode before
entering the suspend state it is not necessary to restore the timer contents after the
exit from ALT access mode.
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5.11.10.1Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 76 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.
Table 74. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of
2)
Restore Data Restore Data
I/O
Add
r
#
of
Rd
s
Acces
sData I/O
Add
r
#
of
Rd
s
Acces
sData
00h 2 1DMA Chan 0 base addres s low
byte
40h 7
1 Timer Counte r 0 status, bits [5:0]
2DMA Chan 0 base addres s hi gh
byte 2Timer Counter 0 ba se count low
byte
01h 2 1DMA Chan 0 base count low
byte 3Timer Counte r 0 ba se count high
byte
2DMA Chan 0 base count hig h
byte 4Timer Counter 1 ba se count low
byte
02h 2 1DMA Chan 1 base addres s low
byte 5Timer Counte r 1 ba se count high
byte
2DMA Chan 1 base addres s hi gh
byte 6Timer Counter 2 ba se count low
byte
03h 2 1DMA Chan 1 base count low
byte 7Timer Counte r 2 ba se count high
byte
2DMA Chan 1 base count hig h
byte 41h 1 Timer Counte r 1 status, bits [5:0]
04h 2 1DMA Chan 2 base addres s low
byte 42h 1 Timer Counte r 2 status, bits [5:0]
2DMA Chan 2 base addres s hi gh
byte 70h 1 Bit 7 = NMI Enable,
Bit s [6:0] = RTC Address
05h 2 1DMA Chan 2 base count low
byte C4h 2 1DMA Chan 5 base address low
byte
2DMA Chan 2 base count hig h
byte 2DMA Chan 5 base address high
byte
06h 2 1DMA Chan 3 base addres s low
byte C6h 2 1 DMA Ch an 5 base count low byte
2DMA Chan 3 base addres s hi gh
byte 2 DMA Chan 5 base count high byte
07h 2 1DMA Chan 3 base count low
byte C8h 2 1DMA Chan 6 base address low
byte
2DMA Chan 3 base count hig h
byte 2DMA Chan 6 base address high
byte
NOTES:
1. The OCW1 register must be read before entering ALT access mode.
2. Bits 5, 3, 1, and 0 return zero.
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5.11 .10.2Programmable Interrupt Controller (PIC) Reserve d Bits
Many bits within the PIC are reserved, and must have certain v alues written in o rder for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in the following table.
08h 6
1 DMA Chan 0-3 Comm and 2CAh 2 1 DMA Chan 6 base count low byte
2 DMA Chan 0-3 Request 2 DMA Chan 6 bas e count hig h byte
3DMA Chan 0 Mode : Bits(1:0) =
“00” CCh 2 1DMA Chan 7 base address low
byte
4DMA Chan 1 Mode : Bits(1:0) =
“01” 2DMA Chan 7 base addres s hi gh
byte
5DMA Chan 2 Mode : Bits(1:0) =
“10” CEh 2 1 DMA Chan 7 base count low byte
6DMA Chan 3 Mode : Bits(1:0) =
“11”. 2 DMA Chan 7 base count high byte
20h 12
1 PIC ICW2 of Master controller
D0h 6
1 D MA Chan 4-7 Command2
2 PIC ICW3 of Master controller 2 DMA Chan 4-7 Request
3 PIC ICW4 of Master controller 3 DMA Ch an 4 Mod e: Bits(1 :0) =
“00”
4 PIC OCW1 of Master controller14DM A Ch a n 5 Mo d e: B i ts(1:0 ) =
“01”
5 PIC OCW2 of Master controller 5 DM A Ch a n 6 Mo d e: B i ts(1 :0) =
“10”
6 PIC OCW3 of Master controller 6 DM A Ch a n 7 Mo d e: B i ts(1 :0) =
“11”.
7 PIC ICW2 of Slave controller
8 PIC ICW3 of Slave controller
9 PIC ICW4 of Slave controller
1 0 PIC OCW 1 of Slave controlle r1
1 1 PIC OCW 2 of Slave controlle r
1 2 PIC OCW 3 of Slave controlle r
Table 74. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of
2)
Restore Data Restore Data
I/O
Add
r
#
of
Rd
s
Acces
sData I/O
Add
r
#
of
Rd
s
Acces
sData
NOTES:
1. T h e OC W 1 re g i ste r must b e read before entering ALT a ccess mode.
2. Bit s 5, 3, 1, and 0 retu rn zero.
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5.11.10.3Read-Only Registers with Write Paths in ALT Ac cess Mode
The registers described in Table 76 have write paths to them in ALT access mode.
Software will restore these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
5.11.11 System Power Supplies, Planes, and Signals
5.11.11.1Power Plane Control with SLP_S3 #, SLP_S4 # and
SLP_S5#
The SLP_S3# output signal may be used to cut power to the system core supply, since
it will only go active for the STR state (typically mapped to ACPI S3). Power must be
maintained to system memory, the Intel® 6300ESB ICH resume well, and to any other
circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done through the power supply, or by external FETs
to the mothe rb oar d. The SLP _S4# or S LP_S 5# output si gnal ma y be us ed to cu t powe r
to the system core supply, as well as power to the system memory, since the context of
the system is saved on the disk. Cutting power to the memory may be done through
the power supply, or by external FETs to the motherboard.
5.11.11.2PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active at least 16 ms after the power is ensured valid.
Note: Please review these notes regarding the PWROK signal:
Table 75. PIC Reserved Bits Return Values
PIC Reserved Bits Value Returned
ICW2(2:0) 000
ICW4(7:5) 000
ICW4(3:2) 00
ICW4(0) 0
OCW2(4:3) 00
OCW3(7) 0
OCW3( 5) Reflect s bit 6
OCW3(4:3) 01
Tabl e 76. Regi ster Write Accesse s in ALT Access Mode
I/O
Address Register Write Value
08h DMA Status Register for channels 0-3.
D0h DMA Status Register for channels 4-7.
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1. Traditional designs have a reset button logically ANDs with the PWROK signal from
the power supply and the processor’s voltage regulator module. When this is done
with the Intel® 6300ESB ICH, the PWROK_FLR bit will be set. The Intel® 6300ESB
I CH trea ts thi s int ern all y as thou gh the RSMRST# sign al ha d gon e act iv e. Howe ve r,
it is not treated as a full power failure. When PWROK goes inactive and then active
(but RSMRST# stays hi gh), the n th e Intel® 6300ESB I CH will reboot (regardless of
the state of the AFTERG3 bit). When the RSMRST# signal also goes low before
PWROK goes high, then this is a full power failure and the reboot policy is
controlled by the AFTERG3 bit.
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by the Intel® 6300ESB
ICH.
5.11.11. 3VRMPWRGD Signal
The VRMPWRGD signal is not implemented in the Intel® 6300ESB ICH. VRMPWRGD
need to be pulled up to Vcc in order to disable internal legacy logic. If not pulled up,
this logic may come up i n an unknown state.
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5.11.11.4Controlling Leakage and Power Consumption during Low-
Power States
To control leakage in the system, various signal s will tri-state or go low during some
low-power states.
Gen eral pr inci ple s:
All signals going to powered down planes (either internally or externally) must be
either tri-stated or driven low.
Signals with pull-up resistors should not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
Buses should be halted (and held) in a known state to avoid a floating input
(perhaps to some other devi ce). Floating inputs may cause extra power
consumption.
Based on the above principles, the following measures are taken:
During S3 (STR), all signals attached to powered down planes will be tri-stated or
dri ven low.
5.11.12 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 77.
Tabl e 77 . Inte l® 6300ESB ICH Clock Inputs
Clock
Domain Frequency Source Description
CLK66 66 MHz Ma in Clock Generator Clock f or H ub In ter fac e . Should be running in all
Cx state s. St opped i n S3 ~ S5 based o n SLP _S3 #
a sse rtion. This sig n al is n ot 5V tole ra nt .
PCICLK 33 MH z Main Clock Generator
Free-running PCI Clock to the Inte l® 6300 ESB
I CH . Provides timing for all transactions on the
internal primary PCI bus, as well as units inside
the In te l® 6300ESB ICH.
This clock may be stopped in S3, S3 or S5 states.
This signal is not 5V tole ran t.
PXPCICLK 66 MHz Main Clock Generator
Free-running PCI Clock to the Inte l® 6300 ESB
I CH . Provides timing for all transactions on the
internal primary PCI-X bus, as well as units inside
the In te l® 6300ESB ICH.
This clock may be stopped in S3, S3 or S5 states.
This signal is not 5V tole ran t.
CLK48 48 MHz Ma in Clock Generator Used by USB Controllers. Stopped in S3 ~ S5
based on SLP_S3# assertion.
CLK14 14.318 MHz Main Clock Generator Used by ACPI timers. Stopped in S3 ~ S5 based
on SLP_S3# assertion.
AC_BIT _CLK 12.288 MHz AC’97 Cod e c AC’97 Bit Clock: 12.288 MHz serial data clock
gene rate d by the exte rna l COD ECs. Integrated
pull down re sis t or.
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5.11.13 Legacy Power Management Theory of Operation
5.11.13.1Overview
I ns t ea d of re l y in g on A C PI s of t w ar e , l e ga cy power ma na g eme n t u se s B I OS and v a r i ou s
hardware mechanisms. The Intel® 6300ESB IC H has a greatly simplified method for
legacy power management compared with previous component generations.
The scheme relies on the con cept of detecting when individual subsystems are idle,
detecting when the whole system is idle, and detecting when accesses are attempted to
idle subsystems.
Ho wever, the OS is assum ed to be at least APM enabled. Witho ut APM calls, there is no
quick way to know when the system is idle between keystrokes. The Intel® 6300ESB
I CH does not support the burst modes found in previous components.
5.11.13.2A PM Feature Notes
The Intel® 6 300ES B I CH ha s a t ime r th at, when ena bled by the 1M IN_E N bit in t he SMI
Control and Enable register, will generate an SMI# once per minute. The SMI handler
may check for system activity by reading the DEVACT_STS register. When none of the
system bits are set, the SMI hand ler may increment a software counter. When the
counter reaches a sufficient number of consecutive minutes with no activity, the SMI
handler may then put the system into a lower power state. When there is activity,
various bits in the DEVACT_STS register will be set. Software clears the bits by writing
a one to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyb oard controller access es, or audio functions
on LPC or PCI. Other PCI activity may be monitored by checking the PCI interrupts.
5.12 System Management (D31: F0)
5.12.1 Overview of System Management Functions
The Intel® 6300ESB ICH p rovid es vari ous func tions to m ake a syst em easier to manage
and to lower the Total Cost of Ownership (TCO) of the system. It builds on functions
that have been found in prior generat ions of serial interface ACPI-compatible processor
system monitor components products, such as the LM78 and LM80. Features and
functions may be augmented through external A/D converters and GPIO, as well as an
external microcontroller.
The I nte l® 63 00ESB ICH supports the following features and functions:
First Hard Coded Timer to Generate SMI# after Programmable Time.
First timeout causes SMI#. Allows for SMM-Based Recovery from OS lockup.
OS-based software agent accesses the Intel® 6300ESB ICH to periodically reload
timer.
Ability for SMM Handler to generate “TCO” interrupt to OS.
Allows for OS-based code augmentation.
Ability for OS to generate SMI#.
Call-back from OS to TCO code in SMM handler.
Second hard coded timer to generate reboot after programmable time.
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Used only after first timeout occurs.
Second timeout allows for system “reset and reboot” when a hardware error is
detected. Various system states are preserved through this special reset to allow
for possible error detection and correction.
Reset associated with “reboot” may attempt to preserve some registers for
diagnostic purposes.
SMI# handler must periodically reload second timer to prevent “reboot” (timeout
during SMI is assumed as broken processor or stuck hardware).
Option to generate limited reset when second timeout occurs.
Ability to detect aBroken” processor.
Detects when the processor fails to restart after it has been reset.
When processor failure detected, option to pulse a GPIO or send SMBus message.
The SMBus message may be used to indicate to an external LAN controller to send
a distress message. The GPIO may control an LED with optional blink.
Ability to Handle Various Errors (such as ECC Errors) Indicated by MCH.
Can generate SMI# or TCO interrupt.
Intruder Detect input when the system c over is removed.
May generate TCO interrupt or SMI#.
Ability for TCO messages to coexist with standard SMBus devices.
Detection of bad FWH progr amming. Done by checking that data on the first read is
not FFh.
5.12.2 TCO Signal Usage
5.12.2.1 Intruder# Signal
This signal may be used to detect the chassis being opened. The activation of this
signal may be used to cause an SMI#, and is reported through the Heartbeat/Event
mechanism. When SMI# is desired, the signal’s level may be read, so this may be used
as a type of General Purpose Input.
5.12.2.2 Pin Straps
Some the TCO functions are decided at powerup (rising edge of PWROK). See
Section 3.21, “Pin Straps” for specific assignments of the pin straps.
5.12.2.3 SMLINK Signals
The Intel® 6300ESB ICH supports TCO compatible mode connectivity. The Intel®
6300ESB ICH supports LAN controllers. A LAN controller can be used to receive or
retrieve TCO message or information on Host SMBus if needed. In Legacy TCO mode
messages will be driven via SMLink. For the I ntel® 6300 ESB IC H, messag es o n th is l ink
will use SMBus protocol at the rates described in Section 5.12, “System Management
(D31:F0)” for TCO compatible mode.
Note: All mention of “LAN” refers to an external LAN controller.
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5.12.3 TCO Theory of Operatio n
5.12.3.1 Overview
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality be provided without the aid of an external microcontroller.
5.12.3.2 Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. When the
processor fails to fetc h the first inst ruction after res et, the TCO t imer will timeout twice
and the Intel® 6300ESB ICH will assert PXPCIRST#.
When TCO Reboots are not enabl ed, then the Intel® 6300ESB ICH will either:
The SMLink will still send out the first 8 bits of the message. After the eighth bit,
the logic will stall because there is no integrated LAN controller to send the ACK.
The logic will abort the transfer. External logic may monitor the toggling and use
that to drive LED.
If an LAN controller is connected: send the appropriate message to the LAN
controller.
When TCO Reboots are enabled, then the Intel® 6300ESB ICH will attempt to reboot
the syst em.
Note: When the NO-REBOOT bit (D31:F0:Offset D4:bit 1) is set (no reboots are intended),
and the SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is set, and the DOACPU_STS
bit (TCO I/O Offset 06h, bit 2), the Intel® 6300ESB ICH will indicate this in the TCO
message by setting the CPU Missing bit in the message.
When the NO-REBOO T bit is n ot set (reb oots intend ed), and the SECOND_T O_STS bit i s
set, the Intel® 6300ESB ICH will attempt to reboot. After the reboot, the
SECOND_TO_STS bit will still be set. When the processor fails to fetch the first
instruction, the DOA _CPU_STS bit is set, and when the TCO timer times out (actually
for the third time, the first 2 times caused the SECOND_TO_STS bit to be set), the
Intel® 6300ESB ICH will set the CPU MISSING EVENT bit for the TCO message.
5.12.3.3 Handling an OS Lockup
Und er so me co nd it io ns, the O S ma y lo ck up . To hand le t hi s, the T CO Ti mer i s use d with
the following algorithm:
1. BIOS p rog ra ms the TCO Timer, through th e TCO _TMR re gist er, wi th an i nit ial v alue .
Generally, this will probably be set to four seconds, but could be greater.
2. An OS-based software agent periodically writes to the TCO_RLD register to reload
the timer and keep it from generating the SMI#. The software agent may read the
TCO_RLD register to see when it is close to timing out, and possibly determine if
the time-out should be increased.
3. When the timer reaches 0, an SMI# may be generated. This should only occur
whe n the OS wa s no t able to reloa d the tim er. It is a ssumed that the OS will not be
able to reload the timer if it has locked up.
4. Upon generating the SMI#, the TCO Timer automatically reloads with the value in
the TCO_TMR register and start counting down.
5. The SMI handler may then:
a. Read the TIMEOUT bit in the TCO_STS register to check that the SMI# was
caused by the TCO timer.
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b. Write to the TCO_RLD register to reload the timer to make sure the TCO timer
does not reach 0 again.
c. Attempt to recover. May need to periodically reload the TCO timer.
The exact recovery algorithm will be system-specific.
When after the TIMEOUT SMI is generated, and the TCO timer again reaches 0, and
reboots are enabled, the System Management logic will reset (and reboot) the system.
This would be in the case where the processor or system is locked up. During every
boot, BIOS should read the SECOND_TO_STS bit in the TCO_STS register to see if this
is normal boot or a reboot due to the timeout.
5.12.3.4 Handling an Intruder
The Intel® 6300ESB ICH has an input signal, INTRUDER#, that may be attached to a
switch that is activated by the system’s case being open. This input has a two RTC clock
debounce. When INTRUDER# goes active (after the debou ncer), this will set the
INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register
may enab le the Int el® 6300ESB ICH to cause an SMI# or interrupt. The BIOS or
interrupt handler may then cause a transition to the S5 state by writing to the SLP_EN
bit.
The software may also directly read the status of the INTRUDER# signal (high or low)
by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a
GPI whe n the intruder function is not required.
When the INTRUDER# signal goes inactive some point after the INTRD_DET bit is
written as a 1, the I NTRD_DET signal will go to a 0 when INTRUDER# input signal goes
inactive. Note that this is slightly different than a classic sticky bit, since most sticky
bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
Note: The I NTRD_D ET bit resides in the Intel® 6300ESB ICHs RTC well, and is set and
cleared synchronously with the RTC clock. Thus, when software attempts to clear
INTRD_DET (by writing a ‘1’ to the bit location) there may be as much as two RTC
clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER#
signal should be asserted for a minimum of 1 ms in order to ensure that the
INTRD_DET bit will be set.
Note: When the INTRUDER# signal is still active when software attempts to clear the
INTRD_DET bit, the bit will remain set and the SMI will be generated again
immediately. The SMI handler may clear the INTRD_SEL bits to avoid further SMIs.
However, when the INTRUDER# signal goes inactive and then active again, there will
not be furth er S MIs , sin ce the INTR D_SEL b it s woul d s elect t hat no S MI# be generated.
5.12.3.5 Detecting Improper FWH Programming
The Intel® 6300ESB ICH may detect the case where the FWH is not programmed. This
will result in the first instruction fetched to have a value of FFh. When this occurs, the
Intel® 6300ESB ICH will set the BA D_BIOS bit, which may then be reported through
the Heartbeat and Event reporting via an LAN Controller.
5.12.3.6 Handling an ECC Error or Othe r Memo ry Error
The Host Controller provides a message to indicate that it would like to cause an SMI#,
SCI, SERR#, or NMI. The software mu st check the Host Controller as to the exact cause
of the error.
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5.12.4 Heartbeat and Event Reporting through SMLink/
SMbus
SMLink signals are implemented on the Intel® 6300ESB ICH ICH to support TCO
compatible mode. Heartbeat and event reporting are accomplished via the SMLink
signals.
5.12.4.1 Overview
5.12.4.1.1 TCO Compatible Mode
The Intel® 6300ESB ICH may function directly with a LAN Controller to report
me ssages to a network management console without the aid of the system processor.
This is crucial in cases where the processor is malfunctioning or cannot function due to
being in a low-power state.
Note: A system that has locked up and cannot be restarted with a power button press is
assumed to have broken hardware (bad power supply , short circuit on some bus, etc.),
and is beyond the Intel® 6300ESB ICH’s recovery mechanism s.
The basic scheme is for the Intel® 6300ESB ICH to send specific messages through the
SMLink
I/F to the LAN. Upon receiving the SMLink message, the LAN has a prepared Ethernet
me ssage th at it m ay send to a networ k manage ment cons ole. Th e pre pared messa ge is
stored in a non-volatile memory connected directly to the LAN.
Messages will be sent by the Intel® 6300ESB ICH to a LAN either because a specific
event has occurred (see Table 78), or they will be sent periodically (also known as a
Heartbeat). The Event and Heartbeat messages will have exactly the same form.
Whenever an event occurs that causes the Intel® 6300ESB ICH to send a new
message, it will increment its SEQ[3:0] field. For Heartbeat messages, the sequence
number will not increment.
Table 78. Event Transition s that Ca us e Messages
Event Assertion
?Deassertion
?Comments
INTRUD ER# pin Yes No Must be in “heartbeat mode” (G1 or
hung G0).
THRM# pin Yes Yes
Must be in heartbeat mode”. Note
that the THRM# pin is isolated when
the core power is off, thus preventing
this event in S3-S5. Also, the THRM#
pin is sampled with the PCI clock,
which means that THRM# transitions
cannot be det ected in S1-M.
Watchdog Timer Expired Yes N o (N A) “H e a rtb e a t mod e ” e n te re d
SEND_NOW bi t Yes NA Occurs in G0
GPIO[11]/SMBALERT#
pin Yes Yes Must be in “heartbeat mode” (G1 or
hung G0).
CPU_PWR_FLR Yes No “HeartBeat mode” entered {Intel®
6300ESB ICH D CN 36}.
NOTE: The GPIO[11]/SMBALERT# pin will trigger an event message (when enabled by the
GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
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When a triggering event occurs while a message is already being generated and sent,
the new event may not appear in the current message. If not, then a second message
will be generated, with the SEQ[3:0] field incremented, to report the new event.
The following rules/steps apply when the system is in a G0 state and the policy is for
the Intel® 6300ESB ICH to reboot the system after a hardware lockup:
1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel®
6300ESB ICH may send up to 1 Event message to the LAN. The Intel® 6300ESB
ICH will then attempt to reboot the processor.
2. When the reboot at step 1 is successful then the BIOS should clear the
SECOND_TO_STS bit. This will prevent any further Heartbeats from being sent. The
BIOS may then perform addition recovery/boot steps.
Warning:It is im p o r ta nt that the BI OS clear s the SE C O N D _TO_S TS bit, as th e
messages (alerts) will interfere with the LAN device driver from working
properly. The alerts reset part of t he LAN and would prev ent an OSs device
driver from sending or receiving some messages.
3. When the reboot attempt in step 1 is not successful, then the timer will timeout a
third time. At this point the system has locked up and was unsuccessful in
rebooting. The Intel® 6300ESB ICH will not attempt to automatically reboot again.
The Intel® 6300ESB ICH will start sending a message every heartbeat period (30-
32 seconds). The heartbeats will continu e until some external intervention occurs
(reset, power failure, etc.).
4. After step 3 (unsuccessful reboot after third timeout), when the user does a Power
Button Override, the system will go to an S5 state. The Intel® 6300ESB ICH will
continue sending the messages every heartbeat period.
5. After step 4 (power button override after unsuccessful reboot) when the user
presses the Power Button again, the system should wake to an S0 state and the
processor should start executing the BIOS.
6. When step 5 (power button press) is successful in waking the system, the Intel®
630 0ESB ICH wi ll cont inue se nding me ssage s e very hea rtbeat p eriod un til the BIOS
clears the SECOND_TO_STS bit.
7. When step 5 (po wer button press) is unsuccessful in waking the system, the Intel®
6300ESB ICH will continue sending a message every heartbeat period. The Intel®
6300ESB ICH will not attempt to automatically reboot again. The Intel® 6300ESB
ICH will start sending a message every heartbeat period (30-32 seconds). The
heartbeats will continue until some external intervention occurs (reset, power
failure, etc.).
8. After step 3 (unsuccessful reboot after third timeout), when a reset is attempted
(using a button that pulses PWROK low or through the message on the SMBus
slave I/F), the Intel® 6300ESB ICH will attempt to reset the system.
9. After step 8 (reset attempt), when the reset is successful, then the BIOS will be
run. The Intel® 6300ESB ICH will conti nue sen di ng a message ever y hea rtbea t
period until the BIOS clears the SECOND_TO_STS bit.
10.After step 8 (reset attempt), when the reset is unsuccessful, then the Intel®
6300ESB ICH will continue sending a message every heartbeat period. The Intel®
6300ESB ICH will not attempt to reboot the system again without external
intervention.
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The following rules/steps apply when the system is in a G0 state and the policy is for
th e In t e l ® 6300ESB ICH to not reboot the system after a hardware lockup:
1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel®
6300ESB ICH will send a message with the Watchdog (WD) Event status bit set
(and any other bits that must also be set). This message will be sent as soon as the
lockup is detected, and will be sent with the next (incremented) sequence number.
2. After step 1, the Intel® 6300ESB ICH will send a message every heartbeat period
until some external intervention occurs.
3. Rules/steps 4-10 apply when no user intervention (resets, power button presses,
SMBus reset messages) occur after a third timeout of the watchdog timer. When
the intervention occurs before the third timeout, then jump to rule/step11.
4. After step 3 (third timeout), when the user does a Power Button Override, the
system will go to an S5 state. The Intel® 6300ESB ICH will continue sending
heartbeats at this point.
5. After step 4 (power button override), when the user presses the power button
again, the system should wake to an S0 state and the processor should start
executing the BIOS.
6. When step 5 (power button press) is successful in waking the system, the Intel®
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
7. When step 5 (power button press) is unsuccessful in waking the system, the Intel®
6300ESB ICH will continue sending heartbeats. The Intel® 6300ESB ICH will not
attempt to reboot the system again until some external intervention occurs (reset,
power failure, etc.).
8. After step 3 (third timeout), when a reset is attempted (using a button that pulses
PWROK low or through the message on the SMBus slave I/F), the Intel® 6300ESB
I CH will attempt to reset the system.
9. When step 8 (reset a ttempt) is successful, then the BIOS will be run. The Intel®
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
10.When step 8 (reset attempt), is unsuccessful, then the Intel® 6300ESB ICH will
continue sending heartbeats. The Intel® 6300ESB ICH will not attempt to reboot
the system again without external intervention.
11.This and the following rules/steps apply when the user intervention (power button
pre ss, reset, SM Bus message , etc.) occ ur prior t o the third tim eo ut of the w atc hdog
timer.
12.After step 1 (second timeout), when the user does a Power Button Override, the
system will go to an S5 state. The Intel® 6300ESB ICH will continue sending
heartbeats at this point.
13.After step 12 (power button override), when the user presses the power button
again, the system should wake to an S0 state and the processor should start
executing the BIOS.
14 .W he n st ep 13 (po we r bu tt on pres s) is succ e s sfu l in wakin g th e sy ste m , the Int el ®
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
15.When step 13 (power button press) is unsuccessful in waking the system, the
Intel® 6300ESB ICH wi ll c ont inue send ing heartb e ats. The Inte l ® 6300 ESB ICH wil l
not attempt to reboot the system again until some external intervention occurs
(reset, power failure, etc.).
16.After step 1 (second timeout), when a reset is attempted (using a button that
pulses PWROK low or through the message on the SMBus slave I/F), the Intel®
6300ESB ICH will attempt to reset the system.
17.When step 16 (reset attempt) is successful, then the BIOS will be run. The Intel®
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
18.When step 16 (reset attempt), is unsuccessful, then the Intel® 6300ESB ICH will
continue sending heartbeats. The Intel® 6300ESB ICH will not attempt to reboot
the system again without external intervention.
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The following rules will apply when the system is in a G1 (S1-S4) state:
1. The Intel® 6300ESB ICH will send a Heartbeat message every Heartbeat Period
(30-32 seconds).
2. When an event occurs prior to the system being shut down, the Intel® 6300ESB
ICH will immediately send another Event message with the next (incremented)
sequence number.
3. After the event, it will resume sending Heartbeat messages.
Note: There is a boundary condition when a hardware event (event or heartbe at) happens
right as the system is transitioning into a G0 state. In this condition, the hardware will
send messages even though the system will be in a G0 stat e (and the status bits could
potentially indicate that). Normally the Intel® 6300ESB ICH will not send heartbeats in
the G0 state (except in the case of a lockup).
Note: A spurious alert could occur in the following sequence:
a. The processor has initiated an alert using the SEND_NOW bit
b. During the alert, t he THRM#, INTRUDER# or GPI[11] changes s tate
c. The system then goes to a non-S0 state.
Once the system transitions to the non-S0 state, it may send a single alert with an
incremented SEQUENCE number.
Note: An inaccurate alert message may be generated in the following scenario:
a. Th e system successfully boots after a second watchdog Timeout o ccurs.
b. PWROK goes low (typi cally due to a reset button press) or a power
button override occurs (before the SECOND_TO_STS bit is cleared).
c. An alert messag e i ndicat i ng that t he processo r i s missi ng or lock ed up is
gener a t ed with a new sequence number.
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5.13 General P urp o se I/O
5.13.1 GPIO Mapping
Table 79. GPIO Implementation (Sheet 1 of 2)
GPIO Type Alternate
Function Power
Well Tolera
nt Notes
GPI[0] Input
Only PXREQ[2]# Core 5.0 V
GPIO_USE_S EL bit 0 enables REQ/GNT[A]# pair.
Input active status read from GPE0_STS register bit
16.
Input active high/low set through GPI_INV register bit
0.
NOTE: GPEO_STS re gist er, Section 8.8.3.7 GPI_INV
register, Section 8.10.6
GPI[1] Input
Only PXREQ[3]# Core 5.0 V
GPIO_USE_S EL bit 1 enables REQ/GNT[B]# pair.
Input active status read from GPE0_STS register bit
17
Input active high/low set through GPI_INV register bit
1.
GPI[2:5] Input
Only PIRQ[E:H]# Core 5.0 V
GPIO_USE_S EL bit s [2:5] ena b le PIRQ[E:H ]#.
Input active status read from GPE0_STS reg . bits
[18:21].
Input active high/low set through GPI_INV re g. bit
[2:5].
GPI[6] Input
Only Unmuxed Core 3.3 V
Input active status read from GPE0_STS register bit
22.
Input active high/low set through GPI_INV register bit
6.
GPI[7] Input
Only Unmuxed Core 3.3 V
Input active status read from GPE0_STS register bit
23.
Input active high/low set through GPI_INV register bit
7
GPI[8] Input
Only Unmuxed Resum
e3.3 V
Input active status read from GPE0_STS register bit
24.
Input active high/low set through GPI_INV register bit
8.
GPI[11] Input
Only SMBALERT# Resum
e3.3 V
GPIO_USE_SEL bit 11 enables SMBALERT #
Input active status read from GPE0_STS register bit
27.
Input active high/low set through GPI_INV register bit
11.
GPI[12] Input
Only Unmuxed Resum
e3.3 V
Input active status read from GPE0_STS register bit
28.
Input active high/low set through GPI_INV register bit
12.
GPI[13] Input
Only Unmuxed Resum
e3.3 V
Input active status read from GPE0_STS register bit
29.
Input active high/low set through GPI_INV register bit
13.
NOTES:
1. GPIO[0:7], GPIO[1 6:21, 23], and GPIO[32:43] are in the core well.
2. GPIO [8:13] and GPIO[24:28] are in the suspe nd we ll.
3. Core -we ll G PIO are 5V tole rant, excep t for GPIO[ 7:6] and [32:43].
4. Resume-well GPIO are not 5V tolerant.
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
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GPO[16] Outpu
t Only PXGNT [2]# Core 5.0 V Output co ntrolled thro ugh GP_LVL regis te r bit 16.
TTL driv er ou tput
NOTE: GP_LVL register, Section 8.10.4
GPO[17] Outpu
t Only PXGNT [3]# Core 5.0 V Output co ntrolled thro ugh GP_LVL regis te r bit 17.
TTL driv er ou tput
GPO[18] Outpu
t Only Unmuxed Core 5.0 V Output co ntrolled thro ugh GP_LVL regis ter bit s
[18:19].
TTL driv er ou tput
GPO[19] Outpu
t Only Unmuxed Core 5.0 V Output co ntrolled thro ugh GP_LVL regis ter bit s
[18:19].
TTL driv er ou tput
GPO[20 Outpu
t Only Unmuxed Core 5.0 V Output co ntrolled thro ugh GP_LVL regis te r bit 20.
TTL driv er ou tput
GPO[21] Outpu
t Only Unmuxed Core 5.0 V Output co ntrolled thro ugh GP_LVL regis te r bit 21.
TTL driv er ou tput
GPIO[23 Outpu
t Only Unmuxed Core 5.0 V Output co ntrolled thro ugh GP_LVL regis te r bit [23].
TTL driv er ou tput
GPIO[24] I/O Unmuxed Resum
e3.3 V Inp ut active status read from GP_LVL register bit 24.
Output co ntrol led thro ugh GP_LVL regis te r bit 24.
TTL driv er ou tput
GPIO[25] I/O Unmuxed Resum
e3.3 V
Blink e n abled through GPO_BLINK registe r b it 25.
Input active status read from GP_LV L register bit 25
Output co ntrol led thro ugh GP_LVL regis te r bit 25.
TTL driv er ou tput
GPIO[27:2
8] I/O Unmuxed Resum
e3.3 V
Input active status read from GP_LVL register bits
[27:28]
Output co ntrol led thro ugh GP_LVL regis te r bits
[27:28]
TTL driv er ou tput
GPIO[32] I/O WDT_TOUT# Core 3.3 V
GPIO[36:3
3] I PXIRQ[3:0]# Core 3.3 V
GPIO[39:3
7] I/O Unmux ed Core 3.3 V
GPIO[43:4
0] I/O Unmux ed Core 3.3 V These GPIOs have high stre ng th outp u t capability (for
drivin g LED s)
GPIO[57:5
6] OD Unmuxed Resum
e and
RTC 3.3 V
Tab l e 79 . G PI O Im p lem e n ta t ion (S he et 2 of 2)
GPIO Type Alternate
Function Power
Well Tolera
nt Notes
NOTES:
1. GPIO[0:7], GPIO[16:2 1, 23], and GPIO [32:43] are in the core we ll.
2. GPIO[8:13] and GPIO[24:28] are in the sus pend we ll.
3. Core-well G PIO are 5V tole rant, excep t for GPIO[7:6] and [32: 43].
4. Resume-well GPIO are not 5V tolerant.
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
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5.13.2 Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes.
Some Intel® 630 0ES B ICH GP IOs m ay be conn ec ted to pins on d evice s tha t e xi st in th e
core well. When these GPIOs are outputs, there is a danger that a loss of core power
(PWROK low) or a Power Button Override event will result in the Intel® 6300ESB ICH
driving a pin to a logic ‘1’ to another device that is powered down.
5.13.3 SMI # and SCI Routi ng
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither.
See Section 8.8.3.3 f or the routing register
Note: A bit may be routed to either an SMI# or an SCI, but not both.
5.13.4 Triggering
GPIO[0:15] have “sticky” bits on the input. See Section 8.8.3.7 for the GPE0_STS
register. As long as the signal goes active for at least 2 clocks, the Intel® 6300ESB ICH
will keep the sticky status bit active. The active level (high or low) can be selected via
the GP_I NV regis ter.
If the s y ste m i s in an S0 o r S1- D s t at e, th e G PI ar e sa mp l ed at 33 M Hz, so th e s i gnal on ly ne ed s t o
be active for about 60 ns to be latched . In the S3-S 5 s tates, the GP I are sampled at 32.768 KHz, and
thus must be active for at le ast 61 microseconds to be latched.
Note: GPIs that are in the core well are not capable of waking the system from sleep states
where the core well is not powered.
If the input signal is still active when the latch is cleared, it will again be set (another
edge is not required). This makes these signals ìlevelî triggered inputs.
5.14 IDE Controll er (D31:F1 )
5.14.1 Overview
The Intel® 6300ESB ICH IDE controller features two sets of interface signals (Primary
and Secondary) that may be independently enabled, tri-stated or driven low.
The Intel® 6300ESB ICH IDE controller supports both legacy mode and native mode
IDE interface. In native mode, the IDE controller is a fully PCI compliant software
interface and does not use any legacy I/O or interrupt resources.
The IDE interfaces of the Intel® 6300ESB ICH may support several types of data
transfers:
Programmed I/O (PIO): Processor is in control of th e data transfer.
8237 style D MA: DMA protocol that resembles the DMA on the ISA bus, although it
does not u se the 82 37 in th e In tel® 6300E SB ICH. Thi s pr otocol off l oads the p roc essor
from moving data. This allows higher transfer rate of up to 16 Mbytes/s.
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Ultra ATA/3 3: DMA protocol that redefines signals on the IDE cable t o allow both host
and target throttling of data and transfer rates of up to 33 Mbytes/s.
Ultra ATA/66: DMA prot ocol that redefines signals on the IDE cable to allow both host
and target throttling of data and transfer rates of up to 66 Mbytes/s.
Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 100 Mbytes/s.
5.14.2 PIO Transfers
5.14.2.1 Overview
The Intel® 6300ESB ICH IDE controller includes both compatible and fast timing
modes. The fast timing modes may be enabled only for the IDE data ports. All other
transactions to the IDE registers are run in single transaction mode with compatible
timings.
Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The
IDETIM and SIDETIM Registers permit different timing modes to be programmed for
dri ve 0 and drive 1 of the same co nnec tor.
The Ultra ATA/33/66/100 synchronous DMA timing modes may also be applied to each
drive by programming the IDE I/O Configuration register and the Synchronous DMA
Control and Timing registers. When a drive is enabled for synchronous DMA mode
operation, the DMA transfers are executed with the synchronous DMA timings. The PIO
transfers are executed using compatible timings or fast timings when also enabled.
5.14.2.2 IDE Port Decode
The Command and Control Block registers are accessed differently depending on the
decode mode, which is selected by the Programming Interface configuration register
(Offset 09h).
Note: The primary and secondary channels are controlled by separate bits, allowing one t o be
in native mode and the other in legacy mode simultaneously.
5.14.2.3 IDE Legacy Mode and Nativ e Mode
The Intel® 6300ESB ICH IDE controller supports both legacy mode and PCI native
mode. In legacy mode, the Command and Control Block registers are accessible at
fixed I/O addresses, may not be accessed through the I/O BARs. These blocks are
decoded when I/O space is enabled through the P-ATA function’s configuration space
and A TA decode is enab le d throug h th e PTIM/S TIM re gis ter s, bit 15. An a cce ss to the s e
addresses results in the assertion of the appropriate chip select (CS1#/CS3#) and the
command strobes (DIOR#, DIOW#).
There are two I/O ranges for each IDE cable: the Command Block, which corresponds
to the CS1P#/CS1S# chip select, and the Control Block, which corresponds to the
CS3P#/CS3S# chip select. The Command Block is an 8 byte range, while the control
block is a 4 byte range.
Comman d Bloc k O ffset: 01F0h for Pri mary, 0170h for Secondary
Control Block O ffset : 03F4h for Primary, 0374h for Secondary
Table 80 and Table 81 specify the registers and transaction timings as they affect the
Intel® 6300ESB ICH hardware definition.
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Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O
instructions. All other registers should be accessed using 8-bit I/O instructions.
Note: These registers are implemented in the IDE device. Therefore, accesses to these I/O
registers cause corresponding accesses on the IDE interface.
In native mode, the Intel® 6300ESB ICH will not decode the legacy ranges. The same
offsets are used as in Table 80, however, the base addresses are selected using the PCI
BARs, rather than fixed I/O locations.
For accesses to the Alt Status register in the Control Block, the P-ATA host controller
must always force the upper address bit (PDA[2] or SDA[2]) to 1 in order to ensure
proper decode by the P-ATA device. Unlike the Legacy Mode fixed address location, the
Native Mode address for this register may contain a 0 in address bit 2 when it is
received by the P-ATA host controller.
5.14.2.4 PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and
shutdown latency.
Startup latency is incurred when a PCI master cycle targeting the IDE data port is
de coded and the DA[2:0] an d CSxx# li nes are not se t up. Sta rtup la tency prov ide s the
setup time for the DA[2:0] and CSxx# lines prior to assertion of the read and write
strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that t ransactions may occur back-to-back on the IDE
interface (without incurring startup and shutdown latency) without violating minimum
cycle periods for the IDE interface. The command strobe assertion width for the
enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,
or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set
to 1, 2, 3, or 4 PCI clocks.
When IORDY is asserted when the initial sample point is reached, no wait-states are
added to the command strobe assertion length. When IORDY is negated when the
initial sample point is reached, additional wait-states are added. Since the rising edge
of IORDY must be synchronized, at least two additional PCI clocks are added.
Table 80. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)
I/O Offset Registe r Function (Read ) Register Function (Writ e)
00h Data Data
01h Error Features
02h Sector Count Sector Count
03h Sector Number Secto r Number
04 h Cylind e r Lo w Cylind e r Low
05 h Cylind e r Hig h Cylind e r High
06h Drive Head
07h Status Command
NOTE: For acces ses to the A lt S ta tus reg ister in the Control Bloc k, the Intel® 6300ESB ICH
must alwa y s fo rce the upper a d dr e ss bit (PD A[2] or SDA[2] ) to 1 in order to ens ure
proper native mode decode by the IDE device. Unlike the legacy mode fixed a ddress
location, the native mode address for this register may contain a 0 in address bit 2 when
it is re ce ived by the Inte l® 6300ESB ICH.
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Shutdown latency is incurred after outstanding scheduled IDE data port transactions
(either a non-empty write post buffer or an outstanding read prefetch cycles) have
completed and before other transactions may proceed. It provides hold time on the
DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and
DIOW#). Shutdown latency is two PCI clocks in duration.
The IDE timings for various transaction types are shown in Table 81.
Note that bit 2 (16-bit I/O recovery enable) of the ISA I/O Recovery Timer Register
does not add wait-states to IDE data port read accesses when any of the fast timing
modes are enabled.
5.14.2.5 IORDY Masking
The IORDY signal may be ignored and assumed asserted at the first IORDY Sample
Point (ISP) on a drive by drive basis through the IDETIM Register.
5.14.2.6 PIO 32-Bit IDE Data Port Accesses
A 32- bi t PCI tr ansacti on run to th e IDE data ad dre ss (01F0h p rimary, 0170h s ec ondary)
results in two back to back 16-bit transactions to the IDE data port. The 32-bit data
port feature is enabled for all timings, not just enhanced timing. For compatible
timings, a shutdown and startup latency is incurred between the two 16-bit halves of
the IDE transaction. This ensures that the chip selects will be deasserted for at least
two PCI clocks between the two cycles.
5.14.2.7 PIO IDE Data Port Prefetching and Posting
The Intel® 6300ESB ICH may be programmed th rough th e IDETIM registers to allow
data to be posted to and prefetched from the IDE data ports.
Data pre fetching is initiated when a data port read occurs. The read prefetch
eliminates latency to the IDE data ports and allows them to be performed back to back
for the highest possible PIO data transfer rates. The first data port read of a sector is
called the demand read. Subsequent data port reads from the sector are called
prefetch reads. The demand read and all prefetch reads much be of the same size (16
or 32 bits).
Data posting is performed for writes to the IDE data ports. The transaction is completed
on the PCI bus after the data is received by the Intel® 6300ESB ICH. The Intel®
6300ESB ICH will then run the IDE cycle to transfer the data to the drive. When the
Intel® 6300ESB ICH write buffer is non-empty and an unrelated (non-data or opposite
channel) IDE transaction occurs, that tr ansaction will be stalled until all current data in
the write buffer is transferred to the drive.
Table 81. IDE Transaction Timings (PCI Clocks)
IDE Trans act ion Type Startup
Latency
IORDY
Sample
Point (ISP)
Recover y Time
(RCT) Shutdown
Latency
Non-Data Port Compatible 4 11 22 2
Data Port Comp a tib le 3 6 14 2
Fa st Ti ming Mode 2 2 1 2
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5.14.3 Bus Maste r Functi on
The Intel® 630 0ESB ICH ma y ac t a s a PCI B us ma ste r o n b e hal f of an IDE sl a v e de v ice .
Two PCI Bus master channels are provided, one channel for each IDE connector
(p ri ma ry an d se con da ry ). B y per for m in g t he I DE d ata tr an sf e r as a PC I B us master, th e
Intel® 6300ESB ICH off-loads the processor and improves system performance in
multitasking environments. Both devices attached to a connector may be
pr ogr ammed for b us mast er tr ansfe rs, but only one de vi ce per co nnect or may be a ctive
at a time.
5.14.3.1 Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.
The data transfer proceeds until all regions described by the PRDs in the table have
been transferred. Note that the Intel® 6300ESB ICH bus master IDE function does not
support memory regions or descriptor tables located on ISA.
D escr ip tor Tab le s mus t not cro ss a 64-K by te bo undar y. Each PRD e ntr y i n th e t ab l e is 8
byte s in l eng th. The firs t 4 by tes spe cif y the b yte addre ss of a ph ysica l memory regi on.
Th is m emory re gio n m ust b e DWOR D al igne d and must not cr os s a 64- Kb yte bound ar y.
The next two bytes specify the size or transfer count of the region in bytes (64-Kbyte
limit per region). A value of zero in these two bytes indicates 64 Kbytes (thus the
minimum transfer count is 1). When bit 7 (EOT) of the last byte is a 1, it indicates that
this is the final PRD in the Descriptor table. Bus master operation terminates when the
last descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of
the Base Address is masked and byte enables are asserted for all read transfers. When
writing data, bit 1 of the Base Address is not masked and if set, will cause the lower
WORD b yte en ables to be deass ert ed for th e fir st DWO RD tr an sfe r. The wri te to PC I will
typically consist of a 3 2-byte cache line. When valid data ends prior to end of the cache
line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to
or greater than the si ze of the disk transfer request. When greater than the disk
transfer request, the driver must terminate the bus master transaction (by setting bit 0
in the Bus Master IDE Comman d Register to zero) when the drive issues an int errupt to
signal transfer completion.
Figure 16 . Physical Region Descriptor Table Entry
051910_3.d
rw
Byt e 3
Byte 2
Byte 1 Byt e 0
EOT
Reserved
Byte Count [15:1]
Memory Region Physical Base Address [31:1]
Memory
Region
Main Memory
0
0
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5.14.3.2 Line Buffer
A single line buffer exists for the Intel® 6300ESB ICH Bus master IDE interface. This
buffer is not shared wit h any other function. The buffer is maintained in either the read
state or the write state. Memory writes are typically 4-DWORD bursts and invalid
DWORDs have C/BE[3:0]#=0Fh. The line buffer allows burst data transfers to proceed
at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically
when the controller has transferred all data associated with a Descriptor Table (as
determined by EOT bit in last PRD). The IDE Interrupt Status bit is set when the IDE
device generates an interrupt. These events may occur prior to line buffer emptyi ng for
mem o ry wr i t es . Wh en ei t h er of t h es e c o nd i ti o ns ex i st, al l PC I Ma s te r no n -Me m o ry re a d
accesses to the Intel® 6300ESB ICH are retried until all data in the line buffers has
been transferred to memory.
5.14.3.3 Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO
transfers. The DMA Timing Enable Only bits in IDE Timing register may be used to
program fast timing mode for DMA transactions only. This is useful for IDE devices
whose DMA transfer timings are faster that its PIO transfer timings. The IDE device
DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is
deasserted. When inactive, the DMA Acknowledge signal is deasserted on th e next PCI
clock and no more transfers take place until DMA request is asserted again.
5.14.3.4 Interrupts
Legacy Mode:
The Intel® 6300E SB ICH is conne ct ed t o IRQ14 f or the prima ry inte rrup t and IRQ1 5 for
the secondary interrupt. This connection is done from the ISA pin, before any mask
registers. This implies the following:
Bus Master IDE is operating under an interrupt based driver. Therefore, it will not
operate under environments where the IDE device drives an interrupt but the
interrupt is masked in the system.
Bus Master IDE devices are connected directly off of the Intel® 6300ESB ICH. IDE
interrup ts cannot be communicated through PCI devices or the serial stream.
Caution:In thi s m o d e , th e Intel® 6300ESB ICH will not drive the PCI Interrupt
associated with this function. That is only used in nati ve mode.
Native Mode:
In this case both the Primary and Secondary channels share an interrupt. It will be
internally connected to PIRQ[C]# (IRQ18 in APIC mode). The interrupt will be active-
low and shared.
Behavioral notes in native mode
The IRQ1 4 and IRQ 15 pi ns do not affe ct th e i nternal IR Q14 and IRQ15 inp uts to the
interrupt controllers. The IDE logic forces these signals inactive in such a way that
the Serial IRQ source may be used.
The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt
controller may come from other sources (Serial IRQ, PIRQx).
The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
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When switching the IDE controller to native mode, the IDE Interrupt Pin Register
will be masked (see Section 9.1. 19, “Offset 3Dh: INTR_PNInterrupt Pin Register
(IDE—D31:F1)”). When an interrupt occurs while the masking is in place and the
interrupt is still active when the masking ends, the interrupt will be allowed to be
asserted.
The active-low PIRQ must be masked by hardware when the IOSE bit is cleared in
order to allow other interrupts that are shared with this pin to be delivered and
serviced. When the IOSE bit is 0, software may not clear the IDE i nterrupt status
bits. When in Native Mode, a ‘1’ in the Bus Master Interrupt status bit (bit 2 of BMISP/BMISS) forces
the interrupt asserted. This bit must be cleared in order to deassert the interrupt. This implementation is
different from the L egacy Mode.
5.14.3.5 Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following
steps are required:
1. Software prepares a PRD Table in system memory. The PRD Table must be DWORD
aligned and must not cross a 64-Kbyte boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table
Pointer Register. The direction of the data transfer is specified by setting the Read/
Write Control bit. The interrupt bit and Error bit in the Status register are cleared.
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a '1' to the Start bit in the
Command Register. The first entry in the PRD table is fetched and loaded into two
registers which are not visible by software, the Current Base and Current Count
registers. These registers hold the current value of the address and byte count
loaded from the PRD table. The value in these registers is only valid when there is
an active command to an IDE device.
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. Th e controller tran sfers data to/from memory responding to DMA reques ts from the
IDE device. The IDE device and the host controller may or may not throttle the
t rans fer s e ver al ti mes. Wh en the last d ata tr a nsfe r for a reg ion ha s be en c omple ted
on the IDE interface, the next descriptor is fetched from the table. The descriptor
contents are loaded into the Current Base and Current Count registers.
7. At the end of the transfer the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command
register. It then reads the controller status followed by the drive status to
determine when the transfer completed successfully.
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data
transfers will terminate when the physical region described by the last PRD in the table
has been completely transferred. The active bit in the Status Register will be reset and
the DDRQ signal will be masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state)
when a terminal count condition exists; that is, the current region descriptor has the
EOL bit set and that region has been exhausted. The buffer is also flushed (write state)
or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register
is set. Software that reads the status register and finds the Error bit reset, and either
the Active bit reset or the Interrupt bit set, may be assured that all data destined for
syst em mem ory has bee n transf erred an d that data is valid in system memory.
Table 82 describes how to interpret the Interrupt and Active bits in the Status Register
after a DMA transfer has started.
During concurrent DMA or Ultra ATA transfers, the Intel® 6300ESB ICH IDE interface
will arbitrate between the primary and secondary IDE cables when a PRD expires.
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5.14.3.6 Error C on d itions
IDE devices are sector based mass storage devices. The drivers handle errors on a
sector basis; either a sector is transferred successfully or it is not. A sector is 512
bytes.
When the IDE device does not complete the transfer due to a hardware or software
error, the command will e ve ntual ly b e stopped by the d rive r sett in g Command Start bit
to zero when the driver times out the disk transaction. Information in the IDE device
registers help isolate the cause of the problem.
When the controller encounters an error while doing the bus master transfers, it will
stop the transfer (i.e., reset the Active bit in the Command register) and set the Error
bit in the Bus Master IDE Status register. The controller does not generate an interrupt
when this happens. The device driver may use device specific information (PCI
Configuration Space St atus register and IDE Drive Register) to determine what caused
the error.
Whenever a requested transfer does not complete properly, information in the IDE
device registers (Sector Count) may be used to determine how much of the transfer
was completed and to construct a new PRD table to complete the requested operation.
In most cases the existing PRD table may be us ed to complete the operation.
5.14.3.7 8237-L ike Protocol
8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins
familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/
write strobes. These pins have similar characteristics to their ISA counterparts in terms
of when data is valid relative to strobe edges, and the polarity of the strobes, however
the Intel® 6300ESB ICH does not use the 8237 for this mode.
Table 82. Interrupt/Active Bit Interaction Definition
Interrup
tActive Description
01
DMA transfer is in progress. No interrupt has been generated by the IDE
device.
10
The IDE device generated an interr upt . The contr oll er exh aust ed the
Physical Region Descriptors. This is the normal completion case where the
size of the physical memory regi ons was equal to the IDE device transfer
size.
11
The IDE device generated an interrupt. The controller has not reached the
end of the phy sical memory regions. This is a valid completion case where
the size of the physi cal memory regio ns was larg e r than the IDE devi ce
transf er size .
00
This bit comb ina tion signals a n er ror condition . W h e n th e Error b it in the
sta tu s re g ist e r is se t , th e cont roller has some pr ob le m transferring data
to/fr om me mory. Specific s of the err or have to be d e te rmined using bus-
spec ific inf ormation. When the Error b it is not set, then the PRD's
specified a smaller size than the IDE transfer size.
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5.14.4 Ultra ATA/33 Protocol
Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for
each IDE device. The IDE signal protocols are significantly different under this mode
than for the 8237 mode. These differe nces allow the following enhancements to the
transfer:
A source synchronous protocol to allow higher data transfer rates of up to 33
Mbytes/s. The device that drives the data lines also drives the data strobe signal.
Both the source and destination may pause the transfer. The source pauses the
burst by not toggling its strobe signal, while the destination pauses the burst by
deasserting a redefined signal, DMARDY#.
16 bit wide CRC error checking, sent from the Intel® 6300ESB ICH to the IDE
device on DDACK# deassertion.
Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33
capable IDE controller such as the Intel® 6300ESB ICH and one or more Ultra ATA/33
capable IDE devices. It utilizes the standard Bus Master IDE functionality and interface
to initiate and control the transfer. Ultra ATA/33 utilizes a “source synchronous
signaling protocol to transfer data at rates up to 33 Mbytes/s. The Ultra ATA/33
definition also incorporates a Cyclic Redundancy Checking (CRC-16) error checking
protocol.
5.14.4.1 Signal Descriptions
The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does
redefine a number of the standard IDE control signals when in Ultra ATA/33 mode.
These redefinitions are shown in the following table. Read cycles are defined as
transferring data from the IDE device to the Intel® 6300ESB ICH. Write cycles are
defined as transferring data from the Intel® 6300ESB ICH to IDE device.
The DIOW# signal is redefined as STOP for both read and write transfers. This is always
driven by the Intel® 6300ESB ICH and is used to request that a transfer be stopped or
as an acknowledgment to stop a request from the IDE device.
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device
to th e Intel ® 63 00ES B ICH (r ead). It i s u sed b y the In tel® 6300E SB IC H to signa l when
it is ready to transfer data and to add wai t-states to the current transaction. The
DIOR# signal is redefined as STROBE for transferring data from the Intel® 6300ESB
ICH to the IDE device (write). It is the data strobe signal driven by the Intel® 6300ESB
ICH on which data is transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to
the Intel® 6300ESB I CH (re ad). I t is the d ata st robe sig nal dr iv en b y the IDE devi ce on
which data is transferred during each rising and falling edge transition. The IORDY
signal is redefined as DMARDY# for transferring data from the Intel® 6300ESB ICH to
the IDE device (write). It is used by the IDE device to signal when it is ready to t ransfer
data and to add wait-states to the current transaction.
Table 83. UltraATA/33 Control Signal Redefinitions
Standard IDE
Signal
Definition
Ultra ATA/33
Read Cycle
Definition
Ultra ATA/33
Wr ite Cycle
Definition
Intel®
6300ESB ICH
Primary
Channel
Signal
Intel®
6300ESB ICH
Second ary
Channel
Signal
DIOW# STOP STOP PDIOW# SDIOW#
DIOR# DMARDY# STROBE PDIOR# SDIOR#
IORDY STROBE DMARDY# PIORDY SIORDY
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All other signals on the IDE connector retain their functional definitions during Ultra
ATA/33 operati on .
5.14.4.2 Operation
Init ial setup programming consists of enabling and performing the proper configuration
of the Intel® 6300ESB ICH and the IDE device for Ultra ATA/33 operation. For the
Intel® 6300ESB ICH, this consists of enabling synchronous DMA mode and setting up
appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE
programming model is followed. Once progr ammed, the drive and Intel® 630 0ESB IC H
control the transfer of data through the Ultra ATA/33 protocol. The actual data transfer
consists of three phases, a start-up phase, a data transfer phase, and a burst
termination phase.
The IDE device begins the start -up phase by asserting DMARQ signal. When ready to
begin the transfer, the In tel® 6300ESB ICH will assert DMACK# signal. When DMACK#
signal is asserted, the host controller will drive CS0# and CS1# inactive, DA0–DA2 low.
For write cycles, the Intel® 6300ESB ICH will deassert STOP, wait for the IDE device to
assert DMARDY#, and then drive the first data word and STROBE signal. For read
cycles, the Intel® 6300ESB ICH will tri-state the DD lines, deassert STOP, and assert
DMARDY#. The IDE device will then send the first data word and STRO BE.
The data transfer phase continues the burst transfers with the data transmitter (Intel®
6300ESB ICH - writes, IDE device - reads) providing data and toggling STROBE. Data is
transferred (latched by receiver) on each rising and falling edge of STROBE. The
tr ansmi tte r may paus e the b urs t by h ol ding S TROBE hig h or low, res umin g the burs t b y
again toggling STROBE. The receiver may pause the burst by deasserting DMARDY#
and resumes the transfers by asserting DMARDY#. The Intel® 6300ESB ICH will pause
a burst transaction in order to prevent an internal line buffer over or under flow
condition, resuming once the condition has cleared. It may also pause a transaction
when the current PRD byte count has expired, resuming once it has fetched the next
PRD.
Warning:The curren t burst may be terminated by either the transmitter or receiver. A
burst termination consists of a S top Request, Stop Ac knowledge and tran sfer
of CRC data. The Intel® 6300ESB ICH may stop a burst by assert ing STOP,
with the IDE devi ce acknowledging by deassert ing DMARQ. The IDE device
stops a burst by deasserting DMARQ and the Intel® 63 00 ESB ICH
acknowle dges by asserting STOP. The transmitter then drives the ST ROBE
signal to a hi gh level . The Intel® 6300ESB ICH will t he n d r ive th e C R C va lue
onto th e DD lines an d deassert DMACK#. Th e IDE device will latch the CRC
value on rising edge of D MAC K #. The Inte l® 63 00ESB IC H will t e rm inate a
burst tran sfer when it needs t o service the opposite IDE channel, wh en a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running
th e bur st, or up on transfe rr ing the las t d a ta f rom the fin a l P R D.
5.14.4.3 CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33
transfers. The CRC value is calculated for all data by both the Intel® 6300ESB ICH and
the IDE device over the duration of the Ultra ATA/33 burst transfer segment. This
segment is defined as all data transferred with a valid STROBE edge from DDACK#
assertion to DDACK# deassertion. At the end of the transfer burst segment, the Intel®
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6300ESB ICH will drive the CRC value onto the DD[15:0] signals. It is then latched by
the IDE device on deassertion of DDACK#. The IDE device compares the Intel®
6300ESB ICH CRC value to its own and reports an error if there is a mismatch.
5.14.5 Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the Intel® 6300ESB ICH supports the Ultra ATA/66
prot ocol. The Ultr a A T A/ 66 prot ocol is e nabled through con fig bits 3:0 at of fs et 54h. The
two protocols are similar, and are intended to be device driver compatible. The Ultra
ATA/66 logic may achieve transfer rates of up to 66Mbytes/s.
In order to achieve the higher data rate, the timings are shortened and the quality of
the cable is improved to reduce reflections, noise, and inductive coupling. Note that the
improved cable is required and will still plug into the standard IDE connector.
The Ultra ATA/66 protocol also supports a 44 Mbytes/s mode.
5.14.6 Ul tra A TA/100 Protocol
When the ATA_FAST bit is set for any of the four IDE devices, then the timin gs for the
transfers to and from the corresponding device run at a higher rate. The Intel®
6300ESB ICH Ultra ATA/100 logic may achieve read transfer rates up to 100 Mbytes/s,
and write transfer rates up to 88.9 Mbytes/s.
The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so
no further cable improvements are required when implementing Ultra ATA/100.
5.14.7 Ultra ATA/33/66/100 Ti ming
Th e t imi ngs f or U l tr a AT A/ 3 3/66/100 modes are p rog ra mme d t hroug h the S y nch rono us
DMA Timing Register and the IDE Configuration Register. Different timings may be
programmed for each drive in the system. The Base Clock frequency for each drive is
selected in the IDE Configuration Register. The Cycle Time (CT) and Ready to Pause
(RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous
DMA Timing Register. The Cycle Time represents the minimum pulse width of the data
strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock
periods that the Intel® 6300ESB ICH will wait from deassertion of DMARDY# to the
assertion of STOP when it desires to stop a burst read transaction.
Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle
Time (CT) must be set for three Base Clocks. The Intel® 6300ESB ICH will thus toggle
the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe
edge . This m eans tha t th e I ntel® 6300E SB IC H will p er form Mod e 5 wri te transfer s at a
maximum rate of 88.9 Mbytes/s. For read transfers, the read strobe will be driven by
the ATA/100 devi ce, and the Intel® 6300ESB ICH supports reads at the maximum rate
of 100 Mbytes/s.
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5.15 SATA Host Con tro l le r (D31:F2)
5.15.1 Overview
The Intel® 6300ESB ICH SA T A controller features two sets of interface signals that may
be independently enabled, tri-stated or driven low. Each interface is supported by an
independent DMA controller.
The Intel® 6300ESB ICH SATA controller interacts with an attached mass storage
device through a register interface that is equivalent to that presented by a traditional
IDE host adapter. The host software follows existing standards and conventions when
accessing the register interface and follows standard command protocol conventions.
5.15.2 Theory of Operation
5.15.2.1 Standard ATA Emulation
The Intel® 6300ESB ICH contains a set of register s that shadow the contents of the
legacy IDE registers. The behavior of the Command and Control Block registers, PIO
and DMA data transfers, resets, and interrupts are all emulated.
5.15.2.2 48-bit LBA Operation (Logical Block Addressing)
The SATA host controller supports 48-bit LBA through the host-to-device register FIS,
Frame Information Structure, when accesses are performed through writes to the task
file. The SATA host controller will ensure that the correct data is put into the correct
byte of the host-to-de vic e FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16 bits. Since the registers are only 8 bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
When software clears bit 7 of the control register before performing a read, the last
item written will be returned from the FIFO. When software sets bit 7 of the control
register before performing a read, the first item written will be returned from the FIFO.
5.15.3 Hot Plug Operation
Dynamic hot plug (such as surprise removal) is not supported by the SATA Host
controller. However, using the SPC register configuration bits, and power management
flows, a device may be powered down by software, and the port may then be powered
off, allowing removal and insertion of a new device.
5.15.4 Power Management Operation
Power management of the Intel® 6300ESB ICH SATA Controller and ports will cover
operations of the host controller and the SATA wire.
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5.15.4.1 Power State Mappings
The following PCI power management states for devices are supported by the Intel®
6300ESB ICH SATA Controller:
D0 – working
D3 – very deep sleep. This state is split into two sub-states, D3HOT (may respond to
PCI configuration accesses) and D3COLD (cannot respond to PCI configuration
accesses). These two sub-states are considered the same, where D3HOT has VCC, but
D3COLD does not. This is the only state allowed for the host controller when the system
is in an S1-S5 state.
SATA devices may also have multiple power states. From parallel ATA, three device
states are supported through ACPI. They are:
D0 – Device is working and instantly available.
D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency
fro m th is st ate is in se co nd s
D3 – from the SATA device’s perspective, no different than a D1 state, in that it is
entered through the STANDBY IMMEDIATE command. However, an ACPI method is also
called which will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Fi nal ly, SATA de fin es thre e PH Y la ye r p owe r s tat es , wh ich ha v e no equivalent map ping s
to parallel ATA. They are:
PHY READY – PHY logic and PLL are both on and active
Partial PHY logic is powered, but in a reduced state. Exit latency is no longer than 10
ns
Slumber – PHY logic is powered, but in a reduced state. Exit latency may be up to 10
ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA Controller defines these states as sub-states of the device D0 state.
Figure 17. SATA Power States
Host = D0
Device = D3
Power
Resume Latency
Host = D3
Device = D3
PHY =
OFF
Device = D0
PHY =
Ready
Device = D1
PHY =
Slumber
PHY =
Partial PHY =
Off (port
disabled)
PHY =
Slumber PHY =
Off (port
disabled)
PHY =
Slumber PHY =
Off (port
disabled)
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5.15.4.2 Power State Transitions
5.15.4 .2.1 Pa rtia l and Slumbe r State Entry/E xit
The partial and slumber states save interface power when the interf ace is idle. I t would
be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the
interface may have power saved while no commands are pending.
The SATA Controller defines PHY layer power management (as performed through
primitives) as a driver operation from the host side, and a device proprietary
mechanism on the device side. The SATA Controller will accept device transition types,
but will not issue any transitions as a host. All received requests from a SATA device
will be ACKed.
When an operation is performed to the SATA Controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
5.15.4.2.2 Device D1, D3 States
These states are entered after some perio d of time when software has determined th at
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
5.15.4.2.3 Host Controller D3 state
Aft er the i nter fac e and dev ice hav e b een put i nto a low powe r sta te, the host contr oll er
may be put into a low power state. This is performed through the PCI power
management registers in configuration space.
There are two very important aspects to note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the memory or I/O sp aces must result in master abort.
2. When the power state is D3, no interrupts may be generated, even when they are
enabled. When an interrupt status bit is pending when the controller transitions to
D0, an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as though no device is present on the
cable, and power will be minimized.
5.15.4.3 SMI Trapping (APM)
Offs et 48h, bits 3:0 i n the p ower m anag ement I/ O sp ace con tain c ont r ol f or gene r ati ng
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges only
(1f0- 1f7h, 3f6 h, 170-177h, an d 376h). Whe n the S A T A contr oller is in legac y mo de and
is using these addresses, accesses to one of these ranges with the appropriate bit set
will cause the cycle to not be forwarded to the SATA controller, and an SMI# is
generated.
To block accesses to the native IDE ranges, software must use the generic Power
Management control registers described in Section 8.8.1.7, “Offset C4h, C6h, C8h,
CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4-7 (PM—
D31:F0)”.
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5.15.5 SATA Interrupts
The following table summarizes interrupt behavior for MSI and wire-modes. In the
table “bits” refers to the 4 possible interrupt bits in I/O space, which are: BMISP.PRDIS
(offset 02h, bit 7), BMISP.I (offset 02h, bit 2), BMISS.PRDIS (offset 0Ah, bit 7), and
BMISS.I (offset 0Ah, bit 2). See Section 20.2, “Bus Master IDE I/O Registers (D31:F2)”
for I/O space register details.
5.15.6 SATALED#
The SATALED# pin is driven low to indicate SATA drive activity. When SATALED# is
asser te d, the LE D is act ive.
5.16 Multimedia Event Timers
5.16.1 Overview
This function provides a set of timers that may be used by the operating system. The
t im e rs are de f i ne d s u ch t hat i n t h e f ut u r e, th e OS ma y be ab l e to as s i gn spe c if i c ti m er s
to be used directly by specific applications. Each timer may be configured to cause a
separate interrupt. This speci ficat ion allows for a block of 32 timers, with support for up
to eight blocks, for a total of 256 timers. However, specific implementations may
include only a subset of these timers.
The Intel® 6300ESB ICH provides three timers. The three timers are implemented as a
single counter each with its own comparator and value register. Each timer’s counter
increases monotonically. Each individual timer may generate an interrupt when the
value in its value register matches the value in the main counter. Some of the timers
may be enabled to generate a periodic interrupt.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware may
support an assignable decode space, however the BIOS will set this space prior to
handing it over to the OS (see Section 6.4, “Memory Map”). It is not expected that the
OS will move the location of these timers once it is set by the BIOS.
In the Intel® 6300ESB ICH, one timer block is implemented. The timer block has one
counter and three timers (comparators). Future devices may have a different number
of imple mented tim ers. Various cap abili tie s reg iste rs in dica te the n umber of ti mers an d
the capab ili ti es of each .
Table 84. SATA MSI vs. PCI IRQ Actions
Interrupt Register Wire-Mode Action MSI Act ion
All bits are ‘0’. Wire Inactiv e No A ction
On e or more b its set to ‘1’. Wire Activ e S e nd Mess a g e
On e or more b its set to ‘1’, new bit gets set to ‘1’. Wire Active Send Messag e
One or more bits set to ‘1, software clears some
(but not all) bits. Wire Ac tive Send Message
On e or more b its set to ‘1’, softwa re cle ars all bits. Wire Inactiv e N o A ction
Software clears one or more bits, and one or more
bits is se t simultane ously. Wire Ac tive Send Message
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5.16.2 T imer Accuracy
1. The timers are accurate over any 1 ms period to within 0.005% of the time
specified in the timer resolution fields.
2. Within any 100 ms period, the t imer will report a time that is up to two ticks too
early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
3. The timer is monotonic. It will not return the same value on two consecutive reads
(unless the counter has rolled over and reached the same value).
The main counter will be clocked by the 14.31818 MHz clock, synchronized into the
66.666 MHz domain. This will result in a non-uniform duty cycle on the synchronized
clock, but does have the correct average period. The main counter will be as accurate
as the 14.3818 MHz clock.
5.16.3 Interrupt Mapping
Mapping Option #1: Legacy Opti on
In this case, the Legacy Rout bit (LEG_RT_CNF) will be set. This will force the mapping
found in Table 85. Se e Section 15.1.3, Offset 010-017h: General Config Register” for
LEG_RT_CNF details.
Mapping Option #2: Standar d Opti on
In this case, the Legacy Rout bit (LEG_RT_CNF) will be zero. Each timer has its own
routing control. The supported interrupt values are IRQ 20, 21, 22, and 23. See
Section 15.1.3, “Offset 010-017h: General Config Register” for LEG_RT_CNF details.
5.16.4 Periodic vs. Non-Periodic Modes
Non-Periodic Mode
When a timer is set up for non-periodic mode, it will generate a value in the main
counter which matches the value in the timer’s comparator register. When the timer is
set up fo r 32-bit mode , it will gene ra te anoth er inte rrup t when the main coun ter wr aps
around and matches this same value again. Timer 0 is configurable to 32 (default) or
64-bit mo de, whereas Timers 1 and 2 only support 32-bit mode.
Durin g run -ti me, th e v alue in the tim er’ s compar at or v alu e reg iste r will no t be chang ed
by the hardware. Software may change the value.
Warning:Software must be careful when prog ramming t h e co mp arator registers. When
the value written to the register is not sufficiently far in the future, the counter
Table 85. Legac y Routing
Time
r8259
Mapping APIC
Mapping Comment
0 IRQ0 IRQ2 In this case, the 8254 timer will not c ause a ny
interrupts.
1 IRQ8 IRQ8 In this case , the RTC will not cause any inte rrupts.
2As per IRQ
Routing Field As per IRQ
Routing Field
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may pass the value before it reaches the register and the interrupt will be
missed.
All three timers support non-periodic mode.
Periodic Mode
Timer 0 is the only timer that supports p eriodic mode. When Timer 0 is set up for
periodic mode, the software writes a value into the timer’s comparator value register.
When the main counter value matches the value in the timer’s comparator value
register, an interrupt may be generated. The hardware will then automatically increase
the value in the comparator value register by the last value written to that register.
To make the periodic mode work properly, the main counter is typically written with a
value of zero so that the first interrupt occurs at the right point for the comparator.
When the main counter is not set to zero, interrupts may not occur as expected.
During run-time, the value in the timer’s comparator value register may be read by
software to find out when the next periodic interrupt will be generated (not the rate at
which it ge nerates interrupts). Soft ware is expected to remember the last v alue written
to the comp arator’s value register (the rate at which interrupts are generated).
When software wants to change the periodic rate, it should write a new value to the
comparator value register. At the point when the timer’s comparator indicates a match,
this new value will be added to derive the next matching point.
When the software resets the main counter, the value in the comparators value
register needs to be reset as well. This may be done by setting the
TIMER0_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with
t he mai n co unt er ha lt ed. Se e Section 15, “Multimedia Timer Registers” for register and
bits deta ils .
The following usage model is expected:
1. Software clears the ENABLE_CNF bit to prevent any interrupts
2. Software Clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register
5. Software sets the ENABLE_CNF bit to enable interrupts.
Warning:As the timer p e ri o d a p p roaches z er o, the in te r rupts a ss o c ia ted wi th the
periodi c t imer may no t g et comp letely serviced befo r e the next timer match
occurs. In terrupts may get lost and/or sy stem perform ance may be degraded
in th is case.
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-
bit write in a 32-bit environment except when only the periodic rate is being changed
during run-time. When the actual Timer 0 Comparator Value needs to be reinitialized,
the following software solution will always work regardless of the environment:
1. Set TIMER0_VAL_SET_CNF bit
2. Set the lower 32 bits of the Timer0 Comparator Value register
3. Set TIMER0_VAL_SET_CNF bit
4. Set the upper 32 bits of the Timer0 Comparator Value register
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5.16.5 Enabling the Timers
The BIOS or O S PnP cod e sho uld rou te the i nterr upt s. Th is in cludes the Le gacy R out bi t,
Interrupt Rout bit (for each timer), interrupt type (to se lect the edge or level type for
each timer)
The Device Driver code should do the following for an available timer:
1. Set the Overall Enable bit (Offset 04h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable.
4. Set the comparator value.
5.16.6 Int errupt Levels
Interrupts directed to the internal 8259s are active high. See Section 5.7,Advanced
Interrupt Controller (APIC) (D29:F5)” for information regarding the polarity
progr am ming of the
I/O APIC for detecting internal interrupts. When the interrupts are mapped to the I/O
APIC and set for level-triggered mode, they may be shared with PCI interrupts,
although it is unlikely for the OS to attempt this. When more than one timer is
configured to share the same IRQ using the TIMERn_INT_ROUT_CNF fields, the
software must configure the timers to level-triggered mode. Edge-triggered interrupts
cannot be shared.
5.16.7 Handling Interrupts
When each timer has a unique interrupt and the timer has been configured for edge-
triggered mode, no specific steps are required. No read is required to process the
interrupt.
When a timer has been configured to level-triggered mode, its in terrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a 1 back to the bit position for the interrupt to be cleared.
Independent of the mode, software may read the v alue in the main counter to see how
much time has passed between when the interrupt was generated and when it was first
serviced.
When Ti mer 0 is set up to gene ra te a peri od ic interrupt, the softw a re may ch eck to see
how much time remains until the next interrupt by checking the timer value register.
5.16.8 Issues Related to 64-bit Timers with 32-bit
Processors
A 32-bit timer may be read directly using processors that are capable of 32-bit or 64-
bit instructions. However, a 32-bit processor may not be able to directly read 64-bit
timer. A race condition comes up when a 32-bit processor re ads the 64-bit register
using two separate 32-bit reads. The danger is that just after reading one half, the
other half rolls over and changes the first half.
When a 32-bit processor needs to access a 64-bit timer, it must first halt the timer
before reading both the upper and lower 32-bits of the timer.
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When a 32-bi t pr oces sor doe s not w an t to hal t the tim er, it may us e the 64-bit t ime r as
a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This will cause the timer to
behave as a 32-bit timer. The upper 32 bits will always be 0.
5.17 USB UHCI Controllers (D29:F0 and F1)
5.17.1 Overview
The Intel® 6300ESB ICH c onta i ns two U SB UHCI Hos t C ont rol lers . Ea ch Ho st Co ntrol le r
inc lud es a roo t h ub wi th two s e para te U SB ports e ach, for a to ta l of f our USB por ts. T he
Intel® 6300ESB ICH Host Controllers support the standard Univ ers al Ho st Con tro ll er
Interface (UHCI) Specification, Rev 1.1.
Overcurrent detection on all four USB ports is supported. The overcurrent inputs are
5V-tolerant and may be used as GPIs when not needed.
The Intel® 6300ESB ICH’s USB UHCI controllers are arbitrated differently from
standard PCI devices to improve arbitration latency.
The USB UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB High-speed signaling rates instead of USB I/O buffers.
5.17.2 Data Structures in Main Memory
This section describes the details of the data structures used to communicate control,
status, and data between software and the Intel® 6300ESB ICH: Frame Lists, Transfer
Descriptors, and Queue Heads. Fr ame Lists are aligned on 4-Kbyte boundaries. T r ansfer
Descriptors and Queue Heads are aligned on 16-byte boundaries.
5.17.2.1 Frame List Pointer
The frame list pointer contains a link pointer to the first data object to be processed in
the frame, as well as the control bits defined in Table 86.
Table 86. Frame List Pointer Bit Description
Bit Description
31:4 Frame List Pointer (FLP): This field contains the address of the first data object to be
processed in the frame and corresponds to memory address signals [31:4], respectively .
3:2 Reserved. T hese bits must be written as zero.
1
QH/TD Se lect (Q): Th is bit in di cates to the hard wa re whethe r the ite m re f ere nce d by
the link pointer is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the
Intel® 6300ESB ICH to p er fo rm the pr op e r type of processing on the item af te r it is
fetched.
1 = QH
0 = TD
0
Terminate (T): This bit indic ate s to the Inte l® 6300ESB ICH whether the schedule for
this frame ha s valid e ntrie s in it.
1 = Emp ty Fram e (pointer is invalid).
0 = Pointer is valid (po ints to a QH or TD ).
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5.17.2.2 Transfer Descriptors (TD)
Trans fer Descriptors (TDs) express the characteristics of the transaction requested on
USB by a client. TDs are always aligned on 16-byte boundaries, and the elements of
the TD are shown in Figure 18. The four different USB transfer types are supported by
a small number of control bits in the descriptor that the Intel® 6300E SB ICH inter prets
during operation. All Transfer Descriptors have the same basic, 32-byte structure.
During operation, the Intel® 6300ESB ICH hardware performs consistency checks on
some fields of the TD. When a consistency check fails, the Intel® 6300ESB ICH halts
immediately and issues an interrupt to the system. This interrupt cannot be mask ed
within the Intel® 6300ESB ICH.
Figure 18. Transfer Descriptor
Table 87. TD Link Pointer
Bit Description
31:4 Link Pointer (LP): Bits [31:4 ] Corre spond to memory ad dr es s signals [31:4],
res pec tively. This field points to an other TD or QH .
3 Reserved. Mus t be 0 when wri ti ng thi s field.
2
Dep th/Br eadt h Sel ect (V F): This bit is only v alid for que ued TDs and ind icates to the
hardware whether it should process in a d epth first or b readth first fashion. When set to
dep th first, it inf orms the Intel® 6300ES B ICH to pro cess the next transacti on in the
queue rather than starting a new queue.
0 = Bre a d th fi rst
1 = D e pth firs t
1
QH/TD Select (Q): This bit informs the Intel® 6300ESB ICH whe the r the item
refe re nce d by the lin k poi nte r is a noth e r T D or a QH. T his a llows the Intel® 63 00ES B
ICH to perform the proper typ e of processing on the item after it is fetched.
0 = T D
1 = QH
0
Terminate (T): This bit informs the Intel ® 6300ESB ICH that the link pointer in this T D
does not point to another val i d entry. When encounter ed in a queue context, this bit
indic ate s to the Inte l® 63 00ESB ICH that there are no more valid entries in the queue.
A TD en countered outside of a queue context with the T bit set info rms th e Intel ®
63 00ES B ICH tha t this is th e last TD in the frame .
0 = Link Pointer field is valid.
1 = Link Pointer field not valid.
Q V f 0
0 1 2 3 4 31
L i n k P o i n t e r
Max Len
B u f f e r P o i n t e r
T
7 8 15 16 23 24 10 11 14 18 19 20
R D
Status R A c t L e n
E n d P t D e v i c e A d d r e s s P I D
R I
O
C
I
O
O
S
L
S
C
_
E
R
R
S
P
D
25 26 27 28 29 30 21
R = R e s e r v e d
ICH Read/Write
ICH R ead Only
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Table 88. TD Control and Status (Sheet 1 of 3)
Bit Description
31:30 Reserved.
29
Short Pack et Dete ct (SPD): When a packet has this bit set to 1 and the packet is an
input p a cket, is in a que ue ; an d s ucce ssfully comp le te s with an actua l le ng th le ss tha n
the maximum length then the TD is marked inactive, the Queue Header is not updated
and the USBINT status bit (Status Register) is set at the e nd of the frame. In addition,
when the inte rru p t is enab le d , th e inte rru p t will b e se nt a t the end of th e frame .
Note that any error (e.g., babble or F IFO error) prevents the short packet fr om being
reported. The behavior is und efined when this bit is set with output packets or pac kets
outsid e of q ue ues .
0 = Disab le
1 = Enable
28:27
Error Counter (C_ERR): This fiel d is a 2-bit down c ounte r that keep s track of the
numbe r of Erro rs detected while executin g this TD. When thi s fi el d is pr ogr am med with
a non zero value during setup, the Intel® 6300ESB ICH decre ments t he count and
writes it bac k to the T D when the tra nsacti on fai ls. Wh e n the counter counts from one
to zero, the Intel® 6300ESB ICH mark s the TD inactive, sets the “STALLE D” and error
statu s bi t for th e error that caus ed th e transition to zero in the TD. An inte rru p t will b e
generated to H ost Controller Drive r (H CD ) whe n the decr em e nt to zero was caused by
Data Buff e r e rror, Bit stuf f error, or when enab le d , a CRC or Timeout error. Whe n H CD
programs this field to zero during setup, the Intel® 6300ESB ICH will not count errors
for this T D and th e re will b e no limit on the re trie s o f this TD.
Bits [28:27 ]In ter rupt After
00 No Error Limit
01 1 Erro r
10 2 Errors
11 3 Errors
Error Decrement Counter Error Decrement Counter
CRC Error Yes Data Buffer Error Yes
Time out E rror Yes Stalled No1
NAK Rec eived No Bit stuff Error Yes
Babble Detected No
Detec tion of Babble or Stall automatically de activat es the TD. Thus, count is not
decremented.
26
Low Speed De vice (LS): This bit indicates that the target device (USB data source or
sink) is a low speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/s).
There are s pecial res trictio ns on schedule pl acement for low speed TDs. When an Intel ®
6300ESB ICH root hub port is connected to a ful l speed dev ice and this bit is set to a 1
for a low spe e d transac tion, the Inte l® 6300ESB ICH send s out a low s peed preamble
on that port befo re sending the PID. No preamble is sent when a Intel® 6300ESB ICH
roo t hu b po rt is co nn e cte d to a low spe e d device.
0 = Full S pee d Device
1 = Low Speed D evice
25
Isoc hronous Select ( IOS): The fi eld specifies the type of the data structure. When
this bit is set to a 1, then the TD is an isochronous transfer. Isochronous TDs are always
mar ked ina ctiv e by the hard wa re after execution, regardless of the res ults of th e
transaction.
0 = N on -isochro n ou s Transfer Descriptor
1 = Isochronous Transfer Desc rip tor
24
Interru pt on Comple te (IOC): This specifies that the Intel® 6300ESB ICH should
issu e an int er ru p t on completi on of th e frame in wh ich th is Transf er Descriptor is
exec u ted. Even when the Act iv e bit in the TD is already cleared w hen the TD is fetch ed
(no transac tion will occur on USB), an IOC inte rrup t is g ene rated at the end of the
frame.
1 = I ssue IOC
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23
Active: For I ntel ® 6300ESB ICH schedule execution op erations, se e Section 5.17.3,
“Data Transfers to/from Main Memory”, Data Transfers to/f rom M a in Mem ory.
0 = Whe n the transaction associated with this de scr ip tor is co mp le te d , the Intel®
6300ESB ICH sets this bit to 0 indicating that the descriptor should not b e executed
when it is next encountered in the schedule. The Active bit is also set to 0 when a
stall handshake is received from the endpoint.
1 = Set to 1 by software to enable the e xecution of a message transaction by the Intel®
6300ES B ICH.
22
Stalled:
1 = Se t to a 1 by the Intel ® 6300ESB ICH during statu s updates to indica te that a
serious erro r h a s occurred a t t he de vice/end point addressed by th is TD. This may
be cau se d by bab b le , th e er ror counter counting down t o zero, or re ce ption of the
STALL handshake from the device d u ring the transa ctio n. Any time that a
transac tion re sults in the Stalled bit b ei ng set, th e Acti ve bit is also cleared (set to
0). When a STALL handshake is received from a SETUP transaction, a time-out
error will also be re ported.
21 Dat a B u ffe r Error (DBE):
1 = Se t to a 1 by the Intel ® 6300ESB ICH during status update to ind icate that the
Intel® 6300ESB ICH is unable to keep up with th e rec eptio n of inc oming data
(over run) or is una ble to supply data fast enough during transmission (underrun).
When this occurs, th e actua l le ng th an d Max Len g th f ie ld o f the TD will n ot match.
In the case of an underrun, the Intel® 6300ESB ICH will transmit an incorrect CRC
(thus invalid atin g th e data a t the endpoint) an d lea ve the TD ac tiv e (unless error
cou nt re a che d ze ro). W he n an overrun condition occurs , the Intel® 6300ESB ICH
will force a timeout condition on the USB, invalidating the transaction at the source.
20 Babble Detected (BABD):
1 = Se t to a 1 by the Intel ® 6300ESB ICH during status update when “bab b le” is
detected during the transaction generated by this descriptor. Babble i s unexpected
bus acti vity f or more than a preset amount of time. In addition t o setting this b it,
the Intel® 6300ESB ICH also sets the ”STAL LED ” bi t (bit 22) to a 1. Since “babble”
is considered a f atal error for that transfer, setting the ”STALLED” bit to a 1 insure s
that no m ore transactions occur as a result of this descriptor. Detection of babble
causes i mmediate term inat ion of t he current fram e. No fur ther TDs in t he frame are
executed. Execution resumes with the next frame list index.
19 Negative Acknowledgment (NAK) Received (NAKR):
1 = Se t to a 1 by the Intel ® 6300ESB ICH during status update whe n the Intel®
6300ESB ICH receives a “NAK” packet during the transaction generated by t his
descriptor. When a NAK handshake is received from a SETUP transaction, a time-
out error will also be reported.
18
CRC/time-out error (CRC_TOU T):
1 = Se t to a 1 by the Intel ® 6300ESB ICH as follows:
Durin g a sta tu s u pd at e in t he ca se t ha t n o re sponse is re ceived from th e ta rg et devic e/
end p oint within the time sp e cif ie d by th e protocol cha pter of the US B sp e cif ica tion.
Duri ng a s t at us u pdat e w hen a Cy c lic Redundanc y C hec k ( C R C) er r or is detect ed du r in g
the transac tion a ss ociate d with this transf er desc rip tor.
In the transmi t case (OUT or SETUP Command), this is in res po nse to the Inte l®
6300ES B ICH detecting a timeout from the ta rg e t device/e nd p oint.
In the receive case (IN Command), t h is is in response to the Intel® 6300ESB ICH s CRC
che cker cir cuitry detecting an error on the data rece iv e d from the devic e/ endpoint or a
NAK or S TAL L ha n d sh ake being re ce ived in re sponse to a SETUP transa ction.
17 Bit stuff Erro r (BSE):
1 = T his bit is set to a 1 by the Inte l® 6300ESB ICH during status update to indicate
that the receive data stream contained a sequence of more than 6 ones in a row.
Table 88. TD Control and Status (Sheet 2 of 3)
Bit Description
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
200 Order Number: 300641-004US
16
Bus Turn Arou nd Time-o ut (BTTO):
1 = This bit is set to a 1 by the Intel® 6300ESB ICH during status updates to indicate
that a bus t ime -o ut cond ition wa s d etected for this US B t ran sa ction. Th is time-out
is specially defined as not detecting an IDLE-to ‘K’ state Start of Packet (SOP)
tr ansition from 16 to 18 bit times after the SE0-to-IDE tr ansition of previous End of
Packet (EOP).
15:11 Reserved
10:0
Actual Length (ACTLEN): The Actua l Length fi eld is written b y the Intel® 6300ESB
ICH at the conc lusio n of a USB transa ctio n to indi cate the actual number of bytes tha t
were transf e rre d . It may be use d by the soft ware to maintain data integrity. The value
progr ammed i n this regi ster is encoded as n- 1 (see Maximu m L ength fi eld desc ription i n
the TD Token).
Table 89. TD Token
Bit Description
31:21
M a ximum Length (MA X LEN): The Maximum Length field specifies the maximum
number of dat a bytes allowed for the transfer. The Ma x imum Length value does not
incl u de p rot ocol byt es , su ch a s Packet ID (PI D) and CRC. The ma x imu m data pack e t is
1280 byte s. Th e 12 80 pac ket le ng th is the long e st pa cket theoretically ensured to fit
into a frame. Actual packet maximum lengths are set by HCD according to the type and
speed of the transfer. Note that the maximum length allowed by the USB specification
is 1023 byte s . Th e valid enc odings for t h is fiel d a re:
0x000 = 1 byt e
0x001 = 2 byt es
....
0x3FE = 1023 byte s
0x3FF = 1024 byte s
....
0x4FF = 1280 byte s
0x7FF = 0 bytes (null data packe t)
Note tha t value s from 500h to 7FEh are ille g a l a nd cau se a consistency ch e ck failure.
In the transmit case, the Intel® 6300ESB ICH uses this value as a terminal count for
the numbe r of bytes it fetc he s f rom host memory. In most cases, this is the number of
bytes it will actually transmit. In rare case s, the Intel® 6300ES B ICH may be unable to
access memory ( e.g., due to excessive latency) in time to av oid underrunning the
20 Reserved.
19
Data Toggle (D): This bit is us ed to synchronize data transfe rs be twe e n a USB
endpoint and the host. This bit determines which data PID i s sent or expected
(0=DATA0 and 1=DATA1). The Data Toggle bit provides a 1-bit sequence number to
check whether the previous pack et completed. This bit must always be 0 for
Isochronous TDs.
18:15 Endpoint (ENDPT): This 4-bit field extend s the ad dr essing interna l to a particular
device by providing 16 endpoints. This permits more flexible addressing of devices in
whic h more tha n on e sub-cha nnel is require d .
14:8 D evi ce Addr ess: This field id entifies the specific device servin g as the data sour ce or
sink.
7:0
Packet Identification (PID): This field contains the Packet ID to be used for this
transaction. Only the IN (69h), OUT (E1h), an d S ETUP (2Dh) tokens are allowed. Any
other value in this field causes a consistency che ck failure resu lting in an imm e diate
halt of the Intel® 6300ESB ICH. Bits [3:0] are com p le me nts of b its [7:4].
Table 88. TD Control and Status (Sheet 3 of 3)
Bit Description
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 201
5—Intel® 6300ESB ICH
5.17.2.3 Queue Head (QH)
Queue heads are special structures used to support the requirements of Control, Bulk,
and Interrupt transfers. Since these TDs are not automatically retired after each use,
their maintenance requirements may be reduced by putting them into a queue. Queue
Heads must be aligned on a 16-byte boundary, and the elements are shown in
Table 91.
Table 90. TD Buffer Pointer
Bit Description
31:0
Buff er Pointer (BUFF_PNT): Bits [31:0] cor re spond s to memory addr ess [31:0],
respectively. It points to the b e gi nning of the buffer tha t will be used dur ing th is
transaction. This buffer must be at least as long as the value in the Maximum Length
field described int t he TD token. The data buffer may be byte-aligned.
Table 91. Queue Head Block
Bytes Description Attributes
00-03 Queue Head Link Pointer RO
04-07 Queue Element Link Pointer R/W
Table 92. Queue Head Link Pointer
Bit Description
31:4 Queue Head Link Pointer (QHLP): This field contains the ad dr e ss of the next da ta
obj ect t o be pr o cess ed i n the ho r i zon ta l lis t an d cor re sponds to memo ry addr es s si gna l s
[31:4], re sp e ctiv e ly.
3:2 Reserved. T hese bits must be written as zeros.
1QH/TD Se lect (Q): This bit indicates to the hard ware whe the r the ite m ref er en ce d by
the link poi n te r is anoth e r TD or a QH.
0 = TD
1 = QH
0
Terminate (T): This bit indicates to the Intel® 6300ESB ICH that thi s is the last QH in
the schedule. When t here are active TDs in this queue, they are the last to be executed
in this frame.
0 = Pointer is valid (points to a QH or TD).
1 = Las t QH (po inte r is invalid ).
Table 93. Queue Element Link Pointer (Sheet 1 of 2)
Bit Description
31:4 Queue Element Link Pointer (QELP): This field contains the address of the next TD
or Q H t o be proc es sed i n this que u e an d cor r es pon ds t o m emor y a ddr ess s ig n als [31 :4 ],
respectively.
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
202 Order Number: 300641-004US
5.17.3 Data Transfers to/from Main Memory
The following sections describe the details on how HCD and the Intel® 6300ESB ICH
communicate through the schedule data structures. The discussion is organized in a
top-down manner, beginning with the basics of walking the Frame List, followed by a
description of generic processing steps common to all transfer descriptors, and finally a
discussion on Transfer Queuing.
5.17.3.1 Executing the Schedule
Software programs the Intel® 6300 ESB IC H wit h the st arting add ress o f the F ra me List
and the F r ame L ist i nde x, the n ca uses the In tel ® 6 300ES B I CH to e xe cu te the sche d ule
by setting the Run/Stop bit in the Control register to Run. The Intel® 6300ESB ICH
processes the schedule one entry at a time; the next element in the frame list is not
fetched until the current element in the frame list is retired.
Schedule execution proceeds in the following fashion:
1. The Intel® 6300ESB ICH fir st fetches an entry from the Frame List. This entry has
three fields. Bit 0 indicates whether the address pointer field is valid. Bit 1 indicates
whether the address points to a Transfer Descriptor or to a queue head. The third
field is the pointer itself.
2. When isochronous traffic is to be moved in a given frame, the Frame List entry
points to a Transfer Descriptor. When no isochronous data is to be moved in that
frame, the entry points to a queue head or the entry is marked invalid and no
transfers are initiated in that frame.
3. When the Frame List entry indicates that it points to a Transfer Descriptor, the
Intel® 6300ESB ICH fetches the entry and begins the operations necessary to
initiate a transaction on USB. Each TD contains a link field that points to the next
entry, as well as indicating whether it is a TD or a QH.
4. When the Frame List entry contains a pointer to a QH, the Intel® 6300ESB ICH
processes the information from the QH to determine the address of the next data
object that it should process.
5. The TD/QH process continues until the millisecond allotted to the current frame
expires. At this point, the Intel® 6300ESB ICH fetches the next entry from the
Frame List. When the Intel® 6300ESB ICH is not able to process all of the transfer
descriptors during a given frame, those descriptors are retired by software without
having been executed.
3:2 Reserved.
1
QH/TD Select (Q): This bit indicates to the hardware whether the item re ference d by
the link pointer is anothe r TD or a QH . For entr ies in a queue , this bit is typically set to
zero.
0 = TD
1 = QH
0
Terminate (T): T his bit indicates to the Intel® 63 00ESB I CH that there are no v alid TDs
in this queue. When HCD has new queue entries it overwrites this value with a new TD
pointer to the queue entry.
0 = Pointer is v alid.
1 = Term inate (No valid queue entries).
Table 93. Queue Element Link Pointer (Sheet 2 of 2)
Bit Description
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 203
5—Intel® 6300ESB ICH
5.17.3.2 Proce ssing Transfer Descriptors
The Intel® 6300ESB ICH executes a TD using the following generalized algorithm.
These basic steps are common across all modes of TDs. Subsequent sections present
processing steps unique to each TD mode.
1. The Intel® 6300ESB ICH fetches TD or QH from the current Link Pointer.
2. When a QH, go to 1 to fetch from the Queue Element Link Pointer. When inactive,
go to 12.
3. Build token, actual bits are in TD token.
4. When (Host-to-Function) then
[PCI Access] issue request for data, (referenced through TD.BufferPointer)
wait for first chunk data arrival
end if
5. [Begin USB Transaction] Issue token (from token built in 2, above) and begin data
transfer.
if (Host-to-Function) then Go to 6
else Go to 7
end if
6. Fetc h data f rom memor y (through TD B uf ferPointe r) a nd tr a nsfe r o v er U SB unt il T D
Max-Length bytes have been read and transferred. [Concurrent system memory
and USB Accesses]. Go to 8.
7. Wait for data to arrive (from USB). Write incoming bytes into memory beginning at
TD BufferPointer. Internal HC buffer should signal end of data packet. Number of
bytes received must be TD Max-Length; The length of the memory area referenced
by TD Buffer Point er.
8. Issue handshake based on status of data received (Ack or Time-out). Go to 10.
9. Wait for handshake, when required [End of USB Transaction].
10.Update Status [PCI Access] (TD.Status and TD.ActualLength).
When the TD was an isochronous T D, mark the TD inactive. Go to 12.
When not an isochronous TD, and TD completed successfully , mark the TD inactive.
Go to 11.
When not successful, and the error count has not been reached, leave the TD
active. When the error count has been reached, mark the TD inactive. Go to 12.
11.Write the link pointer from the current TD into the element pointer field of the QH
structure. When the Vf bit is set in the TD link pointer, go to 2.
12.Proceed to n ext entry.
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
204 Order Number: 300641-004US
5.17.3.3 Command Register, S ta tus Register, and TD Status Bit
Interaction
Note that when a NAK or STALL response is received from a SETUP transaction, a Time-
Out Error will be reported. This will cause the Error counter to decrement and the CRC/
Time-Out Error status bit to be set within the TD Control and Status DWORD during
write b ack. When the Error counter changes from 1 to 0, the Active bit will be reset to
0 and Stalled bit to 1 as normal.
5.17.3.4 Transfer Queuing
Transfer Queues are used to implement an ensured data delivery stream to a USB
Endpoint. Transfer Queues are composed of two parts: a Queue Header (QH) and a
linked list. The linked list of TDs and QHs has an indeterminate length (0 to n).
Table 94. Command Register, Status Register and TD Status Bit Interaction
Condition Intel® 6 300ESB ICH USB Status R egist e r
Actions TD Status Register
Actions
CR C/time-out error Set USB Error Int bit1, Clear HC Halte d bit Clear Active bit1 and set
Stall b it1.
Illegal PID, PID
Error,
Max Length
(illegal)
Clear Run/Stop bit in command register
Set HC Process Error and HC Halted bits
PCI Master/Target
Abort Clear Run/Stop bit in command register
Set Host System Error and HC Halted bits
Suspend Mode Clear Run/Stop bit in command register2
Set HC Halted b it
Resume Received
and
Suspen d Mode = 1 Set Resume received bit
Run/Sto p = 0 Clear Run/Stop bit in command register
Set HC Halted b it
Con f ig Flag Set Se t Con f ig Fla g in command re gis te r
HC Reset/Global
Reset
Clear Run/Stop and Config Flag in command
register
Cl e ar USB Int, US B Err or I nt, Res u me
received, Host Syst em Error, HC Proces s Error,
and HC Halted bits
IOC = 1 in TD
Status Set USB Int bit
Stall Se t USB Error Int bit Clear Active b it1 and set
Stall b it.
Bit Stuff/Dat a
Buffer Error Se t US B E rror Int bit1.Clear Active bit1 and set
Stall b it1.
Short P ac ket
Detect S e t US B Int bit Clear Act ive bit
NOTES:
1. Only when error counter counted do wn fr om 1 to 0.
2. Suspend mode may be entered only when Run/Stop bit is 0.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 205
5—Intel® 6300ESB ICH
The QH contains two link pointers and is organized as two contiguous DWORDs. The
first DWORD is a horizontal pointer (Queue Head Link Pointer), used to link a single
transfer queue with either another transfer queue, or a TD (target data structure
depends on Q bit). When the T bit is set, this QH represents the la st data structure in
the current Frame. The T bit informs the Intel® 6300ESB ICH that no further
processing is required until the beginning of the next frame. The second DWORD is a
vertical pointer (Queue Element Link Pointer) to the first data structure (TD or QH)
being managed by this QH. When the T bit is set, the queue is empty. This pointer may
reference a TD or another QH.
Figure 19 illustrates four example queue conditions. The first QH (on far left) is an
example of an “empty” queue; the termination bit (T Bit), in the vertical link pointer
field, is set to 1. The horizontal link pointer references another QH. The next queue is
the expected typical configuration. The horizontal link pointer references another QH,
and the vertical link pointer references a valid TD.
Typically, the vertical pointer in a QH points to a TD. However, as shown in Figure 19
(third example from left side of figure) the vertical pointer cou ld point to another QH.
When this occurs, a new Q Context is entered and the Q Context just exited is NULL
(The Intel® 6300ESB ICH will not update the vertical pointer field).
The far right QH is an example of a frame ‘termination’ node. Since its horizontal link
poi nter has its termination bit set, the Intel® 6300ESB ICH assumes there is no more
work to complete for the current Frame.
Transfer Queues are based on the following characteristics:
A QH’s vertical link poin ter (Queue Element Link Pointer) references the ‘Top’ qu eue
member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the
“next” work element in the Frame.
Each queue member’s link pointer references the next element within the queue.
In the simplest model, the Intel® 6300ESB ICH follows vertical link point to a queue
element, then executes the element. When the completion status of the TD satisfies
the advance criteria as shown in Table 95, the I ntel® 6300ESB ICH advances the queue
Figure 19. Example Queue Conditions
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Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
206 Order Number: 300641-004US
by writing the just-executed TD’s link pointer back into the QH’s Queue Element link
point er. The next time the queue head is traversed, the next queue element will be the
Top element.
The traversal has two options: Breadth first, or Depth first. A flag bit in each TD (Vf -
Ver t ical Tra ve rsa l F lag ) cont r ol s wh ether trav er sa l is Brea dt h or De pt h firs t. T he def au lt
mode of traversal is Breadth-First. For Breadth-First, the Intel® 6300ESB ICH only
executes the top element from each queue. The execution path is shown below:
1. QH (Queue Element Link Pointer)
2. TD
3. Write-Back to QH (Queue Element Link Pointer)
4. QH (Queue Head Link pointer).
Breadth-First is also performed for every transaction execution that fails the advance
criteria. This means that when a queued TD fails, the queue does not advance and the
Intel® 6300ESB ICH traverses the QH’s Queue Head Link Pointer.
I n a Depth-first traversal, the top queue element must c omplete successfully to satisfy
the advance criteria for the queu e. When the Intel® 6300ESB ICH is current ly
processing a queue, and the advance criteria are met, and the Vf bit is set, the Intel®
6300ESB ICH follows the TD’s link pointer to the next schedule work item.
Note that regardless of traversal model, when the advance criteria are met, the
successful TD’s link pointer is written back to the QH’s Queue Element link pointer.
When the Intel® 6300ESB ICH encounters a QH, it caches the QH internally, and sets
internal state to indicate it is in a Q-context. It needs this state to update the correct
QH (for auto advancement) and also to make the correct decisions on how to traverse
th e Frame Li st .
R est r icti ng the a dva nc emen t of q ueu es t o ad van cem ent cri ter ia i mpl emen ts a n en sure d
data delivery stream.
A queue is never advanced on an error completion status (even in the event the error
count was exhausted).
Table 95 lists the general queue advance criteria, which are based on the execution
status of the TD at the “Top” of a currently “active” queue.
Table 96 is a decision table illustrating the valid combinations of link pointer bits and
the valid actions taken when advancement criteria for a queued transfer descriptor are
met. The column headings for the link pointer fields are encoded, based on the
following list:
Table 95. Queue Advance Criteria
Function-to-Host (IN) Host-to-Function (OUT)
Non-NULL NULL Error/NAK Non-NULL NULL Error/NAK
A dvanc e Q Ad vanc e Q Retr y Q El em ent Ad vance Q Ad v ance Q Re try Q Eleme nt
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 207
5—Intel® 6300ESB ICH
Legend:
QH.LP = Queue Head Link Pointer (or Horizontal Link Poi nter) QE.Q = Q bit i n QE
QE.LP = Queue Element Li nk Pointer (or Vertical Link Pointer) Q E.T = T bit in QE
TD.LP = TD Link Pointer TD. Vf = Vf bit in TD
QH.Q = Q bit in QH TD.Q = Q bit in TD
QH.T = T bit i n QH TD. T = T bit in TD
QT
QHLP
QH
QT
QELP
QE Vf
TDLP
TD
Vf Q T
Table 96. USB Schedul e List Traversal Decision Table
Q
Contex
tQH.Q QH.T QE.Q QE.T TD.Vf TD.Q TD.T Description
0 ----x00
Not in Queue - execute TD.
Use TD.LP to get next TD
0 - - - - x x 1 Not in Queue - execute TD. End of Frame
0 ----x10
Not in Queue - execute TD.
Use TD.LP to get next (QH+QE).
Set Q Conte x t to 1.
1 00000xx
In Queue. Use QE .LP to get TD.
Execute TD. Update QE.LP with TD .LP.
Use QH.LP to get next TD.
1 xx00100
In Queue. Use QE .LP to get TD.
Execute TD. Update QE.LP with TD .LP.
Use TD.LP to get next TD.
1 xx00110
In Queue. Use QE .LP to get TD.
Execute TD. Update QE.LP with TD .LP.
Use TD.LP to get next (QH+QE).
100x1xxx
In Queue. Empty queue.
Use QH.LP to get next TD
1 x x 1 0 - - - In Queue. Use QE.LP to get (QH+QE)
1 x1000xx
In Queue. Use QE .LP to get TD.
Execute TD. Update QE.LP with TD .LP.
End of Frame
1 x 1 x 1 x x x In Queue. Empty queue. End of Frame
1 10000xx
In Queue. Use QE .LP to get TD.
Execute TD. Update QE.LP with TD .LP.
Use QH.LP to get next (QH+QE).
110x1xxx
In Queue. Empty queue.
Use QH.LP to get next (QH+QE)
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5.17.4 Data Encoding and Bit Stuffing
The USB employs NRZI data encoding (Non-R eturn t o Z ero Inverted) when tr ansmitting
packets. In NRZI encoding, a 1 is represented by no change in level and a 0 is
represented by a change in level. A string of zeros causes the NRZI data to toggle each
bi t time. A stri ng of on es c au ses long pe rio ds w i th no tr ansi ti ons i n the d a ta. In o rde r t o
ensure adequate signal transitions, bit stuffing is employed by the transmitting device
when sending a packet on the USB. A zero is inserted after every six consecutive ones
in the data stream before the data is NRZI encoded to force a transition in the NRZI
da ta stre am. This gives the r ec ei ver logi c a data tr ansiti on at l ea st once every seve n bi t
times to ensure the data and clock lock. A waveform of the data encoding is shown in
Figure 20.
Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire
t ra nsmi ssi on. The d ata “ one” tha t end s th e Sy nc P at te rn i s co unt ed as the f irs t on e in a
sequence. Bit stuffing is always enforced, without exception. When required by the bit
stuffing rules, a zero bit will be inserted even when it is the last bit before the end-of-
packet (EOP) signal.
5.17.5 Bus Protocol
5.17.5.1 Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,
through to the most significant bit (MSb) last.
5.17.5.2 SYNC Field
All packets begin with a synchronization (SYNC) field, which is a coded sequence that
generates a maximum edge transition density. The SYNC field appears on the bus as
IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the
input circuitry to align incoming data with the local clock and is defined to be eight bits
in length. SYNC serves only as a synchronization mechanism and is not shown in the
following packet diagrams. The last two bits in the SYNC field are a mark er that is used
to identify the first bit of the PID. All subsequent bits in the packet must be indexed
from this point.
5.17.5.3 Packet Field Formats
F i el d f or m ats f o r t h e t ok e n, dat a , a n d ha nd s ha k e p acket s a r e de sc r i be d i n t h e f o llow in g
section. The effects of NRZI coding and bit stuffing have been removed for the sake of
clarity. All packets have distinct start and end of packet delimiters.
Figure 20. USB Data Encoding
CLOCK
Data
Bit Stuffed Data
NRZI Da t a
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Table 97. PID Format
Bit Data Sent Bit Data Sent
0PID 0 4NOT(PID 0)
1PID 1 5NOT(PID 1)
2PID 2 6NOT(PID 2)
3PID 3 7NOT(PID 3)
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Pa cket Identifier Field
A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID
consists of a four bit packet type field followed by a four-bit check field as shown in
Table 97. The PID indicates the type of packet and, by inference, the format of the
packet and the type of error detection applied to the packet. The four-bit check field of
the PID insures reliable decoding of the PID so that the remainder of the packet is
interpreted correctly. The PID check field is generated by performing a ones
comp lem en t of the pac ket type fiel d.
Any PID received with a failed check field or which decodes to a non-defined value is
assumed to be corrupted and the remainder of the packet is assumed to be corrupted
and is ignored by the receiver. PID types, codes, and descriptions are listed in Table 98.
PIDs are divided into four coding groups: token, data, handshake, and special, with the
first two transmitted PID bits (PID[1:0]) indicating which group. This accounts for the
distribution of PID codes.
5.17.5.4 Address Fields
Function endpoints are addressed using two fields: the function address field and
endpoint field.
Address Fie ld
Table 98. PID Types
PID Type PID
Name PID[3:0] Description
Token
OUT b0001 A d d ress + end po int numbe r in hos t -> function
transaction
IN b1001 Ad d ress + end point numbe r in f unctio n -> host
transaction
SOF b0101 Start of frame marker and frame number
SETUP b1101 Address + end point numb er in host -> function
transaction f or se tup to a control endpo int
Data DATA0 b 0011 D ata p acket PID even
DATA1 b 1011 Data p a cket PID od d
Handshake
ACK b0010 Receiver accepts error f re e data pack et
NAK b1010 Rx device cannot accept data or Tx device cannot send
data
STALL b 1110 Endp oint is stalle d
Special PRE b1100 Host -is sued pr eamble. Enab les dow nstr eam bus tr affic to
low speed devices.
Table 99. Address Field
Bit Data Sent Bit Data Sent
0ADDR 0 4 ADDR 4
1ADDR 1 5 ADDR 5
2ADDR 2 6 ADDR 6
3ADDR 3
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The function address (ADDR) field specifies the function, through its address, that is
either the source or destination of a data packet, depending on the value of the token
PID. As shown in Table 99, a total of 128 addresses are specified as ADDR[6:0]. The
ADDR field is specified for IN, SETUP, and OUT tokens.
Endpoint Field
An additional four-bit endpoint (ENDP) field, shown in Table 100, permits more flexible
addressing of functions in which more than one sub-channel is required. Endpoint
numbers are function specific. The endpoint field is defined for IN, SETUP, and OUT
token PIDs only.
5.17.5.5 Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per fr ame
basis. The frame nu mber field rolls o ver upon reaching its maximum value of x7FF, and
is sent only for SOF tokens at the start of each frame.
5.17.5.6 Data Field
The data field may range from zero to 1023 bytes and must be an integral numbers of
bytes. Data bits within each byte are shifted out LSB first.
5.17.5.7 Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context,
these fields are considered to be protected fields. The PID is not included in the CRC
che ck of a pa ck et c onta i ni ng CRC. Al l CRCs are gene r at ed over thei r re sp ecti ve fi el ds i n
the transmitter before bit stuffing is performed. Similarly, CRCs are decoded in the
receiver after stuffed bits have been removed. Token and data packet CRCs provide
100% coverage for all single and double bit errors. A failed CRC is considered to
indicate that one or more of the protected fields is corrupted and causes the receiver to
ignore those fields, and, in most cases, the entire packet.
5.17.6 Packet Formats
5.17.6.1 Token Packets
Table 101 shows the field formats for a token packet. A token consists of a PID,
specifying either IN, OUT, or SETUP packet type, and ADDR and ENDP fields. For OUT
and SETUP transactions, the address and endpoint fields uniquely identify the endpoint
that will receive the subsequent data packet. For IN transactions, these fields uniquely
identify which endpoint should transmit a data packet. Only the Intel® 6300ESB ICH
may issue token pac kets. IN PIDs define a data transaction from a function to the
Intel® 6300ESB ICH. OUT and SETUP PIDs define data transactions from the Intel®
6300ESB ICH to a function.
Table 100. Endpoint Field
Bit Data Sent
0ENDP 0
1ENDP 1
2ENDP 2
3ENDP 3
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Token packets have a five-bit CRC which covers the address and endpoint fields as
shown above. Th e CRC does not cover the PID, which has its own check field. Token
and SOF pack ets are delimited by an EOP after three bytes of pack et field data. When a
packet decodes as an otherwise valid token or SOF but does not terminate with an EOP
after three bytes, it must be considered invalid and ignored by the receiver.
5.17.6.2 Start of Frame Packets
Table 102 shows a start of fr ame (SOF) packet. SOF packets are issued by the host at a
nominal rate of once every 1.00 ms +/- 0.05. SOF packets consist of a PID indicating
packet type followed by an 11-bit frame number field.
The SOF token comprises the token-only transaction that distributes a start of frame
marker and accompanying frame number at precisely timed intervals corresponding to
the start of each frame. All full speed functions, including hubs, must receive and
decode the SOF packet. The SOF token does not cause any receiving function to
generate a return packet; therefore, SOF delivery to any given function cannot be
ensured. The SOF packet delivers two pieces of timing information. A function is
informed that a start of frame has occurred when it detects the SOF PID. Frame timing
sensitive functions, which do not need to keep track of frame number, need only
decode the SOF PID; they may ignore the frame number and its CRC. When a function
needs to track frame nu mber, it must comprehend both the PID and the time stamp.
5.17.6.3 Data P ackets
A data packet consists of a PID, a data field, and a CRC as shown in Table 103. There
are two types of data packet s, identified by differing PIDs: DAT A0 and DA TA1. Two data
packet PIDs are defined to support data toggle synchronization.
Data must always be sent in integral numbers of bytes. The data CRC is computed over
only the data field in the packet and does not include the PID, which has its own check
field.
Table 101. Token Format
Packet Width
PID 8 bits
ADDR 7 bits
ENDP 4 bit s
CR C5 5 bit s
Table 102. SOF Packet
Packet Width
PID 8 bits
Frame Number 11 bits
CRC5 5 bits
Table 103. Data Packet Format
Packet Width
PID 8 bits
DATA 0-102 3
bytes
CR C16 16 bits
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5.17.6.4 Handshake Packets
Handshake packets consist of only a PID. Handshake packets are used to report the
status of a data transaction and may return values indicating successful reception of
data, flow control, and stall conditions. Only tr ansaction types that support flow control
may return handshakes. Handshakes are always returned in the handshake phase of a
transaction and may be returned, instead of data, in the data phase. Handshake
packets are delimited by an EOP after one byte of packet field. When a packet is
decoded as an otherwise valid handshake but does not terminate with an EOP after one
byte, it must be considered invalid and ignored by the receiver.
There are three types of handshake packets:
ACK indicates that the data packet was received without bit stuff or CRC errors
over the dat a field and that the data PID was receiv ed correctly. An ACK handshake
is applicable only in transactions in which data has been transmitted and where a
handshake is expected. ACK may be returned by the host for IN transactions and
by a function for OUT transactions.
NAK indicates that a function was unable to accept data from the host (OUT) or
that a func ti on has no data to tra nsmit to the host (IN). NAK ma y onl y be returne d
by functions in the data phase of IN transactions or the handshake phase of OUT
transactions. The host may not issue a NAK. NAK is used for flow control purposes
to in dic ate t hat a fu nct ion i s t empor ari l y una ble to tr ans mit o r rece iv e data, b ut wi ll
eventually be able to do so without need of host intervention. NAK is also used by
interrupt endpoints to indicate that no interrupt is pending.
STALL is retur ned by a functi on in respons e to an IN tok en or aft er the data phas e
of an OUT. ST ALL in dicates th at a fun ction is unabl e to trans mit or receiv e data, a nd
that the condition requires host intervention to remove the stall. Once a function’s
endpoint is stalled, the function must continue returning STALL until the condition
causing the stall has been cleared through host intervention. The host is not
permitted to return a STALL under any condition.
5.17.6.5 Handshake Responses
IN Transaction
A function may respond to an IN transaction with a STALL or NAK. When the token
received was corrupted, the function will issue no response. When the function may
transmit data, it will issue the data packet. The Intel® 6300ESB ICH, as the USB host,
may return only one type of handshake on an IN transaction, an ACK. When it receives
a corrupted data, or cannot accept data due to a condition such as an internal buffer
overrun, it discards the data and issues no response.
OUT Transactio n
A function may respond to an OUT transaction with a STALL, ACK, or NAK. When the
transaction contained corrupted data, it will issue no response.
SE TU P Transa c ti on
Setu p def ines a sp ecial typ e of hos t to funct io n data tr ansa ction whi ch p ermi ts the hos t
to initialize an endpoint’s synchronization bits to those of the host. Upo n receiving a
Setup transaction, a function must accept the data. Setup transactions cannot be
STALLed or NAKed and the receiving function must accept the Setup transfer’s data.
When a non-control endpoint receives a SETUP PID, it must ignore the transaction and
return no re sponse.
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5.17.7 USB Interrupts
5.17.7.1 Overview
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from an Intel® 6300ESB ICH
operation error. All transaction-based sources may be masked by software through the
Intel® 6300ESB ICHs Interrupt Enable register. Additionally, individual transfer
descriptors may be marked to generate an interrupt on completion.
When the Intel® 6300ESB ICH drives an interrupt for USB, it internally drives the
PIRQ[A]# pin for USB function #0, PIRQ[D]# pin for USB function #1 until all sources
of the interrupt are cleared. In order to accommodate some operating systems, the
Interrupt Pin register must contain a different value for each function of this new multi-
function device.
5.17.7.2 Transaction Based Interrupts
Th ese inte rrup ts ar e not si gnal ed unt il a fter the st atus f or the l as t comp le te transacti on
in the frame has been written back to host memory. This ensures that software may
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error/Time-O ut
A CRC/Time-Out error occurs when a packet transmitted from the Intel® 6300ESB ICH
to a USB device or a packet transmitted from a USB device to the Intel® 6300ESB I CH
generates a CRC error. The Intel® 63 00ESB ICH is informed of this event by a time-out
from the USB device or by the Intel® 6300ESB ICH’s CRC checker gene rating an error
on reception of the packet. Additionally, a USB bus time-out occurs when USB devices
do not respond to a transaction phase within 19-bit times of an EOP. Either of these
conditions will cause the C_ERR field of the TD to decrement.
When the C_ERR field decrements to zero, the following occurs:
The Active bit in the TD is cleared
The Stalled bit in the TD is set
The CRC/Time-out bit in the TD is set.
At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
When the CRC/Time out interrupt is enabled in the Interrupt Enable register, a
hardware interrupt will be signaled to the system.
Interrupt on Comple tio n
Transfer Descriptors contain a bit that may b e set to cause an interrupt on their
completion. The completion of the transaction associated with that block causes the
USB Interrupt bit in the HC Status Register to be set at the end of the frame in which
the tr an sfer co mpl eted. Wh en a TD i s enc ounte red with th e I OC bit s et to 1, t he IO C bit
in the HC Status register is set to 1 at the end of the frame when the active bit in the
TD is set to 0 (even when it was set to zero when initially read).
When the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a
hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status
register is set either when the TD completes successfully or because of errors. When
the completion is because of errors, the USB Error bit in the HC status register is also
set.
Short Packet Detect
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A transfer set is a collection of data which requires more than one USB transaction to
completely move the data across the USB interface. An example might be a large print
file which requires numerous TDs in multiple frames to completely transfer the data.
Reception of a data packet that is less than the endpoint’s Max Packet size during
Control, Bulk or Interrupt transfers signals the completion of the transfer set, even
when there are active TDs remaining for this transfer set. Setting the SPD bit in a TD
indicates to the HC to set the USB Interrupt bit in the HC status register at the end of
the frame in which this ev ent occurs. This feature streamlines the processing of input
on these transfer types. When the Short Packet Interrupt Enable bit in the Interr upt
Enable register is set, a hardware interrupt is signaled to the system at the end of the
frame where th e event occurred.
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it
is said to be babbling. Since isochrony may be destroyed by a babbling device, this
error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble
bits being set to one. The C_ERR field is not decremented for a babble. The USB Error
Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware
interrupt is signa led to the system.
When an EOF babble was caused by the Intel® 630 0ESB ICH (due to inco rrect schedul e
for instance), t he Intel® 6300ESB ICH will force a bit stuff error followed by an EOP and
the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a
transaction or that the transaction ended in an error condition. The TDs Stalled bit is
set and the Active bit is cleared. Reception of a STALL does not decrement the error
counter. A hardware interrupt is signaled to the system.
Data Buffer Error
Thi s event indicates that an overrun of incoming data or a under-run of outgoing data
has occurred for this transaction. This would generally be caused by the Intel®
6300ESB ICH not being able to access required data buffers in memory within
necessary latency requirements. Either of these conditions will cause the C_ERR field of
the TD to be decremented.
When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is
set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the
frame and a hardware interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that 6 ones in a row
within the incoming data stream. This will cause the C_ERR field of the TD to be
decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared
to 0, th e Stal led bi t is s et to on e, th e U SB Err or Int erru pt bit in the HC Sta tus reg iste r i s
set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
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5.17.7.3 Non-Transaction Based Interrup ts
When an Intel® 6300ESB ICH process error or system error occurs, the Intel®
6300ESB ICH halts and immediately issues a hardware interrupt to the system.
Resume Re ceive d
This event indicates that the Intel® 6300ESB ICH received a RESUME signal from a
device on the USB bus during a global suspend. When this interrupt is enabled in the
Interrupt Enable register, a hardware interrupt will be signaled to the system allowing
the USB to be brought out of the suspend state and returned to normal operation.
Intel® 6300ESB ICH Process Error
The HC monitors certain critical fields during operation to ensure that it does not
process corrupted data structures. These include checking for a valid PID and verifying
that the MaxLength field is less than 1280. When it detects a condition that would
indicate that it is processing corrupted data structures, it immediately halts pro cessing,
sets the HC Proc ess Error bit in the HC Sta tus register an d signals a hardware interrupt
to the system.
This interrupt cannot be disabled through the Interrupt Enable register.
Host S ystem Error
The Intel® 63 00ES B ICH sets thi s bit to 1 wh en a PCI Pa rity erro r, PCI Master Abort, or
PCI Target Abort occur. When this error occurs, the Intel® 6300 ESB ICH clear s the Ru n/
Stop bit in the Command register to prevent further execution of the scheduled TDs.
This interrupt cannot be disabled through the Interrupt Enable register.
5.17.8 USB Power Management
The H ost Con tr ol l er m a y be p ut i nt o a su sp en ded st at e and it s po we r ma y be r emoved.
This requires that certain bits of information are ret ained in the resume power plane o f
the Intel® 6300ESB ICH so that a device on a port may wake the system. Such a
dev ice ma y be a f ax - mo dem , wh ic h wi l l w ak e up the machi n e to re ce iv e a fax or take a
voice message. The settings of the following bits in I/O space will be maintained when
the Intel® 6300ESB ICH enters the S3, S4 or S5 states:
When the Intel® 6300 ESB IC H de te cts a re sume e ve nt on an y o f it s po rts, it wi ll set t he
corresponding USB_STS bit in ACPI space. When USB is enabled as a wake/break
event, the system will wake up and an SCI will be generated.
Ta ble 104. Bits Maintained in Low Power States
Register Offset Bit Description
Command 00h 3 Enter Global Suspend Mode (EGSM)
Status 02h 2 Resume Detect
Port Status and
Control 10h and 12h
2 Port Enabled/Disabled
6Resume Detect
8 Low Speed Device Attached
12 Suspend
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5.17.9 USB Legacy Keyboard Ope r ation
Typically when a USB keyboard is plugged into the system, and a standard keyboard is
not, the system may not boot, and DOS legacy software will not run, because the
keyboard will not be identified. In an I ntel® 6300ESB ICH sys tem P ort 60/64 emul at ion
will allow the USB keyboard and DOS legacy software to run. Port 60/64 emulation
registers may be enabled by BIOS typically in a pre-OS environment and may be
disabled during run time.
The Intel® 6300ESB ICH implements a series of trapping operations that will snoop
accesses that typically go to the keyboard controller and put the expected data from
the U SB keyboard into ports 60/64.
The following table summarizes the implementation of the bits in the USB Legacy
Keyboard/Mouse Control Registers.
Table 105. USB Legacy Keyboard/Mous e Control Register Bit Implementa tion
(Sheet 1 of 2)
Bit
#Bit Name Summary Details
15 SMI Caused by
End of Pass-
Through
Logically 1 bit
for all
controllers
Note this bit in a ll host c ontrollers will be set at the same time a nd
cleared at the same time. It is cleared whenever software writes a
one to this bit in any of the three host controllers. This bit may either
be implemente d s epara te ly for each co ntroller or shared and alia se d .
13 PCI Interrup t
Enable Independent
enable Each bit provides individual host c ontrol.
12 SMI Caused by
USB I nte rru p t Independent
status Individual status bits for each controller.
11 SMI Caused by
Port 64 Write
Logically 1 bit
for all
controllers
Note this bit in a ll host c ontrollers will be set at the same time a nd
cleared at the same time. It is cleared whenever software writes a
one to this bit in any of the three host controllers. This bit may either
be implemente d s epara te ly for each co ntroller or shared and alia se d .
10 SMI Caused by
Port 64 Read
Logically 1 bit
for all
controllers
Note this bit in a ll host c ontrollers will be set at the same time a nd
cleared at the same time. It is cleared whenever software writes a
one to this bit in any of the three host controllers. This bit may either
be implemente d s epara te ly for each co ntroller or shared and alia se d .
9SMI Caused by
Port 60 Write
Logically 1 bit
for all
controllers
Note this bit in a ll host c ontrollers will be set at the same time a nd
cleared at the same time. It is cleared whenever software writes a
one to this bit in any of the three host controllers. This bit may either
be implemente d s epara te ly for each co ntroller or shared and alia se d .
8SMI Caused by
Port 60 Read
Logically 1 bit
for all
controllers
Note this bit in a ll host c ontrollers will be set at the same time a nd
cleared at the same time. It is cleared whenever software writes a
one to this bit in any of the three host controllers. This bit may either
be implemente d s epara te ly for each co ntroller or shared and alia se d .
7SMI at End of
Pass- Through
Enable
Separate
enables ORed
together
This bit enables the generation of the SMI b ased on bit 15 within the
same function. When bit 15 is implemented as a shared/aliased bit
acro ss a ll f un ctions, the b it 7 ’s from all three con trollers are ORed
together a nd used to enab le the SMI ba sed on bit 15.
6Pass Through
State
Logically 1 bit
for all
controllers
This bit in all host cont rolle rs refle cts the state of th e Pass-T h roug h
state machine. Software may force this bit to zero by clearing the
A20Gate Pass-Through Enable (bit 5) in all of the host controllers.
5A20Gate Pass-
Through Enable
ORed together
to enab le the
pass-through
state ma chine
When any of these bits in the three host controllers is set, the Intel®
6300ES B ICH will enable the Legacy Keyboard A20Gate Pass-through
sequence. This prevents the SMI status bits (11:8) from asserting in
all three controllers when the specific sequence of I/O cycles is
observed.
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Note: The scheme described below assume s that the keyboard controller (8042 or
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space.
Figure 21 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R,
64 W) is a vai la bl e i n the Status R egiste r. Since the en able is after the l atc h, it is possi ble
to check for other events that didn't necessarily cause an SMI. It is the software's
responsibility to logically AND the value with the appropriate enable bits.
Note als o that t he SMI is gener ated before the PCI cy cle compl etes (e .g. , befor e TRD Y#
goes active) to ensure that the processor doesn't complete the cycle before the SMI is
observed. This method is used on MPIIX and has been validated.
The logic will also need to block the accesses to the 8042. When there is an external
8042, then this is simply accomplished by not activating the 8042 CS. This is simply
don e by log ica lly ANDi ng the four enable s (60 R, 60W, 64R, 64W) with th e four ty pe s of
accesses to determine when 8042CS should go active. An additional term is required
for the “Pass-through” case.
The state table for the diagram is shown in Table 106.
4SMI on USB IRQIndepend ent
Enable Each bit provides individual host control.
3SMI on Port 64
Writes Enable
Separat e
enables ORed
together
Each bi t enables S MI generation when the corre sp ond ing b it 11 is
se t. W hen bit 11 is imp le me nte d as a share d /a lia sed bit acros s all
func tions, th en the bit 3’s from all three controllers are ORed
together and used to enab le the SMI bas ed on bit 11.
2SMI on Port 64
Reads Enable
Separat e
enables OR’ed
together
Each bit enable s S MI g eneration if the correspond ing bit 10 is set. If
bit 10 is implemented as a shared/aliased bit across all functions,
then the bit 2's from all t hree contro llers are OR'ed togethe r and
used to enable the SMI based on bit 10.
1SMI on Port 60
Writes Enable
Separat e
enables OR’ed
together
Each bit enable s S MI g eneration if the correspond ing bit 9 is set. If
bit 9 is im plemented as a shared/aliased bit across all functions, then
th e bit 1's from all th re e controllers are OR'ed tog et he r an d used to
enable the SMI based on bit 9.
0SMI on Port 60
Reads Enable
Separat e
enables OR’ed
together
Each bit enable s S MI g eneration if the correspond ing bit 8 is set. If
bit 8 is im plemented as a shared/aliased bit across all functions, then
th e bit 0's from all th re e controllers are OR'ed tog et he r an d used to
enable the SMI based on bit 8.
NOTE: If bit 7 of the Extended Test Mode Register 1 (D31:F0, offset F4h ETR1, section 9.1.36) is set. Port 60/64h
Reads an d Writes fro m an e xternal PCI agent wil l n ot affe ct set bits 8-11 and will not ca use an SMI
indep e nd en t of the setting of bits 0-3
Table 105. USB Legacy Keyboard/Mouse Control Register Bit Implementation
(Sheet 2 of 2)
Bit
#Bit Name Summary Details
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Figure 21. USB Legacy Keyboard Flow Diagram
KBC Accesses
PCI Config
Re ad, Write
60 READ
Clear SMI_60_R
EN_SMI_ON_60R
Comb
.
Decoder
AND
Same for 60W, 64R, 64W
SMI
OR
T o Individual
"C aus e d B y"
"Bits"
To PIRQD#
T o "C aus ed B y" Bit
AND
AND
EN_PIRQD#
USB_IRQ
Clear USB_IRQ
EN_SMI_ON_IRQ
S
D
R
S
D
R
NOT (No r th PCI g nt)
North PCI cycle
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Table 106. USB Legacy Keyboard State Transitions
Current
State Action Data
Value Next
State Comment
IDLE 64h / Write D1h GateState
1
Standard D1 command. Cycle passed throug h to 8042.
SMI# doesn't go active. PS TAT E (offset C0, bit 6) goes
to 1.
IDLE 64h / Write Not D 1h IDLE Bi t 3 in Config Register determine s if cycle p a sse d
through to 8042 and if SMI# generated.
IDLE 6 4h / Read N/A IDLE Bi t 2 in Config Register determine s if cycle p a sse d
through to 8042 and if SMI# generated.
IDLE 60h / Write D on't Care IDL E B it 1 in Con f ig Regi ste r d etermines if cycle p asse d
through to 8042 and if SMI# generated.
IDLE 6 0h / Read N/A IDLE Bi t 0 in Config Register determine s if cycle p a sse d
through to 8042 and if SMI# generated.
GateS tate 1 60h / Write XXh GateState
2
Cycle passed through to 8042, even if trap enabled in
Bit 1 in Config Register. No SMI# generated. PSTATE
remains 1. When data value is not DFh or DDh then
the 8042 may chose t o ign ore it.
GateS tate 1 64h / Write D1h GateState
1
Cycle passed through to 8042, even if trap enabled
through Bit 3 in Con fig Register. No SMI# genera te d.
PSTATE remains 1. Stay in GateS ta te 1 b e ca use this is
part of the double- trigger s equen ce .
GateS tate 1 64h / Write Not D 1h IDLE
Bit 3 in Conf ig space determines if cyc le pas se d
through to 8042 and if SMI# ge nerated. PS TATE goes
to 0. When B it 7 in Conf ig Register is set, then S MI#
shoul d be gener at ed.
GateState1 60h / Read N/A IDLE
This is a n in valid se q uence. Bit 0 in Con f ig Regis te r
det e rmine s if cycle p a sse d th rou g h to 80 42 and if
SMI# gen erated. PSTATE goes to 0. When Bit 7 in
Con fig Register is set, then SMI# should be generate d .
GateState1 64h / Read N/A GateState
1Just stay in same state. Gen erate an SMI# when
enab le d in Bit 2 of Config Register. PSTAT E re ma ins 1.
GateSt at e2 64 / Write FFh IDLE Standard end of sequence. Cycle passed through to
8042. PSTATE goes to 0. Bit 7 in Config S pace
dete rmin e s if SM I# should be gene rate d.
GateS tate 2 64h / Write Not FFh I DLE
Improper end of sequence. Bit 3 in Config Register
det e rmine s if cycle p a sse d th rou g h to 80 42 and if
SMI# gen erated. PSTATE goes to 0. When Bit 7 in
Con fig Register is set, then SMI# should be generate d .
GateState2 64h / Read N/A GateState
2Just stay in same state. Gen erate an SMI# when
enab le d in Bit 2 of Config Register. PSTAT E re ma ins 1.
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5. 18 USB EHCI Controller (D 29: F7)
5.18.1 Overview
The Intel® 6300ESB ICH contains an Enhanced Host Controller Interface (EHCI)
compliant host controller which supports up to four High-speed USB 2.0 Specification
compliant root ports. High-speed USB 2.0 allows data transfers up to 480 Mbps using
the same pins as the four Full-speed and Low-speed USB Universal Host Controller
Interface (UHCI) ports. The Intel® 6300ESB ICH contains port-routing logic that
determines whether a USB port is controlled by one of the UHCI controllers or by the
EHCI controller. A USB 2.0 based Debug Port is also implemented in the Intel®
6300ESB ICH.
A summary of the key architectural differences between the USB UHCI host controllers
and the USB EHCI host controller are shown in the table below:
5.18.2 EHC Initialization
The following descriptions step through the expected Intel® 6300ESB ICH Enhanced
Host Controller (EHC) initialization sequence in chronological order, beginning with a
complete power cycle in which the suspend well and core well have been off.
GateState2 60h / Write XXh IDLE
Improper end of sequence. Bit 1 in Config Register
dete rmines if cycle passed thro ugh to 8042 and if
SMI# generat ed. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
GateState2 60h / Read N/A IDLE
Improper end of sequence. Bit 0 in Config Register
dete rmines if cycle passed thro ugh to 8042 and if
SMI# generat ed. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
NOTES:
1. If bit 7 of the Extended Test Mode Register 1 (D31:F0, offset F4h ETR1, section 9.1.36) is set. P ort 60/64h
Reads and Writes from a n e x te rna l PCI agent will not affect set bits 8-11 and will not cause an SMI
independe nt of the setting of bits 0-3
2. System Software should ensure that the host controller and an external PCI agent are not simultaneously
executing keyboard accesses including an A20Gate Pass-through sequence to Port 60h & 64h. This is not
supported and the results may be indeterminate.
Table 106. USB Legacy Keyboard State Transitions
Current
State Action Data
Value Next
State Comment
Table 107. UHCI vs. EHCI
Feature USB 1.1 UHCI USB 2.0 EHCI
Accessible by I/ O sp a ce Memory Spac e
Memory Data Structure Single linked list Se p a rate d into Periodic and Asynchronous
lists.
Differe ntia l S ig n alin g Voltage 3.3 V 400 mV
Ports per Con troller 2 4
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5.18.2.1 Power On
The suspend well is a “deeper” power plane than the core well, which means that the
suspend well is always functional when the core well is functional but the core well may
not be functional when the suspend well is. Therefore, the suspend well reset pin
(RSMRST#) deasserts before the core well reset pin (PWROK) rises.
1. Th e sus p end w ell r e set deas se r ts , le a v in g all r egi sters a nd l o gic i n the su sp en d we ll
in the default state. However, it is not possible to read any registers until after the
core well reset deasserts. Note that normally the suspend well reset will only occur
when a desktop system is unplugged or the battery is removed from a mobile
system. In other words, suspend well resets are not easily achieved by software or
the end-user. This step will typically not occur immediately before the remaining
steps.
2. The core well reset deasserts, leaving all registers and logic in the core well in the
default state. The EHC configuration space is accessible at this point. Note that the
core well reset may (and typically does) occur without the suspend well reset
asserting. This means that all of the Configure Flag and Port Status and Control bits
(and any other suspend-well logic) may be in any valid state at this time.
5.18.2.2 BIOS Initialization
BIOS performs a number of platform customization steps after the core well has
powered up as described in the Intel® 6300ESB ICH BIOS Spe cif ica tio n.
5.18.2.3 Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 0.96.
5.18.2.4 EHC Resets
In addition to the standard Intel® 6300ESB ICH hardware resets, portions of the EHC
are reset by the HCRESET bit and the transition from the D3hot device power
management state to the D0 state. The effects of each of these resets are:
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When the detailed register descriptions give exceptions to these rules, those exceptions
override these rule s. This summary is provided to help explain the reasons for the res et
policies.
5.18.3 Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 0.96.
Tab l e 10 8. EH C Re set s
Reset Does Reset Does not Reset Commen ts
HCRESET bit
set
Memory space
registers except
Structural Parameters
(which is written by
BIOS).
Configuration
registers
The HCRES E T must only
affect registers that the EHCI
driver co ntrols. PCI
Configuration space and
BIOS-programmed
param eters cann ot be rese t .
See S ection 11.2.2.1, “Offset
CAPLENGTH + 00 - 03h: USB
EHCI CMD —USB EHCI
Command Register” for
information reg a rd ing offse t
00h, bit 1.
Software writes
the Device
Powe r S tate
from D3 hot
(11b) to D0
(00b).
Co re we ll re gi ste rs
(except BIOS -
programmed
registers).
Suspend well
registers; BIOS-
prog ramm ed c o r e
well reg iste rs
The D3-to-D0 tr ansition must
not cause wake information
(suspend well) to b e lost. It
also must not clear BIOS-
prog ramm ed r egisters
because BIOS may not be
invoked following the D3-to-
D0 transition.
See Section 11.1.17, “Offset
54 - 55h: Power Management
Control/Status for more
information.
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5.18.4 USB 2.0 Enhanced Host Controller DMA
The Intel® 6300ESB ICH USB 2.0 EHC implements three sources of USB packets. They
are, in order of priority on USB during each microframe:
1. USB 2.0 Debug Port (see Section 5.18.11, “USB 2.0 EHCI Based Debug Port”)
2. Periodic DM A engine
3. Asynchronous DMA engine
The Intel® 6300ESB ICH always performs any currently-pending deb ug port
transaction at the beginning of a microframe, followed by any pending periodic traffic
for the current microframe. When there is time left in the microframe, then the EHC
performs any pending asynchronous traffic until the end of the microframe (EOF1).
Note th at the d ebug por t t ra ffic i s onl y p res ented on one po rt (P o rt # 0), whi le th e othe r
ports are idle during this time.
The following subsections describe the policies of the periodic and asynchronous DMA
engines.
5.18.4.1 Periodic List Execution
The Periodic DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports. Note that a multiple-packet, High-Bandwidth transaction occupies one of these
buf fe r e ntrie s, whi ch me ans th at up t o six 1- Kby te dat a pack ets m ay be a ssoci ated wi th
the two buffered control structures.
5.18.4.1.1 Read Policies for Periodic DMA
The Periodic DMA engine performs reads for th e following structures.
Table 109. Read Policies for Periodic DMA
Memory Structure Size
(DWORDs) Comments
Periodic Frame List
entry 1The EHC reads th e entry for each microframe. The
frame li st is n ot intern ally cached a cross mi crof ra me s.
iTD 23 Only the 64-bit addressing format is supported.
siTD 9 Only the 64-bit addressin g format is supported.
qTD 13 Only the 64-bit addressing format is supported.
Queue Head 17 Only the 64-bit addressing format is supported.
Ou t Data Up to 257 The Intel® 6300ESB ICH b re ak s larg e re ad reque sts
down into smaller aligned read requests based on the
sett ing of the Read Requ est M ax Le ngt h field.
Frame Span
Transversal Node 2
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The EHC Periodic DMA Engine (PDE) does not generate accesses to main memory
unless all three of the following conditions are met.
The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit
indirectly by setting the RUN/STOP bit to 1. See Section 11.2.2.2, “Offset
CAPL ENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status for more information.
The Periodic Schedule Status bit is 1 (memory space, offset 04h, bit 14). Software
sets this bit indirectly by setting the Periodic Schedule Enable Bit to 1. See
Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07 h: USB EHCI STS—USB EHCI
Status” for more information.
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See
Section 11.1.1, “Offset 04 - 05h: Command Register” for more information.
Note: Prefetching is limited to the current and next microframes only.
Note: Once the PDE checks the length of a periodic packet against the remaining time in the
microframe (late-start check) and decides that there is not enough time to run it on the
wire, then the EHC switches over to run asynchronous traffic.
5.18.4.1.2 Write Policies for Periodic DMA
The Periodic DMA engine performs writes for the following reasons.
Tabl e 11 0. Wr ite Polic ie s for Perio dic DMA
Memory Structure Size
(DWORDs
)Comments
iTD Sta tus Write 1 Only the DWORD that co rre spond s to the ju st-
executed microframe’s status is wr itten. All bytes of
the DWO RD a re wri tten.
siTD S ta tu s Write 3 DWO RDs 0C:17h are wr itten. IOC a nd B uffe r Pointe r
field s are re -writte n with the orig in al value .
Interrupt Queue Head
Overlay 14 Only the 64-bit addressing format is supported.
DWORDs 0C:43h are writte n.
Interrupt Queue Head
Stat us Wri t e 5 DWO RDs 14:27h are written.
Interrupt qTD Status
Write 3DWORD s 04:0Fh are wr itte n. PID Code, IOC, Bu ffer
Pointers, and A lt. N ext qTD Poin te rs are re -writte n
with the original value.
In Data Up to 257 The In t e l ® 6300ESB ICH breaks data writes down into
16 DWORD aligned chunks.
NOTES:
1. The Periodic DMA En g ine (P DE) will on ly gene ra te write s af te r a trans action is executed on
USB.
2. Status writes are always performed after In Data writes for the same transaction.
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5.18.4.2 Asynchronous List Execution
The Asynchronous DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports.
5.18.4.2.1 Read Policies for Asynchronous DMA
The Asynchronous DMA engine performs reads for the following structures.
The EHC Async hronous DMA Engin e (ADE) does not gener ate accesses to main memory
unless all four of the following conditions are met. (Note that the ADE may be active
when the periodic schedule is actively executed, unlike the description in the EHCI
specification; since the EHC contains independent DMA engines, the ADE may perform
memory accesses interleaved with the PDE accesses.)
The HCHalted bit is 0 (memory space, offset 04h, bit 12). Software clears this bit
indirectly by setting the RUN/STOP bit to 1.
The Asynchronous Schedule Status bit is 1 (memory space, offset 04h, bit 15).
Software sets this bit indirectly by setting the Asynchronous Schedule Enable Bit to
1. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB
EHCI Status” for more information.
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2). See
Section 11.1.1, “Offset 04 - 05h: Command Register” for more information.
Th e A DE i s not s lee pin g du e to the d et ect ion o f a n emp ty s che dule . T her e is not o ne
single bit that indicates this state. However, the sleeping state is entered when the
Queue Head with the H bit set is encountered when the Reclamation bit in the USB
EHCI Status register is 0. See Section 11.2.2.2, “Offset CAPLENGTH + 04 - 07h:
USB EHCI STS—USB EHCI Status for information regarding offset 04h, bit 13.
Note: The ADE does not fetch data when a QH is encountered in the Ping state. An Ack
handshake in response to the Ping results in the ADE writing the QH to the Out state,
which results in the fetching and delivery of the Out Data on the next iteration through
the asynchronous list.
Note: Once the A DE ch ecks the len gth of an async hron ous packe t aga inst th e rema ini ng time
in th e micr ofr ame (l at e-sta rt chec k) a nd decid es tha t ther e is not enough ti me to run it
on the wire, then the EHC stops all activity on the USB ports for the remainder of that
microframe.
Note: Once the ADE detects an “emptyasynchronous schedule as described in Section 4 of
the EHCI specification, it implements a waking mechanism like the one in the example.
The amount of time that the ADE “sleeps” is 10 µs ± 30 ns.
Table 111. Read Policies for Asynchronous DMA
Memory
Structure Size (DW) Comme nts
qTD 13 Only the 64-bit addressing fo rmat is supported.
Queu e Head 17 Only the 64-bit addressing format is supported.
Ou t Data Up to 129 The I n t e l ® 6300ES B ICH br ea ks large read re qu ests
down into smaller aligned read re q u e sts based on the
setting of the Read Request Max Leng th f ield .
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5.18.4.2.2 Write Policies for Asynchronous DMA
The Asynchronous DMA engine performs writes for the following reasons.
5.18.5 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification.
5.18.6 Packet Formats
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification.
5.18.7 USB EHCI Interrupts and Error Conditions
Section 4 of the EHCI specification goes into detail on the EHC interrupts and the error
conditions that cause them. All error conditions that the EHC detect s may be reported
thr ough th e EHCI I nter rupt statu s bi ts. Only Int el® 630 0ESB ICH -spe cific inte rrup t and
error-reporting behavior is docu mented in this section. The EHCI Interrupts Section
must be read first, followed by this section of the EDS to fully comprehend the EHC
interrupt and error-reporting functionality.
Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
Error may not occur on the Intel® 6300ESB ICH.
Master Abort and Target Abort responses from Hub Interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
The Intel® 6300ESB ICH may assert the interrupts which are based on the
interrupt threshold as soon as the status for the last complete transaction in the
interrupt interval has been posted in the internal write buffers. The requirement in
the EHC I Specifi cation ( that the sta tus is wri tten to memory) is met interna lly, even
though the write may not be seen on the Hub Inter face before the interrupt is
asserted.
Sin ce the Intel ® 6300ESB ICH supports the 1024-element Frame List size, the
Frame List Rollover interrupt occurs every 1024 milliseconds.
Table 112. Write Policies for Asynchronous DMA
Memory Structure Size
(DWORDs
)Comments
Asynchronous
Queue Head
Overlay 14 Only the 64-bit addressing format is supported. DWORDs
0C:43h are written.
Asynchronous
Queue Head Status
Write 34 D W ORD s 14:1Fh are written.
As ync h ronou s qTD
Stat us Wri t e 3DWORDs 04:0 Fh a re writte n. PID Cod e , IOC, B uf fer Pointer
(Page 0), an d Alt. Ne xt qTD Pointe rs are re -written with the
original value.
In Data Up to 1297 The In t e l ® 6300ESB ICH breaks data write s down into 16
DWORD aligned chunks.
NOTES:
1. The Asynchronous DMA Engine (ADE) will only generate writes after a transaction is executed
on USB.
2. Status writes are always performed after In Data writes for the same transaction.
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The Intel® 6300ESB ICH delivers interrupts using PIRQ#[H].
The Intel® 6300ESB ICH does not modify the CERR count on an Interrupt IN when
the “Do Complete-Split” execution criteria are not met.
F or c om plete -spl it tr ansa ct ions in th e P eri odic l ist, th e “ Missed M i croframe” b it d oes
not get set on a control-structure-fetch that fails the late-start test. When
subsequent accesses to that control structure do not fail the late-start test, then
the Missed Microframe” bit will get set and written back.
5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads
When a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
The Host System Error status bit is set. See Section 11.2.2.2, “Offset CAPLENGTH
+ 04 - 07h: USB EHCI STS—USB EHCI Status” for information regarding offset
04h, bit 4.
The DMA engines are halted after completing up to one more transaction on the
USB inte r fac e.
When enabled (by the Host System Error Enable), an interrupt is generated. See
Section 11.2.2.3,Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI
Interrupt Enable” for information regarding offset 08h, bit 4.
When the status is Master Abort, the Received Master Abort bit in configuration
space is set. Section 11.1.2, “Offset 06 - 07h: Device Status for information
rega rdin g offset 06h, bit 13.
When the status is Target Abort, the Received Target Abort bit in configuration
space is set. Section 11.1.2, “Offset 06 - 07h: Device Status for information
rega rdin g offset 06h, bit 12.
When enabled (by the SERR Enable bit in the function’s configuration space, see
Section 11.1.1, “Offset 04 - 05h: Command Register”, offset 04h, bit 8), the
Signaled System Error bit is set by the Intel® 6300ESB ICH when it signals SERR#
(internally). Section 11.1.2, “Offset 06 - 07h: Device Status” for information
regarding offset 06h,
bit 14.
5.18.8 USB EHCI Power Management
5.18.8.1 Pause Featur e
This feature allows platforms, especially mobile systems, to dynamically enter low-
power states during brief periods when the system is idle, i.e., between keystrokes.
This is useful for enabling power management features like C3, C4, and Intel®
SpeedStep® technology in the Intel® 6300ESB ICH. The policies for entering these
states typically are based on the recent history of system bus activity to incrementally
enter deeper power management states. Normally, when the EHC is enabled, it
regularly accesses main memory while traversing the DMA sch edules looking for work
to do; this activity is viewed by the power management software as a non-idle system,
thus preventing the power managed states to be entered. Suspending all of the
enabled ports may prevent the memory accesses from occurring, but there is an
inherent latency overhead with entering and exiting the suspended state on the USB
ports that mak es this unacceptable for the purpose of dynamic power management. As
a result, the EHCI software drivers are allowed to pause the EHC s DMA engines when it
kn ows tha t the tr aff ic p atterns of the at tache d de vices may af ford the de la y. The pause
only prevents the EHC from gener ating memory accesses; t he SOF packets co ntinue to
be generated on the USB ports (unlike the suspended state).
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5.18.8.2 Suspen d Feature
The EHCI Specification describes the details of Port Suspend and Resume in detail in
Section 4.3.
5.18.8.3 ACPI Device States
The USB EHCI function only supports the D0 and D3 PCI Power Management states.
Notes regarding the Intel® 6300ESB ICH implementa tion of the Device States:
1. The EHC hardware does not inherently consume any more power when it is in the
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
con sum pt ion is redu ce d.
2. In the D0 state, all implemented EHC features are enabled.
3. In t he D3 state, accesses to the EHC memory -mapped I /O range will master abort.
Note that, since the Debug Port uses the same memory range, the Debug Port is
only operational when the EHC is in the D0 state.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
PME# signal is used to signal wake events, etc.
5. When the Device Power State field is written to D0 from D3, an internal reset is
gen erated. See section EHC Resets for general rules on the effects of this reset.
6. Attempts to write any other value into the Device Power State f ield other than 00b
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field. See Section 11.1.17, “Offset 54 - 55h: Power Management
Control/Status for information regarding offset 54h, bits [1:0].
5.18.8.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
When in D0, the Pause feature (See Section 5.18.8.1, “Pause Feature) enables
dynamic processor low-power states to be entered.
All core well logic is reset in the S3/S4/S5 states (core power turns off).
5.18.8.5 Low-power system Considerations
The Intel® 6300ESB ICH USB EHCI implementation does not behave differently in low
power configurations. However, some features may be especially useful for th e low
power configurations.
Low-power systems are not likely to use all four of the USB ports that are provided
on the Intel® 6300ESB ICH. With this in mind, the Intel® 6300ESB ICH provides
mechanisms for changing the structural parameters of the EHC and hiding unused
USB UHCI controllers. See Intel® 6300ESB ICH BIOS Specification on how BIOS
should configure the Intel® 6300ESB ICH.
Low-power systems may want to minimize the conditions that will wake the
system. The Intel® 6300ESB ICH implements the “Wake Enable” bits in the Port
Status and Control registers, as specified in the EHCI spec, for this purpose.
Low-power systems may want to cut suspend well power to some or all USB ports
when in a low-power state. The Intel® 6300ESB ICH implements the optional Port
Wake Capability Register in the EHC Configuration Space for this platform-specific
information to be communicated to software.
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5.18.9 Interaction with Classic Host Controllers
Th e Enhance d Host Control ler share s th e four USB port s with two UHCI Ho st Cont rolle rs
in the Intel® 6300ESB ICH. The USB UHCI Controller at D29:F0 shares ports 0 and 1
and the USB UHCI Controller at D29:F1 shares ports 2 and 3 with the EHCI Controller.
There is very little interaction between the USB EHCI and the USB UHCI controllers
other than the muxing control which is provided as part of the EHCI Controller.
Figure 22 depicts the USB Port Connections at a conceptual level. The dashed rectangle
indicates all of the logic that is part of the Enhanced Host Controller cluster.
5.18.9.1 Port-Routing Logic
Integrated into the EHC functionality is port-routing logic, which performs the muxing
between the USB UHCI and USB EHCI host controllers. The Intel® 6300ESB ICH
conceptually implements this logic as described in Section 4.2 of the EHCI
Specification. When a device is connected that is not capable of USB 2.0’s High-Speed
signaling protocol or when the EHCI software drivers are not present as indicated by
the Configured Flag, the USB UHCI Controller owns the port. Owning the port means
that the differential output is driven by the owner and the input stream is only visible to
the owner. The host controller that is not the owner of the port internally sees a
disconnected port.
No te tha t t he port - rout in g lo gic i s the onl y b lock of l ogic w ithi n th e Inte l ® 6300ES B ICH
that observes the physical (real) connect/disconnect information. The port status logic
inside each of the host controllers observes the electrical connect/disconnect
information that is generated by the port-routing logic.
Only the differential signal pairs are muxed/demuxed between the USB UHCI and USB
EHCI host controllers. The other USB functional signals are handled as follows: The
overcurrent inputs (OC#[3:0]) are directly routed to both controllers. An overcurrent
event is recorded in both controllers’ status registers.
The Port-Routing logic is implemented in the Suspend power well so that re-
enumeration and remapping of the USB ports is not required following entering and
exiting a system sleep state in which the core power is turned off.
Figure 22. Intel® 6300ESB ICH-USB Port Connections
Port 0
Port 1
Port 2
Port 3
UHCI #2
(D29:F1) UHCI #1
(D29:F0)
E H CI (D29:F7 ) Debug
Port
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The Intel® 6300ESB ICH also allows the USB Debug Port traffic to be routed in and out
of Po rt #0. When in this mode, the Enhanced Host Controller is the owner of Port #0.
5.18.9.2 Device Connects
Sec tion 4.2 of the E HCI Specif icat ion descr ibes the deta ils of ha ndling Devi ce Conne cts.
There are four general scenarios that are summarized below. See Section 11.2.2.8,
“Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register”.
1. Configure Flag = 0 and a USB Full-speed/Low-speed -only Device is connected
In this case, the U SB UHCI Controller is the owner of the port both before
and after the co nnect occurs. The EHC (except for the port-routing logic)
never sees the connect occur. The UHCI driver handles the connection and
in itializa ti o n p r o c ess.
2. Configure Flag = 0 and an USB High-speed-capable Device is connected
In this case, the U SB UHCI Controller is the owner of the port both before
and after the co nnect occurs. The EHC (except for the port-routing logic)
never sees the connect occur. The UHCI driver handles the connection and
in itializa ti o n p r o c ess. Sinc e the U SB UHC I Co ntro lle r does no t perf o r m the
high-speed chirp handshake, the device operates in compatible mode.
3. Configure Flag = 1 and a USB Full-speed/Low-speed-only Device is connected
In this case, the USB EHCI Controller is the owner of the port before the
conn ect occurs . Th e EH CI dr iver ha ndles the connection an d per f orms the
port reset. Aft er the reset proc ess co mpl et es, th e EHC hardware has
cleared (not set) the P o rt Enable bit in the EHC’ s P ORTSC regist er. Th e
EHCI driver then writes a 1 to the Port Own er bit in the same register,
causing the U SB UHCI Contro ller to see a connect event and the EHC to
see an electrical disconnect event . The UHCI driver and hardware hand l e
th e co nne ct ion a nd ini ti a lizat io n process from th at point on. The E H C I
driver and ha rd ware ha ndle the per c e ived d isco nne c t.
4. Configure Flag = 1 and an USB High-speed-capable Device is connected
In this case, the USB EHCI Controller is the owner of the port before, and
remain s th e owner after, t he connect occ urs. The EHCI driver handles the
connection and performs the port reset. After the reset process completes,
the EHC hardware has set the Port Enable bit in the EHCs PORTSC register.
Th e port is funct io nal a t this poin t. The US B U H C I Cont rolle r continu es to
see an unconne c te d p or t.
5.18.9.3 Dev i ce Disconnects
Sec tion 4.2 of the E HCI Specif icat ion descr ibes the deta ils of ha ndling Devi ce Conne cts.
There are three general scenarios that are summarized below. See Section 11.2.2.8,
“Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register”.
1. Configure Flag = 0 and the device is disconnected.
In this case, the U SB UHCI Controller is the owner of the port both before
and after the disco nnect occurs. The EHC (except for th e port-routing
logic) nev er sees a device attached. The UH CI driver handles disconn ection
process.
2. Configure Flag = 1 and a USB Full-speed/Low-speed-capable De vice is
disconnected.
In this case, the USB UHCI Controller is the owner of the port before the
disconnect occurs. The disconnect is reported by the USB U HCI Controller
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and serviced by the associated UHCI driver. The port-routing logic in the
EHC c lu s ter fo rc es the Port O w n e r bi t to 0, ind i ca ting that the EHC ow n s
the un co nne c te d p or t.
3. Configure Flag = 1 and a USB High-speed-capable Device is disconnected.
In thi s case, the USB EHCI Controller is the owner of the port before, and
remains th e own e r a f te r, th e d is connect occ ur s. The EH C I ha rdw a r e a nd
driver h andle th e disconnection process. The US B UHCI Controller never
sees a device att ached.
5.18.9.4 Effect of Resets on Port-Routing Logic
As mentioned above, the Port Routing logic is implemented in the Suspend power well
so that reenumeration and remapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
5.18.10 USB 2.0 Legacy Keyboard Operation
The Intel® 6300ESB ICH must support the possibility of a keyboard downstream from
either a USB UHCI or a USB EHCI port. The description of the legacy keyboard support
i s unchan ge d fr om USB UHC I ( S ee Se ct io n 5.17 .9, “ U SB Le g ac y Keyboar d Ope r a ti on ).
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
5.18.11 U SB 2.0 EH CI Ba sed De bug Port
The Intel® 6 300E SB ICH s uppo rts t he eli mina tion o f t he leg acy COM p orts by pro vid ing
the ability for new debugger software to interact with devices on a USB EHCI port.
High-level restrictions and features are:
Must be operational before USB EHCI drivers are loaded.
Must work even when the port is disabled.
Must work even though non-configured port is default-routed to the classic
cont roller. Note that the Debug Port cannot be used to debug an issue that requires
a classic USB device on Port #0 using the UHCI drivers.
Must allow normal system USB E HCI traffic in a system that may only have one
USB po rt.
Debug Port device (DPD) must be High-Speed capable and connect to a High-Speed
port on Intel® 6300ESB ICH systems.
Debug Port FIFO must always make forward progress (a bad status on USB is
simply presented back to software)
The Debug Port FIFO is only given one USB access per microframe
Table 113. Effect of Resets on Port-Routing Logic
Reset Event Effect on Configure Flag Effect on Port Owner Bits
Suspend Well Reset cleared (0) set (1)
Core Well Reset no effect no effect
D3-to-D0 Reset no effect no effect
HCRESET clear ed (0) set (1)
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5.18.11.1Overview
The Debug port facilitates OS and device driver debug. It allows the software to
communicate with an external console using a USB EHCI connection. Since the
interface to this link does not go through the normal USB EHCI stack, it allows
communication with the external console during cases where the OS is not loaded, the
USB EHCI software is broken, or where the USB EHCI software is being debugged.
Specific features of this implementation of a debug port are:
Only works with an external USB 2.0 debug device (console)
Implemented for a specific port on the host controller
Operational anytime the port is not suspended AND the host controller is in D0
power state.
Capability is interrupted when port is driving USB RESET
5.18.11.2Theory of Operation
There are two operational modes for the USB debug port:
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard
host controller driver. In Mode 1, the Debug Port controller is required to generate a
“keepalive” packets less than 2 ms apart to keep the attached debug device from
suspending. The keepalive packet should be a standalone 32-bit SYNC field.
2. Mode 2 is when the host controller is running (i.e., Host controller’s Run/Stop# bit
is 1). In Mode 2, the normal transmission of SOF packets will keep the debug
device from suspending.
Detail for the registers mentioned in the next sections can be found in Sectio n 11.2.3,
“USB 2.0-Based Debug Port Register” and in Section 11.2, “Memory-Mapped I/O
Registers”.
Behavioral Rules:
1. In both modes 1 and 2, the Debug Port controller must check for software
requested debug transactions at least every 125 microseconds.
2. When the debug port is enabled by the debug driver, and the standard host
controller driver resets the USB port, USB debug transactions are held off for the
duration of the reset and until after the first SOF is sent.
3. When the standard host controller driver suspends the USB port, then USB debug
tr ansa ction s ar e held o ff for the d urati on of t he sus pend/r esu me sequ ence an d unti l
after the first SOF is sent.
4. The ENABLED_CNT bit in the debug register space is independent of the similar
port control bit in the associated Port Status and Control register.
Table 114 describes the debug port behavior related to the state of bits in the debug
registers as well as bits in the associated Port Status and Control register.
Table 114. USB Debug Port Behavior (Sheet 1 of 2)
OWNER_CN
TENABLED_C
NT Port
Enable Run /
Stop Suspen
d Debug Port Behavior
0XXXX
Debug port is not being used.
Normal operation.
10XXX
Debug port is not being used.
Normal operation.
1100X
Debug port in Mode 1. SYNC
keep alives sent pl us debug
traffic.
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5.18.11.2.1OUT Transactions
An Out transaction sends data to the debug device . It may occur only when the
following are true:
1. The debug port is enabled.
2. The debug software sets the GO_CNT bit.
3. The WRITE_READ#_CNT bit is set.
The sequence of the transaction is listed below.
1. Software sets the appropriate values in these bits:
USB_ADDRESS_CNF
—USB_ENDPOINT_CNF
DATA_BUFFER[63:0]
TOKEN_PID_CNT[7:0]
SEND_PID_CNT[15:8]
—DATA_LEN_CNT
WRITE_READ#_CNT (Note: This will a lways be 1 f or OUT trans actions.)
—GO_CNT (Note: Th is will alwa y s b e 1 to initiate the transac tion .)
1101X
Debug port in Mode 2. SOF
(and only SOF) is sent as
keepalive. Debug traffic is also
sent. Note that no other
normal tra ffic is sent out this
port, be cause the port is not
enabled.
11100
Illega l. Ho st con troller driver
should never p ut controller
into this state (ena b led , not
running and not suspended).
11101
Port is suspended. No debug
traf fic sent .
11110
Debug port in Mode 2. Debug
traffic is inte rspe rsed with
normal traffic.
11111
Port is suspended. No debug
traf fic sent .
Table 114. USB Debug Port Behavior (Sheet 2 of 2)
OWNER_CN
TENABLED_C
NT Port
Enable Run /
Stop Suspen
d De bug Port Be h avior
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2. The debug port controller sends a token packet consisting of:
a. SYNC
b. TOKEN_PID_CNT field
c. USB_ADDRESS_CNT field
d. USB_ENDPOINT_CNT field
e. 5-bit CRC field
3. After sending the token packet, the debug port controller sends a data packet
consisting of
a. SYNC
b. SEND_PID_CNT field
c. The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER
d. 16-bit CRC
Note: A DATA_LEN_CNT value of zero is valid in which case no data bytes would be included
in the packet.
4. After sending the data packet, the controller waits for a handshake response from
the debug device.
When a handshake is received, the debug port controller:
a. Places the received PID in the RECEIVED_PID_STS field
b. Resets th e ERROR_GOOD#_STS bi t
c. Sets the DONE_STS bit
When no handshake PID is received, the debug port controller:
a. Sets the EXCEPTION_STS field to 001b
b. Sets the ERROR_GOOD#_STS bit
c. Sets the DONE_STS bit
5.18.11.2.2IN Transactions
An IN transaction receives data from the debug device. It may occur only when the
following are true:
1. The debug port is enabled
2. The debug software sets the GO_CNT bit
3. The WRITE_READ#_CNT bit is reset
The sequence of the transaction is:
1. Software sets the appropriate values in the following bits:
USB_ADDRESS_CNF
—USB_ENDPOINT_CNF
TOKEN_PID_CNT[7:0]
—DATA_LEN_CNT
WRITE_READ#_CNT (Note: T his will always be 0 for IN transactions.)
—GO_CNT (Note: Th is will a lways be 1 to initiate th e transac tion.)
2. The debug port controller sends a token packet consisting of:
a. SYNC
b. TOKEN_PID_CNT field
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c. USB_ADDRESS_CNT field
d. USB_ENDPOINT_CNT field
e. 5-bit CRC field.
3. Af ter sending t he token packet, the debug po rt controller waits for a response from
the debug device. When a response is received:
a. The received PID is placed into the RECEIVED_PID_STS field
b. Any subsequent bytes are placed into the DATA_BUFFER
c. The DATA_LEN_CNT field is updated to show the number of bytes that were
received after the PID.
4. When valid packet was received from the device that was one byte in length
(indicating it was a handshake packet), then the debug port controller:
a. Resets the ERROR_GOOD#_STS bit
b. Sets the DONE_STS bit
5. When valid packet was received from the device that was more than one byte in
length (indicating it was a data packet), then the debug port controller:
a. Transmits an ACK handshake packet
b. Resets the ERROR_GOOD#_STS bit
c. Sets the DONE_STS bit
6. When no valid packet is received, then the debug port controller:
a. Sets the EXCEPTION_STS field to 001b
b. Sets the ERROR_GOOD#_STS bit
c. Sets the DONE_STS bit.
5.18.11.2.3 Debug Software
Enabling the Debu g Po rt
There are two mutually exclusive conditions that debug software must address as part
of its startup processing:
1. The EHC I ha s bee n ini t ial ized by sys t em sof tware
2. The EHCI has not been initialized by system software
Debug software may determine the current ‘initialized’ state of the EHCI by examining
the Configure Flag in the EHCI USB 2.0 Command Register. See Section 11.2.2.8,
“Of fs et CAPLENGTH + 40 - 43h: CONFIGFLAG—Conf igure Flag R egiste r for information
regarding offset 40h, bit 0. When this flag is set, then system software has initialized
the EHCI. Ot herwise, the EHCI should not be considered init ialized. Debug software will
initialize the debug port registers depending on the state the EHCI. However, before
this may be accomplished, debug software must determine which root USB port is
designated as the debug port.
Determining the Debu g Po r t
Debug software may determine which USB root port has been designated as the debug
port by examining bits 20:23 of the EHCI Host Controller Structural Parameters
regi ster. See Section 11.2.1.3, “Offset 04 - 07h: HCSPARAMS—Host Controller
Structural Parameters” for information regarding offset 04h. This 4-bit field represents
the numeric value assigned to the debug port (i.e., 0000=port 0).
Debug Software Startup with Non-Initialized EHCI
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Debug sof tw are ma y a ttempt to us e th e debug port a fte r s etti ng th e OWNE R_CNT b it in
the Control/Status Register, Section 11.2.3.1, “Offset 00h: Control/Status Register”,
offset 00h, bit 30, and the Current Connect Status bit in the appropriate (See
Determining the Debug Port) PORTSC register is set. See Section 11.2.2.9, “PORTSC-
Port N Status and Control” for information regarding bit 0. When the Current Connect
Statu s bit is not se t, th en debu g softw are may choo se to te rmina te or it may ch oose to
wait until a device is connected.
When a device is connected to the port, then debug software must reset/enable the
port. Debug software does this by setting and then clearing the Port Reset bit the
PORTSC register. To ensure a successful re set, debug softw are should wait at least 50
ms before clearing t he P ort R eset bit. Du e to pos sible del ays, th is bi t ma y not chang e to
zero immediately; reset is complete when this bit reads as zero. Software must not
continue until this bit reads zero.
When a hi gh-speed device is attached, the EHCI will automatically set the Port
Enabled/Disabled bit in the PORTSC register and the debug software may proceed.
Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status
regis ter, and then reset ( cl ear) the P ort Enable d/Disabl ed bit in the POR TSC regi ster (so
that the system host controller driver doesn't see an enabled port when it is first
loaded).
Debug Software Startup with Initialized EHCI
Debug software may attempt to use the debug port when the Current Connect Status
bit in the appropriate (See Determining the Debug Port) PORTSC register is set. When
the Current Connect Status bit is not set, then debug software may choose to
terminate or it may choose to wait until a device is connected.
When a device is connected, then debug software must set the OWNER_CNT bit and
then the ENABLED_CNT bit in the Debug Port Control/Status register. See
Sec tion 11.2.3. 1, “Offset 00h : Co ntrol/ St atus R eg ister” for information regarding offs et
00h, bits 30 and 28.
Determin ing Debu g Peri pheral Presence
After enabling the debug port functionality, debug software may determine when a
debug peripheral is attached by attempting to send data to the debug peripher al. When
all attempts result in an error (Exception bits in the Debug Port Control/Status register
indicates a Transaction Error), the attached device is not a debug peripheral. See
Sec tion 11.2.3. 1, “Offset 00h : Co ntrol/ St atus R eg ister” for information regarding offs et
00h, bits [9:7]. When the debug port peripheral is not present, then debug software
may choose to terminate or it may choose to wait until a debug peripheral is
connected.
5. 19 SMBus Controller Functio na l Descrip tion
(D31:F3)
5.19.1 Overview
The Intel® 6300ESB ICH pro vides an SMBus 2. 0 compliant H ost Con troller a s we ll as an
SMBus slave interface.
The host controller provides a mechanism for the processor to initiate communications
with SMBus peripherals (slaves). T he Intel® 6300ESB ICH is also capable of operating
in a mode in which it may communicate with I2C compatible devices.
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The Intel® 6300ESB ICH may perform SMBus messages with either packet error
checking (PEC) enabled or disabled. The actual PEC calculation and checking is
performed in software.The SMBus Host Controller logic may automatically append the
CRC byte when configured to do so.
The Slave Interface allows an external master to read from or write to the Intel®
6300ES B ICH . W ri te c yc les m ay be u sed to caus e ce rta in e ve nts or pass me ssages , and
the read cycles may be used to determine the state of various status bits. The Intel®
6300ESB ICH’s internal Host Controller cannot access the Intel® 6300ESB ICH’s
internal Slave Interface.
The Intel® 6300ESB ICH SMBus logic exists in Device 31:Function 3 configuration
sp ace, and c onsis ts of a tra ns mit da ta pat h, a nd ho st c ont rol ler. The tr an smit data path
provides the data flow logic needed to implement the seven different SMBus command
protocols and is controlled by the host controller. The Intel® 6300ESB ICH SMBus
controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done through the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
5.19.2 Host Controlle r
The SMBus Host Controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it will generate an SMI# or
interrupt, when enabled.
The host controller supports seven command protocols of the SMBus interface (see the
SMBus Specification): Quick Command, Send Byte, Receive Byte, Write Byte/Word,
Read Byte/Word, ProcessCall, Block Read, Block Write and Block Write-Block Read
process call.
The SMBus Host Controller requires that the various data and command fields be setup
for th e type of command to be se nt. When softw are sets the ST A RT bit, the SMB us Host
Controller will perform the requested transaction, and interrupt the processor (or
generate an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control, Host Command,
Transmit Slave Address, Data 0, Data 1) should not be changed or read until the
interrupt status bit (INTR) has been set (indicating the completion of the command).
Any register values needed for computation purposes should be saved prior to issuing
of a new command, as the SMBus Host Controller will update all registers while
completing the new command.
Using the SMBus Host Controller to send commands to the Intel® 6300ESB ICH's
SMBus slave port is supported.
The Intel® 6300ESB ICH supports slave functionality, including the Host Notify
protocol, on the SMLink pins when in TCO compatible mode. Therefore, in order to be
fully compliant with the SMBus 2.0 specification (which requires the Host Notify cycle),
the SMLink and SMBus signals must be tied together externally. However, this
req uirement to ti e b oth SMLink an d SMBus signals e xter nally is no t needed in adv anced
TCO mode as the slave functionality is available on the SMBus pins.
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5.19.2.1 Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to
determine the progress of the command. While the command is in operation, the
HOST_BUSY bit is set. When the command completes successfully, the INTR bit will be
set in the Host Status Register. When the device does not respond with an
acknowledge, and the transaction times out, the DEV_ERR bit is set. When software
sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set. When the KILL bit is set, the Intel®
6300ESB ICH will abort current transaction by asserting SMBCLK low for greater than
the timeout period, assert a STOP condition and then releases SMBCLK and SMBDATA.
However, setting the KILL bit does not affect SMLINK or TCO transactions or causes
Intel® 6300ESB ICH to force a timeout when it is not performing a transaction.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent.
The PEC byte is never appended to the Quick Protocol. Software should force the
PEC_EN bit to ‘0’ when performing the Quick Command. Software must force the
I2C_EN bit to 0 when running this command. The format of the protocol is shown in
Table 115.
Send Byte/Receive Byt e
For the Send Byte command, the Transmit Slave Address and Device Command
Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data
received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when
ru nnin g this com ma nd .
The Receive Byte is similar to a Send Byte, the only difference is the direction of data
transfer. The format of the protocol is shown in Table 116 and Table 117.
Tab l e 11 5. Quic k Pro toc ol
Bit Description
1 S tart Condition
2–8 Sla ve Addr es s - 7 bits
9 R ead / Write Di recti o n
10 Acknowledge from
slave
11 Stop
Table 116. Send/Receive Byte Protocol without PEC
Send Byte Prot ocol Rece ive Byt e Protoc ol
Bit Description Bit Description
1 Start 1 Start
2–8 Slave Addres s - 7 bits 2– 8 Slave Address - 7 bits
9Write 9 Read
10 Ack nowledge fr om slave 10 Acknowled ge f rom slave
11–18 Co mmand code - 8 bits 11–18 Data byte from slave
19 Ack nowledge fr om slave 19 NOT Ackn owledge
20 Stop 20 Stop
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Write Byte/Word
The first byte of a Write Byte/W ord access is the command code. The next 1 or 2 bytes
are the data to be writt en. Whe n pro gramm ed for a Write Byte /Word com ma nd , the
Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,
the Data1 Register is sent on a Write W ord command. Software must force the I2C_EN
bit to 0 when running this command. The format of the protocol is shown in Table 118
and Table 119.
Table 117. Send/Receive Byte Protocol with PEC
Send Byte Protoc ol Receive B yte Protoc ol
Bit Description Bit Description
1 Start 1 Start
2 –8 S la ve Addre ss - 7 bits 2–8 S la ve A dd re ss - 7 bits
9Write 9Read
10 Ac knowledge from slave 10 Acknowledge from slave
11–18 Comm and cod e - 8 bits 11 –18 Data byte from s lave
19 Ac knowledge from slave 19 Acknowledge
20–27 PEC 20–27 PEC from slave
28 Ackno wle d ge f rom sla ve 2 8 Not Acknowledge
29 Stop 29 Stop
Table 118. Write Byte/Word Protocol without PEC
Write Byte Prot ocol Write Word Protoc ol
Bit Description Bit Description
1 Start 1 Start
2–8 Slav e Addr es s - 7 bits 2–8 Sla v e Addr es s - 7 bits
9 Write 9 Write
10 Ac kno w le dge from sla v e 10 Ackno w ledge fr om sla v e
11–18 Command code - 8 bits 11–18 Command code - 8 bit s
19 Ac kno w le dge from sla v e 19 Ackno w ledge fr om sla v e
20–27 Data Byte - 8 bits 20–27 D ata Byte Low - 8 bits
28 Ac kno w le dge from Sla ve 28 Acknow l edge fr om Sla ve
29 Stop 29–36 Data Byte High - 8 bits
37 Ackno wl edge fr om sla v e
38 Stop
Table 119. Write Byte/Word Protocol with PEC
Write Byte P rotocol Wri te Word Protocol
Bit Description Bit Description
1 Start 1 Start
2–8 Slav e Addres s - 7 bits 2–8 Slav e Addr es s - 7 bits
9 Write 9 Write
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 241
5—Intel® 6300ESB ICH
Read B yte/Word
Reading data is slightly more complicated than writing data. First the Intel® 6300ESB
ICH m ust wr it e a c o mma nd to t he sl av e dev i ce . Th en it must f ol l ow tha t co mman d w i th
a repeated start condition to denote a read from that device's address. The slave then
re turns 1 or 2 b yte s of data. So ft wa re mu st f orc e the I2 C_ EN bi t to 0 wh en r un ni ng th is
command.
When programmed for the read byte/word command, the Transmit Slave Address and
Devic e Command R egist ers are se nt. Data is rec eiv ed in to th e DATA0 on the r ead byte ,
and the DATA0 and DATA1 registers on the read word. The format of the protocol is
shown in Table 120 and Table 121.
10 Acknowledge from slave 10 Acknowledge from slave
11–18 Command c od e - 8 bits 11 –18 Command c od e - 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
20–27 Data Byte - 8 bits 20 –27 D a ta B yt e Low - 8 bits
28 Acknowledge from Slave 28 Acknowledge from Slave
29–36 PEC 29–36 Data Byte High - 8 bits
37 Acknowledg e from Slave 37 Acknowledge from slav e
38 Stop 38–45 PEC
46 A ck n owledge from slave
47 Stop
Tab l e 11 9. Wr ite By te/ W o rd Pr oto co l wi t h PEC
Write Byte Protocol W rite Word Protocol
Bit Description Bit Description
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
242 Order Number: 300641-004US
Table 120. Read Byte/Word Protocol without PEC
Read Byte Protocol Read Word Protocol
Bit Description Bit Description
1Start 1Start
2–8 Slave Addres s - 7 bits 2–8 Slave A ddress - 7 bits
9Write 9Write
10 Acknowledge fr om sla v e 10 Acknowle dge fr om slave
11–18 Command code - 8 bits 11–18 Command co de - 8 bits
19 Acknowledge fr om sla v e 19 Acknowle dge fr om slave
20 Re peated Start 20 Repeated Start
21–27 S lave A ddres s - 7 bits 21– 27 S lave Address - 7 bits
28 Read 28 Read
29 Acknowledge fr om sla v e 29 Acknowle dge fr om slave
30–37 Data from sl ave - 8 bits 30–37 D ata B yte L ow f rom slave - 8 bits
38 NOT acknowledge 38 Acknow le dge
39 Stop 39–46 Data Byte Hig h fr om slave - 8 bits
47 NOT acknowledge
48 Stop
Table 121. Read Byte/Word Protocol with PEC
Read Byte Protocol Read Word P rotocol
Bit Description Bit Description
1 Start 1 Start
2–8 Slave Address - 7 bits 2–8 Slave Address - 7 bits
9 Write 9 Write
1 0 Acknowledge fr om slave 10 A cknowl edg e from slave
11–18 Command code - 8 bits 11–18 Com mand code - 8 bit s
1 9 Acknowledge fr om slave 19 A cknowl edg e from slave
20 Repeated Start 20 Repeated Start
21–27 Slave Addres s - 7 bits 21–2 7 Slave Address - 7 bits
28 Read 28 Read
2 9 Acknowledge fr om slave 29 A cknowl edg e from slave
30–37 Data f rom sl ave - 8 bits 30–37 Data Byte Low from slave - 8 bits
38 Acknowledge 38 Acknowledge
39–46 PEC from slave 39–46 Data Byte High f rom slave - 8 bits
47 NOT Acknowledge 47 Acknowledge
48 Stop 48–55 PEC from slave
56 NOT acknowledge
57 Stop
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 243
5—Intel® 6300ESB ICH
Pro ce ss Ca l l
The pr oce ss cal l i s s o na med beca us e a com mand se nds d at a a nd w a it s f or t he s la v e t o
re t ur n a v a lu e d ep e nd ent on t h at d ata. T he protoc o l is si mp l y a W r it e Word followed b y
a Read Word, but without a second command or stop condition.
When programmed for the Process Call command, the Intel® 6300ESB ICH transmits
the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data
received from the device is stored in the DATA0 and DATA1 registers. The Process Call
command with I2C_EN set and the PEC_EN bit set produces undefined results.
Software must force either I2C_EN or PEC_EN to 0 when running this command. The
format of the protocol is shown in Table 122 and Table 123.
Note: Fo r process call command, the value written into bit 0 of the Transmit Slave Address
Register (SMBus I/O register, offset 04h) needs to be 0.
Ta ble 122. Process Call Protocol without PEC
Bit Description
1Start
2–8 Slave Address - 7 bits
9Write
10 Acknowled ge f rom Slave
11–18 Command code - 8 bits
19 Acknowled ge f rom sla ve
20–27 Data byte Low - 8 bits
28 Acknowled ge f rom sla ve
29–36 Data Byte High - 8 bits
37 Acknowled ge f rom sla ve
38 Re p eated Start
39–45 Slave Address - 7 bits
46 Read
47 Acknowled ge f rom sla ve
48–55 Data Byte Low from sl ave - 8
bits
56 Acknowledge
57–64 Data B y te Hi gh from slave -
8 bits
65 NOT acknowle d ge
66 Stop
Table 123. Process Call Protocol with PEC (Sheet 1 of 2)
Bit Description
1Start
2–8 Slave Address - 7 bits
9Write
10 Ack n owledge from S lave
11–18 Co mmand code - 8 bits
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
244 Order Number: 300641-004US
Blo c k R ead/ W rite
The Intel® 6300ESB ICH contains a 32-byte buffer for read and write data which may
be enabled by setting bit ‘1’ of the Auxiliary Control register at offset 0Dh in I/O space,
as opposed to a single byte of buffering. This 32-byte buffer is filled with write data
before transmission, and filled with read data on reception. I n the Intel® 6300ESB ICH,
the inte rr up t is generat ed only aft er a tran sm iss ion or r ece ptio n of 32 byt es , or when
the entire byte count has been transmitted/received.
This requires the Intel® 6300E SB ICH to che ck the byte count f iel d. Curr entl y, t he byte
count field is transmitted but ignored by the hardware as software will end the transfer
after all bytes it cares about have been sent or received.
For a Block Write soft ware must either force the I2C_EN bit or both the PEC_EN and
AAC bits to 0 when running this command.
SMBus mode: The block write begins wit h a slave address and a write condition. After
the command code the Intel® 6300ESB ICH issues a byte count describing how many
more bytes will follow in the message. When a slave had 20 bytes to send, the first
byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may
not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
By te reg ist er; the total dat a sent bei ng the v alue st ored in t he Da ta0 R egi ster. On b lock
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register.
The format of the Block Read/W rite protocol is shown in Table 124 and Table 125.
19 Ack n owle d g e from slave
20–27 Data byte Low - 8 bits
28 Ack n owle d g e from slave
29–36 Data Byte High - 8 bits
37 Ack n owle d g e from slave
38 Repeated Start
39–45 Slave Addre ss - 7 bits
46 Read
47 Ack n owle d g e from slave
48–55 Data Byte Low from slave - 8 bits
56 Acknowledge
57–64 Data Byte High from slave - 8 bits
65 Acknowledge
66–73 PEC from slave
74 NOT ack nowledge
75 Stop
Table 123. Process Call Protocol with PEC (Sheet 2 of 2)
Bit Description
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 245
5—Intel® 6300ESB ICH
I2C Mode: For Block Write, when the I2C_EN bit is set, the format of the command
changes slightly. The Intel® 6300E SB ICH will still send the number of bytes (on writes)
or receive the number of bytes (on reads) indicated in the DATA0 register. However, it
will not send the contents of the DATA0 register as part of the message.
l
Table 124. Block Read/Write Protocol without PEC
Block Write Protoc ol B loc k Read Protocol
Bit Description Bit Description
1 Start 1 Start
2–8 Slave Address - 7 bits 2–8 Slave Addre ss - 7 bits
9 Write 9 Write
10 A cknow le dge from slav e 10 Acknow ledge fr o m slav e
11–18 Command code - 8 bits 11–18 Com mand code - 8 bits
19 A cknow le dge from slav e 19 Acknow ledge fr o m slav e
20–27 Byte Count - 8 bits
(Skip this step when I2C_En bit
set) 20 Repeated Start
28 Acknowle dge from Slave
(Skip this step when I2C_EN bit
set) 21–27 Slave Address - 7 bits
29–36 Data Byte 1 - 8 bits 28 Read
37 A cknow le dge from Sla ve 29 Ackno wl edge fr o m slav e
38–45 Data By te 2 - 8 bits 30–37 Byte Count from slave - 8 bits
46 Acknowledge from slave 38 Acknowledge
... Data B y te s / S lave
Acknowledges... 39–46 Dat a Byte 1 fro m slave - 8 bits
... Data Byte N - 8 bits 47 A ck nowle d g e
... Acknowled g e from Slave 48–55 Data Byte 2 from slave - 8 bits
... Stop 56 Acknowledge
... Data Bytes from slave/
Acknowledge
... Data Byte N from slave - 8 bits
... NOT Acknowledge
... Stop
Table 125. Block Read/Write Protocol with PEC (Sheet 1 of 2)
Block Write Prot ocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
2–8 Slave address - 7 bits 2–8 Slave addres s - 7 bits
9 Write 9 Write
10 Ac kno w le dge from sla v e 10 Ackno w ledge fr om sla v e
11–18 Com mand code - 8 bit s 11–18 Com mand code - 8 bits
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
246 Order Number: 300641-004US
I2C Block Read
This command allows the Intel® 6300ESB ICH to perform block reads to certain I2C
devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing
mode only. However, this does not allow access to devices using the I2C “Combined
F orm at” th at has data by tes a fte r the a ddre ss. Typic all y the se da ta byte s corres po nd to
an offset (address) within the serial memory chips.
Note: This command is supported independent of the setting of the I 2C_EN bit . The I 2C R ead
command with the PEC_EN bit set produces undefined results. Software must force
both the PEC_EN and AAC bit to 0 when running this command.
For I2C Read command, the value written into bit 0 of the Transmit Slave Address
Register (SMBus I/O register, offset 04h) needs to be 0.
To support these devices, the Intel® 6300ESB ICH implements an I2C Read command
with the format: shown in Table 126.
19 Acknowledge from slave 19 Acknowledge from slave
20–27 Byte count - 8 bits
(Skip this step when I2C_En bit set) 20 Repeated start
28 Acknowle dge from slave
(skip this step when I2C_EN bit set) 21–27 Slave address - 7 bits
29–36 Data byte 1 - 8 bits 28 Read
37 Acknowledge from slave 29 Acknowledge from s lave
38–45 Data byte 2 - 8 bits 30–37 Byte count from slave - 8 bits
46 Acknowledge from slave 38 Acknowledge
... Data byte s/sl ave
Acknowledges 39–46 Data byte 1 from slave - 8 bits
... Data b y te N - 8 bits 47 Ackn owle d g e
... Acknowledge from slave 48–55 Data by te 2 from slave - 8 bi ts
... PEC - 8 bits 56 Acknowledge
... Acknowledg e from slave ... Data byte s from slave/acknowle d g e
... Stop ... Data byte N from slave - 8 bits
... Acknowledge
... PEC from sl ave - 8 bits
... NOT acknowledge
... Stop
Table 125. Block Read/Write Protocol with PEC (Sheet 2 of 2)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
Table 126. I2C Block Read Protocol (Sheet 1 of 2)
Bit Description
1Start
2-8 Slave Address - 7 bits
9Write
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 247
5—Intel® 6300ESB ICH
The Intel® 6300ESB ICH will continue readi ng data from the periphera l until t he NAK i s rec ei ved .
Block Write-Block Read Proces s Call
The Block Write-Block Read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has 6 bytes to send, the byte count field will have the v alue 6
(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be
zero.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a Read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be zero.
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
M 1 byte
N 1 byte
M + N 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the Block
Write-Block Read Process Call. Software must do a read to the command register
(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Note: There is no STOP condition before the repeated START condition, and a NACK signifies
the end of the read transfer.
Note: E32B bit in the Auxiliary Control register must be set when using this protocol.
1 0 Acknowl edg e fr om sla v e
11-18 Send DAT A1 register
1 9 Acknowl edg e fr om sla v e
20 Repeated Start
20-27 Slave Address - 7 bits
28 Read
2 9 Acknowl edg e fr om sla v e
30-38 Data Byte 1 f rom slave - 8 bits
39 Acknowledge
39-46 Data Byte 2 f rom slave - 8 bits
47 Acknowledge
... Data Bytes from slave/
Acknowledge
... Data Byte N from slave - 8 bits
... NOT Ac knowledge
... Stop
Tab l e 12 6. I2C Block Read Protocol (Sheet 2 of 2)
Bit Description
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
248 Order Number: 300641-004US
Table 127. Block Write-Block Read Process Call Protocol With/Without PEC
Bit Description
1Start
2-8 S lave Address - 7 bits
9Write
1 0 Acknow le dge fr om S la ve
11-18 Command code - 8 bits
1 9 Acknow le dge from slave
20-27 Data B yte Co unt (M ) - 8 bits
2 8 Acknow le dge fr om S la ve
29-36 Data B yte (1) - 8 bits
3 7 Acknow le dge from slave
38-45 Data B yte (2) - 8 bits
4 6 Acknow le dge from slave
……
Data B yte (M) - 8 b its
Ackn owledge from slave
Repeated Start
Slave Address - 7 bits
Read
Ackn owledge from slave
Data Byte Count (N) from slave – 8 bits
Ackn owledge fr om master
Data B yte (1) from slave – 8 bits
Ackn owledge fr om master
Data B yte (2) from slave – 8 bits
Ackn owledge fr om master
……
Data Byte Count (N) from slave – 8 bits
Acknowledge fr om master (Ski p if no PEC)
PEC from slave (Skip if no PEC)
NOT acknowledge
Stop
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 249
5—Intel® 6300ESB ICH
5.19.2.2 I2C Behavior
When the I2C_EN bit is set, the Intel® 6300ESB ICH SMBus logic will instead be set to
communicate with I2C devices. This forces the following changes:
1. The Process Call command will skip the Command code (and its associated
acknowledge).
2. The Block Write command will skip sending the Byte Count (DATA0).
In addition, the Intel® 6300ESB ICH will support the new I2C Read command. This is
independent of the I2C_EN bit.
Note: When oper ating in I2C m ode the Intel® 6300ES B ICH will not use the 3 2-byte buf fer fo r
block commands.
5.19.2.3 Heartbeat for Use with the External LAN Controller
The Heartbeat method allows the Intel® 6 300E SB IC H to send mes sages to an e xtern al
LAN Controller when the processor is otherwise unable to do so. I t uses the SMLINK I/F
between the Intel® 630 0ESB I CH and the external LAN Controller. The actua l Heartbeat
message is a Block Write. Only eight bytes are sent.
5.19.3 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The Intel® 6300ESB ICH must
continuously monitor the SMBDATA line. When the Intel® 6300ESB ICH is attempting
to drive the bus to a 1’ by letting go of the SMBDATA line, and it samples SMBDATA
low, then some other master is driving the bus and the Intel® 6300ESB ICH must stop
transferring data.
When the Intel® 6300ESB ICH sees that it has lost arbitration, the condi tion is called a
collision. The Intel® 6300ESB ICH will set the BUS_ERR bit in the Host Status Register,
and when enabled, generate an interrupt or SMI#. The processor is responsible for
restarti ng the transaction.
When the Intel® 6300ESB ICH is a SMBus master, it will drive the clock. When the
Intel® 6300ESB ICH is sending address or command as an SMBus master, or data
bytes as a master on writes, it will drive data relative to the clock it is also driving. It
will not start toggling the clock until the start or stop condition meets proper setup and
hold time. The Intel® 6300ESB ICH will also ensure minimum time between SMBus
transactions as a master.
Note: The Intel® 63 00ESB ICH su pp orts the s ame arbitr ati on protocol for both the SMBus an d
the System Management (SMLINK) interfaces.
5.19.4 Bus Timing
5.19.4.1 Clo ck Stretching
Some dev ice s may not b e able to hand le thei r cl ock togg lin g at the r ate tha t the Intel®
6300ESB ICH as an SMBus master would like. They have the capability of stretching
the low time of the clock. When the Intel® 6300ESB ICH attempts to release the clock
(a ll o w in g t h e cl oc k to g o h ig h) , t he c lock w il l r e ma in low for a n e x te n d ed p e r io d of ti me .
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
250 Order Number: 300641-004US
The Intel® 6300ESB ICH must moni tor th e SMBus clock lin e aft er it r ele ases the bus to
determine whether to enable the counter for the high time of the clock. While the bus is
still low, the high time counter must not be enabled. Similarly, the low period of the
clock may be stretched by an SMBus master when it is not ready to send or receive
data.
5.19.4.2 Bus Time Out (Intel® 6300ESB ICH as SMBus Master)
When there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
wil l time out. The Intel® 6300ESB ICH will discard the cycle, and set the DEV_ERR bit.
The time out minimum is 25 ms. The time-out counter inside the Intel® 6300ESB ICH
will start after the last bit of data is transferred by the Intel® 6300ESB ICH and it is
waiting for a response. The 25 ms will be a count of 800 RTC clocks.
5.19.5 Interrupts/SMI#
The Intel® 6300ESB ICH SMBus controller uses PIRQB# as its interrupt pin. However,
the system may alternatively be set up to generate SMI# instead of an interrupt, by
setting the SMBUS_SMI_EN bit.
Table 129 and Table 130 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that when more than one row is true
for a particular scenario then the results for all of the activated rows will occur.
Table 128. Enable for SMBALERT#
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI _EN (Host
Configurat ion
Register,
D31:F3:Offset 40h,
Bit 1)
SMBAL ERT_DI S
(Sla ve Command I/
O Register, Offs et
11h, Bit 2)
Result
SMBALERT#
asserted low
(always reported in
Host Status
Register, Bit 5)
XX XWake generated
X1 0
Slave SMI#
generated
(SMBUS_SMI_STS)
10 0
Interrupt
generated
Table 129. Enables for SMBus Slave Write and SMBus Host Events
Event INTREN (Host Control
I/O Register, Offs et
02h, Bit 0)
SMB_SMI_EN (Host
Configurat ion Register,
D31:F3:Offset 40h, Bi t1) Event
Slave Write to Wake/
SMI# Command XX
Wake generated when asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave Write to
SMLINK_SLAVE_SMI
Command XX
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
Any comb in at ion of
Host Sta tu s Reg ister
[4:1] a sserted
0XNone
1 0 Interrupt generated
11Host SMI# generated
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 251
5—Intel® 6300ESB ICH
5.19.6 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted,
the Int el® 6300E SB ICH may genera te an int erru pt, an SMI# or a wak e eve nt from S1
S4.
Note: Any event on SMBALERT# (regardless whether it is programmed as a GPIO or not),
causes the event message to be sent in “heartbeat mode.
5.19.7 SMBu s CR C Generation and C hecking
When the AAC bit is set in the Auxiliary Control register, the Intel ® 6300ESB ICH will
automatically calculate and drive CRC at the end of the transmitted packet for write
cycles, and will check the CRC for read cycles. It will not transmit the contents of the
PEC regis ter for CRC. The PEC bit must not be se t in the Ho st Cont rol regis ter when this
bit is set, or unspecified behavior will result.
When the read cyc le results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
5. 19.8 SMBus Slave Inter fa c e
The Intel® 6300ESB ICH’s SMBus Slave interface is accessed through the SMLINK[1:0]
signals. The SMBus slave logic will not generate or handle receiving the PEC byte and
will only act as a Legacy Alerting Protocol (Alert on LAN*) device. The slave interface
allows the Intel® 6300 ESB IC H t o deco de cy cles , and al lows a n ext ernal micro cont roll er
to perform specific actions. Key features and capabilities include:
Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify
Receive Slave Address register: This is the address that the Intel® 6300ESB ICH
decodes. A default value is provided so that the slave interface may be used
without the processor having to program this register.
Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller
Registers that the external microcontroller may read to get the state of the Intel®
6300ESB ICH. See Table 135.
Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or
SMI# due to the reception of a message that matched the slave address.
Bit 0 of t he Slave Status Register for the Host Notify command.
Table 130. Enables for the Host Notify Command
HOST_NOTIFY_INTREN
(S lav e Co ntr o l I /O
Register, Offset 11h, bit
0)
SM B_ SMI_EN ( H os t
Config Register,
D31:F3:Of f40h, Bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11 h, bit
1)
Result
0X0None
XX1Wake generated
1 0 X Interrupt generated
11X
Slave SMI# generated
(SMBUS_SMI_STS)
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
DS November 2007
252 Order Number: 300641-004US
B it 16 of the SMI Status R egis ter (Section 8.8.3.10, “SMI_STS—SMI Status Register ) for
all others.
Note: The external microcontroller should not attempt to access the Intel® 6300ESB ICH’s
SMBus slave logic until 1 second after both: RTEST# is high and RSMRST# is high.
When a master leav es th e clock and d ata bits of the SMLink inte rfac e at ‘1’ for 50 µs or
more in the middle of a cycle, the Intel® 6300ESB ICH slave logic’s behavior is
undefined. This is interpreted as an unexpected idle and should be avoided when
performing management activities to the slave logic.
Note: When an external microcontroller accesses the SMBus S lave Interface over the SMLink
a tr ans lati on in th e addres s is nee ded to ac commodate the le ast sig nif ican t bit us ed for
read/write control. For example, when the Intel® 6300ESB ICH slave address
(RCV_SLVA) is left at 44h (default), the external microcontroller would use an address
of 88h/89h (write/read).
5.19.8.1 Format of Slave Write Cycle
Th e exter nal mast er per form s By te W ri te comman ds to the I nte l® 6300 ESB IC H S MBu s
Slave I/F. The “Command” field (bits 11-18) indicate which register is being accessed.
The Data field (bits 20-27) indicates the value that should b e writ ten to that register.
The W rite Cycle format is shown in Table 131. Table 132 has the v a lu es as sociat ed wi th
the regis ters .
Table 131. Slave Write Cycle Format
Bits Description Driven by Comment
1 Start Con d ition External
Microcontroller
2–8 Sl ave Address - 7
bits External
Microcontroller Must match value in Receive Slave
Address register.
9Write External
Microcontroller Always 0
10 ACK Intel® 6300ESB
ICH
11–18 Command External
Microcontroller
This f i e ld indicates which registe r will be
accessed.
See Table 132 below for the re gi ste r
definitions
19 ACK Intel® 6300ESB
ICH
20–27 Register Data Extern al
Microcontroller See Table 132 be low for the regi ste r
definitions
28 ACK Intel® 6300ESB
ICH
29 Stop External
Microcontroller
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.
Ta bl e 13 2. S la v e W rite Re g is ter s
Register Function
0 Command Register. See Table 133 for legal values writte n to th is re gis te r.
1–3 Reserved
4 Data Message Byte 0
5 Data Message Byte 1
6–7 Reserved
8Fre quen cy Straps will be writte n on b its 3:0. Bits 7:4 should be 0, but will be
ignored.
9-FFh Reserved
NOTE: The e xt er nal microcontrolle r is re sp onsible to make sure that it doe s not up date the
contents of the data byte registers until they have been read by the system processor.
The Intel® 6300ESB ICH wi ll overw rite the ol d valu e wit h any new v alue rec eived. A r ace
condition is possible where the new value is being written to the re gister just at the time
it is being read . In te l® 6300ESB ICH will not atte mpt to cover this race condi tion (i.e .
unpredictable results in this case).
Table 133. Command Types (Sheet 1 of 2)
Command
Type Description
0Reserved
1
Wake/SMI#: Wake system if it is not already awake. If system is already
awake, then a n S M I# will b e gene rate d.
NOTE: The SMB_WA K_STS bit will be set by this command, even when the
system is already awake. The SMI handler should t hen clear this bit.
2Unconditional Powerdown: This command sets th e PWRBTNOR_S TS b it, an d
has the s ame effect as the Powerbutton Over ride occurring.
3Hard Reset Without Cycling: The will cause a ha rd reset o f the system (does
not include cy cling of the power supp ly). This is equiv alent to a write to the CF9h
register with bits 2:1 set to 1, but bit 3 set to 0.
4Hard Reset Sy stem: The will cause a hard reset of the system (including
cycl in g of the po we r su p p ly). This is equival en t to a write to the CF 9h re g iste r
with bit s 3:1 set to 1.
5
Disa ble the TCO Messa ges. This command will disable the Intel® 6300ESB
ICH from sending Heartbeat and Event messages (as described in
Section 5.12.4, “Heartbeat and Eve nt Rep orting through SMLink/SMbus”). Once
this command has been executed, Heartbeat and Event message reporting m ay
only be re enabled by assertion and deassertion of the RSMRST# signal.
6WD Reload: Reload watchd og time r.
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5.19.8.2 Format of Read Command
The ex ternal m aster pe rforms Byte Rea d commands to th e In tel® 6 300ES B ICH SM Bus
Slave I/F. The “Command” field (bits 11-18) indicate which register is being accessed.
The Data field (bits 30-37) contains the value that should be read from that register.
Table 134 shows the Read Cycle format. Table 135 shows the register mapping for the
data byte.
7 Reserved
8
SMLINK_SLV_S MI. W he n Inte l® 6300ESB ICH dete cts this co mma nd ty pe while
in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 8.9.8,
“TCO1_CNT TCO1 Control Register”). This command should only be used when
the system is in an S0 st ate. When the message is receiv ed during S1- S5 states,
the Intel® 6300ESB ICH acknowledges it, but the SMLINK_SLV_SMI_STS bit
does not ge t set.
NOTE: It is p oss ible that the syste m tran sitio n s out of the S0 st ate at the sam e
time that the SMLINK_SLV _S MI com man d is received. In this case, the
SMLINK_SLV _S MI _S TS b it ma y get se t bu t not se rv iced bef ore the
system goes to sleep. Once the system returns to S0, the SMI associated
with this bit would the n be generated. Software must be able to hand le
this scenario.
9-FFh Reserved
Table 133. Command Types (Sheet 2 of 2)
Command
Type Description
Table 134. Read Cycle Format (Sheet 1 of 2)
Bit Des criptio n Dr iven by : Comm ent:
1Start External
Microcontroller
2-8 Slave Address - 7 bits External
Microcontroller Must match value i n Receive Slave
Addres s regi ster.
9Write External
Microcontroller Always zero.
10 ACK Intel® 6300ESB
ICH
11-18 Co mman d code – 8
bits External
Microcontroller Indica te s which regi ste r is b e in g
accessed. See Table 135.
19 ACK Intel® 6300ESB
ICH
20 Repeated Start External
Microcontroller
21-27 Sl ave Address - 7 bits External
Microcontroller Must match value i n Receive Slave
Addres s regi ster.
28 Read External
Microcontroller Always one.
29 ACK Intel® 6300ESB
ICH
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30-37 Data Byte Intel® 6300ESB
ICH Value depends on register being
accessed. See Table 135.
38 NOT ACK External
Microcontroller
39 Stop Exte rnal
Microcontroller
Tab l e 13 5. D ata Va lu e s fo r Slav e Read Re gis te rs (Sh e et 1 of 2)
Registe
r Bit
sDescription
07:0Reserved.
12:0
Sys tem Power S t ate
000 = S0
001 = S1
010 = Reserved
011 = S3
100 = S4
101 = S5
110 = Reserved
111 = Reserved
17:3Reserved
2 3:0 Frequency Strap Register
27:4Reserved
3 5: 0 Wa tchdog Timer cur re nt value
37:6Reserved
40
1 = The Intruder Detect (INTRD_DET) bit is set. This ind icates that the syste m
cover ha s probabl y been opened.
41
1 = BT I Temperature Event occurred. This bit will be set when the Intel®
6300ESB ICH’s THRM# inp ut sign al is ac tive. Ne e d to take after p olarity
control.
4 2
Boot-Status. This bit wi ll be 1 whe n the pr ocess or does not fetch the first
instruction.
43
This bit will be set af ter the T CO timer times out a second time (Both TIMEOUT
and SECOND_TO_STS bits set).
46:4Reserved.
47
The bit will reflect the state of the GPI[11]/SMBALER T # signal, and will depend
on the GP_INV [11] bit. It does not matter if the pin is configured as GPI[11] or
SMBALERT#.
NOTE: W h e n the GP_IN V [11] bit is 1 then the value of re giste r 4 bi t 7 will
equal the level of the GP I[11]/S M B A LERT# pin (hig h = 1, low = 0).
NOTE: W h e n the GP_IN V [11] bit is 0 then the value of re giste r 4 bi t 7 will
equ al th e in v er s e o f t he l evel of t he GP I[ 11 ] /SMBALERT# pin (h i gh = 1 ,
low = 0).
5 0
Unprogrammed FWH bit. This bit wi ll be 1 to ind icate that the first BIOS f e tch
returned FFh, which indicates that the FWH is probably blank.
51Battery Low Status. ‘1’ when the BATLOW# pin is a ‘0’.
52
CPU Po wer Fa ilu r e Stat u s : ‘1’ whe n the CPUPWR_FLR bit in the
GEN_PM CON _2 r egist er is se t .
Table 134. Read Cycle Format (Sheet 2 of 2)
Bit D e s cr iption Driven by : Com ment :
Intel® 6300ESB ICH—5
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Warning:The external microcontroller is respo nsible to make sure that it does not read
the cont ents o f the var ious mess age re g ister s u nti l the y hav e be e n w ri tten by
th e system processor. The Intel ® 6300ESB ICH will overwrite the old value
with any ne w value received. A ra ce condition is possible where the new val ue
is bei ng written to the register just at the time it is being read. The Intel®
63 00ESB IC H w i ll n ot attemp t to cove r th i s race condition ( i.e., unpre d icta ble
results).
5.19.8.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit -
Address - Write bit sequence. When the Intel® 6300ESB ICH detects that the address
matches the value in the Receive Slave Address register, it will assume that the
protocol is always followed and ignore th e Write bit (bit 9) and signal an Acknowledge
during bit 10 (See Table 131 and Table 134). In other words, when a Start - Address -
Read occurs (which is illegal for SMBus Read or Write protocol), and the address
ma tch e s th e In t el® 6300ESB ICH’s Slave Address, the Intel® 6300ESB ICH will still
grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start - Address -
Read sequence beginning at bit 20 (See Table 134). Once again, when the Address
ma tch e s th e In t el® 6300ESB ICH’s Receive Slave Address, it will assume that the
protocol is followed, ignore bit 28, and proceed with the Slave Read cycle.
Note: An external microcontroller must not attempt to access the Intel® 6300ESB ICHs
SMBus Slave logic until at least 1 second after both RTC RST# and RSMRST# are
deasserted (high).
5.19.8.3 Format of Host Notify Command
The Intel® 6300ESB ICH tracks and responds to the standard Host Notify command as
specified in the SMBus 2.0 specification. The host address for this command is fixed to
0001000b. When the Intel® 6300ESB ICH already has data for a previously-received
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NO TIFY_STS bit), it will NACK following the host address byte of
the protocol. This allows the host to communicate non-acceptance to the master and
retain the host notify address and data values for the previous cycle until host software
comp let el y ser vic es the in ter rup t.
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 136 shows the Host Notify format.
57:3Reserved
67:0
Contents of the Message 1 regi ster. See Sect ion 8.9.1 0, “TCO_MESSAGE1 and
TCO_MESSAGE2 Registers”.
77:0
Contents of the Message 2 regi ster. See Sect ion 8.9.1 0, “TCO_MESSAGE1 and
TCO_MESSAGE2 Registers”.
87:0
Contents of the WDSTATUS register. See Section 8.9.11, “Offset TCOBASE +
OEh: TCO_WDSTATUSTCO2 Control Register”.
9 – FFh 7:0 Reserv ed
Table 135. Data Values for Slav e Read Registers (Sheet 2 of 2)
Registe
r Bit
sDescription
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5.20 AC’97 Controller Functional Description
(Audio D31:F5, Modem D31:F6)
5.20.1 Overview
Note: All references to AC’97 in this document refer to the Au di o Cod ec 97 C om po n en t
Specification, Version 2.2. For further information on the operation of the AC-link
protocol, please see the AC 97 specification.
The Intel® 6300ESB ICH AC’97 controller features include:
Independent (FDX) channels for mono Line in and out.
Supports 16 bit samples.
Multiple sample rates up to 48 KHz
Supports dual codec implementations for audi o in dock
Supports read/write access to all Primary and Secondary AC'97 registers
Supports low latency access to 16 GPIO and wake up event status bits.
Note: The AC’97 R ev 2.0 spec. defines the following features which are NOT supported by the
Intel® 6300ESB ICH:
Support for optional double rate sampling (n+1 sample for PCM L, R and C)
Support for 18 and 20 bit sample lengths
Handset channels (In and Out)
Dual Audio Codec support
Table 136. Host Notify Format
Bit Description Driven by: Comment
1 Start External Master
2–8 SMBus Host Address - 7
bits External Master A lways 0001_000
9 Write External Master Always zero.
10 ACK (or NACK) Intel® 6300ES B ICH Intel® 6300ESB ICH NACKs when
HOST_NOTIFY _STS i s 1.
11–17 Device Address – 7 bits External Maste r Indicates the address of the
master; loaded i nto the No tify
Device A dd r e ss Regist er.
18 Unused - Always 0 External Master 7-b it-only ad dr es s; this bit is
inserted to complete the byte
19 ACK Intel® 6300ESB ICH
20–27 Data Byte Low - 8 bits Exter nal Master Load e d into the Notify Data Low
Byte Regist er.
28 ACK Intel® 6300ESB ICH
29–36 Data Byte High - 8 bits External Master Load e d into the Noti fy Data Hig h
Byte Regist er.
37 ACK Intel® 6300ESB ICH
38 S top External Ma ster
Intel® 6300ESB ICH—5
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Table 137 shows a detailed list of features supported by the Intel® 6300ESB ICH AC’ 97
digital controller.
.
Table 137. Features Supported by Intel® 6300ESB ICH (Sheet 1 of 2)
Feature Description
System
Interface
Isochrono u s low la te n cy bus ma st e r me mory int e rf a ce
Scatte r/g a the r support for word -a lig ne d buf fers in me mory
(all mono or stereo 20-bit and 16-bit data types ar e supported, no 8-bit
data types are supported)
Dat a buffe r size in system memory f rom 3 to 65535 samples per input
Data buff e r size in system me mory f rom 0 to 65535 samples per output
Inde pendent PCI aud io and modem f unctio ns with co nfiguration and IO
spaces
A C’9 7 cod ec registers are sh adowed in system m emory through driver.
A C’ 97 codec reg ister acce sse s are serialized thr o ugh semap h ore bi t in PCI
IO space (n e w a ccesses are not a llowed wh ile a prior ac ce ss is still in
progress).
Power
Management Power management through PCI Po we r Manag ement
PCI Audio
Function
Read / wr ite access to aud io cod ec re gisters 00h-3Ah and vendor re gisters
5Ah-7Eh
20-bit stereo PCM output, up to 48 KHz (L,R, Ce nte r, Sub-woof er, L-r ea r
and R-re ar channels on slots 3,4,6 ,7,8,9,10,11)
16-bit stereo PCM input, up to 48 KHz (L,R cha nnels on slots 3,4)
16-b it mono mic in w/ or w/o mono mix, up to 48 KH z (L, R cha n ne l, slots
3,4) (mono mix supports mono hardware AEC reference for spe akerphone)
16-bit mono PCM input, up to 48 KHz from dedicated mic ADC (slot 6)
(supp orts speec h re cognition or ste re o h ard wa re A E C re f for
speakerphone)
Du rin g cold re se t A C_RS T# is held low u ntil a f te r POS T and software
de asserti on of AC_R ST# (su pports passive PC_BEE P to s peaker c onnec ti on
during POST).
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Note: T hro ughout thi s d ocu ment, ref ere nces to D31:F 5 i ndi ca te tha t t he audi o func ti on ex ists
in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function
exists in PCI Device 31, Function 6.
Note: Throughout this document, references to tertiary, third, or triple codecs refer to the
third codec in th e s ys tem connec ted to the AC_SDI N[2] pin. The A C’97 2.2 spec ificati on
refers to non-primary codecs as multiple secondary codecs. To avoid confusion and
excess verbiage this EDS refers to it as the third or tertiary codec.
PCI Modem
function
Read/write access to modem codec registers 3Ch-58h and vendor registers
5Ah-7Eh
16-bit mono mo dem line 1 outp ut an d input, up to 48 KHz (slot 5)
Low latency GPIO[15:0] via hard wired update between slot 12 and PCI IO
register.
Programmable PCI interrupt on modem GPIO input changes via slo t 12
GPIO_INT
SCI event generation on AC_SDIN[2:0] wake-up signals
AC-link
AC’97 2.0 compliant AC-link interface
Variable s amp le rate output sup p ort through AC’97 SLOTREQ protocol
(slots 3,4,5,6,7,8,9,10,11)
Variable sample r ate input sup port throug h monitoring of slot valid tag bits
(slots 3,4,5,6)
3.3 V digital operation mee ts A C’ 97 2.2 D C switching le vels
AC-lin k IO drive r ca p ability meets AC’97 2.2 triple codec spec ifi ca tions
Codec r egister stat us re ads must be returned w ith dat a i n t he n ex t AC-l in k
frame, per AC’97 2.2 spec.
Multiple Cod e c
Tripl e codec addressing: All AC’9 7 Audio codec register accesses are
addressable to codec ID 00 (primary), c odec ID 01 (secondary), or codec
ID 10 (tertiary).
Modem codec addressing: Al l AC’97 Modem codec register accesses are
add r e ssable to codec ID 00 ( p rimary) or cod ec ID 01 (se con d a ry).
Tr ipl e c od ec re ce ive cap a b ility th roug h A C_S DIN[2:0] pin s
(AC_SD IN [2:0] frames are internal ly validated , synch’d, and OR’d
depending on the Steer Enable bit status in the SD M register)
A C_SDIN map ping to DMA engine ma p p ing capab ility al lows for
simultaneous input from three different audio codecs.
NOTES:
1. Audio Codec IDs are remap p a b le and not limite d to 00,01,10
2. Modem Codec IDs are r emappable and limited to 00,01
3. When using multiple codecs, the Modem Codec must be ID 01.
Table 137. Features Supported by Intel® 6300ESB ICH (Sheet 2 of 2)
Feature Description
Intel® 6300ESB ICH—5
Intel® 6300ESB I/O Controller Hub
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5.20.1.1 PCI Power Management
This Po wer Management section applies for all AC’97 controller functions. After a p ower
management event is detected, the AC’97 controller will wake the host system. The
sections below describe these events and the AC’97 controller power states.
Device Power S tates
The AC’97 controller supports D0 and D3 PCI Power Management states. Notes
regarding the Intel® 6300ESB ICH AC’97 controller implementation of the Device
States:
1. Th e AC’97 controller ha rdware do es n ot inheren tly co nsume an y more power when
it is in the D0 state than it does in D3 state. However, software may halt the DMA
engine prior to entering these low power states such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented AC’97 controller features are enabled.
3. In D3 state, accesses to the AC’97 controller memory-mapped or I/O range will
result in master abort.
4. In D3 st ate, the AC’97 controller interrupt must never assert for any reason. The
internal PME# signal is used to signal wake events, etc.
5. When the Device Power State field is written from D3HOT to D0, an i nterna l reset is
generated.
6. AC’97 STS bit will be set only when the audio or modem resume events were
detected and their respective PME enable bits were set.
7. GPIO Status change interrupt no longer has a direct path to AC97 STS bit. This will
cause a wake up event only when the modem controller was in D3.
8. Resume events on AC_SDIN[2:0] will cause resume interrupt status bits to be set
only if their respective controllers are not in D3.
9. Edge detect logic will prevent the interrupts from being asserted in case AC’97
controller is switched from D3 to D0 after a wake event.
10.Once the interrupt status bits are set, they will cause PIRQB# if their respective
enable bits were set. One of the audio or the modem drivers will handle the
interrupt.
5.20.2 AC- L ink Ov erview
Figure 23. Intel® 6300ESB ICH Based AC’97 Controller Connection to Companion
Codec(s)
Audio In (Record)
Audio Out (Playback)
Modem
Handset
Mic.
PC
Intel® 63 00ESB I/O Controller Hub
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5—Intel® 6300ESB ICH
The Intel® 6300ESB ICH is an AC’97 2.0 compliant controller that communicates with
companion codecs through a digital serial link called the AC-link. All digital audio/
modem streams and command/status information is communicated over the AC-link.
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and
output data streams, as well as control register accesses, employing a time division
multiplexed (TDM) scheme. The AC -link architecture provides for data transfer through
individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing
and 12 incoming data streams, or slots. The architecture of the Intel® 6300ESB ICH
AC-link allows a maximum of three codecs to be connected. Figure 24 shows a three
codec topology of the AC-link for the Intel® 6300ESB ICH.
The AC'97 modem controller is a separate PCI function. However, the AC'97 modem
contr oller is implemented in the same logical unit as the AC'97 audio functions. There
are registers declared in the audio function which contain modem information - these
registers are also visible in the modem IO space, but are implemented as a single
register.
The AC-link consists of a five signal interface between the controller and codec.
Table 138 indicates the AC-link signal pins on the Intel® 6300ESB ICH and their
associated power wells.
Figure 24. AC’97 2.2 Controller-Codec Connection
Intel® 6300ESB ICH—5
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Intel® 6300ESB ICH core well outputs may be used as strapping options for the Intel®
6 300ESB ICH, sampled during system reset. These signals may have weak pullups/
pulldowns on them, however this will not interfere with link operation. Intel® 6300ESB
ICH inputs integrate weak pulldowns to prevent floating traces when a seconda ry and/
or tertiary codec is not attached. When the Shut Off bit in the control register is set, all
buffers will be turned off and the pins will be held in a steady state, based on these
pullups/pulldowns.
BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the
necessary clocking to support the twelve 20-bit time slots. AC-link serial data is
transitioned on each rising edge of BIT_CLK. The receiver of AC-link data samples each
serial bit on the falling edge of BIT_CLK.
When BIT_CLK makes no transitions for four consecutive PCI clocks, the Intel®
6300ES B ICH ass umes t he pri mary cod ec i s n ot pres ent o r not work ing . It sets bi t 28 of
the Global Status Register (I/O offset 30h). All accesses to codec registers with this bit
set will return data of FFh to prevent system hangs.
Synchronization of all AC-link data transactions is signaled by the AC’97 controller
through the AC_SYNC signal, as shown in Figure 25. The primary codec drives the
seri al bit clo ck ont o the AC-l ink , whic h the AC’9 7 contr olle r then qua lif ies with the
AC_SYNC signal to construct data frames. AC_SYNC, fixed at 48 KHz, is derived by
dividing down BIT_CLK. AC_SYNC remains high for a total duration of 16 BIT_CLKs at
the beginning of each frame. The portion of the frame where AC_SYNC is high is
defined as the tag phase. The remainder of the frame where AC_SYNC is low is defined
as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.
The Intel® 6300ESB ICH has three AC_SDIN pins allowing a single, dual, or triple codec
configuration. When multiple codecs are connected, the primary, secondary, and
tertiary codecs may be connected to any AC_SDIN line. The Intel® 6300ESB ICH does
Table 138. AC’97 Signals
Si gn al Name Type P ower Well Des crip tion
AC_RESET# Outp u t Resume Ma ster hard ware reset
AC_SYNC Output Core 48 KHz fixed rate sample sync
AC_ BIT_CLK Input Core 12.288 MHz Seri al data cl ock
AC_SDOUT Output Core Serial output data
AC_SDIN 0 Input Resume Serial input data
AC_SDIN 1 Input Resume Serial input data
AC_SDIN 2 Input Resume Serial input data
NOTE: Power well vo lta g e level s are 3.3 V.
Figure 25. AC-Link Protocol
SYNC
BIT_CLK
SDIN
slot(1)
Tim e Slot "Valid"
Bits
20.8uS
(48 KHz)
Slot 1 Slot 2
0
19
0
19
0
19
0
Slot 3 Slot 12
81.4 nS
12.288 M Hz
slot(2)
"0"
"0"
"0"
slot(12)
("1" = time slot contains valid PC M
data)
19
Codec
Ready
E nd of previou s
Au di o Frame
Tag Phase Data Phase
Intel® 63 00ESB I/O Controller Hub
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not distinguish between codecs on its AC_SDIN[2:0] pins, however the registers do
distinguish between AC_SDIN[0], AC_SDIN[1], and AC_SDIN[2] for wake events, etc.
When using a Modem Codec it is recommended to connect it to AC_SDIN[1].
See your Platform Des ign Guide for a matrix of valid codec configurations.
The Intel® 6300ESB ICH d oes not s uppo rt opti ona l test modes as outl i ned in the AC’97
specification.
5.20.2.1 AC-link Output Frame (SDOUT)
A new output frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the
time when both sides of AC-link are aware of the start of a new frame. On the next
rising edge of BIT_CLK, the Intel® 6300ESB ICH transitions SDOUT into the first bit
position of slot 0, or the valid frame bit. Each new bit position is presented to the AC-
link on a rising edge of BIT_CLK, and subsequently sampled by the codec on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time
aligned.
The output frame data phase corresponds to the multiplexed bundles of all digital
output data targeting codec DAC inputs and control registers. Each output frame
supports up to twelve outgoing data time slots. The Intel® 6300ESB ICH generates 16
or 20 bits and stuffs remaining bits with zeros.
The output data stream is sent with the most significant bit first, and all invalid slots
are stuffed with zeros. When mono audio sample streams are output from the Intel®
6300ESB ICH, software must ensure both left and right sample stream time slots are
filled with the same data.
5.20.2.2 Output Slot 0: Tag Phase
Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein
each bit conveys a valid tag for its corresponding time slot within the current frame. A
one i n a g iv en bit pos iti on o f sl ot 0 indic ates tha t the c orr esp ondi ng ti me s lot wi th in the
current frame has been assigned to a data stream and contains valid data. When a slot
is tagged invalid with a zero in the corresponding bit position of slot 0, the Intel®
6300ESB ICH stuffs the corresponding slot with zeros during that slots active time.
Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of
the entire frame. When the valid frame bit is set to one, this indicates that the current
frame contains at least one slot with valid data. When there is no transaction in
progress, the Intel® 6300ESB ICH will deassert the frame valid bit. Note that after a
write to slot 12, that slot will always stay valid, and therefore the frame valid bit will
remain set.
The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding
twelve time slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to
distinguish between separate codecs on the link.
Using the valid bits in the tag phase allows data streams of differing sample rates to be
transmitted across the link at its fixed 48 KHz frame rate. The codec may control the
output sample rate of the Intel® 6300ESB ICH using the SLOTREQ bits as described in
the AC’97 specification.
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5.20.2.3 Output Slot 1: Command Address Port
The command port is used to control features and monitor status of AC‘97 functions
including, but not limited to , mixer settings and power management.
The control interface architecture supports up to 64 16-bit read/write registers,
addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are
valid.
Output frame slot 1 communicates control register address, and write/read command
information.
In the case of the multiple codec implementation, accesses to the codecs are
differentiated by the driver using address offsets 00h7Fh for the primary codec,
address offsets 80hFEh fo r the se c ondary co de c, and add r es s off s et s 100 h17Fh for
the tertiary codec. The differentiation on the link, however, is done through the codec
ID bits.
5.20.2.4 Output Slot 2: Command Data Port
The command data port is used t o deliver 16-bit control register write data in t he event
that the current command port operation is a write cycle as indicated in slot 1, bit 19.
When the current command port operation is a read, the entire slot time stuffed with
zeros by the Intel® 6300ESB ICH. Bits [19:4] contain the write data. Bits [3:0] are
reserved and are stuffed with zeros.
5.20.2.5 Output Slot 3: PCM Playback Left Channel
Output frame slot 3 is the composite digital audio left playback stream. Typically this
slot is composed of standard PCM (.wav) output samples digitally mixed by the host
pr oc esso r. The Intel ® 6300ESB ICH transmits sampl e streams of 16 bits or 20 bi ts and
stuffs remaining bits with zeros.
Data in output slots 3 and 4 from the Intel® 6300ESB ICH should be duplicated by
software when there is only a single channel out.
5.20.2.6 Output Slot 4: PCM Playback Right Channel
Output frame slot 4 is the composite digital audio right playback stream. Typically this
slot is composed of standard PCM (.wav) output samples digitally mixed by the host
processor. The Intel® 6300ESB ICH transmits sample streams of 16 or 20 bits and
stuffs remaining bits with zeros.
Data in output slots 3 and 4 from the Intel® 6300ESB ICH should be duplicated by
software when there is only a single channel out.
5.20.2.7 Output Slot 5: Modem Codec
Output frame slot 5 contains modem DAC data.
The modem DAC output supports 16-bit resolution. At boot time, when the modem
codec is supported, the AC’97 controller driver determines the DAC resolution. During
normal runtime operation the Int el® 6300ESB ICH stuffs trailing bit positions within
t his time slot with zeros.
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5.20.2.8 Output Slot 6: PCM Playback Center Front Chann e l
When set up for 6-channel mode, this slot is used for the front center channel. The
form at is th e s ame as Sl ots 3 and 4. When no t se t up for 6- cha nne l mode , thi s chan nel
will always be stuffed with zeros by Intel® 6300ESB ICH.
5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear
Channels
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and
Right channels. The format for these two channels are the same as Slots 3 and 4.
5.20.2.10Output Slot 9: Playback Sub Woofer Channel
When set for 6-channel mode, this slot is used for the Sub Woofer. The format is the
same as Slot three. When not set up for 6-channel mode, this channel will always be
stuffed with zeros by Intel® 6300ESB ICH.
5.20.2.11Output Slots 1 0-11: Reserved
Output frame slots 10-11 are reserved and are always stuffed with 0s by the Intel®
6300ESB ICH AC’97 controller.
5.20.2.12Output Slot 12: I/O Control
Sixteen bits of DAA and GPIO control (output) and status (input) have been directly
assigned to bits on slot 12 in order to minimize latency of access to changing
conditions.
The value of the bits in this slot are the values written to the GPIO control register at
offset 54h and D4h (in the case of a secondary codec) in the modem codec I/O space.
The following rules govern the usage of slot 12.
1. Slot 12 is marked invalid by default on comin g out of AC-link reset, and will remain
invalid until a register write to 54h/D4h.
2. A write to offset 54h/D4h in codec I/O space will cause the write data to be
transmitted on slot 12 in the next frame, with slot 12 marked valid, and the
address/data information to also be transmitted on slots 1 and 2.
3. After the fi rst write to offset 54h/D4h, slot 12 remains valid for all follo wing frames.
The data t ransmitted on slot 12 is the data last written to offset 54h/D4h. Any
subsequent write to the register will cause the new data to be sent out on the next
frame.
4. Slot 12 will get invalidated after the following events:
PCI reset, AC'97 cold re set, warm re set, and hence a wake fr om S 3, S 4, or S 5.
Slot 12 will rem ain invalid u ntil th e ne xt wr ite to of fs et 54h/D4h.
5.20.2.13AC-Lin k Input Frame (SD IN)
Ther e are three AC_SD IN lines on the Intel ® 6300ESB ICH for use with up to three
codecs. Each AC_SDIN pin may have a codec attached. The input frame data streams
correspond to the multiplexed bundles of all digital input data targeting the AC’97
controller. As in the case for the output frame, each AC-link input frame consists of
twelve time slots.
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A new audio input frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks
t he ti me wh en both s ides of A C -li nk are aw are o f th e sta rt of a n ew a ud io f r ame. O n the
next ri s ing ed ge of BIT_C L K, the co dec tra nsit ions A C_SDI N into the fi rst bi t p osition of
slot 0 (codec ready bit). Each new bit position is presented to AC-link on a rising edge
of BIT_CLK, and subsequently sampled by the Intel® 6300ESB ICH on the following
falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDIN data stream must follow the AC’97 specification and be MSB justified wit h all non-
valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros.
AC_SDIN data is sampled by the Intel® 6300ESB ICH on the falling edge of BIT_CLK.
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5.20.2.14Input Slot 0: Tag Phase
Input slot 0 consists of a codec ready bit (bit 15), and slot valid bits for each
subsequent slot in the frame (bits [14:3]).
The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is
ready for register access (digital domain). When the codec ready bit in slot 0 is a zero,
the codec is not ready for register access. When the AC-link codec ready bi t is a 1, it
indicates that the AC-link and codec control and status registers are in a fully
operational state. The codec ready bits are visible through the Global Status regist er of
the Intel® 6300ESB ICH. Software must further probe the Powerdown Control/Status
register in the codec to determine exactly which subsections, when any, are ready.
Bits [14:3] i n slot 0 indi cate which slots of the inp ut str eam to the Int el® 6300 ESB ICH
contain valid data, just as in the output frame. The remaining bits in this slot are
stuffed with zeros.
5.20.2.15Inpu t Slot 1: Status Address Port/Slot Request Bits
The status port is used to monitor status of codec functions including, but not limited
to, mixer settin gs and po wer manage men t.
Slot 1 must echo the control register index, for historical reference, for the data to be
returned in slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in
slot 0.
For variable sample rate output, the codec examines its sample rate control registers,
the state of its FIFOs, and the incoming SDOUT tag bits at the beginning of each audio
output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits
asserted during the current audio input frame signal which output slots require data
from the controller in the next audio output frame. For fixed 48 KHz operation the
SLOTREQ bits are always set active (low) and a sample is transferred each frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid
data is present or not.
Table 139. Input Slot 1 Bit Definitions
Bit Description
19 Reserv ed (S e t to zero)
18:1
2Control Register Index (Stuffed with zer os when tagged as invalid)
11 Slot 3 Request: PCM Left Channel(1)
10 Slo t 4 Request: PCM Right Channe l(1)
9 Slot 5 Request: Mod e m Line 1
[8:2
}Slot 6-12 Request: Not Implemented
1:0 Reserved (Stuffed with zeros)
NOTE: Slot 3 Request and Slot 4 Request bits must be the same value, i.e. set or cleared in
tandem. This is also true for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and
Slot 9 Request bits.
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As shown in Table 139, slot 1 delivers codec control register read address and multiple
sample rate slot request flags for all output slots of the controller. When a slot request
bit is set by the codec, the controller will return data in that slot in the next output
frame. Slot request bits for slots 3 and 4 are always set or cleared in tandem, i.e. both
are set or cleared.
When set, the input slot 1 tag bit only pertains to Status Address Port data from a
previous read. SLOTREQ bits are always valid independent of the slot 1 tag bit.
5.20.2.16Input Slot 2: Status Data Port
The status data port receives 16-bit control register read data.
Bit [19:4]: Control Register Read Data
Bit [3:0]: Reserved.
5.20.2.17Input Slot 3 : PCM Record Left Channel
Input slot 3 is the left channel input of the codec. The Intel® 6300ESB ICH supports
16-bit sample resolution. Samples transmitted to the Intel® 6300ESB ICH must be in
left/right channel order.
5.20.2.18Input Slot 4: PCM Record Right Channel
Input slot 4 is the right channel input of the codec. The Intel® 6300ESB ICH supports
16-bit sample resolution. Samples transmitted to the Intel® 6300ESB ICH must be in
left/right channel order.
5.20.2.19Input Slot 5: Modem Line
Input slot 5 contains MSB justified modem data. The Intel® 6300ESB ICH supports 16-
bit sample resolution.
5.20.2.20Input Slot 6: Optional Dedicated Microphone Record Data
Input slot 6 is a third PCM system input channel available for dedicated use by a
microp hone. This input channel supplements a true stereo output which enables more
precise echo cancellation algorithm for speakerphone applications. The Intel® 6300ES B
ICH supports 16-bit resolution for slot 6 input.
5.20.2.21Input Slots 7-11: Reserved
Input frame slots 7-11 are reserved for future use and should be stuffed with zeros by
the codec , per the AC’97 specifi ca tion.
5.20.2.22Input Slot 12: I/O Status
The status of the GPIOs configured as inputs are to be returned on this slot in every
frame. The data returned on the latest frame is accessible to software by reading the
register at offset 54h/D4h in the codec I/O space. Only the 16 MSBs are used to return
GPI status. In order for GPI events to cause an interrupt, both the 'sticky' and
'interrupt' bits must be set for that particular GPIO pin in regs 50h and 52h. Therefore,
the interrupt will be signalled until it has been cleared by the controller, which may be
much longer tha n one fram e.
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Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data
from the most recent slot 12 is returned on reads from offset 54h/D4h.
5.20.2.23Register Access
In the Intel® 6300ESB ICH implementation of the AC-link, up to three codecs may be
connected to the SDOUT pin. The following mechanism is used to address the primary,
secondary, and tertiary codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits
[18:12] of slot 1 are used for the register index. For I/O writes to the primary codec,
the v alid bits [14:13] for sl ots 1 a nd 2 mus t be set in slot 0, as shown in Table 140. Slot
1 is used to transmit the register address, and slot 2 is used to transmit data. For I/O
reads to the primary codec, only sl ot 1 shoul d be valid since only an address is
transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1
and 2 valid bits ar e set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as
described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot
0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non zero value. This
allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and
bit s [1:0] of s lo t 0 to determin e when the ac ce ss is dire ct ed to the sec ondary or ter tiary
codec. When the register access is targeted to the secondary or tertiary codec, slot 1
and 2 will contain the address and data for the register access. Since slots 1 and 2 are
marked invalid, the primary codec will ignore these accesses.
When accessing the codec registers, only one I/O cycle may be pending across the AC-
link at any time. The Intel® 6300ESB ICH implements write posting on I/O writes
acros s the A C-li nk (i .e. , wri tes across the link are ind icated as compl et e bef ore they are
actually sent across the link). In order to prevent a second I/O write from occurring
befor e the first on e i s compl ete, softw are must moni tor the CAS b it i n the Co de c Ac ce ss
Semaphore register which indicates that a codec access is pending. Once the CAS bit is
cleared, then another codec access (read or write) may go through. The exception to
this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with
the most recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary,
secondary and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a
normal register access. Slot 12 is also updated immediately to reflect the data being
written.
The co ntr ol l er wi ll not issu e b a ck t o bac k rea ds . It must g e t a re sp on se to th e f i rst re a d
before issuing a second. In addition, codec reads and writes are only executed once
across the link, and are not repeated.
Tab l e 14 0. O ut pu t Tag Slo t 0
Bit Primary
Access
Example
Secondary
Access
Example Description
15 1 1 Frame Vali d
14 1 0 Sl ot 1 Valid, Co m ma nd Address bit (Pri ma ry c o dec
only)
13 1 0 S lot 2 Val id, Command Data bit (Primary codec on ly )
12:
3X X Slot 3-12 Valid
2 0 0 Reserved
1:0 00 01 Codec ID (00 reserved for primary ; 01 ind icate
se con d a ry ; 10 in d ica te terti a ry ) .
5—Intel® 6300ESB ICH
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5.20.3 AC-Link Low Po wer M o de
The AC-link signals may be placed in a low-power mode. When the AC’97 Powerdown
Register (26h), is programmed to the appropriate value, both BIT_CLK and AC_SDIN
will be brought to, and held at a logic low voltage level.
BIT_CLK and AC_SDIN transition low immediately, within the maximum specified time,
after a write to the Powerdown Register (26h) with PR4 enabled. When the AC’97
controller driver is at the point where it is ready to program the AC-link into its low-
power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output
frame. At this point in time it is assumed that all sources of audio input have been
neutralized.
Th e AC’ 97 c ontrol ler a lso dr iv e s AC_S Y NC, a nd SDO UT lo w a ft er p rog ra mm in g AC ’9 7 to
this low power, halted mode.
Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must
be used to bring the AC-link to the activ e mode since normal output and input frames
cannot be communicated in the absence of BIT_CLK. Once in a low-power mode, the
Intel® 6300ESB ICH provides three methods for waking up the AC-link; external wake
event, cold reset and warm reset.
Note: Before entering any low-power mode where the link interface to the codec is expected
to be powered down while the rest of the system is awake, the software must set the
“Shut Off” bit in the control register to ensure that the Intel® 6300ESB ICH controller
does not drive the output pins of the link.
5.20.3.1 Externa l Wake Event
Codecs may signal the controller to wake the AC-link, and wake the system using
AC_SDIN.
Figure 26. AC-Link Powerdown Timing
S DOUT
TAG
SYNC
BIT_CLK
Write to
0x20
Data
PR4
slot 12
prev. fram e
TAG
slot 12
prev. fram e
SDIN
Note:
B IT_C LK n o t to s ca le
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The minimum AC_SDIN wake up pulse width is 1 us. The rising edge of SDATA_IN
(SDATA_IN(0) or SDATA)IN(1) for split partitioned implementation) causes the audio
controller to sequence through its AC-link “warm reset” and signal PME# to the
systems ACPI controller. The primary codec must wait to sample AC_SYNC high and
low before restarting BIT_CL K as diagrammed in Figure 6-24. The codec that signaled
th e wake ev ent mu st ke ep its AC _SDI N h igh unt il it ha s sampl ed AC_SY NC ha ving go ne
high, and then low.
The AC-link protocol provides for a cold reset and a warm reset. The t ype of reset used
depends on the system’s current power down state. Unless a cold or register reset (a
write to the Reset register in the codec) is performed, wherein the AC‘97 codec
registers are initialized to their default values, registers are required to keep state
during all power down modes.
Once powered down, activation of the AC-link through re-assertion of the AC_SYNC
signal must not occur for a minimum of four audio frame times following the frame in
which the power down was triggered. When AC-link powers up, it indicates readiness
via the codec ready bit.
5.20.4 AC‘97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_ RST# low,
BIT_CLK, and SDOUT will be activated and all codec registers will be initialized to their
default power on reset values.
AC_RST# is an asynchronous AC‘97 input to the codec.
5.20 .5 AC‘97 Warm Reset
A warm reset will re-a ctivate the AC-link without altering the current codec register
values. A warm reset is signaled by driving AC_SYNC high for a minimum of 1us in the
absence of BIT_CLK.
Within normal frames, AC_SYNC is a synchronous AC‘97 input to the codec. However,
in the absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec
used in the generation of a warm reset.
The codec must not respond with the activation of BIT_CLK until AC_SYNC has been
sampled low again by the codec. This will prevent the false detection of a new frame.
Figure 27. SDIN Wake Signaling
SDOUT
TAG
SYNC
BIT_CLK
Write to
0x20
Data
PR4
slot 12
prev. frame
TAG
slot 12
prev. frame
SDIN
TAG
Slot 1
Sl ot 2
Power Down
Frame Wake EventSleep State New Audio
Frame
TAG
Slot 1
Slot 2
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Note: On receipt of wake up signalling from the codec, the digital controller will issue an
interrupt when enabled. Software will then h ave to issue a warm or cold reset to the
codec by setting the appropriate bit in the Global Control Register.
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5.20.6 System Reset
Table 141 indicates the states of the link during various system reset and sleep
conditions.
The transition of AC_RST# to the deasserted state will only occur under driver control.
In the S1 sleep state, the state of the AC_RST# signal is controlled by the AC’97 Cold
Reset# bit (bit 1) in the Global Control register. AC_RST# will be asserted (low) by the
Intel® 6300ESB ICH under the following conditions:
RSMR S T # (sy s t e m r e se t, inclu d in g th e re set of th e r es u m e we ll an d PX PC I R S T #)
Mechanical power up (causes PXPCIRST#)
Write to CF9h hard reset (causes PXPCIRST#)
Transition to S3/S4/S5 sleep states (causes PXPCIRST#)
Write to AC’97 Cold Reset# bit in the Global Control Register.
Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit)
automatically. Only software may deassert the Cold Reset# bit, and hence the
AC_RST# signal. This bit, while it resides in the core well, will remain cleared upon
return from S3/S4/S5 sleep states. The AC_RST# pin will remain actively driven from
the resume well as indicated.
5.20.7 Hardware Assist to Determin e A C_SDIN Used Per
Codec
Software first performs a read t o one of t he audio c odecs. The read request goes out on
AC_SDOUT. Since under our micro-architecture only one read may be performed at a
time on the link, eventually the read data will come back on one of the AC_SDIN[2:0]
lines.
Tab l e 14 1. AC-lin k Stat e duri ng PX P C IRS T #
Signal Power
Plane I/O During
PXPCIRST#/ After
PXPCIRST#/ S1 S3 S4/S5
AC_RST# Resume3Outpu
tLow Low Cold Reset b it
(Hub Inte rface) Low Low
AC_SDOUT Core1Outpu
tLow Running Low Low Low
AC_SYNC Core Outpu
tLow Running Low Low Low
BIT_CLK Core Input Dri ven by
codec Running Low2,4Low2,4Low2,4
AC_SDIN[2:0] Resume Input Driven by
codec Running Low2,4Low2,4Low2,4
NOTES:
1. Intel® 6300ESB ICH core we ll outp uts are used as strapp ing op tions for the Intel® 6300ESB ICH, sam pl ed
during system reset. T hese signals may have weak pullups/pulldowns on them. The Intel® 6300ESB ICH
outputs w ill be driv en to the ap p rop ria te le vel prior to AC_RS T# be in g deasserted, prev e ntin g a cod ec fro m
entering te st mod e . S traps are tied to the core we ll to p re vent leak ag e duri ng a suspend stat e.
2. The pull-down resistors on these signals are only enabled w hen the AC-Link Shut Off bit in the AC’97 Global
Control Register is s et to 1. All other times, the pull-down resisto r is disabled.
3. AC_RST# w ill b e held low d u ring S 3 -S5 . It can not b e programmed high d urin g a suspend state .
4. BIT_CLK and AC _SDIN[2:0] are driven low by the codecs during normal states. When the codec is powered
during suspend states, it will hold these signals low. However, when the codec is not present, or not powered
in suspend, external pull-down resistors are required.
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The codec will do this by indicating that status data is valid in its TAG, then echo the
read address in slot 1 followed by the read data in slot 2.
The new function of the Intel® 6300ESB ICH hardwa re is to notic e which AC_SDIN line
contains the read return data, and to set new bits in the new register indicating which
AC_SDIN line the register read data returned on. When it returned on AC_SDIN0, bits
[1:0] contain the value ‘00’. When it returned on AC_SDIN1, the bits contain the value
‘01’, etc.
Intel® 6300ESB ICH hardw are may set these bits every time register read data is
returned from a function 5 read. No special command is necessary to cause the bits to
be set. The new driver/BIOS software will read the bits from this register when it cares
t o, and may i gnore i t ot herwi se. Whe n sof tw are is atte mpt ing to establ ish th e codec - to-
AC_SDIN mapping, it will single feed the read request and not pipeline to ensure it gets
the right mapping, hardware cannot ensure the serialization of the access.
5.20.8 Software Mapping of AC_SDIN to DMA Engine
Once software has performed the register read to determine codec-to-AC_SDIN
mapping, it will then either set bi ts [5:4] or [7:6] in th e SDAT A_IN MAP register to map
this codec to the DMA engine. Aft er it maps the audio codecs, it will set the “SE” (steer
enable) bit, which now lets the hardware know to no longer OR the AC_SDIN lines, and
to use the mappings in the register to steer the appropriate AC_SDIN line to the correct
DMA engines.
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Register and Memory Mapping 6
The Intel® 6300ESB ICH contains registers that are located in the processor’s I/O
space, memory space and sets of PCI configuration registers that are located in PCI
configuration space. This chapter details the Intel® 6300ESB ICH I/O and memory
maps. Regist er access is also described.
Register-level address maps and Individual register bit descriptions are provided in the
following chapters. The following notations are used in the chapters that follow.
RO Read Only: Writes to this register location generally have
no effect. However, in some cases, two separate registers
are lo cated at the sam e locatio n where a read will access
one register and a write will access the other register. See
the I/O and me mory map tables fo r detai ls.
WO Write Only: Reads to this register location generally
have no effect. However, in so me cases, two separate
registers are located at the same locati on where a read
will access o ne regi ster and a write wil l access the other
register. See the I/O an d memory map tabl es for details.
R/W Read/Write: A register with this attribute may be read
and written.
R/WC Read/Wr ite Clear: A register bit with this attribute may
be read an d writ ten. Howev er, writin g a 1 wi ll clear (sets
to zero) the correspon ding bit , and writing a 0 will hav e
no effect.
Default When coming out o f re set, the re g ister s a r e set to
predetermined default states. It is the responsibility of
th e syst em ini tiali za tio n soft wa r e to d e term i n e
configuration, operating parameters, and optional system
features t hat are applicable, and to program the Intel®
6300ESB ICH registers accordingly.
6. 1 PCI Devices and Functions
The Intel® 6300ESB ICH incorporates multiple PCI functions as shown in Table 142.
These functions are divided into four PCI devices. The first is the Hub In terface Link -To-
PCI bridge, D: 30 F:0. The second device, D31:F1, contains most of the standard PCI
functions present in most ICHs, as well as some new related Intel® 6300ESB ICH
features; SATA and SMBus Controller. The third device, D29 Fx, is the USB host
controller device which includes new features specific to the Intel® 6300ESB ICH;
Watchdog Timer and an additional IOxAPIC. The fourth PCI device, D28:F0, is also a
new Intel® 6300ESB ICH feature; a Hub Interface-to-PCI-X bridge.
When a particular system does not want to support any one of Device 31’ s, 29’s or 28’s
functions, they may individually be disabled. When a function is disabled, it does not
appear at all to the software. A disabled function will not respond to any register reads
or writes.
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Table 142. PCI Devices and Functions
Bus:Device:Func tion Funct ion Descri pti on
Bus 0: Dev ice 30: Function 0 Hub Interf a ce to PCI B ridge
Bus 0: Dev ice 31: Function 0 PCI to L P C B ridge
Bus 0: Dev ice 31: Function 1 ID E Controller
Bus 0: Dev ice 31: Function 2 SATA Controller
Bus 0: Dev ice 31: Function 3 SM B us Controller
Bus 0: Dev ice 31: Function 5 A C’97 A ud io Controller
Bus 0: Dev ice 31: Function 6 A C’97 Mod e m Controller
Bus 0: Dev ice 29: Function 0 US B Controller #1
Bus 0: Dev ice 29: Function 1 US B Controller #2
Bus 0: Dev ice 29: Function 4 Ne w: Watchdog Timer
Bus 0: Device 29: Function 5 Ne w: IOx A PIC
Bus 0: Dev ice 29: Function 7 USB 2.0 Controller
Bus 0: Dev ice 28: Function 0 Ne w: Hub Inte rfac e to PCI-X Brid ge
NOTE: The PCI t o LPC bri dge cont ai ns regist er s tha t control LPC , Power Managemen t, Sys tem
Management, GPIO, CPU Inte rfa ce , RTC, Interrupts, Tim ers, D M A.
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6.2 PCI Configuration Map
Each PCI function on the Intel® 6300ESB ICH has a set of PCI configuration registers.
The register map tables for each function are included at the beginning of each
respective chapter.
Conf ig ur ati on Sp ac e r egi st ers are acc es sed thro ug h c onfi gu ra ti on cy cle s on the PC I bus
by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus
Specification, Revision 2.2.
Some PCI registers contain “Reserved” bits. Software must deal correctly with fields
that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. Note the software does not need to perform
read, merge, write operation for the Configuration Address Register (0xCF8h).
Figure 28. Intel® 6300ESB ICH Device Diagram
HubLink Bus 0
A C’97 M ode m
Bus0:Dev31:F6
AC’97 Audio
Bus0:Dev31:F5
IDE
Bus0:Dev31:F1
USB2 Host
Bus0:Dev29:F7
Ph ysica l and
Logic al C onne ction
Logic al C onnection
Only
Physic al Connec tion
Only
US B Cla ssic H ost
Bus0:Dev29:F0,1
HubLink to
PCI Bridge
Bus 0
Dev30:F0
Legacy PCI Bus
SMBus Cntrl
Bus0:Dev31:F3
PCI - LPC Bridge
Bus0:Dev31:F0
LP C Bus
HubLink to
PCI
-
X Bridge
Bus 0
Dev28:F0
PCI
-
X Bu
s
Watch Dog T im e r
Bus0:Dev29:F4
SATA
Bus0:Dev31:F2
IOxAPIC
Bus0:Dev29:F5
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In addition to reserved bits within a register, the configur ation space contains reserved
locations. Software should not write to reserved PCI configuration locations in the
device-specific region (above address offset 3Fh).
6.3 I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be
moved, but in some cases may be disabled. Variable ranges may be moved and may
also be disabled.
6.3.1 Fixed I/O Address Ranges
Table 143 sho ws the Fixed I/O decode ranges from the CPU perspective. Note that for
each I/O range, there may be separate behavior for reads and writes. The Hub
Interface cycles that go to target ranges that are marked as “Reserved” will not be
decoded by the Intel® 6300ESB ICH, and will be passed to PCI. When a PCI master
targets one of the fixed I/O target ranges, it will be positively decoded by the Intel®
6300ESB ICH in medium speed.
Note: Unclaimed PCI cycles will be subtractively decoded and forwarded to the LPC.
Address ranges that are not listed or marked “Reserved” are NOT decoded by the
Intel® 6300ESB ICH (unless assigned to one of the variable ranges).
Table 143. Fixed I/O Ranges D ecoded by Intel® 6300ESB I/O Controller Hub
(Sheet 1 of 3)
I/O
Address Read Target Write Target Internal Unit
0 0h - 08h DMA Controller DMA Controller DMA
09h - 0Eh Res erved DMA Controller DMA
0 Fh DMA Controller D MA Con troller DM A
1 0h - 18h DMA Controller DMA Controller DMA
19h - 1Eh Res erved DMA Controller DMA
1 Fh DMA Controller D MA Con troller DM A
20h - 21h Interrupt Controller Interrupt Controller Interrupt
24h - 25h Interrupt Controller Interrupt Controller Interrupt
28h - 29h Interrupt Controller Interrupt Controller Interrupt
2Ch - 2Dh Interrupt Controller Interrupt Controll er Interrupt
2E -2F LPC SIO L PC S IO Forwarded to LPC
30h - 31h Interrupt Controller Interrupt Controller Interrupt
34h - 35h Interrupt Controller Interrupt Controller Interrupt
NOTES:
1. Only when the Port 61 Alias Enable bit (De v ice 31:Function 0, Offset D0, Bit 4) bit is set.
Othe rwise, the target is PCI.
2. On ly when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in legacy mode. Oth er wise, the ta rg e t is PCI.
3. Only when IDE St an dar d I/O spac e is en a bled f or Primary Cha nne l a nd the ID E Controller is
in lega cy mode. Otherwise, the ta rg e t is PCI.
4. Should forward read c ycles to this address to LPC Variable I/O Decode Ranges.
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38h - 39h Interrupt Controller Interrupt Controller Interrupt
3Ch - 3Dh Int errup t Controller Inte rrupt Controller Inter rupt
40h - 42h Timer/C ounte r Tim e r/Counter PIT (8254)
43h Reserved Timer/Counter PIT
4E-4F LPC SIU LPC SIU Forwarde d to LPC
50h - 52h Timer/C ounte r Tim e r/Counter PIT
53h Reserved Timer/Counter PIT
60h Microcontrolle r/E mulation Microcontroller/Emulati on Forward e d to L PC
61h NMI Con troller NMI Controller CP U I/F
62h Microc ontroller Microco ntroller Forwarde d to LP C
63h NMI Con troller NMI Controller CP U I/F
64h Microcontrolle r/E mulation Microcontroller/Emulati on Forward e d to L PC
65h NMI Con troller NMI Controller CP U I/F
66h Microc ontroller Microco ntroller Forwarde d to LP C
67h NMI Con troller NMI Controller CP U I/F
70h Re ser ved NM I and R TC Con tro ller RTC
71h RTC Controller RT C Controller RT C
72h RTC Co ntr oller N MI and RT C Co ntr oller R TC
73h RTC Controller RT C Controller RT C
74h RTC Co ntr oller N MI and RT C Co ntr oller R TC
75h RTC Controller RT C Controller RT C
76h RTC Co ntr oller N MI and RT C Co ntr oller R TC
77h RTC Controller RT C Controller RT C
80h DMA Co ntroller DMA Controller and LPC or
PCI DMA
81h - 83h DMA Controller DMA Controller DMA
84h - 86h DMA Controller DMA Controller and LPC or
PCI DMA
87h DMA Controller DMA Controller DMA
88h DMA Co ntroller DMA Controller and LPC or
PCI DMA
89h - 8Bh D M A Co ntroller DMA Controller DMA
Table 143. Fixed I/O Ranges Decoded by Intel® 6300ESB I/O Controller Hub
(Sheet 2 of 3)
I/O
Address Read Target Write Target Internal Unit
NOTES:
1. Only when the Port 61 Alias Enable b it (Dev ice 31:Function 0, Offset D0, Bit 4) bit is set.
Otherwise, the target is PCI.
2. Only when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in lega cy mod e . Oth e rwise, the target is PC I.
3. Only whe n IDE Sta nd a rd I/O sp a ce is e n ab le d for Primary Cha nne l a nd the IDE Controller is
in legacy mode. Othe rwise , the target is PCI.
4. Should forward read cycles to this address to LPC Var iable I/O Decode Ranges.
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8Ch - 8Eh DMA Controller DMA Controller and LPC or
PCI DMA
08Fh DMA Controller D M A Con troller DMA
9 0h - 91h DMA Controller DMA Controller DMA
92h Reset Generator Reset Generator CPU I/F
93h - 9Fh D MA Controller DMA Contro ller DMA
A0h - A1h Interrupt Controller Interrupt Controller Interrupt
A4h - A5h Interrupt Controller Interrupt Controller Interrupt
A8h - A9h Interrupt Controller Interrupt Controller Interrupt
ACh - ADh Interrupt Controller Interrupt Controller Interrup t
B0h - B1h Interrupt Controller Interrupt Controller Interrupt
B2h - B3h Power Management Power Management Power
Management
B4h - B5h Interrupt Controller Interrupt Controller Interrupt
B8h - B9h Interrupt Controller Interrupt Controller Interrupt
BCh - BDh Interrup t Controller Interrupt Controller Interrup t
C0h - D1h DMA Controller DMA Controller DMA
D2h - DDh R e se rv e d DMA Con tr ol l er DMA
DEh - DFh DM A Controller D M A Con troller DMA
F0h S ee Note 2 FERR#/IGNNE # / Interrup t
Controller CPU I/F
170h - 177h IDE Controller2IDE Con trolle r2For w ar ded t o IDE
1F0h - 1F7h IDE Controller1IDE Con trolle r1For w ar ded t o IDE
376h IDE Controller2IDE Controller2For w ar ded t o IDE
200-207h Ga me p ort L ow G ameport Low Forwarded to LP C
208-20Fh Game p ort H ig h Gam epor t H igh Forwarded to LP C
376h IDE Controller2IDE Controller2For w ar ded t o IDE
388-38B h AdLib Ad L ib Forwarded to LPC
3F6h IDE Controller1IDE Con trolle r1Forwarded IDE
4D0h - 4D1h Interrupt Controller Interrupt Controller Interrupt
CF9h Reset Generator Reset Generator CPU I/F
Table 143. Fixed I/O Ranges D ecoded by Intel® 6300ESB I/O Controller Hub
(Sheet 3 of 3)
I/O
Address Read Target Write Target Internal Unit
NOTES:
1. Only when the Port 61 Alias Enable bit (De v ice 31:Function 0, Offset D0, Bit 4) bit is set.
Othe rwise, the target is PCI.
2. On ly when IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller
is in legacy mode. Oth er wise, the ta rg e t is PCI.
3. Only when IDE St an dar d I/O spac e is en a bled f or Primary Cha nne l a nd the ID E Controller is
in lega cy mode. Otherwise, the ta rg e t is PCI.
4. Should forward read c ycles to this address to LPC Variable I/O Decode Ranges.
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6.3.2 Variable I/O Decode Ranges
Table 144 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various PCI configuration spaces.
The PNP software (PCI or ACPI) may use their configuration mechanisms to set and
adjust these values.
When a cycle is detected on the Hub Interface, the Intel® 6300ESB ICH will positively
decode the cycle. When the response is on the behalf of an LPC device, the Intel®
6300ESB ICH will forward the cycle to the LPC.
Refer to Table 144 for a complete list of all variable I/O registers.
Warning:The Variable I/O Ranges should not be set to conflict with the Fixed I/O
Ranges. There may be unpredictable results when the co nfiguratio n software
allows confli cts to occu r. The Intel ® 6300ESB ICH does not perform any checks
for conflicts.
Tab l e 14 4. V a ri abl e I/ O De co de Ran ge s
Range Name M appable Size (Bytes) Target
ACPI Anywhere in 64K I/O
Space 64 Power Management
IDE Bus Master Anywhere in 64K I/O
Space 16 IDE Unit
USB #1 Anywhere in 64K I/O
Space 32 USB 1.0 Host Controller
1
SMBus Anywhere in 64K I/O
Space 32 SM B Unit
AC’97 Aud io Mi xer Anywhere in 64K I/O
Space 256 AC’97 Unit
AC’ 97 B u s M a ster Anywhere in 64K I/O
Space 64 AC’97 Unit
AC’97 Modem Mixer Anywhere in 64K I/O
Space 256 AC’97 Unit
TCO 96 Bytes above ACPI Ba se 32 TCO Un it
GPIO Anywhere in 64K I/O
Space 64 GPIO Unit
Parallel Port 3 ranges in 64K I/O Space 8 LPC Peripher al
Serial Port 1 8 Ranges in 64K I/O
Space 8 LPC Peripheral
Serial Port 2 8 Ranges in 64K I/O
Space 8 LPC Peripheral
Floppy Disk Controller 2 Ranges in 64K I/O
Space 8 LPC Peripheral
MIDI 4 Ra nges in 64K I/O
Space 2 LPC Peripheral
MSS 4 Ranges in 64K I/O
Space 8 LPC Peripheral
SoundBlaster 2 Ranges in 64K I/O
Space 32 LPC Pe ripheral
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USB #2 Anywhe re in 64K I/O
Space 32 USB 1.0 Host Controller
2
LPC Generic 1 Anywher e in 64K I/O
Space 128 LPC Peripheral
LPC Generic 2 Anywher e in 64K I/O
Space 16 LPC Peripheral
Monitors 4:7 Any wher e in 64K I/O
Space 16 LPC Periph eral or Trap
on PCI
Nati ve IDE Pri mary
Command Any wher e in 64K I/O
Space 8IDE Unit
Nati ve IDE Pri mary
Control Any where in 64K I/O
Space 4IDE Unit
Nati ve IDE Secon dar y
Command Any wher e in 64K I/O
Space 8IDE Unit
Nati ve IDE Secon dar y
Control Any where in 64K I/O
Space 4IDE Unit
Table 144. Variable I/O Decode Ranges
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6. 4 Mem o r y Map
Table 145 shows, from the CPU perspective, the memory range s that the Intel®
6300ESB ICH will decode. Cycles that arrive from the Hub Interface that are not
direc te d to a n y of the internal memory targe ts that decode direc tly fr om Hub Interfa ce
will be driven out on PCI. The Intel® 6300ESB I CH may th en cl aim the cyc le for i t to b e
forwarded to LPC or claimed by the internal
I/O APIC or subtractive decode the cycle. When subtractive decode is enabled, the
subtractive decoded cycle may be forwarded to the LPC I/F or to the FWH.
PCI cycles g ene r at e d by a n ex te rn al PC I ma ste r w il l be po si ti v el y decoded un le s s i t fa l ls
in the PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-
peer traffic). When the cycle is not in the I/O APIC or FWH/LPC ranges, it will be
forwarded up the Hub Interface to the Host Controller. PCI masters cannot access the
memory ranges for functions that decode directly from Hub Interface.
Table 145. Memory Decode Ranges from CPU Perspective (Sheet 1 of 2)
Memory Range Target Dependency/Comments
0000 0000 - 000D FFFF
0010 0000 - TOM
(Top of Mem ory) Main Me mory TOM re g i ste rs in Host Controller
000E 0000 - 000F FFFF FWH B it 7 in FW H Decode Enable Register is set
FEC0 0000 - FEC0 0043
I/O APIC
insi de the
Intel®
6300ESB ICH
Downs tre am memory writes t o FEC0 0020 are
also decoded by D29:F5 APIC to suppo rt EOI.
FEC1 0000 - FEC1 0043 I/O APIC
(D29:F5)
D29:F5 APIC also supports FEC00000-FEC00043
range o f message signaled interrupts from the
PCI-X interface (See Note 1)
FFC0 0000 - FF C7 FFFF
FF80 0000 - FF87 FFFF FWH Bit 0 in FW H Decode Enable Register
FFC8 0000 - FFCF FFFF
FF88 0000 - FF8F FFFF FWH B it 1 in FWH Decode Enable Registe r
FFD0 0000 - FFD7 FFFF
FF90 0000 - FF97 FFFF FWH Bit 2 in FW H Decode Enable Register is set
FFD8 0000 - FFDF FFFF
FF98 0000 - FF9F FFFF FWH B it 3 in FW H Decode Enable Registe r is se t
FFE0 000 - FFE7 FFFF
FFA0 0000 - FFA 7 FFFF FWH B it 4 in FW H Decode Enable Register is se t
FFE8 0000 - FFEF FFFF
FFA8 0000 - FFA F FFFF FW H Bit 5 in FW H Decode Enable Registe r is se t
FFF0 0000 - FFF7 FFFF
FFB0 000 0 - FFB 7 FFFF FW H Bit 6 in FW H Decode Enable Registe r is set.
FFF8 0000 - FFFF FFFF
FFB8 000 0 - FFB F FFFF FWH
Always enabled.
The top two 64K -byte blocks of this range may be
swap ped, as descri bed in Section 6.4.1, “Boot-
Block Up dat e Schem e”.
NOTES:
1. These r anges are dec oded di rectly f rom Hub Inter face. The mem or y cycles will not be see n on
PCI.
2. Software must not atte mpt locks to memory mapped I/O ranges for U SB EHCI, Hig h
Performance Event Timers, and IDE Expansion. When attempted, the lock is not honored,
which means pote nt ial deadlock con d itions may occu r.
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FF70 0000 - FF7F FFFF
FF30 0000 - FF3F FFFF FWH Bit 3 in FW H Decode Enab le 2 Register is se t
FF60 0000 - FF6F FFFF
FF20 0000 - FF2F FFFF FWH Bit 2 in FW H Decode Enab le 2 Register is se t
FF50 0000 - FF5F FFFF
FF10 0000 - FF1F FFFF FWH Bit 1 in FW H Decode Enab le 2 Register is se t
FF40 0000 - FF4F FFFF
FF00 0000 - FF0F FFFF FWH Bit 0 in FW H Decode Enab le 2 Register is se t
1 Kbyte anywhere
in 4 G b yte range IDE
Expansion2Enable through standard PCI mechanism and bits
in IDE I/O Configuration Register (Device 31,
Function 1)
512B anywhere in 4 G byte
range
AC’97 Host
Controller
(Mixer)1
Enable via standard PCI mechanism (Device 31,
Function 5)
256B anywhere in 4 G byte
range
AC’97 Host
Controller
(Bus Master)1Enable via standard PCI mechanism (Device 31,
Function 5)
1 Kbyte anywhere in 4
Gbyte range USB EHCI
Controller1, 2Enable through standard PCI mechanism (Device
29, Function 7).
FED0 X000 - FED 0 X 3FF Multimedia
Timers1, 2BIOS determines the “fixed” location which is one
of four, 1-Kbyte ranges where X (in the first
column) is 0h , 1h, 2h, or 3h.
1 Kbyte anywhere in 4
Gbyte range SATA1Enable via standard PCI mechanism (Device 31,
Function 2)
1 Kbyte anywhere in 4
Gbyte range WDT Enable via standard PCI mechanism (Device 29,
Function 4)
1 Mbyte to 4 Gbyte
anywhere in 4 Gbyte range PCI-X1Enable via standard PCI mechanism (Device 28,
Function 0)
All other PCI
None/ If the address is below 16M, is not in one of
the above BIOS Ranges, and positive decode is
disabled; t hen the cycle will be forwarded to LPC
as a standard LPC memory cycle.
If th e address is abov e 16M, if the cycle is not
claimed by a device on PCI and neither by the
Intel® 6300ESB ICH , the n the cycle will M aster-
Abort on PCI
Table 145. Memory Decode Ranges from CPU Perspective (Sheet 2 of 2)
Memor y Range Target Depe nd ency/Co mments
NOTES:
1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on
PCI.
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High
Performanc e Event Time rs, and IDE Exp a nsion. When atte mpted, the lock is not honore d ,
w hich me an s poten tial dead lock cond itions m ay oc cu r.
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6.4.1 Boot-Block Update Scheme
The Intel® 6300ESB ICH supports a “top-block swap” mode that has the Intel®
6300ESB ICH swap the top block in the FWH (the boot block) with another location.
This allows for safe update of the Boot Block (even if a power failure occurs). When the
“TOP_SWAP” Enable bit is set, the Intel® 6300ESB ICH will invert A16 for cycles
targ et in g FWH BIO S spac e. Whe n this bit is zero, the Inte l® 6300ESB ICH will not
invert A16. This bit is automatically set to zero by RTCRST#, but not by PXPCIRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block,
and the blo ck immed iatel y belo w the top blo ck is reser ved for doin g boot-blo c k
updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top.
2. Software checks that the copied block is correct. This could be done by performing
a che c ksu m calcu la t io n.
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the FWH.
Processor access to FFFF_0000 through FFFF_FFFF will be directed to FFFE_0000
through FFFE_FFFF in the FWH, and processor accesses to FFFE_0000 through
FFFE_FFFF will be directed to FFFF_0000 through FFFF_FFFF.
4. Software erases the top block.
5. Software writes the new top block.
6. Software checks the new top block.
7. Software clears the TOP_SWAP bit.
If a power failure occurs at any point after step 3, the system will be able to boot from
the copy of the boot block that is sto red in the block below the top. This is because the
TOP_SWAP bit is backed in the RTC well.
Note: The top-block swap mode may be forced by an external strapping option (See
Section 3.21.1, “Functional Straps”). When top-block swap mode is forced in this
manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap
removed will be required to exit a forced top-block swap mode.
Note: Top-block swap mode only affects accesses to the FWH BIOS space, not feature space.
Note: The top-block swap mode has no effect on accesses below FFFE_0000.
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7—Intel® 6300ESB ICH
Hub Interface to PCI Bridge
Registers (D30:F0) 7
The Hub Interface to PCI Bridge resides in PCI Devi ce 30, Function 0 on Bus #0. This
portion of the Intel® 6300ESB ICH implements the buffering and control logic between
PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device.
The PCI decoder in this device must decode the ranges for the Hub Interface. All
register contents will be lost when core well power is removed.
7.1 PCI Configuration Registers (D30:F0)
Note: Registers that are not shown should be treated as Reserved (see Section 6.2, “PCI
Configuration Map” for details).
.
Table 146. PCI Configuration Registers (D30:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name/Function Default Type
00-01h VID Vendor ID 8086h RO
02-03h DID Dev ice ID 244Eh RO
04-05h CMD PCI Device Command Register 0001h R/W
06-07h PD_STS PCI D e vice Stat us Register 00 80h R/ W
08h RID Revision ID See NOTE: RO
0A h SCC Sub Clas s Code 04h RO
0Bh B CC Ba se Class Code 06h RO
0 Dh PMLT Pri ma ry M aste r Latency Timer 00h RO
0Eh HEA DTYP Heade r Ty pe 01h RO
18h PBUS_NUM Primary Bus Number 0 0h RO
19h SBUS _N UM Secondary Bus Number 00h R/W
1Ah SUB_B US_N UM Subord inate B u s Numb e r 00h R/ W
1Bh S MLT Secondary Master Latency Timer 00h R/W
1Ch IOB ASE IO B ase Register F0h R/ W
1Dh IOLIM IO Limit Register 0 0h R/ W
1E-1Fh SECSTS Se condary S tatus Regis ter 0280h R/ W
20-21h MEMBASE Memory Base FFF0h R/W
22-23h MEMLIM Memory Limit 0000h R/W
24-25h PREF_MEM_BAS E Pre f etchab le Me mory Base 0000h RO
26-27h PREF_M EM_MLT Prefe tchable Memory Limit 00 00h RO
30-31h I OB ASE_HI I/O Base Upp e r 16 B its 0000h RO
32-33h IOL IMIT_HI I/O Limit Upper 16 B its 00 00h RO
NOTE: Refer to the Intel® 6300ESB ICH S p ec if ica tion Update for the most up-to-date value of
th e Revisio n ID re gist e r.
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7.1.1 Offset 00 - 01h: VID—Vendor ID Register (HUB-
PCI—D30:F0)
7.1.2 Offset 02 - 03h: DID—De vice ID Registe r (HUB-
PCI—D30:F0)
3Ch INT_LIN E Interrupt Line 00h RO
3E-3Fh B RID G E _CNT Bridge Co ntrol 0000h R/W
40-43h HI1_CMD Hub Interface 1 Command Control 20202802h R/W
44-45h DEVICE_HIDE Secondary P CI Device Hiding
Register 00 R/W
50-51h CNF Intel® 6300ESB ICH Conf ig uration
Register 1400h R/W
70 h M TT Multi-Transa ction Time r 20h R/W
82h PCI_MAST_STS PCI Master Status 00 h R/W
90h ERR_CMD Error Command Register 00h R/W
92h ERR_S TS Error Status Register 00h R/W
F8h MANID Manufacturer’s ID 0F66h RO
Table 147. Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0)
Bits Name Description Access
15:0 Vendor I dentifi ca tion
Number This is a 16-bit value assig n e d to Inte l. Inte l V I D = 808 6h . RO
Table 148. Offset 02 - 03h: DID—Device I D Register (HUB-PCI—D30:F0)
Bits Name Description Access
15:0 De v i ce Identif ica ti on
Number This is a 16-b it value a ssig ne d to th e Inte l® 63 00ES B ICH
Hub In terf ace to PCI brid ge. RO
Table 146. PCI Configuration Regi sters (D30:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name/Function Default Type
NOTE: Refer to the Intel® 6300ES B ICH S pecification U pdate for the most up-to-date value of
the Revision ID register.
Device: 30 Function: 0
Offset: 00-01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Device: 30 Function: 0
Offset: 02-03h Attribute: Read-Only
Defau lt Value: 244Eh Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 289
7—Intel® 6300ESB ICH
7. 1.3 Offset 04 - 05h: CMD—Command Register (HUB-
PCI—D30:F0)
Table 149. Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)
Bits Name Description Access
15:1
0Reserved Reserved.
9Fast Back to Back Enable
(FBE) Hard wired to’0’. Th e Intel ® 6300ESB ICH does not support
this capability. RO
8SERR# Enable
(SERR_EN)
0 = D isa b le .
1 = Enable the Intel® 6300ESB ICH to g e nerate an NMI (or
SMI# if NMI ro ute d to SMI#) when the D30:F0 SSE bit
(offset 06h, b it 14) is set .
R/W
7 Wait Cycle Control Hardwired to ‘0’ RO
6 Parity Error Respon se
0 = The Intel® 6300ES B ICH will ig nore p arity er rors on the
Hub Interfac e.
1 = The Intel® 6300ESB ICH is allowed to report parity errors
de tected on t he Hub Interfac e.
NOTE: The Hub Interface Parity Unsupported bit
(D30:F0:40h:bit20) must be cleared for the PER bit to
ha ve any effect.
R/W
5 VGA Palette Snoop Hardwired to ‘0’. RO
4Memory Write and
Invalidate Enable (MWE) Hardwired to ‘0’. RO
3Special Cycle Enable
(SCE) Hardwired to ‘0’ by P2P Bridge s p ec. RO
2Bus M a ste r E n able
(BME)
0 = D isa b le
1 = Allows the Hub Interfa ce-to-PCI bridge to accept cycles
from PC I to run on the Hub Interf ace .
NOTE: T h is bit do es not a ffect the CF8 h an d CFC h I/O
accesses.
NOTE: Cycles that generated from the Intel® 6300ESB ICH’s
Device 31 functionality are not blocked by clearing
this bit.
R/W
1Memory Space Enable
(MSE)
The I nt el® 6300ESB ICH prov ides this bit as read/writable for
softwar e on ly. H owever, the Inte l® 6300ES B ICH ig nore s the
programming of this bit, and runs Hub Interface memory
cycles to PCI.
R/W
0 I/O Space Enable (IOE)
The I nt el® 6300ESB ICH prov ides this bit as read/writable for
softwar e on ly. H owever, the Inte l® 6300ES B ICH ig nore s the
programming of this bit and runs Hub Interface I/O cycles to
PCI that are not intended for USB, IDE, or AC’97.
R/W
Device: 30 Function: 0
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 0001h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
290 Order Number: 300641-004US
7.1.4 Offse t 06 - 07h: PD_S TS—Pr imary Devi ce Status
Register (HUB-PCI—D30:F0)
Note: For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit
will have no effect.
Table 150. Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—
D30:F0)
Bits Name Description Access
15 Det ecte d Parity Error
(DPE)
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Indicates that the Inte l® 6300ES B ICH detected a parity
error on the H ub In te rf a ce an d the H ub In te rf a ce Parity
Unsupported bit is cleared (D30:F0:40h:bit20). This bit
gets set even when the Parity Error R esponse bit (offset
04, bit 6) is not set.
R/WC
14 Signaled System Error
(SSE)
0 = Softwar e clear s this bi t by writing a ‘1’ to the bit location.
1 = An address, or com ma nd parity error, or special cycles
data parity e rror has bee n detected on the PCI bus, and
the Parity Er ror Respo nse bit (D30:F0, Offset 04h, b it 6)
is set. When this bit is set because of parity error and the
D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, t he
Intel® 6300ESB ICH will generate an NMI (or SMI# if NMI
routed to SMI#).
R/WC
13 R eceived Mas ter Abort
(RMA)
0 = Softwar e clear s this bi t by writing a ‘1’ to the bit location.
1 = The Intel® 6300ESB ICH rece ived a master ab ort from
the Hub Interface device. R/WC
12 R eceived Target Abort
(RTA)
0 = Softwar e clear s this bi t by writing a ‘1’ to the bit location.
1 = The Intel® 6300ESB ICH received a target abort from the
Hub Interface device. The setting of this bit can be
enabled to c ause a n inter nal SE RR#.
R/WC
11 Signa led Targ et Abor t
(STA)
0 = Softwar e clear s this bi t by writing a ‘1’ to the bit location.
1 = The Intel® 6300ES B ICH signals a target abort condition
on the Hub Interface. R/WC
10:9 D EV S EL# Timing Status 00h = Fast timing. This register a p p lie s to the Hu b Inte rfa ce . RO
8Master Data P arity Error
Detected (MDPD)
Since this reg ist er applie s to the H ub Inte rf ace , the Intel®
6300E SB ICH must interpret this b it d if ferently than it is in
the PCI spec.
0 = Softwar e clear s this bi t by writing a ‘1’ to the bit location.
1 = The Intel® 6300ESB ICH detects a pari ty error o n the
Hub Interfac e and the Parity Error Response b it in the
Command Register (offset 04h, bit 6) is set.
R/WC
7 Fa st Back to Back Hard wire d to ‘1’. RO
6User Definable Features
(UDF) Hardwired to ‘ 0’. RO
5 66 MHz C apable Hardwired to ‘0. RO
4:0 Reserved Reserved.
Device: 30 Function: 0
Offset: 06-07h Attribute: Read/Write Clear
Defau lt Value: 0080h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 291
7—Intel® 6300ESB ICH
7.1.5 Offset 08h: RID—Revision Identification Register
(HUB-PCI—D30:F0)
7.1.6 Offset 0Ah: SCC—Sub-Clas s Code Register (HUB-
PCI—D30:F0)
7.1.7 Offset 0Bh: BCC—Base-Class Code Register
(HUB-PCI—D30:F0)
Table 151. Offset 08h: RID—Revision Identification Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:0 R evision ID Value 8-b it value that ind icates the revision numb e r f o r the In te l®
6300ESB ICH ICH Hub Interface-to-PCI bridge. RO
Table 152. Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:0 Sub-Class Code 8-bit value that indicates the categ ory of bridge for the Intel®
6300ESB ICH Hub Interface to PCI bridge. The code is 04h
indica ting a PCI-to- PCI br id ge. RO
Table 153. Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:0 Base Class Code 8 -b it value that indi cate s the type of device f or the Intel®
6300ESB ICH Hub Interface to PCI bridge. The code is 06h
indi c atin g a bridge devi c e. RO
Device: 30 Function: 0
Offset: 08h Attribute: Read-Only
Defau lt Value: 08h Size: 8-bit
Device: 30 Function: 0
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 04h Size: 8-bit
Device: 30 Function: 0
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 06h Size: 8-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
292 Order Number: 300641-004US
7.1.8 Offset 0Dh: PMLT—Primary Master Latency Timer
Register (HUB-PCI—D30:F0)
Note: This register does not apply to Hub Interface.
7.1.9 Offset 0Eh: HEADTYP—Header Type Register
(HUB-PCI—D30:F0)
7.1.10 Offse t 18h: PBUS_NUM—Primary Bus Number
Register (HUB-PCI—D30:F0)
Table 154. Offset 0Dh: PM LT—Primary Master Latency Timer Register (HUB-PCI—
D30:F0)
Bits Name Description Access
7:3 Master Latency Count Not implemented .
2:0 Reserved Reserved.
Table 155. Offset 0Eh: HEADTYP—Header Type Register (HUB-PCI—D30:F0)
Bits Name Description Access
7 Multi-Function Device This b it is ‘0’ to indicate a single function device. RO
6:0 Header Type 8-bit field identifies the header layout of t he configuration
space, which is a PCI-to-PCI b rid g e in thi s case . RO
Table 156. Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—
D30:F0)
Bits Name Description Access
7:0 Primary Bus Numbe r This field indicates the bus number of the Hub Interface and
is hardwir ed to 00h. RO
Device: 30 Function: 0
Offset: 0Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 30 Function: 0
Offset: 0Eh Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Device: 30 Function: 0
Offset: 18h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 293
7—Intel® 6300ESB ICH
7. 1.11 Offset 19h: S BUS_N UM—Se condary Bus Number
Register (HUB-PCI—D30:F0)
7.1.12 Offset 1A: SUB_BUS_NUM—Subordinate Bus
Number Register (HUB-PCI—D30:F0)
7.1.13 Offset 1Bh: SMLT—Secondary Master Latency
Timer Register (HUB-PCI—D30:F0)
This Master Latency Timer (MLT) controls the amount of time that the Intel® 6300ESB
ICH will continue to burst data as a master o n the PCI bus. When the Intel® 6300ESB
ICH starts the cycle after being granted the bus, the counter is loaded and starts
count in g down fr om the asser ti on of FRAME#. Whe n the inter nal gra nt to this device is
removed, the expiration of the MLT counter will result in the deassertion of FRAME#.
When the internal grant has not been removed, the Intel® 6300ESB ICH may continue
to own the bus.
Whe n th e S e c on d ary Ma ster L a te n cy Timer i n D evi c e 30 ( o f fset 1B h ) is pro gra mm ed to
00h (the default value), the North PCI initiator logic operates as though the timer never
expires. Therefore, with this programming, constant consecutive writes from the Hub
Interface to PCI are capable of occupying the PCI bus indefinitely without releasing
FRAME#.
Table 157. Offset 19h: SBUS_NUM—Secondary Bus Number Register (HUB-PCI—
D30:F0)
Bits Name Description Access
7:0 Secondary Bus Num ber
This field indicates the bus number of PC I.
When this n umber is equal to th e p rimary bus number (i.e.,
bus #0), the Intel® 6300ESB ICH will run Hub Interfac e
co nfiguratio n cycles to this b u s n u mber as Type 1
configuration cycles on PCI.
R/W
Table 158. Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-
PCI—D30:F0)
Bits Name Description Access
7:0 Subordinate Bus
Number
This fi eld specifi es th e high est PCI bus n umber bel ow the Hub
Interface to PCI bridge. When a Type 1 configuration cycle
from the Hub Inte rf a ce d oe s not fa ll in the Secondary-to-
Subordinate Bus ranges of Device 30, the Intel® 6300ESB
ICH will in di cate a master ab ort back to the Hub Interfac e .
R/W
Device: 30 Function: 0
Offset: 19h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 30 Function: 0
Offset: 1A Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
294 Order Number: 300641-004US
A value of 00h disables the timer such that the North PCI initiator logic is never forced
t o end a burst prematurely due to a timeout.
7.1.14 Offset 1Ch: IOBASE—I/O Bas e Register (HUB-
PCI—D30:F0)
Table 159. Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-
PCI—D30:F0)
Bits Name Description Access
7:3 Master Latency Count 5-bit value that indicates the number of PCI clocks, in 8-clock
increme nts, that the Inte l® 6300ES B ICH will re main as
mas ter of the b u s. R/W
2:0 Reserved Reserved.
Table 160. Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:4 I/O A ddres s B a se bits
[15:12]
I/O Base bits corresponding to address lines 15:12 for 4-
Kbyte alignment. Bits 11:0 are assumed to be padded to
000h. R/W
3:0 I/O Addressing
Capability
This is hardwire d to 0h, indicating th at the Hub Interf a ce to
PCI bridge does not support 32-bit I/O addressing. This
means that the I/O base and limit upper address registers
must be read only.
RO
Device: 30 Function: 0
Offset: 1Bh Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 30 Function: 0
Offset: 1Ch Attribute: Read/Write
Defau lt Value: F0h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 295
7—Intel® 6300ESB ICH
7.1 .15 Offs et 1Dh : IOLI M—I /O Li mit Re gist er (HU B-P CI—
D30:F0)
7. 1.16 Offset 1E - 1Fh: SECSTS—Secondary St atus
Register (HUB-PCI—D30:F0)
Note: For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit
will have no effect.
Table 161. Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:4 I/O Address Limit bits
[15:12]
I/O Ba se bits correspondi ng to addr e ss lin e s 15:12 f or
4 Kbyte alignment. Bits 11:0 are ass ume d to b e pad ded to
FFFh. R/W
3:0 I/O Addres sing
Capability
This is hardwired to 0h, indic ating tha t the Hub Interf ace-to-
PCI bridge does not s upport 32-bit I/O addressing. This
means that the I/O base and limit upper address registers
must be read only.
RO
Table 1 62. Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI
D30:F0)
Bits Name Description Access
15 Dete cte d Parity Error
(DPE)
0 = This bit is cle ared by softw are w riting a 1.
1 = The Intel® 6300ESB ICH d etec ted a parity error on the
PCI bus. R/WC
14 Received System Error
(SSE) 0 = Sof twa re clea rs this bit by writing a ’1’ to the bi t position.
1 = SE RR# assertion is rec e ived on PCI. R/WC
13 Rece ived M a ste r Abort
(RMA) 0 = Sof twa re cle ars this bit by writing a ’1’ to the bi t position.
1 = Hub Interface t o PCI cycle was master-aborted on PCI. R/WC
12 Received Target Abort
(RTA)
0 = Sof twa re cle ars this bit by writing a ’1’ to the bi t position.
1 = Hub Interface to PCI cycle was target-aborted on PCI. F or
“compl et i on re qui re d” cyc le s f rom th e Hu b In ter fa ce, t hi s
event sho uld also se t the Si gnaled Target Abort in the
Prima ry Status Registe r in th is dev ice , a nd th e Intel®
6300ESB ICH must send the “target abort” status back to
the Hub Int erface.
R/WC
11 Signal ed Target Abort
(STA) Intel® 6300ESB ICH d oe s not ge nerate target abo rts. RO
10:9 DEV SEL# Timing Status 01h = Medium timing. RO
Device: 30 Function: 0
Offset: 1Dh Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 30 Function: 0
Offset: 1E-1Fh Attribute: Read/Write
Defau lt Value: 0280h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
296 Order Number: 300641-004US
7.1.17 Offset 20 - 21h: MEMBASE—Memory Base Register
(HUB-PCI—D30:F0)
This register defines the base of the Hub Interface to PCI non-prefetchable memory
range. Since the Intel® 6300ESB ICH will forward all Hub Interface memory accesses
to PCI, the Intel® 6300ESB ICH will only use this information for determining when not
to accept cycles as a target.
This register must be initialized by the configuration software. For the purpose of
address decode, address bits AD[19:0] are assumed to be zero. Thus, the bottom of
the defined memory address range will be aligned to a 1 Mbyte boundary.
8Master Data P arity Error
Detected (MDPD)
0 = Softwar e c lea rs this bit by wr iting a’ 1’ to the bit position.
1 = The Intel® 6300ESB ICH sets this bit when all of the
following three conditions are met:
- The Parity Error Response Ena ble bit in the Br id ge
Control Registe r (bit 0, offset 3Eh) is set
- USB, AC’97 or IDE is a Maste r
- PERR# as se rts during a write cycle OR a p arity er ror is
detected internally during a read cycle
R/WC
7 F ast Back to Back Hardwire d to ‘1’ to ind icate tha t the PCI to H ub Inte rf ace
target logic is capable of receiving fast back- to-back cycles. RO
6User Definable Features
(UDF) Hardwired to ‘ 0’. RO
5 66 MHz C apable Hardwired to ‘0. RO
4 PERR# Assertion Detect
This bit is set by hardware whenever the PERR# pin is
asserted on the rising edge of PCI clock. This in clu d e s ca ses
in which the chipset is the agent driving PERR#. It re mains
asserte d until clea re d by software writing a ‘1’ to this
location. W he n en abled by the PERR#-to-SERR# Enable bit
(in the Br id ge Control registe r), a ‘1’ in this bit can gen e rate
an internal SERR# and be a source for the NMI logic.
R/WC
3:0 Reserved Reserved.
Table 162. Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—
D30:F0)
Bits Name Description Access
Device: 30 Function: 0
Offset: 1E-1Fh Attribute: Read/Write
Defau lt Value: 0280h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 297
7—Intel® 6300ESB ICH
7.1.18 Offset 22 - 23h: MEMLIM—Memory Limit Register
(HUB-PCI—D30:F0)
This register defines the upper limit of the Hub Interface to PCI non-prefetchable
memory range. Since the Intel® 6300ESB ICH will forward all Hub Interface memory
accesses to PCI, the Intel® 6300ESB ICH will only use this information for determining
when not to accept cycles as a target.
This register must be initialized by the configuration software. For the purpose of
address decode, address bits AD[19:0] are assumed to be FFFFFh. Thus, the top of the
defined memory address range will be aligned to a 1 Mbyte boundary.
Table 163. Offset 20 - 21h: MEMBASE—Memory Base Register (HUB-PCI—D30:F0)
Bits Name Description Access
15:4 Memory Address B a se Defines the base of the memory range for PCI. These 12 bits
co rre sp on d t o a d dress bit s 31:20. R/W
3:0 Reserved Reserved.
Device: 30 Function: 0
Offset: 20-21h Attribute: Read/Write
Defau lt Value: FFF0h Size: 16-bit
Tab l e 16 4. Of fse t 22 - 23h : ME ML IM —Me m ory Lim it Re g ist er (HU B- P CI D3 0: F0 )
Bits Name Description Access
15:4 Memory Address Limit Defines the top of the memory range for PCI. These 12 bits
co rre sp on d t o a d dress bit s 31:20. R/W
3:0 Reserved Reserved.
Device: 30 Function: 0
Offset: 22-23h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
298 Order Number: 300641-004US
7.1.19 Offset 24h - 25h: PREF_MEM_BASE—Prefetchable
Memory
Base Register (HUB-PCI—D30:F0)
Offset Address: 24h-25h Attr ibute: R/W
Default Val ue: 0000FFF0h Size: 16-bit
This register defines the Base Address of the Hub Interface-to-PCI prefetchable
memory range. Since the Intel® 6300ESB ICH will forward all Hub Interface memory
acc ess es to PCI, the In te l® 6300ESB ICH will only use this information for determining
when not to accept cycles as a target.
Note: When the Hub Interface is acting as the initiator, it will not respond as a target.
This register must be initialized by the config software. For the purpose of address
decode, address bits AD[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be aligned to a 1 Mbyte boundary.
Table 165. Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory Base
Register (HUB-PCI—D30:F0)
Bits Name Description Access
15:4 Prefetchable Memory
A d dress B a se
Defi nes the base add ress o f th e prefet chable m emory addr ess
r a nge for PCI. These 12 bits corre spon d to addres s bit s
31:20. R/W
3:0 Reserved Reserved. RO
Device: 30 Function: 0
Offset: 24h-25h Attribute: Read/Write
Defau lt Value: 0000FFF0h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 299
7—Intel® 6300ESB ICH
7. 1.20 Offset 26h-27h: PR EF_MEM_MLT Prefetchable
Memory
Limit Register (HUB-PCI—D30:F0)
This register defines the upper limit of the Hub Interface-to-PCI non-prefetchable
memory range. Since the Intel® 6300ESB ICH will forward all Hub Interface memory
accesses to PCI, the Intel® 6300ESB ICH will only use this information for determining
when not to accept cycles as a target.
Note: When the Hub Interface is acting as the initiator, it will not respond as a target.
Note: This register must be initialized by the config software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be aligned to a 1 Mbyte boundary.
7.1.21 Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16
Bit s Regis ter (H UB-PCI—D30:F0)
Table 166. Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory Limit Register
(HUB-PCI—D30:F0)
Bits Name Description Access
15:4 Prefetchable Memory
Address Limit
Defi ne s the limit address of the prefet chable me mory address
range for PCI. These 12 bits correspond to address bits
31:20. RW
3:0 Reserved Reserved. RO
Table 167. Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-
PCI—D30:F0)
Bits Name Description Access
15:0 I/O Address Base Upper
16 bits [31:16] Not supp orted; hardwired to 0. RO
Device: 30 Function: 0
Offset: 26h-27h Attribute: Read/Write
Defau lt Value: 00000000h Size: 16-bit
Device: 30 Function: 0
Offset: 30-31h Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
300 Order Number: 300641-004US
7.1. 22 Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16
Bit s Regis ter
(HUB-PCI—D30:F0)
7.1.23 Of fset 3Ch: INT_LINE—Interr upt Line Register
(HUB-PCI—D30:F0)
Tabl e 168. Offset 32 - 33h: IOLI M_HI—I/O Limit Upper 16 Bits Register (HUB-
PCI—D30:F0)
Bits Name Description Access
15:0 I/O A ddress L imit Upper
16 bits [31 :16] Not supporte d; hardw i red to 0. RO
Table 169. Offset 3Ch: INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:0 Interrupt Line Routing Hardwired to 00h. The bridge does not generate interrupts,
and in terrupts from downstream devices are routed around
the bridge. RO
Device: 30 Function: 0
Offset: 32-33h Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Device: 30 Function: 0
Offset: 3Ch Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 301
7—Intel® 6300ESB ICH
7. 1.24 Off set 3E - 3Fh: BRIDGE_C NT—Bri dg e Contro l
Register (HUB-PCI—D30:F0)
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)
(Sheet 1 of 3)
Bits Name Description Access
15:1
1Reserved Reserved.
12 PERR# to SERR# Enab le
When th is b it is se t to ‘1’ PCI PERR N M I reporting is enab le d.
In addition to setting this bit, you also must set b it 1 of
D30_F0 PNE Register. Section 7.1.28
When this bit is set to a ‘1’ and PERR# is asserted on PCI, the
PERR# As sertion detect status bit (in the Secondary Statu s
Register) will indicate a PERR# inte rnal SERR# assertion. The
SE R R # can b e a s so u r ce on N M I.
RW
11 Discard Ti me r S E RR#
Enable (DTSE)
Controls the gener ation of SERR# on the primary interface in
response to a ti me r d isca rd on the se conda ry in te rface:
When ‘0’: Do not ge nerate SERR# on a secondary timer
discard
Wh en ‘1’: Generate SERR# in res ponse to a secondary
timer discard.
This bit replaces bit 1 of off set 90h, which held this function in
ICH3.
R/W
10 Discard Timer Status
(DTS)
This bit is set to a ‘1’ whe n the se condary di scard timer
expires (there is no discard time r for the prima ry inte rface).
This bit replaces bit 1 of off set 92h, which held this function in
ICH3.
R/W
9Se condar y D iscard
Timer (SDT)
Sets the maximum numbe r of PCI clock cycles that the Intel ®
6300ESB ICH waits for an initiator on PCI to repe at a delayed
transac tion request. The counter starts once the delayed
transaction completion is at the head of the queue. When the
master has not repeated the transaction at least once before
the cou nte r exp ire s, the Intel® 6300ESB ICH d isc ard s the
transaction from it s queu e .
When ‘0’: The PCI master timeout value is between 215
and 216 PCI clock s
When ‘1’: The PCI master timeout value is between 210
and 211 PCI clock s
R/W
8Primary Discard
Timer (PDT)T h is b it is RW fo r sof twa re compatib ility on ly. R/W
7 F ast Back to Back Enable Hardwir e d to ‘0’. The PCI log ic will not g enerate fas t bac k-to-
back cycles on th e P CI b u s.
Device: 30 Function: 0
Offset: 3E-3Fh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
302 Order Number: 300641-004US
6Secondary Bus Reset
Controls PXPCIRS T# assertion on PCI(X).
1 = The Intel® 6300ESB ICH asserts PCIXSBRST#. W he n
PCIXSBR ST# is asserted, the data buffers between the
Hub Interface and PCI(X) and the PC I(X ) bus are
initialized back to reset conditions. The Hub Interface and
the configuration registers are not affected.
0 = The Intel® 6300ESB ICH deas serts PCIXSBRST#
R/W
5Master Abort Mode
This bit controls the behavior of the Inte l® 6300ESB ICH
when a master abort occurs on a tr ansactio n that crosses the
Hub Interface-PCI bridge in either direction. The default is 0.
When set to 0, the Intel® 6300ESB ICH b e haves in the
following manne r:
H ub Interf a ce Completion-Requir ed req ue sts to PCI:
When these master abo rt on PCI, the Intel ® 6300ESB ICH
returns a master abort statu s. For read s, FFFFh is
returned for ea ch DWORD.
Hub Interface Pos ted Writes to PCI: When these master
abort on PCI, the Intel® 6300ESB ICH discards the data.
PCI Reads to Hub Interface: When these master abort on
Hub Interf a ce, the Intel® 6300ES B ICH re turns the data
provided wi th the Hub Interface master abort packet to
the PCI requestor.
PCI writes to Hub Inte rf ace : Inte l® 6300ESB ICH has no
idea when these “master-abort.
When set to 1, the Intel® 6300ESB ICH treats the master
abort as an error:
H ub Interf a ce Completion-Requir ed req ue sts to PCI:
When these master abo rt on PCI, the Intel ® 6300ESB ICH
returns a target abort status. For reads, FFFFh is returned
for each DWORD.
Hub Interface Pos ted Writes to PCI: When these master
abort on PCI, the Intel® 6300ESB ICH discards the data
and sets the Prim ary Si gnal ed SERR# b it (whe n the
corresponding SER R_E N b i t is se t) .
PCI Reads to Hub Interface: When these master abort on
Hub Interf a ce, the Intel® 6300ES B ICH te rminates the
cycle with a target abort and flushes the remainder of the
prefetched data.
PCI writes to Hub I nter fac e: The In tel ® 6300ESB ICH has
no idea when these “master-abort.
R/W
VGA 16-Bit Decode
This bit does not have any functionali ty relative to address
decode s bec ause the Int el® 6300ESB ICH will forward the
cycles to PCI, independent of the dec ode. Wr ites of o ne have
no impact othe r than to fo rce the bit to one . Writes of zero
have no impact oth er tha n to force the bit to zero. Reads to
this bit will return the previously written value (or zero when
no writes since reset).
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)
(Sheet 2 of 3)
Bits Name Description Access
Device: 30 Function: 0
Offset: 3E-3Fh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 303
7—Intel® 6300ESB ICH
3VGA Enable
0 = No VGA device on PCI.
1 = Indicates that the VGA device is on PCI. Therefore, the
PCI to Hub Inte rf a ce dec oder w ill not accept memory
cycles in the range A0000h-BFFFFh. Note that the Intel®
6300ESB ICH will nev er take I/O cy cles in the VGA range
from PC I. If VG A is enable d on PCI-X Brid ge D evic e 28
Function 0, offset 3Eh, bit 3. PCI-X will claim memory
cycles in the VGA range before the legacy PCI Bridge.
R/W
2ISA Enable
The I n t e l® 6300ESB ICH ignores this b it. Howe ver, this bit is
read/write for software compatibility. Since the Intel®
6300ESB ICH forwards all I/O cycles that are not in the USB,
AC’9 7 , or IDE r anges to PCI, this bit would h ave n o effec t.
ISA should be enabl ed on the leg a cy PCI or the PCI/PCI-X
bridge, but NOT both. If both are enabled, unpredictable
results will occur.
R/W
1 S ERR# Enab le
0 = D isa b le
1 = Whe n this b it is set AN D bit 8 in CMD register (D30:F0
Offset 04h) is also set, the Intel® 6300ESB ICH will set
the SSE bit in PD_STS reg ister (D 30:F0, offset 06h, b it
14) an d also generate an NMI (or SMI# if NMI routed to
SMI) when the SERR # signal is asserted. T he internal
SERR# wil l be generated on ly if the SERR_EN bi t is also
set in offset 04h.
NOTE: See Section 5.1.4, “SERR# Functionality” for more
details on this bit.
R/W
0Parity Error Response
Enable
0 = D isa b le
1 = Enable the Hub Interface to PCI bridge for parity error
detection and reporting on the PCI bus. R/W
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)
(Sheet 3 of 3)
Bits Name Description Access
Device: 30 Function: 0
Offset: 3E-3Fh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
304 Order Number: 300641-004US
7.1.25 Of fset 40 - 43h: HI_ CMD—Hub Interface
Command Control
Register (HUB-PCI—D30:F0)
Table 171. Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register
(HUB-PCI—D30:F0)
Bits Name Description Access
31:2
0Reserved Reserved.
30:2
8SATA Hub ID Thi s field ident ifies t he Hub Inter face ID number for the Ser ial
ATA requ ests on the H ub Inter fac e. Def ault=111b RO
27 Reserved Reserved. RO
26:2
4Second Hub ID This field identifies the Hub Interface ID number for
integrated re q ue sters. Default=110b RO
23:2
1First Hub ID This field identifies the Hub Interface ID number fo r
integrated requesters. Hardwired to 001b RO
20 Hub Interface Parity
Unsupported
When set to 1, the Intel® 6300ESB ICH will not che ck p arity
on th e Hub Interfac e even if en abled t o d o so accordi ng to the
Parity Error Response bit in D30.F0.04h bit 6 or if the Parity
Error Response b it of D28.F0.04h bit 6 is set.
R/W
19:1
6Hub Interface Time slice
This field sets the Hub Inte rf a ce a rbite r time -slice value with
four base-clock granularity. A value of 0h means that the
time-slice is immediately expired and that the Intel®
6300E SB ICH will allow the othe r master’s request to be
serviced after every message.
R/W
15:1
4HI Width This field is hardwired to 00b, indicating that the Hub
Interface is eig ht bi ts wid e . RO
13 HI Rate_ Valid Hardwired to ‘1’. RO
12:1
0HI Rate
Encoded value r epresenting the clock-to-transfer rat e of the
Hub Interface: 1:4 = 010b
The value is loa d e d at rese t b y sampling the ca pability of the
device connected to the Hub Interface port. The value for this
fiel d i s fi xed for 4 x mo de only.
RO
9:4 Reserved Reserved.
3:1 Max Dat a (MAXD )
Hardwire d to 001b. This f ie ld spe cif ie s the maximum a mount
of data that the Intel® 6300ES B ICH is allowed to burs t in
one packet on the Hub Interface. T he Intel® 6300ESB ICH
will always do 64 byte bur sts.
RO
0 Reserved Reserved.
Device: 30 Function: 0
Offset: 40-43h Attribute: Read/Write
Defau lt Value: 76202802h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 305
7—Intel® 6300ESB ICH
7. 1.26 Offset 44 - 45h : DEVICE_HIDE—Seconda ry PCI
Device
Hiding Register (HUB-PCI—D30:F0)
This register allows software to “hide” PCI devices. Specifically, when PCI devices are
hidden, the configuration space is not accessible because the PCI IDSEL pin does not
assert. The Intel® 6300ESB ICH supports the ability to hide four external devices (0
through 3).
Hiding a PCI device may be useful for debugging, bug work-arounds, and system
management support. Devices should only be hidden during initialization before any
conf i gur a ti on cy cl es are r un. This ensur es th at th e d evice i s not in a sem i- enab l e state .
Table 172. Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hidin g Register
(HUB-PCI—D30:F0)
Bits Name Description Access
15:9 Reserved Reserved.
8 Reserved Reserved.
7:6 Reserved Reserved.
5 Reserved Reserved.
4 Reserved Reserved.
3 HIDE_DEV3 Same as bit 0 of this register, except for device 3 (AD{19]).
2 HIDE_DEV2 Same as bit 0 of this register, except for device 2 (AD{18]).
1 HIDE_DEV1 Same as bit 0 of this register, except for device 1 (AD[17])
0HIDE_DEV0
When this b it is se t, it hides de v ice 0 on the PCI bus . This is
done by mask ing the IDSEL (keeping it low) for configuration
cycles to tha t device. S ince the device will not see its IDSEL
go activ e , it will not re sp ond to PCI conf iguratio n cyc le s an d
the processor will think the device is not present. AD[16] is
used as IDSEL for device 0.
When this b it is a 0, the PCI con f ig u ration cy cle s for this slot
are not affected.
Device: 30 Function: 0
Offset: 44-45h Attribute: Read/Write
Defau lt Value: 00h Size: 16-bit
Power Well: 00h
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
306 Order Number: 300641-004US
7.1.27 Offse t 50 - 51h: CNF—Intel® 6300 ESB ICH
Configurat ion Register ( HUB-PCI—D30:F0)
NOTE: Refer to th e lat est re v ision of the Intel® 6300ESB ICH BIOS Specification for the
recom me n d e d c on f iguratio n of this registe r.
Table 173. Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register
(HUB-PCI—D30:F0)
Bits Name Description Access
15:1
4Reserved Reserved.
13 Prefetch Flush Enable
Prefetch Flu sh Enab le.
0 = Prefetch Flush Disable
1 = Causes CP U to PCI log ic to only deliver “Demand” data
for a delayed transa ction if a processor-to-PCI write has
occu rre d since th e d el aye d transaction was initiated.
(Default)
NOTE: Th is bit m ust b e set by system B I OS.
R/W
12:1
0Reserved Reserved.
9 HP_PCI_EN
High Priority PCI En ab le
0 = All PCI REQ#/GNT pairs ha ve the same arbitration
priority.
1 = Enables a mode where the REQ[0]#/GNT[0]# sig nal pair
has a hig her arb i tration priority.
R/W
8Ho le Enable (15 MB -16
MB) 0 = Disabl e
1 = Enabl es the 15 Mbyte to 16 Mbyte hole in the DRAM. R/W
7 Reserved Reserved.
6HI-PCI Write Combining
Enable HI-PCI Write Combining Enable
1 = Disa bl es H ub Interf ace to PCI Write comb ining R/W
5:3 Reserved Reserved.
2Delayed Transaction
Discard Timer
De la yed Tra nsa ction Discard Timer
When set to 1 this bit shortens all delayed tr ansaction discard
timers to 128 PCI clocks. R/W
1:0 Reserved Reserved.
Device: 30 Function: 0
Offset: 50-51h Attribute: Read/Write
Defau lt Value: 1400h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 307
7—Intel® 6300ESB ICH
7.1 .28 Offs et 58 - 5Bh: D3 0_PN E — P ERR #_NMI _ENA BLE
Register (HUB-PCI—D30:F0)
Table 174. Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-
PCI—D30:F0)
Bits Name Description Access
31:2
2Reserved Reserved.
21:2
0Ou tstand ing SATA Mem
Read Acceptance
Indicate the number of outstanding (not completed) memory
read reques t s from S ATA that are accepted. The value of the
bits is decoded as fo llows:
00 = Disab le th is f e a ture by allowing Stunit to accep t an y
num ber of ou tstanding me mory reads f rom SATA u nt il its
buff er resourc es are full .
11 Accepts four outstanding reads from SATA. Default
NOTE: D e faul t value is 11b, BIOS must write 00 to this
register
R/W
19:8 Reserved Reserved.
7SATA Request Enable
0 = The arbit er wi l l bl o ck S-ATA requests w hen th ere i s a loc k
transaction targ eting PCI X .
1 = the arbiter will allow S- A TA requests even when there is a
lock transaction targe ting PCIX.
NOTE: Default value should be 0b, BIOS must write 1 to this
register
6:3 Reserved Reserved.
2PCI-X PERR NM I
Reporting
This b it en ables PCI-X PERR NMI reporting .
When this bit is set to ‘1’ PCI-X PERR NMI repor ting is
enab le d . Once enabled, this bit should not cha ng e . In
addition to setting this bit, you also must set bit 12 of D30_F0
Bridge Cont r ol Register. See secti on Section 18.6.1.21.
Def a u lt = 0
R/W
1PCI PERR NMI Reporting
This b it en ables PCI PERR N M I repo rting .
When th is b it is se t to ’1’ PCI PERR N M I reporting is enab le d.
Once enabled, this bit should not change. In addition to
sett ing thi s bit, you also must set bit 12 of D30_F0 Brid g e
Co ntrol Reg ister. See se ction Section 18.6.1.21. Default = 0
R/W
0 Reserved Reserved.
Device: 30 Function: 0
Offset: 58-5Bh Attribute: Read/Write
Defau lt Value: 01341150h Size: 32-bit
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
308 Order Number: 300641-004US
7.1.29 Offset 70h: MTT—Multi-Transaction Timer
Register
(HUB-PCI—D30:F0)
MT T is an 8-bit regi ster t hat co ntrol s the a mount of time t hat the In te l® 6300E SB ICH ’s
a rbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI
bus. The Intel® 6300ESB I CH’s MTT mechanism is used to ensure a fair share of the
P ri ma r y PCI ban dw i dth to an initia t or that p er fo r ms mu lt ip l e ba ck-to- b a ck tr a nsa ct ions
to fragmented memory ranges (and as a consequence it may not use long burst
transfers).
The number of clocks programmed in the MTT represents the ensured time slice
(me as ured in PCI cloc ks) allotte d to the curr ent agent, after whi ch th e arbi ter will gra nt
anot her agent that is requesting the bus. The MTT value must be programmed with 8-
clock granularity in the same manner as MLT. For example, if the MTT is programmed to
18 h, then the selected value corresponds to the time period of 24 PCI clocks.The
default value of MTT is 20h (32 PCI clocks).
Note: Progra mming the MTT to a value of 00h disables this function, which could cause
starvation problems for some PCI master devices. Programming of the MTT to anything
less than 16 clocks will not allow the Grant-to-FRAME# latency to be 16 clocks. The
MTT timer will timeout before the Grant-to-FRAME# trigger causing a rearbitration.
Table 175 . Offse t 70h : MTT Mu lti-T ra nsa c tio n Time r Re gis te r (HUB - PCI
D30:F0)
Bits Name Description Access
7:3 Multi-Transa ction Timer
Count Value
This field sp e cif ie s the a mount of time tha t grant will remain
asserted to a mas te r con tinuously a sserting its re q u e st f or
multi ple tra nsf e rs. This fie ld sp ec if ie s th e coun t in an 8-clock
(PCI clock) granularity.
R/W
2:0 Reserved Reserved.
Device: 30 Function: 0
Offset: 70h Attribute: Read/Write
Defau lt Value: 20h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 309
7—Intel® 6300ESB ICH
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)
7. 1.31 Offset 90h: ERR_CMD—Error Com ma nd Re gister
(HUB-PCI—D30:F0)
Note: This register configures the Intel® 6300ESB ICH’s Device 30 responses to various
system errors. The actual assertion of the internal SERR# (routed to cause NMI# or
SMI#) is enabled through the PCI Command register.
Table 176. Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—
D30:F0)
Bits Name Description Access
7Internal South PCI
Master Request Status
(INT_MREQ_STS)
Allows software to se e if the internal DMA con troller or LPC
has requested use of the PCI bus.
0 = Sof twa re cle ars this bit by w riting a ’1‘to the b it po sition.
1 = The Intel® 6300ESB ICH’s internal DMA controller or LPC
has requested use of the PC I bus.
R/WC
6:4 Reserved Reserved.
3:0 PCI Master Request
Status (PCI_MREQ_STS)
Allows software to se e if a particular b us ma ster has
requested use of the PCI bus.
0 = Sof twa re cle ars the se bits by writing a 1 to the bit
position.
1 = The associated PCI master has requested use of the PCI
bus.
R/WC
Table 177. Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Bits Name Description Access
7:3 Reserved Reserved.
2SERR# Enable on
Re cei v ing Target A bo rt
(SERR_RTA_EN)
0 = D isa b le .
1 = Enab le. W he n SERR _EN is set, the Intel® 6300ESB ICH
will report SERR# when SER R_RTA is set. R/W
1:0 Reserved Reserved. Bit 1 was the SERR# Enabled for Delayed
Transaction Timeout, see Section 7.1.24, “Offset 3E - 3Fh:
BRIDG E _CNT—Bri dge Control Register (HUB -PCI—D 30:F0)”.
Device: 30 Function: 0
Offset: 82h Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Device: 30 Function: 0
Offset: 90h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—7
Intel® 6300ESB I/O Controller Hub
DS November 2007
310 Order Number: 300641-004US
7.1.32 Offset 92h: ERR_STS—Error Status Register
(HUB-PCI—D30:F0)
Note: This register records the cause of system errors in Device 30. The actual assertion of
SERR# is enabled through the PCI Command register.
7.1.33 Offset F8h - FBh : MANID— Ma nufacturer’s ID
Table 178. Offset 92h: E RR_STS—Error Status Register (HUB-PCI D30:F0)
Bits Name Description Access
7:3 Reserved Reserved.
2SERR# D ue t o Receiv ed
Target Abort
(SERR_RTA)
0 = This bit is cleared by wri ti n g a 1.
1 = Intel® 6300ESB ICH se ts this bit when the Inte l®
6300ESB ICH re ceiv es a target abort. When SERR_EN,
the Int el® 6300ES B ICH will also generate an SERR#
when SER R_RTA is set.
R/W
1:0 Reserved Reserved. Bit 1 wa s th e S E R R# E na bled for De layed
Tran saction Timeout, se e S ection 7.1 .24, “Of f se t 3E - 3Fh:
BRIDGE_CNT—Bridge Control Register (HUB-PCI —D30:F0)”.
Table 179. Offset F8h - FBh: MANID— Manufacturer’s ID
Bits Name Description Access
31:1
6Reserved Reserved.
15:8 Manufacturer 0Fh = Inte l RO
7:0 P rocess/Dot 66h = Process 859.6 RO
Device: 30 Function: 0
Offset: 92h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 30 Function: 0
Offset: F8h-FBh Attribute: Read-Only
Defau lt Value: 0000 0F66h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 311
8—Intel® 6300ESB ICH
LPC I/F Bridge Registers
(D31:F0) 8
The LPC Bridge function of the Intel® 6300ESB ICH resides in PCI Device 31:Function
0. This function contains many other functional units, such as DMA and Interrupt
Controllers, Timers, Power Management, System Management, GPIO RTC and LPC.
Registers and functions associated with other functional units (USB UHCI, USB EHCI,
IDE, etc.) are described in their respective sections.
8.1 PCI Configuration Registers (D31:F0)
Note: Registers that are not shown should be treated as reserved. (See Section 6.2, “PCI
Configuration Map” for details).
.
Table 180. PCI Configuration Registers (D31:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Type
00-01h V ID Ve nd or ID 8086h RO
02-03h DID Dev ice ID 25A1h RO
04-05h PCICMD PCI Command Register 00 0Fh R /W
06-07h PCIS TA PCI Device Status 0280h R /W
08h RID Revisi on ID See NOTE: RO
09h PI Programmi ng Inter face 00 h RO
0Ah SCC Sub Class Cod e 01 h RO
0Bh BCC Base Class Code 06h RO
0Eh HEADTYP He ader Type 80h RO
40-43h PMBASE ACPI Base Add ress 00000001h R/W
44h A CPI_CNTL AC PI Control 00h R /W
4E-4Fh BIOS_CNTL BIOS Control 0000h R/W
54h TC O _ C NTL TCO C o n t rol 00h R/W
58-5B h GPIO_BASE GPIO Base Address 00000001h R/W
5Ch GPIO_CNTL GPIO Contr ol 00h R /W
60-63h PIRQ[n]_RO UT PIRQ[A-D] Routing Contro l 80808080h R/W
64h SE RIRQ Serial IRQ Contr ol 50h R/W
68-6Bh PIRQ[n]_ROUT PIRQ[E-H] Routing Control 80808080h R/W
88h D31_ERR_CFG Dev ice 31 Error Config 00h R /W
8Ah D31_ERR_STS Device 31 Err or S tatus 00 h R/W
90-91h PCI_DMA_CFG PCI DMA Confi guration 0000h R /W
NOTE: Refer to the Intel® 6300ESB ICH S p ec if ica tion Update for the most up-to-date value of
th e Revisio n ID re gist e r.
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
312 Order Number: 300641-004US
8.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/
F—D31:F0)
A0-CF h Power Manage ment
D0-D3h GEN_CNTL General Control 00000080h R/W
D4h GEN_ST A General Status 0Xh R/W
D5h BACK_CNTL Backed Up Control 00f R/W
D8h RTC_CONF Rea l Tim e Clo ck Conf ig urat ion 00h R/W
E0h COM_DEC LPC I/F CO M Port Decode Ranges 00h R/W
E1h FDD/LPT_DEC LPC I/F FDD and LPT Dec ode
Ranges 00h R/W
E2h SND_D EC L PC I/F S ound Dec od e Ranges 00h R/W
E3h FWH_DEC_EN1 F WH Decode Enab le 1 FFh R/W
E4-E5h G EN 1_D EC LPC I/F Ge ne ral 1 Decode Range 0000h R/W
E6-E7h L PC_EN LPC I/F Enable s 00h R/W
E8-E Bh FW H_SEL1 FWH Select 1 00112233h R/W
EC-EDh GE N2_DEC L PC I/F G e ne ral 2 Decode Range 0000h R/W
EE-EFh FW H _S EL 2 FWH Select 2 5678h R/W
F0h FWH_D EC_EN 2 FWH Decode Enab le 2 0Fh R/W
F2h FUNC_DIS Function Disable R egister 0080h R/W
F4-F7h ETR1 PC I-X Extended Features 00000000h R/W
F8h-FBh Manufacturer ’s ID 000S 0F66 RO
Table 181. Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31 :F0)
Bits Name Description Access
15:0 Vendor ID Value This is a 1 6-b it value a ssig ne d to Inte l. In tel VID = 8086h RO
Table 180. PCI Configuration Regi sters (D31:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Ty pe
NOTE: Refer to the Intel® 6300ES B ICH S pecification U pdate for the most up-to-date value of
the Revision ID register.
Device: 31 Function: 0
Offset: 00-01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 313
8—Intel® 6300ESB ICH
8.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/
F—D31:F0)
8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0 )
Tab l e 18 2. O f fse t 02 - 03h : DID— D ev i ce ID Reg is te r (LPC I/F D3 1: F0 )
Bits Name Description Access
15:0 Device ID Value This is a 16-bit value assigned to the Intel® 6300ESB ICH LPC
Bridge.
Table 183. Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Bits Name Description Access
15:1
0Reserved Reserved.
9FBE : Fast B a ck to Back
Enable Hardwired to 0. RO
8SERR_EN: S ERR#
Enable 0 = D isa b le .
1 = Enable. Allow SERR# to be generated.
7 WCC: Wait Cycle Control Hardwir e d to 0. RO
6PER: Parity Error
Response
0 = No action is taken when detecting a parity error.
1 = The processor will take normal action when a parit y error
is detecte d .
5 VPS: VGA Palette Snoop Hardwir e d to 0 RO
4PMWE: Postable Memory
Write Enable Hardwire d to 0 RO
3SCE: Speci al Cycle
Enable Hardwired to 1.
2 BME: Bus Master Enable Hardwired to 1 to indicate tha t bus mastering cannot be
disabled for function 0 (DMA/ISA Master) RO
1MSE: M emory Sp ace
Enable Hardwired to 1 to indic ate that me mory space can not be
dis abl ed fo r Functi on 0 (LPC I/F) RO
0 IOE: I/O Space Enable Hardwir e d to 1 to indic a te that the I/O spac e cannot b e
disabled for function 0 (LPC I/F) RO
Device: 31 Function: 0
Offset: 02-03h Attribute: Read-Only
Defau lt Value: 25A1h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 000Fh Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
314 Order Number: 300641-004US
8.1.4 Offset 06 - 07h: PCISTA—PCI Device Status
(LPC I/F—D31:F0)
Table 184. Offset 06 - 07h: PCISTA—P CI Device Status (LPC I/F—D31:F0)
Bits Name Description Access
15 DPE: Detected Parity
Error
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = PERR# signal goes ac tive. Set even when t he PER bi t is 0 . R/W
14 SSE: Sig n ale d Sy s t em
Error
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = Set by the Intel® 6300ESB ICH n the SERR_EN bit is set
and the Intel® 6300ESB ICH generate s an SERR# on
function 0. The ERR_STS register may be read to
determine the cause of the SERR#. The SERR# may be
routed to cause S MI#, N MI, or inte rrupt.
R/W
13 RMA: Received Master
Abort
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = The Intel® 6300ES B ICH g e ne rated a master abor t on
PCI due to LPC I/F master or DMA cycles.
R/W
12 RTA: Received Target
Abort
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = The Intel® 6300ESB ICH receiv ed a target abort during
LPC I/F master or DMA cycles to PCI.
R/W
11 STA: Sign al ed Target
Abort
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = The Intel® 6300ESB ICH generate d a target ab ort
condition on PCI cyc le s cla imed by the Int e l® 6300ES B
ICH for In tel® 6300ESB ICH internal registers or for
going to LPC I / F.
R/W
10:9 DEV_STS: DEVSE L#
Timing Status 01 = M edium Tim ing. RO
8DPED: Data P arity Error
Detected
0 = This bit is cleared by software writing a 1 to the bit
position.
1 = Set when all three of the following conditions are true:
- The Intel® 6300ESB ICH is the initiator of the cycle,
- The Intel® 6300ESB ICH asserted PERR# (for reads) or
observed PERR# (f or writes), and
- The PER bit is set.
R/WC
7 FB2 B: Fast Back to Back Always 1. Indicate s the Intel® 6300ESB ICH as a target may
accept fast back-to - back trans a ction s. RO
6UDF: User Definable
Features Hard wire d to 0
566MHZ_CAP: 66 MHz
Capable Hardwire d to 0 RO
4:0 Reserved Reserved.
Device: 31 Function: 0
Offset: 06-07h Attribute: Read/Write Clear
Defau lt Value: 0280h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 315
8—Intel® 6300ESB ICH
8.1.5 Offse t 08h: RID—Revision ID Re gist er (LP C I/F—
D31:F0)
8.1 . 6 Offs et 09 h: PI—Pro gra m min g I n terface (LPC I/F—
D31:F0)
8.1.7 Off set 0Ah: SCC—Sub-Class Code Reg ister
(LPC I/F—D31:F0 )
Table 185. Offset 08h: RID—Revision ID Register (LPC I/F—D31:F0)
Bits Name Description Access
7:0 R evision ID Value Refer to the Intel® 6300ESB ICH Specification Update for t he
most up -to-d a te value of th e Revision ID Register. RO
Table 186. Offset 09h: PI—Programming Interface (LPC I/F—D31:F0)
Bits Name Description Access
7:0 Programming Interface
Value Programm ing Interfa ce Value. RO
Table 187. Offset 0Ah: SCC—Sub-Class Code Register (LPC I/F—D31:F0)
Bits Name Description Access
7:0 Sub-Class Code 8-bit value that indicates the categ ory of brid g e for the L PC
PCI bridge. RO
Device: 31 Function: 0
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descript io n Size: 8-bit
Device: 31 Function: 0
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 0
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
316 Order Number: 300641-004US
8.1.8 Offset 0Bh: BCC—B ase-Class Code Register
(LPC I/F—D31:F0)
8.1.9 Offset 0Eh: HEADTYP—Header Type Register
(LPC I/F—D31:F0)
Table 188. Offset 0Bh: BCC—Base-Class Code Register (LPC I/F—D31:F0)
Bits Name Description Access
7:0 Base Class Code 8-b it value that ind icate s the typ e of device for the LPC
bridge. The code is 06h in d ica ting a bridge d evice. RO
Table 189. Offset 0Eh: HEADTYP—Header Type Register (LPC I/F—D31:F0)
Bits Name Description Access
7 Multi-Function Device This bit is 1 to indicate a multi-function device. RO
6:0 Header Type 7-bit field identifies the header layout of t he configuration
space. RO
Device: 31 Function: 0
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 06h Size: 8-bit
Device: 31 Function: 0
Offset: 0Eh Attribute: Read-Only
Defau lt Value: 0Eh Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 317
8—Intel® 6300ESB ICH
8.1.10 Offset 40 - 43h: PMBASE—ACPI Base Address
(LPC I/F—D31:F0 )
Note: Usage: ACPI or Legacy.
Note: Sets base address for ACPI I/O registers and TCO I/O registers. May be mapped
anywhere in the 64K I/O space on 128-byte boundaries.
8.1.11 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F
D31:F0)
Note: Usage: ACPI or Legacy.
Table 1 90. Offset 40 - 43h: PMBASE—ACPI Base Address (LPC I/F—D31:F0)
Bits Name Description Access
31:1
6Reserved Reserved.
15:7 Base Address Provides 128 by te s of I/O sp ace for ACP I , GPIO, and TCO
logic . This is placed on a 128- byte bo und ary. R/W
6:1 Reserved Reserved.
0 Resource Indicator Tied to 1 to indicate I/O spa ce. RO
Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 1 of
2)
Bits Name Description Access
7:5 Reserved Reserved.
Device: 31 Function: 0
Offset: 40-43h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: 44h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
318 Order Number: 300641-004US
4 A CPI_EN: A CPI Enable
0 = Disabl e.
1 = Decode of the I /O range pointed to by the ACPI base
register is enabled, and the ACPI power management
function is enable d . N ote th at the APM powe r
management ranges (B2/B3h) are always enabled and
are not affected by this bit.
R/W
3 Reserved Reserved.
2:0 SCI_IRQ _S EL: SCI IRQ
Select
Speci fies on wh ich IRQ th e SCI will inter nally appe a r. Wh en
not using the APIC, the SC I must be routed to IRQ9-11, and
that interrupt is not shared with the SERIRQ stream, but may
be shared with other PCI interrupts. When using the APIC,
the SC I may also be mapped to IRQ20-23, and may be
shared with other interrup ts.
Bits SCI Map
000 IRQ9
001 IRQ10
010 IRQ11
011 Reserved
100 IRQ20 (Only available when A PIC e nabled)
101 IRQ21 (Only available when A PIC e nabled)
110 IRQ22 (Only available when A PIC e nabled)
111 IRQ23 (Only available when A PIC e nabled)
NOTE: W he n the int errup t is map p e d to APIC inte rrupts 9,
10, or 11, th e APIC sho u ld be prog ramme d for active-
high rec e pti o n. When t he i n terru pt is mapped to APIC
interrupts 20 throug h 23, the A PIC should be
programmed for active-low reception.
R/W
Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 2 of
2)
Bits Name Description Access
Device: 31 Function: 0
Offset: 44h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 319
8—Intel® 6300ESB ICH
8. 1.12 Offset 4E - 4Fh: BI OS_C NTL (LP C I/F—D31:F0)
Table 192. Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0)
Bits Name Description Access
15:2 Reserved Reserved.
1 BLE: BIOS Lock Enable 0 = Setting the BIOSW E will not cause S M Is. Onc e s et, this
bit may o nly be cleared by a PXPCIRST # .
1 = Enab les setting the BIOSWE bit to cause SM Is. R/W
0BIOSWE: BIOS Write
Enable
0 = On ly read cycles result in FWH I/F cy cle s.
1 = Access to the BIOS space is enabled for both read and
write c ycles . Wh en this bit is writte n f rom a 0 to a 1 and
BIOS lock Enab le (BLE) is also set, an SMI# is generated.
This ensures that only SMI code may update BIOS.
R/W
Device: 31 Function: 0
Offset: 4E-4Fh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
320 Order Number: 300641-004US
8.1.13 Offset 54h: TCO_CNTL—T CO Control (LPC I/F—
D31:F0)
Table 193. Offse t 54h: TCO_CN TL—T CO Control (LPC I/F—D31 :F0)
Bits Name Description Access
7:4 Reserved Reserved.
3TCO_INT_EN: TCO
In te rru p t En able
This bit enables/disables the TCO interrupt.
0 = Disa bl es TCO interrup t.
1 = Enabl es TCO Interrupt, a s selected by the TCO_INT_SEL
field.
R/W
2:0 TCO_INT_SEL : TCO
Inter rupt Select
Speci fies on which IRQ th e TCO wil l inte rn ally a ppe ar. When
not using the A PIC, the TCO interrup t must be routed to
IRQ9-11, a nd that inte rrup t is not sh a red wit h the SERIRQ
stream , but may be share d with other PCI inte rrupts. When
using the AP IC, the TCO interrup t ma y also be mappe d to
IRQ20-23, and may be shared with other inte rrupt. Note that
when the TCOSCI_EN b it is set (bit 6 of the GPEO_EN
register), the TCO interrupt will be sent to the same interrupt
as the SCI, a nd the TCO_INT _SEL bits will have no me a ning .
When th e TCO in terru pt is mapped t o APIC interrupt s 9, 10 or
11, the signal is in fact active high. When the TCO interrupt is
mapp ed to IRQ 20, 21, 22, or 23 the sig nal is ac tive low and
may be shared with PCI inte rrupts that may be map p e d to
those sa me sig n a ls ( IR Qs).
Bits SCI Map
000 IRQ9
001 IRQ10
010 IRQ11
011 Reserved
100 IRQ20 (Only available when A PIC e nabled)
101 IRQ21 (Only available when A PIC e nabled)
110 IRQ22 (Only available when A PIC e nabled)
111 IRQ23 (Only available when A PIC e nabled)
R/W
Device: 31 Function: 0
Offset: 54h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 321
8—Intel® 6300ESB ICH
8.1 .14 Offs et 58h - 5Bh: GP IO_BA SE— GPI O Base Addr ess
(LPC I/F—D31:F0 )
Note: Sets base address for GPIO registers. May be mapped anywhere in the 64K I/O space
on 128-byt e boundarie s.
8.1.15 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—
D31:F0)
Table 194. Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address (LPC I/F—D31:F0)
Bits Name Description Access
31:1
6Reserved Reserved.
15:6 Base Address Provides the 64 bytes of I/O space for GPIO. R/W
5:1 Reserved Reserved.
0 Resource Indicator Tied to 1 to indicate I/O spa ce. RO
Table 195. Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
Bits Name Description Access
7:5 Reserved Reserved.
4 GPIO_EN: GPIO Enable
This bit enables/disables decode of the I/O range pointed to
by the GPIO base regi ster and enables/disables the GPIO
function.
0 = D isa b le .
1 = Enable.
R/W
3:0 Reserved Reserved.
Device: 31 Function: 0
Offset: 58h-5Bh Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: 5Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
322 Order Number: 300641-004US
8.1 .16 Offset PIRQA - 60h: PIRQ [n]_ ROUT—
PIRQ[A,B,C,D]
Routing Control (LP C I/F—D31:F0)
Table 196. Of fset PIRQA - 60h: PIRQ[n]_R OUT —PIRQ[ A,B,C,D ] Rou ting Control
(LPC I/F— D31:F0)
Bits Name Description Access
7IRQEN: Interrupt
Routing En ab le
0 = The corresp onding PIRQ is rout ed to one of the ISA-
compatible interr u p ts sp e cif ie d in bits[3:0].
1 = The PIRQ is not routed to the 82 59.
NOTE: BIOS must program this bit to “0” during POST for any
of the PIRQs that are being used. The value of this bit
may subsequen tly be chan ged by th e OS when s etti ng
up for I/O APIC int er rup t deliv e ry mod e .
R/W
6:4 Reserved Reserved.
3:0 IRQ Rout ing
(ISA comp a tib le )
Bits Mapping Bits Mapping
0000 = Reserved 1000 = Reserved
0001 = Reserved 1001 = IRQ9
0010 = Reserved 1010 = IRQ 10
0011 = IRQ3 1011 = IRQ11
0100 = IRQ4 1100 = IRQ12
0101 = IRQ5 1101 = Rese rved
0110 = IRQ6 1110 = IRQ14
0111 = IRQ7 1111 = IRQ15
R/W
Device: 31 Function: 0
Offset:
PIRQA - 60h, PIRQB -
61h,
PIRQC - 62h, PIRQD -
63h
Attribute: Read/Write
Defau lt Value: 80h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 323
8—Intel® 6300ESB ICH
8.1.17 Offset 64h: SERIRQ_CNTL—Serial IRQ Control
(LPC I/F—D31:F0 )
Table 197. Offset 64h: SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
Bits Name Description Access
7SIRQEN: Ser ial IRQ
Enable
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = S eria l IRQs will be re cognized. The SERIRQ pin will be
configured as SERIRQ. R/W
6SIRQMD: Serial IRQ
Mode Select
0 = The se rial IRQ machine will be in qu ie t mod e .
1 = The se rial IRQ machine will be in continuous m od e .
NOTE: For syste ms using Quiet Mode , this b it should be set
to 1 (Continuous Mode) for at least one frame after
co ming out of reset befor e switchi n g ba ck to Qu ie t
Mode . Fail ure to do so will re sult in the Intel ®
6300ESB ICH not reco gni zi ng SE RI RQ inter r upt s . In
order to enable UARTS, the LPC Master should be
programmed to be in continuous mode. UART by
default will be progra mme d to be in con tinuous m ode.
R/W
5:2 SIRQSZ: Serial IR Q
Frame S ize
Fixed field that indicates the size of the SERIRQ frame. In the
Intel® 6300ESB ICH, this f ie ld needs to be p rogrammed to 21
frames (0100 ). This is an offset from a base of 17 which is
the smallest data frame size.
R/W
1:0 SFPW: Start Frame Pulse
Width
This is the n umb e r of PCI clocks that the SERIRQ pin will be
driven low by the serial IRQ machine to signal a start frame.
In continuous mode, the Intel® 6300ESB ICH will drive the
start fr ame for the number of cl ocks specif ied. In quiet mo de,
the Intel® 6300ESB ICH will d riv e the star t frame f or the
number of clocks specified m inus one, as th e first clock was
driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
R/W
Device: 31 Function: 0
Offset: 64h Attribute: Read/Write
Defau lt Value: 10h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
324 Order Number: 300641-004US
8.1.18 Offset PIRQE - 68h: PIRQ[n]_R OUT—
PIRQ[E,F,G,H] Rou tin g
Contro l ( LPC I/F— D3 1:F0)
Table 198. Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control
(LPC I/F— D31:F0)
Bits Name Description Access
7IRQEN
Interrupt Ro uting Enabl e
0 = The corresp onding PIRQ is rout ed to one of the ISA-
compatible interr u p ts sp e cif ie d in bits[3:0].
1 = The PIRQ is not routed to the 82 59.
NOTE: BIO S mus t p rogram t his bit to ‘0’ du ring POS T f o r any
of the PIRQs that are being used. The value of this bit
may subsequen tly be chan ged by th e OS when s etti ng
up for I/O APIC int er rup t deliv e ry mod e .
R/W
6:4 Reserved Reserved.
3:0 IRQ Rout ing
(ISA comp a tib le )
0000 = Reserved1000 = Reserved
0001 = Reserved1001 = IRQ9
0010 = Reserved1010 = IRQ10
0011 = IRQ31011 = IRQ11
0100 = IRQ41100 = IRQ12
0101 = IRQ51101 = Reserved
0110 = IRQ61110 = IRQ14
0111 = IRQ71111 = IRQ15
R/W
Device: 31 Function: 0
Offset:
PIRQE - 68h, PIRQF -
69h,
PIRQG - 6Ah, PIRQ H -
6Bh
Attribute: Read/Write
Defau lt Value: 80h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 325
8—Intel® 6300ESB ICH
8.1.19 Offset 88h: D31_ERR_CFG—Device 31 Error Config
Register (LPC I/F—D31:F0)
Note: This register configures the Intel® 6300ESB ICH’s Device 31 responses to various
system errors. The actual assertion of SERR# is enabled through the PCI Command
register.
8.1.20 Offset 8Ah: D31_ERR_STS—Device 31 Error Status
Register (LPC I/F—D31:F0)
Note: This register configures the Intel® 6300ESB ICH’s Device 31 responses to various
system errors. The actual assertion of SERR# is enabled through the PCI Command
register.
Table 1 99. Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—
D31:F0)
Bits Name Description Access
7:3 Reserved Reserved.
2SERR_RTA_EN: SERR#
on Received Target
Abort Enable
0 = D isa b le . N o SERR# assertion on Receive d Target Abort .
1 = The Intel® 6300ESB ICH will generate SERR# if the
SERR_RTA i s set and if SERR_EN is set. R/W
1SERR_DTT_EN: S ERR#
on Delayed Transaction
Tim e out Ena ble
0 = D isa b le . N o SERR# assertion on Del aye d Tran sa ction
Timeout.
1 = The Intel® 6300ESB ICH will generate SERR# if the
SERR_DTT bit is set and if SERR_EN is s et .
R/W
0 Reserved Reserved.
Device: 31 Function: 0
Offset: 88h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
326 Order Number: 300641-004US
8.1.21 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA
Configuration (LPC I/ F—D31:F0)
Note: Since there is no ISA bus, the default is for DMA to be disabled. BIOS must set
pa rticul ar channe ls for LPC DMA . When ISA i s prese nt (thro ugh MoonIS A), cha nnels not
assigned to LPC should be assigned as Disabled.
Tab le 200. Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F
D31:F0)
Bits Name Description Access
7:3 Reserved Reserved.
2SERR_RTA: SERR# D ue
to Received Targ et Abort
0 = Software clears this bit by wr iting a 1 to the bit loc a tion.
1 = The Intel® 6300ESB ICH sets this bit when it receives a
target abort. When SERR_EN, the Inte l® 6300ESB ICH
will also generate an SERR# whe n SERR_RTA is set.
R/WC
1SERR_DTT: SER R# Due
to Delayed Transaction
Timeout
0 = Software clears this bit by wr iting a 1 to the bit loc a tion.
1 = When a PCI m aster d oe s not return for the data within 1
ms of the cycle’s completi on, the Inte l® 6300ESB ICH
clears the de layed transa ction and sets this bit. When
both SERR_DTT_EN a nd SERR_EN are set, the n Inte l®
6300ESB ICH will a lso generate an SERR# wh en
SERR_DT T is set.
R/WC
0 Reserved Reserved.
Table 201. Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—
D31:F0) (Sheet 1 of 2)
Bits Name Description Access
15:1
4Channe l 7 S e le ct
00 = Reserved
01 = Reserved
10 = Reserved
11 = LPC I/F DMA
R/W
13:1
2Channe l 6 S e le ct Same bit decod e a s f or Cha nn e l 7. R/W
11:1
0Channe l 5 S e le ct Same bit decod e a s f or Cha nn e l 7. R/W
9:8 Reserved Reserved.
7:6 Channel 3 Select Same bit decode as for Channel 7. R/W
Device: 31 Function: 0
Offset: 8Ah Attribute: Read/W rite Clear
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: 90h-91h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 327
8—Intel® 6300ESB ICH
8.1.22 Offset D0h - D3h: GEN_CNTL—General Control
Register
(LPC I/F—D31:F0 )
5:4 Channel 2 Select Same bit decode as for Channel 7. R/W
3:2 Channel 1 Select Same bit decode as for Channel 7. R/W
1:0 Channel 0 Select Same bit decode as for Channel 7. R/W
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
D31:F0)
(Sheet 1 of 3)
Bits Name Description Access
31:2
5Reserved Reserved.
24 HIDE_ISA: Hide ISA
Bridge
0 = The Intel® 6300ESB ICH will not prev en t AD22 f rom
asse rti ng du ring con fi g cyc le s to the PCI -to-ISA bridge.
1 = Sof twa re sets this bit to 1 to disab le config cycle from
being c la ime d by a P CI-to-ISA bri dge . This will prevent
the OS PCI PnP from getting con fus ed by seein g two ISA
bridges.
It is required for the Intel® 6300ESB ICH PCI address line
AD22 to connect to the PCI -to-ISA bridge’ s IDSEL input.
When this b it is set, the Inte l® 6300ES B ICH will not
ass er t AD 22 during config cycle s to t he P CI- to- ISA
bridge.
R/W
23:2
2Reserved Reserved.
21 FERR#-MUX-EN: CPU
Break Event Indic at ion
Enable
0 = (De faul t) The Inte l® 6300ESB ICH will not examine the
FERR# signa l during C2, C3 or C4.
1 = Sof twa re se ts this bit to 1 to enab le the Intel® 6300ESB
ICH to examine the FERR# signal during a C2, C3 or C4
state as a break event. (See Section 5.11.6, “Dy namic
Proce ssor Clock Control” f or d e tails.)
R/W
20 Reserved Reserved.
Table 201. Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—
D31:F0) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: 90h-91h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: D0h - D3 h Attribute: Read/Write
Defau lt Value: 00000080h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
328 Order Number: 300641-004US
19:1
8SCRATCHPAD These bits are provided for possible future use.
17 MMT_ADDR_EN W he n se t to 1, this bit e nabl es the Intel® 6300ESB ICH to
decode the High Performance Event Timer Memory Addr ess
Range se le cted by bit s 16: 15 below.
16:1
5MMT_ADDR_SEL
This 2-bit field selects 1 of 4 possible memory address ranges
for the High Performa nce Even t Timer func tionality. The
encod i ngs are:
Bits [16:15] Memory Address Range
00 FED0_0000h - FED0_03FFh
01 FED0_1000h - FED0_13FFh
10 FED0_2000h - FED0_23FFh
11 FED0_3000h - FED0_33FFh
14 Reserved Reserved.
13 COPR_ERR_EN:
Coprocessor Error
Enable
0 = FERR# wil l not generate I RQ13 nor IGNNE#.
1 = When FERR# is low, the Intel® 6300ESB ICH g enerates
IRQ13 internally and holds it u ntil an I/O write to p ort
F0h. It will als o drive IG NNE# active.
R/W
12 IRQ1LEN: K eyboard
IRQ1 Latch Enable
0 = IRQ1 will b y pas s the la tch.
1 = The activ e edg e of IRQ1 will be latched and held unt il a
port 60h rea d . R/W
11 IRQ12LEN: Mouse
IRQ12 Latch Enable
0 = IRQ12 will byp ass the latch.
1 = The activ e edg e of IRQ12 will be latched and he ld un til a
port 60h rea d . R/W
10:9 Reserved Reserved.
8 A PIC_EN: APIC Enab le 0 = Disabl es inte rna l I/O (x ) A PIC.
1 = Enables the internal I/O (x) A PIC and its add ress decode. R/W
7 Reserved Reserved.
6ALTACC_EN: Alternate
Acce ss Mode Enab le
0 = Alt Access Mode Disabled (default). ALT access mode
allows reads to otherwise unreadable registers and writes
otherwise unwritable registers.
1 = Alt Acc e ss M od e E na b le .
R/W
5:3 Reserved Reserved.
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
D31:F0)
(Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 0
Offset: D0h - D3 h Attribute: Read/Write
Defau lt Value: 00000080h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 329
8—Intel® 6300ESB ICH
8.1.23 Offset D4h: GEN_STA—General Status (LPC I/F—
D31:F0)
2DCB_EN: DMA Collection
Buffer Enable
0 = D CB disa bl ed.
1 = Enables DMA Collection Buffer (DC B) for LPC I/F and PC/
PCI DMA. R/W
1DT E : Delayed
Tr ansaction Enab le
0 = Delayed transactions disabled.
1 = The Inte l® 6300ESB ICH enables delayed transactions f or
internal register, FWH and LPC I/F accesses. R/W
0 POS_DEC_EN
0 = The Intel® 6300ESB ICH will p e rf orm su b tractive d e code
on the PCI bus and forward the cycles to LPC if not to a n
internal regist e r or othe r k n own ta rg e t on LPC. Accesses
to internal registers and to known LPC devices will still be
pos it iv el y dec oded.
1 = Enable s Intel® 6300ES B ICH to only perf orm positi ve
de code on the PCI bus. This must be selected when t he
PCI to ISA (subtractive docking bridge) is used.
Table 203. Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)
Bits Name Description Access
7:3 Reserved Reserved.
2SAFE_MODE
0 = The Intel® 6300ESB ICH sam pl ed A C_SDOUT low on the
risin g edge of PWROK .
1 = The Intel® 6300ESB ICH sampled AC_SDOUT high on the
risin g edge of PWROK .
RO
1 NO_REBOOT
0 = Normal TCO Timer reboot functionality (reb oot after 2nd
TCO timeout). This bit cannot be set to 0 by softwa re
when the strap is set to N o Reboot.
1 = The Intel® 6300ESB ICH will disa ble the TCO Tim e r
syste m rebo ot feat ure. This bit is set ei th e r by hardware
when SPKR is sampled high on the rising edge of PWROK,
or by s oftware writing a 1 t o the bit.
R/W
(special)
0 Reserved Reserved.
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
D31:F0)
(Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 0
Offset: D0h - D3 h Attribute: Read/Write
Defau lt Value: 00000080h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: D4h Attribute: Read/Write
Defau lt Value: 0Xh Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
330 Order Number: 300641-004US
8.1. 24 Offse t D5h: BACK_CNTL—Backed Up Control
(LPC I/F—D31:F0)
Table 204. Offset D5h: BACK_CNTL—Backed Up Control (LPC I/F—D31:F0)
Bits Name Description Access
7 Reserved Reserved. RO
6 Reserved Reserved. RO
5TOP_SWAP: Top-Block
Swa p Mo de
0 = The Intel® 6300ESB ICH will not invert A16. This bit is
automatically set to 0 by R TCRST#, b ut not by any other
typ e o f rese t.
1 = The Intel® 6300ESB ICH will invert A 16 f or cycles g oing
to the BIOS spac e in the FWH (b ut not fo r cycles to the
F eatu re Space in the FWH).
NOTE: If the Intel® 6300ES B ICH is strapp e d for Top-Swap
(SIU0_DTR# is low at rising e dge of PWR OK ), the n
this bit CANNOT be cleared by software. The strap
jumper should be removed and the system rebooted.
R/W
4CPU_B I ST_E N : En ab le s
CP U B I ST
0 = Disabl e.
1 = The INIT# signal will be drive n active whe n CPURST# is
active. INIT# will go inactive with th e same timings a s
the oth e r CP U I/ F signal s (H old Time afte r CPURST#
inactive). N ote tha t CPURS T # is g e ne rated by the
memory controller hub, b ut the Intel® 6300 ESB ICH has
a Hub Interface sp e cial cycle that allows the Intel®
6300ESB ICH to control the assertion/d e ass ertion of
CPURST#.
NOTE: This bit is in the Resume we ll an d is re se t b y
RSMRST#, but not by PXPC IRS T# nor CF9h write s.
R/W
3:0 FREQ_STRAP[3:0]: CPU
Fr e que ncy Stra p
These bits de te rmine the intern a l freque ncy multiplier of the
process or. T hese b i t s m ay be re s et t o 1111 ba sed on an
extern al pin s trap or thro ugh the RTCRST# input signa l.
Software m ust program this field based on the processor’s
specif ie d freq ue n cy. No te tha t this f ie ld is only writable whe n
the SAFE_MODE b it is cleare d to zero, a nd SAFE_MODE is
only c l eared by PWROK risi ng edg e. Thes e bit s are i n t he RTC
well.
R/W
Device: 31 Function: 0
Offset: D5h Attribute: Read/Write
Defau lt Value: 0Fh (up on RTCRST# assertion
low)
2Fh (T OP_SWAP strap activ e) Size: 8-bit
Lockable: No Power Well: RTC
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 331
8—Intel® 6300ESB ICH
8.1.25 Offset D8h: RTC_CONF—RTC Configuration
Register
(LPC I/F—D31:F0 )
Table 205. Offset D8h: RTC_ CONF —RTC Configu ration Register (LPC I/F—
D31:F0)
Bits Name Description Access
7:5 Reserved Reserved.
4U128LOCK: Upper 128-
byte Lock
0 = Acc ess to these bytes in the upper CMOS RAM r ange have
not been locked.
1 = Locks reads and writes to bytes 38h-3Fh in the upper
128-byte bank of the R TC CMOS RAM. Write cycles to this
range will have no effect and read cycles will not return
any particular ensured v alue. This is a write once register
that may on ly be re se t b y a ha rd wa re re se t.
R/W
(special)
3L128L OCK: Lower 128-
byte Lock
0 = Acc ess to these bytes in the lower CMOS RAM range have
not been locked.
1 = Lo ck s rea d s and write s to b y te s 38h-3Fh in the lower
128-byte bank of the R TC CMOS RAM. Write cycles to this
range will have no effect and read cycles will not return
any particular ensured v alue. This is a write once register
that may on ly be re se t b y a ha rd wa re re se t.
R/W
(special)
2U128E: Upper 128-byte
Enable
0 = D isa b le .
1 = Enables access to the upper 128-b yte bank of R T C CMOS
RAM. R/W
1:0 Reserved Reserved.
Device: 31 Function: 0
Offset: D8h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: Yes Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
332 Order Number: 300641-004US
8.1.26 Offset E0h: COM_DEC—LPC I/F Communication
Port
Decode Ranges (LPC I/F—D31:F0)
Table 206. Offset E0h: COM_DEC—LPC I/F Communication Port Decode Ranges
(LPC I/F— D31:F0)
Bits Name Description Access
7 Reserved Reserved.
6:4 COMB Decode Range
This field determines which range to decode fo r the COMB
Port.
Bits Decode Ra n ge
000 3F8h - 3FFh (COM 1)
001 2F8h - 2FFh (COM 2)
010 220h - 227h
011 228h - 22Fh
100 238h - 2 3Fh
101 2E8 h - 2EFh (C O M 4)
110 338h - 3 3Fh
111 3E8 h - 3EFh (C O M 3)
R/W
3 Reserved Reserved.
2:0 CO M A Decode Range
This field determines which range to decode fo r the COMA
Port.
Bits Decode Ra n ge
000 3F8h - 3FFh (COM 1)
001 2F8h - 2FFh (COM 2)
010 220h - 227h
011 228h - 22Fh
100 238h - 2 3Fh
101 2E8 h - 2EFh (C O M 4)
110 338h - 3 3Fh
111 3E8 h - 3EFh (C O M 3)
R/W
Device: 31 Function: 0
Offset: E0h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 333
8—Intel® 6300ESB ICH
8.1.27 Off set E1h: FDD/LPT_DEC—LPC I/F FDD and LPT
Deco de Ranges (LPC I/F—D31:F0)
Table 207. Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC
I/F—D31:F0)
Bits Name Description Access
7:5 Reserved Reserved.
4 FDD Decode Ran ge Dete rmin e s wh ich ra nge to decode for the FDD Port
0 = 3F0h - 3F5h, 3F7h (Primary )
1 = 370h - 2FF h (Sec ond a ry ) R/W
3:2 Reserved Reserved.
1:0 LPT Decode Range
This field determines which range to decode for the LPTPort.
00 = 378h - 37Fh and 778h - 77Fh
01 = 278h - 27Fh (p ort 279h is read only) and 678h - 67Fh
10 = 3BCh -3BEh and 7BCh - 7BEh
11 = Reserved
R/W
Device: 31 Function: 0
Offset: E1h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
334 Order Number: 300641-004US
8.1. 28 Offse t E 2h: SND_DEC—LPC I/F Sound Decode
Ranges (LPC I/F—D31:F0)
Note: This register is no longer supported and will not be validated.
Table 208. Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—
D31:F0)
Bits Name Description Access
7:6 Reserved Reserved.
5:4 MSS Decod e Range
This field determines which range to decode fo r the
Microsoft* Sound System (MSS)
00 = 530h - 537h
01 = 604h - 60Bh
10 = E80h - E87h
11 = F40h - F47h
R/W
3MIDI Decode Range
This bit dete rmines which range to decode for the Mid i Port.
0 = 330h - 331h
1 = 300h - 301h R/W
2 Reserved Reserved.
1:0 SB 16 Decode Range
This field determines which range to decode for t he Sound
Blaster 16 (SB 16) Port.
00 = 220h - 233h
01 = 240h - 253h
10 = 260h - 273h
11 = 280h - 293h
R/W
Device: 31 Function: 0
Offset: E2h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 335
8—Intel® 6300ESB ICH
8.1.29 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1
Register (LPC I/F—D31:F0)
Note: This register determines which memory ranges will be decoded on the PCI bus and
forw arded to the FWH. The Inte l® 6300ESB ICH will subtractively decode cy cles on PCI
unless POS_DEC_EN is set to 1.
Table 209. Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—
D31:F0) (Sheet 1 of 2)
Bits Name Description Access
7 FWH_F8_EN
Enab le s d e coding two 512 Kbyte F W H me mory ranges, a nd
one 128 Kbyte memory range .
0 = D isa b le
1 = Enable the following ranges for the FWH
FFF80000h - FFFFFFFFh
FFB800 00h - FFB FFFFFh
000E0000h - 000FFFFFh
RO
6 FWH_F0_EN
Enab le s d e coding two 512 Kbyte F W H me mory ranges.
0 = D isa b le .
1 = Enable the following ranges for the FWH:
FFF00000h - FFF7FFFFh
FFB000 00h - FFB 7FFFFh
R/W
5 FWH_E8_EN
Enab le s d e coding two 512 Kbyte F W H me mory ranges.
0 = D isa b le .
1 = Enable the following ranges for the FWH:
FFE80000h - FFEFFFFh
FFA80000h - FFAFFFFFh
R/W
4 FWH_E0_EN
Enab le s d e coding two 512 Kbyte F W H me mory ranges.
0 = D isa b le .
1 = Enable the following ranges for the FWH:
FFE00000h - FFE7FFFFh
FFA00000h - FFA7FFFFh
R/W
3 FWH_D8_EN
Enab le s d e coding two 512 Kbyte F W H me mory ranges.
0 = D isa b le .
1 = Enable the following ranges for the FWH
FFD80000h - FFDFFFFFh
FF980000h - FF9FFFFFh
R/W
Device: 31 Function: 0
Offset: E3h Attribute: Read/Write
Defau lt Value: FFh Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
336 Order Number: 300641-004US
8.1. 30 Offse t E4h - E 5h: GEN1_DEC —LPC I/F Generic
Decode R ange 1 (LPC I/F—D31:F0)
2 FWH_D0_EN
Enables decod ing two 512 Kb yt e FWH memory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FFD00000h - FFD7FFFFh
FF900000h - FF97FFFFh
R/W
1 FWH_C8_EN
Enables decod ing two 512 Kb yt e FWH memory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FFC80000h - FFCFFFFFh
FF880000h - FF8FFFFFh
R/W
0 FWH_C0_EN
Enables decod ing two 512 Kb yt e FWH memory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FFC00000h - FFC7FFFFh
FF800000h - FF87FFFFh
R/W
Tab l e 210. Off set E 4h - E5 h: GE N1_D EC —LPC I/ F Ge ner ic Dec ode Ra nge 1 (L PC I/
F—D31:F0)
Bits Name Description Access
15:7 GEN1_BASE: Generic I/
O De cod e Ra nge 1 Base
Address
This address is aligned on a 128-byte boundary, and must
have address lines 31:16 as 0.
Note that this ge ne ric d ecod e is for I/O a d dres ses only, not
memo ry addre ss es . The siz e of this range is 128 bytes.
R/W
6:1 Reserved Reserved.
0GEN1_EN: Generic
De code R a nge 1 Ena bl e
0 = Disabl e.
1 = Enabl e the GEN1 I/O ran ge to be forwar ded to the LPC I/
F. R/W
Table 209. Offset E3h: FWH _DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—
D31:F0) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: E3h Attribute: Read/Write
Defau lt Value: FFh Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: E4h - E5h Attribute: Read/Write
Defau lt Value: 00h Size: 16-bit
Lockable: Yes Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 337
8—Intel® 6300ESB ICH
8.1.31 Offset E6h - E7h: LPC_EN—LPC I/F Enables
(LPC I/F—D31:F0 )
Table 2 11. Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—D31:F0) (Sheet
1 of 2)
Bits Name Description Access
15:1
4Reserved Reserved.
13 CNF2_LPC_EN 0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to
the LPC interf ace. This is used for the internal SIU. R/W
12 CNF1_LPC_EN
0 = D isa b le .
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to
the LPC interf ace. Thi s range is used for Super I/O
devices.
R/W
11 MC_LPC_EN 0 = Disab le .
1 = Enables t h e dec odi ng o f t he I /O l ocat io n s 62h and 6 6 h t o
the LPC interface. This range is used f or a microcontroller. R/W
10 KBC_LPC_EN 0 = D isable.
1 = Enables t h e dec odi ng o f t he I /O l ocat io n s 60h and 6 4 h t o
the LPC interface. This range is used f or a microcontroller. R/W
9 GAMEH_LPC_EN 0 = Disa b le .
1 = Enables the decoding of the I/O locations 208h to 20Fh to
the LPC interf ace. This range is used for a gameport. R/W
8 GAMEL_LPC_EN 0 = Disa b le .
1 = Enables the decoding of the I/O locations 200h to 207h to
the LPC interf ace. This range is used for a gameport. R/W
7 ADLIB_LPC_EN
0 = D isa b le .
1 = Enables the decoding of the I/O locations 388h - 38Bh to
the LPC inte rfac e .
NOTE: This bit is no long e r su p p orte d and will not be
validated.
R/W
6 MSS_LPC_EN
0 = D isa b le .
1 = Enables the decoding of the MSS range to the LPC
interfa ce . This range is sel ec te d in the L PC_Sound
Decode Range Re gister.
NOTE: This bit is no long e r su p p orte d and will not be
validated.
R/W
5 MIDI_LPC_EN
0 = D isa b le .
1 = Enables the decoding of the MIDI range to the LPC
interfa ce . This range is sel ec te d in the L PC_Sound
Decode Range Re gister.
NOTE: This bit is no long e r su p p orte d and will not be
validated.
R/W
Device: 31 Function: 0
Offset: E6h - E7h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: Yes Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
338 Order Number: 300641-004US
4 SB16_LPC_EN
0 = Disabl e.
1 = Enabl es the deco din g of the SB16 rang e to the LPC
interf ace . This range is sele cted in the LPC_Soun d
Decod e Range Register.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/W
3 FDD_LPC_EN
0 = Disabl e.
1 = Enables the deco din g of the FDD range to the LPC
interf ace . This rang e is se le cted in the LPC_FDD/LP T
Decod e Range Register.
R/W
2 LPT_LPC_EN
0 = Disabl e.
1 = Enabl es the deco din g of the LPTrang e to the LPC
interf ace . This rang e is se le cted in the LPC_FDD/LP T
Decod e Range Register.
R/W
1COMB_LPC_EN
0 = Disabl e.
1 = Enables the deco din g of the COMB range to the LPC
interf ace . This range is sele cted in the LPC_COM De code
R an ge Reg ist er.
R/W
0COMA_LPC_EN
0 = Disabl e.
1 = Enables the deco din g of the COMA range to the LPC
interf ace . This range is sele cted in the LPC_COM De code
R an ge Reg ist er.
R/W
Table 211. Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—D31:F0) (Sheet
2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: E6h - E7h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: Yes Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 339
8—Intel® 6300ESB ICH
8.1.32 Offset E8h: FWH_SEL1—FWH Select 1 Register
(LPC I/F—D31:F0 )
Table 212. Offset E8h: FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)
Bits Name Description Access
31:2
8FWH_F8_IDSEL
IDSEL for two 512 Kbyte FWH memory ranges and one 128
Kbyte memory ran ge. T his fie ld is fixed at 0000. The IDSEL
programmed in this field addresses the fo llowing memory
ranges:
FFF8 0000h - FFFF FFFFh
FFB8 00 00h - FFB F FFFFh
000E 0000h - 000F FFFFh
RO
27:2
4FWH_F0_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFF0 0000h - FFF7 FFFFh
FFB0 00 00h - FFB 7 FFFFh
R/W
23:2
0FWH_E8_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFE8 0000h - FFEF FFFFh
FFA8 0000h - FFAF FFFFh
R/W
19:1
6FWH_E0_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFE0 0000h - FFE7 FFFFh
FFA0 0000h - FFA7 FFFFh
R/W
15:1
2FWH_D8_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFD8 0000h - FFDF FFFFh
FF98 0000h - FF9F FFFFh
R/W
11:8 FWH_D0_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFD0 0000h - FFD7 FFFFh
FF90 0000h - FF97 FFFFh
R/W
7:4 FWH_C8_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFC8 0000h - FFCF FFFFh
FF88 0000h - FF8F FFFFh
R/W
3:0 FWH_C0_IDSEL
IDS EL f or two 512 Kby te FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FFC0 0000h - FFC7 FFFFh
FF80 0000h - FF87 FFFFh
R/W
Device: 31 Function: 0
Offset: E8h Attribute: Read/Write
Defau lt Value: 00112233h Size: 32-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
340 Order Number: 300641-004US
8.1. 33 Offset ECh - EDh: GEN2_DE C—LP C I/F Generic
Decode
Range 2 (LPC I/F—D31:F0)
Tab l e 213. Off set ECh - EDh: GEN2_ DEC —LPC I/ F Gen eri c Dec ode Ran ge 2 (LP C I/
F—D31:F0)
Bits Name Description Access
15:4 GEN2_BASE
Generic I/O Decode Range 2 Base Addr es s. This address is
aligned on a 64-byte boundary, and must have address lines
31:16 as 0.
Note that this ge ne ric d ecod e is for I/O a d dres ses only, not
memory addresses. The size of this range is 16 by tes.
R/W
3:1 Reserved Reserved. Read as 0.
0 GEN2_EN
Generic I/O Decode Range 2 Enable
0 = Disabl e.
1 = Accesses to the GEN2 I/O range will be forwa rd e d to the
LPC I / F.
R/W
Device: 31 Function: 0
Offset: ECh - EDh Attribute: Read/Write
Defau lt Value: 00h Size: 16-bit
Lockable: Yes Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 341
8—Intel® 6300ESB ICH
8.1.34 Offset EEh - EFh: FWH_SEL2—FW H Select 2
Register
(LPC I/F—D31:F0 )
Table 214. Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register (LPC I/F—
D31:F0)
Bits Name Description Access
15:1
2FWH_70_IDSEL
IDS EL f or two 1M FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FF70 0000h - FF7F FFFFh
FF30 0000h - FF3F FFFFh
R/W
11:8 FWH_60_IDSEL
IDS EL f or two 1M FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FF60 0000h - FF6F FFFFh
FF20 0000h - FF2F FFFFh
R/W
7:4 FWH_50_IDSEL
IDS EL f or two 1M FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FF50 0000h - FF5F FFFFh
FF10 0000h - FF1F FFFFh
R/W
3:0 FWH_40_IDSEL
IDS EL f or two 1M FW H me mory ranges.
The IDSEL programmed in this field addresses the following
mem o ry range s:
FF40 0000h - FF4F FFFFh
FF00 0000h - FF0F FFFFh
R/W
Device: 31 Function: 0
Offset: EEh-EFh Attribute: Read/Write
Defau lt Value: 4567h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
342 Order Number: 300641-004US
8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2
Register (LPC I/F—D31:F0)
Note: This register determines which memory ranges will be decoded on the PCI bus and
forwarded t o the FWH. The Intel® 6300ESB ICH will subtractively decode cycles on PCI
unless POS_DEC_EN is set to 1.
Table 215. Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—
D31:F0)
Bits Name Description Access
7:4 Reserved Reserved.
3 FWH_70_EN
Enab le s dec o d ing tw o 1M FW H me mory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FF70 0000h - FF7F FFFFh
FF30 0000h - FF3F FFFFh
R/W
2 FWH_60_EN
Enab le s dec o d ing tw o 1M FW H me mory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FF60 0000h - FF6F FFFFh
FF20 0000h - FF2F FFFFh
R/W
1 FWH_50_EN
Enab le s dec o d ing tw o 1M FW H me mory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FF50 0000h - FF5F FFFFh
FF10 0000h - FF1F FFFFh
R/W
0 FWH_40_EN
Enab le s dec o d ing tw o 1M FW H me mory ranges.
0 = Disabl e.
1 = Enabl e the following ranges for the FWH
FF40 0000h - FF4F FFFFh
FF00 0000h - FF0F FFFFh
R/W
Device: 31 Function: 0
Offset: F0h Attribute: Read/Write
Defau lt Value: 0Fh Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 343
8—Intel® 6300ESB ICH
8 .1.36 Offset F2h: FUNC_DIS—Function Disable R egister
(LPC I/F—D31:F0 )
Note: The USB functions must be disabled from highest function number to lowest. For
ex ampl e , if o nl y 2 USB host con t rol l ers a re wa nt ed, sof tw a re mu st dis ab le F un ct ion #2 .
USB functions are expected to only be disabled by BIOS during system initialization.
Table 216. Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)
(Sheet 1 of 2)
Bits Name Description Access
15 D29_F7_Disable
Softwa re se ts this bit to dis able the US B EH CI Controller
function. BIOS must not enable I/O or me mory address space
decode , inte rrup t g e ne ration, or an y oth er functiona lity of
functions that are to b e disabled.
0 = US B EHC I Controller is e na b le d
1 = US B EHC I Con troller is di sabled
R/W
14:1
0Reserved Reserved.
9 D29_F1_Disable
Softwa re sets this bit to disable the US B UH CI Controller #2
function. BIOS must not enable I/O or me mory address space
decode , inte rrup t g e ne ration, or an y oth er functiona lity of
functions that are to b e disabled.
0 = US B UHCI Controller #2 is enab le d
1 = US B UHCI Controller #2 is dis a bl ed
R/W
8 D29_F0_Disable
Softwa re sets this bit to disable the US B UH CI Controller #1
function.BIOS must not enable I/O or memory address space
decode , inte rrup t g e ne ration, or an y oth er functiona lity of
functions that are to b e disabled.
0 = US B UHCI Controller #1 is enab le d
1 = US B UHCI Controller #1 is dis a bl ed
R/W
7 Reserved Reserved
6 D31_F6_Disable
Softwa re se ts this bit to disable the A C’97 modem contro lle r
functi on. Wh e n disabl ed, the PCI config space registers for
that funct ion are not dec od ed by the Intel® 6300ES B ICH .
BIOS must not enable I/ O or memory addr es s space dec ode,
interr up t genera tion, or an y othe r fun ctionality of functio ns
that are to be disabled.
0 = AC’97 M od e m is enable d
1 = AC’97 M od e m is dis abled
R/W
5 D31_F5_Disable
Software se ts this bit to dis able the A C’97 a ud io controller
function. BIOS must not enable I/O or me mory address space
decode , inte rrup t g e ne ration, or an y oth er functiona lity of
functions that are to b e disabled.
0 = A C’97 a ud io controller is enab le d
1 = AC’97 aud io controller is disabl ed
R/W
4 Reserved Reserved.
Device: 31 Function: 0
Offset: F2h Attribute: Read/Write
Defau lt Value: 0080h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
344 Order Number: 300641-004US
3 D31_F3_Disable
Softwa re sets this bit to d isab le the SMBu s Ho st Controller
function. BIOS must not enable I/O or memory ad dress space
decode , inte rrup t gene ration, or any other functi onality of
function s that a re to be disab le d.
0 = SMBus contro lle r is e na b le d
1 = SMBus controller is disabled
R/W
2 D31_F2_Disable
Software sets this bit to disable the SATA Controlle r fu nction.
BIOS mu st n ot enable I/O or me mory add re ss sp a ce decode ,
interrupt g e neration, or a ny oth er functiona lity of func tions
that are to be disabled.
0 = SATA controller is enab le d
1 = SATA controller is d isa b le d
R/W
1 D31_F1_Disable
Software sets this bit to d isab le the IDE co ntroller function.
BIOS mu st n ot enable I/O or me mory add re ss sp a ce decode ,
interrupt g e neration, or a ny oth er functiona lity of func tions
that are to be disabled.
0 = IDE controller is enab le d
1 = IDE controller is dis a bled
R/W
0SMB_FOR_BIOS
This bit is use d in conjunction wi th bit 3 in this re gis te r.
0 = No effect.
1 = Allows the SMBus I/O space to be accessible by software
when bit 3 in this register is set. The PCI con f ig ura tion
space is hidd en in this case. Note that whe n b it 3 is set
alone, the decode of both SMBus PCI configuration and I/
O space will b e disa bled .
R/W
NOTE: Software must always disa bl e all fu nctionality within the f u nction before d isa b lin g the con f ig u ration
space.
Table 216. Offset F2h: FUNC_DIS—F unction Disable Register (LPC I/F—D3 1:F0)
(Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: F2h Attribute: Read/Write
Defau lt Value: 0080h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 345
8—Intel® 6300ESB ICH
8.1.37 Offset F4: ETR1 —PCI-X Extended Features
Register
(LPC I/F—D31:F0 )
Warning:Make sure that reserved bits values are not modified to avoid indeterminate
behavior.
8.1.38 Offset F8h: Manufacturer’s ID
Table 217. Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0)
Bits Name Description Access
31:8 Reserved Reserved.
7 Trapping Disable
Def a u lt = 0.
0 = Trapping is enabled for all access to these ports. See
Section 5.1 7.9, “USB Legacy Keyboa rd Operation” for
deta ils on US B Legacy Keyboar d Opera tion.
1 = Disab le the US B Legac y Trapp ing to Ports 60h and 64h
when an exter nal PCI Master is accessing these ports.
R/W
6PXIRQ Routing
Def a u lt = 0.
0 = APIC1 b oot inte rrupt is routed to IRQ9#. See
Section 5.7.3, “B oot Interrupt” for details on Boot
Interrupt.
1 = Routes the APIC 1 boo t inte rrup t to the PIRQG # output.
R/W
5:0 Reserved Reserved.
Table 218. Offset F8h: Manufacturer’s ID
Bits Name Description Access
31:1
6Reserved Reserved.
15:8 Manufacturer 0Fh = Inte l
7:0 Process/Dot Process 859.6
Device: 31 Function: 0
Offset: F4-f7h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: F8h-FBh Attribute: Read-Only
Defau lt Value: 000S 0F66 Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
346 Order Number: 300641-004US
8.2 DMA I/ O Re gisters
Table 219. DMABASE_CA—DMA Base and Current Address Registers (Sheet 1 of
2)
Port Alias Register Name/Function Default Type
00h 10h Channel 0 DMA Base and Current Ad dr ess
Register Undefined R/W
01h 11h Channel 0 DMA Base and Current Count
Register Undefined R/W
02h 12h Channel 1 DMA Base and Current Ad dr ess
Register Undefined R/W
03h 13h Channel 1 DMA Base and Current Count
Register Undefined R/W
04h 14h Channel 2 DMA Base and Current Ad dr ess
Register Undefined R/W
05h 15h Channel 2 DMA Base and Current Count
Register Undefined R/W
06h 16h Channel 3 DMA Base and Current Ad dr ess
Register Undefined R/W
07h 17h Channel 3 DMA Base and Current Count
Register Undefined R/W
08h 18h Channel 0-3 DMA Command Register Undefined WO
Channel 0-3 DMA Status Register Undef ined RO
0Ah 1A h Channe l 0-3 D M A Write Single Mask Register 000001XX b WO
0Bh 1Bh Channel 0-3 DMA Channe l Mod e Register 000000XXb W O
0Ch 1Ch Channel 0-3 D M A Clea r Byte Pointe r Register Undef ine d WO
0Dh 1Dh Channel 0-3 DMA Maste r Clea r Regist er Und e f ine d WO
0Eh 1Eh Channel 0-3 DM A Clear Ma sk Register Und ef ine d WO
0Fh 1Fh Channel 0-3 DMA Write All Mask Registe r 0Fh R/W
80h 90h Reserved Page Register Undefined R/W
81h 91h Channel 2 DM A Memory Low Page Register Unde f ine d R/W
82h - Channel 3 DMA Memory Low Page Register Undefined R/W
83h 93h Channel 1 DM A Memory Low Page Register Unde f ine d R/W
84h - 86h 94h - 96h Reserve d Page Registers Unde f ine d R/W
87h 97h Channel 0 DM A Memory Low Page Register Unde f ine d R/W
88h 98h Reserved Page Register Undefined R/W
89h 99h Channel 6 DM A Memory Low Page Register Unde f ine d R/W
8Ah 9Ah Channel 7 DMA Memory Low Page Register Undefined R/W
8Bh 9Bh Channel 5 DMA Memory L ow Page Register Undefined R/W
8Ch - 8Eh 9Ch - 9Eh Reserved Page Registers Undefined R/W
8Fh 9Fh Refresh Lo w Page Register Undefined R/W
C0h C1h Channel 4 DMA Base and Current A d dress
Register Undefined R/W
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 347
8—Intel® 6300ESB ICH
C2h C3h Channel 4 DMA Base and Curr en t Count
Register Undefined R/W
C4h C5h Channel 5 DMA Base and Current Address
Register Undefined R/W
C6h C7h Channel 5 DMA Base and Curr en t Count
Register Undefined R/W
C8h C9h Channel 6 DMA Base and Current Address
Register Undefined R/W
CAh CBh Channel 6 DMA Base and Curr en t Count
Register Undefined R/W
CCh CDh Channel 7 DMA Base and Current Address
Register Undefined R/W
CEh CFh Channel 7 DMA Base and Curr en t Count
Register Undefined R/W
D0h D1h Channel 4- 7 DMA Command Register Undefined WO
Channel 4- 7 DMA Status Register Un defined R O
D4h D 5h Channel 4-7 DMA Write Single Mask Register 000001X Xb WO
D6h D7h Channel 4-7 DMA Channel M od e Register 00000 0X Xb WO
D8h D9h Channel 4-7 DMA Clear Byte Pointer Re g ister Undefined WO
DAh D Bh Channel 4-7 DMA Master Clear Register Undefined WO
DCh DDh Channel 4-7 DMA Clear Mask Register Undefined WO
DEh DFh Channe l 4-7 DMA Write A ll Ma sk Registe r 0Fh R/W
Table 219. DMABASE_CA—DMA Base and Current Address Registers (Sheet 2 of
2)
Port Alias Register Name/Function Default Type
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
348 Order Number: 300641-004US
8.2.1 DMABASE_CA—DMA Base and Current Address
Registers
Table 220. DMABASE_CA—DMA Base and Current Address Registers
Bits Name Description Access
15:0 Base a nd C urre n t
Address
This register determines the address for the transfers to be
perfo rmed . T h e addres s s pec i fied po in ts to t wo s epar ate
regis t er s. On writes , the val ue is stored in the Base Address
register and copied to the Current A ddress register. On reads,
the value is returned from the Current Address re gister.
The addr ess increments/decrements in the Current Address
register after each transfer, depending on the mode o f the
tran sf e r. Whe n the channe l is in au to-initialize mod e, the
Current Addre ss re g ister will b e reloaded fr om th e B a se
Address registe r af te r a term ina l count is genera te d .
For transfers to/f rom a 16-b it slave (channe l’s 5-7), the
addres s is shi fted le ft one bit location. Bit 15 wil l be shifte d
into Bit 16.
The register is accessed in 8 bit quan tities. The byte is
poin te d to by the curren t byte poin te r flip/ fl o p. Befo r e
accessing an address register, the byte pointer flip/flop should
be clear ed to ensure that the lo w byte is accessed first
R/W
Device: 31 Function: 0
I/O Address:
Ch . #0 = 00h; Ch. #1 =
02h, Ch. #2 = 04h; Ch.
#3 = 06h, Ch. #5 = C4h
Ch . #6 = C8h, Ch. #7 =
CCh
Attribute: Read-Only
Defau lt Value: Undefined Size: 16-bit, access e d in tw o 8-b it quantities
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 349
8—Intel® 6300ESB ICH
8. 2.2 DM A BASE_CC—DMA Base and Current Count
Registers
Table 221. D MABAS E_CC— DMA Base and Current Count Registers
Bits Name Description Access
15:0 Base and Current Count
This register determines the number of transfers to be
performed. The address specified points to two separate
registers. On writes, the value is stored in the Base Count
register and copied to the Current Count register. On reads,
the value is returned from the Cur ren t Count register.
The actual number of trans fers is one more than the number
progr a mm ed i n th e Base Co un t Registe r (i.e ., programming a
count of 4h results in 5 transfers). The count is decrements in
the Curr en t Count re g ister a f ter e a ch transf e r. Whe n the
value in the register rolls from zero to FFFFh, a terminal count
is gener ated. When the channel is in auto-initialize mode, the
Cur re nt Cou nt re g ister will b e reloaded from the Base Count
registe r after a terminal count is gen e rated.
For tr ansfers to/from an 8-bit slave (channels 0-3), the count
register indicate s the numb e r of byte s to b e trans ferr e d. For
transfers to /fr om a 16-b it slav e (cha nne ls 5-7 ), the count
register indicates the number of words to be t ransferred.
The register is accessed i n 8 bit quan ti t ies. The byte is
pointed to by the current byte po inte r fl ip/ flo p. Befo re
accessi ng a count register, the byte pointer flip/flop should be
clear ed to en sure that the low byte is acc es sed fir st.
R/W
Device: 31 Function: 0
I/O Address:
Ch . #0 = 01h; Ch. #1 =
03h, Ch. #2 = 05h; Ch.
#3 = 07h, Ch. #5 = C6h
Ch . #6 = CA h, Ch. #7 =
CEh
Attribute: Read/Write
Defau lt Value: Undefined Size: 16-bit, accessed in two 8-b it quantities
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
350 Order Number: 300641-004US
8.2.3 DMAMEM_LP—DMA Memory Low Page Registers
8.2.4 DMACMD—DMA Command Register
Table 222. DMABASE_CC—DMA Base and Current Count Registers
Bits Name Description Access
7:0 DMA Low Page (ISA
Address bits [23:16]
This re gis te r work s in conjunction wi th the DMA controller's
Current Address Register to define the complete 24-bit
address for th e DMA ch a nn e l. This reg ister rem a in s static
throughout the DMA transfer. Bit 16 of this register is ignored
when in 16 bit I/O count by words mode as it is replaced by
the bit 15 shif te d out from the curre nt ad dress regist er.
R/W
Table 223. DMACMD—DMA Command Register
Bits Name Description Access
7:5 Reserved Reserved. Must be 0.
4DMA Group Arbitration
Priority
Each cha nnel gro u p is in divid u a lly a ssigned eith e r f ixed or
rotati ng arbitration priority. At part rese t, e ach g roup is
initiali ze d in fixed pr iority.
0 = Fixed pri ority to the cha nnel group
1 = Rotating priority to the group.
WO
3 Reserved Reserved. Must be zero.
2DMA Channel Group
Enable
Both cha nn e l g roups are ena b le d follo win g part r e se t.
0 = E nable the DMA ch ann el grou p.
1 = Disab le . Disabling channel group 4 -7 also disa bles
channel group 0-3, whi ch is cascaded thr ough channel 4.
WO
1:0 Reserved Reserved. Must be zero.
Device: 31 Function: 0
I/O Address:
Ch . #0 = 87h; Ch. #1 =
83h, Ch. #2 = 81h; Ch.
#3 = 82h, Ch. #5 = 8Bh
Ch . #6 = 89h, Ch. #7 =
8Ah
Attribute: Read/Write
Defau lt Value: Undefined Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 08h
Ch. #4-7 = D0h Attribute: Write-Only
Defau lt Value: Undefined Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 351
8—Intel® 6300ESB ICH
8.2.5 DMASTA—DMA Status Register
Table 224. DMASTA—DMA Status Register
Bits Name Description Access
7:4 Channel Request Status
When a valid DMA re quest is pen ding f or a cha nn e l, the
corre sponding bit is set to 1. Whe n a DMA request is not
pen ding for a pa rticular cha n nel, the correspon d in g bit i s se t
to 0. The source of the DREQ may be hardware or a software
reque st. Note that channel 4 is the cascade channel, so the
requ e st status of cha nn e l 4 is a logical OR of the re q u e st
status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
RO
3:0 Channel Terminal Count
Status
When a channel reaches terminal count (TC), its status bit is
set to 1. When TC has not be e n rea ched , the status bit is set
to 0. Ch anne l 4 is programme d for cascad e , so the TC bit
response for cha n ne l 4 is irre le vant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
RO
Device: 31 Function: 0
I/O Address: C h. #0-3 = 08h
Ch. #4-7 = D0h Attribute: Read-Only
Defau lt Value: Undefined Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
352 Order Number: 300641-004US
8.2.6 DMA_WRS MSK—DMA Writ e S ing le Mask Register
8.2.7 DMACH_MODE—DMA Ch ann el Mode Register
Table 225. DMA_WRSMSK—DMA Write Single Mask Register
Bits Name Description Access
7:3 Reserved Reserved. Must be zero.
2 Channel Mask Select
0 = Enable DREQ for the selected channel. The channel is
selected through bits [1:0]. Therefore, only one channel
may be masked / unma sked a t a tim e .
1 = Dis a ble DREQ fo r the selecte d ch a nn e l.
WO
1:0 DMA Channel Select
These bi ts s elect t he DMA C han nel Mode R egis t er to pro gra m.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
WO
Table 226. DMACH_MODE—DMA Channel Mode Register ( Sheet 1 of 2)
Bits Name Description Access
7:6 DMA Transfer Mode
Each DMA channel may be programmed in one of four
different modes:
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mod e
WO
5Addr es s Increm ent /
Decrement Select
This bit con trols address incr em e n t/d e crement during DMA
transfers.
0 = Address increment. (default after part reset or Master
Clear)
1 = Address decrement.
WO
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Ah
Ch. #4-7 = D4h Attribute: Write-Only
Defau lt Value: 0000 01xx Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Bh
Ch. #4-7 = D6h Attribute: Write-Only
Defau lt Value: 0000 00xx Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 353
8—Intel® 6300ESB ICH
8.2.8 DMA Clear Byte Pointer Register
4 Autoinitialize Enable
0 = Autoinitialize feature is disabled and DMA transfers
terminate on a terminal count. A part reset or Master
Clear d isables auto in itia lization .
1 = DMA restores the Base Address and Count registers to
the curr en t regis te rs following a termina l count ( TC).
WO
3:2 DM A Trans fer Type
These bits represent the direction of the DMA transfer. When
the channel is programmed for cascade mode, (bits[7:6] =
“1 1”) the tran sf er type is irrele vant.
00 = Verify - No I/O or memory strobes generated
01 = Write - Data transfer re d from the I/O devices to
memory
10 = Read - Dat a transferred from memory to the I/O device
11 = Illegal
WO
1 :0 DMA Ch a nn e l S e le ct
These bits select the DMA Channel Mode Register that will be
writte n by bi ts [7:2].
00 = Chan nel 0 (4)
01 = Chan nel 1 (5)
10 = Chan nel 2 (6)
11 = Chan nel 3 (7)
WO
Table 227. DMA Clear Byte Pointer Register
Bits Name Description Access
7:0 Clear Byt e Poi n ter
No specific p attern. Command enabl ed with a write to the I/O
port ad d re ss. Writin g to th is re g iste r in itializes the byte
pointe r f lip /f lop to a known state. It clea rs t he int ern al la tch
used to addr ess the upper or lowe r byte of the 16-bit Addre ss
and Word Count Registers. The latch is also cleared by part
reset and by the Master Clear command. This command
precedes the first access to a 16-bit DMA controller register.
Th e firs t access to a 16 -b it re gister will then access the
significant byte, and the se cond a ccess automatically
acc e sse s the most sig n if icant byte.
WO
Table 226. DMACH_MODE—DMA Channel Mode Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Bh
Ch. #4-7 = D6h Attribute: Write-Only
Defau lt Value: 00 00 00x x Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Ch
Ch. #4-7 = D8h Attribute: Write-Only
Defau lt Value: xxxx xxxx Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
354 Order Number: 300641-004US
8.2.9 DMA Master Clear Register
8.2.10 DMA_CLMSK—DMA Clear Mask Regi ster
Table 228. DMA Master Clear Register
Bits Name Description Access
7:0 Master Clear
No specific pattern. Enabled with a write to the port. This has
the same effect as the hardware Res et. The Command,
Status, Request, and Byt e Pointer flip/flop registers are
cleare d and the Ma sk Reg ister is se t.
WO
Table 229. DMA_CLMSK—DMA Clear Mask Register
Bits Name Description Access
7:0 Clear M a sk Reg i ster N o sp e cific p a ttern. Command e na b le d wi th a write to the
port. WO
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Dh
Ch. #4-7 = DAh Attribute: Write-Only
Defau lt Value: xxxx xxxx Size: 8-bit
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Eh;
Ch. #4-7 = DCh Attribute: Write-Only
Defau lt Value: xxxx xxxx Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 355
8—Intel® 6300ESB ICH
8.2.11 DMA_WRMSK—DMA Write All Mask Register
I
8.3 Timer I/O Registers
Tabl e 23 0. D M A_W RM S K—D MA Write All Ma sk Regis te r
Bits Name Description Access
7:4 Reserved Reserved. Must be 0.
3:0 Channel Mask Bits
This re gister pe rmits all fou r ch an ne ls to be sim u ltan e ou sly
enabled/di sa b l e d ins t e ad of e na b lin g / d isa b lin g e a ch ch a nn e l
indiv id u ally, as is the case with the Mas k Regis te r - Write
Single Ma sk Bit . In addition, this register has a re a d path to
allo w the status of the channe l mask bits to be read . A
channel's mask bit is automatically set to 1 when the Current
Byte/Word Count Register reache s terminal count (unless the
cha n ne l is in a uto-in itializa tion mod e ).
Setti n g the bit(s ) to a 1 disabl es the cor re spon di ng DR EQ ( s).
Setting the bit( s) to a 0 enables th e corre sp ond ing DREQ(s).
Bits [3:0] are set to 1 upo n part rese t or M aste r Clea r. Whe n
read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask
status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = No t Ma sked
Bit 1 = Channel 1 (5)1 = Masked, 0 = No t Ma sked
Bit 2 = Channel 2 (6)1 = Masked, 0 = No t Ma sked
Bit 3 = Channel 3 (7)1 = Masked, 0 = No t Ma sked
NOTE: D isa b lin g ch an ne l 4 a lso disab le s cha nn e ls 0 -3 due to
the ca scade o f channel ’s 0 - 3 thr ou g h ch a nn e l 4 .
R/W
Table 231. Timer I/O Registers
Port Al iases Regi ster Name / Functi on Default
Value Type
40h 50h Counter 0 Interval Time S ta tus By te
Format 0XXXXXXXb RO
C oun ter 0 Count er Access Port Register U nde f in e d R/W
41h 51h C ounte r 1 Inte rval Time S tatus B y te
Format 0XXXXXXXb RO
C oun ter 1 Count er Access Port Register U nde f in e d R/W
42h 52h C ounte r 2 Inte rval Time S tatus B y te
Format 0XXXXXXXb RO
C oun ter 2 Count er Access Port Register U nde f in e d R/W
43h 53h
Time r Control Word Register Undefine d WO
Timer Control Word Register Read Back XXXXXXX0 b WO
Counter Latch Command X0h WO
Device: 31 Function: 0
I/O Address: Ch. #0-3 = 0Fh;
Ch. #4-7 = DEh Attribute: Read/Write
Defau lt Value: 00 00 1111 Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
356 Order Number: 300641-004US
8.3.1 TCW —Timer Control Wo rd Regist er
Note: This register is programmed prior to any counter being accessed to specify counter
modes. Fol lowing part reset, the co ntro l words for each reg ister are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
Note: There are two special commands that may be issued to the counters through this
register, the Read Back Command and the Counter Latch Command. When these
commands are chosen, several bits within this register are redefined. These register
formats are described below.
Table 232. TCW —Timer Control Word Register
Bits Name Description Access
7:6 Counter Select
The Counter Selection bits select the counter the control word
acts upon as shown below. The Read Back Command is
selected when bits[7:6] are both 1.
00 = Counter 0 select
01 = Counter 1 select
10 = Counter 2 select
11 = Read Back Comm and
WO
5:4 Read/Write Select
These bits are the re ad /write control bits. The a ctual counter
program ming is d on e through the counter port (40h f or
counter 0, 41h for counter 1, and 42h for counte r 2).
00 = Counter Latch Command
01 = Read/Write Least Si gnificant Byte (L SB)
10 = Read/Write Most Signif icant Byte (MS B )
11 = Read/Write LSB then MS B
WO
3:1 Counter Mod e Sele cti on
These bits select one of six possible modes of operation for
the se le ct e d cou n te r.
0 0 0 = Mode 0Out s ignal on en d of c ount (=0)
001 = Mode 1Hardware retriggerable one-shot
x 1 0 = Mode 2Rate generator (divide b y n c ounter)
x11 = Mode 3Square wave output
100 = Mode 4So ftw are trig ge r ed st robe
101 = Mode 5Hardware triggered strobe
WO
0Binary/BCD Countdown
Select
0 = Binary countdown is used. The larg e st poss ible binary
count is 216
1 = Binary cod e d de cimal (BCD) c ount is use d . The larges t
possible BCD cou nt is 1 04
WO
Device: 31 Function: 0
I/O Address: 43h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 357
8—Intel® 6300ESB ICH
8.3.1.1 RDBK_CMD—Read Back Command
Note: The Read Back Command is used to determine the count value, programmed mode,
and current states of the OUT pin and Null count flag of the selected counter or
counters. Status and/or count may be latched in any or all of the counters by selecting
the counter during the register write. The count and status remain latched until read,
and further latch commands are ignored until the count is read. Both count and status
of the selected counters may be latched simultaneously by setting both bit 5 and bit 4
to zero. When both are latched, the first read operation from that counter returns the
latched status. The next one or two reads, depending on whether the counter is
programmed for one or two byte counts, returns the latched count. Subsequent reads
return an unlatched count.
8.3.1. 2 LTCH_CMD—Counter Latch Command
Note: The Coun ter La tch C ommand latch es the cu rr ent cou nt v alue . Thi s comma nd is us ed to
insure that the count read from the counter is accurate. The count value is then read
from each counter's count register through the Counter Ports Access Ports Register
(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read
acco rd ing to the pro gramm ed form at , i.e., when the counte r is progra mm ed for two
byte counts, two bytes must be read. The two bytes do not have to be read one right
after the other (read, write, or programming operations for other counters may be
inserted between the reads). When a counter is latched once and then latched again
before the count is read, the second Counter Latch Command is ignored.
Table 233. RDBK_CMD—Read Back Command
Bits Name Description Access
7 :6 Read Back Command Must be “11” to sele ct th e Read Back Command
5Latch Count of Selected
Counters.
0 = Current count value of the se le cte d counte rs will be
latched
1 = Curr e nt count will not be latched
4Latch Status of Selected
Counters. 0 = Statu s of the se le cte d count er s will b e la tche d
1 = Sta tus will not be latched
3 Counte r 2 S e le ct. 1 = Cou nter 2 count an d /or status will be latche d
2 Counte r 1 S e le ct. 1 = Cou nter 1 count an d /or status will be latche d
1 Counte r 0 S e le ct. 1 = Cou nter 0 count an d /or status will be latche d.
0 Reserved Reserved. Must be 0.
Device: 31 Function: 0
Attribute: Read-Only
Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
358 Order Number: 300641-004US
8.3.2 SBYTE_FMT—Interval Ti mer St atus Byte Format
Register
Note: Each counter's status byte may be read following a Read Back Command. When latch
status is chosen (bit 4=0, Read Back Command) as a read back option for a given
counter, the next read from the counter's Counter Access Ports Register (40h for
coun te r 0, 4 1h fo r c oun ter 1, and 42 h for c ount er 2) ret urns th e status byt e. T he sta tus
byte returns the following:
Table 234. LTCH_CMD—Counter Latch Command
Bits Name Description Access
7:6 C ounte r Selection
These bits s el ect the counter f or latching. When “11” is
writte n, the write is interpreted as a read back command.
00 = Counter 0
01 = Counter 1
10 = Counter 2
5:4 Counter Latch Command 00 = Selects the Counter Latch Comm and.
3:0 Reserved Reserved. Must be 0.
Device: 31 Function: 0
Attribute: Read-Only
Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 359
8—Intel® 6300ESB ICH
Table 235. SBYTE_FMT—Interval Timer Status Byte Format Register
Bits Name Description Access
7 Counter OUT Pin State 0 = OUT pin of the counte r is also a 0.
1 = OUT pi n of the counter is also a 1. RO
6Count Register Status
This bit ind icates whe n the last count written to the Count
Register (CR) has been loaded into the counting elem ent
(CE). The e xac t time this happ e ns d epend s on the counter
mode, but until the count is loaded into the counting element
(CE) , th e cou nt value will b e incorrect.
0 = Count has been transferred from CR to CE and is
avail able for reading.
1 = Null Count. Count has not b een transferred from CR to CE
and is not ye t available for reading.
RO
5:4 Rea d /Writ e Se le ction
Status
These reflect the read/write selection mad e through bits[5:4]
of the control register. The binary codes returned during the
status rea d match the codes used to program the count er
read/write selection.
00 = Counte r Latc h Command
01 = Read/Write Least S ig nif ican t B y te (LSB )
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MS B
RO
3:1 Mode Selection Status
These bits return the counter m od e progra mming. The
binary cod e re turne d matches the code used to prog ram the
counte r mod e, a s lis te d under the bit function a b ove.
000 = Mo de 0:Out sign al on en d of coun t (=0)
001 = Mode 1: H ard wa re re trig g e rable one -shot
x10 = Mode 2: Rate generator (divide by n counter)
x11 = Mode 3: Square wave outp ut
100 = Mo de 4: S of tware triggered strobe
101 = Mode 5: Ha rd wa re trig g e re d s trob e
RO
0 Countdown Ty pe Status This bit reflec ts the current countdown type .
0 = Binary count do wn
1 = Bin ary Coded Decim a l (B CD) countdown. RO
Device: 31 Function: 0
I/O Address: C ounte r 0 = 40h,
Counte r 1 = 41h,
Counte r 2 = 42h Attribute: Read-Only
Defau lt Value: Bits [6:0] und e f ine d , Bit
7=0 Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
360 Order Number: 300641-004US
8.3.3 Counter Access Ports Register
8.4 825 9 Interrupt Cont roller (PIC) Registe r s
8.4.1 Interrupt Controller I/O M AP
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 13). These registers
have multiple functions, depending upon the data written to them. Listed in the table
below are descriptions of the different register possibilities for each address.
Table 236. Counter Access Ports Register
Bits Name Description Access
7:0 C ounter Port
Each counte r po rt add re ss is used to program the 1 6-bit
Count Register. T he or der of p rog ramming, either LS B onl y,
MSB only, or LSB then MSB, is defined with the Interval
Coun ter Contr o l R e gi ster at port 43h . T h e co unter port is al s o
used t o read the current count from the Count Register, and
return the status of the counter p rog ramming f ollowing a
Read Back Command.
R/W
Device: 31 Function: 0
I/O Address: Counter 0 - 40h,
Counte r 1 - 41h,
Counte r 2 - 42h Attribute: Read/Write
Defau lt Value: All bits undefined Size: 8-bit
Table 237. PIC Registers
Port A liases Register Name/Function Default
Value Type
20h 24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
Master PIC ICW 1 Init. Cmd Wo rd 1
Register Undefined WO
Maste r PIC OCW2 Op Ctrl Word 2
Register 001XXXXXb WO
Maste r PIC OCW3 Op Ctrl Word 3
Register X01XXX10b R/W
21h
25h, 29h,
2Dh, 31h,
35h, 39h,
3Dh
Master PIC ICW 2 Init. Cmd Wo rd 2
Register Undefined WO
Master PIC ICW 3 Init. Cmd Wo rd 3
Register Undefined WO
Master PIC ICW 4 Init. Cmd Wo rd 4
Register 01h WO
Maste r PIC OCW1 Op Ctrl Word 1
Register 00h R/W
A0h
A4h, A8h,
ACh, B0h,
B4h, B8h,
BCh
Slave PIC ICW1 Init. Cmd Word 1
Register Undefined WO
Slav e P IC O CW2 Op C tr l Word 2 R egi s t er 001XXXXXb WO
Slave PIC OCW3 Op Ctrl W ord 3 Register X01XXX10b R/W
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 361
8—Intel® 6300ESB ICH
8.4.2 ICW1—Initialization Command Word 1 Register
A write to Initialization Command Word 1 st arts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
A1h
A5h, A9h,
ADh, B1h,
B5h, B9h,
BDh
Slave PIC ICW2 Init. Cmd Word 2
Register Undefined WO
Slave PIC ICW3 Init. Cmd Word 3
Register Undefined WO
Slave PIC ICW4 Init. Cmd Word 4
Register 01h WO
Slave PIC OCW1 Op Ctrl Word 1 R egister 00h R/W
4D0h - M aster PIC Edge/ Level Triggered
Register 00h R/W
4D1h - Slave PIC Edge/L evel Trigg ere d R egi s ter 00h R/W
Table 237. PIC Registers
Port Aliases Register Name/Function Default
Value Type
Table 238. ICW1—Initialization Command Word 1 Register
Bits Name Description Access
7 :5 ICW/OCW se le ct These bits are MCS-85 specific, and not needed.
000 = Should be programmed to “000” WO
4 ICW/OCW select 1 = This bit must be a 1 to select ICW1 and enable the ICW2,
ICW3, and ICW4 seque nce. WO
3Edge/Level Bank Select
(LTIM) Disabled. Replaced by the edge/level triggered control
reg isters (E LCR). WO
2ADI
0 = Ignore d fo r th e Intel ® 6300ESB ICH. Should be
programmed to 0. WO
1Single or Cascade
(SNGL) 0 = Must be pr og ram me d to a 0 to indicate two controllers
operati ng i n casca de mode. WO
0ICW4 Write Required
(IC4) 1 = This bit must be programmed to a 1 to indicate that ICW4
needs to be programmed. WO
Device: 31 Function: 0
Offset: Mast er Controller - 020h
Slave Controller - 0A0h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
362 Order Number: 300641-004US
8.4.3 ICW2—Initialization Command Word 2 Register
Note: ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
Table 239. ICW2—Initialization Command Word 2 Register
Bits Name Description Access
7:3 Interrup t Vector Bas e
Address
Bits [7:3 ] define the base ad d ress in the inte rrupt vector
table for t he i nt err upt routi nes associat ed wi t h eac h inter ru pt
reques t le vel inp u t. WO
2:0 Inte rrupt Request Level
When writing ICW 2, the se bits should a ll be 0. D uring a n
interrupt acknowledge cycle, these bits are programmed by
the interrupt controller with the interrupt to be serviced. This
is combined with bits [7:3] to form the interrupt vector driven
ont o th e d ata bus during the secon d INT A# cycle. The code is
a three bit binar y code:
Code Master Interru ptSlave Inte rrupt
000 IRQ0 IRQ8
001 IRQ1 IRQ9
010 IRQ2 IRQ10
011 IRQ3 IRQ11
100 IRQ4 IRQ12
101 IRQ5 IRQ13
110 IRQ6 IRQ14
111 IRQ7 IRQ15
WO
Device: 31 Function: 0
Offset: Mast er Controller - 021h
Slave Controller - 0A1h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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8—Intel® 6300ESB ICH
8.4.4 ICW 3—Master Controller Initialization Command
Word 3 Register
8.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register
Tab le 240. ICW3—Master Controller Initialization Command Word 3 Register
Bits Name Description Access
7:3 0 = These bits must be progr am med to zero.
2Cascad e d Interrupt
Contro lle r IR Q
Connection
This bit indicate s tha t the slave controller is cascade d on
IRQ2. Wh en IRQ 8#-IRQ15 is asserted, it g oes throug h the
sla ve co ntrol l er’ s pri orit y res olv er. The slav e cont ro ller’s INTR
output ont o IRQ2. IRQ2 then goes through the master
con troller’s priority so lver. Wh en it wi ns, the IN TR sig na l is
asse rte d to th e processo r an d the re turning int er rupt
ackno wledge retur ns the interrupt vec tor for the slave
controller.
1 = This bit must always be programmed to a 1.
WO
1:0 0 = These bits must be progr am med to zero.
Table 241. ICW3—Slave Controller Initialization Command Word 3 Register
Bits Name Description Access
7:3 0 = These bits must be progr am med to zero.
2:0 Slave Identification Code
These bits are compared agai nst th e slav e identif icat i on code
broadcast by the master controller from the trai ling edge of
the first internal INTA# p ulse to the trailing edg e of the
second internal INT A# pulse. These bits must be programmed
to 02h to mat ch the cod e broadcast by the ma ster controller.
When 02h is broadc a st by the ma ster controller during t he
INTA # sequence, the slave controller assumes responsibility
for broadcasting the interrupt vector.
WO
Device: 31 Function: 0
Offset: 21h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Device: 31 Function: 0
Offset: A1h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
364 Order Number: 300641-004US
8.4.6 ICW4—Initialization Command Word 4 Register
8.4.7 OCW1—Operational Con trol Word 1 (Interrupt
Mask) Register
Table 242. ICW4—Initialization Command Word 4 Register
Bits Name Description Access
7:5 0 = These bits mu st be programmed to zero.
4Special Fully Nested
Mode (SFNM) 0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed. WO
3 Buffered Mode (BUF ) 0 = Must be programmed to 0 for the Intel® 6300ESB ICH.
This is non- b uf fere d mode. WO
2Master/Slave in Buffered
Mode Not used.
0 = Should always be programmed to 0. WO
1Autom a tic End of
Interrupt (AEOI)
0 = This bit should normally be pr og ram me d to 0. This is the
normal end of interrupt.
1 = Automa t ic En d o f I nterr u pt ( AE OI ) mode is pr o gr am m ed. WO
0 Microprocess or M od e
1 = Must be programmed to 1 to indica te tha t the controller
is operatin g in an Inte l® Arch i tectu r e - b a sed sy st e m.
NOTE: Programming this bit to 0 will result in improper
cont rolle r op e ra tion.
WO
Table 243. OCW1—Operational Con trol Word 1 (Interrupt Mask) Register
Bits Name Description Access
7:0 Interrupt Request Mask
When a 1 is writte n to an y bit in this regis te r, the
corresponding IRQ line is masked. When a 0 is written to any
bit in this register, the corresponding IRQ mask bit is cleared,
and inter r upt req ue sts will agai n be accepted by the
contr olle r. Ma sk ing IRQ2 on th e maste r control le r will a lso
mask the inte rrup t re q ue sts fro m the slave cont rolle r.
R/W
Device: 31 Function: 0
Offset: Mast er Controller - 021h
Slave Controller - 0A1h Attribute: Write-Only
Defau lt Value: All bits undefined Size: 8-bit
Device: 31 Function: 0
Offset: Mast er Controller - 021h
Slave Controller - 0A1h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 365
8—Intel® 6300ESB ICH
8.4.8 OCW2—O perational Control Word 2 Register
Note: Following a part reset or ICW initialization, the controller enters the fully nested mode
of op eration. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
Table 244. OCW2—Operational Control Word 2 Register
Bits Name Description Access
7:5 Rotate and EOI Codes
(R, SL, EOI)
These three bits control the Rotate and End of Interrupt
modes and combination s of the two.
000 = Rotate in Auto E OI Mod e (C lea r)
001 = Non-specific EOI command
010 = No Operation
011 = Specific EOI Command
100 = Rotate in Auto EOI M od e (Set)
101 = Rotate on Non-S pec ifi c EOI Com man d
110 = *S et Priority Command
111 = *Rotate on Specific EOI Com mand
*L0 - L2 Are Used
WO
4 :3 OCW2 S e lect When selecting OC W 2 , bits 4:3 = “00 WO
2:0 Interrup t Level S e le ct
(L 2, L1 , L0)
L2, L1, and L0 determine the interrupt level acted upon when
the SL bit is activ e . A s imp le binary code, ou tline d below,
selec ts the channe l f or the com mand to act upon. When the
SL bit is inac tive, these b its do not have a define d function;
progra mming L2, L1 and L0 to 0 is suf fi cie n t in th is ca se .
Bits Int err u pt Leve lB its Int errupt Level
000 IRQ0/8 100 IRQ4/12
001 IRQ1/9 101 IRQ5/13
010 IRQ2/10 110 IRQ6/14
011 IRQ3/11 111 IRQ7/15
WO
Device: 31 Function: 0
Offset: Mast er Controller - 020h
Slave Controller - 0A0h Attribute: Write-Only
Defau lt Value: Bit[4:0]=undefined,
Bit[7:5]=001 Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
366 Order Number: 300641-004US
8.4.9 OCW3 —Operational Con trol Word 3 Register
Table 245. OCW3—Operational Control Word 3 Register
Bits Name Description Access
7 Reserved Reserved. Must be 0.
6Spec ial Mask Mode
(SMM)
1 = The Special Mask Mode may be used by an interrupt
service routine to dynamically alter the system priority
str ucture whi le the routin e is ex ecuting , through select ive
enabling/disabling of the other channel's mask bits. Bit 5,
the ESMM bit, mus t be set for this bit to have any
meaning.
WO
5Enab le S pecial Mask
Mode (ESMM)
0 = Disable. The SMM bit becomes a don't care”.
1 = Enabl e the SM M bi t to set or re set the Spe cial M ask
Mode. WO
4:3 O CW 3 Sele ct When sele cting OCW 3, bits 4:3 = ‘01’. WO
2Poll Mode Command
0 = Dis abl e. Poll Comman d is not issued .
1 = Ena bl e. The next I /O re ad to th e inte rru p t controller is
trea ted a s an interru pt acknow l edge cy c le . An encoded
byte is driven onto the data bus, representing the highest
priority le vel requesting se rvice.
WO
1:0 Register Read Command
These bi ts pr ovi de c o ntrol fo r readi ng t he I n- Servi c e R e gi ster
(ISR) and the Interrup t Req u est Regist er (IRR) . When bit
1=0, bit 0 will not af fect the register read selection. When bit
1=1, b it 0 select s th e regi ster statu s r e tu rn e d following a n
OCW3 read . W h e n bit 0= 0, the I RR will b e read. W he n bi t
0=1, the ISR will b e read. Following ICW init ialization, the
default OCW3 port address read will be “read IRR. To retain
the c ur ren t se le ctio n ( read I SR or r ead IRR), al ways write a 0
to bi t 1 wh en progr amming th is r egister. The selec ted regi ster
may be read repeatedly without reprogramming OCW3. To
select a n e w sta tus regi st e r, OC W 3 must be reprogramme d
prior to attempting the read .
00 = No Action
01 = No Action
10 = Rea d IRQ Re gi ster
11 = Rea d IS Re gi ster
WO
Device: 31 Function: 0
Offset: Mast er Controller - 020h
Slave Controller - 0A0h Attribute: Write-Only
Defau lt Value: Bit[6,0]=0,
Bit[7,4:2]=undefined,
Bit[5,1]=1 Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
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8.4.10 ELCR1—Master Controller Edge/Level Triggered
Register
Note: In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
8.4.11 ELCR2—Slave Controller Edge/Level Triggered
Register
Note: In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
lev el mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Table 246. ELCR 1—Mas ter C ontroller Edge/Level Triggered Register
Bits Name Description Access
7IRQ7 ECL
0 = Ed ge.
1 = Level. R/W
6IRQ6 ECL
0 = Ed ge.
1 = Level. R/W
5IRQ5 ECL
0 = Ed ge.
1 = Level. R/W
4IRQ4 ECL
0 = Ed ge.
1 = Level. R/W
3IRQ3 ECL
0 = Ed ge.
1 = Level. R/W
2:0 Reserved Reserved. Must be 0.
Table 247. ELCR2—Slave Controller Edge/Level Triggered Register (Sheet 1 of 2)
Bits Name Description Access
7 I RQ15 ECL 0 = Edge.
1 = Level. R/W
6 I RQ14 ECL 0 = Edge.
1 = Level. R/W
5 Reserved Reserved. Must be 0.
4 I RQ12 ECL 0 = Edge.
1 = Level. R/W
Device: 31 Function: 0
Offset: 4D0h Attribute: Read-Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 0
Offset: 4D1h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
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8.5 Advanced Inter rupt Cont ro ller (A PIC0)
There are two APICs in the Intel® 6300ESB ICH: APIC0 and APIC1 (device29, function
5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, only
primary (legacy) PCI device may write to these registers. APIC1’s direct registers are
assigned with base address FEC1xxxxH. To support legacy device/drivers on external
PCI bus used with the Intel® ICHx, APIC1 has an alternate base address, FEC0xxxxH.
This means external PCI devices may write to the IRQ pin assertion register (either
FEC0_0020H or FEC1_0020H) to generate interrupts from APIC1.
Si nce th e Inte l® 6300ES B ICH doe s not i mpleme nt Hub In ter face EO I s pecia l cyc le, t he
MCH will translate EOI special cycle to a memory write cycle to EOI register at address
FEC0_0040H and pass it to the Intel® 6300ESB ICH. This memory write cycle will be
passed to both APIC0 and APIC1 internally.
From the CPU/MCH point of view, it should always use address FEC0xxxxH to access
APIC0 registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not
respond to the CPU/MCU’s access to address FEC0xxxxH, other than the EOI cycle
stated above.
APIC0 also includes an XAPIC_EN config bit. This bit must be se t to enable the I/O (x)
APIC extension to the I/O APIC. This allows the extended feature to be disabled if a
problem is found. For APIC1, this extension is always enabled.
8.5 .1 A PIC Register Ma p
The APIC is accessed through an indirect addressing scheme. Two registers are visible
by software for manipulation of most of the APIC registers. These registers are mapped
into m emo ry spa ce and are sh o wn in Table 248.
3IRQ11 ECL
0 = Edge.
1 = Level. R/W
2IRQ10 ECL
0 = Edge.
1 = Level. R/W
1IRQ9 ECL
0 = Edge.
1 = Level. R/W
0 Reserved Reserved. Must be 0.
Table 247. ELCR2—Slave Controller Edge/Level Triggered Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: 4D1h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Table 248. APIC Direct Registers
Address Register Size Type
FEC0_0000h Index Regis te r 8 bits R/W
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Table 249 lists the registers which may be accessed wi thin the APIC through the Index
Register. When accessing these registers, accesses must be done a DWORD at a time.
For example, software should never access byte 2 from the Data register before
accessing bytes 0 and 1. The hardware will not attempt to recover from a bad
programming model in this case.
8.5.2 IND—Index Register
Note: The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in Table 249. Soft wa re
will program this register to select the desired APIC internal register.
8.5.3 DAT—Data Registe r
This is a 32-b it r egiste r spe cif yi ng the da ta to be r ead or writte n to t he regis ter pointe d
to by the Index register. This register may only be accessed in DWORD quantities.
FEC0_0010h Data Register 32 bits R/W
FECO_0020h IRQ Pin Assertion Reg ister 32 bits WO
FECO_0040h EOI Register 32 bits WO
Table 248. APIC Direct Registers
Table 249. AP IC Indirect Registers
Index Register Size Type
00 ID 32 bits R/W
01 Version 32 bits RO
02 Arbitration ID 32 bits RO
03 Boot Configuration 32 bits R/W
03-0F Reserved RO
10 -11 Redirection Table 0 64 bits R/W
12 - 13 Redirection Table 1 64 bits R/W
... ... ... ...
3E-3F Redirect ion Table 23 64 bits R/W
40-FF Reserved RO
Table 250. IND—In dex Register
Bits Name Description Access
7 :0 APIC In dex T his is a n 8-b it pointer into th e I/O APIC reg ister table. R/W
Device: 31 Function: 0
Offset: FEC0_0000h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
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8.5.4 Offset FEC0 _0020h: IRQPA— IRQ P in Asse rtion
Register
Note: The IRQ Pin Assertion Register is present to provide a mechanism to scale the number
of interrupt inputs into the I/O APIC without increasing the number of dedicated input
pins. When a device that supports this interrupt assertion protocol requires interrupt
service, that device will issue a write to this register. Bits 4:0 written to this register
cont ai n th e IRQ number for thi s interru pt . The only va lid va lues are 0-23. Bi ts 31:5 are
ignored. To provide for future expansion, peripherals should always write a value of 0
for Bits 31:5.
See Secti on 5.7.4, “Interrupt Mapping for more details on how PCI devices will use
this field.
Note: Writes to this register are only allowed by the processor and by masters on the Intel®
6300ES B ICH s PCI bus . W ri tes by d evic es on P CI b uses above th e Inte l® 6300ESB I CH
are not sup por ted.
8.5.5 Offset FEC0 - EOIR: EOI Register
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower eight bits
written to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entr y will be cle ared.
Note: This is similar to what already occurs when the APIC sees the EIO message on the
serial bus. Note t hat if multiple I/O R edirection entries, for any reason, assign the same
Table 251. DAT—Data Register
Bits Name Description Access
7:0 AP IC Data This is a 32-b it re g iste r f or the data to be read or writte n to
the APIC indirect register pointed to by the Index register. R/W
Device: 31 Function: 0
Offset: FEC0_0010h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Table 252. Offset FEC0_0020h: IRQPA—IRQ Pin Ass ertion Register
Bits Name Description Access
31:5 Reserved Reserved. To provide for future expansion, the processor
should always write a value of 0 to Bits 31:5.
4:0 IRQ Numb er Bits 4:0 written to this regist er contain the IRQ number for
this interrupt. The only valid value s are 0-23. WO
Device: 31 Function: 0
Offset: FEC0_0020h Attribute: Write-Only
Defau lt Value: N/A Size: 32-bit
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vector for more than on e interrupt input, each of those entries will have the
Remote_IRR bit reset to zero. The interrupt which was prematurely reset will not be
lost because if its input remained active when the Remote_IRR bit is cleared, the
interrupt will be reissued and serviced at a later time.
8. 5.6 Offset 00h: ID—Identificatio n Register
Note: The APIC ID serves as a physi c al name of th e APIC. The APIC bus arb i trati on ID for the
APIC is derived from its I/O APIC ID. This register is reset to zero on power up reset.
Table 253. Offset FEC0 - EOIR: EOI Register
Bits Name Description Access
31:8 Reserved Reserved. To provide for fut ure expansion, the pro cessor
sho uld al ways wr ite a value of zero to B its 31 :8.
7:0 Redirecti o n En tr y C lear
When a write is issued to this register, the I/O APIC will check
this field, and compare it with the vector field for each entry
in the I/O Redirection Table. When a match is found, the
Remote_IRR b it f or tha t I/O Redirection Entry will b e clea re d .
WO
Table 254. Offset 00h: ID—Identification Register
Bits Name Description Access
31:2
8Reserved Reserved.
27:2
4APIC ID Software must program this value before using the APIC. R/W
23:1
6 Reserved Reserved.
15 Scratchpad Scratchpad bit.
14:0 Reserved Reserved.
Device: 31 Function: 0
Offset: FEC0_0040h Attribute: Write-Only
Defau lt Value: N/A Size: 32-bit
Device: 31 Function: 0
Offset: 00h Attribute: Read/Write
Defau lt Value: 00000000h Size: 16-bit
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8.5.7 Offset 01h: VER—Version Register
Note: Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their v ersions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
8.5.8 Offset 02h: ARBID Arbitration ID Register
Note: This register contains the bus arbitration priority for the APIC. When the APIC Clock is
running, this register is loaded whenever the APIC ID register is loaded. A rotating
pr io ri ty sc heme is used fo r APIC bu s arb it ra ti on. The wi nner of th e arb it r ati on be come s
the lowest priority agent and assumes an arbitration ID of zero.
Table 255. Offset 01h: VER Version Register
Bits Name Description Access
31:2
4Reserved Reserved.
23:1
6Maximum Redirection
Entries
This is the entry numbe r (0 being the lowe st entry) of the
highest entry in the r edirection table. It is equal to the
number of interrupt input pins minus one and is in the range
0 through 239 . In the Intel® 6300ESB ICH this field is
hardwired to 17h to indicate 24 inte rrup ts.
RO
15 PRQ This bit is set to 1 to indicate that this version of the I/O APIC
impl em ent s th e IR Q Assertio n r egi s ter and allows P CI devices
to write to it to cause interrupts. RO
14:8 Reserved Reserved.
7:0 Version This is a version number that identifies the implementation
ver sion . The version number assigned to t he Intel ® 6300ESB
ICH for the I/O (x) APIC is 20h. RO
Table 256. Offset 02h: ARBID—Arbitration ID Register
Bits Name Description Access
31:2
8Reserved Reserved.
27:2
4I/O APIC Identi fication This 4-bit field contains the I/O APIC Arbitration ID. RO
23:0 Reserved Reserved.
Device: 31 Function: 0
Offset: 01h Attribute: Read-Only
Defau lt Value: 00170020h Size: 32-bit
Device: 31 Function: 0
Offset: 02h Attribute: Read-Only
Defau lt Value: 00000000h Size: 32-bit
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8. 5.9 Offset 03h: BOOT_CONFIG—Boot Confi guration
Register
8.5.10 Offset 10h - 11h (Vecto r 0) through 3E - 3F h
(Vector 23): Redirection Table
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the inte rrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC bus unit that the interrupt message was sent
ov er the APIC bus. Onl y then wi ll the I/O APIC be abl e to reco gniz e a new edg e on that
interrupt pin. That new edge will only result in a new invocation of the handler if its
acceptance by the destination APIC causes the Interrupt Request Register bit to go
from 0 to 1. (i.e., when the interrupt was not already pending at the destination).
See Table 259 for Delivery Mode Encoding information.
Table 257. Offset 02h: ARBID—Arbitration ID Register
Bits Name Description Access
31:1 Reserved Res erved
0 DT: Deliv e ry Type Hardwire to 1. Interrupt delivery mechanism is always a
Processor System Bus message. RO
Device: 31 Function: 0
Offset: 02h Attribute: Read-Only
Defau lt Value: 00000000h Size: 32-bit
Table 2 58. Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection
Table
(Sheet 1 of 2)
Bits Name Description Access
63:5
6Destination
When b it 11 of this entry is 0 [Physical], then bits [59:56]
specify an APIC ID. In this case, bits 63:59 should b e
programmed by software to 0.
When b it 11 of this e ntry is 1 [Logical], bits [63: 56] spe cif y
the log ica l desti n a tion a ddress of a se t of processors.
R/W
55:4
8Extended Destination ID
(EDID) These bits are only s ent to a local APIC when in Processor
System Bus mode. They become bits [11:4] of the address.
47:1
7Reserved Res er ved . So ftwar e s hould pr og ram th ese bits to 0
Device: 31 Function: 0
Offset: 10h-11h (v ector 0)
through
3E-3Fh (vector 23) Attribute: Read/Write
Defau lt Value: Bit 16-1, Bits[15:12]=0.
All other bits undefined
Size: 64-bit ( a cce ssed as tw o 32 bi t
quantities)
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16 Mask
0 = Not masked: An edge or level on this interrupt pin results
in the deliv er y of the inte rrupt to the destin ation.
1 = Masked: Inter rup ts are not delivered nor held pending .
Setting this bit after the inte rrupt is accep te d by a local
APIC has no effect on that interrupt. This behavior is
identical to the device withdrawing the interrupt before it
is posted to the processor. It is software's responsibility
to deal with the case where the mask bit is set after the
interrupt message has been accepted by a local APIC unit
but before the i nterrupt is dispensed to the processor.
R/W
15 Trigger Mode
This field indicates the type of signal on the interrupt pin that
trigge rs a n inte rrupt.
0 = E dge triggere d.
1 = Level triggered.
R/W
14 Remote IRR
This bit is used for level triggered interrupts (in Fix ed or
Lowe st p riority Delivery Mo d e s only); its meaning is
undefined f or e dge trig g ere d interrupts. For level trigger ed
interrupts, this bit is set if the I/O APIC succ essfully sends the
level interrupt vector in th is entry. This bit is ne ver set for
SMI, NMI, INT or ExtINT del ivery modes.
R/W
13 Interrup t Inpu t Pin
Polarity
This bit specifies the polarity of each inte rrupt sign al
connecte d to the interrupt pins.
0 = Active hig h.
1 = Active low.
R/W
12 D elivery St atus
This field contains the current status of the delivery of this
interrupt. Write s to this bit have no e ffect.
0 = Idle. No activity for this interrupt.
1 = Pendi ng. I nt er ru pt has been injected, but del i very i s h eld
up due to the APIC bus being bus y or the inability of the
receiving APIC unit to accep t the inte rrup t at this time.
RO
11 Destination Mode
This field determines the interpreta tion of the Destin ation
field.
0 = Physical. Destination APIC ID is identified by bits [59:56].
1 = Logical. Dest ina tions a re identif ie d by ma tching bit
[63:56 ] with the Logical Desti na tion in th e Destination
Format Register and Logical Destination Register in each
Local API C.
R/W
10:8 De livery Mode
This field sp e cif ie s h ow the APICs l iste d in t he destination
field should act upon reception of this signal. Certain D elivery
Modes will only operate as intended when used in conjunction
with a specific trigger mode. These encodings are listed in the
note below:
R/W
7:0 Vector This field contains the interrupt vector for this inte rrup t.
Values range between 10h and F Eh. R/W
Table 258. Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection
Table
(Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
Offset: 10h-11h (v ector 0)
through
3E-3Fh (vector 23) Attribute: Read/Write
Defau lt Value: B it 16-1, Bits[15:12]=0.
All other bits undefined
Size: 64-bit ( a cce ssed as tw o 32 bi t
quantities)
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8.6 Real Time Clo ck Reg ister s
8.6.1 I/O Register Address Map
The RTC internal registers and RAM are organized as two banks of 128 bytes each,
called the standard and extended banks. The first 14 bytes of the standard bank
contain the RTC time and date information along with four registers, A - D, that are
used for configuration of the RTC. The extended bank contains a full 128 bytes of
battery backed SRAM, and will be accessible even when the RTC module is disabled
(through the RTC configuration register). Registers A-D do not physically exist in the
RAM.
All data move ment betw een th e h ost pro ce ssor a nd the re al- time c lo ck i s done th rough
registers mapped to the standard I/O space. The register map appears in Table 260.
Table 259. Delivery Mode Encoding
Bits Description
000 Fixed: Deliv er the signal on the INTR sign al of all processor core s listed in the
destination. Tr igger Mode may be edge or level.
001 Lowest Priority: Del iver th e sig nal on t he INTR sig nal of th e pro ce ssor co re that is
exec ut ing a t th e lowe st p riority among al l the processors listed in the specified
destination. Tr igger Mode may be edge or level.
010 SMI (S yste m Mana ge ment In ter rupt) : R equi res the interr upt to b e progr ammed
as edge t r i gge re d. The vector inf orm at ion i s i gno r ed b ut mus t be p rogrammed to al l
ze roe s for f u ture compatibi lity. -- no t sup po rte d .
011 Reserved
100
NMI: Deliver the sign al on the NMI s ignal o f all processor cores listed in the
destination. Vector inf ormation is ignored. NMI is tre ate d a s an e dge trig g er e d
interrupt even when it is progra mmed as level triggered. For proper operation this
redirec tion table entry must be programmed to edge triggered. The NMI delivery
mod e does no t set th e RIRR bit . O nce the in terru p t is d e te cte d , it will be sent over
t he APIC b u s. W he n the re di re ction table is inc orre ctly set to leve l, the loop count
w ill continue coun ting throug h the red ire ction table add resses. Onc e the count for
th e NMI p in is re a ched again, the inte rrupt will be sent over the AP IC bus a gain. --
not supported.
101
INIT: De liv e r the signal to all proce ssor core s listed in the destination b y as se rting
the INIT signal. A ll address e d lo cal APICs will assum e their INIT state. INIT is
always treated as an edge triggered interrupt even when programmed as level
triggered. For proper operation this redirection table entry must be programmed to
edge triggered. The INIT delivery mode does not set the RIRR bit. Once the
interrupt is detected, it will be sent over the APIC bus. When the redirection table is
incorrectly set to level, the loop count will continue counting through the redirection
t able addresses. Once the co u nt for the INIT pin is re ache d again, th e interrupt will
be sent over the APIC bus again. -- not supported.
110 Reserved.
111
ExtINT: Deliver the sig na l to the IN TR s ignal o f all proc es sor cores listed in the
destination as an interrupt that originated in an externall y conne cted 8259A
comp atib le inte rrupt control ler. The INTA cycle that co rre sp ond s to this Ex tIN T
deliv e ry will be routed to the e xt er na l cont roller that is expected to supply the
vector. Requires the interrupt to be pr ogrammed as edge t riggered.
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8.6.2 Indexed Registers
The RTC contains two sets of indexed registers that are accessed using the two
separate Index and Target registers (70/71h or 72/73h), as shown in Table 261.
Table 260. RTC I/O Registers
I/O
Locations When U128E bit = 0 Functi on
70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Inde x Register
NOTE: Writes to 72h, 74h and 76h do not affect the
NMI enab le (bit 7 of 70h )
71h and 75h Also alias to 73h and 77 h Real-Time Clock (Standard RAM) Target Register
72h and 76h Extend e d RAM Index Register (when enab le d)
73h and 77h Extended RAM Target Register (when enabled)
NOTES:
1. I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for
this bank is shown in Table 261. Locations 72h and 73h are f or accessing the extended RAM.
The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used
as the address pointer and I/O address 73h is used as the data register. Index addresses
above 127h are not valid. When the extended RAM is not needed, it may be disabled.
2. Sof tware must preserve the value of bit 7 at I/O addresses 70 h and 74h. When writing to
these addresses, software must first read t he value, and then write the same value for bit 7
during the sequential address write.
Table 261. RTC (Standard) RAM Bank
Index Name
00h Seconds
01h Second s Alarm
02h Minutes
03h Minutes Alarm
04h Hours
05h Hours Alarm
06h Day of Wee k
07h Day of Mo nth
08h Month
09h Year
0Ah Registe r A
0Bh Registe r B
0Ch Register C
0Dh Register D
0Eh - 7Fh 114 By te s of User RA M
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8.6.2.1 RTC_REGA—Regis ter A
Note: T his reg iste r i s u sed for gener al co nfiguratio n of th e R TC func tions . No ne of the bi ts are
affected by RSMRST# or any other Intel® 6300ESB ICH reset signal.
Table 262. RTC_RE GD—Registe r D ( Flag Register)
Bits Name Description Access
7 UIP: Update In Progress
This bit may be monitored as a status flag.
0 = The up date cycle will n ot start for at leas t 492 µs. The
time, calendar, and alarm information in RAM is always
avai la ble when the UIP bit is 0.
1 = The update is soon to occur or is in progress.
R/W
6:4 DV [2:0]: Division Chain
Select
The se three bits control the divide r ch ain f or the oscillator,
and are not affected by RSMRST# or any other reset signal.
DV[2] corresponds to bit 6.
010 = Normal Operation
11X = Divi der Rese t
101 = Byp ass 15 s tages (te st mod e only )
100 = Byp ass 10 s tages (te st mod e only )
011 = Byp ass 5 st ages (tes t mod e only )
001 = Invalid
000 = Invalid
R/W
3:0 RS[3: 0] Rat e S e lect
Sele cts on e of 13 tap s of the 15 stag e divid e r chain. The
selec te d tap may gene rate a period ic interrupt when the PIE
bit is set in Register B. Otherwise this tap will se t th e PF f la g
of Register C. Whe n the periodic interr upt is not to be used,
these bits should all be set to zero. RS3 corresponds to b it 3.
0000 = Inte rrup t ne ver tog g les
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
0101 = 488.281 µs
0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
R/W
Device: 31 Function: 0
RTC Index: 0A Attribute: Read/Write
Defau lt Value: Undefined Size: 8-bit
Lockable: No Power Well: RTC
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8.6.2.2 RTC_REGB—Register B (General Configuration)
Table 263. RTC_REGB—Register B (General Configuration)
Bits Name Description Access
7SET: Update Cycle
Inhibit
Enables/Inhib its the upd ate cycles. This bit is not aff ecte d by
RSMRS T# nor any other re se t signal.
0 = Update cycle occurs normally once each second.
1 = A current up date cycle will abort and subsequ e n t update
cycles will not occur unt il SET is re tu rne d to zero. When
set is one, th e BI OS may initialize time an d cale n d a r
bytes sa f e ly.
R/W
6PIE: Periodic Interrupt
Enable
This bit is cleared by RSMRST#, but not on any other reset.
0 = Disabl e.
1 = Allows an interrupt to occur with a time base set with the
RS bits of register A.
R/W
5AIE: Ala rm Inter r u pt
Enable
This bit is clea re d by RSM RST#, but not on any othe r rese t.
0 = Disabl e.
1 = All ow s an in te rrupt to occu r when t he AF is se t by an
alarm match from the update cycle. An alarm may occur
once a second , one a n hour, once a day, or one a month.
R/W
4UIE: Upd ate-Ended
In te rru p t En able
This bit is cleared by RSMRST#, but not on any other reset.
0 = Disabl e.
1 = All ow s an in te rrupt to occu r when t he up d a te cycle ends. R/W
3SQWE : Squ are Wave
Enable
This bit serves no function in the Intel® 630 0ES B ICH . It is
left in thi s re gi ste r b an k to provid e comp a tib ility with th e
Motorola* 146818B. The Intel® 6300ESB ICH has no SQW
pin. This bit is cleared by RSMRST#, but not on any other
reset.
R/W
Device: 31 Function: 0
RTC Index: 0Bh Attribute: Read-Write
Defau lt Value: U0U00UUU (U:
Undefined) Size: 8-bit
Lockable: No Power Well: RTC
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2 DM: Data Mode
Specifies either binary or BCD data representation. This bit is
not af fected by RSMRST# no r any ot he r reset sign a l.
0 = BCD
1 = Binary
R/W
1HOURFORM: Hour
Format
Indicates the hour by te format. This bit is not affected by
RSMRST # nor any other reset signal.
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit
represents AM as zero and PM as one.
1 = Twenty-four hour mode.
R/W
0DSE: D aylight Savi ngs
Enable
Triggers two special hour updates per year. The days for the
hour adjustme nt are those specified i n United Stat es feder a l
law as of 1987, which is different than prev ious y ears. T his b it
is no t affe cte d by RSMRST# nor any othe r re se t signal .
0 = Daylight S avings Time upd a tes do not occu r.
1 = a) Update on the first Sunday in April, where time
increme nts f rom 1:59:59 AM to 3:00:00 A M.
b) Updat e on the last Sunday in Octob e r when the time
first reac he s 1:59:59 AM, it is changed to 1:00:00 A M.
The time must increment normally for at least two update
cyc les (seco nds) pr evious to these c onditio ns for the ti me
change to occur properly.
R/W
Tab l e 263. R TC_ RE GB Re gis te r B (Ge ne ra l Conf igu r a tion )
Bits Name Description Access
Device: 31 Function: 0
RTC Index: 0Bh Attribute: Read-Write
Defau lt Value: U0U00UUU (U:
Undefined) Size: 8-bit
Lockable: No Power Well: RTC
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
380 Order Number: 300641-004US
8.6.2.3 RTC_REGC—Register C (Flag Register)
Note: Writes to Register C have no effect.
8.6.3 RTC_REGD—Register D (Flag Register)
Table 264. RTC_ REGC—Register C (Flag Register)
Bits Name Description Access
7IRQF: Interrupt Request
Flag
IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This also causes
the CH_IRQ_B signal to be asserted. This bit is cleared upon
RSMRST# or a read of Register C. RO
6PF: Pe riodic Inte rrup t
Flag
This bit is cleared upon RSMRST# or a read of Register C.
0 = When no taps are specified through the RS bits in
Register A, th is f lag will n ot b e set .
1 = Periodic inter rup t Fla g will b e 1 whene v er th e tap
specif ie d by th e RS b its of re gi ste r A is 1.
RO
5 AF: Alarm Flag 0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alar m Flag will be set after all Alarm value s match t he
current time. RO
4UF: Update-ended Flag
0 = The bit is cleare d upon RSMR S T # or a read of Registe r C.
1 = Set immediat e ly following an upd ate cycle for ea ch
second. RO
3:0 Re serv ed Res er ved. Wil l alwa ys repor t 0.
Table 265. RTC_ REGD—Register D (Flag Register)
Bits Name Description Access
7VRT: Valid RAM an d
Time Bit
0 = This bit should always be written as a 0 for write cycle,
however it will return a 1 fo r re a d cycle s.
1 = This bit is hard-wi re d to 1 in the RTC power well. R/W
6Reserved
Reserved. This bit alwa ys re turns a 0 a nd should b e set to 0
for write cycles.
5:0 Date Alarm
These bits store the date of month alarm value. When set to
000000b, then a “d oe s not car e” state is ass ume d . The host
must configure the date alarm for these bits to do anything,
yet they may be writte n at a ny tim e. When the d ate ala rm is
not enabled, thes e bits will re tu rn zeros to mim ic the
function ality of the Motorola 146818B. The se bit s are not
affected by RESET.
R/W
Device: 31 Function: 0
RTC Index: 0Ch Attribute: Read-Only
Defau lt Value: 00U00000 (U:
Undefined) Size: 8-bit
Lockable: No Power Well: RTC
Device: 31 Function: 0
Offset: 0Dh Attribute: Read/Write
Defau lt Value: 10UUU UUU (U:
Undefined) Size: 8-bit
Lockable: No Power Well: RTC
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 381
8—Intel® 6300ESB ICH
8.7 CPU Interface Registers
8.7.1 NMI_SC—NMI Status and Control Register
I
Table 266. NMI_SC—NMI Status and Control Register
Bits Name Description Access
7SERR#_NMI_STS:
SERR # NMI Sou r c e
Status
1 = PCI agent detected a system error and pulses the PCI
SERR# line. This interrupt source is enabled by setting bit
2 to 0. T o reset the interrupt, set bit 2 to 1 and then set it
to 0. When writing to port 61h, this bit must be 0.
RO
6IOCHK_NMI_STS:
IOCHK # NMI Source
Status
1 = An ISA ag ent (thro u gh SER IR Q) asser ted I OC HK# on the
ISA bus. This interrup t source is en a b le d by se tting bit 3
to 0. To reset the inte rrupt, set bit 3 to 0 and then se t it
to 1. When writing to port 61h, this bit must be a 0.
RO
5TMR2_OUT_STS: Timer
Counter 2 OUT Status
This bit re fl ects the current state of the 82 54 counter 2
output. Counte r 2 mus t be programmed fo llowing any PCI
reset for this bit to have a de terminate value. When writing to
port 61h, this bit must be a 0.
RO
4REF_TOGGLE: Ref resh
Cycle Toggle
This signal toggles from either 0 to 1 or 1 to 0 at a rate that is
equivalent to when refresh cycles would occur. When writing
to port 61h, this bit must be a 0. RO
3IOCHK_NMI_EN:
IOCHK# NMI Enable 0 = Enabled.
1 = Disabled and cleared. R/W
2PCI_S ERR_EN : PCI
SERR# Enable 0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared. R/W
1SPKR_DAT_EN: Speaker
Data Enable
0 = SPKR outp ut is a 0.
1 = SPKR outp ut is eq uivalent to the Counter 2 O UT signa l
value. R/W
0TIM_CNT2_EN: Timer
Counter 2 Enable 0 = D isab le
1 = Enable R/W
Device: 31 Function: 0
Offset: 61h Attribute: Read/Write, Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
382 Order Number: 300641-004US
8. 7.2 N MI_E N—N MI En abl e ( and R eal T im e Clo ck In dex )
Note: The RTC Index field is write-only for normal operation. This field may only be read in
Alt-Access Mode. This register is aliased to Port 74h, and all bits are readable at that
address.
8.7.3 PORT9 2—Fas t A20 and Ini t Register
Table 267. NMI_EN—NMI Enable (and Real Time Clock Index)
Bits Name Description Access
7 NMI_EN: NMI Enable 0 = En able NMI sources.
1 = Dis a ble All NMI sources. R/W
6:0 RTC_INDX: Real T ime
Clock Index Address This data goe s to the RTC to select which re g ister or CMOS
RAM address is being accessed. R/W
Table 268. PORT92—Fast A20 and Init Register
Bits Name Description Access
7:2 Reserved Reserved.
1ALT_A20_GATE:
Alte r nat e A2 0 Gate
This bit is ORed with the A20 G ATE input signal to g en erate
A20M# to the p roce ssor.
0 = A2 0M # sig na l may potentia lly go active.
1 = This bit is set when INIT# goes active.
R/W
0 INIT_NOW When this bit transitions from a 0 to a 1, the Intel® 6300ES B
ICH will forc e INIT # activ e for 16 PCI cloc ks . R/W
Device: 31 Function: 0
i/O Address: 70h Attribute: Read/Write (Special)
Defau lt Value: 80h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
i/O Address: 92h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 383
8—Intel® 6300ESB ICH
8.7.4 COPROC_ERR— Coprocessor Error Register
8. 7.5 RST_CNT—Res et Con trol Register
Table 269. COPROC_ERR—Coprocessor Error Register
Bits Name Description Access
7:0 COPROC_ERR
Any value wri tte n to this re gister will ca use IG N N E# to g o
active, if FERR# had generated an internal IRQ13. For FERR#
to generate an internal IRQ13, the COPRO C_ERR_EN bit
(Device 31:Function 0, Offset D0, Bit 13) must be 1.
WO
Tabl e 27 0. RST_ C N T— Re set Con trol Re g ist er
Bits Name Description Access
7:4 Reserved Reserved.
3 FULL_RS T: Full Res e t
This bit is used to determine the states of SLP_S3#, SLP_S4#
and SLP_S5# after a CF9 hard reset (SYS_RST =1 and
RST_CPU is s et to 1), after PWROK going low (with RSMRST#
high), or after two TCO timeouts.
0 = The Intel® 6300ESB ICH will keep SLP_S3#, SLP_S4#
and SLP_ S5# high.
1 = The Intel® 6300ESB ICH will drive SLP_S 3#, S LP_S4#
and SL P_S5# low for 3 - 5 seconds.
R/W
2RST_CPU: Reset CPU
When this bit transitions from a 0 to a 1, it initiates a hard or
soft res et , a s determined by the SYS_ RS T b it (bit 1 of this
register). R/W
1SYS_RST: System Reset
This b it is used to determine a hard or soft re set to the
processor.
0 = When RST_CPU bit goes from 0 to 1, the Intel® 6300ESB
ICH performs a soft reset by activating INIT# for 16 PCI
clocks.
1 = When RST_CPU bit goes from 0 to 1, the Intel® 6300ESB
ICH performs a hard reset by activating PXPCIRST# for 1
millisecond. It also resets the resume well bits (except for
those no ted throughout the datasheet). The SLP_S3#,
SLP_S4#, and SLP_S 5# sig n als will n ot g o activ e.
R/W
0 Reserved Reserved.
Device: 31 Function: 0
i/O Address: F0h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: CF9h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
384 Order Number: 300641-004US
8.8 Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
other w ise indi ca te , b its are in the ma in (core) po wer we ll.
Bits not explicitly defined in each register are assumed to be reserv ed. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
8.8.1 Powe r Manageme nt PCI Configuratio n Registers
(D31:F0)
Table 271 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 271. Power Management PCI Configuration Registers (D31:F0)
Offset M nemo nic Register Name/Fun ctio n Def ault Type
40h -43h ACPI_ BASE ACP I Base Addre ss 00000001
hR/W
44h ACPI_CNTL ACPI Control 00h R/W
A0h GEN_PMCON_1 General Power Management
Config uration 1 0000h R/W
A2h GEN_PMCON_2 General Power Management
Config uration 2 00h R/W
A4h GEN_PMCON_3 General Power Management
Config uration 3 00h R/W
A8h Reserved 0Dh R/W
B8 - BBh GPI_ROUT GPI Ro ute Control 00000000
hR/W
C0h MON_FWD_EN I/O Monitor Forward Enable 00h RW
C4 - CA hh MON[n]_TRP_RNG I/O Monitor[4:7] Trap Range 0000h R/W
CCh MON_TRP_MSK I/O Monitor T rap Range Mask 0000h R/W
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 385
8—Intel® 6300ESB ICH
8.8.1.1 Offset A0h: GEN_PMCON_1—General PM Configuration 1
Register
(PM—D31:F0)
Note: Usage: ACPI or Legacy.
Table 272. Offset A0h: GEN_PM CON_1—General PM C onfiguration 1 Register
(PM—D31:F0)
Bits Name Description Access
15:1
1Reserved Reserved.
10 Reserved Reserved.
9PWRBTN_LVL
This read-only bit indicates the current state of the PWRBTN#
sig nal.
0 = Lo w.
1 = Hig h.
RO
8:6 Reserved Reserved.
5CPUSL P_EN : CPU SL P#
Enable
0 = D isa b le .
1 = Enables the CPUSLP# signal to go active in the S1-D
states. This reduces the process or power.
Note that CPUSLP# will go active on entry to S3, S4 and S 5
even when this bit is not se t.
R/W
4SMI_LOCK
When this b it is se t, writes to the G LB_ S MI_E N b it will ha ve
no effec t Once the SMI_LOCK bit is set, writes of 0 to
SMI_LO CK bi t will ha ve no eff ect (i.e . on ce set, this bit ma y
only be cleared by PXPCIRST#).
R/WO
3:2 Reserved Reserved.
1:0 PER_SMI_SEL: Periodic
SMI# rate Select
Set by software to control the rat e at which per iodic SMI# is
generated.
00 = 64 second s
01 = 32 second s
10 = 16 second s
11 = 8 second s
R/W
Device: 31 Function: 0
Offset: A0h Attribute: Read/Write
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
386 Order Number: 300641-004US
8.8.1.2 Offset A2h: GEN_PMCON_2—General PM Configuration 2
Register
(PM—D31:F0)
Note: Usage: ACPI or Legacy.
Table 273. Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Bits Name Description Access
7:5 Reserved Reserved.
4System Reset Status
(SRS)
The I n t el® 6 300ES B ICH sets this bit when the SYS_RESET#
button is pre ssed . B IOS is expec te d to read this bit a nd clear
it when it is se t. T h is b it is a lso r ese t by RS M RST# and CF9h
resets. SRS b it is set only when the system is in S0 or S1
state.
R/WC
3CPU Th e rma l Trip St at us
(CTS)
This bit is set wh e n PXP CIRS T# is ina ctiv e and
CPUTHR MTRIP# goes active while the sy ste m is in an S0 or
S1 state. T his bit is also reset by RSMRST# and CF9h resets.
It is not reset by the shutd own and reboot associated with the
CPUTHRMTRIP# event.
R/WC
2 Reserved Reserved.
1CPUP W R_FLR: CPU
Power Failure
0 = Software clears this bit by wr iting a 0 to th e bit position.
1 = Indicates that the PWRGD signal from the CPU’s VRM
went low.
Software clears this bit by writing a 0 to this bit p osition.
R/WC
0PWROK_FLR: PWROK
Failure
0 = Software clears this bit by wr iting a 1 to th e bit position,
or when the sy stem goes into a G3 state.
1 = This bit wil l be set any tim e PWR OK go es low, when the
system was in S0, or S1 state . The bit will be cleare d only
by software by writing a 1 to this bit or when the system
goes to a G3 state.
NOTE: Tradi tion a l d e sig n s h ave a re set button log ica lly OR’d
wit h t he PWROK s i gnal fro m the power supply an d t h e
CPU’s voltage re gu la tor module. When th is is do n e
with the Intel® 6300ESB ICH, the PWROK_FLR bit will
be set. The Intel® 6300ESB ICH treats this in te rnally
as though the RS MRS T# s ign al had gone a ctive .
However, it is not treated as a full power failure. When
PWROK goes inactive and then active (but RSMRST#
stay s h igh), the I n tel® 6300ESB ICH will reboot
(regardless of the state of the AFTERG3 bit). When
the RSMRST# signal also goes low before PWROK
goes hig h , this is a f ull power failure a nd th e reboot
policy is controlled by th e A FTERG3 bit.
NOTE: In the cas e of true PWROK fa ilure , PW ROK will go low
first befor e PWRGD.
R/WC
Device: 31 Function: 0
Offset: A2h Attribute: Read-O nly Cl ear
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 387
8—Intel® 6300ESB ICH
8.8.1.3 Offset A4h: GEN_PMCON_3—General PM Configuration 3
Register (PM—D31:F0)
Note: Usage: ACPI or Legacy.
Table 274. Offset A4h: GEN_PM CON_3—General PM C onfiguration 3 Register
(PM—D31:F0)
Bits Name Description Access
7:6 SWSMI_RATE_SEL
This 2-bit value i ndicates when the SWSMI ti mer will time out.
Valid values are:
00 1.5 ms ± 0.5 ms
01 16 ms ± 4 ms
10 32 ms ± 4 ms
11 64 ms ± 4 ms
R/W
5:3 Reserved Reserved.
2RTC_PW R_S TS: RTC
Power Status Th is bit is set when RTCRST# is low. The bit is not clea re d by
any type of reset. R/W
1PWR_FLR: Power Failure
This b it is in the RTC well, and is not cle a re d by a ny type of
reset e xc e pt RTCR S T#.
0 = Indicates that the trick le current has not failed since the
last tim e th e bit was clear e d. S of tw a re cle a rs t h is b it by
writing a 1 to the bit po sition.
1 = Ind icate s tha t the tr ick le curre nt (f rom the main ba ttery
or trickle supply) was removed or failed.
NOTE: Clearing CMOS in a processor-based platform may be
done by using a jumper on RTCRST# or GPI, o r using
SAFEMODE strap. Implementations should not
attem pt to clea r CMOS by using a jumper to pull
VccRTC low.
R/WC
0 AFTERG3_EN
Dete rmine s w ha t state to g o to whe n po we r is re -applied
after a power failure (G3 state). This bit is in the RT C well and
is not cleare d by any ty pe of reset exc ept wri tes to CF9h or
RTCRST#.
0 = System w ill re turn to S0 state (boot) after power is re-
applied.
1 = System will return to the S5 state (except when it was in
S4, in which case it will return to S4). In the S5 state, the
only enabled wake event is the Pow er Button or any
enabled wake event that was preserved through the
power f a ilure .
R/W
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period
may not be detected by the Intel® 6300ESB ICH.
Device: 31 Function: 0
Offset: A4h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: RTC
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
388 Order Number: 300641-004US
8.8.1.4 Offset ACh: RS T_CNT2—Reset Control 2 Register (PM—
D31:F0)
Table 275. Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0)
Bits Name Description Access
31:2
4Reserved Reserved.
23 Change Sub Class Code
(CSCC)
When set, the sub class code for the SATA controller will
report the value of “04h”, a RAID device. When cleared, the
sub class code for th e SATA controller will report the value of
“01h”, a n IDE contr olle r. T h is b it is in th e re sume well and is
not reset when re turning from S3 .
22 Change Device ID
(CDID)
When set, the Device ID for the S A T A controller will report the
value of “25B0h”(RAID). When cleared, the Device ID for the
SATA con troller will rep ort the value of “25A 3h ”(hard drive ).
This bit is in th e resume well an d is not re se t whe n re turn ing
from S3.
21:1
9Reserved Reserved.
18 CWORWRE - CF9
Without Resume Well
Re se t Ena bl e
1 = CF9h wri te of 6h or Eh will not cause internal Resume
We ll Reset to be asserte d a nd thu s re su me well logi c will
maintain to their states.
0 = CF9h write of 6h or Eh will reset re sume we ll logic,
R/W
17:1
6
Programmable
CPUTHRMTRIP#
Behavior (PCTB)
This field selects the handling of CPUTHRMTRIP# event by the
Intel® 6300ESB ICH internal logic.
Bits CPUTHRMTRIP# Behavior
00 CPUTHRMTRIP#Event will cause asynchronous assertion of
SLPS3#, SLPS4#, SLPS5# and immediate
tra nsitio n to S5
01 CPUTHRMTRIP#Event will be double-synchronized to
RTCC LKs bef o r e caus ing as s er t ion of
SLPS3#, SLPS4#,SLPS5# and entry to S5
10 CPUTHRMTRIP Event will cause asynchronous assertion of
SLPS3#, SLPS4# and SLPS5#. However ,
internal entry to S5 is delayed until
synchro nization w ith RTCCL K
11 Reserved.
15:0 Reserved Reserved.
Device: 31 Function: 0
Offset: ACh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 389
8—Intel® 6300ESB ICH
8.8.1.5 Offset B8h - BBh: GPI_ROUT—GPI Routing Contr ol
Register
(PM—D31:F0)
Table 276. Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register (PM—
D31:F0)
Bits Name Description Access
31:2 GPI[15] through GPI[1] See bits 1:0 for description.
1: 0 GPI0 Rou te
GPIO[15:0] may be routed to cause an SMI or SCI when the
GPI[n]_STS bit is set. When the G PIO is not set to an inp u t,
this field has no effect.
When the syst em is in an S1-S 5 stat e and if the GPE 0_EN bit
is also set, the GPI may cause a Wake event, even if the GPI
is NOT routed to cause an SMI# or SCI. Exception: If the
syste m is in S5 state due to a powerbutton override, then the
GPIs will not cause wake events,
00 = No effect.
01 = SMI# (when corresponding A LT_G P_S MI _EN b it is also
set)
10 = SCI (when co rrespond ing G PE0_EN b it is also set)
11 = Reserved
R/W
Device: 31 Function: 0
Offset: B8h - BBh Attribute: Read/Write
Defau lt Value: 0000h Size: 32-bit
Lockable: No Power Well: Resume
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
390 Order Number: 300641-004US
8.8.1.6 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable
Register
(PM—D31:F0)
Note: Usage: Legacy Only.
Note: The Intel® 6300ESB ICH uses this register to enable the monitors to forward cycles to
LPC, independent of the POS_DEC_EN bit and the bits that enable the monitor to
generate an SMI#. The only criteria is that the address passes the decoding logic as
determined by the MON[n]_TRP_RNG and MON_TRP_MSK register settings.
8.8.1.7 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O
Monitor [4:7]
Trap Range Register for Devices 4-7 (PM—D3 1:F0)
Note: Usage: Legacy Only.
These registers set the ranges that Device Monitors 4-7 should trap. Offset C4h
corresponds to Monitor 4. Offset C6h corresponds to Monitor 5, etc.
When the trap is enabled in t he MON_SMI register and the address is in the trap range
(and passes the mask set in the MON_TRP_MSK register) the Intel® 6300ESB ICH will
generate an SMI#. This SMI# occurs when the address is positively decoded by
anot he r d evi ce on PC I or by the Intel® 6300 ESB IC H (b ecau se i t wo uld be for wa rde d to
LPC or some other Intel® 6300ESB ICH internal registers). The trap ranges should not
point to registers in the Intel® 6300ESB IC H’s i nternal IDE, USB, A C’97. When th e cycle
is to be claimed by the Intel® 6300ESB ICH and targets one of the permitted Intel®
6 300ESB ICH internal registers (interrupt controller, RTC, etc.), the cycle will complete
Table 277. Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register (PM—
D31:F0)
Bits Name Description Access
7 MON7_FWD_EN
0 = Disable. Cycles trapped by I/O Monitor 7 will not be
forwarded to LPC.
1 = Enab le. Cycles trapped by I/O Monitor 7 will be forwarded
to LPC.
R/W
6 MON6_FWD_EN
0 = Disable. Cycles trapped by I/O Monitor 6 will not be
forwarded to LPC.
1 = Enab le. Cycles trapped by I/O Monitor 6 will be forwarded
to LPC.
R/W
5 MON5_FWD_EN
0 = Disable. Cycles trapped by I/O Monitor 5 will not be
forwarded to LPC.
1 = Enab le. Cycles trapped by I/O Monitor 5 will be forwarded
to LPC.
R/W
4 MON4_FWD_EN
0 = Disable. Cycles trapped by I/O Monitor 4 will not be
forwarded to LPC.
1 = Enab le. Cycles trapped by I/O Monitor 4 will be forwarded
to LPC.
R/W
3:0 Reserved Reserved.
Device: 31 Function: 0
Offset: C0h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 391
8—Intel® 6300ESB ICH
to the intended target and an SMI# will be generated (this is the same functionality as
the Intel® 6300ESB ICH component). When the cycle is to be claimed by the Intel®
6300ESB ICH and the intended target is on LPC, an SMI# will be generated but the
cycle will only be forwarded to the intended target when forwarding to LPC is enabled
through the TRP_FWD_EN register settings.
8.8.1.8 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Rang e Mask
Register
for De vices 4-7 (PM—D31:F0)
Note: Usage: Legacy Only.
Table 278. Off set C4h, C6h, C8h , CAh: MON[n] _TRP_RNG—I/O Monitor [4:7] Trap
Range
Register for Devices 4-7 (PM—D31:F0)
Bits Name Description Access
15:0 MON[n]_TRAP_BASE
Base I/O locations that M ON[n] tra ps (whe re n = 4, 5, 6 or
7). The r an ge may be mapped an ywhere i n the CPU I/O sp ace
(0-64K).
Any access to the rang e will generate an SMI# when enabled
by the associated DEV[n]_TRAP_EN bit in the MON_S M I
register (PMB ASE +40h).
R/W
Table 279. Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register
for Devices 4-7 (PM—D31:F0)
Bits Name Description Access
15:1
2MON7_MASK Sele cts low 4-bit mask f o r the I/O loca tions that MON 7 will
trap. Simi lar to M ON 4_MASK. R/W
11:8 MON6_MASK Selects low 4-b it ma sk for the I/O locations that MON 6 w ill
trap. Simi lar to M ON 4_MASK. R/W
7:4 MON5_MASK Selects low 4-bit mask for th e I/O locations that M ON 5 will
trap. Simi lar to M ON 4_MASK. R/W
3:0 MON4_MASK
Sele cts lo w 4-b it ma sk f or th e I/O locations that M ON 7 will
trap. When a mask b it is set to a 1, the corresponding bit in
the b ase I/O se le ction will not b e decoded.
For example, if MON4_TRAP_BASE = 1230h, and MON4_MSK
= 0100b, the Intel® 6300ESB ICH will decode 1230h and
1234h fo r M onitor 4.
R/W
Device: 31 Function: 0
Offset: C4h, C6h, C8h, CAh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
Offset: CCh Attribute: Read/Write
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
392 Order Number: 300641-004US
8.8. 2 AP M I/O Decode
Table 280 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O locat io n).
8.8.2.1 APM_CNT—Advanced Power Management Control Port
Register
Note: Usage: Legacy Only.
8.8.2.2 APM_STS—Advanced Power Management Status Port
Register
Note: Usage: Legacy Only.
Table 280. APM Register Map
Address Mnemonic Register Name/Function Default Type
B2h APM_CNT Advanced Power Management Contro l
Port 00h R/W
B3h APM_STS Advanced Power Management S tatus
Port 00h R/W
Table 281. APM_CNT—Advanced Power Management Control Port Register
Bits Name Description Access
7:0
Used to pa ss an APM com man d between the OS an d the SMI
hand le r. Writes to this port not onl y st ore data in th e A PM C
register, but also generate s an SMI# when the APMC _EN bit
is set.
Table 282. APM_STS—Advanced Power Management Status Port Register
Bits Name Description Access
7:0 Used to pa ss data between the OS and the SMI hand le r.
Basica lly, this is a scrat chpad re g ist e r a n d is n ot a ffecte d b y
any other register or function (other than a PCI re set).
Device: 31 Function: 0
I/O Address: B2h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: B3h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 393
8—Intel® 6300ESB ICH
8 .8.3 Power M anageme nt I/ O Re gisters
Table 283 shows the registers associated with ACPI and Legacy power management
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and may be moved to any I/O location (128-byte aligned). The registers
are defined to be compliant with the ACPI 1.0 specification, and use the same bit
names.
Note: All re served bits and regist ers will always return zero when read and will have no effect
when written.
Table 283. ACP I and Legacy I/O Registe r Map
PMBASE+
Offset Register Name ACPI Pointer Default Attributes
00-01h PM1 Status PM 1a_EV T_BL K 0000h R/W
02-03h PM1 Enab le PM 1a_EVT_BLK +2 0000h R/W
04-07h PM1 Control PM1 a_CNT_BLK 0000000 0h R/W
08-0Bh PM1 Time r PMTM R_B LK 00000000h RO
10h -13h Processor Control P_BLK 00000000h R/W
14h Level 2 Reg i ster P_BLK +4 00h RO
28-2Bh General Purpose Event 0
Status GPE0_BLK 00000000h R/W
2C-2Fh General Purpose Event 0
Enables GPE0_BLK+4 00000000h R/W
30-33h SM I# Control and Enable 0000000 0h R/W
34-37h SM I Sta tus Register 0000000 0h R/W
38-39h Alte rnate G PI SMI Enable 0000h R/W
3A-3Bh Alternate GPI SMI Status 0000h R/WC
40h Device Monitor SMI Status
and Enable 0000h R/W
44h De vice Activity Status 0000h R/W
48h De vice Trap Enable Register 0000h R/W
4Ch-4Dh Bus Address Tracker Last Cycle RO
4Eh Bus Cycle Tracker Last Cycle RO
60h-7F h Rese rved f or TC O R e gist e rs
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
394 Order Number: 300641-004US
8.8.3.1 PM1_STS— Power Mana gement 1 Status Register
Note: Usage: ACPI or Legacy
Note: When bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the
PM1_EN register, the Intel® 6300E SB ICH will gene r ate a W a ke Event. O nce back in an
S0 state (or if already in an S0 state when the event occurs), the Intel® 6300ESB ICH
will also generate an SCI when the SCI_EN bit is set, or an SMI# when the SCI_EN bit
is not set.
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
may cause an SMI# or SCI.
Tab le 284 . PM 1_ ST S— P ow e r Ma nag e m ent 1 Sta t us Re g is ter (Sh e et 1 of 2)
Bits Name Description Access
15 WAK_STS: Wake Status
This bit is not affected by hard resets c aused by a CF9 write,
but is reset by RS M RS T#.
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Set by hardware when the sy stem is in one o f the sleep
states (through the SLP_EN bit) and an enabled wake
event occu rs. Upon setting th is bit, the Inte l® 6300ESB
ICH will transition the system to th e ON sta te .
When the AFTERG3_EN bit is not set and a power failure
(such as removed b atte rie s) oc curs without the S LP_EN bit
set, the system will re turn to an S 0 sta te whe n p owe r
returns, and the WAK_STS b it will not be set.
When the AF T ERG 3_ EN bit is set an d a power fai l ure occurs
witho ut th e SLP_E N bit having bee n se t, th e sy ste m will go
into an S5 s tate w hen power retu rns, and a subseq uent wake
event will c au se the WAK_ST S bit to b e set. No te tha t any
subsequent wake event would have to be c aused by either a
Power Button press, or an enabled wake event that was
preserved through the power failure (enable bit in the RTC
well).
R/WC
14:1
2Reserved Reserved.
11 PRBTNOR_STS: Power
Button Ove rrid e St atus
This bit is set any time a Power Butt on Override occurs (I.E.
the pow er button is pressed for at least four consecutive
seconds), or d u e to the corresp onding bi t i n th e SM B u s sla v e
message. The power button override cause s an unconditional
tran sition to t he S5 state, as well as sets the AFTERG3 bit.
The BIOS or SC I ha ndl er clea rs this bit by writing a 1 t o it.
This bit is not affe cted by hard re sets thr oug h CF9h writes,
and is not reset by RSMRST#. Thus, t his bit is preserved
through power failure s.
R/WC
Device: 31 Function: 0
I/O Address: PM BASE + 00h
(ACPI PM1a_EVT_BLK) Attribute: Re ad/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Bits 0-7: Core;
Bits 8-10, 12-15;Resume;
Bit 11: RTC
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 395
8—Intel® 6300ESB ICH
10 RTC_STS: RTC Status
This bit is not affec ted by har d resets caused by a CF9 write,
but is reset b y RSMRS T #.
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = Set by hardware when the RTC generates an alarm
(asse rtion of the IRQ8# signal). Additionally whe n the
RTC_EN bit is se t, th e se tting of the RTC_STS bit will
generate a wake eve nt.
R/WC
9 Reserved Reserved.
8PWRBTN__STS: Power
Button Status
This bit is not affec ted by har d resets caused by a CF9 write.
0 = When the PWRBTN# signal is held low for more than four
second s, the ha rd ware clears the PW RBTN_ST S bit, sets
the PWRBTNOR_S TS bit, and the sy stem transitions to
the S5 state with only PWRBTN# enabled as a wake
event. This bit may be cleared by software by writing a
one to the bit pos ition.
1 = Th is bit is set when th e P W R BTN# signal is as se rted
(low), independent of any other enable bit. See
PWRB T N _EN for the effect when PWRBTN_ST S goes
active. PWRBTN_STS is always a wake event. This bit is
only set by hardware and can be cleared by software
writing a one to this bit pos ition. This bit is not affec te d
by hard resets caused by a CF9 write, but is reset by
RSMRST#.
R/WC
7:6 Reserved Reserved.
5GBL _STS: Global Status
0 = The S CI h an d le r should then cl ear th is b it by writing a 1
to the bit location.
1 = Set when an SCI is generate d due to BIOS wanti n g the
attention of the SCI handler. BIOS has a correspond ing
bit, BIOS _RLS, which will cause an SCI and set th is b it.
R/WC
4:1 Reserved Reserved.
0TMROF_STS: Timer
Overflow Status
0 = The S CI or S M I# ha nd le r cle a rs th is b it by writing a 1 to
the bit location.
1 = Thi s bit gets set any time b it 22 of th e 24 -bi t timer g oe s
high (bits are numbered from 0 to 23). This will occur
every 2.3435 seconds. When the TMROF_EN bit is set,
then the setting of th e TMROF_STS bit will add itionally
generate an SCI or SMI# (depending on the SCI_EN).
R/WC
Table 284. PM1_STS—Power Management 1 Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 00h
(ACPI PM1a_EVT_BLK) Attribute: Read/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Bits 0-7: Core;
Bits 8-10, 12-15;Resume;
Bit 11: RTC
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
396 Order Number: 300641-004US
8.8.3.2 PM1_EN—Power Management 1 Enable Register
Note: Usage: ACPI or Legacy.
Table 285. PM1_EN—Power Management 1 Enable Register
Bits Name Description Access
15:1
1Reserved Reserved.
10 RTC_EN : RTC Even t
Enable
This bit is in the RTC well to allow an RTC event to wake after
a power failure. This bit is not cleared by any reset other than
RTCRST# or a Power Button Override eve nt.
0 = No SCI (o r SMI# ) or wa ke event is ge nerated the n
RTC_STS goes active.
1 = An SCI (or SMI#) and a wake even t will occur when this
bit is set and the RTC_STS bit goes activ e .
R/W
9 Reserved Reserved.
8PWRBTN_EN
This bit is the power button enable. It works in conjunction
with the SCI_EN b it:
PWRBTN_EN SCI_EN Eff ect whe n PWRBTN_STS is set
0 x No SMI# or SCI
10SMI#
11SCI
PWRBTN_EN has no effect on the PWRBTN_STS bit being set
by the assert ion of th e power button. The Pow er Button is
always enabled as a Wake event.
7:6 Reserved Reserved.
5 GBL_EN: Global Enable
When both the GBL_ EN and the GBL_S TS are set, an SC I is
raised.
Disable.
En abl e SCI o n GBL_ST S going active .
R/W
4:1 Reserved Reserved.
0TMROF_ E N. Ti m e r
Overf low Interrupt
Enable
Work s in conjunc tion with the SC I_EN bit as describ ed bel ow:
TMROF_EN SCI_EN Effect when TMROF_STS is set
0 x N o SMI# or SC. If sy stem was in S1-
S5, no wake event
1 0 SMI# If system was in S1-S5, then a
wake vent occurs before th e SMI#
1 1 SCI I f system wa s in S1-S5, t h e n a
wake vent occurs before th e SMI#
R/W
Device: 31 Function: 0
I/O Address: PM BASE + 02h
(ACPI PM1a_EVT_BLK +
2) Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Bits 0-7: Core
Bits 8-9, 11-15: Resume
Bit 10: RTC
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 397
8—Intel® 6300ESB ICH
8.8.3.3 PM1_CNT—Power Management 1 Control
Note: Usage: ACPI or Legacy.
Table 286. PM1_CNT—Power Management 1 Control
Bits Name Description Access
31:1
4Reserved Reserved.
13 SLP_EN: S leep Enable Setti ng t his bit caus es the sy stem to se quenc e int o the Sleep
state defined by the SLP_TYP field. WO
12:1
0SLP_TY P: S leep Ty p e
This 3-bit field defines the type of Sleep the system should
enter whe n the S LP_EN b it is set to 1.
00 0 = ON: Ty p i ca lly ma ps t o S 0 st a t e .
001 = Asserts STPCLK#. Puts CPU in Stop-Grant state.
Optional to assert CP US LP# to put CPU in sleep s ta te :
Typic al ly maps to S1 state.
010 = Reserved
011 = Reserved
100 = Reserved
101 = Suspend-To-RAM . Asser t SLP_S1 # and SLP_S3 # :
Typic al ly maps to S3 state.
110 = Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and
SLP_S4#: Typically maps to S4 state.
111 = Soft Off. Assert SLP_S 1#, SLP_ S3 #, SLP_S4 # , and
SLP_S5#: Typically maps to S5 state.
NOTE: These bits are only reset by RTC R ST #.
R/W
9:3 Reserved Reserved.
2GBL_RLS: Global
Release
0 = This bit always reads as 0.
1 = ACPI sof tware writes a 1 to this bit to raise an event to
the BI OS. BIOS software has a corresponding enab le and
stat u s bi ts to control its ability to re ce iv e ACPI events.
WO
1 Reserved Reserved.
0SCI_EN: SCI Enable
Sele cts the SCI interrupt or the SMI# interrupt for various
events including the bit s in the PM1_STS regi ster (bit 10, 8,
0), and b its in GPE0_S TS.
0 = These events will ge n e rate an SM I#.
1 = These events will ge n e rate an SCI.
R/W
Device: 31 Function: 0
I/O Address: PMBASE + 04h
(ACPI PM1a_CNT_BLK) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Bits 0-7: Core,
Bits 8-12: R T C
Bits 13-15: R esume
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
398 Order Number: 300641-004US
8.8.3.4 PM1_TMR—Power Management 1 Timer Register
Note: Usage: ACPI only.
8.8.3.5 PROC_CNT—Processor Control Register
Note: Usage: ACPI or Legacy.
Table 287. PM1_TMR—Power Management 1 Timer Register
Bits Name Description Access
31:2
4Reserved Reserved.
23:0 TMR_VAL: Time r Value
Returns the running count of the PM timer. This counte r runs
off a 3.579545 MH z clock (14.31818 MHz divide d by 4). It is
reset to zero during a PCI reset, and then continues counting
as long as t he system is i n th e S0 sta te.
Anytime bit 22 of the time r g oe s HIG H to LOW (b its
referen ce d from 0 to 23), the TMROF_STS bit is set. The
High-to-Low transition will occur every 2.3435 seconds. When
the TMROF _EN bit is set, a n SC I inte rrup t is also genera te d.
RO
Table 288. PROC_CNT—Processo r Control Register (Sheet 1 of 2)
Bits Name Description Access
31:1
8Reserved Reserved.
17 THTL_STS: Th rott l e
Status
0 = No clock th rottling is occurrin g (m aximum proc e ssor
performance).
1 = Indicates that the clock s tate machine is in some type of
low power state (where the processor is not running at its
maximum perform a nce ): the rmal throttling or hard wa re
throttling.
RO
16:9 Reserved Reserved.
8FORCE_THTL: Force
Ther mal Thro tt l i n g
Softwa re may set this bit to forc e the thermal throttling
function. This has the same effect as the THRM# signal being
activ e for 2 seco nds.
0 = No forced throttling.
1 = Throttling at the duty cycle spe cifie d in THRM_DT Y starts
immedia te ly (n o 2 se cond delay) , a nd no S MI# is
generated.
R/W
Device: 31 Function: 0
I/O Address: PM BASE + 08h
(ACPI PMTMR_BLK) Attribute: Read-Only
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: PM BASE + 10h
(ACPI P_BLK) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No (b its 7 :5 are write
once) Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 399
8—Intel® 6300ESB ICH
7:5 THRM_DTY
This write-once 3-bit f ie ld dete rmines the duty cycle of the
throttling whe n the therma l ov er rid e condition occurs. The
duty c ycle indicates the approximate percentage of time the
STPC LK# sig nal is asserted while in the thro ttle mod e . The
STPCLK# th rottle p e riod is 1024 PCICLKs. Note that the
throttling only occurs when the system is in the C 0 state.
When in the C2 state, no throttling occurs.
There is no enable bit for thermal throttling, because it should
not be disa b led. Onc e the THRM _DTY fie ld is writte n, any
subs eque n t writes will have no ef fec t u ntil PX PCIRS T# goes
active.
THR M_ DTY Throttle ModePC I Cloc ks
000 50% Default 512
001 87.5% 896
010 75.0% 768
011 62.5% 640
100 50% 512
101 37.5% 384
110 25% 256
111 12.5% 128
4THTL_EN
When set and the system is in a C0 state, it enables a
proc essor-controlle d STPCLK# throttling . The duty cy cle is
selected in the THTL_DTY field.
0 = D isa b le
1 = Enable
3:1 THTL_DTY
This 3-b it fie ld dete rmines the duty cycle of the throttling
when the THT L_EN bit is set. The du ty cycle indicate s the
approximate percentage o f time the STPCLK# signal is
asse rte d (low) while in the throttle mod e . The S TPCL K#
throttle period is 1024 PCICLKs.
THR M_ DTY Throttle ModePC I Cloc ks
000 50% Default 512
001 87.5% 896
010 75.0% 768
011 62.5% 640
100 50% 512
101 37.5% 384
110 25% 256
111 12.5% 128
0 Reserved Reserved.
Table 288. PROC_CNT—Processor Control Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 10h
(ACPI P_BLK) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No (b its 7 :5 are write
once) Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
400 Order Number: 300641-004US
8.8.3.6 LV2—Level 2 Register
Note: Usage: ACPI or Legacy.
8.8.3.7 GPE0_STS—General Purpose Event 0 Status Register
Note: This register is symmetrical to the General Purpose Event 0 Enable Register. When the
corresponding _EN bit is set, and the _STS bit get set, the Intel® 6300ESB ICH will
ge ne r a te a Wake Ev e nt. Once b ac k in an S0 s tat e ( or i f al rea d y in an S0 s t at e w he n t h e
event occurs), the Intel® 6300ESB ICH will also generate an SCI when the SCI_EN bit
is set, or an SMI# when the SCI_EN bit is not set. There will be no SCI/SMI# or wake
event on THRMOR_STS since there is no corresponding _EN bit. None of these bits are
reset by CF9h write. All are reset by RSMRST#.
Note: Usage: ACPI.
Table 289. LV2—Level 2 Regi ster
Bits Name Description Access
7:0
Reads to this register return all ze ros, writes to th is re g iste r
have no effect. Reads to this register generate a “enter a level
2 power sta te ” (C2) to the cloc k co n trol log ic. This will cau se
the STPCLK# signal to go active, and stay active until a break
event occurs. Throttling (due either to THTL_EN or THRM#
override) will be ignored.
RO
Device: 31 Function: 0
I/O Address: PM BASE + 14h
(ACPI P_BLK + 4) Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 401
8—Intel® 6300ESB ICH
Table 290. GPE0_STSGeneral Purpose Event 0 Status Register (Sheet 1 of 3)
Bits Name Description Access
31:1
6GPIn_STS
These bits are set any time the corresponding GPIO is set up
as a n i npu t an d th e c orr es pon di ng GP IO s i gna l i s hi gh ( o r lo w
when the cor re spond ing GP _IN V bit is set) . Wh en the
co rre sp on d in g e n a b le bit is set in the GPE0_EN register, then
the GPI[n]_S TS b it is set:
When the system is in an S1- S 5 state, the event will also
wake th e system .
When the sy stem is in an S0 state (or upon waking back
to an S0 state), a SCI will be caused depending on the
GPI_ROUT bi ts for the corresponding GPI.
NOTE: T hese bits are sticky and are cleared by wr iting a 1
back to this b it p ositi on.
Corresponding bits and GPIOs
Bit # GPI[n]Bit # GPI [n]
16 0 24 8
17 1 25 na
18 2 26 na
19 3 27 11
20 4 28 12
21 5 29 13
22 6 30 na
23 7 31 na
R/WC
15:1
4Reserved Reserved.
13 PME_B0_STS
This bi t will be se t to 1 by the Intel ® 6300ES B ICH whe n any
internal dev i ce on bus 0 asserts the equ ivalent of the PME#
signal . Add itionally, when the PME_B 0_EN bit is set, and the
system is in an S0 state, the setting of the PME_B0_STS bit
will generate an SCI (or SMI# when SCI_EN is not set). When
the PME_B0_S TS bit is set, and the system is in an S1-S4
state (or S5 stat e due to S LP_TYP and SL P_EN), the settin g of
the PME_B 0_S TS bit will generate a wake event, and a n SCI
(or SMI# when SCI_E N is not se t) will b e gene ra te d. When
the system is in an S5 state due to power button override,
the PME_B 0_S TS bit will not cause a wake eve nt or S CI.
The defa ult fo r this bit is 0. Writin g a 1 to this bit posi tion
clear s this bit.
R/WC
12 Reserved Reserved.
Device: 31 Function: 0
I/O Address: PMBASE + 28h
(ACPI PGPE0_BL K) Attribute: Read/Write Clear
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Resume
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
402 Order Number: 300641-004US
11 PME_STS
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Set by hardware when the PME# signal goes active.
Addition a lly, w hen the PME_ EN bit is set and the syste m
is in an S0 state, then the setting of the PME_STS bit will
generate an SCI or SMI# (when SCI_EN is not set).
When the PME_EN bit is set and the sy stem is in an S1-
S4 state (or S5 state du e to setting SLP_TYP and
SLP_EN), then the se tting of the PM E_S TS bit will
generat e a wake event, and an SCI (or SMI# if SMI_EN is
not set) will be generated. When the system is in an S5
state d ue to power button overrid e , PM E_S TS will not
cause a wake event or SCI.
R/WC
10:9 Reserved Reserved.
8RI_STS
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Set by hardware when the RI# input signal goes active. R/WC
7SMBus Wake Status
(SMB_WAK_STS)
The S M B u s controller may inde pendently ca use an SMI # or
SCI, so this bit d oe s not need to do so (unlike the other bits in
this regist er ).
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Set by har dware to ind icate that the wake event was
caused by the Intel ® 6300ESB ICH s SMBus logic.This bit
will be set by the WAKE/SMI# command type, even when
the system is already awake. The SMI handler should
then clear this bit.
NOTE: This bit is set by the SMBus slave command 01h
(Wake/SMI#) even when the system is in the S0
state. Therefore, to avoid an instant wake on
subse quent t ra nsit ions to sle e p states, softwa re mu st
clear this bit afte r e ach re ce p tion of the Wa ke/SM I#
command or just prior to entering the sleep state.
NOTE: When SMB_ WAK_STS is set du e to SMBus s lave
receiving a message, it will be cleared by internal logic
when a T HRMTR IP# e vent happens or a Power Button
Override event. However, THRMTRIP# or Power
Button Ov er rid e eve nt will not cle a r SMB_WAK_STS
when it is se t d u e to SMBALERT# signa l go in g ac tive.
R/WC
6 TCOSCI_STS 0 = Softwar e c lea rs this bit by wr iting a 1 to th e bit position.
1 = Set by hardware when the TCO logic causes an SCI. R/WC
Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PM BASE + 28h
(ACPI PGPE0_BL K) Attribute: Re ad/Write Clear
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 403
8—Intel® 6300ESB ICH
5 AC97_STS
This bit will be set to 1 by whe n the codecs are attempting to
wake the system and the PME events for the codecs are
armed for wakeup. A PME is armed by programming the
appropriate PMEE bit in the Power Management Control and
Status regis ter at bit 8 of offs e t 54h in each AC ’97 f unction.
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = Set by hardwar e when the c odecs are attemp ti ng to w ake
the system. The AC 97_S TS b it gets se t only from the
following two cases:
1. The PMEE bit for the function is set, and the AC-link bit
clock ha s been shut and the routed AC_SDIN line is high
(for audio, when routing is disabled, no wake events are
allowed).
2. For modem, when audio routing is disabled, the wake
event is an OR of a ll A C_S DIN lines. Wh en routin g is
enabled, the wake event for modem is the r emaining
non-route d AC_SDIN line), or o GP I S tatus Change
Interrupt bit (NABMBAR + 30h, bit 0) is 1.
This bit is not af fected by a hard reset caused by a CF9h
write.
R/WC
4 USB2_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = S e t by ha rd ware wh e n US B U HCI Controller 2 needs to
caus e a wake. Wake eve nt will b e ge ne rat ed whe n th e
corresponding USB2_EN bit is set.
R/WC
3 USB1_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = S e t by ha rd ware wh e n US B U HCI Controller 1 needs to
caus e a wake. Wake eve nt will b e ge ne rat ed whe n th e
corresponding USB1_EN bit is set.
R/WC
2 Reserved Reserved.
1Thermal Interrupt
Override Status
(THRMOR_STS)
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = This bi t is set by hardware anytime a thermal over-ride
con dition occurs a n d sta rts throttling the processor’s
clock at the THRM_DTY ratio. This wi ll not cause an
SMI#, SCI, or wake event.
R/WC
0Thermal Interrupt
Status (THRM_STS)
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = Set by hardware anytime the THRM# signal is driven
active as defined by the THRM_POL bit. Additi onally,
when the THRM_EN bit is set, the setting of the
THRM_STS bit will also generate a power management
event (SCI or SMI#).
R/WC
Table 290. GPE0_STSGeneral Purpose Event 0 Status Register (Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 28h
(ACPI PGPE0_BL K) Attribute: Read/Write Clear
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Resume
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
404 Order Number: 300641-004US
8.8.3.8 GPE0_EN—General Purpose Event 0 Enables Register
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override. The resume
well bits are all cleared by RSMRST#. The RTC well bits are cleared by RTCRST#.
Note: Usage: ACPI.
Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 1 of 2)
Bits Name Description Access
31:1
6GPIn_EN These bits enable the corresponding GPI[n]_STS bits being
set t o cau se a SCI, and/o r wake event. These bits are cl eared
by RSMRS T #. R/W
15:1
4Reserved Reserved.
13 PME_B0_EN
Enables the setting of the PME_B0_STS bit to generate a
wake event and/or an SC I or SMI#. PME_B0_STS may be a
wake event from the S1-S4 states, or from S5 (when entered
through SLP_TYP and SLP_EN ) or powe r failure, but not
Power Button Override. This bit defaults t o 0. It is only
cleared by Software or RTCRST#. It is not cle a re d by CF9h
writes.
R/W
12 Reserved Reserved.
11 PME_EN
This bit defaults to 0. It is only cleared by Software or
RTCRST# . It is not clea red by CF9h write s.
0 = Disabl e.
1 = Enables the se tting of the PME_STS to generate a wake
event and/ or an SCI. PME# may be a wake event from
the S1 - S4 state or from S5 (when entered through
SLP_EN or power failure, but not power button override).
R/W
10 Reserved Reserved.
9 Reserved Reserved.
8RI_EN
The value of t his b it will b e ma inta ine d through a G 3 sta te
and is not affected by a hard reset caused by a CF9h write.
0 = Disabl e.
1 = Enabl es the se tting of the RI_STS to g e ne rate a wake
event.
R/W
7 Reserved Reserved.
6TCOSCI_EN
0 = Disabl e.
1 = Enables the se tting of the TCOSCI_ STS to generate an
SCI. R/W
5AC97_EN
0 = Disabl e.
1 = Enabl es the setting of the AC97_STS to generate a wake
event. R/W
Device: 31 Function: 0
I/O Address: PM BASE + 2Ch
(ACPI GPE0_ BLK + 4) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Bits 0 -7, 12, 16-31 Resum e,
Bits 8-11, 13 RTC
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 405
8—Intel® 6300ESB ICH
8.8.3.9 SMI_EN—SMI Control and Enable Register
Note: Usage: ACPI or Legacy
4USB2_EN
0 = D isa b le .
1 = Enab le the setting of the USB 2_S TS bit to generate a
wake event. The U SB2_STS bit is set anytime USB UHCI
Controller #2 signals a wa ke event. Break events are
handled through the USB interrupt.
R/W
3USB1_EN
0 = D isa b le .
1 = Enab le the setting of the USB 1_S TS bit to generate a
wake event. The U SB1_STS bit is set anytime USB UHCI
Controller #1 signals a wa ke event. Break events are
handled through the USB interrupt.
R/W
2THRM#_POL
This bit controls the polarity of th e THRM # p in nee ded to set
the THRM_S TS bit.
0 = Lo w value on th e THRM # signal will se t the THRM _STS
bit.
1 = HIGH value o n the THRM# signal will set the THRM_STS
bit.
R/W
1 Reserved Reserved.
0THRM_EN
0 = D isa b le .
1 = Active as se rt ion of the TH RM# sig n a l (a s d efine d by the
THRM_POL bit) will set the THRM_STS bit and generate a
power mana gem ent eve nt (SCI or SMI ).
R/W
Table 292. SMI_EN—SMI Control and Enable Register (Sheet 1 of 3)
Bits Name Description Access
31:1
9Reserved Reserved.
18 INTE L_U SB2_EN Ena b le s Inte l-S p ecific USB EHCI S M I logi c to cau se SMI#.
17 LEGACY _USB 2_EN Enables le g acy US B EHCI log ic to cause SMI#.
16:1
5Reserved Reserved.
Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 2Ch
(ACPI GPE0_ BLK + 4) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Bits 0-7, 12, 16-31 Resume,
Bits 8-11, 13 RTC
Device: 31 Function: 0
I/O Address: PMBASE + 30h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
406 Order Number: 300641-004US
14 PERIODIC_EN
0 = Disabl e.
1 = Enables the Intel® 6300ESB ICH to g e ne rate an SMI#
when the PERIOD IC_S TS bi t is set in the SMI_ STS
register.
R/W
13 TCO_EN
0 = Disabl es TCO logic g ene rating an S MI#. N ote tha t when
the NMI2SMI_EN bit is set, S MIs that are caused b y re-
routed NMIs will not be gated by the TCO_EN b it. E ven
when the TCO_EN bit is 0, NM Is will still be rou te d to
cause SMIs.
1 = Enabl es the TCO logic to generate SM I#.
NOTE: This bit can not be written once the TCO_LOCK bit (at
offset 08h of TCO I/O Space) is set. This prevents
unauthor ized softwa re from disabling the genera tion
of T C O-bas ed SMI s
R/W
12 Reserved Reserved.
11 M CS MI_EN : M icrocon-
trolle r SMI Ena b le
0 = Disabl e.
1 = Enables the Intel® 6300ESB ICH to trap a ccess e s to the
microcontroller rang e (62h or 66h) a nd gene rate a n
SMI#. Note th at “tra pped cycle s will b e claime d by the
Intel® 6300ESB ICH on PCI, but not forwarded to LPC.
R/W
10:8 Reserved Reserved.
7BIOS_R LS : BIOS
Release
0 = This bit will always return 0 on reads. Writes of 0 to this
bit have no effect.
1 = Enabl es the gene ration of an SCI interrupt for ACPI
software when a one is written to this bit position by
BIOS softw are .
WO
6SWSMI_TMR_EN:
Softw are SMI# Timer
Enable
0 = Disabl e. Clea ring the SWSMI_TMR_EN bit before the
timer ex pir e s will re se t th e timer and the S M I# will not
be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer
expires (the timeout period depends upon the
SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set
and an SMI# is generated. SWSMI_TMR_EN stays set
until clea re d by sof twa re.
R/W
5APMC_EN
0 = Disable. Writes to the APM_CNT register will not cause an
SMI#.
1 = Enabl es write s to th e APM_CN T re g iste r to caus e an
SMI#.
R/W
4 SLP_SMI_EN
0 = Disabl es the genera tion of SMI# on SLP_EN . N ote tha t
this bit must be 0 before the sof tware a tte mpts to
trans ition the system into a sleep state by writing a 1 to
the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CN T
register) will gene rate an SMI#, a nd the sy stem will not
trans ition to the sl eep state b ase d on tha t write to the
SL P_EN bit.
R/W
3 LEGACY_USB_EN 0 = Disable.
1 = E nables le gac y U SB c i rc u it to caus e S MI#. R/W
Table 292. SMI_EN—SMI Control and Enable Register (Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PM BASE + 30h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 407
8—Intel® 6300ESB ICH
8.8.3.10 SMI_STS—SMI Status Register
Note: When the corresponding _EN bit is set when the _STS bit is set, the Intel® 6300ESB
ICH will cause an SMI# (except bits 8-10 and 12, which do not need enable bits since
they are logically ORed with other registers that have enable bits). The Intel® 6300ESB
ICH uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/disable
both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns
the entire GPE0_EN register per ACPI spec. Problems arise when some of the general-
purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs
are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input
signals that are not indicated as SCI general-purpose events at boot, and exit from
sleeping states. BIOS should define a dummy control method which prevents the ACPI
OS from clearing the SMI GPE0_EN bits.
Note: Usage: ACPI or Legacy.
2BIOS_EN
0 = D isa b le .
1 = Enables the generation of SMI# when ACPI software
writes a 1 to th e GBL_RLS bit. R/W
1EOS: End of SMI
This bit controls the arbitration of the SMI s ign al to the
proce ssor. This b it must be set for the Intel® 6300ESB ICH to
asse rt S MI# low to the p roce ssor.
0 = Once the Intel® 6300ESB ICH ass erts SMI# low, the EOS
bit is automatically cl eared.
1 = W he n th is b it is se t, SMI# signal will be dea sse rted for 4
PCI clocks before its assertion. In the SMI handler, th e
processor shou ld cle a r all pending SM Is (b y se rvi cing
them and then clearing their respective status bits), set
the EOS bit, and exit SMM. This will allow the SMI arbiter
to re-ass ert SMI upon d e te ction of an S MI event a nd the
settin g of a SMI sta tus bit.
NOTE: The In t e l® 6300ESB ICH is able to gen erate 1st SMI
after reset even though EOS bit is not set. Subsequent
SMI require EOS bit is set.
R/W
(special)
0 GBL_SMI_EN
0 = No S M I# will b e genera te d by the Intel® 6300ES B ICH.
This bit is re set by a PCI re se t event.
1 = Enables the generation of SMI# in the system upon any
enabled SMI event.
R/W
Table 292. SMI_EN—SMI Control and Enable Register (Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 30h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
408 Order Number: 300641-004US
Table 293. SMI_STS—SMI Status Register (Sheet 1 of 2)
Bits Name Description Access
31:2
4Reserved Reserved.
23 WDT_SMI_STS 0 = SMI# not caused by WDT 1st timeout.
1 = Indicates the SMI# was caused by the WDT 1st time out.
22:1
9Reserved Reserved.
18 INTEL_USB2_STS
This non-sticky re ad-only bit is a logi cal OR of each of the SMI
status bits in the Intel-Sp ecific USB EHCI SMI Status Register
ANDed with the corresponding enable bits. This bit will not be
active wh e n th e enab le bit s a re n ot se t. Writes to t his b it will
have no effect.
17 LEGACY_USB2_STS
This non-sticky re ad-only bit is a logi cal OR of each of the SMI
status bits in the U SB EHCI Legacy Support Register ANDed
with the correspond ing enable bits. This bit will not be a ctive
when the enable b its are not se t. Writes to this bit will have
no effect.
16 SMBus SMI Status
(SMBUS_SMI_STS)
0 = Th is bi t is cl eared by writi ng a 1 to it s bit positi on. Thi s bit
is set from the 64 KHz clock domain used by the SMBus.
Softwar e mu st wait a t le ast 15.63 us after the ini tia l
assertion of this b it bef ore cle a ring it.
1 = Indicates that the SMI# was caused by:
1. The SMBus Sl ave receiving a message, o r
2. The SMBALERT# signal goes active and the
SMB_SMI_EN bit is set and the SM BALERT _DIS bit is
cleare d , or
3. The SMBus Slave receiving a Host Notify message and
the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits
are set, or
4. The Intel® 6300ESB ICH detecting the
SMLINK_SLAVE_SMI command while in the S0 state.
R/WC
15 SERIRQ_SMI_STS
0 = SMI# was not caused by SERIRQ decoder. This is not a
stic ky bit.
1 = Indicates that the S M I# was caus ed by the SERIRQ
decoder.
RO
14 PERIODIC_STS
0 = This bit is cleared by writing a 1 to its bit po sition.
1 = This bit wil l be set at the rate dete rmine d by the
PER_SMI_SEL bits. When the PERIODIC_EN bit is also
set, the Intel® 6300ESB ICH w ill genera te a n SMI#.
R/WC
13 TCO_STS 0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note
that this is not a wake event. RO
12 DEVMON_STS: Device
Monitor Status
0 = SMI# not caused by Device Monitor.
1 = Set und e r a ny of the fol lowin g conditions:
- Any of the DEV[7 : 4]_TRA P _STS bi ts are set and the
corresponding DEV[7:4]_TRAP_EN bits are also set.
- Any of the DEVT RA P_S TS bit s are set and the
co r re spond in g DE VT RA P_EN bi t s are also set.
RO
Device: 31 Function: 0
I/O Address: PM BASE + 34h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 409
8—Intel® 6300ESB ICH
11 MCSMI_STS: Microcon-
tro ller SM I# Stat us
0 = Indicates that there has been no access to the power
management microcontroller range (62h or 66h). This bit
is cleared by s oftware writing a 1 t o the bit position.
1 = Set when there has been an access to the power
management microcontroller range (62h or 66h). When
this bit is set, an d the MCS MI_EN b it is also se t, the
Intel® 6300ESB ICH will g e ne rate an SMI#.
R/WC
10 GPE1_STS
This b it is a log ica l OR of the bi ts in the ALT _G P _S M I_S TS
register that are also set up to cause an SM I# (as indicated
by the GPI_ROUT registers) and h ave the corresponding bit
set in the ALT_GP_SMI_EN register. Bits that are not routed
to cause an SMI# will have no effect on this bit.
0 = SM I# was not g e nerated by a GPI as sertion.
1 = SMI# was generated by a GPI assertion.
RO
9 GPE0_STS
This b it is a log ica l OR of the bits in the GPE0 _S TS re gis te r
that also have the corresp onding bit set in the GPE 0_EN
register.
0 = SM I# was not g ene rated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
R/WC
8 PM1_STS_REG
This is an ORs of the bits in the ACPI PM1 St atus Register
(offset PMBASE+00h) that may cause an SMI#.
0 = SM I# was not g ene rated by a PM1_S TS e vent.
1 = SMI# was generated by a PM1_STS event.
R/WC
7 Reserved Reserved.
6 SWSMI_TMR_STS 1 = Set by the hardware when the Software SMI# Timer
expires.
0 = Sof twa re clears this bit by writing a 1 to the bit lo cation. R/WC
5APM_STS
0 = Sof twa re clears this bit by writing a 1 to the bit lo cation.
1 = SMI# was generated by a write access to the APM control
register with the APMC_EN bit set. R/WC
4SLP_SMI_STS
0 = Sof twa re clears this bit by writing a 1 to the bit lo cation.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN
bit when SLP_S MI_EN b it is als o set. R/WC
3 LEGACY_USB_STS
This b it is a log ica l OR of e a ch of th e SMI status bits in the
USB Le g a cy Keyboard/M ouse Con trol Register s ANDed w ith
the corresponding enable bits. This bit will not be active When
the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy even t.
RO
2 BIOS_STS
0 = This bit cleared by software writing a 1 to its bit position.
1 = SMI# was generated due to ACPI software requesting
attentio n (writing a 1 to the GBL _RL S bit with the
BIOS_EN bi t set).
R/WC
1:0 Reserved Reserved.
Tab l e 29 3. S MI _S TS SM I Sta t u s Reg is ter (S he et 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE + 34h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
410 Order Number: 300641-004US
8.8.3.11 ALT_GP_SMI_ EN—Alternate GPI SMI Enable Regi ster
Note: Usage: ACPI or Legacy.
Table 294. ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
Bits Name Description Access
15:0
These bits are used to enable th e corresponding GPIO to
cause an SMI#. In order for these bits to have any effect, the
following must be true.
The corresponding bit in th e ALT _G P_SMI_EN register is
set.
The corresponding GPI must be routed in the GPI_ROUT
register to cause an SMI.
The corresponding GPIO must be implemented.
Device: 31 Function: 0
I/O Address: PM BASE +38 h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 411
8—Intel® 6300ESB ICH
8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register
Note: Usage: ACPI or Legacy.
8.8 . 3.1 3 M ON _S MI D evi c e Mon i to r SMI Statu s an d En ab le R e gi ste r
Note: Usage: Legacy only.
Table 295. ALT_GP_SMI_STS—Alternate GPI SMI Status Register
Bits Name Description Access
15:0
These bits report the status of the corresponding GPIs. 1 =
active, 0 = inactive. These bits are sticky. When the
follow in g cond itions are true, a n SMI# will be g e ne rated an d
the GPE0_S TS b it set:
The cor responding bit in the ALT_GPI_SMI_EN register i s
set.
The cor responding GPI must be routed in the GPI_ROUT
regi ster to cause an SMI .
The cor responding GPIO must be implemented.
All bits a re in th e re sume we ll. Defau lt fo r th e se bits is
dependent on the state of the GPI pins.
Ta ble 29 6 . MO N _ SMI— Dev i ce M on i to r S M I St a t u s an d Ena b l e Re g is t er
Bits Name Description Access
15:1
2DEV[7:4]_TRAP_STS
Bit 12 co rre spond s to M onitor 4, bit 13 co rresp ond s to
Monitor 5 etc.
0 = SMI# wa s n ot cau sed by the a ssociated device mon it or.
1 = SMI# was ca u sed by an a ccess to the corre sp o nding
device monitor’s I/O range.
R/WC
11:8 DEV[7:4]_TRAP_EN
Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5
etc.
0 = D isa b le .
1 = E na bles SM I# d u e to an access to th e corresp onding
device monitor’s I/O range.
R/W
7:0 Reserved Reserved.
Device: 31 Function: 0
I/O Address: PMBASE +3Ah Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Device: 31 Function: 0
I/O Address: PMBASE +40h Attribute: Re ad/Write, Read/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
412 Order Number: 300641-004US
8.8.3.14 DEVACT_STS—Device Ac tivity Status Regist er
Note: This register is used in conjunction with the Periodic SMI# timer to detect any system
activity for legacy power management.
Each bit indicates if the an access has occurred to the corresponding device’s trap
range, or for bits 6:9 if the corresponding PCI interrupt is active. Write 1 to the same
bit position to clear it. This register is used by APM power management software to see
if there has been system activity. The periodic SMI# timer indicates if it is the right
ti me to re a d th e DE V T R AP_ ST S regis t e r.
Note: Usage: Legacy only.
Table 297. DEVACT_STS—Device Ac tivity Status Register (Sheet 1 of 2)
Bits Name Description Access
15:1
4Reserved Reserved.
13 ADLIB_ACT_STS
Ad-Lib.
0 = Indicates t hat there h as been no acces s to this device’s I/
O range.
1 = This device’s I/O range has been acces sed. Clear this bit
by writing a 1 to the bi t location.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/WC
12 KBC_ACT_STS
KBC (60/64 h).
0 = Indicates t hat there h as been no acces s to this device’s I/
O range.
1 = This device’s I/O range has been acces sed. Clear this bit
by writing a 1 to the bi t location.
NOTE: If bit 7 of ETR1 (D31:F0, offset F4h, section 9.1.35) is
set. Port s 60/ 64h acce sses initiated from an e xternal
PCI agen t will not se t this bit.
R/WC
11 MIDI_ACT_STS
MIDI.
0 = Indicates t hat there h as been no acces s to this device’s I/
O range.
1 = This device’s I/O range has been acces sed. Clear this bit
by writing a 1 to the bi t location.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/WC
10 AUDIO_ACT_STS
Audio (Sound Blaster “OR’d” with MSS).
0 = Indicates t hat there h as been no acces s to this device’s I/
O range.
1 = This device’s I/O range has been acces sed. Clear this bit
by writing a 1 to the bi t location.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/WC
9PIRQDH_ACT_STS
PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
1 = At le ast one of the corresponding PCI interrupts has been
active. Cle ar this b it by writing a 1 to the bit locati on.
R/WC
Device: 31 Function: 0
I/O Address: PM BASE +44 h Attribute: Read/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 413
8—Intel® 6300ESB ICH
8 PIRQCG_ACT_STS
PIRQ[C or G ].
0 = The corresp onding PCI inte rr upt s have not been active.
1 = At least one of the c orresponding PCI interrupts has b een
active. Cle ar this bit by wr iting a 1 to the bit loc a tion.
R/WC
7PIRQBF_ACT_STS
PIRQ[B or F].
0 = The corresp onding PCI inte rr upt s have not been active.
1 = At least one of the c orresponding PCI interrupts has b een
active. Cle ar this bit by wr iting a 1 to the bit loc a tion.
R/WC
6PIRQAE_ACT_STS
PIRQ[A or E].
0 = The corresp onding PCI inte rr upt s have not been active.
1 = At least one of the c orresponding PCI interrupts has b een
active. Cle ar this bit by wr iting a 1 to the bit loc a tion.
R/WC
5LEG_ACT_STS
Pa rallel Port, Serial Port 1, Ser ial Port 2, Floppy Disk
Controller.
0 = Indicates that t her e ha s been no acce ss to thi s devic e’s I/
O ran ge.
1 = This device’s I/O range h as be e n a ccessed. Clear this bit
by writing a 1 to the bit location.
R/WC
4 Reserved Reserved.
3IDES1_ACT_STS
IDE Secondary Drive 1.
0 = Indicates that t her e ha s been no acce ss to thi s devic e’s I/
O ran ge.
1 = This device’s I/O range h as be e n a ccessed. Clear this bit
by writing a 1 to the bit location.
R/WC
2IDES0_ACT_STS
IDE Secondary Drive 0.
0 = Indicates that t her e ha s been no acce ss to thi s devic e’s I/
O ran ge.
1 = This device’s I/O range h as be e n a ccessed. Clear this bit
by writing a 1 to the bit location.
R/WC
1 IDEP1_ACT_STS
IDE Primary Drive 1.
0 = Indicates that t her e ha s been no acce ss to thi s devic e’s I/
O ran ge.
1 = This device’s I/O range h as be e n a ccessed. Clear this bit
by writing a 1 to the bit location.
R/WC
0 IDEP0_ACT_STS
IDE Primary Drive 0.
0 = Indicates that t her e ha s been no acce ss to thi s devic e’s I/
O ran ge.
1 = This device’s I/O range h as be e n a ccessed. Clear this bit
by writing a 1 to the bit location.
R/WC
Table 297. DEVACT_STS—Device Activity Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE +44h Attribute: Re ad/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
414 Order Number: 300641-004US
8.8.3.15 DEVTRA P_EN— Device Trap Enable Register
Note: This register enables the individual trap ranges to generate an SMI# when the
c or re sp o n di ng s t atus bi t i n t h e D E V A C T_ ST S reg i s t er i s se t. Wh en a rang e i s enab le d , I /
O cycles associated with that range will not be forwarded to LPC or IDE.
Note: Usage: Legacy only.
Table 298. DEVTRAP_EN— Device Trap Enable Register
Bits Name Description Access
15:1
4Reserved Reserved.
13 ADLIB_TRP_EN
Ad-Lib.
0 = Disabl e.
1 = Enable.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/W
12 KBC_TRP_EN KBC (60/64h).
0 = Disabl e.
1 = Enable. R/W
11 MIDI_TRP_EN
MIDI.
0 = Disabl e.
1 = Enable.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/W
10 AUDIO_TRP_EN
Audio (Sound Blaster “ORed” with MSS).
0 = Disabl e.
1 = Enable.
NOTE: This bit is no long e r sup ported and will no t be
validated.
R/W
9:6 Reserved Reserved.
5 LEG_IO_TRP_EN
Parallel Port, Serial Port 1, Seria l Port 2, Flop py Di sk
Controller.
0 = Disabl e.
1 = Enable.
R/W
4 Reserved Reserved.
3IDES1_TRP_EN
IDE Secondary Drive 1.
0 = Disabl e.
1 = Enable. R/W
Device: 31 Function: 0
I/O Address: PM BASE +48 h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 415
8—Intel® 6300ESB ICH
8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker
This register could be used by the SMI# handler to assist in determining what was the
last cycle from the processor. BUS_ADDR_TRACK may not contain “expected” last I/O
cycle data when Asynchronous SMIs and Synchronous SMIs are occurring
simultaneously. This register only reports “expected” last I/O cycle data when
Asynch ronous SMIs are disabled.
Note: Usage: Legacy only.
8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker
This register could be used by the SMM handler to assist in determining what was the
last cycle from the processor. BUS_CYC_TRACK may not contain “expected” last I/O
cycle data when Asynchronous SMIs and Synchronous SMIs are occurring
simultaneously. This register only reports “expected” last I/O cycle data when
Asynch ronous SMIs are disabled.
Note: Usage: Legacy only.
2 IDES0_TRP_EN IDE S econdary Drive 0.
0 = D isa b le .
1 = Enable. R/W
1IDEP1_TRP_EN
IDE Primary Drive 1.
0 = D isa b le .
1 = Enable. R/W
0IDEP0_TRP_EN
IDE Primary Drive 0.
0 = D isa b le .
1 = Enable. R/W
Table 298. DEVTRAP_EN— Device Trap Enable Register
Bits Name Description Access
Device: 31 Function: 0
I/O Address: PMBASE +48h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Tab l e 29 9. BUS _ AD DR _TRA C K— Bu s Add re ss Tr ac ke r
Bits Name Description Access
15:0
Corresponds to the low 16 bits of the last I/O cy cle, as would
be defined by the PCI AD[15:0] sign als on the PCI bus (even
thou gh it m ay not be a real PCI cycle). T he value is latched
base d on SMI# ac tive. This functi on ality is useful fo r fi guring
out which I/O wa s last being a cce ssed.
Device: 31 Function: 0
I/O Address: PMBASE +4Ch Attribute: Read-Only
Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
416 Order Number: 300641-004US
8.9 System Management TCO Registers
(D31:F0)
The TCO logic is accessed through registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. Fo r TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
8.9. 1 TC O Register I/ O Map
Th e T C O I/O re g is t e rs r es id e in a 32- b yte ra ng e p o i nte d t o by a T COBAS E v a lu e, wh ich
is, ACPIBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the sections
below.
Table 300. BUS_CYC_TRACK— Bus Cycle Tracker
Bits Name Description Access
7:4
Corresponds to the byte enables, as would be defined by the
PCI C/BE# signals on the PCI bus (even though it may not be
a real PCI cyc le). The value is latched based on SMI# going
active.
3:0
Cor responds to the c ycle t ype, as would be d efine d by th e PCI
C/BE# signals on the PCI bus (even t hough it may no t be a
real PCI cy cle ). The value is la tched base d on SMI# going
active.
Device: 31 Function: 0
I/O Address: PM BASE +4E h Attribute: Read-Only
Size: 8-bit
Lockable: No Power Well: Core
Table 301. TCO I/O Register Map
Offset Typ
eRegister Name: Function
00h R/W TCO_RLD: TCO Timer Relo ad and Curren t Value
01 h R/W TCO _TMR: TCO Timer In itial Value
02h R/W TCO_DAT _IN : TCO Data In
0 3 h R/ W TCO _ DAT _ O UT: TC O Data O u t
04h - 05h R/W TC O1_STS: TCO Status
06h - 07h R/W TC O2_STS: TCO Status
08h - 09h R/W TCO1_CNT: TCO Control
0Ah - 0Bh R/W T CO2_CNT: TCO Control
0Ch - 0Dh R/W TCO_MESSAGE1, TC O_MESSAGE2: Used by BIOS to indicate POST/Boot
progress
0Eh R/W TCO _WDSTAT US: Watchdo g Stat us Regist er
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 417
8—Intel® 6300ESB ICH
8.9.2 TCO1_RLD—TCO Timer Reload and Current Value
8.9.3 TCO1_TMR—TCO Timer Initial Value
0Fh RO Reserved
10h R/W SW_IRQ_GEN: Software IRQ Generation Register
11h - 1Fh RO Reserved
Table 302. TCO1_RLD—TCO Timer Reload and Current Value
Bits Name Description Access
7:0 Re ad in g th is re g ister will retu rn the cu rrent count of the TCO
time r. Writin g any value to this reg iste r will rel oa d the tim e r
to prevent the timeout. Bits 7:6 will always be 0.
Tab l e 30 3. TC O 1 _T MR —T C O Tim e r Init i al Va lue
Bits Name Description Access
7:6 Reserved Reserved.
5:0
Va lue that is loa ded into the timer each time the TCO_RL D
register is written. Values of 0h - 3h will be ignored and
shou ld not be atte mp te d . The timer is clocked at
approximately 0.6 seconds, and this allows timeouts ranging
from 2.4 seconds to 38 seconds.
R/W
Table 301. TCO I/O Register Map
Offset Typ
eRegister Name: Function
Device: 31 Function: 0
I/O Address: TCOBASE +00h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: TCOBASE +01h Attribute: Read/Write
Defau lt Value: 04h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
418 Order Number: 300641-004US
8.9.4 TCO1_DAT_IN—TCO Data In Register
8.9.5 TCO1_DAT_OUT—TCO Data Out Register
Table 304. TCO1_DAT_IN—TCO Data In Register
Bits Name Description Access
7:0 Data Register for passing commands from the OS to the SMI
hand le r. Writes to th is re g iste r will cause an S M I an d set the
OS_TCO_SMI b it in the TCO_STS re g ister.
Table 305. TCO1_DAT_OUT—TCO Data Out Register
Bits Name Description Access
7:0
Data Register for passing commands from the SMI handler to
the OS. Write s to this register will set the TCO_INT_STS bit in
the TCO_S TS re gister. It wi ll a lso ca use an int er rupt, as
select e d by the TCO_ INT_S E L b its.
Device: 31 Function: 0
I/O Address: TCOBASE +02h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 0
I/O Address: TCOBASE +03h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 419
8—Intel® 6300ESB ICH
8.9.6 TCO1_STS—TCO1 Status Register
Table 306. TCO1_STS—TCO1 Status Register (Sheet 1 of 2)
Bits Name Description Access
15:1
3Reserved Reserved.
12 HUBSERR_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = The Intel® 6300ES B ICH re ceived an SER R# me ss age
through the Hub Interface. The software must read t he
mem ory cont roller hub (or its e q u ivalen t) to d e te rmine
the reason f or the S E RR#.
NOTE: W he n this b it is set A ND th e SERR_EN bit in CMD
register (D30:F0, Offset 04h, b it 8) is also set, the
Intel® 6300ESB ICH will set the SSE bit in SECSTS
registe r (D30:F0, offset 1E h, b it 14) A ND will a lso
generate a NMI (or SMI# when N MI routed to SMI#).
R/WC
11 HUBNMI_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = The Intel® 6300ESB ICH re ceived an NMI message
through the Hub Interface. The software must read t he
mem ory cont roller hub (or its e q u ivalen t) to d e te rmine
the rea son f or the N M I.
R/WC
10 HUBSMI_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = The Intel® 6300ESB ICH re ceived an SMI message
through the Hub Interface. The software must read t he
mem ory cont roller hub (or its e q u ivalen t) to d e te rmine
the rea son f or the S M I#.
R/WC
9 HUBSCI_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = The Intel® 6300ESB ICH re ceived an SCI message
through the Hub Interface. The software must read t he
mem ory cont roller hub (or its e q u ivalen t) to d e te rmine
the rea son f or the S CI .
R/WC
8 BIOSWR_STS
0 = Sof twa re cle ars this bit by w riting a 1 to the bit pos ition.
1 = The Intel® 6300ESB ICH se ts th is bit and gene rates and
SMI# to ind ica te an illegal attempt to write to the BIOS .
This occurs when either:
a) T he BIOSWP bit is change d from 0 t o 1 an d the B LD bit
is also se t, or
b) any write is att emp te d to the B IOS an d the BIOS W P
bit is also set.
R/WC
Device: 31 Function: 0
I/O Address: TCOBASE +04h Attribute: Read-O nly, Read/Write Clea r
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Co re (Exc e pt bit 7, in RT C)
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
420 Order Number: 300641-004US
7NEWCENTURY_STS
This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST#
going ac t i ve.
1 = This bit is set whe n th e Year byte (RTC I/O space, ind e x
offset 09h) rolls over from 99 to 00 . Setting this bit will
cause an SMI# (but not a wake event).
Note that the NEWCENTURY_STS bit is not valid when the
RT C battery is first installed (or when RTC power has not been
maintained). Softwa re may determin e whe n RTC power has
not been ma intaine d by check ing the RTC_PWR_ST S bit, or
by other means (such as a checksum on RTC RAM). When
RTC power is determined to have not been maintaine d , B IOS
should set the time to a legal value and then cl ear the
NEWCENTU RY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for
the bit to be cleared after a “1” is written to the bit to clear it.
After writing a “1” to this bit, sof tware should not exit the SMI
hand ler u ntil verifying tha t the bit has actu ally been cleared.
This will e nsure that the SM I is not re -e n te re d .
R/WC
6:4 Reserved Reserved.
3TIMEOUT
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Set by the Intel® 6300ESB ICH to indicate that the S MI
was caused by the TCO timer reaching 0. R/WC
2TCO_INT_STS
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = SMI handle r caused the interr up t by writing to the
TC O _ DAT_O U T register. R/WC
1SW_TCO_SMI
0 = Software clears this bit by wr iting a 1 to th e bit position.
1 = Softwar e ca used an SMI# by wr iting to the TCO_DAT_IN
register. R/WC
0 NMI2SMI_STS
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the Intel® 6300ESB ICH when an SMI# occurs
becaus e an event occurr ed that would other wi se have
caused an NMI (because NMI2S MI_EN is set).
RO
Table 306. TC O1_STS—TCO1 Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 0
I/O Address: TCOBASE +04h Attribute: Read-O nly, Read/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core ( Exc e pt bit 7, in RT C)
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 421
8—Intel® 6300ESB ICH
8.9.7 TCO2_STS—TCO2 Status Register
Table 307. TCO2_STS—TCO2 Status Register
Bits Name Description Access
15:5 Reserved Reserved.
4 SMLINK_SLV_SMI_STS
SMLink Slave SMI Status (Allow the software to go directly
into pre-d etermin e d sl eep sta te . This avoids race conditions.
0 = The bit is rese t b y RSMRST#, but not due to the PCI
Reset associa te d with exit from S3-S5 sta te s.
1 = The Intel® 6300ESB ICH sets th is bit to 1 whe n it
recei ves the SMI me ss age on the SMLink's Slave
Interface. Software clears the bit by writing a 1 to this bit
position.
R/W
3BAD_BIOS
This bit is set by the Intel® 6300ESB ICH when it detects FFh
on the first BIOS read (i.e. , the BIOS is bad). Intel® 6300ESB
ICH clears this bit to 0 if the first BIOS read is not FFh. This is
detect ed when the init ial re ad re turns FFh fr om the FWH. This
bit is not int ended to be re ad by the BIO S or softwa re . It is
only u se d for sendin g t he TCO/Hear tb eat messages to an
External LAN Controller. Reads to this bit always return 0 and
writes have no effect.
2 BOOT_STS:
0 = Cleared by the Intel® 6300ESB ICH based on RSMRST#
or by soft ware writing a 1 to this bit. N ote that sof tware
shoul d fir s t cle ar t he SECOND_ T O _STS bi t bef ore wri ti n g
a 1 to clear the B OOT_STS bit.
1 = Set to 1 wh en t he SECOND_ T O _ST S bi t goes fr om 0 to 1
and the processor has not fetched the first instruction.
1SECOND_TO_STS
0 = This bit is cleared by writing a 1 to the bit position or by a
RSMRST#.
1 = The Intel® 6300ESB ICH sets th is bit to a 1 to indica te
that the TCO timer time d out a second time (p rob ab ly
du e to syst e m lo ck). Wh e n th i s b i t i s se t an d t h e
NO_REBOOT configur ation bit is 0, then the Intel®
6300ESB ICH will re boot the syste m afte r the second
timeout. The reboot is done by asserting PXPCIRST#.
R/WC
0INTRD_DET: Intruder
Detect
0 = Thi s bit is only cleare d by writing a 1 to the bit position,
or by RTCRST # assertion.
1 = Set by the Intel® 6300 ES B ICH to ind icate that an
intrusion was detected. This bit is set even when the
syste m is in G3 sta te .
R/WC
Device: 31 Function: 0
I/O Address: TCOBASE +06h Attribute: Read-O nly, Read/Write Clea r
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume (Exc ept Bit 0, in RTC)
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
422 Order Number: 300641-004US
8.9.8 TCO1_CNT—TCO1 Control Register
Table 308. TCO1_CNT—TCO1 Control Register
Bits Name Description Access
15:1
3Reserved Reserved.
12 TCO_LOCK
0 = This bit defaults to 0. A core-well re set is r equired to
change this bit from 1 to 0.
1 = Prevents writes from changing the TCO_EN bit (in offset
30h of Power Management I/O space). Once this bit is set
to 1, it can not be clea re d by softwa re writing a 0 to this
bit location.
R/W
11 TCO_TMR _HLT: TC O
Timer Halt
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot
reach a value th at will ca use an SMI# or s et th e
SECON D_ TO_S TS bit. When se t, th is bit will preven t
reb ooting and prev ent Ale rt On LAN even t messag es from
being transmitted on the SMLINK (b ut not Alert On LAN*
heartbeat messages).
R/W
10 SEND_NOW
0 = The Intel® 6300ESB ICH will clear this bit when it has
complet e d se n d in g th e message . Sof twa re must N OT set
this bit to 1 again until the Intel® 6300ES B ICH has se t it
back to 0.
1 = Writing a 1 to th is b it will cau se the Intel® 6300ESB ICH
to send an Event message with the Software Event b it
set.
R/W
9 NMI2SMI_EN
0 = Normal N M I f unctionality.
1 = Forces a ll N MIs to in stead caus e SMIs. The functional ity
of this bit is depende nt u pon the sett ing s of th e NMI_EN
bit and the GBL_SMI_EN b it as detailed in the following
table:
NMI_ENGBL_SMI_ENDescription
0 0 No SMI# at all because GBL_S MI_EN = 0
0 1 SMI # will be cause d du e t o N MI events
1 0 No SMI# at all because GBL_S MI_EN = 0
1 1 No SMI# due to NMI because NMI_EN = 1
R/W
8NMI_NOW
0 = This bit is cleared by writing a 1 to the bit position. The
NMI handler is expected to clear this bit. Another N MI will
not be generated until the bit is cleared.
1 = Writing a 1 to this bit cause s an N M I. This allows the
BIOS or SMI handler to force an entry to the NMI handler.
R/WC
7:0 Reserved Reserved.
Device: 31 Function: 0
I/O Address: TCOBASE +08h Attribute: Read-O nly, Read/Write Clear
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 423
8—Intel® 6300ESB ICH
8.9.9 TCO2_CNT—TCO2 Control Register
8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers
Tab l e 30 9. TCO 2 _CNT— TC O 2 C ont ro l Reg is ter
Bits Name Description Access
15:4 Reserved Reserved.
3GPIO11_ALERT_DISABL
E
Disable GPIO11/SMBALERT# as an alert source for the
heartbe ats and the SMBus slave. At res et (via RS MRS T#
asserted) this bit is set and GPIO[11] alerts are disabled R/W
2:1 INTRD_SE
Selects the act ion to take when the IN TRU DER # sign al g oes
active.
00 = No interr upt or SMI#
01 = Int e rrupt (a s se le ct e d by TCO_INT_SEL).
10 = SMI
11 = Reserved
R/W
0 Reserved Reserved.
Table 310. TCO_MESSAGE1 and TCO_MESSAGE2 Registers
Bits Name Description Access
7:0 TCO_MESSAGE[n]
The v alue written to this register can be passe d via SMBus to
an External LAN controller. It may be us ed by the BIOS or
system management software to indicate more details on the
boot progress. This register will be reset to the default of 00h
based on RSM RST# (but not PCI reset ).
R/W
Device: 31 Function: 0
I/O Address: TCOBASE +0Ah Attribute: Read/Write
Defau lt Value: 0008h Size: 16-bit
Lockable: No Power Well: Resume
Device: 31 Function: 0
I/O Address:
TCOBASE+0Ch(Message
1)
TCOBASE+0Dh(Message
2)
Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
DS November 2007
424 Order Number: 300641-004US
8.9.11 Offset TCOBAS E + OEh: TCO_WDSTATUS—TCO2
Control Register
8.9.12 Offse t TCOB ASE + 10h: SW_IRQ_GEN—S oftware
IR Q Generati on Register
Table 311. Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register
Bits Name Description Access
7:0 WDSTATUS: Wat c hdo g
Status
The value w r itten t o this re gister can be pa ssed via SMBu s to
an External LAN c ontroller. It may be used by the BIOS or
system management software to indicate more details on the
boot progress. This register will be reset to the default of 00h
base d o n RS MRST# (b ut not PCI rese t ).
R/W
Table 312. Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation
Register
Bits Name Description Access
7:2 Reserved Reserved.
1 IRQ12_CAUSE
The state of this bit is lo gica lly AND e d with the IRQ12 sig n al
as received by the Intel® 6300ESB ICH’s SERIRQ logic. This
bit must be a ‘1’ (default) when the Intel® 6300ESB ICH is
expe cte d to receiv e IRQ 1 2 a sse rtions from a SERIRQ device .
R/W
0IRQ1_CAUSE
The state of this bit is logically ANDed with the IRQ1 signal as
received b y the Intel® 6300ES B ICH’s SERIRQ logic. This bit
must be a ‘1’ (default) when the Intel® 6300ESB ICH is
expe cte d to receive IRQ1 a sse rtions f rom a S ER IR Q device .
R/W
Device: 31 Function: 0
Offset: TCOBASE + 0Eh Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Resume
Device: 31 Function: 0
Offset: TCOBASE + 10h Attribute: Read/Write
Defau lt Value: 11h Size: 8-bit
Lockable: No Power Well: Core
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8. 10 Gen eral Purpo se I/ O Registers (D31 :F 0)
The control f or the general purpose I/O signals is handled through a separate 64-byte
I/O space. The base offset for this space is selected by the GPIO_BAR register.
8.10.1 GPIO Register I/O Address Map
Table 313. Registers to Control GPIO
Offset Mn emon ic Regi st er Name Default Acc es s
General Registers
00-03h GPIO_USE_ SEL G PIO Use Select 1B 003100h R/W
04-07h GP_IO_SEL G PIO Inp u t/Output Select 0000
FFFFh R/W
0C -0Fh GP_LVL GPIO Level for Input or Output 1F1F
0000h R/W
Output C o ntrol Regi sters
18-1B h G PO_B LINK GPIO B link Enabl e 00000000h R/W
Input Control Registers
2C-2 Fh GPI_IN V G PIO S ig nal Invert 00000000h R/W
30-33h GPIO_USE_SEL
2GPIO Us e Sele ct 03000000h R/W
34-37h GP_IO_SEL2 G PIO Inp ut/Output Select 2 00000000h R/W
38-3Bh GP_LVL 2 GPIO L evel for Input or Output 2 00000FFFh R/W
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
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426 Order Number: 300641-004US
8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO
Use Select Register
8.10.3 Offset GPIOBASE + 04h: GP _IO_SEL—GPIO
Input/Output Select Register
Table 314. Offset GPI OBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register
Bits Name Description Access
23,
21:1
6,
11,
7:0
GPIO_USE_SEL[0:7, 11,
16:21, 23]
Enables GPIO[n] (whe re n is the bit number ) to be used as a
GPIO, rather than for the native function.
1 = Signal used as GPIO (or unmuxed). 0 = Signal used as
native function.
Notes:
1. The f ol lowing bits ar e not i mplemen ted becaus e there is no
corresponding GPIO: 9:10, 14:15, 22,
26 and 29:31.
2. The following bits are always 1 because they ar e
unmuxed: 8, 12 :13, 24, 25, 2 7:28.
3. When GPIO[n] does not exist, the bit in this reg ister will
always read as 0 and writes will have no effect.
4. After a f ull re se t (RS M RS T#) all multiple x ed sig na ls in the
resume and cor e wells are con f igured as th e ir na ti ve
function rather than as a G PIO. After jus t a PXPCIRS T#,
the GPIO in the cor e well are configured as their nativ e
function.
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select
Register
Bits Name Description Access
31:2
9, 26 Reserved Reserved.
28:2
7
25:2
4
GPIO[n]_SEL 0 = Ou tput. The corresp on d in g GPIO sig n a l is a n ou tput.
1 = Input. The corresponding GPIO signal is an input. R/W
23 Al ways 0. The GPIOs are fixed as outputs.
Device: 31 Function: 0
Offset: GPIO BASE + 00h Attribute: Read/Write
Defau lt Value: 1B003100h Size: 32-bit
Lockable: Yes Power Well: Core for 0:7 and 16 :21, 23
Resume for 8:15 and 24:31
Device: 31 Function: 0
Offset: GPIO BASE +04 h Attribute: Read-Only
Defau lt Value: 0000FFFFh Size: 32-bit
Lockable: No Power Well: Resume
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8.10.4 Off set GPIOBASE + 0Ch: GP_LV L—GPIO Level for
Input or Output Register
22 Reserved Reserved.
21:1
6Always 0. The GPIOs are fixed as outputs.
15:0 Always 1. These GPIOs are fixed a s inputs.
Table 316. Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output
Register
Bits Name Description Access
31:2
9, 26 Reserved Reserved.
28:2
7,
25:2
4
GP_LVL[n]
When G P IO[n] is prog ra mmed to be an outpu t (throug h the
corresponding b it in the GP_IO_SEL register), the bit may be
update d by s o ftw a re t o dri ve a high o r low value o n th e
output pin. When GPIO[n] is programmed as an input,
softwar e m ay rea d the bit to de te rmine the level on the
co rre sp on d i ng input pin. These b i ts corresp ond to GPIO th at
are in the Resum e wel l, an d wil l be reset to the ir d e f ault
values by RSMRST# and also by a write to the CF9h r egister.
0 = Lo w
1 = Hig h
R/W
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select
Register
Bits Name Description Access
Device: 31 Function: 0
Offset: GPIO BASE +04 h Attribute: Read-Only
Defau lt Value: 0000FFFFh Size: 32-bit
Lockable: No Power Well: Resume
Device: 31 Function: 0
Offset: GPIO BASE +0C h Attribute: Read/Write
Defau lt Value: 1B3F0000h Size: 32-bit
Lockable: No Power Well: See bit descript io n s
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
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23 GP_LVL[n]
Th ese bit s ma y be up dat ed by soft w ar e t o dr ive a hi gh o r low
value on the output pin. These bits correspond to GPIO that
are in the core we ll, an d will b e reset to their def au lt value s
by PXPCIRST #.
0 = Low
1 = High
R/W
21:1
6GP_LVL[n]
Th ese bit s ma y be up dat ed by soft w ar e t o dr ive a hi gh o r low
value on the output pin. These bits correspond to GPIO that
are in the core we ll, an d will b e reset to their def au lt value s
by PXPCIRST #.
0 = Low
1 = High
R/W
15:0 Reserved
Reserved. These bits are not needed as the level of general
inputs can be read through the GPE0_STS and
ALT_GP_SMI_STS registers. See Section 8.8.3.7 and
Section 8.8.3.12
Table 316. Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output
Register
Bits Name Description Access
Device: 31 Function: 0
Offset: GPIO BASE +0C h Attribute: Read/Write
Defau lt Value: 1B3F0000h Size: 32-bit
Lockable: No Power Well: See bit descripti on s
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8.10.5 Off se t GPIOBASE + 1 8h: GPO_BLINK—GPO Blink
Enable Register
Table 317. Off set GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register
Bits Name Description Access
31:2
9,
26,
24:2
0,
17:0
Reserved Reserved.
28:2
7, 25 GP_BLINK[n]
The setting of these bits will have no effect when the
corresponding GPIO is programmed as an input. These bits
corre spond to GPIO th at a re in th e Resum e well, and will be
reset to their default values b y RSMRS T # or a write to the
CF9h register.
0 = The correspon d in g G PIO will f u nction norm a lly.
1 = When the corres pondi ng GPIO is programm ed as an
output, the ou tp ut signal will blink at a rat e of
approximately once per second. The high and low times
have approximately 0.5 seconds each. The GP_LVL bit is
not altered whe n this b it is set.
R/W
19:1
8GP_BLINK[n]
The setting of these bits will have no effect when the
corresponding GPIO is programmed as an input. These bits
correspond to GPIO that are in the Core well, and will be reset
to their default values by PXPCIRST#.
0 = The correspon d in g G PIO will f u nction norm a lly.
1 = When the corres pondi ng GPIO is programm ed as an
output, the ou tp ut signal will blink at a rat e of
approximately once per second. The high and low times
are approximately 0.5 seconds each. The GP_LVL bit is
not altered whe n this b it is set.
R/W
Device: 31 Function: 0
Offset: GPIO BASE +18 h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: See bit descript io n
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
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430 Order Number: 300641-004US
8.10.6 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal
Invert Register
Table 318. Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register
Bits Name Description Access
31:1
4,
10:9 Reserved Reserved.
13:1
1, 8 GP_INV[n]
These bits are used to a llow both active-low and active-hi gh
inputs to cause SMI# or SCI. Note that in the S0 or S1 state,
the input signal must be acti ve for at least 2 PCI clocks to
ensure detection by the Intel® 6300ESB ICH. In the S3, S4 or
S5 states the input signal must be active for at least 2 RTC
clocks to ensure detection. The setting of these bits will ha ve
no effec t when t he cor respon din g GPI O is pr ogr am med as an
output. These bits correspond to GPIO that are in the Resume
well, and will b e reset to their defa ult value s by RSMRST# or
a write to the CF9h re g ister.
0 = The corresponding GPIn _STS bit will be set when the
Intel® 63 00ES B ICH dete cts the state of the input p in to
be hig h.
1 = The corresponding GPIn _STS bit will be set when the
Intel® 63 00ES B ICH dete cts the state of the input p in to
be l ow.
NOTE: The GPIn_STS bi ts are i n the GPE0 _ST S R eg i ster. See
section 9.8.3.7
R/W
7:0 GP_INV[n]
These bits are used to a llow both active-low and active-hi gh
inputs to cause SMI# or SCI. Note that in the S0 or S1 state,
the input signal must be acti ve for at least 2 PCI clocks to
ensure d ete ction b y the Intel ® 6300ESB ICH. The s etting of
these bits will have no effect when the corresponding GPIO is
programme d as an outp ut. These bits correspond to GPIO
that are in the Core we ll, a nd will b e reset to their def au lt
values by PXPCIRST#.
0 = The corresponding GPIn _STS bit will be set when the
Intel® 63 00ES B ICH dete cts the state of the input p in to
be hig h.
1 = The corresponding GPIn _STS bit will be set when the
Intel® 63 00ES B ICH dete cts the state of the input p in to
be l ow.
R/W
Device: 31 Function: 0
Offset: GPIO BASE +2C h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: See bit descripti on
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8. 10.7 Offset GP IOBASE + 30h:GPIO_USE_SEL 2—GPIO
Use Select 2 Register
Table 319. Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register
Bits Name Description Access
31:2
6Al w ays 0. N o co rresponding GPI O.
25:2
4Always 1. These pins are unmuxed.
23:1
2Al w ays 0. N o co rresponding GPI O.
11:8
GPIO_USE_SEL[43:40]: Enables GPIO[n] (where n is the
bit number) to be used as a GPIO, rathe r than for the native
function. S ince the se pins may be used as outputs f or
controlling p ower planes, switching the pin from functional to
GPO mode must be g litch-free.
1 = Signal used as GPIO (or unmuxed).
0 = Signal used as native function.
Afte r a full rese t(RSMRS T#) all multiple xed sig na ls in th e
resume and core wells are configured as their native function
rather than as a GP IO. After just a PXPCIR ST#, the G PIO in
the core well are conf igured as GPIO.
7:0
GPIO_USE_SEL[39:32]: Enables GPIO[n] (where n is the
bit number) to be used as a GPIO, rathe r than for the native
function. S ince the se pins may be used as outputs f or
controlling p ower planes, switching the pin from functional to
GPO mode must be g litch-free.
1 = Signal used as GPIO (or unmuxed).
0 = Signal used as native function.
Afte r a full rese t(RSMRS T#) all multiple xed sig na ls in th e
resume and core wells are configured as their native function
rather than as a GP IO. After just a PXPCIR ST#, the G PIO in
the core well are conf igured as GPIO.
Implementation Note: Bits 26:3 1 may be in CORE Well.
Device: 31 Function: 0
Offset: GPIO BASE +30 h Attribute: Read/Write
Defau lt Value: 03000000h Size: 32-bit
Lockable: No Power Well: Co re for 55:32 = b its 23:0
Resume for 63:56 = bits 31:24
Intel® 6300ESB ICH—8
Intel® 6300ESB I/O Controller Hub
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432 Order Number: 300641-004US
8.10.8 Offset GPIOBASE + 34h: GP _IO_SEL2—GPI O
Input/Output Select 2 Regis ter
8.10.9 Off set GP IOBASE + 38h: GP_LVL2—GPIO Le vel f or
Input or Outp ut 2 Register
Table 320. Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2
Register
Bits Name Description Access
31:2
6Always 0. N o corresp on d in g G P I O.
25:2
4Alway s 0 . Output o nly.
23:1
2Always 0. N o corresp on d in g G P I O.
11:0 GP_IO_SEL2[43:32]
When set to a 1, the corre sponding GPIO signal (when
enabled in the GPIO_USE_SEL2 register) is programmed as
an input. When set to 0, the GPIO signal is programmed as an
output.
Impl emen tati o n Note: Bits 26 :31 may be in CORE Well .
Table 321. Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2
Register
Bits Name Description Access
31:2
6Reserved Reserved. Read-only 0. RO
25:2
4GP_LVL[57:56]
The GP_LVL[n] bit may be updated by software to drive a
high or low value on the output pin. 1 = hig h, 0 = low.
NOTE: These output are open drain. Setting this bit to one
does not drive a ‘1’ but allows for an external pullup to
cause a high value on the pin.
Since these bits correspond to GPIO that are in the RTC well,
these bi ts will b e re se t by RTCRST #.
Device: 31 Function: 0
Offset: GPIO BASE +34 h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core for 23:0;
Resume f or 31:24
Device: 31 Function: 0
Offset: GPIO BASE +38 h Attribute: Read/Write
Defau lt Value: 00000FFFh Size: 32-bit
Lockable: No Power Well: Core for 23:0, RTC for 31:24
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23:1
2Re se rv e d Re se rv ed. Rea d-only 0 . RO
11:0 GP_LVL2[43:32]
When G P IO[n] is prog ra mmed to be an outpu t (throug h the
corresponding bit in the GP_IO_SEL2 register), the
corr espondi ng GP_L VL 2[n] bi t may be u pdated b y softwar e to
drive a high or low value on the output pin. 1 = high, 0 = low.
When G PIO[n] is p rog rammed as an input, then the
corre spond ing G P_LVL2 bit reflects the state of the inp ut
signal (1 = high, 0 = low). Writes will have no effect.
Since these bits correspond to GPIO that are in the core well,
these bits will be reset by PXPCIR ST#.
Implementation Note: Bits 26:3 1 may be in CORE Well.
Table 321. Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2
Register
Bits Name Description Access
Device: 31 Function: 0
Offset: GPIO BASE +38 h Attribute: Read/Write
Defau lt Value: 00000FFFh Size: 32-bit
Lockable: No Power Well: Co re for 23:0, RTC for 31:2 4
Intel® 6300ESB ICH—8
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9—Intel® 6300ESB ICH
IDE Controller Registers (D31:F1)9
9.1 PCI Configuration Re gisters (IDE—D31:F1)
Note: Registers that are not shown should be treated as Reserved (see Section 6.2, “PCI
Conf ig ur ati on Ma p” for details). All of the IDE registers are in the core well. None of the
registers may be locked.
Table 322. PCI Configuration Map (IDE-D3 1:F1)
Offset M n emon ic Register Name/Fu ncti on D efa ult T ype
00-01h VI D Ven d or ID 8086h RO
02-03h DID Device ID 25A2h RO
04-05h CMD Command 00h R/W
06-07h STS Device Status 0280h R/W
08h RID Revision ID 0 0h See Note 1 RO
09h PI Programming I nte rf a ce 8Ah RO
0Ah SCC Sub Class Code 01h RO
0Bh BCC Base Class Code 01h RO
0Dh MLT M aster Latency T imer 00h RO
10-13h PCMD_BA R Pri mary Command Block Bas e Add ress 00000001h R/W
14-17h PCNL _B A R Primary Control B lock B a se Add ress 00000001h R/W
18-1Bh SCMD_BAR S econd ary Command Block B ase Addre ss 0 0000001h R/W
1C- 1Fh SCNL_BAR Secondary Control Block Base Address 0 0000001h R/W
20-23h B M_B ASE Bus Master Base Addre ss 0000000 1h R/ W
24-27h CPB A IDE Command Posting Base Ad dr ess 00000000h R/W
2C-2Dh IDE_SVID Subsystem Vendor ID 00h R/W r ite-Once
2E-2Fh IDE_SID Subsystem ID 00h R/Write-Once
3C INTR_LN Interrupt Line 00h R/W
3D INTR_PN Interrupt Pin 01h R/W
40-41h IDE_TIM Pri mary IDE Timing 0000h R/W
42-43h ID _TIMS Second ary ID E Timi ng 0000h R/W
44h SLV_IDETIM S lave IDE Timing 00h R/ W
48h SDMA_CNT Synchronous DMA Control 00h R/ W
4A-4Bh SDMATIM Synchronous DMA Timing 0000h R/ W
54h IDE_CONFIG IDE I/O Config uration 00h R/W
NOTES:
1. See the Intel® 6300ESB ICH Spe cif ication Upd a te for the most up-to-date value of the Revision ID Register.
2. The Intel® 6300ESB ICH IDE controller is not arbitrated as a PCI device, therefore it does not need a master
latency time r.
Intel® 6300ESB ICH—9
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9.1.1 Offset 00 - 01h: VID—Vendor ID Register (LPC I/
F—D31:F1)
9.1.2 Offset 02 - 03h: DID—Device ID Register (LP C I/
F—D31:F1)
Table 323. Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1)
Bits Name Description Access
15:0 Vendor ID Value This is a 16-b it value a ssig ne d to In te l. Inte l V ID = 8086h.
Table 324. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1)
Bits Name Description Access
Device ID This is a 16-b it value a ssig ne d to th e Inte l® 63 00e sb ICH RO
Device: 31 Function: 1
Offset: 00 - 01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 1
Offset: 02 - 03h Attribute: Read-Only
Defau lt Value: 25A2h Size: 16-bit
Lockable: No Power Well: Core
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9.1.3 Offse t 04h - 05h: CMD—C ommand Register ( IDE—
D31:F1)
Table 325. Offset 04h - 05h: CMD—Command Register (IDE—D31:F1)
Bits Name Description Access
15:1
1Reserved Reserved.
10 Interrupt Disable (ID)
Enables the P-ATA host controller to ass e rt the INTA# (in
native mode ) or IRQ14/15 (in legacy mod e ). Wh en set, the
interrupt will be deasserted. When cleared, the interrupt may
be assert ed.
9Fast Back to Back Enable
(FBE) Reserved as ‘0. RO
8 S ERR# Enab le Reserved as ‘0’. RO
7 Wait Cycle Control Res er ved as ‘0’. RO
6 Parity Error Response Reserv ed as ‘0. RO
5 VGA Palette Snoop Reserved as ‘0’. RO
4Postable Me mory Write
Enable (PMWE) Reserved as0. RO
3Special Cycle Enable
(SCE) Reserved as ‘0. RO
2Bus M a ste r E n able
(BME) Controls the Intel® 6300ESB ICH’s ability to act as a PCI
master for IDE Bus Master transfers. R/W
1Memory Space Enable
(MSE)
0 = D isa b le s a ccess.
1 = Enables access to the IDE Expansi on memory range. The
EXBA R register (O ffset 24h) mus t be program med before
this bit is set.
NOTE: B IOS should set this bit to a 1.
R/W
0IOSE - I/O Space Enable
(IOSE)
Th is b it cont rols acc ess to the I /O sp a ce registers.
0 = D isab les access to the Legacy or N ativ e IDE po rts (both
Primary and Secondary) as well as the Bus Master IO
registers.
1 = Enable. The Base Address register for the Bus Master
registers should be programmed before this bit is set.
NOTES:
1. Sep arate bits are provided (IDE Decode Enable, in the IDE
Timing register) to independently disable the Primary or
Se condary I/ O spaces.
2.When this bit is 0 and the IDE controller is in Native Mode,
the Interrupt Pin Register will be masked (the interrupt will
not b e a sse rted) See Section 1 0.1.16, “Offset 60h:
USB_RELNUM—USB Release Number Register (USB—
D29:F0/F1)” for more info rma tion rega rd in g the In te rrupt
Pin Register. When an interrupt occurs while the masking
is in place a nd the interrupt is still activ e wh en the
masking ends, the interrupt will be allowed to be asse rted.
R/W
Device: 31 Function: 1
Offset: 04h-05h Attribute: Read-Only, Read/Write
Defau lt Value: 00h Size: 16-bit
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Intel® 6300ESB I/O Controller Hub
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9.1.4 Offset 06 - 07h: STS—Device Status Register
(IDED31:F1)
Table 326. Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)
Bits Name Description Access
15 Det ecte d Parity Error
(DPE) Res er ved a s ‘0. RO
14 Signaled System Error
(SSE) Re se rv ed as ‘0’. RO
13 Rece ived M a st e r-A b o rt
Status (RMA)
0 Cleared by writing a 1 to it.
Bus Master ID E interf a ce fu nction, as a master, gene rate d a
master-abort. R/WC
12 Reserved Reserv e d as ‘0’.RO
11 Signa led Targ et-Ab ort
Stat us (STA)
0 = Clea red by writing a 1 to it.
1 = The Intel® 6300ES B ICH IDE interface functio n is
targete d wit h a transac tion that the Inte l® 6300ESB ICH
terminates w ith a ta rg e t abor t.
R/WC
10:9 DEVSEL # Timin g Statu s
(DEVT)
01 = Har dw ired; however, the Inte l® 6300ESB ICH does not
have a re al DEVSEL# sig nal associated with the IDE unit, so
these bits have no effect. RO
8Data Parity Error
Detected Re se rv ed as ‘0’. RO
7Fast Back-to-B a ck
Capable Rese rv ed as ‘1 . R O
6User Definable Features
(UDF) Rese rv ed as ‘0’. RO
5 66 MHz Capable Reserved as ‘0. RO
4 Capa b ilities List ( CA P) Reserv e d as ‘0’ RO
3 Interrupt Status (IS)
Reflects the state of interrupt at the input of the
enabl e. dis able circuit. This bit is a 1 when th e inte rrupt is
asserted.
1 = Interrup t is a sserted.
0 = Interrupt has been c leared (independent of the stat e of
the Interrupt Di sable bit in the command register.
RO
2:0 Reserved Reserved as ‘0. RO
Device: 31 Function: 1
Offset: 06-07h Attribute: Read/W rite Clear, Read-Only
Defau lt Value: 0280h Size: 16-bit
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9—Intel® 6300ESB ICH
9 . 1.5 Offset 08h: RID—Revision ID Re gist er (IDE
D31:F1)
9.1.6 Offset 09h: PI—Programming Inter fa ce ( IDE—
D31:F1)
T abl e 32 7. O f fse t 08h : RID R evi sion ID Re gis te r (I DE D3 1 :F 1 )
Bits Name Description Access
7:0 R evision ID Value Refer to the Intel® 6300ESB ICH Specification Update for t he
most
up-to-date value of the Revision ID Register. RO
Table 328. Offset 09h: PI—Programming Interface (IDE—D31:F1)
Bits Name Description Access
7This rea d -only bi t is a 1 to indicate tha t the Inte l® 6300ESB
ICH su pports bus ma ster opera tion
6 :4 Reserv ed Reserved. W ill a lways retu rn 0.
3SOP_MODE_CAP
This rea d -only bi t is a 1 to indicate tha t the se conda ry
controller supports both legacy an d native modes.
2 SOP_MODE_SEL
This rea d -write b its de te rmine s th e mod e that the secondary
IDE cha nn e l is op e ra ting in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
1POP_MODE_CAP
This read-only bit is a 1 to indicate that the primary controller
supports bo th legacy and native m odes.
0POP_MODE_SEL
This rea d -write b its d e termine s the mode that the p rimary
IDE cha nn e l is op e rat ing in .
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
NOTE: In the Inte l® 6300ES B ICH, this bit was read -only
with a value of 0.
Device: 31 Function: 1
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descript io n Size: 8-bit
Device: 31 Function: 1
Offset: 09h Attribute: Read/Write
Defau lt Value: 8Ah Size: 8-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
440 Order Number: 300641-004US
9.1. 7 Offs et 0Ah: SCC Sub C lass Code (IDE —D31 :F1)
Table 329. Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1)
Bits Name Description Access
7:0 Su b Cla ss Code 01h = ID E dev ice, in the cont e x t of a mass s tora ge d e vice. RO
Device: 31 Function: 1
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 441
9—Intel® 6300ESB ICH
9.1.8 Offset 0Bh: BCC—Base Class Code ( ID E—D31:F1)
9.1.9 Offset 0Dh: MLT— Master Latency Timer (IDE
D31:F1)
9.1.10 Of fset 10h - 13h: PCMD_BAR—Pr imar y Comm and
Block
Base Address Register (IDE—D31:F1)
Table 330. Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)
Bits Name Description Access
7 :0 B a se Cla ss Code 01 = Mas s stora g e device RO
T abl e 33 1. O ffs e t 0Dh : ML T— Ma s ter La ten cy Tim e r (IDE D 31 :F 1)
Bits Name Description Access
7 :0 Bu s M a ster Lat e n cy Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitr ated as a PCI device, so it does not
need a Master Latency Timer. These bits are fixed at 0. RO
Table 332. Offset 10h - 13h: PCMD_BAR—Primary Command Block Base
Address Register (IDE—D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:3 Base Address Base addr ess of the I/ O space (8 consecutive I/O locations). R/W
2:1 Reserved Reserved.
0Resource Type Indicator
(RTE) This bit is set to one, indicating a requ e st for IO sp ace. Read -
Only. RO
NOTE: This 8-byte I/O space is used in native mode for t he Pr imary Controlle r’s Command Bl ock .
Device: 31 Function: 1
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Device: 31 Function: 1
Offset: 0Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 1
Offset: 10h-13h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
442 Order Number: 300641-004US
9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control
Block Base
Address Register (IDE—D31:F1)
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary
Command Block
Base Address Regist er (IDE D31:F1)
Table 333. Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address
Register (IDE—D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:2 Base Address Base address of the I/O space (4 consecutive I/O locations). R/W
1 Reserved Reserved.
0 Re so ur ce Typ e In di cato r
(RTE) This bit is set to one , ind icating a re q ues t fo r IO spa ce. RO
NOTE: T his 4-byte I/O spa ce is u sed in native m od e for the Primary Controller’s Command Block .
Tabl e 334. Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base
Address Register (IDE D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:3 Base Address Base address of the I/O space (8 consecutive I/O locations). R/W
2:1 Reserved Reserved.
0Re so ur ce Typ e In di cat or
(RTE) This bit is set to one , ind icating a re q ues t fo r IO spa ce. RO
NOTE: T his 4-byte I/O spa ce is u sed in native m od e for the S e con d a ry Controllers Command Blo ck .
Device: 31 Function: 1
Offset: 14h-17h Attribute: Read-Only
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 1
Offset: 18h-1Bh Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 443
9—Intel® 6300ESB ICH
9. 1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secon dary C ontrol
Block
Base Address Register (IDE D31:F1)
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base
Addre ss Register (IDE—D3 1:F 1)
Note: The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
Table 335. Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block Base
Address Register (IDE D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:2 Base Address Base addr ess of the I/ O space (4 consecutive I/O locations). R/W
1 Reserved Reserved.
0Resource Type Indicator
(RTE) This bit is set to one, indicating a reque st f or IO spa ce. RO
NOTE: This 4-byte I/O space is used in native mode for th e Secondar y Con trolle r’s Command B lock .
Table 336. Offset 20h - 23h: BM_BASE—Bus Master Base Address Register
(IDE—D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:4 Base Address Base address of the I/O space (16 consecutive I/O locations).
3:1 Reserved Reserved.
0Resource Type Indicator
(RTE) Hardwired to’1 , ind ica ting a requ e st f or IO sp ace . RO
Device: 31 Function: 1
Offset: 1Ch - 1Fh Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 1
Offset: 20h - 23h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
444 Order Number: 300641-004US
9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting
Base Address
Note: The Intel® 6300ESB ICH requests 1 Kbyte of memory space for the Command Posting
accesses. This is much more than is needed; by requesting this much space, decoding
may be simplified. In addition to the standard PCI Memory Space Enable bit, the
Command Posting Enable bits in the IDE I/O Configuration register must be set for the
Intel® 6300ESB ICH to properly decode the accesses to this range.
Table 337. Offset 24h - 27h: CPBA – IDE Command Posting Base Address
Bits Name Description Access
31:1
0Ba se Addres s Ba se a ddre ss of the ID E Command Posti ng memory space
(aligned to 1 Kbyte). R/W
9:4 Hardwired Base Address T hese bits are hardwired to ‘0’ to indicate that the size of the
range requested is 1 Kbyte. RO
3Prefetchable
Hard-wire d to ‘ 0’, indicating th at t his ra nge is not pre-
fetchable. RO
2:1 Type Hard-wired to “00”, indicating that this rang e may be mapped
anywh ere in 32-bit address space. RO
0RTE – Resource Type
Indicator This bit is hard-wired to ‘0, indicating a request for memory
space. RO
Device: 31 Function: 1
Offset: 24h-27h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 445
9—Intel® 6300ESB ICH
9.1.16 Of fset 2Ch - 2Dh: IDE_SVI D —Subsystem Vendor
ID
(IDE—D31:F1)
Table 338. Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID (IDE—D31:F1)
Bits Name Description Access
15:0 Subsystem Vendor ID
(SVID)
The SVID register, in combination with the Subsystem ID
(SID) register, enables the operati ng system (OS) to
distinguish subsystems from each other. Software (BIOS)
sets th e value in this regis te r. Af te r tha t, the value may be
read, b u t subse q ue nt writes to this register have no effect.
The v alue w ritten to this r egister will also be r eadable t hrough
the corresponding SVID registers for the USB UHCI #1, USB
UHCI #2, and SMBus functions.
NOTE: Write accesses to the SVID register should only be
done as 16-b it a ccesse s. If two 8- bit w rite accesses
are done, then the value in the register will not be
correct.
R/Write-Once
Device: 31 Function: 1
Offset: 2Ch-2Dh Attribute: Read/Write Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
446 Order Number: 300641-004US
9.1.17 Offse t 2Eh - 2Fh: I DE_SID—Subsy stem I D (IDE—
D31:F1)
9.1.18 Offset 3Ch: INTR_LN—Interrupt Line Register
(IDED31:F1)
Table 339. Offset 2Eh - 2Fh: IDE_SID—Su bsystem ID (IDED31:F1)
Bits Name Description Access
15:0 Subsystem ID (SID)
The S I D register, in combinat ion w ith the SV I D register,
enab les th e op erat i ng s ys tem ( OS) to disti ngu is h s ubsy stems
from each other. Software (BIOS) sets the value in this
register. After that, the value may be rea d , but su bs e quent
wri tes to this r egister hav e no effec t. The v alue writ te n to this
registe r will also be read a b le th rough the corr e sp on d in g SID
registe rs for the US B UHCI #1, USB UH CI #2, an d SMBus
functions.
NOTE: Write accesses to the SID register should only be
done as 1 6-bit accesses. If two 8 -bit wri te ac ce sses
are done, then the value in the regi ster will not be
correct.
R/Write-Once
Table 340. Offset 3Ch: INTR_LN—Interrupt Line Register (IDE—D31:F1)
Bits Name Description Access
7:0 Interrupt Line This data is not used by the Intel® 6300ESB ICH. It is used to
commu nicate to soft ware the in te rrupt line whic h th e
interrupt pin is connected to. R/W
Device: 31 Function: 1
Offset: 2Eh-2Fh Attribute: Read/Write Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 1
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 447
9—Intel® 6300ESB ICH
9.1.19 Of fset 3Dh: INTR_PN—Interrupt Pin Re gi ster
(IDE—D31:F1)
9.1.20 IDE_TIM—IDE Timing Register (IDE—D31:F1)
Note: This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
T abl e 34 1. O f fse t 3Dh : IN TR _P N Int e rru p t Pi n Re gis te r (I D E— D 3 1:F 1 )
Bits Name Description Access
7:3 Reserved Reserved.
2:0 Interrupt Pi
The value of 01h indicates to “software” that the Intel®
6300E S B IC H will dr ive IN TA#. Note that this is only used in
native mod e . Also note that the routing to the internal
interrupt controller does not necessarily relate to the v alue in
this register. The IDE interrupt is in fact routed to PIRQ[C]#
(IRQ18 in APIC mode).
RO
Device: 31 Function: 1
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
448 Order Number: 300641-004US
Table 342. IDE_TIM—IDE Timing R egister (IDE—D31:F1) (Sheet 1 of 3)
Bits Name Description Access
15 IDE Decode Enable
(IDE)
Individ ually enable/disable the Primary or Secondary decode.
The IDE I/O Space Enable bi t in the Command register must
be set in order f or this bit to have any effec t. A dditionally,
separate config ur at i on bit s are provi ded (in the IDE I/O
Configuration register) to individually disable the primary or
secondary ID E interface sig n a ls, even wh e n th e ID E Decode
Enable bit is set.
0 = Disabl e.
1 = Enables the Intel® 6300ESB ICH to d e code the
associated Comm and Blocks (1F0- 1F7h for primary, 170-
177h for secondary) and Control Block (3F6h for primary
and 376h for secondary).
This bit effec ts the IDE decode ran ges for both legacy and
native-Mode de coding. It a lso effec ts th e corresp onding
primary or secondary memor y decode range for IDE
Expansion.
R/W
14 Driv e 1 Timing Register
Enable (SITR E)
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:1 2, 9:8 f or d rive 0, and use the Slave IDE
Ti ming re gi ster for dr iv e 1 R/W
13:1
2IORDY Samp le Point
(ISP)
The setting of these bits det ermine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY
sam ple p oin t.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
11 Reserved Reserved.
Device: 31 Function: 1
Offset: Primary: 40-41h
Secon dar y: 42 -43h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 449
9—Intel® 6300ESB ICH
10 Fa st No n-Data P IO
(FNDPIO)
Software se ts this re a d/w rite b it to 1 to en able the f ast PIO
ac ce sses for n on Dat a Register a ccesses. W h e n t his b i t is a 1 ,
the timings for PIO cycles to IDE drive r egisters other than
offset 170h or 1F0h will run using PIO data timing s. D efault
for this bit is 0. This mode sh ould on ly be e na b led f or UDMA-
based IDE protocols.
When this b it is set to '1', bit 14 in this regis ter (Drive 1
Timing Register Enable) must be either: '0' to force
equivalent timings for both the master and slave devices, or
'1' with equivalent timings program med in the Slave IDE
Timing re g iste r. Bit s 7 and 3 in this re gis te r mu st be '0 ' in
order to utilize this mode. L ikewise, bits 4 and 0 of this
register must be programmed to '1'; bits 5 and 1 must be
programmed to the same value. The timing parameters must,
of course, be compatib le w ith e a ch of t he de v ice s on th e
channel. The two drives must be programmed for the same
tim in g s because some non -data re gi st e r a ccesses must be
received by both the master and slave devices
simul taneo us ly, and be cause diffe rent s etting s would re sult in
timing s that chang e in the mid d le of some of the non- data
accesses.
Bits 13:12 and bits 9:8 d et ermine the cycle timing s. Bits 6
and 2 do not apply to the non-d ata accesses.Note that the
non-data accesse s are not posted, but that accesses to the
Data register may be posted. Therefore, the non-data
acce sse s may actu ally be limited by the access turn-around
ach ievable on Hub Inte rf a ce rather tha n the RC T tim ing .
9:8 Recovery Time (RCT)
The setting of these bits determines the minimum number of
PCI clocks b e twe en the last IORDY samp le p oint and the
IOR#/IOW# strobe of the n e xt cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
R/W
7Dri ve 1 DMA Timi n g
Enable (DTE1)
0 = D isa b le .
1 = Enable the fast timing mode for DMA transfers only for
this drive . PIO transf er s to th e IDE d ata p ort will run in
compatible timing.
R/W
6Drive 1 Prefetch/Posting
Enable (PPE1)
0 = D isa b le .
1 = Enable Prefetch and posting to the IDE data port for this
drive. R/W
5Drive 1 IORDY S amp le
Point Enable (IE1) 0 = Disa b le IORDY sampling for this drive.
1 = Ena b le IORDY samp ling for this drive . R/W
Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 1
Offset: Primary: 40-41h
Secon dar y: 42 -43h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
450 Order Number: 300641-004US
4Drive 1 Fast Timing Bank
(TIME1)
0 = Accesses to the data port wi ll use com patible timings f or
this driv e.
1 = When this bit =’ 1’ and bit 14 =’0’, acces ses to the d a ta
port will use b its 13:12 for the IORDY samp le po in t, an d
bits 9:8 for the re cover y tim e. When this bit =’1and b it
14 =’1’, ac ce sses to the data port will use the I ORDY
sample p oin t an d re cover time specif ie d in the slave IDE
timing reg ister.
R/W
3Drive 0 DMA Timing
Enable (DTE0)
0 = Disabl e
1 = Enabl e fast timing mode for DMA transfer s only for this
drive. PIO transfers to the ID E data port will run in
compatible timing.
R/W
2Driv e 0 Prefetch/P ostin g
Enable (PPE0)
0 = Disab le pref etch an d po st i ng to t he I DE dat a po rt for t his
drive.
1 = Enabl e prefetch and posting to the IDE data port for this
drive.
R/W
1Drive 0 IORDY Sample
Point Enable (IE0) 0 = Disabl e IORDY sampling is d isa b le d for this drive.
1 = Ena bl e IOR DY s amp lin g for th is d rive. R/W
0Drive 0 Fast Timing Bank
(TIME0)
0 = Accesses to the data port wi ll use com patible timings f or
this driv e.
1 = Accesses to the data port wi ll use bit s 13:12 for the
IORDY sample p oint, an d bit s 9:8 for the re cover y tim e
R/W
Table 342. IDE_TIM—IDE Timing R egister (IDE—D31:F1) (Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 1
Offset: Primary: 40-41h
Secon dar y: 42 -43h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 451
9—Intel® 6300ESB ICH
9. 1.21 Offset 44H : SLV_IDETI M —Slave (Drive 1) IDE
Timing Register (IDE—D31:F1)
Table 343. Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)
Bits Name Description Access
7:6 Secondary Drive 1
IORDY Samp le Point
(SISP1)
Dete rmines the number of PCI clocks b etwe e n IDE IOR# /
IOW# assertio n and the fi rst IORDY samp le point, wh e n th e
acce ss is to drive 1 data port a nd bi t 14 of the IDE timing
register for s ec ondary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
R/W
5:4 Secondary Drive 1
Recovery Time (SRCT1)
Determines the minimum number of PCI clocks between the
last IO RDY samp le po in t and the IOR# /IOW # strobe of the
next cy c le , when the acces s is to dr ive 1 data por t and bi t 14
of the I DE timing reg ister fo r se condary is se t.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
R/W
3:2 Primar y Driv e 1 IORDY
Sample Po i nt (PIS P1)
Dete rmine s the num b er of PCI clock s be twe e n IOR#/IOW#
asse rtion and the first IORD Y sample point, when the acce ss
is to drive 1 d ata port and bit 14 of the IDE timing register for
primary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
R/W
1:0 Primary Drive 1
Rec o ve r y Tim e (P RCT1)
Determines the minimum number of PCI clocks between the
last IO RDY samp le po in t and the IOR# /IOW # strobe of the
next cy c le , when the acces s is to dr ive 1 data por t and bi t 14
of the IDE tim ing regis ter fo r pr imary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
R/W
Device: 31 Function: 1
Offset: 44h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
452 Order Number: 300641-004US
9.1.22 Offset 48h: SDMA_CNT—Synchronous DMA
Control Register (IDE—D31:F1)
Table 344. Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—
D31:F1)
Bits Name Description Access
7:4 Reserved Reserved.
3Secondary Drive 1
Synchronous DMA Mode
Enable (SSDE1)
0 = Disable (default)
1 = En a bl e Synchronous DMA mo de for seco n dary chann e l
drive 1 R/W
2Secondary Drive 0
Synchronous DMA Mode
Enable (SSDE0)
0 = Disable (default)
1 = En a bl e Synchronous DMA mo de for seco n dary drive 0. R/W
1Prima ry Driv e 1
Synchronous DMA Mode
Enable (PSDE1)
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive
1R/W
0Prima ry Driv e 0
Synchronous DMA Mode
Enable (PSDE0)
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive
0R/W
Device: 31 Function: 1
Offset: 48h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 453
9—Intel® 6300ESB ICH
9.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA
Timing Register (IDE—D31:F1)
Table 345. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1) (Sheet 1 of 2)
Bits Name Description Access
15:1
4Reserved Reserved.
13:1
2Secondary Drive 1 Cycle
Time (SCT1)
For Synchronous DMA mod e . The setting of the se bit s
determ i nes the minimum writ e strobe cyc le time (CT). The
DMA RDY#-to-S TOP (RP) time is al so det ermine d by the
sett ing of these b its.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 cl ocks
01 = CT 3 clocks, RP 5 cl ocks
10 = CT 2 clocks, RP 4 cl ocks
11 = Reserved
SCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 cl ocks
10 = CT 2 clocks, RP 8 cl ocks
11 = Reserved
FA ST_SC B1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
R/W
11:1
0Reserved Reserved.
9:8 Secondary Drive 0 Cycle
Time (SCT0)
For Synchronous DMA mod e . The setting of the se bit s
determ i nes the minimum writ e strobe cyc le time (CT). The
DMA RDY#-to-S TOP (RP) time is al so det ermine d by the
sett ing of these b its.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 cl ocks
01 = CT 3 clocks, RP 5 cl ocks
10 = CT 2 clocks, RP 4 cl ocks
11 = Reserved
SCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 cl ocks
10 = CT 2 clocks, RP 8 cl ocks
11 = Reserved
FAST_SCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
R/W
7:6 Reserved Reserved.
Device: 31 Function: 1
Offset: 4A - 4Bh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
454 Order Number: 300641-004US
5:4 Prima ry D rive 1 Cycle
Time (PCT1)
For Synchronous DMA mod e , the setting of these bits
determines the minimum write strobe cy cle time (CT). The
DMARDY#-to-ST OP (RP) time is also determined by the
setting of the se bit s.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 ( 133 MHz clk)
00 = Reserved
01 = CT 3 cl ks, RP 16 cl ks
10 = Reserved
11 = Reserved
R/W
3:2 Reserved Reserved.
1:0 Prima ry D rive 0 Cycle
Time (PCT0)
For Synchrono us DMA mode, the setti ng of these b its
determines the minimum write strobe cy cle time (CT). The
DMARDY#-to-ST OP (RP) time is also determined by the
setting of the se bit s.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 ( 133 MHz clk)
00 = Reserved
01 = CT 3 cl ks, RP 16 cl ks
10 = Reserved
11 = Reserved
R/W
Table 345. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 1
Offset: 4A - 4Bh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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9—Intel® 6300ESB ICH
9.1.24 IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
9. 2 Bus M aster IDE I/O Regi sters (D 31:F1)
The Bus Master IDE function uses 16 bytes of I/O space, allocated through the BMIBA
register, located in Device 31:Function 1 Configuration space, offset 20h. All bus
master IDE I/O space registers may be accessed as byte, word, or DWORD quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no effect, but should not be attempted. The description of the I/O
registers is shown below in Table 347.
Table 346. IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)
Bits Name Description Access
31 Enable Prefetch and
Posting Registers (EPPR)
Un til this bit is set, the PPE1 and PPE0 b its in the IDE Timing
R egiste r (bits 6 and 2 o f off set 40h fo r pri mary, and bits 6 and
2 of offs et 42h for s econdary) are ign ored b y the PIO prefet ch
and posting hardware. Therefore, even if those bits are set,
PIO posting and pre fetching will not occur unti l th is b it is se t.
R/W
30:0 Reserved Reserved.
Device: Function: 1
Offset: 54h Attribute: R/W
Defau lt Value: 00h Size: 32-bit
Table 347. Bus Master IDE I/O Registers
Offset Mnemonic Register Default Type
00 BMICP Command Register Primary 00h R/W
01 Reserved 00h RO
02 BMISP Status Register Primary 00h R/W C
03 Reserved 00h RO
04-07 BMIDP Descriptor Table Pointer Primary xxxxxxxxh R/W
08 BMICS Command Re gister Secondary 00h R/W
09 Reserved 00h RO
0 A BMISS Sta tus Register Secon d a r y 00h R/WC
0B Reserved 00h RO
0C- 0F BMIDS Descriptor Table Pointer Secondary xxxxxxxxh R/W
9—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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9.2.1 BMIC[P,S]—Bus Master IDE Command
Register
Table 348. BMIC[P,S]—Bus Master IDE Command Register
Bits Name Description Access
7:4 Re serv ed Res er ved. Re tur ns ‘0’.
3Read / Write Co ntrol
(RWC)
This bit sets the direction of the bus master transf er: This bit
must NOT be changed when the bus m a s ter fun ctio n is a c tiv e.
0 = Memory re ad s
1 = Mem ory writes
R/W
2:1 Re serv ed Res er ved. Re tur ns ’0’.
0Star t/Stop Bu s M a ste r
(START)
0 = All state in fo rma tion is los t wh e n th is b it is cle a re d .
Master mode operation cannot be stopped and then
resume d . W h e n th is b it is re se t while bus ma ste r
operation is still active (i.e. , the Bus Master IDE Active bit
of the Bus Master IDE Status register for that IDE
channel is set) and the drive has not yet finished its data
transfer (the Inter rupt bit in the Bus Master IDE Sta tus
register f or that ID E chan ne l is not set), th e bus m aste r
co mmand is sai d t o be abor te d and data tr ans ferred fr om
the dr ive may be discar ded i nstea d of being writ t en to
syste m memory.
1 = Enables bus master operation of the controller. Bus
master operation begins when this bit is detected
changing from a zero to a one. The controller will transfer
data between the IDE device and memory only when this
bit is set. Master oper ation may be halte d by writing a '0'
to this bit.
NOTE: This bit is intended to be cleared by software after the
data transfer is comp le te d , as ind icate d by e ither the
Bus M a ste r I DE Active b it b eing cleared or the
Interrupt bit of the Bus Master IDE Status register for
that IDE channel being set, or both. Har dwar e does
not clear thi s bi t aut omatically.
R/W
Device: 31 Function: 1
Offset: Primary : 00h
Secondary: 08h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
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9—Intel® 6300ESB ICH
9.2.2 BMIS[P,S]—Bus Master IDE Status Register
T abl e 34 9. BM I S[ P, S ] —B u s Ma s ter IDE St atu s Reg i st e r
Bits Name Description Access
7 PRD_INT_STS
The I n t e l® 6300ESB ICH sets this bit whe n it completes
execution of a PRD that has its PRD_INT bit set. This bit is
clear ed by software writing a 1 to this bit posit ion. Wh e n this
bit is cleared, the interr upt is cle are d . No te tha t ther e is a
small window where the Intel® 6300ESB ICH completes
exec utio n o f a P RD, but the i nt err u pt s er vic e r o utine does not
clear this bit until the ne xt PRD has co mp le te d. In that case,
there is a sm all pr ob a bi lity that th e inter rup t assoc ia ted with
the subseq ue nt PRD is lost. Software must be written to not
break in this case.
R/W
6 Drive 1 DMA Capable
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device
driver) to indicate that drive 1 for this channel is capable
of DMA tra nsfers, and t ha t t he con troller ha s b een
initialized for optimum performance. The Intel® 6300ESB
ICH does not use this bit. It is intended f or systems that
do not attach BMID E to the PCI bus .
R/W
5 Drive 0 DMA Capable
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device
driver) to indicate that drive 0 for this channel is capable
of DMA tra nsfers, and t ha t t he con troller ha s b een
initialized for optimum performance. The Intel® 6300ESB
ICH does not use this bit. It is intended f or systems that
do not attach BMID E to the PCI bus .
R/W
4:3 Reserved Reserved. Ret urns ’0’.
Device: 31 Function: 1
Offset: Primary : 02h
Secondary: 0Ah Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
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2Interrupt
Software may use this bit to dete rmine if an IDE device has
asserted its interru p t lin e (IRQ 14 f or the Primary chan ne l,
and IRQ 15 f or Secondary ).
0 = This bit is cleared by software writing a '1' to the bit
position . When this bit is cleare d while the inte rrup t is
still ac tive, this bit will re ma in cle a r until another
assertion e dge is d etec ted on the inter rup t line.
1 = Set by the rising edge of the IDE interrupt line,
regardl ess of whe the r or not the inte rrupt is masked in
the 8259 or the internal I/O APIC. When this bit is rea d
as a one, all data transferred from the drive is visible in
syste m memory.
R/WC
1Error
0 = This bit is cleared by software writing a '1' to the bit
position.
1 = This bit is set when the controller encounters a target
abort or master abort when transf er ring data on PCI.
R/WC
0Bus Master IDE Active
(ACT)
0 = This bit is cleared by the Intel® 6300ESB ICH when the
last trans fer for a region is performed, where EOT fo r that
reg ion is s et in the region des cri pto r. It is also clear ed by
the Int el® 6300ES B ICH whe n the S ta rt bit is cleared in
the Command register. When this b it is read as a zero, all
data transferre d f rom the d rive d uring the pr evious bus
master command is visible in system memory , unless the
bus master command was aborted.
1 = Set by the Intel® 6300ESB ICH when the Start bi t is
written to the Command reg ister.
RO
Table 349. BMIS[P,S]—Bus Master IDE Status Register
Bits Name Description Access
Device: 31 Function: 1
Offset: Primary : 02h
Secondary: 0Ah Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 459
9—Intel® 6300ESB ICH
9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table
Pointer Register
Note: When this register is read, the current value of the pointer is returned. The Intel®
6300ESB ICH does NOT return the original base value of the pointer once one or more
descriptors have been executed. This capability is useful for enabling low-cost disk
drives.
Table 350. BMID[P,S]—Bus Master IDE Descrip tor Table Pointer Register
Bits Name Description Access
31:2 Ad dr e ss of Descriptor
Table (ADDR)
Corresponds to A[31:2]. The Des criptor Table must be
DWO R D-aligned. The Descriptor Table mu st not cross a 64 K
boundary in me mory. R/W
1:0 Reserved Reserved.
Device: 31 Function: 1
Offset: Primary : 04h
Secondary: 0Ch Attribute: Read/Write
Defau lt Value: All bits undefined Size: 32-bit
Intel® 6300ESB ICH—9
Intel® 6300ESB I/O Controller Hub
DS November 2007
460 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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10—Intel® 6300ESB ICH
USB UHCI Controllers Registers 10
10.1 PCI Configuration Registers (D29:F0/F1)
Note: Registers that are not shown should be treated as Reserved (see Section 6.2, “PCI
Configuration Map” for details).
Table 351. PC I Configu ration Map (USB—D29 :F0/F1 )
Offset Mnemonic Register Name/
Function Function 0
Default Function 1
Default Type
00-01h VID Vendor ID 8086h 8086 h RO
02-03h D ID Device ID 25A9h 25AAh RO
04-05h CM D Command Register 0000h 0000h R/W
06-07h STA Device S tatus 0280h 0280 h R/W
08h RID Revision ID See NOTE: See NOTE: RO
09h PI Programming Interface 00h 00h RO
0Ah S CC Su b Class Cod e 03h 03h RO
0B h BCC Base Class Co d e 0 C h 0Ch RO
ODh MLT Master Late ncy Tim er 00h 00h R/W
0Eh HTYPE H eader Ty p e 80h 00h RO
20-23h BASE Base Address Register 00000001h 00000001h R/W
2C-2Dh SV ID Subsys te m Vendor ID 00 00 RO
2E-2Fh SID Su bs yste m ID 00 00 RO
3Ch INTR_L N Interrupt Li ne 00h 00h R/W
3Dh INTR_PN Interrupt Pin 01h 02h RO
60h USB_RELNUM USB Release Number 10h 10 RO
C0-C1h USB_LEGKEY USB Legacy Keyboard/
Mouse Control 2000h 2000h R/W
C4h USB_RES USB Resume Enable 00h 00h R/W
NOTE: Refer to the I n tel® 6300ESB I/O Controller Hub Specifi ca tion Update for the most up- t o-
date value of the Revision ID Register.
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
462 Order Number: 300641-004US
10.1.1 Offset 00 - 01h: VID—Vendor Identification
Register
(USB—D29:F0/F1)
10.1.2 Offset 02 - 03 h: DID—Dev ice Identification
Register
(USB—D29:F0/F1)
Table 352. Offset 00 - 01h: VID—Vendor Identification Register (USB—D29:F0/
F1)
Bits Name Description Access
15:0 Vendor ID Value This is a 16-b it value assigned to Inte l. RO
Table 353. Offset 02 - 03h: DID—Device Identification Register (USB—D29:F0/
F1)
Bits Name Description Access
15:0 Devi ce ID Va lu e This is a 1 6-b it value assig n e d to the In te l® 63 00ES B ICH
USB Host Controllers. RO
Device: 29 Function: 0/1
Offset: 00 - 01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Device: 29 Function: 0/1
Offset: 02-03h Attribute: Read-Only
Defau lt Value: Function 0: 25A 9h
Function 1: 25AAh Size: 16-bit
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No v ember 20 07 DS
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10—Intel® 6300ESB ICH
10.1 .3 Offset 04 - 05h: CMD—Command Register
(USB—D29:F0/F1)
Table 354. Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)
Bits Name Description Access
15:1
0Reserved Reserved. RO
9Fast Back -to-back
Enable (FBE) Reserved as0’. RO
8 S ERR# Enab le Reserved as ‘0’. RO
7 Wait Cycle Control Res er ved as ‘0’. RO
6 Parity Error Response Reserv ed as ‘0. RO
5 VGA Palette Snoop Reserved as ‘0’. RO
4Postable Me mory Write
Enable (PMWE) Reserved as0. RO
3Special Cycle Enable
(SCE) Reserved as ‘0. RO
2Bus M a ste r E n able
(BME) Wh en set, the Intel® 6300ES B ICH may act as a master on
the PCI bus f or US B transfers. R/W
1Memory Space Enable
(MSE) Reserved as 0’. RO
0 I/O Space Enable (IOSE)
Th is b it cont rols acc ess to the I /O sp a ce registers.
0 = D isa b le
1 = Enable accesses to the US B I/O registers. The Base
Address register for USB should be programmed before
this bit is set.
R/W
Device: 29 Function: 0/1
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
464 Order Number: 300641-004US
10.1.4 Offset 06 - 07h: STA—Device Status Register
(USB—D29:F0/F1)
10.1.5 Offset 08h: RID—Revision Identification Register
(USB—D29:F0/F1)
Table 355. Offset 06 - 07h: STA—Device Status Register (USB—D29:F0/F1)
Bits Name Description Access
15:1
4Reserved Reserve d as ‘00b’. RO
13 Rece ived M a st e r-A b o rt
Status (RMA) 0 = Software clear s this bit by writing a ’1’ to the bit location.
1 = USB, as a master, g e ne rated a ma ster-a b ort. R/WC
12 Reserved Reserved. Always read as ‘0’. RO
11 Signa led Targ et-Ab ort
Stat us (STA)
0 = Softwar e clear s this bi t by writing a ’1’ to the bit location.
1 = USB function is targ e te d with a transa ctio n tha t the
Intel® 6300ESB ICH terminates with a target abort. R/WC
10:9 DEVSEL # Timin g Statu s
(DEVT)
This 2 -bi t fie ld define s t he timi ng for D EVSEL # asse r tion.
These read only bit s indicate the Inte l® 6300ESB ICH's
DEVSEL# timing when performing a positive decode. The
Intel® 6300ES B ICH generates DEVSEL# with medium timing
for USB.
RO
8Data Parity Error
Detected Re se rv ed as ‘0’. RO
7Fast Back-to-B a ck
Capable Rese rv ed as ‘1 . R O
6User Definable Features
(UDF) Rese rv ed as ‘0’. RO
5 66 MHz Capable Reserved as ‘0. RO
4:0 Reserved Reserved. RO
Table 356. Offset 08h: RID—Revision Identification Register (USB—D29:F0/F1)
Bits Name Description Access
7:0 Revis ion ID Value Refer to the Intel® 6300ESB I/O Controller Hub Spec if icat ion
Update for the mo st up -to-d ate value of the Revision ID
Register. RO
Device: 29 Function: 0/1
Offset: 06 - 07h Attribute: Re ad/Write Clear
Defau lt Value: 0280h Size: 16-bit
Device: 29 Function: 0/1
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descripti on Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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10—Intel® 6300ESB ICH
10.1 .6 Off set 09h: PI—Prog r ammi ng I nterface (USB—
D29:F0/F1)
10.1 .7 Off set 0Ah: SCC—S ub Class Code Register
(USB—D29:F0/F1)
10.1 .8 Off set 0Bh: BCC—Base Class Code R egister
(USB—D29:F0/F1)
10.1.9 Off set 0Dh: MLT—Master Latency T i mer
Note: Since the USB controller is internally implemented with arbitration through the Hub
Interface, not PCI, it does not need a master latency timer. The bits are fixed at ‘0’.
Table 357. Offset 09h: PI—Programming Interface (USB—D29:F0/F1)
Bits Name Description Access
7 :0 Program ming I nte rf a ce 00h = No spe cific registe r le vel p rog ram ming interface
defined. RO
Table 358. Offset 0Ah: SCC—Sub Class Code Register (USB— D29:F0/F1)
Bits Name Description Access
7 :0 Sub Clas s Code 03h = Universal Seria l Bus Host Con troller. RO
Table 359. Offset 0Bh: BCC—Base Cl ass Code Register (USB—D29:F0/F1)
Bits Name Description Access
7:0 B ase Class Code 0Ch = Serial Bus controller. RO
Device: 29 Function: 0/1
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 0/1
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 03h Size: 8-bit
Device: 29 Function: 0/1
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 0Ch Size: 8-bit
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
466 Order Number: 300641-004US
10.1.10 Offset 0Eh: HT YPE—Header Type Register
(USB—D29:F0/F1)
Note: For function 1, this register is hard-wired to 00h. For function 0, bit 7 is determined by
the values in bits 15 and 9 of the function disable register (D31:F0:F2h).
Table 360. Offs et 0D h: ML T— Mas ter La ten cy Time r
Bits Name Description Access
MLT These bits are fixed at ‘0’.
Table 361. Offset 0Eh: HTYPE—Hea der Type Register (USB—D29:F0/F1)
Bits Name Description Access
7 Mult i-Func tion Bi t
Multi-Function Device — RO .
0 = Single-f unc tion device.
1 = Multi-function device.
Since the upper functions in this devi ce can be individually
hidden, this bit is bas e d on t he function - disable bits i n Device
31, Function 0, Offset F2h as follows:
D29: F0 D29:F1 Mult i -Fun cti on
(Bit 15) (Bit 9) Bit
0X 1
X X 1
X 0 1
11 0
6:0 Configuration Layout Hardwire d to 00h, which indicates the sta ndar d PC I
configuration layout.
Device: 29 Function: 0/1
Offset: 0Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 0/1
Offset: 0Eh Attribute: Read-Only
Defau lt Value: FN 0: 80h
FN 1: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
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10—Intel® 6300ESB ICH
10.1.11 Offse t 20 - 23h: BASE—Base Address Regis ter
(USB—D29:F0/F1)
10.1.12 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(USB—D29:F0/F1)
Table 362. Offset 20 - 23h: BASE—Base Address Register (USB—D29:F0/F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:5 Base Address Bits [15:5] cor respond to I/O ad dr ess signals AD [15:5],
respe ctively. This giv es 32 byte s of relocata b le I/O sp ace . R/W
4:1 Reserved Reserved.
0Resource Type Indicator
(RTE) This bit is hardwired to ’1’, indi cating tha t the bas e add ress
field i n this regis t er maps to I/O space. RO
Table 363. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (USB—D29:F0/F1)
Bits Name Description Access
15:0 Subsystem Vendor ID
(SVID)
The SVID register, in combination with the Subsystem ID
(SID) register, enables the operati ng system (OS) to
distingui sh subsyst ems from each othe r. The value re tu rned
by reads to this register is the same as that which was written
by BIOS into the IDE_SVID register.
RO
Device: 29 Function: 0/1
Offset: 20-23h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 29 Function: 0/1
Offset: 2Ch - 2Dh Attribute: Read-Only
Defau lt Value: 00h Size: 16-bit
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
468 Order Number: 300641-004US
10.1.13 Offset 2Eh-2Fh: SID—Subsystem ID (USB—
D29:F0/F1)
10.1.14 Offse t 3 Ch: INTR_LN—Interrupt Line Register
(USB—D29:F0/F1)
Table 364. Offset 2Eh-2Fh: SID—Subsystem ID (USB—D29:F0/F1)
Bits Name Description Access
15:0 Subsystem ID (SID)
The S I D register, in combinat ion w ith the SV I D register,
enab les th e op erat i ng s ys tem ( OS) to disti ngu is h s ubsy stems
from each other. The value returned by reads to this register
is the same as that which was written by BIOS into the
IDE_SID register.
R/WO
Table 365. Offset 3Ch: INTR_LNInterrupt Line Register (USB—D29:F0/F1)
Bits Name Description Access
7:0 Interrupt Line This data is not used by the Intel® 6300ESB ICH. It is to
commu nicate to sof t wa re the inte rrup t line that the inte rrup t
pin is c o nne ct ed to. R/W
Device: 29 Function: 0/1
Offset: 2Eh - 2Fh Attribute: Read-Only
Defau lt Value: 00h Size: 16-bit
Device: 29 Function: 0/1
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
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10—Intel® 6300ESB ICH
10.1.15 Off set 3Dh: INTR_PN— Interrupt Pin R egister
(USB—D29:F0/F1)
10.1.16 Offse t 60h: USB_RELNUM—USB Release Number
Register
(USB—D29:F0/F1)
10.1.17 Offset C0 - C1h: USB_LEGKEY—USB Legacy
Keyboard/
Mouse Control Register (USB—D29:F0/F1)
Note: This register is implemented separately in each of the USB UHCI functions. However,
the enable and status bits for the trapping logic are ORd and shared, respectively,
since their functionality is not specific to any one host controller. See Section 19.6,
“Logical Device 7 (07H): Port 60/64 Emulation for details on the relationship between
the same bits in each of the host controllers. System Software should ensure that the
host controller and an external PCI agent are not simultaneously executing a keyboard
sequence to Port 60h and 64h. This event is not supported, and the results will be
indeterminate.
Table 366. Offset 3Dh: INTR_PN—Interrupt Pin Register (USB—D29:F0/F1)
Bits Name Description Access
7:3 Reserved Reserved. RO
2 :0 Inte rrup t Pin
The values of 01h and 02h, in function 0 and 1, respectively,
indicate to software that the corresponding Intel® 6300 ESB
ICH classic USB contro lle rs drive the INTA# and INTB# PCI
sig nals.
Note that this does not dete rmine the mappin g to the Intel®
6300E S B IC H PIRQ in pu ts. Function 0 will drive PIRQA .
Function 1 will drive PIRQD. Functi on 1 does not use the
corresponding map ping in order to spread the interrupts with
AC’97, w hich h as h istorically bee n ma p p e d to PIRQB
RO
Table 367. Offset 60h: USB_RELNUM—USB Release Number Register (USB—
D29:F0/F1)
Bits Name Description Access
7:0 Serial Bus Releas e
Number 10h = Indicates that the USB contr olle r is com p lia nt with the
USB Specif ication, Release 1.0.RO
Device: 29 Function: 0/1
Offset: 3Dh Attribute: Read-Only
Defau lt Value: Function 0: 01h
Function 1: 02h Size: 8-bit
Device: 29 Function: 0/1
Offset: 60h Attribute: Read-Only
Defau lt Value: 10h Size: 8-bit
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
470 Order Number: 300641-004US
Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control
Register (USB—D29:F0/F1) (Shee t 1 of 3)
Bits Name Description Access
15 SMI Caused by End of
Pass-through (SMIB Y-
ENDPS)
Indicates if the event occurred. No te that ev en when the
corresp ond ing enable b it is not set in b it 7, the n this bit will
still be active . It is up to the SMM code to use the enable b it
to determine the exact cause of the SMI#.
0 = Softwar e cl ear s this bit by writing a ’1’ to the bit location
in an y of the controllers.
1 = Event Occurred
R/WC
14 Reserved Reserved.
13 PCI Interrupt Enable
(USBPIRQEN)
Used to prevent the USB controller from generating an
interrupt due t o transactions on its ports. When disabled, it
will be conf ig u red to gene ra te an SMI using bit 4 of this
register. Default to ’1’ fo r compatibility wi th older US B
software.
0 = Disabl e
1 = Enable
R/W
12 SMI Caused by USB
Interrupt (SMIBYUSB)
Indicate s if a n in te rrupt event oc curre d from this controller.
The interrupt from the controller is taken before the enable in
bit 13 has any effec t to crea te this read-only bit. Note that
even when th e correspo nding enable bi t is n ot set in the Bi t 4,
this b it may still be active. It is up to the SMM code to use the
enable bit to de te rmine the exac t cause of the SMI#.
0 = Softwar e s hould clea r the inte rrup ts th roug h the USB
contr olle rs. Writing a ’1’ to thi s bit will h ave n o eff e ct.
1 = Event Occurred.
RO
11 SMI Caused by Port 64
Write (TRAPBY64W)
Indicates if the event occurred. No te that ev en when the
corre sp on d ing enab le b it is n ot se t in th e b it 3, this b it will
still be active . It is up to the SMM code to use the enable b it
to determine the exact cause of the SMI#. Not e that the
A20Gate Pass- Through Log ic allows specific port 64h writes to
complet e wi thout setting this bit.
0 = Softwar e cl ear s this bit by writing a ’1’ to the bit location
in an y of the controllers.
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D 31:F0, offset F4 h ETR1) is set.
See Section 8.1.37, “Offset F 4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information . Port 64 Writes initiate d fr om a n
extern a l PCI agent will not set this bit.
R/WC
10 SMI Caused by Port 64
Read (TRAPBY64R)
Indicates if the event occurred. No te that ev en when the
corre sp on d ing enab le b it is n ot se t in th e b it 2, this b it will
still be active . It is up to the SMM code to use the enable b it
to determine the exact cause of the SMI#.
0 = Softwar e cl ear s this bit by writing a ’1’ to the bit location
in an y of the controllers.
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D 31:F0, offset F4 h ETR1) is set.
See Section 8.1.37, “Offset F 4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information. Port 64 Reads ini tia te d from an
extern a l PCI agent will not set this bit.
R/WC
Device: 29 Function: 0/1
Offset: C0-C1h Attribute: Read/Write
Defau lt Value: 2000h Size: 16-bit
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9SMI Caus e d by Port 60
Write (TRAPBY60W)
Indicates if the event occurred. Note that even when the
corre spond ing e n ab le bit is not se t in the bit 1, this bit wi ll
st ill be active. It is up to the SMM code to use the e na b le bit
to dete rmine the exact caus e of the SM I#. N ote that the
A20Gate Pass- Throug h Logic allows specific port 64h writes to
c omple te witho u t s etting th is bi t.
0 = Sof twa re cle ars this bit by writ ing a ’1’ to the bit locati on
in any of the cont rollers.
1 = Event Oc curred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
See Section 8.1.37, “Offset F4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information. Port 60 Writes initiate d from an
exte rna l PCI ag e n t will not se t this bit.
R/WC
8SMI Caus e d by Port 60
Read (TRAPBY60R)
Indicates if the event occurred. Note that even when the
corre spond ing e n ab le bit is not se t in the bit 0, this bit wi ll
st ill be active. It is up to the SMM code to use the e na b le bit
to dete rmine the exact caus e of the SMI#.
0 = Sof twa re cle ars this bit by writ ing a ’1’ to the bit locati on
in any of the cont rollers.
1 = Event Oc curred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
See Section 8.1.37, “Offset F4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more inform ation. Por t 6 0 Reads in itiate d from an
exte rna l PCI ag e n t will not se t this bit.
R/WC
7SMI at End of Pass-
through Enable
(SMIATENDPS)
May need to cause SMI at the end of a pass-through. May
occur when an SMI is generated i n the middle of a pass
throug h and ne ed s to be serv iced later.
0 = D isa b le
1 = Enable
R/W
6Pa ss -Thr ou gh S tate
(PSTATE)
0 = Whe n softwa re nee ds to rese t this bit, it should set bit 5
in all of the ho st controllers to 0.
1 = Indicates tha t th e sta te ma chine is in the mi ddle of a n
A20GATE pass- t hrou g h se quence .
RO
5A20Gate Pass-Through
En abl e (A20PASSEN)
0 = D isa b le .
1 = A llows A20GATE sequ e n ce Pass -T h rough function. A
specif ic cycle seque n ce in vo lvi n g wr ite s to p ort 60h a nd
64h does not result in the setting of the SMI status bit s.
R/W
4SMI on USB IRQ Enable
(USBSMIEN) 0 = Disable
1 = USB in te rrup t will cause an SMI event. R/W
3SMI on Port 64 Writes
Enable (64WEN)
0 = D isa b le
1 = A ’1’ in bit 11 will cause an SM I event.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
See Section 8.1.37, “Offset F4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information. Port 64 Writes initiate d from an
exte rna l PCI ag e n t will not se t this bit.
R/W
Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control
Register (USB—D29:F0/F1) (Sheet 2 of 3)
Bits Name Description Access
Device: 29 Function: 0/1
Offset: C0-C1h Attribute: Read/Write
Defau lt Value: 2000h Size: 16-bit
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10.1.18 Offse t C4h: USB_R ES—USB Resume Enable
Register (U SB—D29:F0/F1)
Note: This register is in the Resume Well.
2SMI on Port 64 R eads
Enable (64R EN )
0 = Disabl e
1 = A ’1’ in bit 10 will ca use an SMI event.
NOTE: If bit 7 of the ETR1 (D 31:F0, offset F4 h ETR1) is set.
See Section 8.1.37, “Offset F 4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information. Port 64 Reads ini tia te d from an
extern a l PCI agent will not set this bit.
R/W
1SMI on Port 60 Wr ites
Enable (60 W EN)
0 = Disabl e
1 = A ’1’ in bit 9 will ca use an SMI event.
NOTE: If bit 7 of the ETR1 (D 31:F0, offset F4 h ETR1) is set.
See Section 8.1.37, “Offset F 4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information . Port 60 Writes initiate d fr om a n
extern a l PCI agent will not set this bit.
R/W
0SMI on Port 60 R eads
Enable (60R EN )
0 = Disabl e
1 = A ’1’ in bit 8 will ca use an SMI event.
NOTE: If bit 7 of the ETR1 (D 31:F0, offset F4 h ETR1) is set.
See Section 8.1.37, “Offset F 4: ETR1—PCI-X
Extended Features Register (LPC I/F—D31:F0)” for
more information. Port 60 Reads ini tia te d from an
extern a l PCI agent will not set this bit.
R/W
Table 369. Offset C4h: USB_RES—USB Resume Enable Register (USB—D29:F0/
F1)
Bits Name Description Access
7:2 Reserved Reserved.
1PORT1EN
0 = The US B con troller will not look at this port for a wake up
event.
1 = The US B con troller will m on itor th is p ort for remot e
wakeup and connect /d i sconnect event s
R/W
0PORT0EN
0 = The US B con troller will not look at this port for a wake up
event.
1 = The US B con troller will m on itor th is p ort for remot e
wakeup and connect /d i sconnect event s.
R/W
Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control
Register (USB—D29:F0/F1) (Shee t 3 of 3)
Bits Name Description Access
Device: 29 Function: 0/1
Offset: C0-C1h Attribute: Read/Write
Defau lt Value: 2000h Size: 16-bit
Device: 29 Function: 0/1
Offset: C4h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
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10.2 USB I/O Register s
Some of the read/write register bits that deal with changing the state of the USB hub
ports function so that, on read-back, they reflect the current state of the port, and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A Host
Controller Reset, Global Reset, or Port Reset will immediately terminate a transfer on
the affected ports and disable the port. This affects the USBCMD register, bit [4] and
the PORTSC regi sters, bits [12,6,2]. See individual bit descriptions for more detail.
10.2.1 Offset 00 - 01h: USBCMD—USB Command Register
Note: The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed. The table
following the bit description provides additional information on the operation of the
Run/Stop and Debug bits.
Table 370. USB I/O Registers
Offset Mnemonic Register Default Type
00-01 USBCMD USB Com mand Register 0000h R/W *
02-03 USBS TA USB Status Register 0020h R/WC
04-05 USBINTR Interrupt Enab le 0000h R/W
06-07 FRNUM Frame N umb e r 0000h R/W (see NOTE:)
08-0B FRBASEADD Frame List Base Address Undefined R/W
0C S OFM OD S tart of Frame M od ify 40h R/W
0D-0F Reserved 0 RO
10-11 PO RTSC0 Port 0 Status/C ontrol 0080h R/W C (see
NOTE:)
12-13 PO RTSC1 Port 1 Status/C ontrol 0080h R/W C (see
NOTE:)
14-17 Reserved 0 RO
NOTE: These regist ers are WORD writable only. Byte writes to these regi sters have
unpredic ta bl e effec ts.
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Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 1 of 3)
Bits Name Description Access
15:7 Reserved Reserved.
8 Loop B ack Test Mode
0 = Dis abl e loop back test mode.
1 = The Intel® 6300ESB ICH is in loop back test mode. When
both ports are connected together, a write to one port will
be seen on the other p ort, a nd the data will be sto re d in
I/ O of fset 18h.
R/W
7 Max Packet (MAXP)
This bit selec ts t h e ma ximu m p a cke t size th a t ma y be u se d
for full-speed bandwidth reclamation at the end of a frame.
This value is used by th e Ho st Controller to de te rmine
whethe r it sh ould initia te a noth e r tran saction ba se d on the
time remaining in the SOF counter. Use of reclama tion
packets lar ger than th e prog rammed size will cau se a B a bble
erro r when ex ec u ted dur ing the cr itic al windo w at fram e end.
The Babble error re su lts in the off e n di ng en d p oin t b e ing
stalled . Software is re sp on sible for en suring th at any p a cket
that could be executed under bandwidth reclam ation be
within thi s size limit.
0 = 32 bytes
1 = 64 bytes
R/W
6 Configure Flag (CF)
This bit has no effect on the hardware. It is provided only as a
sem apho re serv ice fo r softwar e.
0 = Indicates that software has not completed host controller
configuration.
1 = HCD software sets this bit as the last action in its process
of configuring the Ho st Cont roller.
R/W
5Software Debug
(SWDBG)
The SWDBG bit must only be manipulated when the controller
is in the stopped state. This may be determined by checking
the HCHalted bit in the US BSTS register.
0 = Normal Mode.
1 = Debug mode. In SW Debug mode, the Host Controller
clears the Run/Stop bit afte r the comp letion of eac h US B
trans action. The next transaction is exec uted when
software sets the Run/S top bi t bac k to ‘1’.
R/W
4Force Global Resum e
(FGR)
0 = Softwar e resets this bit to ’0’ after 20 ms has elapsed to
stop sending the Global Resume signal. At that time, all
USB devices should be ready for bus activity. The ’1’ to ’0’
tr ansition causes the port to send a low speed EOP signal.
This bit wil l re main a ’ 1’ u ntil th e EOP h as complete d.
1 = Host Controller sends the Global Resume signal on the
USB and sets this bit to ’1’ when a resume event
(connect, di sconnect, or K-state) is dete cted while in
gl ob al suspend mode.
R/W
Device: 29 Function: 0/1
Offset: 00-01h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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3Enter Global Suspend
Mode (EGSM)
0 = Sof twa re re sets this bit to ’0’ to come out of Glob a l
Suspend mode. Software writes this bit to ’0’ at the same
time that Force Glob a l Resume (bit 4) is writte n to ’0’ or
after writing bit 4 to 0.
1 = Hos t Contr olle r ent ers the Global Suspend mode . No USB
transactions occur during this time. The Host Controller is
able to receive resume signals from USB and interrupt
the system. Software must ensure that the Run/S top bit
(bit 0) is clea red prior to settin g th is b it.
R/W
Tab l e 37 1. Of fs et 00 - 01h : US B C MD US B Com m a nd Re g is te r (S he e t 2 of 3)
Bits Name Description Access
Device: 29 Function: 0/1
Offset: 00-01h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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2 Glob al Res et (GRESET)
0 = This bit is reset by the software after a minimum of 10
ms has elapsed as specified in Chapter 7 of the USB
Specification.
1 = Global Reset. The Host Controller sends the glo bal rese t
signa l on th e USB and then re se ts all its log ic, in cluding
the in ternal hub r egisters. The hub registers are reset to
their po we r on sta te . Ch ip Hardware Reset ha s th e sa me
effect as Global Reset (bit 2), except that the Host
Controlle r d oe s not send the Glo bal Reset on USB.
R/W
1Host Controller R eset
(HCRESET)
The effec ts of HCRESET on Hub registers are sli ghtly diffe rent
from Chip H ard wa re Reset and Gl ob al US B Reset. The
HCRESET affe cts bits [8,3:0] of the Port Status an d Control
Register (PORTSC) of each po rt. HCRES ET re sets the state
mac hin e s of t he Host Controller including the Connect/
Disconnect state machine (one for each port). When the
Connect/Disconne ct sta t e machine is re se t, t he ou tput that
signals connect/disconnect are negated to 0, effectively
signaling a di sconnect, even if a devi ce is atta che d to the
port. This vi rtu a l d i sconne ct ca u ses the port to be disa bled.
Thi s di sco n nect and disa bli ng o f th e po rt ca use s bit 1
(connec t status chan g e ) and bit 3 (p ort e na b le /d isab le
change) of the PORTSC to get set. The disconnect also causes
bit 8 of PORTSC to reset. Ab out 64 b it time s af te r HCRES E T
goes to ‘0’, the connect and l ow-speed detect will take place,
and bit s 0 and 8 o f the POR T SC wil l change accor di ngl y.
0 = Reset by the Host Controller when the reset process is
complete.
1 = Reset. When this b it is set, the H ost Controller mod ule
resets its inte rnal time rs, counters, state machines, etc .
to their initial v alue. Any transaction currently in progress
on USB is immediately te rminate d.
R/W
0 Run/S top (RS)
When set to ‘1’, the Intel® 6300ES B ICH pr ocee d s with
exec ution of th e schedu le . The Int el® 6300ESB ICH continues
execution a s long a s this b it is se t. W h e n th is bit is cle are d,
the Intel® 6300ESB ICH completes the current transaction on
the USB and then halts. The HC Halted bit in the status
register indicates when the Host Controller has finished the
transaction and has entered the stopped state. The Host
Controller clears this bit when the following fatal errors occur:
consistency check failure , PCI Bus errors.
0 = Stop
1 = Run
NOTE: This bit should only be cleared when there are no
active Transaction Descriptors in the executable
sch edul e or software w ill re se t the host con troller
prior to setting this bit again.
R/W
Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 3 of 3)
Bits Name Description Access
Device: 29 Function: 0/1
Offset: 00-01h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1),
the single stepping software debug operation is as follows:
To Enter Softwar e Debug Mode:
1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to ‘0’.
2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to ‘1.
3. HCD sets up the correct command list and Start Of Frame v alue for starting point in
the Frame List Single Step Loop.
4. HCD sets Run/Stop bit to ’1’.
5. Host Controller executes next active TD, sets Run/Stop bit to ‘0’ and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
(HCHalted = 1).
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to
end Software Debug mode.
8. HCD ends Software Debug mode by setting SWDBG bit to ‘0’.
9. HCD sets up normal command list and Frame List table.
10.HCD sets Run/Stop bit to ‘1’ to resume normal schedule execution .
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts.
When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the
HCHalted bit in the USBSTS register (bit 5) is set.
The SW Debug mode skips over inactive TDs and only halts after an active TD has been
executed. When the last active TD in a frame has been executed, the Host Controller
waits until the next SOF is sent and then fetches the first TD of the next frame before
halting.
This HCHalted bit may also be used outside of Software Debug mode to indicate when
the Host Controller has detected the Run/Stop bit and has completed the current
transaction. Outside of the Softw are Debug mode, setting the Run/Stop bit to ’0’
Table 372. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0)
Operation
SWDBG
(Bit 5) Run/Stop
(Bit 0) Description
00
When executing a command, the Host Controller completes the
command and then stops. The 1.0 ms frame counter is reset and
command list execution resumes from start of frame using the fram e
list pointer selected by the current value in the FRNUM register. (While
Run/Stop = 0, the FRNUM register may be reprogrammed).
01
Execution of the command list resumes from Start Of Frame using the
fr ame list pointer selec ted by the current v alue in the FRNUM register.
The Host Contro ller remains running until the Run/Stop bit is cleared
(by soft wa re or hardware).
10
When executing a command, the Host Controller completes the
command and then s tops and the 1 .0 ms frame counter is frozen at
its current value. All statuses are pr eserved. The Host Controller
begins execution of the command list from where it left off when the
Run/Stop bi t is set.
11
Execution of the c ommand list resumes from where the previous
exec u tion stopped. The Ru n/S top bit is set to ’0’ by the Host
Controller when a TD is being fetched. This causes the Host Controller
to stop again after the execution of the TD (single step). When the
Host Controller has com pleted execution, the HC Halted bit in the
Status Register is set.
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al way s r esets t he SOF c ounte r so tha t when the Ru n/St op bit is set, the Hos t Con trol l er
starts over again from the frame list location pointed to by the Frame List Index (see
FRNUM Register description) rather than continuing where it stopped.
10.2.2 Offset 02 - 03h: USBSTA—USB Status Register
Note: This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to ‘0’ in this register by writing a ‘1’ to it.
Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 1 of 2)
Bits Name Description Access
15:6 Reserved Reserved.
5HCHalted
0 = Softwar e res et s this bit to ’0’ by writing a ’1’ to the bit
position.
1 = The Host Controll er has stoppe d executing as a result of
the Run/Stop bit bei ng set to 0, eith er by software or b y
the Host Controlle r hardware (debug mode or an internal
error). Default.
R/WC
4Host Controller Process
Error
0 = Softwar e res et s this bit to ’0’ by writing a ’1’ to the bit
position.
1 = The Host Controll er has detec ted a fatal error. This
indica te s t ha t th e H ost Controller suf f er ed a con sistency
check failure while processing a Transfer Descriptor. An
example of a consistency chec k failure woul d be finding
an illegal PID field while processing the packet header
portion of the TD. When th is error occurs, the Host
Contro lle r cle a rs th e Run/Stop bit in the Command
register to prevent further sc hedule exec ution. A
hardware inte rrup t is ge ne rated to the syste m.
R/WC
3Host System Error
0 = Softwar e res et s this bit to ’0’ by writing a ’1’ to the bit
position.
1 = A serious error occu rre d during a hos t sys tem acce ss
involving the Ho st Controller m odule. In a PCI syste m,
conditio ns that set this bit to ’1’ inc lude PCI Parity error,
PCI Master Ab ort, a nd PCI Tar get A b ort. W he n this e rror
occ urs, the Host Contr o ller clears the Run /St o p bit in the
Command register to prevent further execut ion of the
scheduled TDs. A hard ware inte rrup t is g en erated to the
system.
R/WC
Device: 29 Function: X
Offset: 02 - 03h Attribute: Rea/Write Clear
Defau lt Value: 0020h Size: 16-bit
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10.2.3 Of fset Base + (0 4 - 05h): USBINTR— Inte rrupt
Enable Register
Note: This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Fatal errors (Host Controller Processor Error-bit 4, USBSTS
Register) cannot be disabled by the host controller. Interrupt sources that are disabled
in this register still appear in the Status Register to allow the software to poll for
events.
2Resum e D e tect
(RSM_DET)
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
position.
1 = The H ost Contro lle r re ceived a “RES UME signal fr om a
USB device. This is only valid when the Host Controller is
in a global suspend state (bit 3 of Command register =
1).
R/WC
1 USB Error Interrupt
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
position.
1 = Completion of a USB transa ction resulted in an error
condition (e .g ., er ror co unter und erfl ow). W he n the TD
on which the error interrupt occurred also had its IOC bit
set, both this bit and B it ’0’ are set .
R/WC
0 USB Interrup t (USBINT)
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
position.
1 = The Host Controller se ts this bit whe n the c ause of an
interrupt is a comple tion of a USB transaction whose
Transfer Descriptor h ad its IOC bit set. Also set when a
sho rt pac ket is detected (a ctua l le ngth field in T D is les s
than maximum length fi eld in TD) and short packet
detec tion is enabled in t ha t TD.
R/WC
Tab l e 37 4. Of fs e t Ba se + (04 - 05h ): US BI NTR— I nte r r upt En ab le Re gis t e r (S hee t
1 of 2)
Bits Name Description Access
15:5 Reserved Reserved.
4 Scratchpad Scratchpad. R/W
3Short Packet Interrup t
Enable 0 = D isa b le d .
1 = Enabled . R/W
Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: X
Offset: 02 - 03h Attribute: Rea/Write Clear
Defau lt Value: 0020h Size: 16-bit
Device: 29 Function: X
Offset: Base + (04 -05h) Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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2Interrup t On Complete
(IOC) Ena b le 0 = Dis abl ed.
1 = Enabled. R/W
1Resume I nte rru p t
Enable 0 = Disabl ed.
1 = Enabled. R/W
0Timeout/CRC Interrupt
Enable 0 = Disabl ed.
1 = Enabled. R/W
Table 374. Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register (Sheet
2 of 2)
Bits Name Description Access
Device: 29 Function: X
Offset: Base + (04 -05h) Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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10.2.4 Offset Base + (06 - 07h): FRNUM—Frame Number
Register
Note: Bits [10:0] of this register contain the current frame number included in the frame SOF
pac ket . Th is r egist er re fl ects the count v a lue o f the inte rna l fr ame numb er c oun ter. Bit s
[9:0] are used to select a particular entry in the Frame List during scheduled execution.
This register is updated at the end of each frame time.
Note: This register must be written as a word. Byte writes are not supported. This register
cannot be written unless the Host Controller is in the ST OPPED state as indicated by the
HCHalted bit (USBSTS register). A write to this register while the Run/Stop bit is set
(USBCMD register) is ignored.
10.2.5 Offset Base + (08 - 0Bh): FRBASEADD—Frame List
Bas e Address
Note: This 32-bit register contains the beginning address of the Frame List in the system
memory. HCD loads this register prior to starting the schedule execution by the Host
Controller. When writt en, only the upper 20 bits are used. The lower 12 bits are written
as ’0’ (4-Kbyte alignment). The contents of this register are combined with the frame
number counter to enable the Host Controller to step through the Frame List in
sequence. The two least significant bits are always 00. This requires DWORD alignment
for all list entries. This configuration supports 1024 Frame List entries.
Table 375. Offset Base + (06 - 07h): FRNUM—Frame Number Register
Bits Name Description Access
15:1
1Reserved Reserved.
10:0 Frame List Current
Index/Frame Number
Provides the frame number in the SOF Frame. The value in
this register increments at the end of each time frame
(approximately every 1 ms). In addition, bits [9:0] are used
for the Frame List cu rre nt ind e x an d correspond to memory
address signal s [ 11 :2 ].
R/W
Table 376. Offset Base + (08 - 0Bh): FRBASEADD—Frame List Base Address
Bits Name Description Access
31:1
2Base Address These bits corresp on d to me mory add ress signals [31:12],
respectively. R/W
11:0 Reserved Reserved.
Device: 29 Function: X
Offset: Base + (06 -07h) Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Device: 29 Function: X
Offset: Base + (08-0Bh) Attribute: Read/Write
Defau lt Value: Undefined Size: 32-bit
10—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 482
10.2.6 Offse t Base + OCh: SOFMOD—Start of
Frame Modify Register
Note: This 1-byte register is used to modify the value used in the generation of SOF timing on
the USB. Only the 7 least significant bits are used. When a new value is written into
these 7 bits, the SOF timing of the next frame will be adjusted. This feature may be
used t o adjust out any offset from the clock source that gener ates the clock that drives
the SOF counter. This register may also be used to maintain real-time synchronization
with the rest of the system so that all devices have the same sense of real time. Using
this register, the frame length may be adjusted across the full range required by the
USB specification. Its initial programmed value is system dependent based on the
accuracy of hardwar e USB clock and is initialized by system BIOS. It may be
reprogrammed by USB system software at any time. Its value will take effect from the
beginning of the next frame. This register is reset upon a H ost Controller Reset or
Global Reset. Software must maintain a copy of its value for reprogramming when
necessary.
Table 377. Offset Base + OCh: SOFMOD—Start of Frame Modify Register
Bits Name Description Access
7 Reserved Reserved.
6:0 SOF Timing Value
Guidelines for the modification of frame time are contained in
Chapte r 7 of th e USB S pecification. The SOF cyc le time
(number of SO F counte r clock per iod s to g en erate a SO F
frame length) is equal to 11936 + value in this field. The
default value is decimal 64 whic h give s a SOF cycle time of
12000. For a 12 MHz SOF counter clock input, this produces a
1 ms Frame period. The following table indicates what SOF
Ti ming V a l ue to prog r am into this field fo r a certain fra m e
period.
Frame Length
(# 12 MHz Clocks) SOF Reg. Value
(decimal) (decimal)
11936 0
11937 1
. .
. .
11999 63
12000 64
12001 65
. .
. .
12062 126
12063 127
R/W
Device: 29 Function: X
Offset: Base + (0Ch) Attribute: Read/Write
Defau lt Value: 40h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 483
10—Intel® 6300ESB ICH
10.2.7 P OR TSC[0,1]—Port Status and Control Register
Note: For Function 0 this applies to the Intel® 6300ESB ICH USB ports 0 and 1; for Function
1 this applies to the Intel® 6300ESB ICH USB ports 2 and 3.
After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a
port are: no device connected, Port disabled, and the bus line status is 00 (single-
ended ‘0’).
Table 378. PORT SC[0,1]— Port Status and Control Register (Sheet 1 of 2)
Bits Name Description Access
15:1
3Reserved Reserved. RO
12 Suspend
This bit should not b e written to a ’1’ when a glo bal su spe nd
is active (bit 3 =1 in the USBCMD register). Bit 2 and bit 12 of
this register define the hub states as follows:
Bit s [12, 2] Hub State
X 0 Disable
0 1 Enable
1 1 Susp en d
When in suspend state, downstream propagation of data is
block ed on this po rt, excep t for single-en ded ’0 ’ res ets (g lobal
reset and port reset). The blocking occur s at the end of the
current transaction if a transaction was in progress when this
bit was writ te n to ‘1’. In the suspe nd state , the po rt is
sensitiv e to resume detection. N ote that the b it status does
not change until the port is s usp en ded and that the re may be
a delay in suspending a port when there is a transaction
cur re n tly in progr e ss on t he USB.
1 = Port in su spend st a te.
0 = Por t n ot in suspend sta te .
NOTE: N ormally, if a transaction is in prog re ss when th is b it
is set, the port will be suspe nded when the current
transaction complete s. H owe ver, in the ca se of a
specif ic error condition (out transaction with bab b le ),
the Intel® 6300ESB ICH may issue a start-of-frame,
then suspend the port.
R/W
11 Overcurrent Indicator
Set by ha rd wa re .
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Over current pin has gone from inactive to active on this
port.
R/WC
10 Overcurrent Active This bit is set and c leared by hardware.
0 = Indicates that the overcurrent pin is inactive (high).
1 = Indicates that the overcurrent pin is active (low). RO
9Port Reset
0 = Port is not in Reset.
1 = Port is in R eset. When set, the port is disabled and sends
the USB Reset signaling . RO
8Low Speed Device
Attached (LS)
Writes have no effect.
0 = Full-speed d evice is attache d.
1 = Lo w-spe e d de vic e is atta che d to this port. RO
Device: XFunction: X
Offset: Port 0/2: 10-11h
Port 1/3: 12-13h Attribute: Read/Write
Defau lt Value: 0080h Size: 16-bit
Intel® 6300ESB ICH—10
Intel® 6300ESB I/O Controller Hub
DS November 2007
484 Order Number: 300641-004US
7 Re serv ed Res er ved. Alw ays read as ‘1’. RO
6Resume Detect
(RSM_DET)
Software se ts this bit to a ’1’ to dr ive resume signaling . The
Host Controller sets this bit to a ’1’ when a J-to-K transition is
detec te d for at le a st 32 m icroseconds while t he port is in th e
Suspend state. T he Intel® 6300ESB ICH will then reflect the
K-state back onto the b us as l ong as t he bit r emai ns a ‘ 1’ and
the port is stil l in th e suspen d state (bit 12, 2 are ‘11’).
Writing a ’0’ (from ‘1’) causes the port to send a low-speed
EOP. Th is b it will re main a ’1’ until the EOP has comple te d .
0 = No resume (K-state) det ecte d /dr iven on port.
1 = Resume detected/driven on port.
R/W
5:4 Line Status
These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’
logical lev el s. These bits are used for f ault dete ct an d
recovery as well as for USB diagnostics. This field i s updated
at EOF2 time (See Chapter 11 of the USB Specification).
RO
3Port Enable /Disable
Change
For the root hub, this bit gets set only when a port is disabled
due to disconne ct on th at por t or due to the ap pr op ria te
conditions e xisting at the EOF2 p oint (S e e Chapter 11 of the
USB Specification).
0 = No change. Software clears this bit by writing a ‘1’ to the
bit location.
1 = Port enabled/disabled status has changed.
R/WC
2Port Enabled/Disabled
(PORT_EN)
Ports may be enabled by host s oftware only. Ports may be
disabl ed by either a fault condi ti o n ( dis conn ec t event or o ther
fault condition) or by host software . N ote tha t the bit status
does not c hange until the p ort s tate actually change s and that
there ma y be a delay in disab ling or enab ling a port whe n
there is a trans action curren tly in progre ss o n th e USB.
0 = Disabl e
1 = Enable
R/W
1 Connect Status Change
Indi cat e s th at a chan ge h a s occurr ed in t he port’s Curren t
Connec t Statu s (see bit 0). The hub device sets this bit for
any chan g e s t o the port device con n e ct status even when
syste m softwa re h a s no t cle a re d a conne ct status change. If,
for example, the insertion status changes twice b ef ore
syste m softwa re h a s cle a re d t he ch a nged con dition, hub
hardware will be setting an already-set bit (i.e., the bit will
remain s et ). H owever, the hub transfe rs the chan g e b it only
once when the Host Controller requests a data transfer to the
Stat us Cha n g e e n dpoint. Syste m softwar e is re sp on sible for
determining st at e change h istory in su ch a ca se.
0 = No change. Software clears this bit by writing a ’1’ to the
bit location.
1 = Change in Current Connect Status.
R/WC
0 Current Connec t Statu s
This value reflects the current state o f the port and may not
correspond directly to the event t hat caused the Connect
Status Change bit (Bit 1) to be set.
0 = No device is present.
1 = Device is present on port.
RO
Table 378. PORTSC[0,1]—Port Status and Control Register (Sheet 2 of 2)
Bits Name Description Access
Device: XFunction: X
Offset: Port 0/2: 10-11h
Port 1/3: 12-13h Attribute: Read/Write
Defau lt Value: 0080h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 485
11—Intel® 6300ESB ICH
USB EHCI Controller Registers
(D29:F7) 11
11.1 USB EHCI Co nfi guratio n R egiste r s (D29:F7 )
Note: Registers that are not shown should be treated as Reserved (see Section 6.2, “PCI
Configuration Map” for details).
Offset Reg. Name/Function Default Value Type
00-01h Vend or ID 8086h RO
02-03h Device ID 25A Dh RO
04-05h Command Re g ister 0000h RW
06-07h Device Status 0290h RW
08h Revis ion ID (RID) See NOTE: RO
09h Programming Inte rf ace 20h RO
0A h Sub Clas s Co d e 03h RO
0Bh Base Class Code 0Ch RO
0Dh Ma ster Latency T imer 00h RO
0Eh Heade r Type 0 0h RO
10-13h Memo ry Bas e Addr e ss Regist er 00000000h RW
2C- 2 Dh Subsystem Vendor ID XXX Xh RW-Special
2E- 2Fh Subsys tem ID XXX Xh RW-Specia l
34h Capabilities Pointer 50h RO
3Ch Interrupt Line 00h RW
3Dh Interrupt Pin 04h RO
50h Power Ma na g e me nt Ca p a b ility
ID 01h RO
51h Next Item Ptr 58h RO
52-53h Powe r M an ag e me nt Ca p a b ilitie s C9C2h RO-Special
54-55h Powe r Manage ment Control/
Status 0000h RW
57h Power Manag eme nt Dat a 00h RO
58 h De bug Port Capabili t y ID 0Ah RO
59h Next Item Pointer #2 00h RO
5A-5Bh De bu g Port Base Offset 2080h RO
60h U SB Release Number 20h RO
61h Frame Length Ad jus tment 2 0h RW
62-63h Powe r Wake Capabilitie s 00 7Fh R W
64-65h Classic USB Override 0000 RO
NOTE: Refe r to the Inte l® 6300ESB I/O Controller Hub Spec if icat ion Update for the most up-
to-date value of t he Revision ID Register.
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
486 Order Number: 300641-004US
11.1.1 Offse t 04 - 05h: Command Register
66-67h Reserved 0 RO
68-6Bh USB E H CI Le g a cy Support
Exte nded Cap a b ility 00000001h Read/Write
6C-6Fh USB EH CI Le g a cy Support
Control/Status 00000000h Read/Write
70-73h Intel Specific US B EHCI SMI 00000000h Read/Write
74-7F Reserved 0 Read Only
8 0h Access Contro l 00h Read / Write
81-F Fh R eser ved 0 R ead Only
DCh HS_ Ref_V_USB HS Reference
Voltage Register 00000000h Read/Write
Table 379. Offset 04 - 05h: Command Register
Bits Name Description Access
15:0 Reserved Reserved.
9Fast Back-to-B a ck
Enable (FBE) Res er ved a s 0. RO
8 SERR# Enable
0 = Dis abl es the En ha nce d Ho st Controllers (EHC’s)
capa b ili t y t o genera te a n SERR# .
1 = The EHC is capable of generating internally SERR# when
it receives a completion status other than “successful” for
’1’ of its DMA-in itia te d me mory reads on th e Hu b
Interfa ce (a nd subs e qu ently on its interna l inte rf ace).
R/W
7 Wait Cyc le Control Reserved as 0. RO
6 Parity Error Res ponse Reserved as 0. RO
5 VGA Palette Snoop Reserv e d as 0. RO
4Postable Memory Write
Enable (PMWE) Reser ved as 0 . RO
3Spe cia l Cy cle E na b le
(SCE) Rese rv ed as 0. R O
2Bu s M a st e r En a b l e
(BME)
0 = Disa bl es this f un ctionality.
1 = Enables the Int el ® 6300ESB ICH. May act as a master on
the PCI bus for USB transfers. R/W
1Memory Space Enable
(MSE)
0 = Disa bl es this f un ctionality.
1 = Enables accesses to the USB EHC I registers. The Base
Address register for USB EHCI should be programmed
before this bit is set
R/W
0 I/O Space Enable (IOS E) Reserved as 0. RO
Offset Reg. Name/Function Default Value Type
NOTE: Refer to th e Intel® 6300ES B I/O Controller Hub Spe cification Update for t h e mo s t up-
to-date value o f the Revision ID Register.
Device: 29 Function: 7
Offset: 04-05h Attribute: Read Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 487
11—Intel® 6300ESB ICH
11.1.2 Offset 06 - 07h: Device Status
Table 380. Offset 06 - 07h: Device Status
Bits Name Description Access
15 Dete cte d Parity Error
(DPE)
This bit is set b y the Inte l® 6300ESB ICH when ever a pa rity
error is seen on the i nte rn al interf a ce to the US B host
controller due to a parity error on Hub Interface, regardless
of the setting of bit 6 or bit 8 in the Command reg ister or any
other cond ition s. Software clea rs this bit by writing a ‘1’ to
this bit location. Note that the P arity Error Response bit in the
HL-to-PCI bridge should be set in ord e r fo r th e Hub Inte rf ace
parity er rors t o be forwa rd e d to th e USB2 in te rface. This is a
resu lt of the point-to-point nature of the Hub Inte rf ace
R/W
14 Signa l ed Syst em Erro r
(SSE)
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bi t is set by the Intel® 6300 ESB I CH whenever it
signals SERR # (inte rnally ). The SER_EN bit (bit 8 of the
Command Register) must be ’1’ for this bit to be set.
R/W
13 Rece ived M a ste r -Abo rt
Status (RMA )
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = Thi s bit is set whe n US B EH CI, as a ma ster, rece iv es a
master-abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may o pti o n al l y generate an SER R# by setti ng the SERR#
Enable bit.
R/W
12 Received Target Abort
Status (RTA)
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = Thi s bit is set whe n US B EH CI, as a ma ster, rece iv es a
target abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may o pti o n al l y generate an SER R# by setti ng the SERR#
Enable bit.
R/W
11 Signal ed Target - A bo rt
Sta tu s (STA )
This bit is used to ind icate when the US B EHCI func tion
responds to a cy cle with a target abo rt . There is no reason for
this t o ha ppen , so this bit will be hard -wired to ’0’. RO
10:9 DEVSEL# Timing Status
(DEVT) This 2-bit field defines the timing for DEVSEL# assertion. RO
8Master Data Parity Error
Detected
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bi t is set by the Intel® 6300 ESB ICH whenever a
data parity error is detected on a USB EH CI read
comp le tion p acket on the inte rnal interf ace to the US B
EHCI host controller (due to an equivalent data parity
error on Hu b Interf ace ) and bit 6 of the Command
register is set to 1.
R/W
7Fast Back - t o- Bac k
Capable Reserved as 1. RO
6UDF - User Def in a b le
Features Reserved as 0. RO
5 66 MH z Capab le R ese rv ed as 0. RO
4 Capa bi litie s List This bit is hardwir ed to ‘1’ indicating the presence of a valid
capabilities po in te r at offs et 34h . RO
3:0 Reserved Reserved.
Device: 29 Function: 7
Offset: 06 - 07h Attribute: Read/ Write
Defau lt Value: 0290h Size: 16-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
488 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 489
11—Intel® 6300ESB ICH
11.1 .3 Offset 08h: RID—Revision ID Register
11.1 .4 Off set 09h: Programming Interface
11.1 .5 Off set 0Ah: Sub Class Code
Table 381. Offset 08h: RID—Revision ID Register
Bits Name Description Access
7:0 R evision ID Value Refer to the Inte l® 6300ESB I/O Controller Hub Specification
Update for the most up-to-date value of the Revision ID
Register. RO
Table 382. Offset 09h: Programming Interface
Bits Name Description Access
7 :0 Program ming I nte rf a ce A value of 20h indic ate s that this US B High-speed Host
Con trolle r con f orms to the EHCI Specif ication. RO
Table 3 83. Offset 0Ah: Sub Class Code
Bits Name Description Access
7 :0 Sub Clas s Cod e A value of 03h indic ate s th at this i s a Universal Seria l Bu s
Host Controller. RO
Device: 29 Function: 7
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descript io n Size: 8-bit
Device: 29 Function: 7
Offset: 09h Attribute: Read-Only
Defau lt Value: 20h Size: 8-bit
Device: 29 Function: 7
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 03h Size: 8-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
490 Order Number: 300641-004US
11.1.6 Offset 0 Bh: Base Class Code
11.1.7 Offset 0Dh: Master Latency Timer
11.1.8 Offset 10 - 13h: Memory Ba se Address
Table 384. Offse t 0Bh: Base Class Code
Bits Name Description Access
7:0 Base Class Code A value of 0Ch in d icates tha t this is a Serial Bu s controller. RO
Table 385. Offset 0Dh: Master Latency Timer
Bits Name Description Access
7:0 Master Latency Timer Since th e US B EHCI contro lle r is in te rna lly implem e nte d wi th
arbitration thro ugh the Hub Inte rf ace (a nd not PCI), it d oes
not need a mas te r late ncy time r. These b its will be fi xed to 0. RO
Table 386. Offset 10 - 13h: Memory Base Address
Bits Name Description Access
31:1
0Ba se Addres s Bits [31:10] correspond to me mory address sign als [31:10],
respectively. This gives 1 Kbyte of locatable memory space
aligned to 1 Kbyte boundarie s. RW
9:4 Reserved Reserved.
3Prefetchable
This bit is ha rd wire d to 0, in d ica ting th at this range sh ould
not be prefetched. RO
2:1 Type This field is hard wired to 00b ind icating tha t this ra nge ma y
be mapped anywhere within 32-bit address space. RO
0Re so ur ce Typ e In di cat or
(RTE) This field is h ard wired to 00 b indicating th at th is ra nge may
be mapped anywhere within 32-bit address space. RO
Device: 29 Function: 7
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 0Ch Size: 8-bit
Device: 29 Function: 7
Offset: 0Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 7
Offset: 10 - 13h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 491
11—Intel® 6300ESB ICH
11.1.9 Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID
11.1.10 Off set 2E - 2Fh: SID—USB E HCI Subsystem ID
11.1.11 Off set 34h: Capabilities Pointer
Table 387. Offset 2C - 2Dh: USB EHCI Subsystem Vendor ID
Bits Name Description Access
15:0 USB EHCI Subsy stem
Vendor ID
This re g iste r, in comb ina tion with the USB EHCI Su bs ys te m
ID register, enables the operating system to distinguish each
subs ys te m f rom the othe rs.
Wr ites to this register ar e enabled wh en th e WRT _RDONL Y bit
(offset 80h, bit 0) is set to 1.
RW-Special
Table 388. Offset 2E - 2Fh: SID—USB EHCI Subsystem ID
Bits Name Description Access
15:0 USB EHCI Subsystem ID
This re g iste r, in comb ination with the S ubsystem Vendor ID
register, enables the operating system to distinguish each
subs ys te m f rom other(s).
BIOS sets the value in this register to identify the Subsystem
ID.
Wr ites to this register ar e enabled wh en th e WRT _RDONL Y bit
(offset 80h, bit 0) is set to 1.
RW-Special
Table 389. Offset 34h: Capabilities Pointer
Bits Name Description Access
7 :0 Capa b ilities Pointer T his register points to the s tarting offset of the U SB EHCI
capa b ilities ranges. RO
Device: 29 Function: 7
Offset: 2C-2Dh Attribute: Read/Write-Special
Defau lt Value: XXXXh Size: 16-bit
Device: 29 Function: 7
Offset: 2E-2Fh Attribute: Read/Write-Special
Defau lt Value: XXXXh Size: 16-bit
Device: 29 Function: 7
Offset: 34h Attribute: Read-Only
Defau lt Value: 50h Size: 8-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
492 Order Number: 300641-004US
11.1.12 Offset 3Ch: Interrupt Line
11.1.13 Offse t 3Dh: Interrupt Pin
11.1.14 Offset 50h: PCI Power Management Capability ID
Table 390. Offset 3Ch: Interrupt Line
Bits Name Description Access
7:0 Interrupt Line This data is not used by the Intel® 6300ESB ICH. It is used as
a scratchpad re gi ste r to communicate to softwa re the
interrupt line that the interrupt pin is connected to. R/W
Table 391. Offset 3Dh: Interrupt Pin
Bits Name Description Access
7:0 Interrupt Pin
The value of 04h indicates that the USB EHCI function within
the Intel® 6300ESB ICH’ s multi-function USB device will drive
the fourth interrup t p in fr om the d evic e –N TD# in PCI te rms.
The value of 04h in function 7 is required because th e PCI
specif ica tion doe s not re cog n ize more than f our in te rrupts,
and older APM-based OSs require that each function within a
multi-fu nction device has a different Inte rrup t Pin Regis te r
value.
Internally th e USB EHCI contr olle r u ses PIRQ[H]#.
RO
Table 392. Offset 50h: PCI Power Management Capability ID
Bits Name Description Access
7:0 A v alue of 01h indicates that this is a PCI P ower Management
capa b ilitie s f i e ld .
Device: 29 Function: 7
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 7
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 04h Size: 8-bit
Device: 29 Function: 7
Offset: 50h Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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11—Intel® 6300ESB ICH
11.1.15 Offset 51h: Next Item Pointer #1
11.1.16 Off set 52 - 53h: Power Management Capabilities
Table 393. Offset 51h: Next Item Pointer #1
Bits Name Description Access
7:0 Next Item Pointer #1
This reg ister d e fau lts to 58h, wh ich indicates that the next
capability reg iste rs beg in a t conf iguration off se t 58h. This
registe r is writable wh e n th e W RT_RDONLY bit is set. This
allo ws B I OS to eff e ctiv e ly hide th e Deb u g Port capab ility
registers when necessary . This register should be written only
during system initialization bef ore the plug-and-play software
has enabled any master-initiated traf fic. Only values of 58h
(Debug Port visible) and 00h (Debug Port invisible) are
expected to be programmed in this regi ster.
RW-Special
Table 3 94. Offset 52 - 53h: Power Management Capabilities (Sheet 1 of 2)
Bits Name Description Access
15:1
1PME_Support
This 5-bit f ie ld indicate s the po we r state s in which the
functi on may as sert PME#. The In te l® 6300ESB ICH EHC
does not support D1 or D2 state s. For all other state s, the
Intel® 6300ESB ICH EHC is capa b le of generating P ME#.
Software should never need to modify this field.
RW-Special
10 D2_Support Hard wired to 0 = D2 State is not sup p orte d . RW-Special
9 D1_Sup po rt Hardwired to 0 = D1 Sta te is not sup ported. RW-Special
8:6 Aux_Current
The I n t e l® 6300ESB ICH EHC reports 375 mA maximum
Suspend well current required when in the D3cold state. This
value may be written by BIO S whe n a more accura te value is
known.
RW-Special
5DSI
The I n t e l® 6300ESB ICH reports 0, ind icating that no d evic e -
specific initialization is required. RW-Special
4 Reserved Reserved.
Device: 29 Function: 7
Offset: 51h Attribute: Read/Write Special
Defau lt Value: 58h Size: 8-bit
Device: 29 Function: 7
Offset: 52-53h Attribute: Read/Write Special
Defau lt Value: C9C2h Size: 16-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
494 Order Number: 300641-004US
11.1.17 Offset 54 - 55h: Po wer M anagement Con trol/
Status
3PME Clock
The I n t el® 6 300ES B ICH re p orts 0, indic ating that no PCI
clock is re quir e d to ge ne rate PME#. RW-Special
2:0 Version The In t e l ® 6300ES B ICH re p orts 010b, indicating that it
complies with Revision 1.1 of th e PC I Power Ma na g e ment
Specification. RW-Special
NOTES:
1. Normally, this register is read-only to rep ort ca p a b ilities to the power manag e me nt sof t ware . To rep ort
different power manag ement capabilities depending on the system in which the Intel® 6300ESB ICH is used,
bits 15:11 an d 8:6 in th is register are writable wh e n the WRT_RDONLY bit is set. The value written to this
re giste r do e s not af fect the hardware othe r than changing the value returned during a rea d.
2. Reset: Core well, but not D3-to-D0 warm rese t.
Table 395. Offset 54 - 55h: Power Management Control/Status
Bits Name Description Access
15 PME_Status
This bit is set wh en the Intel® 6300ESB ICH EHC would
normally assert the PME# signal independent of the state of
the PME_En bit. W riting a ’1’ to this bit will clear it and cause
the inte rna l PME to d e asse rt when enab le d . Writing a ’0’ has
no effect. This bit must be explic itly cle a re d by th e op erating
syst em each time th e oper ati ng syst em is loaded.
R/WC
14:1
3Data_Scale The Intel® 6300ESB ICH hardwires these bits to 00b because
it does not support the associated Data register. RO
12:9 Data_Select The I n t el® 6300ESB ICH hardwires the se bits to 0000b
because it do es not support the associated Data register. RO
8PME_EN
A ’1’ enables the Intel® 6300ESB ICH EHC to generate an
internal PME signal when PME_Status is 1. This bit must be
explicitly cleared by the operating system each time it is
initiall y load e d .
R/W
Table 394. Offset 52 - 53h: Power Management Capabilities (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 7
Offset: 52-53h Attribute: Read/Write Special
Defau lt Value: C9C2h Size: 16-bit
Device: 29 Function: 7
Offset: 54 - 55h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
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No v ember 20 07 DS
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11—Intel® 6300ESB ICH
11.1.18 Offset 58h: Debug Port Capability ID
7:2 Reserved Reserved.
1:0 PowerState
This 2-bit field is used both to determine the current power
state of EHC function and to set a new power sta te. The
definition of the field values are:
00b – D0 state
11b – D3 hot state
When software attempts to write a value of 10b or 01b in to
this field , th e write operation must complete normally;
however, the data is discarded and no state change occurs.
When in the D3 hot state, the Intel® 6300ESB ICH must not
accept accesse s to the EHC memory range, but the
co nfi gurat ion space must still be acc e ssible. Whe n n ot in th e
D0 state, the g eneration o f the interrupt output is blocked.
Specif ically, the PIRQ[H ] is not asserted by the Intel®
6300ESB ICH when not in the D0 state.
Whe n sof tw are chang e s th is value fro m t he D3hot sta te t o
the D0 state , a n inte rnal wa rm (sof t) re set is g e nerated, a nd
so ftware must re - in itialize t he function.
R/W
NOTE: Reset (b its 15, 8): suspe nd we ll, a n d not D3-to-D0 warm re se t nor core well re se t.
Table 396. Offset 58h: Debug Port Capability ID
Bits Name Description Access
7:0 Debug Port Capability ID Th is re g iste r is hardwired to 0 Ah , which indicates tha t th is is
the sta rt of a Debu g Port Ca pab ility str uct ure. RO
Table 395. Offset 54 - 55h: Power Management Control/Status
Bits Name Description Access
Device: 29 Function: 7
Offset: 54 - 55h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Device: 29 Function: 7
Offset: 58h Attribute: Read-Only
Defau lt Value: 0Ah Size: 8-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
496 Order Number: 300641-004US
11.1.19 Offset 59h: Next Item Pointer #2
11.1.20 Offse t 5Ah - 5Bh: Debug Port Base Offset
11.1.21 Offse t 6 0h: Serial Bus Release Number
11.1.22 Offset 6 1h: Frame Length A djustm ent
Note: This feature is used to adjust any offset from the clock source that generates the clock
that drives the SOF counter. When a new value is w ritten into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit in the USBSTS register is a ‘1’. Changing
value of this register while the host controller is operating yields undefined results. It
Table 397. Offset 59h: Next Item Pointer #2
Bits Name Description Access
7:0 Next Item Pointer #2 This register is hardwired to 00h which indicates there are no
more c a pability structure s in this fu nction. RO
Table 398. Offset 5Ah - 5Bh: Debug Port Base Offset
Bits Name Description Access
15:1
3BAR Number This field is hard wired to 20h to indi cate the me mory BAR
begins at offset 20h in the EHCI configuration space. RO
12:0 Debug Port Offset This field is hardwired to 080h to indicate that the Debug Port
regis t er s begin at offse t 80h in the EHCI memory range. RO
Device: 29 Function: 7
Offset: 59h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 7
Offset: 5Ah - 5Bh Attribute: Read-Only
Defau lt Value: 2080h Size: 16-bit
Table 399. Offset 60h: Serial Bus Release Number
Bits Name Description Access
7:0 A value of 20h ind ica tes that this controller follows the US B
Speci fica tion re v. 2.0.
Device: 29 Function: 7
Offset: 60h Attribute: Read-Only
Defau lt Value: 20h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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11—Intel® 6300ESB ICH
should not be reprogrammed by USB system software unless the default or BIOS
programmed values are incorrect or the system is restoring the register while returning
from a suspended state.
11.1.23 Offset 62 - 63h: Port Wake Capability
Note: This register is in the suspend power well. The intended use of this register is to
estab lis h a polic y ab out which por ts are to be us ed for wa ke ev ents. Bit p os itio ns 1- 4 in
the mask correspond to a physical port implemented on the current EHCI controller. A
‘1’ in a bit position indicates that a device connected below the port may be enabled as
a wake-up device, and the port may be enabled for disconnect/connect or over-current
events as wake-up events. This is an information-only mask register. The bits in this
register do not affect the actual operation of the EHCI host controller. The system-
specific policy may be established by BIOS initializing this register to a system-specific
value. System software u ses the information in this register when enabling devices and
ports for remote wake-up.
Table 400. Offset 61h: Frame Length Adjustment
Bits Name Description Access
7:6 Reserved Thes e bi ts are reserved for future use and should read as
00b. RO
5:0 Frame Length Timing
Value
Each decimal value change to this register corresponds to 16
high -speed bit ti me s. The SOF cycle time (nu mber of SOF
counter clock periods to generate a SOF micro-frame length)
is equal to 59488 + value in th is fie ld. The def ault value is
decim a l 32 (20h), which gives a SOF cycle time of 60000.
Frame Len gt h
(# High Speed bit times)FLADJ Value
(decimal) (decimal)
59488 0 (00h)
59504 1 (01h)
59520 2 (02h)
59984 31 (1Fh)
60000 32 (20h)
60480 62 (3Eh)
60496 63 (3Fh)
Device: 29 Function: 7
Offset: 61h Attribute: Read/Write
Defau lt Value: 20h Size: 8-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
498 Order Number: 300641-004US
11.1.24 Offse t 64 - 65h: Classic USB Override
Note: This 16-bit register provides a bit corresponding to each of the ports on the EHCI host
controller. When a bit is set to ‘1’, the corresponding USB port is routed to the class ic
(UHCI) host controller and will operate using only the classic signaling rates. The
feature is implemented with the following requirements:
The associated Port Owner bit does not reflect the value in this new Override
register. This guarantees compatibility with EHCI drivers.
The associated Port Owner bit does not reflect the value in this new Override
register. This guarantees compatibility with EHCI drivers.
B IOS m ust onl y w rite t o t h is r egi ster du r i ng in itial izati on ( wh il e t h e C o nf ig ur e d Fl a g
is ‘0’ ).
The regist er is implemented in the Suspend well to maintain port-routing when the
core power goes down
When a ‘1’ is present in the Override register, the classic controller operates the
port regardless of the EHCI port routing logic. The corresponding EHCI port will
always appear disconnected in this mode.
Note: EHCI test modes will not work on a port that has been overridden by this register.
Table 401. Offset 62 - 63h: Port Wake Capability
Bits Name Description Access
15:5 Reserved Reserved.
4:1 Port W ake Up Capability
Mask
Bit position s 1 throug h 4 correspond to a physic al por t
impl em ent ed o n t hi s host c on trol l er. Fo r exam pl e, b it po sit io n
1 corresp ond s to p ort 0, p osition 2 port 1, positio n 3 por t 2,
p osit ion 4 port 3.
RW
0 Port Wake Implemented A ’1’ in bit 0 indicates that this re g ister is im pleme n ted to
software. RW
Device: 29 Function: 7
Offset: 62 - 63h Attribute: Read/Write
Defau lt Value: 001Fh Size: 16-bit
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No v ember 20 07 DS
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11—Intel® 6300ESB ICH
Table 402. Offset 64-65h: CUO - Classic USB Override
11.1.25 Off set 68 - 6Bh : USB EHCI Legacy Support
Extended Capability
Bits Name Description Reset
Value Access
15:4 Reserved Reserved.
3:2 Classic USB
Port Owner A “1” in a bit position forces the corresponding USB port to
the cla ssic host controller R/W
0 Reserved Reserved.
Device: 29 Function: 7
Offset: 64-65h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Power Well: Suspend
Table 403. Offset 68 - 6Bh: USB EHCI Legacy Support Extended Capability
Bits Name Description Reset
Value Access
31:2
5Re se rv ed Rese rv ed. Ha rd wire d to 00h.
24 HC OS
Owned
Semaphore
System sof tware sets this bit to request owne rship of the
EHCI controller. Ownership is obtained wh e n this bit rea d s as
’1’ and the HC BIOS Owned Semaphor e bit read s as clear. R/W
23:1
7Re se rv ed Rese rv ed. Ha rd wire d to 00h. RO
16 HC BIOS
Owned
Semaphore
The BIOS sets this bit to establish ow ner ship of the EHCI
con troller. System BIOS will clear this b it in re sponse to a
requ e st for own e rship of th e EHCI control le r by sy ste m
software.
R/W
15:8 Next EHC I
Capability
Pointer
A value of 00h indicates that there are no EHCI Extended
Capability struc tu re s in this device. RO
7:0 Capability
ID A value of 01h indicates that this EHCI Extended Capability is
the Legacy S upport Capabil ity. RO
Device: 29 Function: 7
Offset: 68-6Bh Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Power Well: Suspend
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
500 Order Number: 300641-004US
11.1.26 Offse t 6C - 6Fh: USB EHCI Legacy Support
Extended Co ntrol/Status
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
(Sheet 1 of 2)
Bits Name Description Access
31 SMI on BAR This bit is set to ‘1whenever the Base Address Register
(BAR) is written. R/WC
30 SMI on PCI Comm and This bit is set to ‘1whenever the PCI Command Register is
written. R/WC
29 SMI on OS Owne rship
Change
This bit is set to ‘1whenever the HC OS Owned Semaphore
bit in the USB EHCI L egac y Sup po rt Ex ten ded Cap abi lity
register transitions from ’1’ to a ’0’ or ’0’ to a ‘1’. R/WC
28:2
2Reserved Hard wire d to 00h . RO
21 SMI on Async Adv a nc e
Shadow bit of the Interrup t on Asy nc A d vance bit in the
USB 2STS regi st e r. To cl ear this b it system s o ftware must
write a ’1’ to the Inte rrup t on A sy nc A dvance bit in the
USB2STS register.
RO
20 SMI on Host System
Error Shad ow bit of Host System Error bit in the USB2STS. To clear
this bi t, system software must write a ’ 1 ’ t o th e Ho st System
Error bit in the US B 2S TS re g iste r. RO
19 SMI on Frame List
Rollover Shadow bit of Frame List Rollover b it in the USB2STS register.
To clear this bit system software must write a ’1’ to the Frame
List Rollover bit in the U SB2S TS re g ister. RO
18 SMI on Port Change
Detect Shadow bit of Port Change Detect bit in the USB2STS register.
To clear this bit system software must write a ’1to the Port
Change Dete ct bit in the US B 2S TS re gi ste r. RO
17 S MI on US B Error Shadow bit of USB Error Interrupt (USBERRIN T) bit in the
USB 2STS regi st e r. To cl ear this b it system s o ftware must
write a ’1’ to the US B Error Interrupt bit in the USB 2S TS
register. RO
16 S MI on US B Comp le te Shadow bit of USB Inte rrup t (USBINT) bit in the USB 2S TS
regi ste r. To cle a r th is bit system softw are must wr ite a ’1’ to
the USB Interrup t bit in the USB 2S TS re g iste r. RO
15 SMI on BAR Enable Wh en this bit is ‘1’ and SMI on B A R is ‘1’, the h ost controlle r
will issue a n SMI. R/W
14 SMI on PCI Command
Enable When this bit is ‘1’ and SMI on PCI Command is ‘1’, the host
contr o lle r will issue a n SMI. R/W
13 SMI on OS Owne rship
Enable When th i s bit is a ’1 ’ AND t he O S O wn er ship C h ange bi t i s ’1 ,
the host controll er will issue an SMI. R/W
12:6 Reser v ed Res er ved —RO. Hardwir ed to 00h. RO
5SMI on Asyn c Adva nc e
Enable When this bit is a ’1’ an d the SMI on Async Advance bit is a
’1’, the host contr olle r will issu e a n SMI immedia te ly. R/W
Device: 29 Function: 7
Offset: 6C-6Fh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Power Well: Suspend
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 501
11—Intel® 6300ESB ICH
11.1.27 Offset 70 - 73h: Intel Specific USB EHCI SMI
Note: This register provides a mechanism for BIOS to provide USB EHCI related bug fixes and
workarounds. Writin g a ‘1’ to that bit location clears bits that are marked as Read/
Write-Clear
(R/WC ). Softw a re sh ould clea r all SMI status b its pri or to setti n g the glob al SMI enable
bit and individual SMI enable bit to prevent spurious SMI when returning from a
powerdown.
4SMI on Host Sy stem
Error Enable Whe n this b it is a ’1’ and the SMI on Host System Error is a
’1’, the host controller will issu e an SM I. R/W
3SMI on Frame List
Rollover Enable When this bit is a ’1’ and the SMI on Frame List Rollover bit is
a ’1’, th e hos t con troller will issue a n SMI. R/W
2SMI on Port Change
Enable When this bit is a ’1’ and the SMI on Port Change Detect bit is
a ’1’, th e hos t con troller will issue a n SMI. R/W
1 SMI on USB Error Enable When this bit is a ’1’ and the SMI on USB Error bit is a ’1’, the
hos t controller will issue a n SMI im me diately. R/W
0SMI on USB Complete
Enable When this bit is a ‘1’ and the SMI on USB Complete bit is a 1’,
the host con troller will is su e an SMI im me diately. R/W
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 1 of 2)
Bits Name Description Access
31:2
8Reserved Res er ved . H a rd wire d to 00h. RO
27:2
6Reserved Reserved. R/WC
25:2
2SMI on Po r tOwn er B its 27: 22 correspond to the Port Owner bits for ports 0 (22)
throug h 3 (25). These bits are set to ‘1’ whenever the
associa ted Port Owner bits transition from ‘0’->’1’ or ‘1’->’0’.
Softwa re cle a rs th ese bits by writing a ’1’. R/WC
21 SMI on PMCSR This bit is set to ‘1’ whenever software modifies the Power
State bits in the Powe r Manage ment Control/Status (PMCSR)
register. R/WC
20 SMI on Async T h is bit is set to ‘1’ whe ne ver the A sync S ched ule Ena b le bit
transit ions from ‘1’->’ 0’ or ‘ 0’- >’1 R/WC
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
(Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 7
Offset: 6C-6Fh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Power Well: Suspend
Device: 29 Function: 7
Offset: 70-73h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Power Well: Suspend
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
502 Order Number: 300641-004US
19 S MI on Perio dic This bit is set to ‘1’ whenever the Periodic Schedule Enable bit
tran sitio ns from ‘1’-> ’0’ or ‘0’->’1’ R/WC
18 SMI on CF This bit is set to ‘1’ whenever the Configure Flag (CF)
tran sitio ns from ‘1’-> ’0’ or ‘0’->’1’. R/WC
17 SMI on HCHalted This bit is set to ‘1’ whenever HCHalted transitions to ‘1’ as a
result of the Run/Stop bit being c leared. R/WC
16 SMI on H CReset This b i t i s se t to ‘1 wh e n e ver HC R E S E T tran si tion s to 1’ R/ WC
15:1
2Reserved Reserved . Hardwired to 00h. RO
11:1
0Reserved Reserved. R/W
9:6 SMI on PortOwner
Enable When any of these bits are ‘1’ and th e corre spondi ng SMI on
PortOwner bits are ‘1’, the host controlle r will issue a n SMI.
Unused ports should have their corresponding bits cleared. R/W
5SMI on PMSCR Enable
When t his b it is ‘1’ an d SMI on PMS CR is ‘1 , the h ost
contr o lle r will issue a n SMI. R/W
4SMI on Async Enable
When this bit is ‘1’ and SMI on A sync is ‘1, the host controller
will issue a n SMI R/W
3 SMI on Peri od ic Enable When this bit is ‘1’ and SMI on Perio dic is ‘1’, the host
contr o lle r will issue a n SMI. R/W
2 SMI on CF Enable Whe n th is b it is ‘1’ an d SMI on CF is ‘1’, th e n the h ost
contr o lle r will issue a n SMI. R/W
1 SMI on HCHalted Enable Whe n th is b it is a ‘ 1’ an d SM I on H CHa lte d is ‘ 1’, th e hos t
contr o lle r will issue a n SMI. R/W
0SMI on HCReset Enable
When this bit is a ‘1’ and SMI on HCR eset is ‘1, host controller
will issue an SMI. R/W
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 7
Offset: 70-73h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Power Well: Suspend
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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11—Intel® 6300ESB ICH
11.1.28 Off se t 80h: Access Control
11.1.29 HS_ Ref_V_USB HS Reference Voltage Regist er
11.2 Memory-Mapped I/O Registers
The USB 2.0 EHCI memory-mapped I/O space is composed of two sets of registers:
Capability Registers and Operational Registers.
Note: When the USB EHCI function is in the D3 PCI power state, accesses to the USB EHCI
memory range are ignored and result a master abort. Similarly, when the Memory
Space Enable (MSE) bit is not set in the Command register in configuration space, the
memory range will not be decoded by the Intel® 6300ESB ICH Enhanced Host
Cont rol ler (EHC ). Whe n the MSE bit is not s et, the I ntel® 6300ESB ICH must default to
allowing any memory accesses for the range specified in the BAR to go to PCI. This is
Table 406. Offset 80h: Access Control
Bits Name Description Access
7:1 Reserved Reserved.
0WRT_RDONLY
When se t to ‘1 , this b it en a bles a s elec t group of norma lly
read-only re g isters in th e EHC function to b e written b y
softwar e. Registers that ma y only be written whe n this mod e
is entere d are note d in the su mmary tables and detailed
descr iption as Read/Write-S p e cial. The registe rs fa ll into two
categories:
1. System-confi gured param eters
2. Status bits
R/W
Ta ble 407. HS_ Ref_V_USB HS Reference Voltage Register
Bits Name Description Access
31:2
2Reserved Reserved RO
21:1
6USB2 HS Ref Vo ltage BIOS should always program this register to the
reco mmended value of ‘111111b . All oth er values are
reserved. RW
15:0 Reserved Reserved RW
NOTE: System BIOS should program a value of '111111b ' into D 29:F7:Register Offset DCh, bits 21:16 dur ing
POST and resum e from S3(ST R)/S 4(S T D) state s on ALL step pi ngs of the Intel 6300ESB ICH.
Device: 29 Function: 7
Offset: 80h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 7
Offset: DCh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
504 Order Number: 300641-004US
because the range may not be valid and, therefore, the cycle must be made available
to any other targets that may be currently using that range.
11.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the Host Controller Capability Registers, only the Structural
P arameters register is writable. This register is implemented in the Suspend well and is
only reset by the standard suspend-well hardware reset, not by HCRESET or the D3-to-
D0 reset.
11.2.1.1 Offset 00h: CAPLENGTH—Capability Registers Length
Offse
t Register Default Type
0 0h Ca p a bilities Registers Length 20 h RO
02-
03h Hos t Contr o ller Inte rface Vers ion Nu mber 010 0h RO
04-
07h Structural Parameters 00103206h R W-Special
08-
0Bh Capability Par ameters 00006871h RO
NOTE: “RW-Sp ec ia l” me an s that the re giste r is n ormally rea d- on ly, but may b e wr itten whe n
the WRT_RDONLY bit is set. Since these registers are expec ted to be programmed by
BIOS during initialization, their contents must not get mod if ie d by HCRESET or D 3 -to-
D0 in ternal r eset .
Table 408 . Offse t 00h : CAP LE NG TH Cap ab ilit y Re gis te rs Len gth
Bits Name Description Access
7:0
This register is used as an offs et to add to the Memory Base
Register to find the beginning of the Operational Register
Space. This is fixed at 20h, indicating that the Operation
Registers begin at offs et 20h.
Device: 29 Function: 7
Offset: 00h Attribute: Read-Only
Defau lt Value: 20h Size: 8-bit
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11—Intel® 6300ESB ICH
11.2.1.2 Offs et 02 - 03h: HCIVERSION—Host Controller Interface
Version Number
11.2.1.3 Offset 04 - 07h : HCSP ARAMS—Host Controller Structural
Parameters
Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.
Note: This register is writable when the WRT_RDONLY bit is set.
Table 409. Offset 02 - 03h: HCIVERSION—Host Controller Interface Version
Number
Bits Name Description Access
15:0 Host Controller Interface
Versio n Nu mber
This is a two-byte register containing a BCD encoding of the
version number of interface that this host controller interface
conforms. RO
Table 410. Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters
(Sheet 1 of 2)
Bits Name Description Access
31:2
4Re se rv e d Re se rv ed. D efa ult = 0h . RO
23:2
0Debug Por t Number
(DP_N) Ha rd wired to 1h, indicating tha t the Debu g Port is on the
lowest numbered port on the Intel® 6300ESB ICH.
19:1
7Reserved Reserved.
16 Reserved Res er ved . H ard wire d to 0.
Device: 29 Function: 7
Offset: 02 - 03h Attribute: Read-Only
Defau lt Value: 0100h Size: 16-bit
Device: 29 Function: 7
Offset: 04-07h Attribute: Read/Write-Special
Defau lt Value: 00102204h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
506 Order Number: 300641-004US
15:1
2Numb e r of Comp a nion
Controllers (N_CC)
This field indicate s t he number of co mpanion controllers
asso cia te d with this US B ECH I host controller.
A ’0’ in this field in d ica te s th er e are no compan ion h ost
contr olle rs. Port-ownership hand- of f is no t sup po rte d . On ly
high -sp e e d d e v ices are sup p o rte d on th e h ost controller root
ports.
A value larger th an ’1 ’ in this field indicates th e re a re
compa ni on U S B UH C I ho st cont roll er(s). Port-owne r sh ip
hand- offs are supp ort ed. H ig h, Full- and Low-s peed devi c es
are sup ported on t he ho st controller root ports.
The I n t el® 6 300ES B ICH allows the default value of 2h to be
over-written by BIOS. S ince the I nte l® 6300ESB ICH cannot
supp ort more than two compan ion h ost con trollers, bits
15:14 are imp lemented as re ad-only 00b. When removing
clas sic control le rs, the y sh ould be disabled in the foll ow ing
order: Function 1 and Function 0, which correspond to ports
3:2 and 1:0, respe ctively.
11:8 Number of Ports per
Companion Contr olle r
(N_PCC)
This field indicates the number of ports suppo rted per
companion host con troller. It is us ed to in d ica te the port
routing configurati on to system software. The Intel®
6300E SB ICH hard wires this field to 2h.
RO
7:4 Reserved Reserved. These bits are reserved and default to ’0.
3:0 N_PORTS
This field specifies th e nu mber of physical downstream p orts
impleme nte d on this host con troller. The value of this fi el d
determines how many port registers are addressable in the
Operational Register Space. Valid values are in the range o f
1H to FH.
The I n t el® 6 300ES B ICH re p orts 4h b y default. H owe v e r,
software may write a value less than four for some platform
config ura tions. A ’0’ in this field is u nd e fined. Bit 3 is always
hardwire d to ’ 0’.
Tab le 410. Offset 04 - 07h: HCSPARAMS—Host Controller Structural Para meters
(Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 7
Offset: 04-07h Attribute: Read/Write-Special
Defau lt Value: 00102204h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 507
11—Intel® 6300ESB ICH
11.2.1.4 Offs et 08 - 0Bh: HCCPARAMS—Host Controller Capability
Parameters
Tabl e 41 1. Offs et 08 - 0Bh: HCCPA RAMS —H ost C on trol le r Cap ab ility Par am et er s
Bits Name Description Access
31:1
6Reserved Reserved.
15:8 EHCI Extended Capab il-
ities Pointer (EECP) This field is hardwire d to 68h, ind icating that the EHCI
capab ilities list ex ists and b egins at offset 68h in the PCI
configuration sp ace. RO
7:4 Isochronous Scheduling
Threshold
This f ie ld ind icates, rela tiv e to th e curre nt position of t he
exec uting ho st cont roller, where s of twa re may reli ably upd ate
the is och ronou s schedu le. Wh en b i t [7] is 0’, the v al ue o f th e
least significant 3 bits indicates the number of micro-frames a
host controller holds a set of isochronous d ata struc tures (one
or more) before flushing the state. When bit [7] is a ’1’, then
hos t software assumes t he h ost controller may c a che a n
isoch ronous data structure f or an e ntire frame. Refer to the
EHCI specification for details on how software uses this
information for schedu lin g isochronous trans fers.
This f ie ld is ha rdwired to 7h.
RO
3 Reserved Reserved. These bits are reserved and shou ld be set to ’0’.
2Asynchronous Schedule
Park Capability This bit is hardwired to 0, indicating that t he Host Controlle r
does not support this optiona l feature .
1Programmable Frame
Li s t F lag
0 = System software must use a frame list leng th of 1024
elemen ts with this host controll er. The USBCMD r egister
Frame List Size field is a read-only register and must be
set to ’0’.
1 = System software may specify and use a smaller frame list
and configure the host control ler through the USBCMD
register Frame List Size field. The frame list must always
be aligned on a 4K page boundary. This requirement
ensure s t ha t th e frame list is al ways p h ys ically
contiguous.
RO
064-b it Addres sin g
Capability
This field doc u me nts th e a d dressin g range capability of t his
impl ementat i on . The value of this fiel d dete rmin es whether
softwar e sh ould use the 32-b it or 64-b it d a ta structures.
Va lues for this field have the followi ng interpretation:
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
This b it is h ardwired to 1.
RO
Device: 29 Function: 7
Offset: 08-0Bh Attribute: Read-Only
Defau lt Value: 00006871h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
508 Order Number: 300641-004US
11.2.2 Host Controller Operation al Registers
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities regi sters. The operational reg ister base must be
DWORD-aligned and is calculated by adding the value in the first capabilities register
(CAPLENGTH=20h) to the base address of the enhanced host controller register
address space. All registers are 32 bits in length.
Note: Software must read and write these registers using only DWORD accesses. These
registers are divided into two sets. The first set at offsets 20h to 3Fh are implemented
in the core power well. Unless oth erwise n oted, the core-w ell registers are reset by the
assertion of any of the following:
Core well hardware reset
HCRESET
D3- t o - D 0 r eset
The second set at offsets 60h to the end of the implemented register space are
implemented in the Suspend power well. Unless otherwise noted, the suspend-well
registers are reset by the assertion of either of the following:
Suspend well hardware reset
HCRESET
Offset Register Default Special Notes Type
00-03h U S B EHCI Command 00080000h R/W
04-07h U S B EHCI Status 00001000h R/W
08-0B h USB EHCI Interrupt Enabl e 00000000h R/W
0C-0Fh USB EHCI Frame Index 00000000h R/W
10-13h Control Data Structure
Segment 00000000h R/W
14-17h Period Frame List Base
Address 00000000h R/W
18-1Bh Next Asynchronous List
Address 00000000h R/W
1C-3Fh Reserved 0h RO
40- 43h Configure Flag Re gister 00000000h Suspend R/W
44-47h Port 0 Status and Control 000030 00h Suspe nd R/W
48-4B h Port 1 S tatus and Control 000030 00h Suspe nd R/W
4C-4Fh Port 2 S tatus and Control 000030 00h Suspe nd R/W
50-53h Port 3 Status and Control 000030 00h Suspe nd R/W
54-5Fh Reserved Undefined RO
60-73h Debug Port R egi s t ers. Undef i ne d RO
74-3FFh Reserved Undefined RO
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 509
11—Intel® 6300ESB ICH
11.2.2.1 Offset CAPLENGTH + 00 - 03h: USB EHCI CMD —USB
EHCI Command Register
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command
Register (Sheet 1 of 3)
Bits Name Description Access
31:2
4Reserved Reserved. These bits are reserved and should be set to ’0’.
23:1
6Interrupt Threshold
Control
Default 04h. This field is used by system software to select
the max imum rate at which the host controller will issue
interrupts. The only valid values are define d below. When
software writes an invalid value to this register, the re sults
are undefined.
Val u e Maximum Interrupt Interval
00h Reserved
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (de f a ult, e quates to 1 ms)
10h 16 micro-f rames (2 ms)
20h 32 micro-f rames (4 ms)
40h 64 micro-f rames (8 ms)
R/W
15:8 Reserved Reserved. These bits are reserved and should be s et to ’0’.
11:8 Unimplemented
Asynchronous Park
Mode Bits T his fie ld is hardw ire d to 000b bec a use the host co ntrolle r
does not support this optiona l feature .
7Lig ht H ost Controller
Reset The In t e l® 6300ESB ICH does not im pl em e nt this optional
reset a nd h ardwires th is b it to 0. RO
6Interrupt on Async
Advance D oorb e ll
This b it is u sed as a doorb e ll by sof twa re to te ll the host
controller to issue an interrupt the next time it a dvances
asynchronous schedule. Software must write a ’1 ’ to this bit
to rin g the d oorb e ll. W h e n th e host controll er has evicted all
appropriate cached schedule state, it sets the Interrupt on
Async Advance status bit in the USBSTS register. When the
Interrup t on Async Advance Enable bit in the US BINTR
registe r is a ’1’, the host controll er w ill assert an inte rru p t a t
the next interrupt threshold. See the EHCI specification for
opera tiona l d e ta ils.
The host cont rolle r sets this b it to a ’0’ after it has set the
Interrup t on Async Advance status bit in the USBSTS register
to a ’1’.
Software should not write a ’1 ’to this bit when the
asynchronous schedule is in a ctive. Doing so will yie ld
undefined results.
R/W
5Asynchronous Schedule
Enable
Default 0b. This bit controls whether the host controller skips
processing the Asy nchro nous S ched ule. Values mean:
0 = Do not pr ocess the Asynchronous Sched ule
1 = Use the ASY N CLISTADDR re gister to ac ce ss t h e
Asynchronous Sched ule.
R/W
Device: 29 Function: 7
Offset: CAPLENG TH + 00-03h Attribute: Read/Write
Defau lt Value: 00080000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
510 Order Number: 300641-004US
4 P er io di c Sch edul e Enable
Default 0b. This bit controls whether the host controller skips
processing the Periodic S che d ule . Values mean:
0 = Do not pro cess the Peri odic Schedule
1 = Use t h e P ER I ODICLI STBASE re g ister t o ac ce ss the
Periodic Schedule.
R/W
3:2 Frame List Size The Intel® 6300ESB ICH hardwires this field to 00b because it
only supports the 1024-element frame list size. RO
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command
Register (Sheet 2 of 3)
Bits Name Description Access
Device: 29 Function: 7
Offset: CAPLENG TH + 00-03h Attribute: Read/Write
Defau lt Value: 00080000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 511
11—Intel® 6300ESB ICH
1Hos t Con troller Reset
(HCRESET)
This control bit is used by software to reset the host
controller. The effects of this on Root Hub registers are similar
to a Chip Ha rd ware Reset (i.e., RSMRS T# as sertion and
PWROK deass er tion on the Inte l® 6300ESB ICH).
When sof tware writes a ’1’ to this bit, the Ho st Controller
resets its internal pipelines, timers, counters, state machines,
etc. to their initial value. Any transaction currently in progress
on USB is immediate ly ter min ate d. A USB res et is not dr iven
on downstream ports.
NOTE: PCI Configuration registers and Hos t Contro ller
Capability Registers are not effe cted by this reset.
All operational registers, including port registers and port
state machines are set to their initial values. Port ownership
reverts to the compan ion h ost controller(s), w ith the sid e
effects described in the EHCI spec. Software must re-initialize
the host controller in order to return the host controller to an
opera tiona l state.
This b it is set to ’0’ by the Host Controller whe n th e res e t
proc ess is co mplete. Soft ware cannot te rminate the rese t
proc ess e arly by writing a ’0’ to this regis te r.
Software should not set this bit to a ’1’ when the HCHalted bit
in the US BSTS register is a ’0’. Attempting to reset an actively
running host controller will re su lt in u nd e fined behavior. This
reset can be used to leave EHCI port test modes.
R/W
0 Run/Stop (RS )
Defaul t 0b. 1=Run. 0= St op. Whe n set to a 1, the Ho st
Contro l ler pro ceed s with execu ti on of the schedule . The Host
Controller continues execution as long as this bit is set. When
this bit is set to 0, the Host Controller co mp le te s the current
transaction on the USB and then halts. The HC Halted bit in
the sta tus regi st e r in d ica tes whe n th e Ho st Con troller ha s
finish ed the transacti on and has enter ed the stopp e d state.
Software should not write a ’1’ to this field unless the host
controller is in the Halted state (i.e ., HCHalted in the USBSTS
register is a ’1’). The Halted bit is cleared immediately when
the Run bit is set.
The fo llowing t able expl ains h ow the di ffer ent combinat ions of
Run and Halted should be interpreted:
Run/Stop Halted Interpretation
0 0 Valid - in the proce ss of halting
0 1 Valid - halted
1 0 Valid - running
1 1 Invalid - the HCHalted bit clears
immediately.
Memory read cy cle s initiated by the EHC th at receive a ny
st atu s othe r th an S uccessfu l will result in this bit b e ing
cleared.
R/W
NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing
to the register causes a c ommand to be executed.
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command
Register (Sheet 3 of 3)
Bits Name Description Access
Device: 29 Function: 7
Offset: CAPLENG TH + 00-03h Attribute: Read/Write
Defau lt Value: 00080000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
512 Order Number: 300641-004US
11.2.2.2 Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI
Status
Note: This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to ’0’ in this register by writing a ’1’ to it. See the Interrupts
description in Section 4 of the EHCI Specification for additional information concerning
USB EHCI interrupt conditions.
Tab le 41 3. Off set CA PLENGT H + 04 - 07h : USB EHCI STS —USB EH CI Stat us (S heet
1 of 2)
Bits Name Description Access
31:1
6Reserved Reserved. These bi ts are reserved and should be s et to ’0’.
15 Asynchro nous Schedule
Status
0 = Default. T his b it repo rts the current real status of the
Asynchronous Schedule. W he n this b it is a ’0’, the status of
the As ynchr o no us Schedule i s disabl ed. When this bit i s a ’1’,
the s tatus of the As ynchron ous Schedul e is enabl ed. The Host
Controller is not required to immediately disable or enable the
Asy nch ronous Sch e d u le wh e n software tra nsitions the
Asy nch ronous Sche d u le E na b le bit in the US B CMD register.
When th is bit an d the Asynchronous Schedule Enable bit are
the sam e v a lu e, t h e As yn chro no us S ched u le is ei t her enabl ed
(1) or disable d (0).
RO
14 Periodic Schedule Status
0 = Default. T his b it repo rts the current real status of the
Periodic Schedule . W he n this bit is a ’0’, the status of the
Periodic Schedule is disabled. When this bit is a ’1’, the status
of the Periodic Schedule is enabled. The Host Controller is not
required to immediately disable or enable the Periodic
S ch e d u l e wh e n so f t w are transitions t he Period ic S che d ule
Enable bit in the USBCMD register. When this bit and the
Periodic S che d u le Enable bit are the same v alue, th e Per io dic
Schedule is either en abled (1) or disabled (0).
RO
13 Reclamation
0 = Default. This is a read-only status bit used to detect an
empty as ynchronous schedule. The operational model and
valid transitions for this bit a re described in Se ction 4 of the
EHCI Specification.
RO
12 HCHalted
(Defaults to 1). T his bit is a ’0’ whenever the Run/St op bit is a
’1’. The Host Controller sets this bit to ’1’ after it has stopped
executing as a result of the Run/Stop bit being set to 0, either
by software or by the Host Controller hardware (e.g., internal
error).
RO
11:6 Reserved Reserved.
5Interrupt on Asyn c
Advance
0 = D efault. System software may force the host controller to
issue an interrupt the next time the host controller advances
the as ynchronou s schedul e by writi ng a ’1’ t o the Interrupt on
Async Advance Doorbell bit in the U SBCMD register. This bit
indicates the ass ertion of tha t inte rrupt source.
R/WC
Device: 29 Function: 7
Offset: CAPLENG TH + 04-07h Attribute: Read/Write Clear
Defau lt Value: 00001000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 513
11—Intel® 6300ESB ICH
4Host System Error
The Hos t Cont roller sets th is b it to ’ 1’ whe n a ser iou s e rror
occurs duri ng a host system access involving the Host
Con trolle r m od ule . A hard wa re inte rrupt is genera te d to the
system. Memory read cycles initiated by the EHC that receive
any stat us other than Successful wi ll re sult in this bit b e ing
set.
W hen this error oc curs, the Hos t C ontrolle r clears the Run/Stop bit in
the Co m m and regi st er t o prevent fu r t her e x ecution of the schedul ed
TD s. A har dwa re int er rupt i s gener at ed t o the syst em (whe n e nabl ed in
the Interrupt Enable Register).
R/WC
3 Frame List Rollover
The Host Controller sets this bit to a ’1’ when the Frame List
Index rolls over from its maximum value to ’0’. Since the
Intel® 6300ES B ICH only supports the 1024-entry Frame List
Size, the Fram e List Index roll s over eve ry time FRNUM[13]
toggles.
R/WC
2Port Change Detect
The Host Controller sets this b it to a ’1’ when any port for
which the Port Owner bit is set to ’0’ has a chan ge bit
transition from a ’0’ to a ’1’ or a Force Port Resume bit
transition from a ’0’ to a ’1’ as a result of a J-K transition
detec ted on a suspende d port .
This b it is a llowed to be main tain e d in th e Auxilia ry power
well. Alterna tively, it is also acce ptable tha t on a D3 to D 0
transit ion of th e EHCI HC device , this bit is loaded with the
OR of all of the PORTSC change bits (including: Force port
resume, over-current change, enable/disable change and
conne ct status change). Regard le ss of the imp le men tation,
whenever this bit is readable (i.e., in the D0 state), it must
provide a valid vi ew of the Por t Status registe rs.
R/WC
1USB Error Interrupt
(USBERRINT)
The Host Controller sets this bit to ’1’ when completion of a
USB tra n saction results in an err or condition (e.g., er ror
counter underflow). Whe n the TD on which the error interrupt
occurred also had its IOC bit set, both this bit and Bit ’0’ are
set. See the EHCI s pecificatio n for a li st of the USB errors that
will res ult in th is in ter rup t being a ss e rte d.
R/WC
0 USB Interrup t (USBINT)
The Host Controller sets this bit to ’1 ’ when the cause of an
interrupt is a completion of a USB transaction whose Transf er
De scriptor ha d its I OC bit set.
The Host Controller also se ts this bit to ’1’ when a short
packet is detected (actual number of bytes receiv e d was le ss
than the expected number of bytes ).
R/WC
Table 413. Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status ( Sheet
2 of 2)
Bits Name Description Access
Device: 29 Function: 7
Offset: CAPLENG TH + 04-07h Attribute: Re ad/Write Clear
Defau lt Value: 00001000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
514 Order Number: 300641-004US
11.2.2.3 Offset CAPL ENGTH + 08 - 0Bh: USB EHCI INTR—USB
EHCI Interrupt Enable
11.2.2.4 Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
Note: This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for the Intel® 6300ESB
ICH since it only supports 1024-entry frame lists. This register must be written as a
Table 414. Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI Interrupt
Enable
Bits Name Description Access
31:6 Res erved Reserved.These bits are reserved and should be ’0 .
5Interrupt on Asyn c
Advance Enable
When this bit is a ’1’ an d the Interrup t on A sync A d vance bit
in the USBSTS register is a ’1’, the host controller will issue an
interrupt at the next inter rupt threshold. The inte rrup t is
acknowledged by sof twa re cle a ring th e In te rrup t on A sy n c
Advance bit.
R/W
4Host System Error
Enable
When this bit is a ’1’ and the Host System Error Status bit in
the US B ST S reg ister is a ’1 , the h ost control le r will issue an
interrupt. The interrupt is acknowledged by software clearing
the Host Syste m Error bit.
R/W
3Fr ame List Rollover
Enable
When this b it is a ’1 ’ an d the Fra me Lis t Rollover bit in the
USBSTS registe r is a ’1 , the h ost co ntroller will issue an
interrupt. The interrupt is acknowledged by software clearing
the Frame List Rollover bit.
R/W
2Port Chang e In te rrup t
Enable
When this b it is a ’1’ and the Port Chang e Dete ct b it in the
USBSTS registe r is a ’1 , the h ost co ntroller will issue an
interrupt. The interrupt is acknowledged by software clearing
th e Port C hange Detec t bit .
R/W
1USB Error Interrupt
Enable
When this b it is a ’1’ an d the USB ERRIN T bit in the US B S TS
regi ste r is a ’1 , the ho st controller will issue a n in te rrupt at
the next interr up t th re shold. The interrup t is acknowledged
by software by c learing the USBERRINT bit in the U SBSTS
register.
R/W
0USB Interrupt Enable
When this b it is a ’1’ and the US B IN T bit in the USB ST S
regi ste r is a ’1 , the ho st controller will issue a n in te rrupt at
the next interr up t th re shold. The interrup t is acknowledged
by software by c learing the USBINT bit in the USBSTS
register.
R/W
NOTES:
1. For all ena b le register bits, 1= Ena b le d , 0= Disabled.
2. This regist er enabl es and dis abl es repor ti n g of the corres pon di ng i nterr upt to the soft wa r e. When a bit is set
an d the cor re sp ond ing interrupt is active, an interrupt is generated to the hos t. Inte rrup t sour ce s that are
dis a bl ed in th is register still ap p e a r in th e Status Registe r to a llow the soft ware to poll for eve n ts. Ea ch
interrupt enable bit description indicates whether it is dependent on the interrupt threshold m echanism (see
Section 4 of the EHCI S p e cif ication), or not.
Device: 29 Function: 7
Offset: CAPLENG TH + 08-0Bh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 515
11—Intel® 6300ESB ICH
DWORD. Word and byte writes produce undefined results. This register cannot be
written unless the Host Con troller is in the Halted state as indicated by the HCHalted bit
(USB EHCI STS register). A write to this register while the Run/Stop bit is set to a ‘1
(USB EHCI CMD register) produces undefined results. Writes to this register also effect
the SOF value. See Section 4 of the EHCI Specification for details.
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Please refer to Section 4 of the EHCI Specification for a detailed
explanation of the SOF value management requirements on the host controller. The
value of FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token
value. The SOF value may be implemented as an 11-bit shadow register. For this
discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every 8
micro-frames. (1 millisecond). An example implementation to achieve this behavior is
to increment SOFV each time the FRINDEX[2:0] increments from a ’0’ to a ’1’.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for high-speed isochronous scheduling purposes and to provide the get micro-
frame number function required to client drivers. Therefore, the value of FRINDEX and
the value of SOFV must be kept consistent when the chip is reset or software writes to
FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to
SOFV[10:0]. To keep the update as simple as possible, software should ne ver write a
FRINDEX value where the three least significant bits are 111b or 000b.
11.2.2.5 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control
Data
Structure Segment Register
Note: This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the Intel® 6300ESB ICH hardwir es the 64-bit Addressing
Capability field in HCCPARAMS to ‘1’, then this register is used with the link pointers to
construct 64-bit addresses to EHCI control data structures. This register is
concatenated with the link pointer from either the PERIODICLISTBASE,
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all contro l data structures within the
same 4 Gbyte memory segment.
Table 415. Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
Bits Name Description Access
31:1
4Reserved Reserved.
13:0 Frame List Current
Index/Frame Number
The value in this register increments at the end of each time
fr ame (e.g., mic ro-f r ame) .
Bits [12:3] are used for the Frame List current index. This
means that each location of the frame list is accessed eight
times (frames or micro-frames) before moving to the next
index.
Device: 29 Function: 7
Offset: CAPLENGTH + 0C-0Fh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
516 Order Number: 300641-004US
11.2.2.6 Offset CAPLENGTH + 14 - 17 h: PERIODICLISTBASE—
Periodic Frame
List Base Address
Note: This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory . Since the Intel® 6300ESB IC H h ost control l er ope ra tes i n 64-bit m ode
(as indicated by the ‘1’ in the 64-bit Addressing Capability field in the HCCSPARAMS
register), then the most significant 32 bits of every control data structure address
comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
Controller to step through the Periodic Frame List in sequence.
11.2.2.7 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
Asynchronous List Address
Note: This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the Intel® 6300ESB ICH host controller operates in 64-bit mode (as
indicated by a ‘1’ in 6 4-bit Addressing Capability field in the HCCP ARAMS register), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. Bits [4:0] of this register cannot be modified by system
software and will always return ‘0’s when read. The memory structure referenced by
this physical memory pointer is assumed to be 32-byte aligned.
Table 416. Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data
Structure Segment Register
Bits Name Description Access
31:0 Upper Address[63:32] This 32-bit fie ld corres po n ds to addres s bit s 63:32 when
forming a control data struc tu re a ddre ss. RW
Ta ble 417. Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
List Base Add ress
Bits Name Description Access
31:1
2B ase Addres s (Low) These bits c o rre sp ond to m em o ry a ddr e ss signa ls [31:12],
respectively. RW
11:0 Reserved Reserved. Mus t be wri tte n as ‘0’s. During runtime, the value
of the se bits are undefi ned.
Device: 29 Function: 7
Offset: CAPLENG TH + 10-13h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Device: 29 Function: 7
Offset: CAPLENG TH + 14-17h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 517
11—Intel® 6300ESB ICH
11.2.2.8 Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure
Flag Register
11.2.2.9 PORTSC- Port N Status and Control
Note: A hos t controller must implement o ne or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This regist er is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
1. No device connected.
2. Port disabled. When a device is attached, the port state transitions to the attached
state and system software will process this as with any status change notification.
Refer to Section 4 of the EHCI Specification for operational requirements for how
change events interact with port suspend mode
3. When a port is being used as the Debug Port, the port may report device connected
and enabled when the Configured Flag is a ’0’.
Tab l e 41 8. Offs e t CAPL EN G TH + 18 - 1Bh : ASY NCLI ST AD DR Cur r ent
Asynchronous List Address
Bits Name Description Access
31:5 Link Pointer L ow (L PL) T h e se bits corres pond to m e mory add re ss signal s [ 31: 5],
respectively. This field may only reference a Queue Head
(QH). RW
4:0 Reserved Reserved. These bits are reserved and their value has no
effect on operation.
Table 419. Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag Register
Bits Name Description Access
31:1 Reserved Res er ved . Read from this f ie ld will a lways ret u rn 0.
0Configure Flag (CF)
Default 0b. Host software sets this bit as the last action in its
proc es s of con f ig u ring th e Host Controller. This bit controls
the default port-routing control logic. Bit values and side
effects are listed below. See Section 4 of the EHCI
Specification for operational details.
0 = Por t routing control logic default–routes each port to the
classic host controllers.
1 = Port routin g control logic def au lt–rout es a ll p orts to this
ho st cont rolle r.
RW
Device: 29 Function: 7
Offset: CAPLENG TH + 18-1Bh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Device: 29 Function: 7
Offset: CAPLENG TH + 40-43h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
518 Order Number: 300641-004US
Table 420. PORTSC- Port N Status and Control (S heet 1 of 4)
Bits Name Description Access
31:2
3Reserved Reserve d. The se bi ts a re re se rved for futu re use a nd will
return a value of ’0 ’ wh en read .
22 Wa ke on Ov er-cu rre nt
Enable (WKOC_ E)
Default = 0b. Writing this bit to a ’1’ enable s th e sett ing of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Over-current Active bit
(bit 4 of this regi ste r) is s et .
R/W
21 Wake on Disconnec t
Enable (WKDSCNNT_E)
Default = 0b. Writing this bit to a ’1’ enable s th e sett ing of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Current Connect Status
changes from conne cted to d isco nne cted (i.e ., bit ’0’ of this
register changes from ’1’ to ‘0’).
R/W
20 Wake on Connect Enable
(WKCNNT_E)
Default = 0b. Writing this bit to a ’1’ enable s th e sett ing of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Current Connect Status
chang e s from dis con ne cted to connecte d ( i.e ., bit ’0’ of th is
register changes from ’0’ to ‘1’).
NOTE: This featur e is not su p ported.
R/W
19:1
6Port Te st Control
Default = 0000b. When t his field is ’0’, the port is NOT
operatin g in a te st mode. A non-’ 0’ value in d icate s that it is
operating in test mode and the specific test mode is indicated
by the specific value. The encoding of the test mode bits is
(0110b - 1111b are reserved):
Bits Test Mode
0000b Test mode not e nab le d
0001b Test J_STATE
0010b Test K_STATE
0011b Test SE0_NA K
0100b Test Packet
0101b Te st FORCE_ENABLE
Refer to Chapter 7 of the USB Specification, Revision 2.0, for
details on ea ch t e st mode.
R/W
15:1
4Reserved Shou ld be written to =00b ; othe r value s will result in
unspecified behavior. R/W
13 Port Owner
Default = 1b. This bit uncond itiona lly goes to a ’0’ when the
Configure d Flag bit makes a ’0’ to ’1’ transition.This bit
unco ndi tion all y goes to 1b whenever the Configure Flag bit i s
’0’
System software uses this field to release ownership of the
port to a selected h ost controller in t he even t that th e
att ac hed device i s not a h i gh- s peed devi c e. So ftw ar e w r i tes a
’1’ to this bit when the atta ched dev ic e is not a high-speed
device. A ’1’ in this bit means that a companion hos t
contr olle r owns and controls the po rt. See S e ction 4 of the
EHCI Specification for operational d e tails.
R/W
12 Port Power (PP) R ead-only with a value of ‘1’ . This indicates that the port d oe s
have power. RO
Device: 29 Function: 7
Offset:
Port 0:CAPLEN G TH+44-47h
Port 1: CAPLEN GTH+48-4Bh
Port 2: CAPLEN GTH+4C-4Fh
Port 3: CAPLEN GTH +50-53h
Attribute: Read/Write
Defau lt Value: 00003000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 519
11—Intel® 6300ESB ICH
11:1
0Line Status
These bits reflect the c urrent logical levels of the D+ (bit 11)
and D- (bit 10) signal l ines. Thes e bits are used for detec tion
of low-speed USB devices prior to the port reset and enable
sequ e nce . This field is valid o nly when the port en able bit is
’0’ a nd th e cu rre n t conne ct st at us bit is se t to a ’1 .
The encoding of the bits are:
Bits[11:10] Meaning
00 SE0 - Not Low-speed device, perform EHCI
reset
10 J-state - Not Low-speed device, perform EHCI
reset
01 K - state - Low s pee d device, release o wner ship
of port
11 Undefined - Not Low- s peed devic e, perfor m
EHCI reset
RO
9 Reserved Reserved. This bit will re tu rn a ’0’ when rea d .
8Port Reset
Def a u lt = 0
1 = Port is in Reset.
0 = Port is not in Reset.
When software writes a ’1’ to this bit from a ’0, the bus reset
sequ e nce a s d e fi n e d in the US B Specifica tion Revision 2.0 is
starte d . Software writes a ’0’ to this bit to terminate the bus
reset sequence. Software must keep this bit at a ’1’ long
enough to ens ure the re set s equence , as s pec ifi ed i n t he U SB
Specification Revision 2.0, completes.
NOTE: When software writes this bit to a ’1’, it must also
write a ’0’ to the Port Enable bit. When software writes
a ’0’ to this bit there ma y be a delay before the bit
status changes to a ’0’. The bit status will not read as
a ’0’ until after the rese t has com p let ed. Whe n the
port is in high-speed mode after reset is complete, the
hos t controller will auto ma tically enable this port
(e.g. , se t the P ort Enable bit to a ’1’). A host controller
must terminat e the r eset and stab ilize t he s tate of the
port within 2 millise conds of software transitioning
this bit from a ’1’ to a ’0’.
For example: If the por t detects that the attached dev ice is
high-speed dur ing reset, then the host controller must have
the p ort in the enabled state within 2ms of so ftware writing
this bit to a ’0’. The H CHa lte d bi t in the U SBSTS re g ister
should be a ’0’ bef ore sof tware a ttempts to use this bit. The
ho st co nt r oll er ma y hol d P o rt R e set as ser ted to a ’1 ’ wh en t he
HCHalted bit is a ’1’. This field is ’ 0’ if Port Power is ’0’.
Warning:S ystem software should not attempt to reset a port
when the HCHalted bit in the USBSTS register is a
’1’. Doing so will result in undefined behavior.
R/W
Table 420. PORTSC- Port N Status and Control (Sheet 2 of 4)
Bits Name Description Access
Device: 29 Function: 7
Offset:
Port 0:CAPLEN G TH+44-47h
Port 1: CAPLEN GTH+48-4Bh
Port 2: CAPLEN GTH+4C-4Fh
Port 3: CAPLENGTH+50-53h
Attribute: Read/Write
Defau lt Value: 00003000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
520 Order Number: 300641-004US
7Suspend
1 = Port in su spend st a te . 0 = Port not in suspend state .
Default = 0. Port Enabled B it a nd Susp en d bit of this reg ister
define the port states as follows:
Bit s [Port Enabled, Suspend]Port State
0X Disable
10 Enable
11 Suspend
When in suspend state, downs tream propag ation of data is
blocked on this por t, excep t fo r po rt re set. N ote tha t the bit
status does not change until the port is suspended and that
there may be a delay in suspendi ng a port depending on the
activity on the port.
The hos t cont roller will unconditionally set this bi t to a ’0’
when software sets the Force Port Resume bi t to a ’0’ (from a
‘1’). A write of ’0’ to this bi t is ignore d by the host con trolle r.
When h ost so ftwar e sets this bit to a ’1’ whe n the port is not
enabl ed (i.e., Port enabled b it is a ’0’), the results are
undefined.
R/W
6Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-
state) d e tected/driven on port. Defa ult = 0.
Software se ts this bit to a ’1’ to dr ive resume signaling . The
Host Controller sets this bit to a ’1’ when a J-to-K transition is
det ected whil e th e po rt is in the S uspend state. When th is bit
tr ansitions to a ’1’ because a J-to-K transition is d etected, the
Port Change Detect bit in the USBSTS register is also set to a
’1’. When softwar e sets this bit to a ’1’, the host controller
must not set the Port Chan ge D etec t bit .
Note that when the E HCI controller owns the port, the
resume sequence follows the defined sequence documented
in the US B Sp e cif icat ion Revision 2. 0. The re su me signa ling
(Full-speed 'K') is driven on the p ort a s long as this bit
remains a ’1’. Sof t ware mu st appropriate ly time the Resume
and set this b it to a ’0’ wh en the ap p rop ria te a mount of time
has elapsed . Writing a ’0’ (from ‘1’) causes the port to return
to high- s peed mode (fo rci ng the bus belo w the port into a
high-sp e e d idle ). This bit will remain a ’1’ until th e port has
swi tch ed to the high -spe ed idle.
R/W
5 O vercurrent Change
Default = 0. 1 = T his bit gets set to a ’1’ when there is a
change to Over-c urre nt A ctiv e . Software clears this bit by
writing a ’1’ to this bit posit ion.
The functio na lity of this bit is not depe nd e nt upo n the port
owner.
R/WC
Table 420. PORTSC- Port N Status and Control (S heet 3 of 4)
Bits Name Description Access
Device: 29 Function: 7
Offset:
Port 0:CAPLEN G TH+44-47h
Port 1: CAPLEN GTH+48-4Bh
Port 2: CAPLEN GTH+4C-4Fh
Port 3: CAPLEN GTH +50-53h
Attribute: Read/Write
Defau lt Value: 00003000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 521
11—Intel® 6300ESB ICH
4 Overcurrent Active
Def ault = 0. 1 = This port currently has an over-current
condition.
0 = This port does not have an over-current condition. This
bit will automatic ally trans ition f rom a ’1’ to a ’0’ when th e
over cu rre nt condition is re moved.
The Intel® 6300ESB ICH automatically disables the port when
the over-curre nt a ctive bit is ‘1’.
RO
3Port Enable/D isa b le
Change
0 = N o ch an g e in sta tu s. This is the de faul t setting .
1 = Por t enabled/disabled status has changed.
For the root hub, this bit gets set to a ’1’ only when a po rt is
disabled due to the appropriate conditions exi sting at the
EOF2 point. (See Chapter 11 of the US B Spe cification for the
defi nition of a por t er ror.) This bit is not set due to the
Disable d -to-Enabled transitio n, nor d u e to a disc onnect.
Software cle ars th is b it by writing a ’1’ to it.
R/WC
2 P o rt E nab l ed/ Dis a bl ed
1 = Enable. 0 = Dis a b le. Def a ult = 0. Ports may only be
enabled by th e host controller as a part of the rese t and
enab le . So ftware cannot ena b le a port by writing a ’1 ’ to this
field. Ports may be disabled by either a fault condition
(disconnect event or other fault condition) or by host
softwar e. Note that th e bit statu s do es not change until the
port state ac tually chang es. Ther e may be a delay in di sabling
or enab lin g a por t due to other host controller and bus
events.
R/W
1Connect Status Change
1 = Change in Current Connect Status. 0 = No change.
De fault = 0. In dic a te s a ch an g e has occ urred in the port’s
Curre nt Conne ct Status. The host controller sets this bit for
all changes to the port device con nect statu s, even when
system soft wa re h a s no t cleare d an e x ist in g con nect sta tu s
change. For example, the in sertion sta tus chan g e s t wice
before system software has cleared the changed condition,
hub hardware will be “setting” an already-set bit (i.e. , the bit
will remain set). Software sets this bit to ’0’ by writing a ’1’ to
it.
R/WC
0 Current Conne ct Status
1 = Device is present o n port. 0 = No device is present.
Default = 0. This value refle cts the curre nt state of the port,
and may not correspond directly to the event that caused the
Conne ct S tatus Chang e b it (B it 1) to be set.
RO
Table 420. PORTSC- Port N Status and Control (Sheet 4 of 4)
Bits Name Description Access
Device: 29 Function: 7
Offset:
Port 0:CAPLEN G TH+44-47h
Port 1: CAPLEN GTH+48-4Bh
Port 2: CAPLEN GTH+4C-4Fh
Port 3: CAPLENGTH+50-53h
Attribute: Read/Write
Defau lt Value: 00003000h Size: 32-bit
11—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 522
11.2.3 USB 2.0-Based Debug Port Register
The Debug Port’s registers are located in the same memory area, defined by the Base
Address Register (BAR) as the standard EHCI registers. The base offset for the debug
port registers is declared in the Debug Port Base Offset Capability Register at
Configuration offset 5Ah. The specific EHCI port that supports this debug capability is
indicated by a 4-bit field (bits 20-23) in the HCSPARAMS register of the EHCI controller.
The map of the Debug Port registers is shown below. Each register is defined
individually.
11.2.3.1 Offset 0 0h: Control/Status Register
Offset Register Type
00h Control/S tatus Regist er Re ad /Write
04h U S B PIDs Read/Write
08h D ata Bu f fer (Byte s 3:0) Read/Write
0Ch Data Buffer (By tes 7:4) Read/Write
10h Confi g Register R ead/ Write
NOTES:
1. All of these registers are implemented in the core well and reset by PXPCIRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
2. The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed illegally is
undefined.
Table 421. Offset 00h: Control/Status Register (Sheet 1 of 3)
Bits Name Description Access
31 Reserved. Reserved.
30 OWNER_CNT
When softwa re write s a ’1’ to this bit, the ow ner ship of the
debug po rt is f orce d to th e EH CI con troller (i.e., im me d ia te ly
taken away from the companion Classic USB Host Controller).
When the port was already owned by the EHCI controller,
setting this bit has no effec t. This bit overrid e s all of the
owners h ip -re la te d bit s in th e stan d ard EH CI re gis te rs. Rese t
default i s ’0.
R/W
29 Reserved Reserved.
28 ENABLED_CNT
This bit = ’1’ when the debug port is enabled for operation.
Software may clear this by writing a ’0’ to it. The hardware
clears t he bit f or th e sa me condition s where the Po rt E na b le/
Disable Change bit (in the PORTSC register) is set. Software
may di r ectly set thi s bit when the port is already enabl ed in
the associated Port Status and Control register (this is
enforced by the hardwa re). Reset default is ’0’.
27:1
7Reserved Reserved.
Device: 29 Function: 7
Offset: 00h Attribute: Read/Write
Defau lt Value: 0000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 523
11—Intel® 6300ESB ICH
16 DONE_STS This bit is set b y hardwa re to ind icate that the reque st is
complete. Writing a ’1’ to this bit will clear it whe n it is set.
Writing a ’0’ to this bit has no effect. Reset de fau lt is ’0’. R/WC
15:1
2LINK_ID_STS This field ide ntif ie s the link interface . It is ha rd wired to 0h to
indicate that it is a USB Debug Port. RO
11 Reserved Reser ved . This bit wi ll re tu rn ’ 0’ whe n re ad . Writes will have
no effec t.
10 IN_USE_CNT
Set by software to indicate that the port is in use. Cleared by
softw are to in di ca te t hat t he por t is free and may be use d by
other software. This bit is cleared after reset. (This bit has no
affect on hardware.)
9:7 EXCEPTION_STS
Default=000b
This field indicates the exception when the
ERRO R_G OOD#_STS bit is se t. This field should be ig nore d
when the ERROR_GOOD#_STS bit is 0.
000 No Error.
Note: This should not be seen, since this field should only be
check ed when there is an error.
001 Transact ion error: Indicates the US B EHCI
transac tion had an error (CRC, bad PID, timeout, etc.)
010 Hardware error: Re q u e st was atte mp te d (or in
prog re ss) when port was suspended o r re se t.
All Others are reserved.
RO
6 ERROR_GOOD#_STS
The hardware cle ars this bit to ’0’ upon the proper completion
of a rea d or write . The hard wa re se ts this bit to in dica te tha t
an error has occurred. Details on the nat u re of the e rror are
provided in the Exception field. Reset default = 0.
RO
5GO_CNT
0 = Hard wa re cle ars th is b it whe n ha rd ware se ts the
DONE_STS bit. Default is 0.
1 = Causes hard ware to perf orm a read or wr ite request.
Writing a ’1’ to this bit when it is already set may result in
undefi ned behavior.
WO
Table 421. Offset 00h: Control/Status Register (Sheet 2 of 3)
Bits Name Description Access
Device: 29 Function: 7
Offset: 00h Attribute: Read/Write
Defau lt Value: 0000h Size: 32-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
524 Order Number: 300641-004US
4WRITE_READ#_CNT:
Software sets this bit to indicate that the current request is a
write. Sof twa re cle ars this bit to indicate that the current
requ est is a re ad.
Reset default is ’0’.
R/W
3:0 DATA_LEN_CNT
This field is us ed to indicate the size of the data to be
tran sf e rre d . Reset default = 0h.
For write operations, this field is set by software to indicate to
the hardware how many bytes of data in Data Buffer are to be
tr ansferred to the console. A value of 0h indicates that a zero-
length pac ket shoul d be sent. A value of 1-8 ind icates 1-8
bytes are to b e t ransferred. Values 9-Fh a re ille gal, and how
hardware b ehav es when used is undefined.
For read operations, this f ie ld is set b y hardware to indicate to
software how many bytes in Data Buffer are valid in response
to a read operation. A value of 0h indicates that a z ero-l ength
packet was returned and the state of D ata Buffer is not
defined. A value of 1-8 indicates 1-8 bytes wer e rec e ived.
Hardwa re is not allowed to retur n values 9-Fh.
The transferring of data always starts with byte ’0’ in the data
area and m oves toward b yte 7 until the transfe r siz e is
reached.
R/W
NOTES:
1. Software should do Read-Mo dify-Write operations to this regist er to preserve the contents of bits not being
modified. This include R e served b its.
2. To pres er ve the us age o f Res er ve d bi ts in the f uture, softw ar e s hould al wa y s wr ite the s a me va lu e read fr om
the bit unti l it is defined. Res er ved bit s will alw a ys return ’0 ’ when read.
Table 421. Offset 00h: Control/Status Register (Sheet 3 of 3)
Bits Name Description Access
Device: 29 Function: 7
Offset: 00h Attribute: Read/Write
Defau lt Value: 0000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 525
11—Intel® 6300ESB ICH
11.2.3.2 Offset 04h: USB PIDs Register
11.2.3.3 Offs et 08h: Data Buffer Bytes 7:0
Table 422. Offset 04h: USB PIDs Register
Bits Name Description Access
31:2
4Reserved Reserve d. Th e se bi ts will re turn ’0’ when read. Writes w ill
have no effect.
23:1
6RECEIVED_PID_STS[23:
16]
The hardware updates this field with the received P ID for
transactions in either direction. Whe n the controller is writing
data, this fie ld is update d with the hand shake PID that is
received from the device. When the host controller is reading
data, this field is updated with the data packet PID (when the
device se n t data), or the handsha ke PI D (when the device
NAKs the request). This field is valid when the hardware
clears th e GO_D ONE#_CNT bit.
15:8 SEND_PID_CNT[15:8]
The hardware send s this PID to be gin the data pac ket when
sending data to U SB (i.e ., WRITE_REA D #_CN T is asserted).
Softwar e will typically set this f ie ld to eithe r D ATA 0 or D ATA 1
PID values .
7:0 TOKEN_PID_CNT[7:0]: The hardware sends this PID as the Token PID for each USB
tr ansaction. Software will typically set this field to either IN,
OUT or SETUP PID values.
NOTE: This DWORD register is used to communicate PID information between the US B debug driver and the
USB debug port. The debug port uses some of these fields to generate USB packets, and uses other fields
to return PID inf ormation to the USB deb ug dri ver.
Table 423. Offset 08h: Data Buffer Bytes 7:0
Bits Name Description Access
63:0 DATABUFFER[63:0
These are the 8 bytes of the data buffer. Bits 7:0 correspond
to least significant byte (byte 0). Bits 63:56 correspond to the
most sig nif icant byte (byte 7).
The bytes in the Data Buffer must be written with data before
softwar e ini tia te s a write re q ue st. For a read request, the
Data Buffer contains valid data when DONE_STS bit is cleared
by the hardware , ERROR_GOOD#_STS is cleared by the
hardware , and the DATA_L EN G TH_CNT field indic ate s the
number of bytes that are v alid.
NOTE: This regi ster may be accessed as eight separate 8-bit registers or t wo separate 32-bit r egisters.
Device: 29 Function: 7
Offset: 04h Attribute: Read/WRite
Defau lt Value: TBD Size: 32-bit
Device: 29 Function: 7
Offset: 08h Attribute: Read/Write
Defau lt Value: 0000000000000000h Size: 64-bit
Intel® 6300ESB ICH—11
Intel® 6300ESB I/O Controller Hub
DS November 2007
526 Order Number: 300641-004US
11.2.3.4 Offset 10h: Config Register
Table 424. Offset 10h: Config Register
Bits Name Description Access
31:1
5Reserved Reserved.
14:8 USB_ADDRESS_CNF This 7-bit field identifies the USB device addr ess used by the
controller for all Token PID generation. This is a R/W field that
is set to 7Fh after re se t.
7:4 Reserved Reserved.
3:0 USB_ENDPOINT_CNF This 4-bit field identifies the endpoint used by the controller
for all Token PID gene ra tion. This is a R/W fiel d that is se t to
01h afte r re se t.
Device: 29 Function: 7
Offset: 10h Attribute: Read/Write
Defau lt Value: TBD Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 527
12—Intel® 6300ESB ICH
SMBUS Controller Regist ers
(D31:F3) 12
12.1 PCI Configuration Registers (SMBUS—
D31:F3)
12.1.1 Offset 00 - 01h: VID—Vendor Identification
Register (SMBUS—D31 :F3)
Offset Mnemonic Register Name/
Function Default Type
00-01h VID V endor ID 8086 RO
02-03h DID Device ID 25A4 R O
04-05h CMD Command Register 0000h R /W
06-07h STA Dev ice St atus 0 280h R /W
08h RID Revision ID See Note 1 RO
09h P I Pr og ramming Inte rf ace 00h R O
0Ah S CC Sub Cla ss Code 05h R O
0Bh B CC Base Class Code 0Ch RO
20-23h SMB_BASE SM Bus Base Address
Register 00000001h R/W
2C-2Dh SV ID Subsystem Vendor ID 0000h RO
2E-2Fh SID Subsystem ID 0000h RO
3Ch INTR_ LN Interrupt Line 00h R/W
3Dh IN T R_PN Interrupt Pin 02h R O
40h HOS TC Ho st Config uration 00h R/W
NOTES:
1. Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the value of the
Re vi sion I D Register.
2. Registers tha t a re n ot sh own should be treat ed a s Res er ve d (See S ection 6.2, “P CI
Conf iguration Map” on page 277 for details).
Table 425. Offset 00 - 01h: VID—Vendor Identification Register (SMBUS
D31:F3)
Bits Name Description Access
15:0 Vendor ID Value This is a 16-b it value assigned to Intel. RO
Device: 31 Function: 3
Offset: 00-01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
528 Order Number: 300641-004US
12.1.2 Offset 02 - 03 h: DID—Dev ice Identification
Register (SMBUS—D31:F3)
12.1.3 Offset 04 - 05h: CMD—Comma nd Re gister
(SMBUS—D31:F3)
Table 426. Offset 02 - 03h: DID—Device Identification Register (SMBUS—
D31:F3)
Bits Name Description Access
15:0 Dev i ce ID value RO
Table 427. Offset 04 - 05h: CMD—Command Register (SMBUS—D31:F3)
Bits Name Description Access
15:1
0Reserved Reserved.
9Fast Back-to-B a ck
Enable (FBE) Res er ved a s ‘0. RO
8SERR # Ena ble
(SERREN) Reser ved a s ‘0. R O
7Wait Cycle Control
(WCC) Reserv ed as ‘0 . RO
6Parity Error R esponse
(PER) Re se rv ed as ‘0’. R O
5VGA Palette Snoop
(VPS) Reser ved as ‘0’. RO
4Postable Memory Write
Enable (PMWE) Reser ved as ‘0’. RO
3Spe cia l Cy cle E na b le
(SCE) Rese rv ed as ‘0’. R O
2Bu s M a st e r En a b l e
(BME) Reser ved a s ‘0. R O
1Memory Space Enable
(MSE) Reser ved as ‘0’. RO
0 I/O Space Enable (IOSE) 0 = Disabl e
1 = E n a bl es access to the SM Bus I/O space regi sters as
defined by the Base Address Register. R/W
Device: 31 Function: 3
Offset: 02-03h Attribute: Read-Only
Defau lt Value: 25A4h Size: 16-bit
Device: 31 Function: 3
Offset: 04-05h Attribute: Read-Only, Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 529
12—Intel® 6300ESB ICH
12.1.4 Of fset 06 - 0 7h: STA—De vice Status Re gis te r
(SMBUS—D31:F3)
12.1 .5 Offset 08h: RID—Revision ID Re gister (SMBUS—
D31:F3)
Table 428. Offset 06 - 07h: STA—Device Status Register (SMBUS—D31:F3)
Bits Name Description Access
15 Dete cte d Parity Error
(DPE) Reserved as 0’. RO
14 Signa l ed Syst em Erro r
(SSE) Reserved as ‘0. RO
13 Rece ived M a ste r Abort
(RMA) Reserved as ‘0. RO
12 Received Target Abort
(RTA) Reserved as ‘0. RO
11 Signal ed Target - A bo rt
Status Reserved as ‘0. R/WC
10:9 DEVSEL# Timing Status
(DEVT) Reserved as ‘0. RO
8Data Parity Error
Detected Reserved as ‘0. RO
7Fast Back - t o- Bac k
Capable Reserved as0’. RO
6User D efi na ble Features
(UDF) Reserved as ‘0. RO
5 66 MH z Capab le R ese rv ed as ‘0’. RO
4:0 Reserved Reserved.
T abl e 42 9. Of fs e t 08h : RID—R ev i si on ID Re gis t e r (S MB U S— D 31 : F3)
Bits Name Description Access
7:0 R evision ID Value Refer to the Inte l® 6300ESB I/O Controller Hub Specification
Update for the most up-to-date value of the Revision ID
Register. RO
Device: 31 Function: 3
Offset: 06-07h Attribute: Read-Only, Read/Write Clea r
Defau lt Value: 0280h Size: 16-bit
Device: 31 Function: 3
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descript io n Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
530 Order Number: 300641-004US
12.1.6 Offse t 0 9h: PI—Programm i ng Interface (SMBUS—
D31:F3)
12.1.7 Offset 0Ah: SCC —Sub Class Code R egister
(SMBUS—D31:F3)
12.1.8 Offse t 0 Bh: BCC—Base Class Code Regist er
(SMBUS—D31:F3)
Table 430. Offset 09h: PI—Programming Interface (SM BUS—D31:F3)
Bits Name Description Access
7:0 Pro gramming Interface RO
Table 431. Offset 0Ah: SCC—Sub Class Code Register (SMBUS—D31:F3)
Bits Name Description Access
7:0 Su b Cla ss Code 05h = SM Bus serial controller RO
Table 432. Offset 0Bh: BCC—Base Class Code Register (SMBUS—D31:F3)
Bits Name Description Access
7:0 B ase Class Code 0Ch = Se rial controller. RO
Device: 31 Function: 3
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 05h Size: 8-bit
Device: 31 Function: 3
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 0Ch Size: 8bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 531
12—Intel® 6300ESB ICH
12.1.9 Off set 20 - 23h: SM B_BASE—SMBUS Base Ad dress
Register (SMBUS—D31 :F3)
12.1.10 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
(SMBUS—D31:F2/F4)
Table 433. Offset 20 - 23h: SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)
Bits Name Description Access
31:1
6Reserved Reserved. RO
15:5 Base Address Provides the 32-byte s ystem I/O base address for the Intel®
6300ES B IC H SMB log ic. R/W
4:1 Reserved Reserved. RO
0IO Space Indicator
This read-only bit is always ‘1’, indicating that the SMB logic is
I/O mappe d . RO
T abl e 43 4. Of fs e t 2C h - 2Dh : SV I D— Su bs y s tem Ve n dor ID (SMB US D3 1: F 2 /
F4)
Bits Name Description Access
15:0 Subsystem Vendor ID
(SVID)
The SVID register, in combination with the Subsystem ID
(SID) register, enables the operati ng system (OS) to
distingui sh subsyst ems from each othe r. The value re tu rned
by reads from this register is the same as that which was
writte n by BI OS into the IDE_SV ID regis te r.
RO
Device: 31 Function: 3
Offset: 20-23h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 3
Offset: 2Ch-2Dh Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
532 Order Number: 300641-004US
12.1.11 Offset 2Eh - 2Fh: SID—Sub sys tem ID (SMBUS—
D31:F2/F4)
12.1.12 Offse t 3 Ch: INTR_LN—Interrupt Line Register
(SMBUS—D31:F3)
12.1.13 Offse t 3Dh: INTR_P N—Interrupt Pin Reg i st er
(SMBUS—D31:F3)
Table 435. Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/ F4)
Bits Name Description Access
15:0 Subsystem ID (SID)
The S I D register, in combinat ion w ith the SV I D register,
enab les th e op erat i ng s ys tem ( OS) to disti ngu is h s ubsy stems
from each other. The value returned by reads from this
registe r is the sa me as that wh ich wa s writte n by B IOS into
the IDE_SID register.
RO
Table 436. Offset 3Ch: INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Bits Name Description Access
7:0 Inte rru p t lin e This d ata is not used by the Intel® 6300ESB ICH. It is to
commu nicate to sof tware th at the inte rru p t lin e is connected
to PIRQB#. R/W
Table 437. Offset 3Dh: INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Bits Name Description Access
7:0 Inte rrupt PIN 02h = Indicates that the Intel® 6300ESB ICH SMBus
Contr olle r will driv e PIRQB # a s its interrupt line . RO
Device: 31 Function: 3
Offset: 2Eh-2Fh Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 3
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 02h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 533
12—Intel® 6300ESB ICH
12.1.14 Off set 40h: HOSTC—Host C onfiguration Register
(SMBUS—D31:F3)
12.2 SMBUS I/O Registers
Table 438. Offset 40h: HOSTC—Host Configuration Register (SMBUS—D31:F3)
Bits Name Description Access
7:3 Reserved Reserved.
2I
2C_EN
0 = SMB us behavior.
1 = The In te l® 6300ESB ICH is enable d to communicate with
I2C devic e s. This will change th e fo rma tting of som e
commands.
R/W
1 SMB_SMI_EN
0 = SM B us inte rrupts will not g e ne rate an S MI#.
1 = A ny source of an SMB interrup t wi ll i nst e ad be rou te d to
generate an SM I#. Refer to Se ction 5.19.5, “Interru pts /
SMI#”.
This bit needs to be set for SMBAL ERT# to be enabled.
R/W
0HST_EN: SMBus Host
Enable
0 = D isable the SMBus Host Contr olle r.
1 = Ena b le . The S M B Host Con troller interf a ce is enab le d to
execute commands. The INTREN bit must be enabled for
the SMB Hos t Controller to interrupt or SMI#. The SMB
Host Controller will not respond to any new requests until
all interrupt requests have been cleared.
R/W
Table 439. SMB I/O Registers (Sheet 1 of 2)
Offset Mnemonic Register Name/Function Default Access
00h HST_STS Host Status 00h R/WC
02h HST_CNT Host Control 00h R/W
03h HST_CMD Host Command 00h R/W
04h XMIT_SLVA Tr ansm i t Slav e Addre ss 00h R/ W
05h H S T _D0 Host Data 0 00h R/W
06h H S T _D1 Host Data 1 00h R/W
07h HOST_B LOCK_DB Host Block Data Byte 00h R/W
08h PEC P ac ket Error Check 00h R/W
09h RCV_SLVA Receive Slave Address 44h R/W
0A-
0Bh SLV_DA TA Slave Data 0000h R/W
0Ch AUX_STS Auxiliar y Sta tus 00h R/WC
0Dh AUX_CTL Auxiliary Control 00h R/W
Device: 31 Function: 3
Offset: 40h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
534 Order Number: 300641-004US
12.2.1 Offse t 00h: HST_STS—Host Status Register
Note: All status bits are set by hardware and cleared by the software writing a ‘1’ to the
particular bit position. Writing a ‘0’ to any bit position has no effect.
0Eh SMLINK_PIN_CT L SMLink Pin Contr ol See regi ster
description R/W
0Fh SM B US_PIN _CT L S M Bu s Pin Co ntrol See register
description R/W
10h SLV_STS Slave Status 00h R/WC
11h SLV _CMD Slave Command 00h R/ W
14h NOTIFY_DAD DR Noti fy Dev ice A d dres s 00h RO
16h NOTIFY_DLO W Noti fy Data L ow By te 00h RO
17h NOTIFY_D HIG H Noti fy Data High B y te 00h RO
Table 439. SMB I/O Registers (Sheet 2 of 2)
Offset Mnemonic Register Name/Function Default Access
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 535
12—Intel® 6300ESB ICH
T abl e 44 0. O ffs e t 00h : HST_ S TS —H o st Sta tu s Re g is te r (S he et 1 of 2)
Bits Name Description Access
7BYTE_DONE_STS
This bit will be set to ’1’ when the host controller has received
a byte (for Block Read commands) or when it has completed
transmission of a byte (for Block Write commands) when the
32-byte buffer is not being used. Note that this bit will be set
even on the last byte of the transfer. Software clears the bit
by writing a ’1’ to the bit position. This bit is not set when
transm ission is due to an exte rna l LAN Controlle r in terface
heartbeat.
This bit has no meaning for block tr ansfers when the 32-b yte
buffer is enabled.
NOTE: When the last byte of a block message is rece ived, the
host controller will set th is b it. Howe ver, it will not
imme d ia te ly set the INT R bit (bit 1 in this re gis te r).
When the interrupt handler clears the
BYTE_D ON E_S TS b it, an other inte rrupt may be
gene rated if the INT R bit is se t. Thus , for a bloc k
me ssage of n bytes, th e I n tel® 6300ESB ICH will
generate n+1 inter rupts. T he interrup t hand ler needs
to be imple men te d to hand le these cases.
R/WC
6INUSE_STS
This bit is used as semaphore among various in dependent
s oftw are threads tha t may ne e d to use th e Intel® 6300ESB
ICH ’s SMBus logic and has no other effect on hardware.
0 = Aft er a full PCI rese t, a read to this b it returns a ‘0’.
1 = Aft er the first re ad, su bs equent re ad s will return a ‘1’. A
write of a ’1’ to this b it will re set the next re ad value to
‘0’. Writing a ’0’ to this bit has no effe ct. Sof tware ma y
poll this bit until it reads a 0 and will then own the usage
of the ho st controller.
R/WC
(special)
5 SMBALERT_STS
0 = Interrupt or SMI# was not generated by SMBA LERT#.
1 = T h e source of t he in terru p t or SM I # was th e SMBA LERT#
si gnal . Thi s bit is o nly clear ed by so ftw a re writ i ng a ’1’ to
the bi t position or by RSMRST# going low.
When the signal is progr ammed as a GPIO , this bit will never
be set.
R/WC
4FAILED
0 = Cleare d by writing a ’1’ to the bit position.
1 = The source of the inte rru p t or S M I# wa s a failed bus
transact ion. This bit is set in re sp onse to the KILL bit
being set to ter minate the host transac tion.
R/WC
3BUS_ERR
0 = Cleare d by writing a ’1’ to the bit position.
1 = The so urce of the inte rrup t of SMI# was a transac tion
collision. R/WC
Device: 31 Function: 3
Offset: 00h Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
536 Order Number: 300641-004US
2DEV_ERR
0 = Softwar e resets this bit by writing a ’1’ to this location.
The I n t el® 6 300ES B ICH will the n d eas sert the inte rrupt
or SMI#.
1 = The source of the inte rrupt or SMI# was due to one of the
following:
- Illegal Command Field
- Unclaimed Cycle (host initiated)
- Host Devic e Time -out Error
- CRC Error
R/WC
1INTR
This bit may b e set on ly by ter mina tion of a comma nd . IN TR
is not dependen t on the IN TREN b it of the Host Controller
Register (offset 02h). It is only d ependent on the termination
of the command. When the INT REN bit is not set, the INTR bit
will be se t, althou g h th e inte rrupt will not be g en erated .
Softwa re may p oll the IN TR b it in th is non-interrupt case .
0 = Software resets this bit by writing ’1’ to this location. The
Intel® 63 00ESB ICH will then deassert the inte rrupt or
SMI#.
1 = The sou rce of the inte rrupt or SMI# was the successfu l
complet ion of its last command.
R/WC
(special)
0HOST_BUSY
0 = Cleared by the Intel® 6300ESB ICH whe n the cur re nt
transaction is complete d.
1 = Indicates that the Inte l® 6300ESB ICH is runni ng a
comma n d from the host in terfac e . No SMB re gisters
should be accessed while this bit is set, except the BLOCK
DA TA BYTE Register. The BLOCK DATA BYTE Register ma y
be accessed when this bit is set only when the SMB_CMD
bits in the Host Control Register are programmed for
Block command or I2C Read command. This i s necessary
in order to check the BYTE _DON E_S TS bit .
RO
Table 440. Offset 00h: HST_STSHost Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 3
Offset: 00h Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 537
12—Intel® 6300ESB ICH
12.2 .2 Offset 02h: HST_CNT—Host Control Reg i ster
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 1 of 3)
Bits Name Description Access
7PEC_EN
0 = SMB us host contro ller does not perform the tran sacti on
with the PEC phase appended.
1 = Cau ses the host controller to perform the SMBus
transaction with the Packet Error Che ck ing phas e
appended. For writes, the value of the PEC byte is
transferre d fro m the PEC Register. For reads, the PEC
byte is lo aded into the PEC Register. This bit must be
writte n pri or to the write in which the START b it is set.
R/W
6START
0 = This bit will always re turn ’0’ on re a d s. The H OS T_BUSY
bit in t he Ho st S ta tu s re gister (o ffse t 00h) may b e u se d
to identify when the Intel® 6300ESB ICH has finis hed the
command.
1 = Writing a ’1’ to this bit initiates the command described in
the SMB_CMD fie ld. All regis te rs sh ould be setup pr ior to
writing a ‘1’ to this bit posi tion.
WO
5 LAST_BYTE
This bit is used fo r Block Read comm a n d s.
1 = Software sets this bit to indicate that the next byte will be
the l as t byte t o be re ceived for the bl ock . This c a uses t he
Intel® 6300ESB ICH to send a NACK (instead of an ACK)
afte r re ce iv in g the last byte.
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register
(D31:F0, TCOBASE+6 h, bit 1) is set, the LAS T_BYTE
bit also gets set. While the SECOND_TO_STS b it is
set, the LAST _B YTE bit can n ot b e clear e d. This
prev ent s the Intel® 6300ESB ICH from running som e
of the SMB us commands (Block Re ad/W rite, I2C R ead,
Block I2C Write).
WO
Device: 31 Function: 3
Offset: 02h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
538 Order Number: 300641-004US
4:2 SMB_CMD
The b i t encoding below ind ica t e s wh ich com ma n d t he Intel®
6300E SB ICH is to pe rf orm. When enabled, the Intel®
6300E SB ICH will generate an interrupt or SMI# when the
comma n d h as comple te d. Whe n th e value is for a non-
supported or reserved command, the Intel® 6300ESB ICH will
set the device error (DEV_ER R) status bit and genera te an
interrupt whe n the START bit is set. The Intel® 6300ESB ICH
will not operate u ntil DEV _E RR is cleared.
000 = Qui ck: The slav e add ress and read/write v alue ( bit 0)
are stored in the transmit slave address register.
001 = Byte: This command uses the transmit slave address
and command registers. Bit 0 of the slave address register
deter mine s if th is is a read or write command.
010 = Byte Data: This command uses the transmit slave
address, command, and DATA0 registers. Bit 0 of the slave
address register determines if this is a read or write
command. When it is a read, the DATA0 register will contain
the read data .
011 = Word Da ta: This command uses the tran smit slave
address, command, DATA0 and DATA1 registers. Bit 0 of the
slave address register determines if this is a read or write
command. When it is a read, after the command completes,
the DATA0 and DATA1 registe rs will contain t he read data.
100 = Process Call: Th is comm an d uses the t ra n smit slave
address, command, DATA0 and DATA1 registers. Bit 0 of the
slave address register determines if this is a read or write
comm an d . A fte r the comm a n d co mpletes, t he DATA0 a nd
DATA1 registers will contain the read data.
101 = Bl o ck: This command uses the transmit slave
address, command, DA TA 0 registers, and the Block Data Byte
register. For block write, the count is stored in the DATA0
register and indicates how many bytes of data will be
transferred. For block reads, the count is received and stored
in the DATA0 register. Bit 0 of the slave address register
selects i f this is a re a d or wr ite command. For write s, d a ta is
retriev ed f rom th e f irst n (where n is equa l to the sp e cif ie d
c o unt) a d d r e sses of the SR A M ar ra y. F o r read s, the d a ta is
stored in the B lock Data Byte regi ste r.
110 = I2C Read: Th is command u se s th e tr an smit slave
address, command, DATA0, DATA1 registers, an d the Block
Data Byte register. The read data is stored in the Block Data
Byte register. The Inte l® 6300ESB ICH will continue reading
data un til th e NAK is re ceived.
111 = Block Process: This command us es the trans mit
slave address, command, DATA 0 and the Block Data Byte
register. For block write, the count is stored in the DATA0
register and indicates how many bytes of data will be
transfe rre d. For block re a d , th e coun t is re ceived an d sto re d
in the DATA0 register. Bit 0 of the slave address register
always indicate a write command. For writes, data is retrieved
from the f irst m (whe re m is equal to the s pec ifi ed count)
addresses of the SRAM array. For reads, the data is stored in
the Block Data B y te registe r.
NOTE: E 32B bi t in the Auxiliary Control registe r must be set
for this co mmand to work .
R/W
Table 441. Offset 02h: HST_C NT—Host Control Register (Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 3
Offset: 02h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 539
12—Intel® 6300ESB ICH
12.2 .3 Offset 03h: HST_CMD—Host Command Register
12.2.4 Of fset 04h: X MIT_SLVA—Transmit Slave Address
Register
Note: This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
1KILL
0 = Normal SMBus Ho st Controller fu nctionality.
1 = W he n set, kills the current host tra nsa ction takin g place,
sets the FAILED status bit, and a sserts the interrupt (or
SMI#). This bit, once set, must be cleared by software to
allow the SMBus Hos t Controller to function normally.
R/W
0INTREN
0 = D isa b le .
1 = Enab le the generation of a n inte rrup t or S MI# up on the
comp le tion of the command. R/W
Table 442. Offset 03h: HST_CMD—H ost Comman d Register
Bits Name Description Access
7:0 This 8-bit fie ld is trans mitted by the host controller in the
command field of the SMBus pr otocol during the execution of
any command. R/W
T abl e 44 3. O f fse t 04h : XM I T_ SL V A— Tr a ns mit Sla ve Addres s Re g is ter
Bits Name Description Access
ADDRESS 7-bit address of the targeted slave. R/W
RW Directi on of the host transfer.
0 = Write
1 = Read R/W
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 3
Offset: 02h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 03h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 04h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
540 Order Number: 300641-004US
12.2.5 Offset 0 5h: HST_D0—Data 0 Regi ster
12.2.6 Offset 0 6h: HST_D1—Data 1 Regi ster
Table 444. Offset 05h: HST_D0—Data 0 Register
Bits Name Description Access
7:0 DATA0/COUNT
Thi s field co ntains th e eight -bit da ta sent in t he DA TA0 f ield of
the SMBus pro tocol. For bloc k write comma nd s, this reg ister
reflects the numb e r of byte s to transfer. This regis te r should
be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in
unpredictable behavior. The host controller does not check or
log illegal block counts.
R/W
Table 445. Offset 06h: HST_D1—Data 1 Register
Bits Name Description Access
7:0 DATA1 This eight-bit registe r is transmitted in the DATA1 f ield of the
SMBu s pr otocol during the exec ution of a ny com man d . R/W
Device: 31 Function: 3
Offset: 05h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 06h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 541
12—Intel® 6300ESB ICH
12.2.7 Of fset 07h: Ho st_BLOCK_DB—Host Block Data
Byte Register
T abl e 44 6. O ffs e t 07h : Hos t_B L O CK _ D B— H os t Blo ck Dat a Byt e Reg is te r
Bits Name Description Access
7:0 Block Data (BDTA)
This is e ith e r a re g iste r or a pointer into a 32 -byt e b lock
array, depending upon whether the E32B bit is set in the
Auxiliary Control register. Whe n the E32B bit is cleared, this is
a register containing a byte of data to be sent on a block
write or read from on a block read.
When the E32B bit is set, reads and writes to this register are
used to acc es s the 32-b y te bloc k data sto rage array. An
internal index pointer is us ed to a d dr e ss th e array, whic h is
reset to ’0’ by reading the HCTL register (offset 02h). The
index pointer then increments automatically upon each
acce ss to this re gi ste r. The transfer of block data into (re a d )
or ou t of (wr ite) this storage a rray during an SMBus
transaction always starts at index address 0.
When the E2B bit is se t, for write s, sof twa re will write up to
32 byte s to this reg ister as part of the setup fo r the
co mmand. Af te r th e Ho st Con troller has sent th e Address,
Command, and Byte Count fields, it will send the bytes in the
SRAM po inted to by this reg iste r. After the byte count has
been exhausted, the controller will set the BY TE_DONE_STS
bit . See Section 12.2.1,HST_ ST S- Ho s t Statu s Regi s t er, bit 7.
When the E2B bit is cleared for writes, software will plac e a
si ngle byte in this re gister. Aft e r th e ho st controller has se nt
the address, command, and byte count fields, it will send the
byte in this re gi ster. Wh en the re is more data to send,
softwar e wi ll write the next serie s of byte s to the SRAM
poin ted to by this re gister an d cl ear the BYTE_ DONE_STS bit .
The controller will then se nd th e next b yte. During the time
betwe e n the last byte b ei ng transm itte d to the next b yte
being tr ansmitted, the controller will insert wait states on the
interface.
When the E2B bit is set for reads, after re ceiving the byte
count into the Data0 register, the first series of data bytes go
into th e SRAM po inte d to by this reg ister. Wh en the by te
count has been exhausted or the 32-byte SRAM has been
filled , th e controller will ge ne rate an S M I# or inte rrupt
(depending on configuration ) and set the BYTE_DONE_STS
bit. Sof twa re will the n rea d th e data. During the time
between when the last byte is read fr om the SRAM to when
the BYT E _D ON E _S TS bi t is clea re d , th e controller will ins e rt
wait stat es on the inte rf a ce.
R/W
Device: 31 Function: 3
Offset: 07h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
542 Order Number: 300641-004US
12.2.8 Offset 08h: PEC—Packet Error Check Register
12.2.9 Offset 09h: RCV_SLVA—R eceive Slave Address
Register
Table 447. Offset 08h: PEC—Packet Error Check Register
Bits Name Description Access
7:0 PEC_DATA
This 8-bit re gi ste r is wr itte n with the 8-b it CRC value that is
used as the SMBus PEC data prior to a write tr ansac ti on. Fo r
read transactions, the PEC data is loaded from the SMBus into
this register and is then read by software. Software must
ensure that the IN US E_S TS bit is properly mainta ine d to
avoid having this field overwritten by a write transaction
following a read transaction.
R/W
Table 448. Offset 09h: RCV_SLVA—Receive S lave Address Register
Bits Name Description Access
7 Reserved Reserved.
6:0 SLAVE_ADDR
This field is the slave add ress that the Intel® 6300ES B ICH
decodes for read and write cycles. The default is not 0, so the
SMBus Slave Interface may respond even before the
proce ssor comes up or if th e pr ocessor is dea d. Thi s re g ist e r
is cleared by RSMRST#, but not by PXPCIRST#.
R/W
Device: 31 Function: 3
Offset: 08h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 09h Attribute: Read/Write
Defau lt Value: 44h Size: 8-bit
Lockable: No Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 543
12—Intel® 6300ESB ICH
12.2.10 Offset 0Ah: SLV_DATA—Receive Slave Data
Register
Note: This register contains the 16-bit data value written by the external SMBus master. The
processor may then read the value from this register. This register is reset by
RSMRST# but not PXPCIRST#.
12.2.11 Offset 0Ch: AUX_STS—Auxiliary Status Register
T abl e 44 9. O ffs e t 0Ah: SLV _ DA TA— R ec eive Sl av e D at a Reg is te r
Bits Name Description Access
15:8 DATA_MS G 1: D a ta
Messa ge Byte 1 See Sect ion 5.19 .8, “SMBus Slave Inte rface” for a discussion
of this field. RO
7:0 DATA_M S G 0: D ata
Messa ge Byte 0 See Sect ion 5.19 .8, “SMBus Slave Inte rface” for a discussion
of this field. RO
Table 450. Offset 0Ch: AUX_STS—Auxiliary Status Register
Bits Name Description Access
7:2 Reserved Reserved.
1SMBus TCO mode
(STCO)
This is the status bit that reflec ts the strap se tting of lega cy
TCO mode vs. Advanced TCO mode. When set, it indicates
that the Intel® 6300ESB ICH is in the advanced TCO mode.
When cleared, the Intel® 6300ESB ICH is in the legacy/
co mp at ib le TCO mod e .
NOTE: For the Intel® 6300ESB ICH this bit is always 0, since
Advanced TCO mode i s not supported
RO
0 CRC Error (CRCE)
This bit is set when a received message contained a CRC
erro r. Wh en this bit is set, the D ERR bit of the hos t status
registe r will also be se t. This bit will be set by the controller
when a sof tware a b ort occurs in the m iddle of the CRC
portio n of the cycle or a n ab ort ha p p en s after the Intel ®
6300ES B IC H has received the final data bit tran smit te d by
an external slave.
R/WC
Device: 31 Function: 3
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Device: 31 Function: 3
Offset: 0Ch Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
544 Order Number: 300641-004US
12.2.12 Offset 0Dh: AU X_ CTL—Auxiliary Control Register
12.2.13 Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control
Register
Note: This register is in the resume well and is reset by RSMRST#.
Table 451. Offset 0Dh: AUX_CTL—Auxiliary Control Register
Bits Name Description Access
7:2 Reserved Reserved.
1Enable 32-byte Buffer
(E32B)
When se t, the Host B lock Data register is a po inte r into a
32-byte buffer, as opposed to a single r egister. This enables
the block comm a nd s to tran sfe r or re ceive up to 32 bytes
before the Inte l® 6300ESB ICH generate s an interrupt.
R/W
0Automatically Append
CRC (AAC)
When set, t he Intel ® 6300ESB ICH will automatically append
the CRC. This bit must not be changed during SMBus
transactions, or unde te rmined beha vi or will re sult R/W
Table 452. Offset 0Eh: SMLINK_PIN_C TL—SMLink Pin Control Register
Bits Name Description Access
7:3 Reserved Reserved.
2 SMLINK_CLK_CTL
This Read/Write bit ha s a def ault of 1.
0 = The Intel® 6300ES B ICH will drive the SMLIN K[0] p in
low, independen t of wha t the othe r S M LINK log ic w ould
otherwise indicate f or the SMLINK[0] pin.
1 = The SMLINK[0] pin is not overdriven low. The other
SMLINK logic controls the state of the pin.
R/W
1 SMLINK1_CUR_STS
This read-only bit has a default value that is dependent on an
external signal level. Th is p in re turn s the value on th e
SMLINK[1] pin. It will be ’1’ to indicate high, ’0’ to indicate
low. This allows software to read the current state of the pin.
RO
0 SMLINK0_CUR_STS
This read-only bit has a default value that is dependent on an
external signal level. Th is p in re turn s the value on th e
SMLINK[0] pin. It will be ’1’ to indicate high, ’0’ to indicate
low. This allows software to read the current state of the pin.
RO
Device: 31 Function: 3
Offset: 0Dh Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Resume
Device: 31 Function: 3
Offset: 0Eh Attribute: Read/Write
Defau lt Value: See Note Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 545
12—Intel® 6300ESB ICH
12.2.14 Offse t 0Fh: SMBUS_PIN_CTL—SM BUS Pin Control
Register
Note: This register is in the resume well and is reset by RSMRST#.
12.2.15 Offset 10h: SLV_STS—Sla ve Status Registe r
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 KHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
Table 453. Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register
Bits Name Description Access
7:3 Reserved Reserved.
2 SMBCLK_CTL
This Read/Write bit has a defa ult of 1.
1 = The SMBCLK pin is not overdriven low. The other SMBus
logic controls the state of the pin.
0 = The Intel® 6300ESB ICH will drive the SMB CL K pin lo w,
independent of what the other SMB logic would otherwise
indicate for the S MB CLK p in.
R/W
1 SMBDATA_CUR_STS
This read-only bit has a default v alue that is dep endent on an
exte rn al signal level. This p in re tu rns the value on the
SMBDA TA p in. It will be ’1’ to indicate high, ’0’ to indi cate low .
This allows software to read the current state of the pin.
RO
0SMBCLK_CUR_STS
This read-only bit has a default v alue that is dep endent on an
exte rn al signal level. This p in re tu rns the value on the
SMBCLK pin. It will be ’1’ to indicate high, ’0’ to indicate low.
This allows software to read the current state of the pin.
RO
Device: 31 Function: 3
Offset: 0Fh Attribute: Read/Write
Defau lt Value: See Note Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
546 Order Number: 300641-004US
12.2.16 Offset 11H: SLV_CMD—Slave Command Register
Note: This register is in the resume well and is reset by RSMRST#.
Table 454. Offset 10h: SLV_STS—Slave Status Register
Bits Name Description Access
7:1 Reserved Reserved.
0 HOST_NOTIFY_STS
The I n t el® 6 300ES B ICH sets this bit to a ’1’ when it has
completely rece ived a suc ce ssful Host N otify Comm a n d on
the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host
Notify Co mma nd. Software clea rs th is b it after reading any
information needed fr om the Notify address and data
registers by writing a ’1’ to this bit. N ote that the Intel®
6300ES B ICH will allow the Notify Address and Data registers
to be overwritten once this bit has been cl ear e d. Whe n this
bit is 1, the Intel® 6300ESB ICH will NACK the first byte (host
address) of any new “Host Notify ” commands on the SMLink .
Writing a ’0’ t o this bit has no ef fect.
R/WC
Table 455. Offset 11H: SLV_CMD —Slave Command Register
Bits Name Description Access
7:3 Reserved Reserved.
2SMBALERT_DIS
0 = Allows the g e ne ration of the interrupt or SMI#.
1 = Softwar e s ets this b it to b lock the genera tion of the
interrupt or SMI# due to the SMBALER T# source. This bit
is logically inverted and ANDed with th e SMBA LERT_ST S
bi t. The r es u l ting sign al i s di s tr ib ute d t o th e SMI # a nd/ o r
interrupt generation logic. This b it does not affect the
wake logic.
R/W
1 HOST_NOTIFY_WKEN
Software se ts this bit to ’1’ to en ab le the reception of a Host
Notify command as a wake event. When enabled, this event
is ‘OR’ed in with the other SMBus wake events and is
reflecte d in the SMB _WAK_STS b it of the Gene ral Purpo se
Event 0 Status register.
R/W
0 HOST_NOTIFY_INTREN
Software sets this bit to ’1’ to e na b le the gene ration of
interrup t or SMI# whe n H OS T_NOTIFY_STS is 1 . This enab le
does not affect th e sett ing of the HOST_NOTIFY_STS b it.
When the int errup t is g enerated , ei ther PIRQ[B ]# or SMI# is
generated, depending on the value of the SMB_SMI_EN bit
(D31, F3, Off 40h, B 1). If the HOST _NOTIFY _S TS bit is set
when this bit is wr itte n to a 1, the n th e inter rup t (or S MI#)
will be gene ra te d. Th e inte rru p t (or S M I#) is logically
generated by ‘AND’ing the STS and INTREN bits.
R/W
Device: 31 Function: 3
Offset: 10h Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 11h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 547
12—Intel® 6300ESB ICH
12.2.17 Offset 14h: NOTIFY _DADD R—Not ify Device
Address
Note: This register is in the resume well and is reset by RSMRST#.
T abl e 45 6. O f fse t 14h : NOT IFY_ DA DD R—No t ify Device Add re ss
Bits Name Description Access
7:1 DEVICE_ADDRESS
This field c ontains the 7-bit device address received during
the Host Notify protocol of th e SMB u s 2.0 specifica tion.
Software should only consider this field valid when the
HOST _N OTIFY_ STS bit is set to ‘1’.
RO
0 Reserved Reserved.
Device: 31 Function: 3
Offset: 14h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—12
Intel® 6300ESB I/O Controller Hub
DS November 2007
548 Order Number: 300641-004US
12.2.18 Offset 16h: NOTIFY_DLOW—Notify Data Low Byte
Register
Note: This register is in the resume well and is reset by RSMRST#.
12.2.19 Offset 17h: NOTIFY_ DH IGH—Notify Data High
Byt e Regis ter
Note: This register is in the resume well and is reset by RSMRST#.
Table 457. Offset 16h: NOTIFY_DLOW—Notify Data Low Byte Regist er
Bits Name Description Access
7:0 DATA_LOW_BYTE
Thi s fiel d c onta in s the fir s t (lo w) by te of data receiv ed dur i ng
the Host Notify protocol of the SMBus 2.0 specification.
Softwa re shou ld only consider th is fi el d valid whe n the
HOST_NOTIFY_STS bit is set to ‘1.
RO
Table 458. Offset 17h: NOTIFY_DHIGH—Notify Data High Byte Register
Bits Name Description Access
7:0 DATA_HIGH_BYTE
This field cont a in s the seco n d (hig h ) byte of d a ta re ce ived
during th e Host N otif y protocol of the SMBus 2.0
specif ica tion. Sof twa re shou ld only consid er th is f ie ld vali d
when the HOST_NOTIFY_STS bit is set to ‘1’.
RO
Device: 31 Function: 3
Offset: 16h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 3
Offset: 17h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 549
13—Intel® 6300ESB ICH
AC’ 97 Aud io Cont ro l le r Reg ist er s
(D31:F5) 13
13 .1 AC’97 Audi o PCI Co nfi guration Space
(D31:F5)
Note: Registers that are not shown should be treated as Reserved.
Table 459. PCI Configuration Map (Audio—D31:F5)
Offset Mnemonic Register Default Access
00-01h VID Ve ndor Identification 8086h RO
02-03h DID Dev ice Id en tifi cation 25A6h RO
04-05h PCIC MD PCI Command 000 0 R/W
06-07h PCISTS PCI Device Status 0 290h R/WC
08h RID Revision Identificati on See Note 1 RO
09h PI Programming Interface 00 RO
0Ah SCC Sub Class Code 01h RO
0Bh BCC Base Class Cod e 04h RO
0Eh HEDT Head e r Ty pe 00h RO
10-13h N A MB AR Native Audio Mix e r Bas e Add re ss 00000000h R/W
14-17h NAB MB A R N ative Audio Bus Maste ring Bas e Addre ss 000 00000h R/W
18-1B h MMB A R Mixer B ase Addre ss (M e m) 000 00000h R/W
1C-1 Fh M B BAR Bus Ma ster B ase Add ress (Mem) 00000000 h R/W
2C-2Dh SVID Subsystem Vendor ID 0000h Write-
Once
2E -2Fh S ID Sub sy stem ID 0 000h Write-
Once
34h CAP_PT R Capabil itie s Poin te r 50h RO
3Ch INTR_LN Inte rrup t Line 00h R/W
3Dh I NTR_PN Interrup t Pin 02h RO
40h PCID Programmable Cod e c ID 09h R/W
41h CFG Configuration 00h R/W
50-51h PID PCI Power Management ID 0001h RO
52-53h PC PC - Power Manageme nt Cap a b ilitie s C9C2h RO
54-55h PCS Power Ma nag eme nt Control and Status 0 000h R/W
NOTES:
1. Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value o f the Revision ID Register.
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
550 Order Number: 300641-004US
Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers
except the following B IOS programmed registers as BIOS may not be invoked following
the D3-to-D0 transition. Resume well registers will not be reset by th e D3HOT to D0
transition.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 551
13—Intel® 6300ESB ICH
Core Well registers not reset by the D3HOT to D0 transition:
Offset 2Ch-2Dh – Subsystem Vendor ID (SVID)
Offset 2Eh-2Fh – Subsystem ID (SID)
Offset 40h – Programmable Codec ID (PCID)
Offset 41h – Configuration (CFG)
Resume Well registers will not be reset by the D3HOT to D0 transition:
Offset 54h-55h – Power Management Control and Status (PCS)
Bus Mastering Register: Global Status Register, bit[17:16]
Bus Mastering Register: SDATA_IN MAP register, bit[7:3]
13.1.1 Offset 00 - 01h: VID—Vendor Identification
Register (Audio —D31:F5)
13.1.2 Offset 02 - 03h: DID—Device Identification
Register (Audio —D31:F5)
Table 460. Offset 00 - 01h: VID—Vendor Identification Register (Audio
D31:F5)
Bits Name Description Access
15:0 Vendor ID Value This is a 16-b it value assigned to Intel. RO
Table 461. Offset 02 - 03h: DID—Device Identification Register (Audio—
D31:F5)
Bits Name Description Access
15:0 Device ID Value RO
Device: 31 Function: 5
Offset: 00-01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 02-03h Attribute: Read-Only
Defau lt Value: 25A6h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
552 Order Number: 300641-004US
13.1.3 Offset 04 - 05h: PC ICMD—PCI C o mm and Register
(Audio—D31:F5)
Note: PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete
details on each bit.
13.1.4 Offset 06 - 07h: PCISTS—PCI Device Status
Register (Aud io—D3 1: F 5)
Note: PCISTS is a 16-bit status register. Refer to the PCI 2.2 specification for complete details
on each bit.
Note: When a master abort occurs on a memory read request performed by a particular
channel, the run bit for that channel gets cleared immediately, and the corresponding
DMA engine halts. Write requests are posted and hence aborts cannot be seen by the
Intel® 6300ESB ICH AC’97 controller for write requests.
Table 462. Offset 04 - 05h: PCICMD—PCI Command Register (Audio—D31:F5)
Bits Name Description Access
15:1
0Reserved Reserved. Re ad ‘0 .
9Fast Back-to-B a ck
Enable (FBE) Not implemented. Hardwired to ‘0’.
8 SERR# Enable (SEN) Not implemented. Hardwired to ‘0’.
7Wait Cycle Control
(WCC) Not implemented. Hardwired to ‘0’.
6Parity Error R esponse
(PER) Not implemented. Hardwired to ‘0.
5VGA Palette Snoop
(VPS) Not implemented. Hardwired to ‘0’.
4Memory Wri te and
Invalidate Enable (MWI) Not implemented. Hardwired to ‘0.
3Spe cia l Cy cle E na b le
(SCE) Not implemented. Hardwired to ‘0’.
2Bu s M a st e r En a b l e
(BME)
Contr ols standard PCI bus m a ste ring capab ilitie s.
0 = Disabl e.
1 = Enable R/W
1Memory Space Enable
(MSE) Enables memory space addresses to the AC’97 Audio
Controller. R/W
Device: 31 Function: 5
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 553
13—Intel® 6300ESB ICH
T abl e 46 3. O ffs e t 06 - 07h: PCI ST S— PCI De vic e St at u s Re gis t er (Au d io
D31:F5)
Bits Name Description Access
15 Dete cte d Parity Error
(DPE) Not implemented. Hardwired to ‘0’.
14 SERR# Status (SERRS) Not implemented. Hardwired to ‘0’.
13 Master- A bort Status
(MAS)
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Bus Maste r AC '97 2.2 inte rf a ce function, a s a maste r,
generates a master abo rt. R/WC
12 Reserved Res er ved . W ill a lways read as ‘0’.
11 Signal ed Target - A bo rt
Sta tu s (STA ) Not implemented. Hardwired to ‘0’.
10:9 DEVSEL# Timing Status
(DEVT)
This 2-bit field reflects the Intel® 630 0ES B ICH ' s DEVSEL#
timin g when perfo r ming a positi v e decode.
01b = Med ium timing.
Hardwired to ‘01’.
RO
8Data Parity Detected
(DPD) Not implemented. Hardwired to ‘0’.
7Fast Back t o back
Capabl e ( FBC) Ha rd wired to ‘1’. This bit indicates that the Intel® 6300ESB
ICH as a target is cap a b le of fast back-to-b a ck transacti o ns.
6 Reserved Reserved. Hardwired to ‘0’.
5 66 MHz Capable Hardwired to ‘0’.
4Capabilities List Exists
(CLIST)
Indicates that the cont roller contains a cap abilities pointe r
list. The first item is pointed to by looking at configuration
offset 34h.
3:0 Reserved Reserved.
Device: 31 Function: 5
Offset: 06-07h Attribute: Read/Write Clear
Defau lt Value: 0290h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
554 Order Number: 300641-004US
13.1.5 Offset 08h: RID—Revision Identification Register
(Audio—D31:F5)
13.1.6 Offset 09h: PI—Programming Interface Register
(Audio—D31:F5)
13.1.7 Offset 0Ah: SCC —Sub Class Code R egister
(Audio—D31:F5)
Table 464. Offset 08h: RIDRevision Identification Register (Audio—D31:F5)
Bits Name Description Access
7:0 Revis ion ID Value Refer to the Intel® 6300ESB I/O Controller Hub Spec if icat ion
Update for the mo st up -to-d ate value of the Revision ID
Register. RO
Table 465. Offset 09h: PI—Programming Interface Register (Audio—D31:F5)
Bits Name Description Access
7:0 Pro gramming Interface RO
Table 466. Offset 0Ah: SCC—Sub Class Code Register (Audio—D31:F5)
Bits Name Description Access
7:0 Sub Class Code 01h = Audio Device
This indicate s the device is an audio de vi ce, in the contex t of
a multimedia devic e (Base Cl ass Code = 04h). RO
Device: 31 Function: 5
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descripti on Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 555
13—Intel® 6300ESB ICH
13.1 .8 Off set 0Bh: BCC—Base Class Code R egister
(Audio—D31:F5)
13.1.9 Offset 0Eh: HEDT—Header Type Register (Audio—
D31:F5)
13.1 .10 Offset 10 - 13h : NAMBAR—Native Au dio
Mixer Base Address Register (Audio—D31:F5)
The Native PCI Mode Audio function uses PCI Base Address register 1 to request a
contiguous block of I/O space that is to be used for the Native Audio Mixer software
interface. The mixer requires 256 bytes of I/O space. This 256 bytes space is divided
into 128 bytes for the primary codec (offsets 00-7Fh) and 128 bytes for the secondary
codec (offsets 80-FFh). Access to these registers will be decoded by the AC’97
controller and forwarded over the AC-link to the codec. The codec will then respond
with the register value.
In the case of split codec implementation, accesses to the different codecs are
differentiated by the controller by using address offsets 00h - 7Fh for the primary codec
and ad dres s offset s 80h - F E h for the seco ndar y codec .
Note: The tertiary codec cannot be addressed through this address space. The tertiary space
is only available from the new MMBAR register. This register powers up as read only
and only becomes writeable when the IOSE bit in offset 41h is set.
For descriptions of these I/O registers, refer to the AC’97 specification.
Table 467. Offset 0Bh: BCC—Base Class Code Register (Audio—D31:F5)
Bits Name Description Access
7:0 B ase Class Code 04h = Multimedia device RO
Table 468. Offset 0Eh: HEDT—Header Type Register (Audio—D31:F5)
Bits Name Description Access
7:0 Header Type Value Hardwired to 00h.
Device: 31 Function: 5
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 04H Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 0Eh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
556 Order Number: 300641-004US
13.1.11 Offset 14 - 17h: NABMBAR—Native Audio Bus
Mastering
Base Address Register (Audio—D31:F5)
The Native PCI Mode Audio function uses PCI Base Address register 1 to request a
contiguous block of I/O space that is to be used for the Native Mode Audio software
interface. This BAR creates 64 bytes of I/O space to signify the base address of the bus
master I/O space.
Note: The DMA registers for S/PDIF and Microphone In 2 cannot be addressed through this
address space. These DMA functions are only available from the new MBBAR register.
This register powers up as read only and only becomes writeable when the IOSE bit in
offset 41h is set.
Table 469. Offset 10 - 13h: NAMBAR—Native Audio Mixer Base Address
Register (Audio—D31:F5)
Bits Name Description Access
31:1
6Reserved Reserved. All bits are hardwired to ‘0’.
15:8 Base Address
These bits are used in the I/O space dec ode of the Native
Au dio Mix er int erface re gister s. The nu mber of u pper b its that
a device actually implements depends on how much of the
address space the device will respond to. For the AC‘97 mixer,
the upper 16 bits are hard wired to ‘0’, while b its 15:8 are
program mab le . This configura tion yields a max imu m I/O
block size of 256 b ytes for th is ba se a ddress.
R/W
7:1 Reserved Reserved. Read as ‘0’s.
0Re so ur ce Typ e In di cat or
(RTE)
This read-only bit defaults to ’0’ and flips to ’1’ if bit ’0’ of
offset 41h is set. W he n this bit is s et to ‘1’, it ind icate s a
requ est for I/O space. RO
Device: 31 Function: 5
Offset: 10-13h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 557
13—Intel® 6300ESB ICH
13.1 .12 Offset 18 - 1Bh: MMBAR—Mixe r Base Address
Register (Audio —D31:F5)
This BAR creates 512 bytes of memory space to signify the base address of the register
space. The lower 256 bytes of this space map to the same registers as the 256-byte I/
O space pointed to by NAMBAR. The lower 384 bytes are divided as follows:
128 bytes for the primary codec (offsets 00 – 7Fh)
128 bytes for the secondary codec (offsets 80h – FFh)
128 bytes for the tertiary codec (offsets 100h – 17Fh).
128 bytes of reserved space (offsets 180h – 1FFh), returning all ‘0’.
Table 470. Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering Base
Address Register (Audio—D31:F5)
Bits Name Description Access
31:1
6Reserved Reserved . H ard wired to ‘0’.
15:6 Base Address
These bits are used in the I/O space decode of th e Native
Audio Bus Mast ering i nt erfac e reg i sters . T he n um ber o f upper
bits that a devi ce actually imple ments depends on how much
of the address space the device will respond to. For AC’97 bus
maste ring , the up per 16 b its ar e hardwired to ‘0’, while b its
15:6 are programmable. This configuration y ields a maximum
I/O b lock size o f 64 b ytes fo r th is b a se a ddress.
R/W
5:1 R eser ved Rese rv ed. R ead as ‘0’s.
0Resource Type Indicator
(RTE)
This read-only bit defaults to ’0’ and f lip s to ’1’ if bit ’0’ of
offset 41h is set. When this bit is set to ‘1, it indicates a
requ e st f or I/O space. RO
Device: 31 Function: 5
Offset: 14-17h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Table 471. Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio
D31:F5) (Sheet 1 of 2)
Bits Name Description Access
31:9 Base Address Lower 32 bits of the 512-b yte memor y off set to use f or
decoding the primary, secondar y, and tertiary codec’s mixer
spaces. R/W
Device: 31 Function: 5
Offset: 18-1Bh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
558 Order Number: 300641-004US
13.1.13 Offset 1C - 1Fh: MBBAR—Bus Mast er Base Address
Register (Aud io—D3 1: F 5)
Note: This BAR creates 256 byte s of memory space to signify the base address of the bus
master memory space. The lower 64 bytes of the space pointed to by this register po int
to the same regi sters as the NABMBAR.
8:3 Reserved Reserved. Read as ‘0’s. RO
2:1 Type Indicates the base address exists in 32-bit address space RO
0Re so ur ce Typ e In di cat or
(RTE) This bit is set to ’0’, ind icating a request for memory sp ace . RO
Table 472. Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register
(Audio—D31:F5)
Bits Name Description Access
31:8 Base Address I/O of fse t to use fo r dec od ing the PCM In, PCM Out, and
Microphone 1 DMA engines. R/W
7:3 Reserved Reserved. Read as ‘0’s. RO
2:1 Type Indicates the base address exists in 32-bit address space. RO
0Re so ur ce Typ e In di cat or
(RTE) This bit is set to ’0’, ind icating a request for memory sp ace . RO
Table 471. Offset 18 - 1Bh: MMBAR—Mixer Base Ad dress Register (Audio—
D31:F5) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 5
Offset: 18-1Bh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 1C-1Fh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 559
13—Intel® 6300ESB ICH
13.1.14 Offset 2D - 2Ch: SVID—Subsystem Vendor ID
Register (Audio —D31:F5)
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value may be read back. Any subsequent writes will have no effect.
This regi st er is not affect ed by the D3HOT to D0 transition.
13.1.15 Offset 2E - 2Fh: SID—Subsys tem ID Register
(Audio—D31:F5)
The SID register, in combination with the Subsystem Vendor ID register make it
possible for the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value may be read back. Any subsequent writes will have no effect.
This regi st er is not affect ed by the D3HOT to D0 transition.
Ta ble 473. Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio—
D31:F5)
Bits Name Description Access
15:0 Subsystem Vendor ID
Value R/WO
Device: 31 Function: 5
Offset: 2D-2Ch Attribute: Read/Write Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Table 474. Offset 2E - 2Fh: SID—Subsystem ID Register (Audio—D31:F5)
Bits Name Description Access
15:0 S u b system ID Value R/WO
Device: 31 Function: 5
Offset: 2E-2Fh Attribute: Read/W rite Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
560 Order Number: 300641-004US
13.1.16 Offset 34h: CAP_PTR—Capabilities Pointer
(Audio—D31:F5)
Note: This register indicates the offset for the capability pointer.
13.1.17 Offse t 3 Ch: INTR_LN—Interrupt Line Register
(Audio—D31:F5)
Note: This register indicates which PCI interrupt line is used for the AC’97 module interrupt.
The AC’9 7 inte rrup t is inte r nally ORed to the inte rr up t con troll er wit h the PIR Q[B ]#
signal.
Table 475. Offset 34h: CAP_PTR—Capabilities Pointer (Audio—D31:F5)
Bits Name Description Access
7:0 Capabi lity Pointer (CP) Indicates that the first capability pointer offset is offset 50h. RO
Table 476. Offset 3Ch: INTR_LN—Interrupt Line Register (Audio—D31:F5)
Bits Name Description Access
7:0 Interrupt Line This data is not used by the Intel® 6300ESB ICH. It is used to
commu nicate to sof t wa re the inte rrup t line that the inte rrup t
pin is c o nne ct ed to. R/W
Device: 31 Function: 5
Offset: 34h Attribute: Read-Only
Defau lt Value: 50h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 561
13—Intel® 6300ESB ICH
13.1.18 Off set 3Dh: INTR_PN— Interrupt Pin R egister
(Audio—D31:F5)
Note: This register indicates which PCI interrupt pin is used for the AC’97 module interrupt.
The AC’97 interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
13.1.19 Offse t 40h: PCID—Programmable Codec ID
Register
(Audio—D31:F5)
Note: This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3HOT to D0 transition.
Note: The value in this register must only be modified prior to any AC’97 codec accesses.
T abl e 47 7. O f fse t 3Dh : IN TR _P N In te rr up t P in Re gis t e r (A udi o—D3 1 :F5 )
Bits Name Description Access
7:3 Reserved Reserved.
2:0 AC'97 Interrupt Routing Ha rdwired to 010b to sel ect PIRQB #. RO
Table 478. Offset 40h : PCID —Program mable Codec ID Register (Audio—
D31:F5)
Bits Name Description Access
7:4 Reserved Reserved.
3:2 Ter tiar y Code c ID ( TID) These bits define the encoded ID that is used to address the
terti ary co dec I/O spac e. Bit ’1’ is the first bit sent a nd Bit ’0’
is the second bit sent on AC_SDATA_OUT during slot 0. R/W
1:0 Seconda ry Codec ID
(SCID)
These two bits define the encoded ID that is used to address
the secondary cod ec I/O space . The two bits are the ID that
will be placed on slot 0, bits ’0’ and ‘1, upon an I/O access to
the seco nda ry cod ec. Bi t ’1’ is the first bit sent and bit ’0’ is
the se cond bit se n t on A C_ S DATA_OUT during slot 0.
R/W
Device: 31 Function: 5
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 3Dh Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 40h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
562 Order Number: 300641-004US
13 .1.20 Offset 41h: CFG—Configuration Register ( Audio
D31:F5)
Note: This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3HOT to D0 transition.
13.1.21 Offset 50h: PID—PCI Power Management
Capability ID Register (Audio—D31:F5)
Table 479. Offset 41h: CFG—Configuration Register (Audio—D31:F5)
Bits Name Description Access
7:1 Reserved Reserved. RO
0 I/O Space Enable (IOSE)
When cleared, t he IOSE bit at offset 04h and the I/O space
BARs at offset 10h and 14h bec ome read-only registers. This
is the default state for the I/O BARs. BIOS must explicitly set
this bit to allow a lega cy d river to work.
R/W
Table 480. Offset 50h: PID—PCI Power Management Capability ID Register
(Audio—D31:F5)
Bits Name Description Access
15:8 Ne x t Cap a bi lity (NEXT ) Ind icates that the next item in the list is at offset 00h. RO
7:0 Cap ID (CA P) Indicates that this pointe r is a me ssage signaled inte rrupt
capability. RO
Device: 31 Function: 5
Offset: 41h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 50h Attribute: Read-Only
Defau lt Value: 0001h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 563
13—Intel® 6300ESB ICH
13.1.22 Off set 52h: PC— Power Mana gement Capabilities
Register (Audio —D31:F5)
Note: This regi ster is not affe cted by the D3HOT to D0 transition.
13.1 .23 Offset 54h: PCS—P o wer Management Control and
Sta t us Register (Aud io —D31 : F 5)
T abl e 481. Of fs e t 52h : PC— P ow e r M ana g em e nt C ap ab iliti es Reg iste r (Au dio
D31:F5)
Bits Name Description Access
15:1
1PME_Support Indicates PME# may be generated from all D states. RO
10:9 Reserved Reserved. RO
8:6 Aux_Current Reports 375mA m axim u m S u spe n d we ll current required
when in the D3 cold state. RO
5Device Speci fic Initia l-
ization (D S I ) Indicates tha t no device-specific initializatio n is required . RO
4 Reserved Reserved. RO
3 PME Clock (PMEC) Indicates that PCI clock is not required to generate PME#. RO
2:0 Version (VS) Indicates support for Revision 1. 1 of the PCI Power
Management S pecification. RO
Table 4 82. Offset 54h: PCS—Power Management Control and Status Register
(Audio—D31:F5) (Sheet 1 of 2)
Bits Name Description Access
15 PME Status (PMES) This b it is se t wh e n the AC’97 cont rolle r would norma lly
assert the PME# signal independent of the state of the
PME_E n bit. T his bit re sid es in the re sume well. R/WC
14:9 Reserved Reserved. RO
Device: 31 Function: 5
Offset: 52h Attribute: Read-Only
Defau lt Value: C9C2h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: 54h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
564 Order Number: 300641-004US
13.2 AC ’97 Audio I/ O Spac e (D31:F5)
The AC’97 I/O space includes Native Audio Bus Master Registers and Native Mixer
Registers. F or the Intel® 6300ESB ICH, the offsets are important as they will determine
bits[1:0] of the TAG field (codec ID).
Audio Mixer I/O space may be accessed as a 16-bit field only since the data packet
length on
AC-link is a word. Any S/W access to the codec will be done as a 16-bit access starting
from th e firs t ac tiv e b yte. In case no b yte ena ble s are acti ve, the a cc ess wi ll b e do ne at
the first word of the qWord that contains the address of this request.
8Power Management
Event Enable (PMEE) W he n set, a nd if cor resp ond ing PMES is also set, the A C'97
controller se ts the AC97 _S TS bit in the GPE0_S TS register. R/W
7:2 Reserved Reserved. RO
1:0 P o we r Stat e (PS)
This field is used both to determine the current power state of
the AC’ 97 cont rolle r and to set a new power state. The v alues
are:
00 – D0 state
01 – not supporte d
10 – not supporte d
11 – D3HOT st a te
When in the D3HOT sta t e , the AC’ 97 con troller’s configura tion
space is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked.
When s oftware attempts to write a value of 10b or 01b in to
this field, the write op e ration must complete no rmally.
However, the data is discarded and no state change occurs.
R/W
Table 482. Offset 54h: PCS—Power Management Control and Status Register
(Audio —D31:F5) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 5
Offset: 54h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 565
13—Intel® 6300ESB ICH
Tab l e 48 3. Int el® 6300ESB I/O Controller Hub Audio Mixer Register
Configuration (Sheet 1 of 2)
Pri mary Offset
(Cod ec ID =00) Sec on dary Offset
(Code c ID = 01) Tertiary Offset
(Codec ID =10) NAMBA R Exposed Registers
(D31:F5)
00h 80h 100h Reset
02h 82h 102h Mas te r Volume
04h 84h 104h Aux Out Volume
06h 86h 106h Mo no Volume
08h 88h 108h Mas ter Tone (R and L)
0Ah 8 Ah 10Ah PC_BEEP Volume
0Ch 8Ch 10Ch Phone Volume
0Eh 8Eh 10Eh M ic Volum e
10h 90h 110h Line In Volume
12h 92h 112h C D Volume
14h 94h 114h Vid eo Volume
16h 96h 116h Aux In Volume
18h 98h 118h PCM Out Volume
1Ah 9 Ah 11Ah Record S el ec t
1Ch 9C h 11Ch Record G a in
1Eh 9Eh 11Eh Record Gain M ic
20h A0h 120h General Purpose
22h A 2h 122h 3 D Cont rol
24h A4h 124h AC’97 RES ERVED
26h A 6h 126h Powerdown Ctrl/Stat
28h A8h 128h Extended Audio
2Ah A Ah 12Ah Extended Audio Ctr l/S tat
2Ch ACh 12Ch PCM Front DAC Rate
2Eh AEh 12Eh PC M Sur round DAC Rate
30h B0h 130h PCM LFE DAC Rate
32h B2h 132h PCM LR ADC Rate
34h B4h 134h MIC ADC Rate
36h B 6h 136h 6Ch Vol: C, LFE
38h B 8h 138h 6Ch Vol: L, R Surround
3Ah BAh 13Ah S/PD IF Control
3C -56h BC-D6h 13C-156h Inte l RESERVED
58h D8h 158h AC’97 Reserved
NOTES:
1. Softwa re should n ot t ry t o a cce ss reserv ed registers.
2. Primary Codec ID cannot be changed. Secondary codec ID may be change d through bits 1:0
of config u ratio n re gi ste r 40h. Tertiary codec ID may be cha nged throug h b its 3:2 of
configuration register 40h.
3. The tertiary offset is only available through the memory space defined by the MMBAR
register.
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
566 Order Number: 300641-004US
Th e Bus Ma ster r egis ter s are l ocate d from offse t + 00h t o offse t + 51h a nd res ide in t he
AC’97 controller. Accesses to these registers do NOT cause the cycle to be forwarded
over the AC-link to the codec. S/W could access these registers as bytes, word, or
dWord quantities, but reads must not cross dWord boundaries.
In the case of split codec implementation, accesses to the different codecs are
differentiated by the controller by using address offsets 00h - 7Fh for the primary
cod ec , addr es s offset s 80 h - FFh for the sec o nd ar y co dec a nd addr es s offset s 10 0h -
17Fh for the tertiary codec.
The Global Control (GLOB_CNT) a nd Global Status (GLOB_ ST A ) registers are aliased to
the same global registers in the audio and modem I/O space. Therefore a read/write to
these registers in either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC’97 controller. The six
channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their
own set of Bus Mastering registers. The following register descriptions apply to all six
cha nne ls. The re gis te r def in itio n se ct io n titl es use a ge ner ic “x_” i n front o f th e reg is ter
to indicate that the register applies to all six channels. The naming prefix convention
us ed i n Table 484 and in the register description I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel.
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
5Ah DAh 15A h Vendor Reserved
7Ch FCh 17Ch Vendor ID 1
7Eh FEh 17Eh Vendor ID2
Table 483. Intel® 6300ESB I/O Controller Hub Audio Mixer R egister
Configuration (Sheet 2 of 2)
Primary Offset
(Co dec ID =00) Seco ndary Offs et
(Cod ec ID =01) Tertiary Offset
(Cod ec ID =10) NAMBAR Ex posed Re gisters
(D31:F5)
NOTES:
1. Software should not try to access reserved reg isters.
2. Primary Codec ID cann o t be cha nged. Sec o nda ry co dec ID may be ch an ged t hrou gh bi t s 1:0
of configuration registe r 40h . Tertiary codec ID may be chan g e d through bit s 3: 2 of
config uration register 40h.
3. T he tertiary offset is only available through the memory space defined by the MMBAR
register.
Table 484. Native Audio Bus Master Control Registers (Sheet 1 of 3)
Offset Mnemonic Name Default Access
00h PI_BDBAR PCM in Buffer Descriptor list Base Address
Register 00000000h R/W
04h PI_CIV P CM in Curre nt Ind ex Value 00h RO
05h P I_LVI PCM in Last Valid Index 00h R/W
06h PI_SR P CM in Stat us Register 0003h R/W
08h P I_PICB P CM in Position in Current Buffer 0000h RO
0Ah PI_PIV PCM in Prefetched Index Value 00h RO
0Bh P I_CR PCM in Contro l Register 00h R/W
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 567
13—Intel® 6300ESB ICH
10h PO_BDBAR PCM out Buffer Descriptor list Base Address
Register 00000000h R/W
14h PO_CIV PCM out Current Ind ex Value 00h RO
15h PO_LVI PCM out L a st Valid Ind ex 00h R/W
16h PO_SR PCM out Status Register 0001h R/W
18h PO_PICB PCM out Positio n In Curre nt B uffer 0000h RO
1Ah PO_PIV PCM out Prefetched Index Value 00h RO
1Bh PO_CR PCM out Control Registe r 00h R/W
20h MC_BDBAR Mic. in Buf f er De scriptor L ist B a se A dd re ss
Register 00000000h R/W
24h MC_CIV Mic. in Current Ind ex Value 00h RO
25h MC_LVI Mic. in L ast Valid Index 00h R/W
26h MC _S R Mic. In Status Registe r 0001h R/W
28h MC_PICB Mic. In Position In Curre nt B uffe r 0000h RO
2Ah MC_PIV Mic. in Prefetched Index Value 00h RO
2Bh MC_CR Mic. in Control Regis te r 00h R/W
2Ch GLOB_CNT Global Control 00000 000h R/W
30h GLOB_STA Global Status 00700 000h RO
34h ACC_SEMA Codec Write Semaphore Register 00h R/W
40-43h MC2_BDBAR Mic. 2 Buffer Descriptor List Base Ad d ress
Register 00h RO
44h MC2_CIV Mic. 2 Cur re nt Ind ex Value 00h R/W
45h MC2_LVI Mic. 2 L a st Valid Index 0001h R/W
46-47h MC2_SR Mic. 2 Status Register 000 0h RO
48-49h MC2_PIC B Mic. 2 Position In Current Buf fer 00h RO
4Ah MC2_PIV Mic. 2 Prefe tched Ind ex Value 00h R/W
4Bh MC2_CR Mic. 2 Control Registe r 00h RO
50-53h PI2_BDBAR PCM in 2 B u ffe r Descriptor Lis t Base Add re ss
Register 00000000h R/W
54h PI2_CIV P CM in 2 Current Index Value 00 h RO
55h P I2_LVI PCM in 2 Last Valid In dex 00 h R/W
56-57h PI2_SR PCM in 2 Status Register 000 1h R/W
58-59h PI2_PICB PCM in 2 Position in Current Buffer 0000h RO
5Ah PI2_PIV PCM In 2 Pref etche d Index Value 00h RO
5Bh PI2_ CR P CM In 2 Control Register 00h R/W
60-63 SP_BAR S/PDIF Buffe r De scriptor List Base Add re ss
Register 00000000h R/W
64h S P_CIV S/PDIF Current Index Valu e 00h RO
65h SP _LVI S/PDIF Last Valid Index 00h R/W
66-67h SP_S R S/PDIF Status Register 0001h R/W
Table 4 84. Native Audio Bus Master Control Registers (Sheet 2 of 3)
Offset Mnemonic Name Default Access
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
568 Order Number: 300641-004US
Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers
except the registers shared with the AC’97 Modem (GCR, GSR, CASR). Resume well
registers will not be reset by the D3HOT to D0 transition.
Core Well registers and bits NOT reset by the D3HOT to D0 transition:
Offset 2Ch-2Fh – bits[15,6:0] Global Control (GLOB_CNT)
Offset 30h-33h – bits[29,15,11:10,0] Global Status (GLOB_STA)
Offset 34h – Codec Access Semaphore Register (CAS)
Resume Well registers and bits will NOT be reset by the D3HOT to D0 transition:
Offset 30h-33h – bits[17:16] Global Status (GLOB_STA)
13.2.1 x_BDBAR—Buffer Descriptor Base Address
Register
Note: Software may read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across dWord boundaries are not supported.
13.2.2 x_CIV—Current Index Value Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
boundaries are not supported.
68-69h SP_PICB S/PD IF Position In Curren t B uffer 0000h RO
6Ah SP_PIV S/PDIF Prefetched Index Value 00h RO
6Bh S P_CR S/PDIF Control Register 00h R/W
80h SDM SD ata_IN Map 00h R/W
Table 484. Native Audio Bus Master Control Registers (Sheet 3 of 3)
Offset Mnemonic Name Default Access
Table 485. x_BDBAR —Bu ffer Descriptor B as e Address Register
Bits Name Description Access
31:3 Buffer Descriptor Base
Address[31:3]
These bits represent address bits 31:3. The data should be
aligned on 8 byte boundaries. Each buffer descript or is 8
bytes long, and the list may contain a maximum of 32
entries.
R/W
2:0 H ard wire d to ‘0’.
Device: 31 Function: 5
I/O Address:
NABMBAR + 00h (PIBDBAR ), NABMBAR +
10h (POBDBAR ), NABMBAR + 20h
(MCBDBAR ) , MBBAR + 40h ( MC 2BDBAR ),
MBBAR + 50h (PI2BD BAR) , MBBA R + 60h
(SPBAR)
Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 569
13—Intel® 6300ESB ICH
13.2.3 x_LVI—Last Valid Index Register
13.2.4 x_SR—Status Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 05h. Reads across dWord
bou ndar i es are not supp orte d.
Table 486. x_CIV—Current Index Value Register
Bits Name Description Access
7:5 Hardwired to ‘0.
4:0 Current I ndex
Value[4:0]
These bits represent which buffer descriptor within the list of
32 descriptors is currently being processed. As each
descriptor is p rocessed , th is value is in cremente d . The value
rolls over a f te r it re a che s 31.
RO
Table 487. x_LVI—Last Valid Index Register
Bits Name Description Access
7:5 Hardwired to ‘0.
4:0 L ast Valid Index [4:0] This value repr e sen ts the la st valid descripto r in the list. This
va lu e is upda te d by the s oft w ar e each t i me it pr epar es a new
buff er and adds it to the list. R/W
Device: 31 Function: 5
I/O Address:
NABMBAR + 04h (PICIV), NABMBAR + 04h
(PICIV), NABMBAR + 04h (PICIV), MBBAR
+ 44h (M C2CIV ), MB B A R + 54h (PI2CIV ),
MBBAR + 64h (SPCIV)
Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
I/O Address:
NABMBAR + 05h (PI LVI), NABMBAR + 1 5h
(POLVI ), NA B MB AR + 15 h (POLVI ),
NABMBAR + 15h (POLVI), MBBAR + 55h
(PI2LVI), MBBAR + 65h (SPLVI)
Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
570 Order Number: 300641-004US
Table 488. x_SR—Status Register
Bits Name Description Access
15:5 Reserved Reserved. RO
4 FIFO Error (FIFOE)
0 = Clea red by writing a “1” to this bi t pos ition.
1 = FIFO error occurs.
PISR Register: FIFO error indicate s a FIFO overrun. T h e
FIFO pointers don't in cremen t; th e incoming data is not
written into the FIFO , thus is lost.
POSR R egis te r : FIFO er ror ind icates a FIFO under run. The
sam ple t ran smitted in thi s ca se should be th e la st valid
sample.
The Intel® 6300ESB ICH will set the FIFOE bit if the underrun
or overrun occurs when there are more valid buffers to
process.
R/WC
3Buffer Completion
Interrupt Status (BCIS)
0 = Clea red by writing a “1” to this bi t pos ition.
1 = Set by the hardwa re aft er th e last sam ple o f a buffer has
been processed, AND if the Interrupt on Completion
(IOC) bit is set in the com man d byte of the buff e r
d e scrip t or. It re m ains a ct ive un t i l clear e d by so f t ware .
R/WC
2Last Valid Buffe r
Compl et ion In te rrup t
(LVBCI)
0 = Clea red by writing a “1” to this bi t pos ition.
1 = Last valid buffer has been processed. It remains active
until cleared by softwa re. This bit indicates th e
occ urr enc e of the event signi fi ed by the last v alid buffer
being processed. Thus, this is an e vent status bi t that
may be cleared by software once this event has been
recogn ized . This event will c a use an inte rrupt when the
enable b it in th e Cont rol Registe r is se t. The inte rrup t is
clear ed when the softwar e clear s this bit.
In the case of Transmits (PCM out, Modem out) this bit is
set af ter the last valid buffer has been fetched, not after
tr ansmitting it. In the case of Receives, this bit is set
after the data fo r the last b uffer has b e e n written to
memory.
R/WC
1Current Equals Last
Va lid (CE LV)
0 = Clea re d by h ardware when controller exits state (i.e.,
until a new value is written to the LVI regis te r.)
1 = Current Index is equal to the v alue in the Last Valid Index
Register, and the bu ffer pointed t o by the CIV has been
processed (i.e., after the last valid buffer has been
processed). This bit is very similar to bit 2, except this bit
reflects the state rather than the event. This bit reflects
the state of the controller and remains set until the
contr olle r exits this s t at e .
RO
0DMA Co n troller Halted
(DCH)
0 = Running.
1 = H alted. T his c ou l d happen bec ause of the Sta r t/ Sto p b i t
being cleared and t he DMA engines are idle, or it could
happen once the controller has processed the last valid
buffer.
RO
Device: 31 Function: 5
I/O Address:
NABMBAR + 0 6h (PI SR) , NABMBAR + 16h
(POSR), NABMBAR + 26h (M CSR ), MBBAR
+ 46h (MC2SR), MBBAR + 56h (PI2SR),
MBBAR + 66h (S PS R)
Attribute: Read/W rite Clear, Read-Only
Defau lt Value: 0001h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 571
13—Intel® 6300ESB ICH
13.2.5 x_PICB—Position In Current Buffer Re gister
13.2.6 x_PIV—Prefetched Index Value Register
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported.
Table 489. x_PICB—Position In Current Buffer Register
Bits Name Description Access
15:0 Position In Current
Buffer[15:0]
These bits represent the number of s amples left to be
proces sed in the current buffer. This means the number of
samples not yet read from memory (in the case of reads f rom
mem ory ) or not y et writte n to me mory (in the case of write s
to mem ory ) irre spective of the numb e r of sa mp le s that have
been transmitted/received across AC-link.
RO
Table 490. x_PIV—Prefetched Index Value Register
Bits Name Description Access
7: 5 Ha rd wired to 0.
4:0 P r efetc h ed Ind ex
Value[4:0]
These bits represent which buffer descriptor in the list has
been prefetched. The bits in this register are also modulo 32
and roll over afte r the y re a ch 31. RO
Device: 31 Function: 5
I/O Address:
NABMBAR + 08h (PIPICB), NABMBAR +
18h (POPICB) , NABMBAR + 28h
(MCPICB) , MBBAR + 48 h (MC2 PI CB),
MBBA R + 58h (PI2PICB), MBBAR + 68h
(SPPICB)
Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
I/O Address:
NABMBAR + 0Ah (PIPIV ), NAB MBAR + 1Ah
(POPIV ), NABM B A R + 2A h (MCPIV ),
MBBAR + 4Ah (MC2PIV), MBBAR + 5Ah
(PI2PIV ), MB BAR + 6Ah (S PPIV )
Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
572 Order Number: 300641-004US
13.2.7 x_CR— Co ntro l Register
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported.
13.2.8 GLO B_CNT—Global Control Register
Note: Reads across dWord boundaries are not supported.
Table 491. x_CR—Control Register
Bits Name Description Access
7:5 Reserved Reserved.
4Interrupt On Completion
Enable (IOCE)
This bit con trols whethe r or n ot an interru p t occurs when a
buffer com p le te s with the IOC bit set in its descrip tor.
0 = Disa bl e. Inter ru p t will not occur.
1 = Enable.
R/W
3FIFO Error Interrupt
Enable (FEIE)
This bit controls whethe r th e occurrenc e of a FIFO e rror will
cause an interrupt or not.
0 = Disa bl e. Bit 4 in the S ta tus Regis te r will b e s et , but the
interrupt will not occur.
1 = Ena bl e. Inter rup t will occur.
R/W
2Last Valid Buffe r
Interrupt Enable (LVBIE)
This bit controls wheth e r the completion of the las t valid
buffer will cause an in te rrup t or n ot.
0 = Dis abl e. Bit 2 in the Status register will still be se t, b u t
the inte rrup t will not occur.
1 = Enable.
R/W
1 Reset Registers (RR)
0 = Removes re se t con d ition.
1 = Con te n ts o f all B us maste r re la te d registers to be rese t,
except the interrupt enable bits (bit 4,3,2 of this
register). S of tware ne eds to set th is bit but need not
clear it sin ce the bit is se lf cleari ng. This bit mus t be se t
onl y when the Run/ Pau s e bit is cleared. Setting i t when
the Run bit is set will cause und efi ned conseq ue nces.
R/W
(special)
0Run/Pause Bus master
(RPBM)
0 = Pause b u s master op eration. This res u lts in a ll state
information being re tain e d (i.e ., mas te r mod e op eration
may be stopped and then resumed).
1 = Run. Bus master operation starts.
R/W
Device: 31 Function: 5
I/O Address:
NABMBAR + 0Bh (PICR ), NABMBAR + 1Bh
(POCR) , NA BMBAR + 2Bh (MCCR ), MBBAR
+ 4Bh (MC 2CR), M B B A R + 5Bh (P I2CR),
MBBAR + 6B h (SP CR)
Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 573
13—Intel® 6300ESB ICH
Table 492. GLOB_CNT —Glo bal Control Re gister (Sheet 1 of 2)
Bits Name Description Access
31:3
0S/PDIF Slot Map (SSM)
When the run/pause bus master bit (bit ’0’ of offs et 2Bh) is
set, the value in these bits indicates which slots S/PDIF data
is transmitted on. Software must ensure that the
programmi ng here does not co nfl ict with the PCM c hanne ls
bein g use d. When the re is a conflict, unp re dictable beha v ior
will res ult; th e ha rd wa re will not check for a co nfl ict.
00 - Reserved
01 - Slots 7 and 8
10 - Slots 6 and 9
11 - Slots 10 and 11
R/W
29:2
4Reserved Reserved.
23:2
2PCM Out Mode (POM )
Enables the PCM out channel to use 16 or 20-bit aud io on
PCM out. This does not affect the microphone of S/PDIF DMA.
When g re ate r tha n 16-b it aud io is used , the da ta struc ture s
are alig ne d as 32 bits per sample, with the highest order bi ts
repre senting the data and the lower order bits as “do not
care”.
00 = 16 bit audio (default)
01 = 20 bit audio
10 = Reserved. When set, indeterminate behavior wi ll re sult.
11 = Reserved . W he n set, in d et er mina te b e h avio r will re su lt.
R/W
21:2
0PCM 4/6 Enable
Configur es PCM Outp ut fo r 2, 4 or 6 channel m ode.
00 = 2-channe l mod e (d e fault)
01 = 4-channe l mod e
10 = 6-channe l mod e
11 = Reserved
R/W
19:7 Reserved Reserved.
6AC_SDIN 2 Inte rrupt
Enable (S2RE)
0 = D isa b le .
1 = Enab le an in te rrup t to occ ur whe n the cod e c on
AC_SDIN[2] causes a resume event on the AC-link. R/W
5AC_SDIN1 Resume
Interrupt Enable (S1RE)
0 = D isa b le .
1 = Enab le an in te rrup t to occ ur whe n the cod e c on
AC_SDIN[1] causes a resume event on the AC-link. R/W
4AC_SDIN0 Resume
Interrupt Enable (S0RE)
0 = D isa b le .
1 = Enab le an in te rrup t to occ ur whe n the cod e c on
AC_SDIN[0] causes a resume event on the AC-link. R/W
3 ACLINK Shut Off (LSO) 0 = Normal operatio n.
1 = Controller disables all outpu ts which will be pulled low by
internal pull down re sistors. R/W
Device: 31 Function: 5
I/O Address: NABMBAR + 2Ch Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
574 Order Number: 300641-004US
13.2.9 GLO B_STA—Global Status Register
Note: Reads across dWord boundaries are not supported.
2AC97 Warm Reset
0 = Norma l op e ration .
1 = Writing a ‘1’ to this bit causes a warm rese t to occ ur on
the AC-link. The wa rm re set will awaken a susp e n d ed
codec w ith out clea ring its int er n al re gi st e rs. When
software attempts to perform a warm reset while bit_clk
is running , the write will be ignore d and the bit will not
chang e . This bit is se lf-clearing; it rem a ins se t u ntil the
reset complete s and bit_clk is seen on the ACLink, after
which it c le a rs itse lf.
R/W
(special)
1 AC’ 97 Cold Reset#
0 = Writing a ‘0’ to this bit causes a cold reset to occur
throughout th e AC’97 c ircuitry. All data in the contr olle r
and the codec will be lost. Software must clear this bit no
sooner than the minimum numb er of ms have elapsed.
1 = This bit de fau lts to ’0’ and h ence , after reset, the driver
needs to set th is bit to a ‘1’. The value of this b it is
retained after suspends ; hen ce, when this bit is set to a
’1’ prior to suspend ing , a cold re set is not gene rate d
automatically upon resuming.
NOTE: This bit is in the Core well.
R/W
0GPI Inte rrupt Enab le
(GIE)
This bit cont rols whethe r the ch an g e in sta tus of any GPI
causes an interrupt.
0 = Bit ’0’ of the Glob al Stat us Register is se t, but no
interrupt is generated.
1 = The change on value of a GPI causes an interrupt and
sets bit ’0’ of the Global Status Regis ter.
R/W
Table 492. GLOB_CNT—Global Control Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 5
I/O Address: NABMBAR + 2Ch Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 575
13—Intel® 6300ESB ICH
T abl e 49 3. GL O B _ ST A— Gl ob a l Sta tu s Re g is te r (S he e t 1 of 3)
Bits Name Description Access
31:3
0Reserved Reserved.
29 AC_SDIN2 Resume
Interrupt (S2RI)
This b it ind icate s that a resume eve nt occurred on
AC_SDIN[2].
0 = Clea re d by writing a ’1’ to this bit position.
1 = Resume ev ent occurred.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/WC
28 AC_SDIN2 Codec Ready
(S2CR)
R efl ec ts the state of the codec ready bit in AC_SDIN[2]. Bus
mas te rs ig n ore the co ndition of the cod ec re a dy b its, so
software must check this bit before starting the bus masters.
Once the codec is “ready, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
27 Bit Clock Stopped (BCS)
In di c ate s t ha t t he b i t cl oc k i s no t r un nin g . Th is bi t i s s et w he n
the Intel® 6300ESB ICH detects that there has been no
transition on BIT_CLK for four consecutive PCI clocks. It i s
cleared when a tra nsit ion is foun d on BIT _CLK.
RO
26 S/PDIF Inte rrupt
(SPINT)
Indicat es tha t the S/PDIF out channel interrup t status bits
hav e been s et . Wh en t he s pec ifi c statu s bit is c lear ed, th is b i t
will be clear ed. RO
25 PCM In 2 Interrupt
(P2INT)
Indicates that one of the PCM In 2 channel status bits have
been set. When the specific status bit is cleared, this bit will
be cleared. RO
24 M icrophone 2 In
Interrupt (M2INT)
Indicates that one of the Mic in channel interrupts status bits
has been set. When the specific stat us bit is cleared, this bit
will be clear ed. RO
23:2
2Samp le Ca p abilities
Indicates the capability to support greater than 16-bit audio.
00 = Reserved
01 = 16 and 20-bit Audio supported ( Intel® 6300ESB ICH
value)
10 = Reserved
11 = Reserved
RO
21:2
0Multichannel Capabilities Indicates the capability to support more 4 and 6 channels on
PCM Ou t. RO
19:1
8Reserved Reserved.
17 MD3
Power down semaphore for Modem. This bit exists in the
sus p end well and ma in tains context across power state s
(except G3). The bit has no hardware function. It is used b y
softwar e in conjunc tion with the AD3 bi t to coordinate the
entry of th e two codecs into D3 state.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/W
Device: 31 Function: 5
I/O Address: NABMBAR + 30h Attribute: Read-Only, Read/Write, Re ad/Write Clear
Defau lt Value: 00700000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
576 Order Number: 300641-004US
16 AD3
Power down semaphore for Audio. This bit exists in the
sus pend we ll a n d main ta ins contex t across powe r states
(except G3). Th e bit has no hard ware f unction. It is used by
software in con junc tion with the M D 3 bit to coordinate the
entry of the two cod ecs into D 3 state .
This bit is not affected by D3HOT to D0 Reset.
R/W
15 Read Co mpletion Status
(RCS)
This bit indicates t he status o f co de c r ead comple t ion s.
0 = A codec read comple te s n ormally.
1 = A codec read re sults in a t ime -o ut. The bit r em a ins set
until bei ng cleared by software writing a “1” to the bit
location.
This bit is not affected by D3HOT to D0 Reset.
R/WC
14 Bit 3 of slot 12 Display bit 3 of th e most re cent slot 12. RO
13 Bit 2 of slot 12 Display bit 2 of th e most re cent slot 12. RO
12 Bit 1 of slot 12 Display bit 1 of th e most re cent slot 12. RO
11 AC_SDIN 1 Res u m e
Interrupt (S1RI)
This bit indicates th a t a re su me event occu rred on
AC_SDIN[1].
0 = Clea re d by writing a ’1 ’ to this bit positi on.
1 = Resume event occurred.
This bit is not affected by D3HOT to D0 Reset.
R/WC
10 AC_SDIN 0 Res u m e
Interrupt (S0RI)
This bit indicates th a t a re su me event occu rred on
AC_SDIN[0].
0 = Clea re d by writing a ’1 ’ to this bit positi on.
1 = Resume event occurred.
This bit is not affected by D3HOT to D0 Reset.
R/WC
9AC_SDI N1 Code c Ready
(S1CR)
Reflects the state of the cod e c rea d y bit in AC_SDIN[1]. Bus
mas ter s ignore the con d ition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once th e cod e c is “ready”, it must never go “not re ady”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
8AC_SDI N0 Code c Ready
(S0CR)
Reflects the state of the codec ready bit in AC_SDIN [0]. Bus
mas ter s ignore the con d ition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once th e cod e c is “ready”, it must never go “not re ady”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
7 M ic In Interrupt (MINT) This bit indicates that one of the Mi c in ch an ne l in te rrupts
status bits h a s b een se t. When th e specific status b it is
cleared, this bit will be cleared. RO
Table 493. GLOB_STA—Global Status Register (Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 5
I/O Address: NABMBAR + 30h Attribute: Read-Only, Read/Write, Read/Writ e Clear
Defau lt Value: 00700000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 577
13—Intel® 6300ESB ICH
6PCM Out Interrupt
(POINT)
This bit ind icate s that one of the PCM out channel interrupts
status b its has be en set. W he n the specific status bit is
cleared, this bit w ill be cle ared. RO
5 PCM In Inte rrupt (PIIN T ) T his b it ind icates that one of the PCM in channel inte rrupts
status b its has be en set. W he n the specific status bit is
cleared, this bit w ill be cle ared. RO
4:3 Reserved Reserved.
2Modem Out Inte rrupt
(MOINT)
This b it indicate s that one of the mode m out channel
interr up ts status bit s has been set. When the spe cific status
bit is cleared, this bit will be cleared. RO
1Modem In Interrupt
(MIINT)
This bit indic ate s that one of the mode m inte rrup t status bits
has been set. When the specific stat us bit is cleared, this bit
will be clear ed. RO
0GPI Status Change
Interrupt (GS CI)
This bit re fl ects the state of bi t ’0’ in slot 12 and is set
whenev er bit ’0’ of slot 12 is set. This ind icate s that one of
the GPIs changed stat e and th at t he new v a lues are available
in slo t 12. The b it is cle a red by software writing a ‘1 ’ to this
bit loca tion.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/WC
T abl e 49 3. GL O B _ ST A— Gl ob a l Sta tu s Re g is te r (S he e t 3 of 3)
Bits Name Description Access
Device: 31 Function: 5
I/O Address: NABMBAR + 30h Attribute: Read-Only, Read/Write, Re ad/Write Clear
Defau lt Value: 00700000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
578 Order Number: 300641-004US
13.2.10 CAS—Codec Access Semaphore Register
Note: Reads across dWord boundaries are not supported.
13.2.11 SDM—SDATA_IN Map Regist er
Note: Reads across dWord boundaries are not supported.
Table 494. CAS—Codec Access Semaphore Register
Bits Name Description Access
7:1 Reserved Reserved.
0C odec Acce ss
Semaphore (CAS)
This bit is read by software to check whether a codec access
is c u rrently in p rogress.
0 = No access in progress.
1 = The act of re a d ing thi s regi ster se ts this b it to 1. The
driver that read this bit may then perform an I/O access.
Once the access is complete d, har dware a utomatica lly
clears thi s bit.
R/W
(special)
Table 49 5. SDM—SDATA_IN Map Register (Sheet 1 of 2)
Bits Name Description Access
7:6 PCM In 2, Microphone In
2 Data In Line (DI2L)
When the SE b it is set, the se b its ind icates which AC_SD I N
line should be used by the hardware for decoding the input
slots for PCM In 2 an d Microphone In 2. When the SE bit is
cleared, the value of these bits is irrelevant, and PCM In 2
and Mic In 2 DMA engines are not avai lable.
00 AC_SD IN0
01 AC_SD IN1
10 AC_SD IN2
11 Reserved
R/W
5:4 PCM In 1, Microphone In
1 Data In Line (DI1L)
When the SE b it is set, the se b its ind icates which AC_SD I N
line should be used by the hardware for decoding the input
slots for PCM In 1 an d Microphone In 1. When the SE bit is
cleared, the value of these bits is irrelevant, and the PCM In 1
and Mic In 1 engines use the OR’d AC_SDIN lines.
00 AC_SD IN0
01 AC_SD IN1
10 AC_SD IN2
11 Reserved
R/W
Device: 31 Function: 5
Offset: NABMBAR + 34h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 5
Offset: NABMBAR + 80h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 579
13—Intel® 6300ESB ICH
3 Steer Enable (SE)
When se t, the A C_S DIN line s are treat ed sep a rate ly and not
OR’d together befor e being se nt to the DMA e ngi ne s. Whe n
cleared, the A C_S D I N lines are OR’d together, an d the
Microphone In 2 and PCM In 2 DMA engines are not av ailable.
R/W
2 Reserved Reserved. RO
1:0 Last Co d ec Read D a t a
Input (L DI)
Whe n a codec reg iste r is read , t his indi cat e s wh ich AC_S DIN
the read data re turned on. Software ma y u se this to
determine how the codecs are mapped. The values are:
00 AC_SDI N0
01 AC_SDI N1
10 AC_SDI N2
11 Reserv ed
RO
Table 495. SDM—SDATA_IN Map Register (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 5
Offset: NABMBAR + 80h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—13
Intel® 6300ESB I/O Controller Hub
DS November 2007
580 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 581
14—Intel® 6300ESB ICH
AC’97 Modem Controller Registers
(D31:F6) 14
14.1 AC’97 Modem PCI Configuration Space
(D31:F6)
Note: Registers that are not shown should be treated as Reserved.
Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers
except the following BIOS progr ammed registers as BIOS may not be in voked following
the D3-to-D0 transition. Resume well registers will not be reset by the D3HOT to D0
transition.
Core Well registers not reset by the D3HOT to D0 transition:
Offset 2Ch-2Dh – Subsystem Vendor ID (SVID)
Offset 2Eh-2Fh – Subsystem ID (SID)
Table 496. PCI Configuration Map (Modem—D31:F6)
Offset Mnemonic Register Default Access
00-01h VID Vendor Identi fic ation 8086h RO
02-03h D ID Device Id e ntif ication 25A7h RO
04-05h PCICMD PCI Command 0 000h R/W
06-07h PCIS TA PCI Device Status 0290h R/ W C
08h RID Revision Identification See Note 1 RO
09 h P I Programming Interface 00h RO
0Ah S CC Sub Cla ss Code 03h RO
0Bh BCC Base Class Code 07h RO
0Eh HEDT Header Type 00h RO
10-13h MMB AR Modem Mixer Base Address 00000001
hR/W
14-17h MBAR M odem Bas e Addre ss 00000001
hR/W
2C- 2Dh SVI D Subsystem Vendor ID 0000h Write-Onc e
2E-2Fh SID Subs yste m ID 0000h Write-Once
34h CAP_PT R Capabilitie s Pointer 50h RO
3 C h I N TR_LN I n t errupt Line 00h R O
3Dh IN T_PN Interrupt Pin 02h RO
50-51h PID PCI Power Management ID 0001h RO
52-53h PC PC - Power Manageme nt Ca p ab ilities C9C2h RO
54-55h PCS Power Manageme nt Control and Status 0000h R/W
NOTES:
1. Refe r to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value o f the Revision ID Register.
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
582 Order Number: 300641-004US
Resume Well registers will not be reset by the D3HOT to D 0 tr an s i ti on:
Offset 54h-55h – Power Management Control and Status (PCS)
14.1.1 Offset 00 - 01h: VID—Vendor Identification
Register (Modem—D31:F6)
14.1.2 Offset 02 - 03 h: DID—Dev ice Identification
Register (Modem—D31:F6)
Tabl e 497. Offset 00 - 01h: VID—Vendor Identification Register (Modem—
D31:F6)
Bits Name Description Access
15:0 Vendor ID Value 16-bit field indicating the company vendor as Intel RO
Table 498. Offset 02 - 03h: DID—Device Identification Register (Modem—D31:F6)
Bits Name Description Access
15:0 Device ID Value Indicates the device number assigned by the SIG RO
Device: 31 Function: 6
Offset: 01 - 01h Attribute: Read-Only
Defau lt Value: 8086 Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 02 - 03h Attribute: Read-Only
Defau lt Value: 25A7h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 583
14—Intel® 6300ESB ICH
14.1 .3 Offset 04 - 05h: P CI CMD—PCI Command Register
(Modem—D31:F6)
Note: PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete
details on each bit.PCISTA—Device Status Register (Modem—D31:F6).
Tab l e 49 9. Of fse t 04 - 05h : PCI CMD— PCI Com ma n d R eg is ter (Mo d em —D 31 : F6)
Bits Name Description Access
15:1
0Re se rv e d Re se rv ed. Rea d 0.
9Fast Back - t o- Bac k
Enable (FBE) Not impl emented. Hardwired to ‘0’.
8 SERR# Enable (SEN) Not implemented. Hard wired to ‘0’.
7Wa it Cy cle Control
(WCC) Not implemented. Hardwired to ‘0’.
6Parity Error Response
(PER) Not implemented . Hardwired to ‘0’.
5VGA Pal ett e Sn oop
(VPS) Not implemented. Hardwired to ‘0’.
4Memory Write and
Invalidate Ena b le (MWI) Not imp lemented. Hardwired to ‘0’.
3Special Cycle Enable
(SCE) Not implemented. Hardwired to ‘0’.
2Bus M a ste r E n able
(BME)
Con trols sta ndard PCI bus ma ste ring capabilities.
0 = D isa b le
1 = Enable R/W
1 Memor y Sp ac e (MS) Hard wired to ‘0’; AC ‘97 doe s not resp ond to me mory
accesses.
0 I/O Sp ace (IOS )
Th is b it cont rols acc ess to the I /O sp a ce registers.
0 = D isa b le a cce ss (default = 0).
1 = E n a ble acce ss to I/ O space. The Nati v e PC I M o de Base
Address register should be programmed prior to setting
this bit.
R/W
Device: 31 Function: 6
Offset: 04 - 05h Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
584 Order Number: 300641-004US
14.1.4 Offset 06 - 07h: PCISTA—Device Status Register
(Modem—D31:F6)
Note: PCIST A is a 16-bit status register. Refer to the PCI 2.2 specification for complete details
on each bit.
Ta ble 500. Offset 06 - 07h: PCISTA—Device Status Register (Modem—D31:F6)
Bits Name Description Access
15 DPE (Detec te d Pa rity
Error) Not implemented. Hardwired to ‘0’. RO
14 SERRS (S ERR# S tatus) Not imp le men ted . Hard wired to ‘0’. RO
13 MAS (Mas te r-Abort
Status)
0 = Softwar e clears th is bit by writing a ‘1’ to the bit position.
1 = Bus Master A C ‘97 inte rf ace f unction, as a master,
generat e s a mast e r abort. R/WC
12 Reserved Reserved. Read as ‘0’. RO
11 STA (Signale d Target-
Abort Status) Not implemented. Hardwired to ‘0. RO
10:9 DE VT (DEVSEL # T iming
Status)
This 2-bit field re f le cts the Intel® 6300ES B ICH 's D EV S EL#
timing pa rame te r. T he se re a d- only bits in di cate the Intel®
6300E SB ICH's DEVSEL# timing when perf orming a positive
decode.
RO
8DPD (Data Parity
Detected) Not implemented. Hardwired to ‘0’. RO
7FBC (Fa st Back to back
Capable) Hardwired to ‘1’. This bit ind icate s t hat the Intel ® 6300ESB
ICH as a ta rget is cap a b le of fa st back-to - b a ck transactions. RO
6 UDF Supported Not implemented. Hardwired to ‘0. RO
5 66 MHz C apable Hardwired to ‘0. RO
4Capabil ities Li st Ex ists
(CLIST)
Indicates that the controller contains a capabilities pointer
list. The fir st ite m is pointed to by looking at confi guration
offset 34h. RO
3:0 Reserved Reserved.
Device: 31 Function: 6
Offset: 06 - 07h Attribute: Re ad/Write Clear
Defau lt Value: 0290h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 585
14—Intel® 6300ESB ICH
14.1.5 Offset 08h: RID—Revision Identification Register
(Modem—D31:F6)
14.1 .6 Off set 09h: PI—Prog r ammi ng I nterface Register
(Modem—D31:F6)
14.1 .7 Off set 0Ah: SCC—S ub Class Code Register
(Modem—D31:F6)
Table 501. Offset 08h: RID—Revision Identification Register (Modem—D31:F6)
Bits Name Description Access
7:0 R evision ID Value Refer to the Inte l® 6300ESB I/O Controller Hub Specification
Update for the most up-to-date value of the Revision ID
Register. RO
Table 502. Offset 09h: PI—Programming Interface Register (Modem—D31:F6)
Bits Name Description Access
7:0 Programming Interface
Value RO
Table 503. Offset 0Ah: SCC—Sub Class Code Register (Modem —D3 1:F6)
Bits Name Description Access
7:0 Sub Class Code Value 03h = Generic Modem. RO
Device: 31 Function: 6
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descript io n Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 03h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
586 Order Number: 300641-004US
14.1.8 Offse t 0 Bh: BCC—Base Class Code Regist er
(Modem—D31:F6)
14.1.9 Offset 0Eh: HEDT—Header Type Register
(Modem—D31:F6)
14.1.10 Offset 10 - 13h: MMBAR—Modem Mixer Base
Address Register (Modem—D31:F6)
Note: The Native PCI Mode Modem uses PCI Base Address register 1 to request a contiguous
block of
I/O space that is to be used for the Mo dem Mixer software interface. The mix er requi res
256 bytes of I/O space. All accesses to the mixer registers are forwarded over the AC-
link to the codec where the registers reside.
In the case of split codec implementation, accesses to the different codecs are
differentiated by t he controller by using address offsets 00h - 7Fh for the primary codec
and address offsets 80h - FEh for the secondary codec.
Table 504. Offset 0Bh: BCC—Base Class Code Register (Modem—D31:F6)
Bits Name Description Access
7:0 Base Class Code Value 07h = S imp le Communic ation s Con troller. RO
Table 505. Offset 0Eh: HEDT—Heade r Type Register (Modem—D31:F6)
Bits Name Description Access
7:0 He a der Value RO
Device: 31 Function: 6
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 07h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 0Eh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 587
14—Intel® 6300ESB ICH
14.1 .11 Offset 14 - 17h: MBAR—Modem Base Addr ess
Register (Modem—D31:F6)
Note: The Modem function uses PCI Base Address register 1 to request a contiguous block of
I/O space that is to be used for the Modem software interface. The Modem Bus
Mastering register space requires 128 bytes of I/O space. All Modem registers reside in
the controller; therefore cycles are not forwarded over the AC-link to the codec.
Table 506. Off set 10 - 13h: MMBAR—Modem Mixer Base Address Register
(ModemD31:F6)
Bits Name Description Access
31:1
6Reserved Hard wired to ‘0’.
15:8 Base Address
These bits are used in the I/O space decode of the Modem
interface registers. The number of upper bits that a device
actual ly i mplem ent s depends on how much of the addre ss
space the device will re spond to. For the AC ‘97 Mod e m, th e
upper 16 bits are hardwired to 0, while bits 15:8 are
progra mmable. T his configuration yields a ma x imu m I/O
block size of 256 by tes for this b a se a d dress.
R/W
7:1 Reserved Read as 0.
0Resource Type Indicator
(RTE) This bit is set to one, ind icating a request f or I/O spa ce. RO
Tab l e 50 7. Of fs e t 14 - 17h: MB A R —M odem Bas e Ad dr e ss Reg i ste r (Mo de m
D31:F6)
Bits Name Description Access
31:1
6Reserved Hard wired to ‘0’.
15:7 Base Address
These bits are used in the I/O space decode of the Modem
interface registers. The number of upper bits that a device
actual ly i mplem ent s depends on how much of the addre ss
space the device will re spond to. For the AC ‘97 Mod e m, th e
upper 16 bits are hardwired to ‘0’, while bits 15:7 are
progra mmable. T his configuration yields a ma x imu m I/O
block size of 128 by tes for this b a se a d dress.
R/W
6:1 R eser ved Rese rv ed. R ead as ‘0’.
0Resource Type Indicator
(RTE) This bit is set to ‘1’, indicating a re quest for I/O space. RO
Device: 31 Function: 6
Offset: 10 - 13h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 14 - 17h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
588 Order Number: 300641-004US
14.1.12 Offset 2C - 2Dh: SVID—Subsystem Vendor I D
(Modem—D31:F6)
Note: This register should be implemented for any function that could be instantiated more
than once in a given system. For example, a system with two audio subsystems, one
on the motherboard and the other plugged into a PCI expansion slot, should have the
SVID register implemented. The SVID register, in combination with the Subsystem ID
register, enable the operating environment to distinguish one audio subsystem from
th e ot h e r( s ) .
Note: Software (BIOS) will write the value to this register. After that, the value may be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3HOT to D0 reset.
14.1.13 Offse t 2 E - 2 F h: SID—Subs yst em ID (Modem—
D31:F6)
Note: This register should be implemented for any function that could be instantiated more
than once in a given system; for example, a system with two audio subsystems, one on
the motherboard and the other plugged into a PCI expansion slot. The SID register, in
combination with the Subsystem Vendor ID register, make it possible for the operating
environment to distinguish one audio subsystem from the other(s).
Note: Software (BIOS) will write the value to this register. After that, the value may be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write. This register is not
affected by D3HOT to D0 reset.
Table 508. Offset 2C - 2Dh: SVID—Subsystem Vendor ID (Modem—D31:F6)
Bits Name Description Access
31:1
6Reserved Hardwired to ‘0’s.
15:7 Base Address
These bits are used in the I/O space dec ode of the Modem
interface registers. The number of upper bits that a device
actually implements depends on how much of the address
space the dev ice will res p ond to. For the AC ‘97 Modem , the
upper 16 bits are hardwired to ‘0’, while bits 15:7 are
program mab le . This configura tion yields a max imu m I/O
block size of 128 b ytes for th is ba se a ddress.
R/W
6:1 Reserved Reserved. Read as ‘0’. RO
0Re so ur ce Typ e In di cat or
(RTE) This bit is set to ‘1’, indicating a request f or I/O space. RO
Device: 31 Function: 6
Offset: 2C - 2Dh Attribute: Write-Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 589
14—Intel® 6300ESB ICH
14.1.14 Offset 34h: CAP_PTR—C a pabilities Pointer
(Modem—D31:F6)
Note: This r egi st er ind ica t es the of fse t for the ca p ab ili ty po int e r.
14.1 .15 Off set 3Ch: INTR _LN—Interrupt Line Register
(Modem—D31:F6)
Note: This register indicates which PCI in terrupt line is used for the AC’97 module interrupt.
Table 509. Offset 2E - 2Fh: SID—Subsystem ID (Modem—D31:F6)
Bits Name Description Access
15:0 S u b system ID Value R/WO
Table 510. Offset 34h: CAP_PTR—Capabilities Pointer (Modem—D31:F6)
Bits Name Description Access
7 :0 Capa b ility Pointer (CP) Indica te s that the first capability pointer offse t is of f se t 50h. RO
Table 511. Offset 3Ch: INTR_LN—Interrupt Line Register (Modem—D31:F6)
Bits Name Description Access
7 :0 In te rru p t Line This data is not used by the Intel® 6300ESB ICH. It is used to
communicate to so ftwar e the interrupt line that the inter rup t
pin is connected to. R/W
Device: 31 Function: 6
Offset: 2E-2Fh Attribute: Write-Once
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 34h Attribute: Read-Only
Defau lt Value: 50h Size: 8-bit
Lockable: No Power Well: Core
Device: 31 Function: 6
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
590 Order Number: 300641-004US
14.1.16 Offse t 3 Dh: INT_PIN—Interrupt P i n ( Modem—
D31:F6)
Note: This register indicates which PCI interrupt pin is used for the AC’97 modem interrupt.
The AC’97 interrupt is internally OR ’d to the interrupt controller with the PIRQB# signal.
14.1.17 Offset 50h: PID—PCI Power Management
Capability ID Register (Modem—D31:F6)
Table 512. Offset 3Dh: INT_PIN—Interrupt Pin (Modem—D31:F6)
Bits Name Description Access
7:3 Reserved Reserved.
2:0 AC’97 Interrupt Routing Hardwired to 010b to sele ct PIR QB #. RO
Table 513. Offset 50h: PID—PCI Power Management Capability ID Register
(Modem—D31:F6)
Bits Name Description Access
15:8 Ne x t Ca p a bi lity (NEX T) Indicates that this is the last ite m in the lis t. RO
7:0 Cap ID (CA P) Indicates that this pointe r is a me ssage signaled inte rrupt
capability. RO
Device: 29 Function: 5
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 02h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 0001h Attribute: Read-Only
Defau lt Value: 0001h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 591
14—Intel® 6300ESB ICH
14.1.18 Off set 52h: PC— Power Mana gement Capabilities
Register (Modem—D31:F6)
14.1 .19 Offset 54h: PCS—P o wer Management Control and
Sta t us Registe r (Mod em —D 31 : F 6)
Note: This regi ster is not affe cted by the D3HOT to D0 transition.
Table 514. Offset 52h: PC—Power Management Capabilities Register (Modem
D31:F6)
Bits Name Description Access
15:1
1PME_Support Indicates PME# may be generated from all D states. RO
10:9 Reserved Reserved. RO
8:6 Aux_Current Reports 375 mA maximum Suspe n d well curre nt re q uire d
when in the D3cold state. RO
5Device Speci fic Initia l-
ization (D S I ) Indicates tha t no device-specific initializatio n is required . RO
4 Reserved Reserved. RO
3 PME Clock (PMEC) Indicates that PCI clock is not required to generate PME#. RO
2:0 Version (VS) Indicates support for Revision 1. 1 of the PCI Power
Management S pecification. RO
Table 5 15. Offset 54h: PCS—Power Management Control and Status Register
(Modem—D31:F6) (Sheet 1 of 2)
Bits Name Description Access
15 PME Status (PMES) This b it is se t wh e n the AC’97 cont rolle r would norma lly
assert the PME# signal independent of the state of the
PME_E n bit. T his bit re sid es in the re sume well. RW/C
14:9 Reserved Reserved. RO
Device: 29 Function: 5
Offset: 52h Attribute: Read-Only
Defau lt Value: C9C2h Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 54h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
592 Order Number: 300641-004US
8Power Management
Event Enable (PMEE) W he n set, a nd if cor resp ond ing PMES is also set, the A C'97
controller se ts the AC97 _S TS bit in the GPE0_S TS register. R/W
7:2 Reserved Reserved. RO
1:0 P o we r Stat e (PS)
This field is used both to determine the current power state of
the AC’ 97 cont rolle r and to set a new power state. The v alues
are:
00 – D0 state
01 – not supporte d
10 – not supporte d
11 – D3HOT st a te
When in the D3HOT sta t e , the AC’ 97 con troller’s configura tion
space is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked.
When software attempts to write a value of 10b or 01b to this
field, the write operation must com p le te no rma lly. H owe v e r,
the data is discarded and no state change occurs.
R/W
Table 515. Offset 54h: PCS—Power Management Control and Status Register
(Modem—D31:F6) (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 5
Offset: 54h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Resume
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14—Intel® 6300ESB ICH
14.2 AC’97 Modem I/O Space (D31:F6)
In the case of split codec implementation, accesses to the modem mixer registers in
different co decs are differentiated by the controller by using address offsets 00h - 7Fh
for the primary codec and address offsets 80h - FEh for the secondary codec. Table 516
shows the register addresses for the modem mixer registers.
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) regis ters are aliased to
the same global registers in the audio and modem I/O space. Therefore a read/write to
these registers in either audio or modem I/O space affects the same physical register.
S/W could access these registers as bytes, word, or dWord quantities, but reads must
not cross dWord boundaries.
These registers exist in I/O space and reside in the AC ‘97 controller. The two channels,
Modem in and Modem out, each have their own set of Bus Mastering registers. The
following register descriptions apply to both channels. The naming prefix convention
Tab l e 51 6. Int el® 6300ESB I/O Controller Hub Modem Mixer Register
Configuration
Register MMBAR Ex posed Registers ( D 31:F6)
Primary Secondary Name
00h:38h 80h:B8h Intel Reserv ed
3Ch BCh Extended Modem ID
3Eh BEh Extended Modem Stat/Ctrl
40h C0h Line 1 DAC/ADC Rat e
42h C2h Line 2 DAC/ADC Rat e
44h C4h Handset DAC/ADC Rate
46h C6h Line 1 DAC/ADC Level Mute
48h C8h Line 2 DAC/AD C Lev el Mu te
4Ah CAh Handset DAC/A DC L e vel Mu te
4Ch CCh GPIO Pin Config
4Eh CEh G PIO Polarity /Type
50h D0h GPIO Pin Stic ky
52h D2h GPIO Pin Wake Up
54h D4h GPIO Pin Status
56h D6h Misc. Modem AFE Stat/Ctrl
58h D8h AC’97 Reserved
5Ah DAh V endor Reserv ed
7Ch FCh V endor ID1
7Eh FEh V endor ID2
NOTES:
1. Registers in italics are for functions not suppor ted b y the Intel® 6300ES B ICH.
2. Softwa re should n ot t ry t o a cce ss reserv ed registers.
3. The Intel® 6300ESB ICH supports a modem codec connected to AC_SDIN[2:0] as long as the
Codec ID is 00 or 01. However, the Intel® 6 300ES B ICH do es n ot supp ort more than one
modem codec. For a complete list of topologies, see the Intel® 875P/E7210/6300ESB Chipset
Plat fo r m Design Guide.
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
594 Order Number: 300641-004US
used is as follow s:
MI = Modem in channel
MO = Modem out channel
Table 517 presents the modem registers.
Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers
except the registers shared with the AC’97 Audio Controller (GCR, GSR, CASR).
Resume well registers will not be reset by the D3HOT to D0 transition.
Core Well registers and bits not reset by the D3HOT to D0 transition:
Offset 3Ch-3Fh – bits[6:0] Global Control (GLOB_CNT)
Offset 40h-43h – bits[29,15,11:10] Global Status (GLOB_STA)
Offset 44h – Codec Access Semaphore Register (CAS)
Resume Well registers and bits will not be reset by the D3HOT to D0 transition:
Offset 40h-43h – bits[17:16] Global Status (GLOB_STA)
Table 517. Modem Registers
Offset Mnemonic Name Default Access
00h MI_BDB AR Modem In Buffer Descriptor List Base Address
Register 00000000
hR/W
04h MI_C IV Modem In Curr en t Index Value Register 00h R
05h MI_LVI Modem In Las t Valid In dex Register 00h R/W
06h M I_S R Mode m In S tatus Register 0001h R/W
08h MI_PIC B Mode m In Position In Curr e nt Buff er Register 00h R
0Ah MI_PIV Modem In Prefetch Index Value Register 00h RO
0Bh MI_CR Mode m In Control Register 00h R/W
10h MO_BDBAR Mod em Out Buffer Descriptor List Base
Address Register 00000000
hR/W
14h MO_C IV Mod e m Out Current Index Value Register 00h RO
15h MO_LVI Mod e m Out L a st Valid Register 00h R/W
16h MO_SR Mod em Out S tatus Register 0001h R/W
18h MI_PIC B Mode m In Position In Curr e nt Buff er Register 00h RO
1Ah M O_PIV Modem Out Prefetched Index Register 00h RO
1Bh MO_CR Mod em Out Control Registe r 00h R/W
3Ch G LOB_ CNT Global Con trol 00000000
hR/W
40h GLOB_STA Global Status 00000000
hRO
44h ACC_SEMA Codec Write Semaphore Register 00h R/W
NOTE: MI = Modem in channel; MO = Modem out channel
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 595
14—Intel® 6300ESB ICH
14.2.1 x_BDBAR—Buffer Descriptor List Base Address
Register
Note: Software may read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across dWord boundaries are not supported.
14.2.2 x_CIV—Current Index Value Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
bou ndar i es are not supp orte d.
Table 518. x_BDBAR— Buffer Descriptor List Base Address Register
Bits Name Description Access
31:3 Buffer Descriptor List
Base Address [ 31:3 ] These b i ts re pres en t addres s bi t s 31:3. T he en t rie s sh ou ld be
aligned on 8-byte boundaries. R/W
2:0 Hardwired to ‘0.
Table 519. x_CIV—Current Index Value Register
Bits Name Description Access
7:5 Hardwired to ‘0.
4:0 Current Index Value
[4:0]
These bits represent which buffer descriptor within the list of
16 descriptors is being processed currently. As each
descriptor is p rocessed , this value is in cremente d. RO
Device: 29 Function: 5
I/O Address: MBA R + 00h (MIB D B AR ),
MBAR + 10h (MOBDBAR) Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: MBAR + 04h (MICIV),
MBAR + 14h (M OCIV) Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
596 Order Number: 300641-004US
14.2.3 x_LVI—Last Valid Index Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software may also read this
register individuall y by doing a single, 8-bit read to of fset 05h. Reads across dWord
boundaries are not supported.
14.2.4 x_SR—Stat us Regist er
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software may also read this
register individually by doing a single, 16-bit read to offset 06h. Reads across dWord
boundaries are not supported.
Table 520. x_LVI—Last Valid Index Register
Bits Name Description Access
7:5 Hardwired to 0 Har dwired to 0.
4:0 La st Valid Ind e x [4: 0] These bits indic a te the last valid descrip t or in th e list. This
value is updated by the software as it prepares new buffers
and adds to the list. R/W
Table 521. x_SR—Status Register (Sheet 1 of 2)
Bits Name Description Access
15:5 Reserved Reserved.
4 FIFO e rror ( FIF OE)
0 = Clea re d by writing a ‘1 ’ to this bit positi on.
1 = FIFO error occurs.
Modem in: FIFO e rror indic ate s a FIFO overru n. The FIFO
pointers don't increment, the incoming data is not written
into the FIFO, thereb y be ing lost.
Modem out: FIFO error indicat es a FIFO underrun. The
sam ple t ran smitted in thi s ca se should be th e la st valid
sample.
The I n t el® 6 300ES B ICH will set the FIFOE bit if the under-
run or over run occurs when there are more valid buffers to
process.
R/WC
3Buffer Completion
Interrupt Status (BCIS)
0 = Clea re d by writing a ‘1 ’ to this bit positi on.
1 = Set by the hardwa re aft er th e last sam ple o f a buffer has
been processed, AND if the Interrupt on Completion
(IOC) bit is set in the com man d byte of the buff e r
descrip tor. Remains active unt il software clea rs bit.
R/WC
Device: 29 Function: 5
I/O Address: MBAR + 05h (MILVI),
MBAR + 15h (MOLVI) Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: MBAR + 06h (MISR),
MBAR + 16h (M OS R) Attribute: Read/Write Clear
Defau lt Value: 0001h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 597
14—Intel® 6300ESB ICH
14.2.5 x_PICB—Position in Current Buffer Register
Note: Software may read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-
bit read from address offset 08h. Software may also read this register individually by
doing a single 16-bit read to offset 08h. Reads across dWord boundaries are not
supported.
2Last Valid Buffer
Comp le tion Inte rrupt
(LVBCI)
0 = Clea re d by writing a ‘1’ to this bit position
1 = Set by hardware w hen last valid buffer has been
proce ssed. I t rem a in s a ctive until cleare d by s o ft w are .
This bi t i ndi c ates t he o ccu rr en ce of th e ev en t s ig nif i ed by
the last valid b uffe r b e in g proc e sse d . Thus, this is an
event status bit that may be cleared by software once
this event has been recognized. This event will cause an
interrupt if the ena ble b it in th e Control Register is set.
The interrupt is cleared when the software clears this bit.
In the case of transmits (PCM out, Modem out), this bit is
set afte r the la st valid buffe r ha s be en fe tched (not a f ter
transmitting it). In the case of Receives, this bit is set
after the data for the la st bu f fer has been written to
memory.
R/WC
1Curren t Equal s Last
Valid (CELV)
0 = Hardware clears when controller exits state (i.e., until a
new value is written to the LVI register).
1 = Current Index is equal to the value in the Last V alid Index
Register, AND the buffe r po inte d to by the CIV has been
proc essed ( i.e., after the last valid buff er has been
proc essed). This bi t i s very sim ilar to b it 2, exc ept this bi t
refle cts the st ate rather than the e vent. This bit reflects
the state of the controller and rem ains set until the
con trolle r e xits this stat e .
RO
0DMA Controller Halted
(DCH)
0 = Running.
1 = Halted. This could happen because of the Start/Stop bit
being cleared and the DMA engines are i dle, or it could
happen once the controller has processed the last valid
buffer.
RO
T abl e 522. x _P IC B— Po sit io n in Curr e nt Buf fe r Reg ist er
Bits Name Description Access
15:0 Position In Current
Buffer[15:0] T hese bits repr esent the number of s amples left to be
proce ss ed in the curren t buff er. RO
Table 521. x_SR—Status Register (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 5
I/O Address: MBA R + 06h (MIS R),
MBAR + 16h (M OS R) Attribute: Read/W rite Clear
Defau lt Value: 0001h Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: MBAR + 08h (MIPICB),
MBAR + 18h (M OPICB) Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
598 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 599
14—Intel® 6300ESB ICH
14.2.6 x_PIV—Prefetch Index Value Register
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported.
14.2.7 x_CR—Co ntro l Register
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported.
Table 523. x_PIV—Prefetch Index Value Register
Bits Name Description Access
15:0 Position In Current
Buffer[15:0] T hese bits repr esent the number of s amples left to be
proce ss ed in the curren t buff er. RO
T abl e 52 4. x _C R Con t rol Re g is te r (S he e t 1 of 2)
Bits Name Description Access
7:5 Reserved Reserved.
4Interrupt On Completion
Enable (IOCE)
This b it contr ols whethe r or not an interrup t occurs when a
buffer completes with the IOC bit set in its desc rip tor.
0 = D isa b le
1 = Enable
R/W
3FIFO Erro r I nte rrupt
Enable (FEIE)
This b it con trols whethe r the occurrence of a FIFO error will
cause an interrupt or not.
0 = D isable. Bit 4 in the Status Registe r will b e se t, but th e
interr upt wi ll not occur.
1 = Enable. Interrupt will occur.
R/W
Device: 29 Function: 5
I/O Address: MBAR + 0A h (MIPIV ),
MBAR + 1Ah (MOPIV) Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: MBAR + 0Bh (MICR),
MBAR + 1Bh (MOCR ) Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
600 Order Number: 300641-004US
14.2.8 GLO B_CNT—Global Control Register
Note: Reads across dWord boundaries are not supported.
2Last Valid Buffe r
Interrupt Enable (LVBIE)
This bit controls wheth e r the completion of the las t valid
buffer will cause an in te rrup t or n ot.
0 = Dis abl e. Bit 2 in the Status register will still be se t, b u t
the inte rrup t will not occur.
1 = Enable
R/W
1 Reset Registers(RR)
0 = Removes re se t con d ition.
1 = Con te nt s o f all register s to b e reset, except t he int er ru p t
enable bits (bit 4,3,2 of this register). Software must s et
this bit. It must be set only whe n the Run/Pause bit is
cleared. Setting it when the Run bit is set will cause
undefine d con sequenc e s. This bit is self-clearing
(software needs not clear it).
R/W
(special)
0Run/Pause B u s M a ster
(RPBM)
0 = Pause b u s master op eration. This res u lts in a ll state
information being re tain e d (i.e ., mas te r mod e op eration
may be stopped and then resumed).
1 = Run. Bus master operation starts.
R/W
Table 525. GLOB_CNT—Global Control Register (Sheet 1 of 2)
Bits Name Description Access
31:7 Reserved Reserved
6AC_SDIN2 Interrupt
Enable (S2RE)
0 = Disabl e.
1 = Enable an interrupt to occur when the codec on
AC_SD IN[ 2] causes a r es ume event on the AC-l i nk. R/W
5AC_SDIN 1 Res u m e
Interrup t Enab le (S1R E)
0 = Disabl e.
1 = Enable an interrupt to occur when the codec on
AC_SD IN[ 1] causes a r es ume event on the AC-l i nk. R/W
4AC_SDIN 0 Res u m e
Interrup t Enab le (S0R E)
0 = Disabl e.
1 = Enable an interrupt to occur when the codec on
AC_SD IN[ 0] causes a r es ume event on the AC-l i nk. R/W
3 ACLINK Shut Off ( LSO) 0 = No rmal op e ra tion.
1 = Controller disables all outputs which will be pulled low by
internal pull down resistors. R/W
Table 524. x_CR—Control Register (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 5
I/O Address: MBAR + 0Bh (MICR),
MBAR + 1Bh (MOCR ) Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: MBAR + 3Ch Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 601
14—Intel® 6300ESB ICH
14.2.9 GLOB_ STA—Global Status Register
Note: On reads from a codec, the controller will give the codec a maximum of four frames to
respond, aft er which, if no response is received, it wil l return a dummy read co mpletion
to the processor (with all ‘F’s on the data) and also set the Read Completion Status bit
in the Global Status Register.
Reads across dWord boundaries are not supported.
2 AC’97 Warm Reset
0 = Normal operatio n.
1 = Writing a ‘1’ to this bit causes a warm reset to oc cur on
the AC-link. The warm re se t will a waken a su sp e n d e d
codec w ithout clea ring its in te rn al registers. Whe n
software a tte mpts to perfor m a warm re se t while bit_clk
is running, the write will b e ignored and the bit wi ll n ot
change. This bit is self-clearing; it remains set until the
reset co mp le te s an d bit_ clk is see n on the AC Link, af te r
whic h it cle a rs itself.
R/W
(special)
1AC97 Cold Reset#
0 = Writing a ‘0’ to this bit causes a cold reset to occur
througho ut the AC ‘97 circui try. All data in the controller
and the cod ec will be lost. Software must clear this bit no
sooner than the minimum number of ms have elapsed.
1 = This bit def aults to ’0’ and hence aft er rese t, the dri ver
needs to se t this bit to a ‘1’. T he value of this bit is
retained after suspends; hence, when this bit is set to a
’1’ prior to su sp en din g, a co ld reset is not generated
autom atically upon resu ming .
NOTE: This bit is in the Core we ll.
R/W
0GPI Interrupt Enable
(GIE)
This b it con trols whethe r the chan ge in sta tus of any GPI
cau ses an inte rrup t.
0 = Bit ’0’ of the Global S tatus Regis te r is set, but no
interr upt is generate d.
1 = The change on value of a GPI causes an interrupt and
sets bit ’0’ of the Global Status Register.
R/W
Table 525. GLOB_CNT —Glo bal Control Re gister (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 5
I/O Address: MBAR + 3Ch Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
602 Order Number: 300641-004US
Table 526. GLOB_STA—Global Status Register (Sheet 1 of 3)
Bits Name Description Access
31:3
0Reserved Reserved.
29 AC_SDIN 2 Res u m e
Interrupt (S2RI)
This bit indicates th a t a re su me event occu rred on
AC_SDIN[2].
0 = Clea re d by writing a ’1 ’ to this bit positi on.
1 = Resume event occurred.
This bit is not affected by D3HOT to D0 Reset.
R/WC
28 AC_SDI N2 Code c Ready
(S2CR)
Reflects the state of the cod e c rea d y bit in AC_SDIN[2]. Bus
mas ter s ignore the con d ition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once th e cod e c is “ready”, it must never go “not re ady”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
27 Bit Clock Stopped (BCS) Indicates that the bit clock is not running. This bit is set when
the Intel® 6300ESB I CH det ec t s that t her e has been no
trans ition on BI T_CLK for four c onsecut i ve PCI clo c ks. It is
cleared when a transition is found on BIT_CLK. RO
26 S/PDIF Inte rrupt
(SPINT) Indicates that the S/PD IF out channel interrupt status bits
have been set. Whe n the specific status bit is cleared, this bit
will be cle are d. RO
25 PCM In 2 Interrupt
(P2INT) Indica tes that on e of the PCM In 2 ch a nn e l sta tus bit s ha ve
been set. When the specific status bit is cleared, this bit will
be c lear ed. RO
24 Microphone 2 In
Interrupt (M2IN T) Indicates that one of the Mic in channel interrupts status bits
has be en set. When the sp ecific sta tu s b it is cleare d, this bit
will be cle are d. RO
23:2
2Sample Capabilities
Indicates the capability to support more greater than 16-bit au-
dio.
00 = Reserved
01 = 16 and 20- bit Audio su pported (Intel ® 6300ESB ICH value)
10 = Reserved
11 = Reserved
RO
21:2
0Mul t icha nn e l Capabiliti es In d ica te s the ca p a b ility to support more 4 and 6 cha nnels on
PCM Out. RO
19:1
8Reserved Reserved.
Device: 29 Function: 5
I/O Address: MBAR + 40h Attribute: Read-Only, Read/Write, Re ad/Write Clear
Defau lt Value: 00300000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 603
14—Intel® 6300ESB ICH
17 MD3
Power down semaphore for Modem. This bit exists in the
sus p end well and ma in tains context across power state s
(except G3). The bit has no hardware function. It is used b y
softwar e in conjunc tion with the AD3 bi t to coordinate the
entry of th e two codecs into D3 state.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/W
16 AD3
Power down semaphore for Audio. This bit exists in the
sus p end well and ma in tains context across power state s
(except G3). The bit has no hardware function. It is used b y
software in c onjunction with the MD3 bit to coo rdinate the
entry of th e two codecs into D3 state.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/W
15 R ead Comp le tion Status
(RCS)
Th is b it in d i cat e s th e sta tus of codec read completions.
0 = A cod e c re a d comp le te s n ormally.
1 = A cod e c re ad res ults in a time -out. The bit re mains set
until being cleared by software writing a “1” to the bit
location.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/WC
14 Bit 3 of slot 12 Display bit 3 of the most rece nt slot 12. RO
13 Bit 2 of slot 12 Display bit 2 of the most rece nt slot 12. RO
12 Bit 1 of slot 12 Display bit 1 of the most rece nt slot 12. RO
11 AC_SDIN1 Resume
Interrupt (S1RI)
This b it ind icate s that a resume eve nt occurred on
AC_SDIN[1].
0 = Clea re d by writing a ’1’ to this bit position.
1 = Resume ev ent occurred.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/WC
10 AC_SDIN0 Resume
Interrupt (S0RI)
This b it ind icate s that a resume eve nt occurred on
AC_SDIN[0].
0 = Clea re d by writing a ’1’ to this bit position.
1 = Resume ev ent occurred.
This b it is n ot a f fected by D3HOT to D0 Reset.
R/WC
9AC_SDIN1 Codec Ready
(S1CR)
R efl ec ts the state of the codec ready bit in AC_SDIN[1]. Bus
mas te rs ig n ore the co ndition of the cod ec re a dy b its, so
software must check this bit before starting the bus masters.
Once the codec is “ready, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
8AC_SDIN0 Codec Ready
(S0CR)
Refle c ts the state of the codec ready bit in A C _SDIN [0 ]. B us
mas te rs ig n ore the co ndition of the cod ec re a dy b its, so
software must check this bit before starting the bus masters.
Once the codec is “ready, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
RO
T abl e 52 6. GL O B _ ST A— Gl ob a l Sta tu s Re g is te r (S he e t 2 of 3)
Bits Name Description Access
Device: 29 Function: 5
I/O Address: MBA R + 40h Attribute: Read-Only, Read/Write, Read/Write Clear
Defau lt Value: 00300000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—14
Intel® 6300ESB I/O Controller Hub
DS November 2007
604 Order Number: 300641-004US
14.2.10 CAS—Codec Access Semaphore Register
Note: Reads across dWord boundaries are not supported.
7 M ic In Interrupt (MINT) This bit indicates that on e of th e Mic in cha n ne l in te rrupts
status bits h a s b een se t. When th e specific status b it is
cleared, this bit will be cleared. RO
6PCM Out Interrupt
(POINT) This bit indicate s th at on e of th e PC M ou t cha nne l in te rrupts
status bits h a s b een se t. When th e specific status b it is
cleared, this bit will be cleared. RO
5 PCM In Interrupt (PIINT) T his bit indicates that one of the PCM in channel interrupts
status bits h a s b een se t. When th e specific status b it is
cleared, this bit will be cleared. RO
4:3 Reserved Reserved. RO
2Modem Out Inte rrupt
(MOINT) This bit indica te s that one of the mod e m out cha nne l
interrupts status bits has bee n set. W he n the sp ecif ic stat us
bit i s cleared, this bit will be cleared. RO
1Modem In Interrupt
(MIINT) This bit indicates that one of the modem in channel interrupts
status bits h a s b een se t. When th e specific status b it is
cleared, this bit will be cleared. RO
0GPI Status Chang e
Inter rupt (G SC I)
This bit reflects the state of bit ’0’ in slot 12, an d is set
whenever bit ’0’ of slot 12 is set. This indicates that one of
the G PIs c hanged state, and that t he new val ues are av ailable
in slot 12. The bit is cleared by software writing a ‘1’ to this
bit location.
This bit is not affected by D3HOT to D0 Reset.
R/WC
Table 527. CAS—Codec Access Semaphore Register
Bits Name Description Access
7:1 Reserved Reserved.
0C odec Acce ss
Semaphore (CAS)
This bit is read by software to check whether a codec access
is c u rrently in p rogress.
0 = No access in progress.
1 = The act of re a d ing thi s regi ster se ts this b it to 1. The
driver that read this bit may then perform an I/O access.
Once the access is complete d, har dware a utomatica lly
clears thi s bit.
R/W
(special)
Table 526. GLOB_STA—Global Status Register (Sheet 3 of 3)
Bits Name Description Access
Device: 29 Function: 5
I/O Address: MBAR + 40h Attribute: Read-Only, Read/Write, Re ad/Write Clear
Defau lt Value: 00300000h Size: 32-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
I/O Address: NABMBAR + 44h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 605
15—Intel® 6300ESB ICH
Multimedia Timer Registers 15
15.1 Memory Ma pp ed Registers
The timer registers are memory mapped in a non-indexed scheme. This allows the
processor to directly access each register without having to use an index register. The
timer register space is 1024 bytes. The registers are generally aligned on 64-bit
boundaries to simplify implementation with IA64 processors. There are four possible
memory address ranges beginning at
1) F ED0_0000h, 2) FED0_1000h, 3) FED0_2000h., 4) FED0_3000h. The choice of
address range will be selected by configuration bits in General Control register (offset
D0h) in Device 31, Function 0.
15.1.1 Be havioral Rules
1. Software must not attempt to read or write across register boundaries. For
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses
should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh , 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in unexpected behavior and may result in a
master abort. However, these accesses will not result in system hangs. 64-bit
accesses may only be to x0h and must not cross 64-bit boundaries.
2. Software should not write to read-only registers.
3. Reads or writes to unimplemented timers should not be attempted. Timers 3:31
are not implemented.
4. All registers are implemented in the Core W ell, and all bits are reset by PXPCIRST#.
5. Reads to reserved registers or bits will return a value of ‘0’.
6. Softw are mu st not attemp t l ocks to the me mory mappe d I/ O r ang es f or Mul ti media
Timers. When attempted, the lock is not honored, which means potential deadlock
conditions may occur.
Table 528. Memory-Mapped Registers (Sheet 1 of 2)
Offset Register Type
000-007h General Cap abilities and ID Read Only
008-00Fh Reserved
010-017h General Config R ead-Write
018-01Fh Reserved
020-027h G e ne ral Inte rrup t St atus Read/Write Clear
028-0EFh Reserved
0F0-0F7h Main Counter V alue Read/Write
0F8-0FFh Reserved
100-107h Timer 0 Co nfi g and Capa bi litie s Read/Write
108-10Fh Time r 0 Comparator Value Read/ Write
110-11Fh Reserved
120-127h Timer 1 Co nfi g and Capa bi litie s Read/Write
128-12Fh Time r 1 Comparator Value Read/ Write
Intel® 6300ESB ICH—15
Intel® 6300ESB I/O Controller Hub
DS November 2007
606 Order Number: 300641-004US
15.1.2 Offset 000-007h: General Capabilities and ID
Register
130-13Fh Reserved
14 0-147h Timer 2 Config an d Capab ilities Read/Write
148-14Fh Timer 2 Comparator Va lue Read/Write
150-15Fh Reserved
160-3FFh Reserved
Table 529. Offset 000-007h: General Capabilities and ID Register
Bits Name Description Access
63:3
2COUNTER_CLK_PER_CA
P
Main Coun ter Tick Perio d: Th is re a d -only field indicates the
peri od at wh ich t he cou nter in cre me nts in fem ptoseconds
(10^-15 seconds). This will return 0429B17F when read. This
indicates a period of 69841279 fs (69.841 279 ns).
RO
31:1
6VENDOR_ID_CAP This is a 16-b it value assigned to Inte l. The se bits will retu rn
8086h when re ad. RO
15 LEG_RT_CAP Legacy Rout Capable: Thi s bi t will re tu rn a ’1 ’ whe n re ad,
indicating that the Legacy Interrupt Rout option is supported. RO
1 4 Res e rved Reserv e d. This b it will re tu rn ’0’ whe n read.
13 COUNT_SIZE_CAP Counter Size: This bit will re tu rn a ’1’ when rea d , ind ica ting
that the counter is 64-b it wid e . RO
12:8 NUM_TIM_CAP Number of Timers: This indicates the number of timers in this
block. The value in th is f ie ld is 02h, in d icating tha t the re ar e
three time rs. RO
7:0 REV_ID This ind icates which revision of the function is implemen te d .
Default value will be 01h. RO
Table 528. Mem ory-Ma pped Registers (Sheet 2 of 2)
Offset Register Type
Offset: 000-007h Attribute: Read-Only
Defau lt Value: 0429 B17F 8086 A201 h Size: 64-bit
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15—Intel® 6300ESB ICH
15.1.3 Offset 010-017h: General Config Register
Table 530. Offset 010-017h: General Config Register
Bits Name Description Access
63:2 Reserved Reserved. These bits will r eturn ’0’ when read.
1LEG_RT_CNF
Legacy Rout: When the EN A BLE_CNF bit and the
LEG_R T _CNF bit are both set, the interrupts will be routed as
follows:
Timer 0 will be routed to IRQ0 in 8259 or IRQ2 in the I/O
APIC.
Timer 1 will be routed to IRQ8 in 8259 or IRQ8 in the I/O
APIC.
Tim er 2-n will b e route d as per the routing in the tim er n
config re gisters.
When the Legacy Rout bit is set, the individual routing
bits for Tim er s 0 and 1 (APIC) will h ave no imp a ct.
When the Legacy Rout bit is not set, the individual routing
bits for eac h of the timers are used.
This bit will default to ‘0’. BIOS may set it to ’1’ to enable
the l egac y routin g or ’0’ to disab le the legacy rou ti n g.
R/W
0ENABLE_CNF: Overall
Enable
This b it must be set to e na b le any of the tim er s to g en erate
interrupts. When this bit is ‘0’, the main counter will halt (will
not inc re men t) an d no in te rrupts will be cau sed by a ny of
these timers. For level-tri gge re d inte rrup ts, if an interrupt is
pend ing when the ENABLE_CNF bi t is changed from ’1’ to ‘0’,
the inte rrupt statu s ind ica tions in the various Txx_IN T_STS
bits wi ll not be cleared. Software must write to the
Txx_INT_STS bits to clear the inte rrupts.
NOTE: This bit will default to ‘0. BIOS may set it to ’1’ or ‘0’.
R/W
Offset: 010-017h Attribute: Read/Write
Defau lt Value: 00 00 0000 0000 0000h Size: 64-bit
Intel® 6300ESB ICH—15
Intel® 6300ESB I/O Controller Hub
DS November 2007
608 Order Number: 300641-004US
15 . 1 . 4 Offset 020-027h: Genera l Int er rupt Status
Register
Table 531. Offset 020-027h: General Interrupt Status R egister
Bits Name Description Access
63:3 Reserved Reserved. These bits will return ’0’ when read.
2T02_INT_STS: Timer 2
Interrupt A ctive Same functionality as Timer 0. R/W
1T01_INT_STS: Timer 1
Interrupt A ctive Same functionality as Timer 0. R/W
0T00_INT_STS: Timer 0
Interrupt A ctive
T h e fu nct ionalit y of t his bit dep end s on wh e ther t h e e d g e or
level-tr igge re d mode is used fo r this timer:
When set to level-triggered mode: This bit defa ul ts t o ‘0’.
This bit will be set by hardware when the corresponding timer
interrupt is ac tive. Onc e the bit is set, it may be cleare d by
software writing a ’1’ to the same bit position. Writes of ’0’ to
this bit will have no effec t. For examp le , if the bit is already
set, a write of ’0’ will not cl ear th e bit.
When set to edge-triggered mode: This bit should be
ignored by software. Software should always write ’0’ to this
bit.
NOTE: Def a ults to ‘0’. In e d ge-triggered mode , this b it will
always read as ’0’ and writes will have no effect.
R/W
Offset: 020-027h Attribute: Read/Write
Defau lt Value: 0000 0000 0000 0000h Size: 64-bit
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15.1.5 Offset 0F0 - 0f7h: Main Counter Value
15.1 .6 T i mer n Config and Capabilities
Note: The letter n may be 0, 1, or 2, referring to Timer 0, 1 or 2.
Table 532. Offset 0F0 - 0f7h: Main Counter Value
Bits Name Description Access
63:0 COUNTER_VAL[63:0]
Reads return the current value of the counter. Writes load the
new value to the counter.
NOTES:
1.Software can access the various bytes in this register
using 32-bi t or 64-bit acc esses. 32-bi t accesse s can be
done to offs et 0F0h or 0F4h. 64-bit acces ses can be do ne
to 0F0h . 32-b it acc esse s m u st not be done star ting at:
0F1h , 0F2h, 0F3h, 0F5h, 0F6h , or 0F7h.
2 . Writes to th is re g iste r should only be d on e while th e
co un te r is ha lte d .
3 . Reads to this register re turn the current value of the main
counter.
4 . 32- bit counte rs will always ret urn ’0’ for the upp e r 32 bi ts
of this reg ister.
5. If 32-b it softwa re atte mpts to read a 64-bit co unte r, it
should firs t halt the counter. Since this will delay the
interrupts for a ll of the tim e rs, th is should b e done only if
the consequences are under stood. It is strongly
reco mmended that 32-b it sof tware only operate the tim e r
in 32-bit mode.
6. Reads to thi s regi ster are monotonic. No two cons e cutive
read s will re tu rn the same value. The se cond of two rea d s
will always return a larger value (unless the timer has
rolled ov er to ‘0’).
R/W
Offset: 0F0-0f7h Attribute: Read/Write
Defau lt Value: N/A Size: 64-bit
Intel® 6300ESB ICH—15
Intel® 6300ESB I/O Controller Hub
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610 Order Number: 300641-004US
Table 533. Timer n Config and Capabilities (Sheet 1 of 3)
Bits Name Description Access
64:5
6Reserved Reserved. These b its will return ’0’ when re ad.
63:3
2
TIMERn_INT_ROUT_CAP
:
TIMERn_INT_ROUT[31:
0]_CAP
This 32-b it re ad-only field ind ica tes which interrupts in th e I/
O (x) APIC this time r’s interrupt may be routed to. Th is is
used in conjunction with the TIMERn_INT_ROUT_CNF field.
Each bit in this field corresponds to a particular interrupt. For
example , when this timer’s interrup t ma y be map ped to
interrupts 16, 18, 20, 22, or 24, bits 16, 18, 20, 22, and 24 in
this field will b e s et to ‘1’. All othe r b its will be ‘ 0’.
Intel® 6300ESB ICH and Timer 0, 1 Specific: Bits 20, 21, 22,
and 23 in this f iel d (corre sp onding to bits 52 , 5 3, 54, and 55
in this reg ister) will have a value of ‘1’. All oth e r bit s will b e
‘0’. Writes will h ave n o e ffe ct.
Intel® 6300ESB ICH and Time r 2 S pecific: Bits 11, 20, 21,
22, and 23 in this field (corre spond ing to bit s 43, 52, 53, 54,
and 55 in this re g iste r) will have a value of ‘1’. All other bits
will be ‘0. W rites will ha ve no effect. When IRQ 11 is used for
MMT#2, sof tware should ensure IRQ11 is not shared with any
other devices to ensure the proper operation of MMT#2.
31:1
6Reserved Reserved. Thes e bits will re turn ’ 0’ whe n re a d .
15 TIMERn_FSB_INT_DEL_
CAP: FSB Interrupt
Delivery
(where n is the time r number: 00 to 31)
If this re ad- o nly bit is 1, then the ha rd wa re supports a dire ct
processor si de b u s d elivery of thi s time r’s interr u pt .
NOTE: This bit will always read as 0, since the Intel ®
6300ES B ICH Multimedia Timer implementation does
not support the direct FSB interrupt delivery.
14 TIMERn_FSB_EN_CNF
(where n is the time r number: 00 to 31).
If the TIMERn_FS B _INT_DEL_CAP bit is set f or this time r,
then the software can set the TIMERn_FSB_EN _CN F b it to
forc e the i nterrupts to be delive red directl y as FSB messag es,
r ather than using the I/O (x ) APIC. In this case, the
TIMER n _IN T_ROUT_CNF f ie ld in th is re g iste r will be ignored.
The TIM ERn _FS B _ROUT register w ill be used in ste ad .
Offset: Timer 0: 100-107h ,
Timer 1: 120-127h ,
Timer 2: 140-147h Attribute: Read/Write
Defau lt Value: N/A Size: 64-bit
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15—Intel® 6300ESB ICH
13:9 TIMERn_INT_ROUT_CNF
Interrupt Rout: This 5-b it field indicates the routing f or the
interrupt to the I/O (x) APIC. A maximum v alue of 32
interrupts is supported; default is 00h. Software writes to this
field to sele ct wh ich i nte rrup t in the I/O (x ) w ill b e us ed for
this timer’s interrupt. When the value is not supported by this
particular tim er, th e value read back will not match what is
writte n . The sof tware must only write valid value s.
NOTES:
1. When the Legacy Rout bit is set, Timers 0 and 1 will have
a differ ent routi ng, and this bi t field h as no effect for thos e
two timers.
2.Timer 0,1 Specific: Software is responsib le to make sure it
programs a valid value (20, 21, 22, or 23) f or this f ield .
The I n t e l® 6300ESB ICH logic does not check the validity
of the value written.
3 . Time r 2 Specific: S oftware is resp onsible to m ake su re it
programs a valid value (11, 20, 21, 2 2, or 23) f or this
field. The Intel ® 63 00ESB ICH logic does not check the
validity of the value wr itte n .
8 TIMERn_32MODE_CNF
Timer n 32-bit Mode: Softwa re ma y se t this bit to f orce a 64-
bit timer to behav e as a 32-bit timer. For Timer 0, this bit will
be read/write and default to ‘0. For Timers 1 and 2, this bit
will al ways rea d a s ’0’, and writes will have n o e ffect, since
these two timers are 32 bits.
7 Reserved Reserved. This b it will re tu rn ’0’ whe n read.
6 TIMERn_VAL_SET_CNF
Timer n Value Set: Software uses this bit only for Timer 0
when it has bee n set to periodic mode. By writing this bit to a
‘1’, the softwa re is then allowe d to d ire ctly set the time r’s
accumulator. Sof tw are does NOT have to write this bit back to
’0’; it automatic ally cle ars.
Software should not write a ’1’ to this bit position when the
time r is set to non-p e riodic mode .
NOTE: This bit will return ’0’ when read. W rite s will only have
an effect for Timer 0 when it is set to periodic mode.
Writes will ha ve no e ffe ct f or Timers 1 and 2.
5 TIMERn_SIZE_CAP
Ti mer n S ize: This r ead-o n l y field in dicate s the size of th e
timer.
V alue is ’1’ (64 bits) for Timer 0. Value is0’ (32 bits) for
Timers 1 and 2.
4 TIMERn_PER_INT_CAP
Periodic Interrupt Capable : W he n th is rea d -only bi t is ‘1’, the
hardware supports a periodic mode for this timer’s interrup t.
Time r 0 will support the period ic interrup t, so the b it will
always re a d as a ‘1’. Time rs 1 a nd 2 will n ot support pe riod ic
interrupts, so the b it will a lways read as ‘0’.
Table 533. Timer n Config and Capabilities (Sheet 2 of 3)
Bits Name Description Access
Offset: Timer 0: 100-107h ,
Timer 1: 120-127h ,
Timer 2: 140-147h Attribute: Read/Write
Defau lt Value: N/A Size: 64-bit
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612 Order Number: 300641-004US
3TIMERn_TYPE_CNF
Timer n Type:
For Time rs 1 an d 2, this bit wi ll always return ’0’ w he n rea d
and writes will have no impact.
For Timer 0, this bit is read/write, and may be used to enable
the timer to g e nerate a per iod ic inte rrupt. Writing a 1 to this
bit enables the timer to generate a periodic interrupt.
NOTE: For time r 0, this b it will be re a d /write , with default of
‘0’. For timers 1:2, this bit wi ll be read-only, with a
fixed val ue o f ‘0 .
2 TIMERn_INT_ENB_CNF
Timer n Interrupt Enable: This bit must be set to enable timer
n to cause an interrupt when it times out. When this bit is ‘0’,
the timer may still count and g enerate appropriate status bits
but will not ca use an inter ru p t. Def a ult value is ‘0 .
1 TIMERn_INT_TYPE_CNF
Time r Inte rru p t Typ e:
0 = The timer interrupt is edge trig gered. This means that an
e dge-typ e interru pt is gen er ated. When anothe r interr upt
occu rs, a nother edg e will be g e ne rated .
1 = The time r in terrupt is le vel triggered. This me a n s tha t a
level-tri gge re d in te rrup t is generated. The inte rrupt will
be held active until it is cleared by writing to the bit in the
General Inte rrupt Status Regis te r. Wh e n an othe r
interrup t occurs bef ore the in te rrup t is cle ared, the
interrup t will remain a ctive .
NOTE: The default value is ‘0’, edge-triggered. The interrupt
type is not expected to be changed dynamically. The
interrup t type for any time r sh ould be set bef ore an y
interrupts are generated by that timer. If the interrupt
type is changed dynamically, there will be some de lay
before the ne w type takes effec t. That dela y is not
known at this time. Supports edge and level triggered
modes f or all thre e timers.
0 Reserved Reserved. Th es e bits w ill re turn ’ 0’ wh e n re a d .
Table 533. Timer n Config and Capabilities (Sheet 3 of 3)
Bits Name Description Access
Offset: Timer 0: 100-107h ,
Timer 1: 120-127h ,
Timer 2: 140-147h Attribute: Read/Write
Defau lt Value: N/A Size: 64-bit
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15—Intel® 6300ESB ICH
15.1 .7 T i mer n Comparator Value
Table 534. Timer n Comparator Val ue
Bits Name Description Access
63:0
1. Reads to thi s regi ste r return the current value of the
comparator.
2. When Tim e rs 0,1, or 2 are config ured to non-per iodic
mode:
A. Writes to this regi ster load the value agains t which the
mai n counte r will be compared for this timer.
B. When the main counter equals the value last written to
this register, the corresponding interrupt will be generated
(wh en enable d ).
C. The value in this re gi ster does n ot c han ge bas ed o n t he
interrupt being generated.
3 . Whe n Timer 0 is configured to p er iod ic mode:
A. When t he main counter equals the value last written to
this register, the corresponding interrupt will be generated
(wh en enable d ).
B. After the main counter eq uals the value in this register,
the value in this re gister is incre a sed by the value last
writte n to the regis ter.
For example, if the value w ritten to the register is
00000123h, then:
1. An interrupt will be generated w hen the main counter
reac hes 00000123h.
2. The value in this re gister will be a dju ste d by the
hardware to 00000246h .
3. Anothe r interrup t will b e gene rated whe n the main
counter re aches 00000246h.
4. The value in this re gister will be a dju ste d by the
hardware to 00000369h .
C. As each p e riod ic interrup t occurs, the value in th is
registe r will increment. Wh e n th e inc re me nte d value is
greate r than the max imum value possible f or th is re g ister
(FFFFFFFFh for a 32-bit time r or FFFFFFFFFFFFFFFFh f or a
64- bit time r), the value will wra p ar ound th roug h 0. For
example, if the current value in a 32-bit timer is
FFFF 0000h and the last value written to this register is
200 00, the n a ft er the nex t inte rrup t the value will change
to 00010000h.
4. Default value for each timer is all ones for the bits that are
implemented. For example, a 32-b it timer will have a
default value of 00000000FFFFFFFFh. A 64-bit timer will
have a default value of FFFFFF FFFFFFFFFFh.
Offset: Timer 0: 108h – 10Fh,
Timer 1: 128h – 12Fh,
Timer 2: 148h – 14Fh Attribute: Read/Write
Defau lt Value: N/A Size: 64-bit
Intel® 6300ESB ICH—15
Intel® 6300ESB I/O Controller Hub
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614 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
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16—Intel® 6300ESB ICH
Watchdog Timer (WDT) (D29:F4)16
16.1 Product Fe atures
The Watchdog Timer (WDT) supports the following features and functions:
Selectable prescaler – approximately 1 MHz and approximately 1 KHz
33 MHz clock (30 ns clock ticks)
Multiple modes: WDT and free-running
Fr ee-r u nning mode:
O n e st ag e timer.
Toggles WDT_OUT# after programmable time.
—WDT Mode:
Two stag e ti mer:
1. Firs t st age generates IRQ an d SMI interrupt after programmabl e time.
2. Second stage dr ives WDT_OUT# low or inverts the previous value.
*Used only after first timeout occurs.
*St at us bit preserved in RTC well for pos s ible error det ec ti on and c orrec tion.
*Drives WDT_TOUT# when OUTPUT is enabl ed.
Timer ma y b e dis a bl ed (def au l t state) or lo ck ed (har d res et re qu i r ed to dis ab l e WD T)
WDT automat ic reloa d of prel oad value when WDT reload sequen ce is perform ed
Note: The WDT device (Dev 29:F4) cannot be hidden by using bit 12 of the D31:F0
FUNC_DIS Register. The WDT will always be present as a PCI device in PCI Config
Space.
Intel® 6300ESB ICH—16
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616 Order Number: 300641-004US
16.2 Prod uct Overview
The timer uses a 35-bit down-counter. The counter is loaded with the value from the
first Preload register. The timer is then enabled and starts counting down. The time at
whi ch th e WD T f irst st arts c ounti ng d own is call ed the fir st s ta ge. When t he ho st fail s to
reload the WDT before the 35-bit down-counter reaches zero, the WDT generates an
internal interrupt. After the interrupt is generated, the WDT loads the value from the
second Preload register into the WDT’s 35-bit down-counter and starts counting down.
The WDT is now in the second stage. When the host still fails to reload the WDT before
the second timeout, the WDT drives the WDT_TOUT# pin low and sets the timeout bit
(WDT_TIMEOUT). This bit indicates that the System has become unstable. The
WDT_TOUT# pin is held low until the system is reset or the WDT times out again
(depending on TOUT_CNF). The process of reloading the WDT involves the following
seq ue nc e of writ e s:
1. Write 80 to o ffset BAR + 0Ch.
2. Write 86 to o ffset BAR + 0Ch.
3. Write 1 to WDT_RELOAD in Reload Register.
The same process is used for setting the values in the preload registers. The only
difference exists in step 3. Instead of writing a ‘1’ to the WD T_RELOAD, write the
desired preload value into the corresponding Preload register. This value is not loaded
into the 35-bit down-counter until the next time the WDT reenters the stage. For
example, when Preload Value 2 is changed, it is not loaded into the 35-bit down-
counter until the next time the WDT enters the second stage.
Figure 29. WDT Block Diagram
PCI
Configuration
Registers
Reset/Inte r rup t C on tr ol Logic
Down
-
Counter
IRQ/SMI
(Internal)
WDT_TOUT#
(External)
PCI
Preload Value 1
P reload Value 2
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16.3 Signal Descriptions
The following signals are driven from the WDT.
16.4 Dev i ce 29: Func ti on 4 Configurati o n
Registers
16. 4. 1 Conf i gur a ti on Register s
Tab l e 53 5. WDT Int erfa c e
Signal Type Name and Description
WDT_TOUT#/
GPIO[32] O
Wa tc hdog Time r Timeout: Th e WDT_ TOUT# signa l i s drive n
low from the Intel® 6300ES B ICH to an e xternal pin. The
signal is d riven low when the main 35-b it d own -counter
reaches zero during the second stage. The WDT_TOUT_CNF bit
in the Conf iguratio n re gis te r d etermines if the outp u t is to
change fro m the previous state when anothe r timeout occurs,
or WDT_OUT# is drive n low un til the system is res e t or po we r
is cycle d .
Driven active to indicate the second stag e of the WDT has
overflowed . This signal will toggle states for eac h overf low in
perio dic mode. In non-periodic mode, this signal will go active
low and re ma in in this state unt il a system res et or power
cycle.
This sign al is mu x ed with GPIO[32].
WDT_INT
( Inte rn al on ly
signal) O
Interrupt: The WDT_INT# i s an i nternal si gnal that is used to
gen era te an in ter r upt w hen th e fir s t stage has b een all owed t o
reach zero. The WDT is ca p a ble of gene ra ting SCI, SM I, an d
IRQ (APIC 1, INT 10) based interrupts. Interrupts are not
generated when WDT_TOUT_CNF is set to change output after
ever y t imeout (See Configuration Register ). The WDT INT#
signal is an active low interrupt.
Table 536. Configuration Registers (Sheet 1 of 2)
Offset Register Default Type
00-01h Vendo r ID 8086h Read Only
02-03h Device ID 25ABh Read Only
04-05h Command Register (CO M ) 0000h Re ad/ Write
06-07h Device S tatus Regis te r (DS) 0280h Rea d/Write Cle ar
08h Revision ID Register (RID) See NOTE: Read Only
09h Programming Interface Regis te r (PI) 00h Read Only
0Ah Sub Class Code Register (S CC) 80h Read Only
0Bh Base Class Code Register (BCC) 08h Read Only
0Eh Header Ty p e Register (HEDT) 00h Read Only
10-13h B ase Address Register (BAR) 00000000h Read /Write
NOTE: Refer to the Intel® 6300ESB I/O Controller Hub S pecification Update for the most up- to-
date value of the Revision ID register.
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
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16.4.2 Memory Map ped Regist ers
16.4.3 Offset 00h: VID—Vendor Identification Register
14-2Bh Reserved 00h
2C- 2Dh Sub sy stem Vendor ID 00h Read/Write Once
2E-2F Subsystem ID 00h Read/Write Once
30-5F Reserved 00h
60-61h WDT Configuration 00h Read/Write
64-67h Reserved 0000h
68h WDT Lock Registe r 00h Read/Write
6C-F7 Reserved 00h
F8-FBh Manu facture r’s ID 00000F66h Read Only
FC-FFh Reserved 00h
Table 537. Memory Mapped Registers
Offset Register Default Type
Base + 00h Preload V alue 1 FFFFFh Read/Write
Base + 04h Preload V alue 2 FFFFFh Read/Write
Ba se + 08h G ener al Interr upt Status 00h Read/W ri t e/C lear
Base + 0Ch Reload R egister 0000h Write
Table 538. Offset 00h: VID—Vendor Identification Register
Bits Name Description Access
15:0 Vend or ID
Table 536. Configuration Registers (Sheet 2 of 2)
Offset Register Default Type
NOTE: Refer to the Intel® 6300ES B I/O Controller Hub Spe cif ication Upd a te for the m ost up- to -
date value of the Revision ID reg ister.
Device: 29 Function: 4
Offset: 00h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
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16.4.4 Offset 02h: DID—Device Identification Register
16.4 .5 Offset 04 - 05h : COM—Command Register
Table 539. Offset 02h: DID—Device Identification Register
Bits Name Description Access
15 :0 D evice I D
Table 540. Offse t 04 - 05h : COM—Com man d Register
Bits Name Description Access
15:1
0Reserved Reserved. NA
9 Fast Back-to-Back
Enable (FBE) Reserved as0’. RO
8 S ERR# Enab le Reserved as ‘0’. RO
7 Wait Cycle Control Res er ved as ‘0’. RO
6 Parity Error Response Reserv ed as ‘0. RO
5 VGA Palette Snoop Reserved as ‘0’. RO
4PMWE - Postable
Memory Write Enable Reserved as0. RO
3SCE - Special Cycle
Enable Reserved as ‘0. RO
2 BME - Bus Master Enable Reserved as ‘0’. RO
1MSE - Memory Space
Enable
This b it contr ols access to the WDT’s Memory Mapped
registers. If this bit is set, acces ses to the W DT’s Memory
Mapped registers are enabled. The Base Address register for
WDT sh ould be programmed before this bit is set.
R/W
0 IO SE - I/O Space Enable Reserved as ‘0’. RO
Device: 29 Function: 4
Offset: 02h Attribute: Read-Only
Defau lt Value: 25ABh Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: 04 - 05h Attribute: Read-Only
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
620 Order Number: 300641-004US
16.4.6 Offset 06h - 07h: DS—D evice Status Register
Table 541. Offset 06h - 07h: DS—Device Status Register
Bits Name Description Access
15 DPE - Detected Parity
Error Reserved as ‘0’. R O
14 SSE - Signale d Sys tem
Error Reserved as ‘0’. R O
13 RMA - Received Master
Abort Res erved as ‘0’. R O
12 RTA - Re ce iv ed Target
Abort Res erved as ‘0’. R O
11 STA - Signa l ed Target -
Abort Status
This bit is set when the function is targeted with a tr ansaction
that the Intel® 6300ESB ICH terminates with a target abort.
Software rese ts STA to ’0’ by writi ng a ’1’ to this bit loca tion. R/WC
10:9 DEVT - DEVSEL# Timing
Status
This 2 -bi t fie ld define s t he timi ng for D EVSEL # asse r tion.
These re ad only bits indicate Intel® 6300ESB ICH’s DEVSEL#
timing when performing a positive decode.
The I n t el® 6 300ES B ICH generates D EV SEL# with medium
time.
RO
8Data Parity Error
Detected Re se rv ed as ‘0’. RO
7Fast Back-to-B a ck
Capable Rese rv ed as ‘1 . R O
6UDF - Use r Defin a ble
Features Reserved as ‘0’. R O
5 66 MHz Capable Reserved as ‘0. RO
4:0 Reserved Reserved. RO
Device: 29 Function: 4
Offset: 06h - 07h Attribute: Read/Write Clear
Defau lt Value: 0280h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 621
16—Intel® 6300ESB ICH
16.4.7 Offset 08h: RID—Revision Identification Register
Note: Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-
to-date value of the Revision ID.
Table 542. Off set 08h: RID—Revision Identification Register
Bits Name Description Access
15 DPE - Detected Pa rity
Error Reserved as ‘0. RO
14 SSE - Signaled System
Error Reserved as ‘0. RO
13 RMA - Re ceived Master
Abort Reserved as0’. RO
12 RTA - Receiv ed Ta rg et
Abort Reserved as0’. RO
11 STA - Signaled Target-
Abort Status
This bit is set when the function is targeted with a transaction
that Intel ® 6300ESB ICH term inate s with a targe t ab ort.
Software re sets S TA to ’0’ by writing a ’1’ to this bit location. R/WC
10:9 DEVT - DEVSEL# Timing
Status
This two-bit field defines the timing for DEVSEL# assertion.
These read-only bits indicate the Intel® 6300ESB ICH ’s
DEVS EL# timing when per fo r ming a positi ve deco de.
The I n t e l® 6300ESB ICH generates DEVS E L# with me d ium
time.
RO
8Data Parity Error
Detected Reserved as ‘0. RO
7Fast Back - t o- Bac k
Capable Reserved as1’. RO
6UDF - User Def in a b le
Features Reserved as 0’. RO
5 66 MH z Capab le R ese rv ed as ‘0’. RO
4:0 Reserved Reserved. RO
Device: 29 Function: 4
Offset: 08h Attribute: Read-Only
Defau lt Value: See Note Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
622 Order Number: 300641-004US
16.4.8 Offset 09h: PI—Programming Interface Register
16.4.9 Offset 0Ah: SCC —Sub Class Code R egister
16.4.10 Offset 0Bh: BCC—Base Code C lass Register
16.4.11 Offset 0Eh: HEDT—Header Ty pe Register
Note: The Base Address Register points to several memory mapped registers for the
Watchdog Timer. It decodes the smallest possible region of 16 Bytes.
Table 543. Offset 09h: PI—Programming Interface Register
Bits Name Description Access
7:0 Pro gramming Interface
Table 544. Offset 0Ah: SCC—Sub Class Code Register
Bits Name Description Access
7:0 Sub Class Code
Table 545. Offset 0Bh: BCC—Base Code Class Register
Bits Name Description Access
7:0 Bas e Code Cl ass
Device: 29 Function: 4
Offset: 09h Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 80h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 08h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 623
16—Intel® 6300ESB ICH
16.4.12 Offset 10h: BAR—Base Address Register
16.4.13 Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID
Note: Software (BIOS) will write the value to this register. After that, the value may be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write.
Table 546. Offset 0Eh: HEDT—Header Type Register
Bits Name Description Access
7:0 H e a der Typ e
Table 547. Offset 10h: BAR—Base Address Register
Bits Name Description Access
31:4 Base Address These bi t s are used to det erm ine the size of the memory -
mapped re gi on bein g req ueste d. R/W
3Prefetchable
Hard-wire d to ‘0’, indicating that this range is not pre-
fetchable. RO
2:1 Type Hard-wire d to ‘00’, indicating that this range can be mapped
anywhere in 32-bit address space. RO
0RTE - Resource Typ e
Indicator Hard-wired to ‘0’, ind icating a request for memory space. RO
Device: 29 Function: 4
Offset: 0Eh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: 10h Attribute: Read-Write
Defau lt Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
624 Order Number: 300641-004US
16.4.14 Offset 2Eh - 2Fh: SID—Sub system ID
Note: Software (BIOS) will write the value to this register. After that, the value may be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write.
Table 548. Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID
Bits Name Description Access
31:4 Base Address These bits are used to determine the size of the memory-
mapped region being requested. R/W
3Prefetchable
Hard-wire d to ‘ 0’, indicating th at t his ra nge is not pre-
fetchable. RO
2:1 Type Hard-wired to ‘00, indicating that this range c an be mapped
anywh ere in 32-bit address space. RO
0RTE - Resource Type
Indicator Ha rd -wire d to ‘ 0’, indicating a requ e st f or me mory spa ce . RO
Table 549. Offset 2Eh - 2Fh: SID—Subsystem ID
Bits Name Description Access
15:0 Subsystem ID
Device: 29 Function: 4
Offset: 2Dh - 2Ch Attribute: Read, W rite Once
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: 2Eh-2Fh Attribute: Read, Write Once
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 625
16—Intel® 6300ESB ICH
16.4.15 Offset 60 - 61h: WDT Configuration Register
16.4.16 Off se t 68h: WDT Lock Regist er
Table 550. Offset 60 - 61h: WDT Configuration Register
Bits Name Description Access
15:6 Reserved Reserved. RO
5WDT _OU TPUT: Out p ut
Enable
This b it in d ica te s whe ther or not the WDT will tog g le th e
exte rnal W DT_TOUT# pin when the W DT times out.
0 = Enabled (Default)
1 = D isa b le d
This sig n al is mu xed with G P IO32.
R/W
4:3 Reserved Reserved. RO
2WDT_PRE_SEL:
Prescaler Select
The WDT provides two options for prescaling the main down-
counter. The preload values are loaded into the main down-
co un te r right justified. The prescaler a d justs the sta rting
point of the 35-b it d own counter.
0 = The 20-bit Preload Value is load ed into bits 34:15 of the
main down cou nte r. The re sulting timer clock is the PCI
Clock (33 MHz) divided by 215. The approximate clock
generated is 1 KHz, (Default)
1 = The 20-bit Preload Value is loaded into bits 24:5 of the
main down cou nte r. The re sulting timer clock is the PCI
Clock (33 MHz) divided by 25. The app rox ima te clock
generated is 1 MHz.
NOTE: Timeout value is determined by the preload value
multiplied by the clock period.
R/W
1:0 WDT_INT_TYPE
The WDT timer supports p rogrammable routing of interrupts.
The set of bits allows the user to choose the type of interrupt
desired when the WDT reached t he end of t he first stage
without being reset.
00 = IRQ (APIC 1, INT 10) (D efault)
01 = Reserved
10 = SMI
11 = Disable d
IRQ is Ac tive low, level trigge red
R/W
Device: 29 Function: 4
Offset: 60 - 61h Attribute: Read, Write
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
626 Order Number: 300641-004US
Table 551. Offset 68h: WDT Lock Register
Bits Name Description Access
7:3 Reserved Reserved. RO
2WDT_TOUT_CNF
Timeou t Conf iguration: Th is re g iste r is u se d to choose the
functionality of the timer.
0 = Watchdog Timer Mode: When enabled (i.e. , WDT_ENABLE
goes from ‘0’ to ‘1’) the timer will re load Pre load V alue 1
and start dec reme nting . (Default) Up on rea ching the
second stage time out, the WDT_TOUT# is d riv en lo w
once an d will n ot cha nge aga in u ntil Pow er is cyc le d or a
hard reset occurs.
1 = Fre e Runni ng Mod e : W DT_TOUT# w ill cha ng e fr om
previous state when the next timeout occurs. The timer
ig nores the firs t s tage. The timer only us es Pr eload Value
2. In this mode the timer is restarted whenever
WD T_ENABLE goes fr om a ’0’ to a 1. This means that the
timer will reload Preload V al ue 2 and start decrementing
every time it is e n ab le d.
In free running m od e it is not n ece ssar y to reload the timer
as it is done automatically every time the decrementer
reaches zero.
R/W
1WDT_ENABLE
The following bit enables or disables the WDT.
0 = Disabled (Default)
1 = Enabled
NOTE: This bit cannot be m odified if WDT_LOCK has been
set.
NOTE: In free-run ning mode, Preload Val ue 2 is reloaded i nto
the do wn-count er ev ery time WD T_EN ABLE goes f rom
‘0’ to ‘1’. In WDT mode, Pr eload Value 1 is reload ed
ever y tim e WDT _E NABLE goes from ‘0’ to ‘1’ or the
WDT _RELOAD bit is written using the proper sequence
of writes (see Register Unloc king Sequenc e ).
WARNING: Software should e n sure that a timeout is not
about to occur before disa b ling the time r. A relo a d sequ e nce
is suggested.
R/W
0WDT_LOCK
Setting this bit will lock the values of this register until a hard
reset occurs or power is cycled.
0 = Unloc ked (Def ault)
1 = Locked
This is a Write-Once bit. It cannot be change d un til e ithe r
powe r is cycled or a h a rd res e t occu rs.
R/WO
Device: 29 Function: 4
Offset: 68h Attribute: Read-Write/Write Once
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 627
16—Intel® 6300ESB ICH
16.4.17 Offset F8 - FBh: Manufacturer’s ID
16.4.18 Offset Base + 00h: Preload Value 1 Register
Preload Value 2 Register
Table 552. Offset F8 - FBh: Manufacturer’s ID
Bits Name Description Access
31:1
6Reserved Reserved. RO
15:8 Manufacturer 0Fh = Inte l RO
7:0 Process/Dot 66h RO
Table 553. Offset Base + 00h: Preload Value 1 Register
Bits Name Description Access
31:2
0Reserved Reserved. RO
19:0 Preload_Value_1 [19:0]
Use this regi s t er t o hold the pr el oad v a lu e for t he WD T Ti mer.
The Value in the Prel oa d Register is automatic a lly tr ansf er red
into the 35-bit down-counter every time the WDT enters the
firs t stage .
NOTE: The v al ue l oaded into t he pre load registe r needs t o be
one less than the intended period, as the timer makes
use of zero-based co unting (i.e., zero is counted as
part of the decrement).
Please refer to Section 16.5.2, “Register Unlocking Sequence”
for de ta ils on how to chang e the value of th is re g ister.
R/W
Device: 29 Function: 4
Offset: F8 - FBh Attribute: Read-Only
Defau lt Value: 00000F66h Size: 32-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: Base + 00h Attribute: Read-Write
Defau lt Value: FFFFFh Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
628 Order Number: 300641-004US
16.4.19 Offset Base + 04h: Preload Value 2 Register
Preload Value 2 Register
16.4.20 Offset Base + 08h: General Interrupt Status
Register
Preload Value 2 Register
Table 554. Offset Base + 04h: Preload Value 2 Register
Bits Name Description Access
31:2
0Reserved Reserved. RO
19:0 Preload_ Value_2 [19:0]
Us e th is regis ter t o h old t he pr elo ad value f or the WDT T i mer.
The Value in th e Prelo ad Register is autom at ical ly t ran s ferr ed
into the 35-bit down-counter every time the WDT enters the
second sta ge.
NOTE: The va lu e l oaded i n to th e pr el o ad r egis t er needs t o be
one less than the intended period, as the timer makes
use of zero-based counting (i.e., zero is counted as
part of the decrement).
Please refer to Section 16.5.2, “R egister Unlocking Sequence”
for detail s on how to change the value of this re g ister.
R/W
Table 555. Offset Base + 08h: General Inte rrupt Status Register
Bits Name Description Access
7:1 Reserved Reserved. RO
0Watchdog Timer
Interrupt Ac ti ve:
(1st Stage) T his b it is set whe n the f irst s ta ge of the 35-b it
down-counter reache s zer o. An interrupt will b e gen e rated if
WDT_INT_TYPE is configured to do so (See WDT
Config urat ion Registe r).
This is a stick y bit and is only cleared by writing a 1.
0 = No In te rrup t
1 = Inte rru p t A ctiv e
NOTE: This bit is not set in free-running mode .
RWC
Device: 29 Function: 4
Offset: Base + 04h Attribute: Read-Write
Defau lt Value: FFFFFh Size: 32-bit
Lockable: No Power Well: Core
Device: 29 Function: 4
Offset: Base + 08h Attribute: Read-Write Cle ar
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 629
16—Intel® 6300ESB ICH
16.4.21 Off set Base + 0Ch: Reload Register
16.5 Theo ry Of Opera tio n
16.5.1 RTC Well and WDT_TOUT# Functionality
The WDT_TIMEOUT bit is set to a ‘1’ when the WDT 35-bit down counter reaches zero
for the second time in a row. The WDT_TOUT# pin is then toggled LOW by the WDT
from the Intel® 6300ESB ICH. The board designer should attach the WDT_TOUT# to
the appropriate external signal. When WDT_TOUT_CNF is a ’1’ the WDT toggles
WDT_TOUT# again when the next timeout occurs. Otherwise, WDT_TOUT# is driven
low unt il the sys t em is re se t or p owe r is cy cl ed.
16.5.2 Register Unlocking Sequence
The register unlocking sequence is necessary whenever writing t o the RELOAD register
or either PRELOAD_VALUE registers. The host must write a sequence of two writes to
offset BAR + 0Ch before attempting to write to either the WDT_RELOAD and
WDT_TIMEOUT bits of the RELOAD register or the PRELOAD_VALUE registers. The first
writes are 80 and 86, in that order, to offset BAR + 0Ch. The next write will be to the
proper register (e.g., RELOAD, PRELOAD_VALUE_1, PRELOAD_VALUE_2)
Table 556. Offset Base + 0Ch: Reload Register
Bits Name Description Access
15:1
0Reserved Reserved. RO
9WDT_TIMEOUT
This bit resides in the RTC We ll a nd it s value is not lost if the
host resets the system. It is set to '1' if the host fails to reset
the WD T bef ore the 35-bi t Down-C ounter reac hes zero f or the
second t ime in a row. This bit is cleared by performing the
Register Unlocking Sequence followed by a '1' to this bit.
0 = Normal (Default).
1 = System has bec ome unstable.
NOTE: In free running mode t his bit is set every time the
down counter reaches zero.
R/W
8WDT_RELOAD
To pre vent a time out, the host must perform the Register
Unloc kin g Seq u ence f o llow ed b y a '1 ' t o thi s bit (See Regist er
Un lock in g Sequence ).
NOTE: Refe r to Registe r Unlocking S e que nce for details on
how to write to this bit.
R/W
7:0 Reserved Reserved. W
NOTE: The reload sequence is only necessary for the Rel oad register and Preload_Value registers and is not
used in Free Running mode.
Device: 29 Function: 4
Offset: Base + 0Ch Attribute: Read-Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—16
Intel® 6300ESB I/O Controller Hub
DS November 2007
630 Order Number: 300641-004US
The following is an example of how to prevent a timeout:
1. Write 80 to o ffset BAR + 0Ch.
2. Write 86 to o ffset BAR + 0Ch.
3. Write a ‘1’ to RELOAD [8] (WDT_RELOAD) of the Reload Register.
Note: Any subsequent writes require that this sequence be performed again.
16.5.3 Reload Sequence
To keep the timer from causing an interrupt or driving WDT TOUT#, the timer must be
updated periodically. Other timers refer to updating the timer as “kicking” the timer.
The frequency of updates required is dependent on the value of the Preload values. To
update the timer, the Register Unlocking Sequence must be performed followed by
writing a ‘1’ to bit 8 at offset BAR+ 0Ch within the watchdog timer memory mapped
space. This sequence of events is referred to as the “Reload Sequence”.
16.5.4 Low Power State
The Watchdog Timer does not operate when PCICLK is stopped.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 631
17—Intel® 6300ESB ICH
APIC1 Configuration Registers
(D29:F5) 17
APIC1s direct registers are assigned with base address FEC1xxxxH. To support legacy
device/driver on external PCI bus used with th e Intel ICHx, APIC1 has an al ternate
base address FEC0xxxxH. This means external PCI devices may write to IRQ pin
assertion register (either FEC0_0020H or FEC1_0020H) to generate interr upt from
APIC1. Devices on the primary PCI bus can write to IRQ Pin Assertion Register
FEC0_0020H to generate an APIC0 interrupt. Devices/drivers on the PCI-X segment
have write access only on the APIC1 IRQ Pin Assertion Register. Devices/drivers on the
PCI segment can access only APIC0 registers.
Sin ce the Intel ® 6300ESB ICH does not implement Hub Interface EOI special cy cle,
MCH will translate EOI special cycle to a memory write cycle to EOI register at address
FEC0_0040H and pass it to the Intel® 6300ESB ICH. This memory write cycle will be
passed to both APIC0 and APIC1 internally.
From CPU/MCH point of view, it should always use address FEC0xxxxH to access APIC0
registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not respond to
CPU/MCU’s access to address FEC0xxxxH other than the EOI cycle stated above.
APIC1 also includes an XAPIC_EN config bit. This bit must be set to enable the I/O (x)
APIC extension to the I/O APIC. For APIC1, this extension is always enabled.
17.1 APIC1 Configuration Registers (D29:F5)
Note: Registers that are not shown should be treated as Reserved. See “PCI Configuration
Map” on page 277 for details .
.
Table 557. APIC1 Configuration Map (D29:F5) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Type
00-03h VID_DID Ve nd or ID/ Dev ice ID 25A CH /8086h RO
04-05h APIC1CMD AP IC1 Command Register 0000h R/W
06-07h APIC1S TA APIC1 Device Status Registe r 0010h RO
08h RID Revisi on ID See Note 1 RO
09-0B h CC Class Cod e 0800 20h RO
0C-0 Fh HEADTYP H e ader Type 00000000h RO
2C-2F SS Su bsys te m Ide ntif ie rs 00000000h RW O
34h CAP Capabilitie s Po inte r 50h R O
3Ch ILINE Interrupt Line 00h R/W
3Dh IPIN Interrup t Pin 00 h RO
40-41h ABAR A lternate Base Address Register 8000h R/W
NOTES:
1. Refe r to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value o f the Revision ID Register.
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
632 Order Number: 300641-004US
17.1.1 Offset 00 - 03h: VID_DID—Ve ndor/ID Register
(APIC1—D29:F5)
17.1.2 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND
Register (APIC1—D29:F5)
44-47h MBAR Memory Base Register FEC1000 0h RO
50-51h X ID PCI-X Identi fier s 0007h RO
54-57h XSR PCI-X Status 000100ED h RO
Table 558. Offset 00 - 03h: VID_DID—Vendor/ID Register (APIC1—D29:F5)
Bits Name Description Access
15:0 Devic e ID Value This is a 1 6-b it value a ssig ne d to th e APIC1. DID = 25ACh
15:0 Vendor ID Value This is a 16-b it value a ssig ne d to In tel. In te l V ID = 8086h
Table 559. Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1
D29:F5) (Sheet 1 of 2)
Bits Name Description Access
15:9 Reserved Reserved.
8SERR_EN: SERR#
Enable
SERR# Enable c ontrols the enable for the DO_SERR special
cycle on the hu b interface.
0 = Dis able special cycle.
1 = Ena bl e s pecial cycle.
R/W
7 Reserved Reserved.
Table 557. APIC1 Configuration Map (D29:F5) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Ty pe
NOTES:
1. Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-date
value of the Revision ID Registe r.
Device: 29 Function: 5
Offset: 00 - 03h Attribute: Read-Only
Defau lt Value: 25ACh-8086h Size: 32-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 633
17—Intel® 6300ESB ICH
17.1 .3 Offset 06 - 07h: APIC1STA—APIC1 Device Status
(APIC1—D29:F5)
6PERE: Parity Err or
Re sp onse Enab le
0 = No action is taken when detecting a parity error.
1 = The Intel® 6300ESB ICH will take normal action when a
parity er ror is d e te cte d .
NOTE: D30FO offset F4h, bit #2 must be set to a ‘1’ AND
D28FO offset F4h, bit #2 must be set to a ‘1’ in order
for PERE to have any effec t.
R/W
5:3 Reserved Reserved.
2 BME: Bus Master Enable Controls the I/O APIC1’s ability to act as a master on Hub
Interf a ce wh e n forwarding p roce ssor side b us in te rrupt
messages. R/W
1MSE: M emory Sp ace
Enable Co ntrols the I/O APIC1s response a s a ta rg e t to me mory
ac ce sses t ha t a d d r e ss th e I / O A P I C1 . R/W
0 Reserved Reserved.
Table 560. Offset 06 - 07h: APIC1STA—APIC1 Device Status (APIC1—D29:F5)
Bits Name Description Access
15:1
1Reserved Reserved.
10:9 DEV_STS: DEVSEL#
Timing Status
00 = Fast Decode.
NOTE: These bits are set for fast decode ‘00’, b ut a true
de vi ce se lect doe s not e xist, so th ey h a ve n o e ff e ct. RO
8:6 Reserved Reserved.
566MHZ_CAP: 66 MHz
capable Hardwired to 1. Not 66 MHz capable. RO
4 Capa bi litie s List This bit is hardwir ed to ‘1’, indicating the pr ese nce of a valid
capabilities po in te r at offs et 34h .
3:0 Reserved Reserved.
Table 559. Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1
D29:F5) (Sheet 2 of 2)
Bits Name Description Access
Device: 29 Function: 5
Offset: 04-05h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 06 - 07h Attribute: Read-Only
Defau lt Value: 0010h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
634 Order Number: 300641-004US
17.1.4 Offset 08h: RID—Revision ID Register (APIC1—
D29:F5)
17.1.5 Offse t 09 - 0Bh: CC—Class Code Register (APIC1—
D29:F5)
Tab le 561 . O f fse t 08 h : RID— R ev i si on ID Reg is te r (AP I C1—D 29 :F 5)
Bits Name Description Access
7:0 Revis ion ID Value Refer to the Intel® 6300ESB I/O Controller Hub Spec if icat ion
Update for the mo st up -to-d ate value of the Revision ID
Register. RO
Table 562. Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5)
Bits Name Description Access
23:1
6BCC: Ba se Cla ss Code The valu e of 0 8h indicates th a t this is a gen e ric syste m
peripheral. RO
15:8 SCC: Sub Cla ss Code The valu e of 00h indicates that this generic per ipheral is an
interrup t controller. RO
7:0 PIF: Programming
Interface The value of 20 h indicates that this interrupt perip he ral is an
I/OxAPIC. RO
Device: 29 Function: 5
Offset: 08h Attribute: Read-Only
Defau lt Value: See bit descripti on Size: 8-bit
Device: 29 Function: 5
Offset: 09-0Bh Attribute: Read-Only
Defau lt Value: 080020h Size: 24-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 635
17—Intel® 6300ESB ICH
17.1.6 Offset 0C - 0Fh: HEADTYP—Header Type Register
(APIC1—D29:F5)
17.1.7 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers
(APIC1—D29:F5)
Note: This register is initialized to logic ‘0’ by the assertion of PXPCIRST#. This register may
be written only once after PXPCIRST# deassertion.
Table 563. Offset 0C - 0Fh: HEADTYP—Header Type Register (APIC1—D29:F5)
Bits Name Description Access
31:2
4Reserved Reserved.
23:1
6Header Type This ind icates that it is a type ‘00’ header (normal PCI device)
and that it is a single function device. RO
15:0 Reserved Reserved.
Table 564. Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers (APIC1—D29:F5)
Bits Name Description Access
31:1
6SSI D : Subs ys t em ID W r i te once re gister for subs ys t em ID . RWO
15:0 SSVI D: Subsystem
Vendor ID Writ e onc e regis te r fo r h old ing t he su bs yste m vendor ID. RWO
Device: 29 Function: 5
Offset: 0C - 0Fh Attribute: Read-Only
Defau lt Value: 00000000h Size: 32-bit
Device: 29 Function: 5
Offset: 2C - 2Fh Attribute: Read/Write Once
Defau lt Value: 0000000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
636 Order Number: 300641-004US
17.1.8 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer
(APIC1—D29:F5)
17.1.9 Offset 3Ch: ILINE—Interrupt Line (APIC1—
D29:F5)
17.1.10 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
Table 565. Offset 34h: CAP_PTR—APIC1 Capabilities Pointer (APIC1—D29:F5)
Bits Name Description Access
7:0 CA P: Capabilities Pointer This register points to the sta rting of fse t (50h) of the I/O
APIC1 cap a b ilitie s rang e. RO
Ta ble 566. Offset 3Ch: ILINE—Interrupt Line (APIC1—D29:F5)
Bits Name Description Access
17:0 ILINE: Interrupt Line This d ata is not used by the Intel® 6300ESB ICH. It is used as
a scratchpad re gi ste r to communicate to softwa re the
interrupt line that the interrupt pin is connected to. R/W
Table 567. Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
Bits Name Description Access
7:0 IPIN: Interrupt pin The value of 00h indicates that I/O APIC1 does not connect to
PIRQ#. RO
Device: 29 Function: 5
Offset: 34h Attribute: Read-Only
Defau lt Value: 50h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 637
17—Intel® 6300ESB ICH
17.1.11 Offset 40 - 41h: AB AR—APIC1 Alternate Base
Addre ss Register (APIC1 —D29: F 5)
Note: This register contains an alternate base address in the legacy APIC range. This range
may coexist with the BAR register ra nge. This range is needed for OSs that support the
APIC but do not yet support remapping the APIC anywhere in the 4 Gbyte address
space.
Note: On downstream writes, only ABAR + Offset 40h (EOI) is claimed. On upstream cycles,
only ABAR + offset 20h are claimed.
17.1.12 Offset 44 - 47h: MBAR—APIC1 Memory Base
Register (A PIC1—D29:F5)
Note: This register contains the APIC1 Base Address for the memory space.
Table 568. Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register
(APIC1—D29:F5)
Bits Name Description Access
15 EN: Enable When set, the range FECX_YZ00 to FECX_YZFF is enabled as
an alternate access method to th e IOxAPIC registers. Bits
‘XYZ’ are defined below. RO
14 BIE: Boot Interrupt
Enable
0 = Boot inte rrupt is enabled.
1 = Boot inte rrupt is disable d.
NOTE: For details on the Boot interrup t, see Section 5.7.3,
“Boot Interrupt”.
RW
13:1
2Reserved Reserved.
11:8 Base A ddress [19:16]
(XBAD)
The se bits dete rmine the high order bits of the I/O A PIC
address map. When a memory addr ess is recognized by the
Intel® 6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
the Intel® 6300ESB ICH will re spond to the cycle and access
the internal I/O APIC1.
7:4 Base Address [15:12]
(YBAD)
The se bits determine the low orde r bi ts of the I/O APIC
address map. When a memory addr ess is recognized by the
Intel® 6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
the Intel® 6300ESB ICH will re spond to the cycle and access
the internal I/O APIC1.
3:0 Base Address [11:8]
(ZBAD)
The se bits determine the low orde r bi ts of the I/O APIC
address map. When a memory addr ess is recognized by the
Intel® 6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
the Intel® 6300ESB ICH will re spond to the cycle and access
the internal I/O APIC1
Device: 29 Function: 5
Offset: 40-41h Attribute: Read/Write
Defau lt Value: 8000h Size: 16-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
638 Order Number: 300641-004US
Table 569. Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—
D29:F5)
Bits Name Description Access
31:1
2ADDR: Address These bits determine the base address of the I/O APIC1. RO
11:4 Reserved Reserved.
3 PF: Prefetchable Indicates that the BAR is not pre-fet chable. RO
2:1 LOC: Location '00' indicates that t he address may be located anywhere in
the 32-bit ad dr ess space . RO
0 SI: Space Indicator Indicates that the BAR is in memory space. RO
Device: 29 Function: 5
Offset: 44-47h Attribute: Read-Only
Defau lt Value: FEC10000h Size: 32-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 639
17—Intel® 6300ESB ICH
17.1.13 Offset 50 - 51h: XID—PCI-X Identifiers Register
(APIC1—D29:F5)
17.1.14 Offset 52h: XSR—PCI-X Status Register (APIC1
D29:F5)
Table 570. Offset 50 - 51h: XID—PCI-X Identifiers Register (APIC1—D29:F5)
Bits Name Description Access
15:8 XNPTR: Nex t Pointer Points to the nex t cap a bilitie s list poin te r (em p ty). RO
7:0 XCID: Capability ID Capabilities ID indicates PCI- X (07h). RO
Table 571. Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5)
Bits Name Description Access
31:2
1Reserved Reserved.
20 Devi ce Comp le x ity Hard wired to logic ’0’ to indica te that this is a simp le dev ice. RO
19 Unexpec ted Split
Completion
This device will n e ver se e a n u nexp e cte d split com p le tion , as
it never generates any master cycles besides posted writes
for MSI. RO
18 Split Comple tion
Discarded This devic e does not support Split Comp le tion . RO
17 133 MHz Capable Hardwir e d to logic ’0’ to in dica te this d e vice is not 133 MH z
capable. RO
16 6 4-b it Dev ice Hardwired to logic ’1’ to in dica te tha t this is a 64- bit device . RO
15:8 Bus Number Indicate s th e bus numb er of the bu s segm ent for t his devi c e.
This value will match the pr ima ry b u s nu mb e r f ie ld from th e
attached bridge. RO
7:3 Device Number Reflects the device number that has been hard-coded for the
devi ce . This nu mb e r will be 1Dh (29) for APIC1. RO
2:0 Function Number Reflects the function number for the d evic e. RO
Device: 29 Function: 5
Offset: 50-51h Attribute: Read-Only
Defau lt Value: 0007h Size: 16-bit
Lockable: No Power Well: Core
Device: 29 Function: 5
Offset: 52h Attribute: Read-Only
Defau lt Value: 000300EDh Size: 32-bit
Lockable: No Power Well: Core
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
640 Order Number: 300641-004US
17.2 Advance d In terrup t Co ntroller (A P IC)
There are two APICs in the Intel® 6300ESB ICH: APIC0 and APIC1 (in device 29,
function 5). APIC0’s direct registers are assigned with base address FEC0xxxxH;
howeve r, no external PCI device may write to these registers. APIC 1s direct registers
are assigned with base address FEC1xxxxH. To support legacy device/ drivers on
external PCI bus used with the Intel ICHx, APIC1 has an alternate base address,
FEC0xxxxH. This means external PCI devices may write to IRQ pin assertion register
(either FEC0_0020H or FEC1_0020H) to generate interrupt from APIC1.
APIC0 also includes an XAPIC_EN config bit. This bit must be se t to enable the I/O (x)
APIC extension to the I/O APIC. For APIC1, this extension is always enabled.
17.2.1 AP IC1 Direct Register Map
The APIC is accessed through an indirect addressing scheme. Two registers are visible
by software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The registers are shown in Table 572.
Table 573 lists the registers which may be accessed within the APIC through the Index
Register. When accessing these registers, accesses must be done a DWORD at a time.
For example, software should never access byte 2 from the Data register before
accessing bytes 0 and 1. The hardware will not attempt to recover from a bad
programming model in this case.
17.2.2 IND—Index Register
Note: The Index Register will select which APIC indirect register to be manipulated by
software. The selector v alues for the indirect registers ar e listed in Table 573. Sof tw are
will program this register to select the desired APIC internal register.
Ta ble 572. APIC1 Direct Registers
Address Register Size Type
FEC1_0000h Index Regis te r 8 bits R/W
FEC1_0010h Data Regi ster 32 bits R/W
FEC1_0020h IRQ Pin Assertion Register 3 2 bit s R/W
FEC1_0040h EOI Register 3 2 bits R/W
Table 573. APIC Indirect Registers
Index Register Size Type
00 ID 32 bits R/W
01 Ve rsion 3 2 bit s RO
02 Arbitration I D 32 bi ts RO
03 Boot Configuration 32 bits R/W
04-0F Reserved RO
10 -11 Redir ec t ion Table 0 64 bi ts R/W
12 - 13 Redirection Table 1 64 bits R/W
3E-3 F Redir ec ti on Table 23 64 bits R/W
40-FF Reserved RO
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 641
17—Intel® 6300ESB ICH
17.2.3 DAT—Data Regi ster
Note: Thi s is a 32-b it regi ster speci fy ing the data to be rea d or wri tten to t he regist er po inte d
to by the Index register. This register may only be accessed in DWORD quantities.
17.2 .4 IRQ PA—IRQ Pin Assertion Regist er
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number
of interrupt inputs in to the I/O APIC without increasing the number of dedicated input
pins. When a device that supports this interrupt assertion protocol requires interrupt
service, that device will issue a write to this register. Bits 4:0 written to this register
contain the IRQ number for this interrupt. The only valid v alues are 0-23. Bits 31:5 are
ignored. To provide for future expansion, peripherals should always write a value of 0
for Bits 31:5.
Note: Writes to this register are only allowed by the processor and by masters on the Intel®
630 0ES B ICH s PC I b us . W r it e s by dev i ce s o n PCI buse s a bo ve the Intel® 6 300ES B ICH
(e.g., a PCI segment on a P64H) are not supported.
Table 574. IND—In dex Register
Bits Name Description Access
7 :0 APIC In dex T his is a n 8-b it pointer into th e I/O APIC reg ister table. R/W
Tab l e 57 5. DAT— Da ta Re gis ter
Bits Name Description Access
7:0 APIC Data Th is is a 32-bit re g ister for the data to b e read or written to
the APIC indirect register pointed to by the Index register. R/W
Device: 29 Function: 5
Memory
Address: FEC0_0000h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 29 Function: 5
Memory
Address: FEC0_0010h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
642 Order Number: 300641-004US
17.2.5 EOIR—EOI Register
The EOI register is present to provide a mechanism to maintain the level-triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register and compare them with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entr y will be cle ared.
Note: When there are multiple I/O Redirection entries, assign the same vector for more than
one interrupt input. Each of those entries will have t he Remote_IRR bit reset to ‘0. The
interrupt that was premat urely reset will not be lost because if its input remained active
when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a
later time. Only bits 7:0 are actually used. Bits 31:8 are ignored.
Table 576. IRQPA—IRQ Pin Assertion Register
Bits Name Description Access
31:5 Reserved Reserved. To provide for future expansion, the processor
should always write a value of ’0’ to Bits 31:5.
4:0 IRQ Numb er Bits 4:0 written to this regist er contain the IRQ number for
this interrupt. The only valid value s are 0-23. WO
Device: 29 Function: 5
Memory
Address: FEC0_0020h Attribute: Write-Only
Defau lt Value: N/A Size: 32-bit
Table 577. EOIR—EOI Register
Bits Name Description Access
31:8 Reserved Reserved. To provide for future expansion, the processor
should always write a value of ’0’ to Bits 31:8.
7:0 End of In te rrup t (E OI) Vector to be compared with vector field in the I/O redirection
table when an EOI is issued. WO
Device: 29 Function: 5
Memory
Address: FEC0_0040h Attribute: Write-Only
Defau lt Value: N/A Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 643
17—Intel® 6300ESB ICH
17.2.6 Offset 00h: ID—Identification Register
Note: The APIC ID serves as a physical name of the APIC1. This register is reset to ‘0’ on
power-up reset.
17.2 .7 Offset 01h: V ER—Version Regi ster
Note: Each I/O APIC contains a hardwired Version Register that identifies different
implementations of APIC and their versions. The maximum redirection entry
information also is in this register to let software know how many interrupts are
supported by this APIC.
Table 578. Offset 00h: ID—Identification Register
Bits Name Description Access
31:2
8Reserved Reserved.
27:2
4APIC ID Software must program this value before using the APIC. R/W
23:0 Reserved Reserved.
T abl e 57 9. O f fse t 01h : VE R— V e rsio n Reg is te r
Bits Name Description Access
31:2
4Reserved Reserved.
23:1
6Maximum Re d irec tion
Entries
This is the e ntry numb e r (0 b ei ng the lowest entry) of the
highest en try in the re d irection table. It is equal to the
num ber of inte rrupt input p in s minus one and is in the range
0 through 239. In the Intel® 6300ESB ICH, this field is
hardwired to 17h to indicate 24 inte rrup ts.
RO
15 PRQ T his b it is set to ’1’ to indicate that this version of the I/O
APIC implements the IRQ Assertion register and allows PCI
devi ces to write to it to cause interrup ts. RO
14:8 Reserved Reserved.
7:0 Version This is a version number th a t id e ntif ie s th e imp le mentation
versi o n. The vers i on num ber assi gn ed to the Int el ® 6300ESB
ICH f or the I/O (x ) APIC is 20h. RO
Device: 29 Function: 5
Offset: 00h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Device: 29 Function: 5
Offset: 01h Attribute: Read-Only
Defau lt Value: 00178020h Size: 32-bit
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
644 Order Number: 300641-004US
17.2.8 Offset 03h: BOO T_CONFIG—Boot Configuration
Register
Note: This register is used to control the interrupt delivery mechanism for the APIC.
17.2.9 Red irection Table
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
Note: The APIC will respond to an edge-triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC bus unit that the interrupt message was sent
over t he APIC bus. Only then will the I/O APIC be able to recognize a new edge on that
interrupt pin. That new edge will only result in a new invocation of the handler if its
acceptance by the destination APIC causes the Interrupt Request Register bit to go
from ‘0’ to ‘1. (i.e., if the interrupt was not already pending at the destination.)
Tabl e 580. Offset 03h: BOOT_CONFIG—Boot Configuration Register
Bits Name Description Access
31:1 Reserved Reserved.
0 DT: Delivery Type H ard wire to 1. In te rrupt deliver y m ec ha nism is always a
Proc es sor Sys te m B u s me ssage . RO
Device: 29 Function: 5
Offset: 03h Attribute: Read-Only
Defau lt Value: 00000001h Size: 32-bit
Table 581. Redirection Table (Sheet 1 of 3)
Bits Name Description Access
63:5
6Destination
When bit 11 of this entr y is 0 [Physica l], b its [59:56] specify
an APIC ID. In this case, bits 63: 59 should be programme d
by software to 0. When bit 11 of this entry is ’1 [Logical], bits
[63:56] spe cif y the log i cal destination ad dress of a se t of
processors.
R/W
55:4
8Extended Destination ID
(EDID) These bits are only sent to a local APIC when in Pr ocessor
System Bus mode. They become bits [11:4] of the address.
47:1
8Reserved Reserv e d. Softwa re should progra m the se b its to 0.
17 Disable Flushi ng
(DFLSH)
This bit is maintained f or any potential software compatibility ,
but the Intel® 6300ESB ICH pe rf orms no flushing action ,
regardless of the setting of this bi t.
Device: 29 Function: 5
Offset: 10h-11h (v ector 0)
through
3E-3Fh (vector 23) Attribute: Read/Write
Defau lt Value: B it 16-1, Bits[15:12]=0.
All other bits undefined Size: 64 bits eac h, accessed as two 32 bit
q
uantities
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 645
17—Intel® 6300ESB ICH
16 Mask
0 = Not masked: An ed ge or level on this interrupt pin results
in the deliv e ry of the inte rrupt to the de stina tion.
1 = Masked: Inter rup ts are not del ivered nor held pending .
Setting this b it aft er the inter rup t is accep te d by a local
APIC ha s no e f fect o n th at in te rrupt. This behavior is
identical to the device withdrawing the inte rrupt before it
is posted to the proce ssor. It is sof tware ' s re sponsibility
to deal with the case whe re the mask b it is set af te r the
inter rupt message ha s been accepted by a local APIC unit
but before the interrupt is dispens ed to the p rocessor.
R/W
15 Trigger Mode
This fiel d i ndi c at es th e type of sign al on the i n ter r u pt pi n t h at
trigge rs an inte rrupt.
0 = Edge triggered.
1 = Level triggered.
R/W
14 Re mote IRR
This b it is u se d fo r leve l-triggered in te rrupts in Fixed or
Lowest Priority Delivery Modes only; its meaning is undefined
for ed ge trig g e re d in te rrup ts. For le vel-triggered in te rrup ts,
this bit is se t if the I/O APIC successfully sends the level
interrupt mess age. R emote IRR bit is reset when an EOI
message is received that matches the interrupt vector in this
entry. This bi t is never set for S M I, NM I, INIT, or ExtIN T
deliver y modes.
R/W
13 Interrupt Input Pin
Polarity
This bit specifie s th e po la rity of each interrup t sig n a l
connected to the interrupt p ins.
0 = Activ e high.
1 = A ctiv e low.
R/W
12 D e livery Status
This f ie ld c o nta ins the curre nt status of the de livery of th is
interr up t. Writes to this bit have no effec t.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, b ut deliv ery is held
up due to the A PIC bus being busy or th e ina b ility of the
receiving APIC unit to accept the interrupt at this time.
RO
11 De stina tion Mode
This fie ld de te rmines the interp re ta tion of the Destination
field.
0 = Phy sical. Destination APIC ID is identified by bits [59:56].
1 = Logical. Destinations are identified by matching bit
[63: 56] with the Logical Des tin ation in the Destin ation
Format Register and L ogi ca l Destination Register in e a ch
Lo c a l APIC .
R/W
T abl e 58 1. Re d ire ct io n Table (Sh eet 2 of 3)
Bits Name Description Access
Device: 29 Function: 5
Offset: 10h-11h (v ector 0)
through
3E-3Fh (vector 23) Attribute: Read/Write
Defau lt Value: Bit 16-1, Bits[15:12]=0.
All
ot
h
e
r
b
i
ts
u
n
de
fin
ed
Size: 64 bits eac h, accessed as two 32 bit
qua
n
t
i
t
i
es
Intel® 6300ESB ICH—17
Intel® 6300ESB I/O Controller Hub
DS November 2007
646 Order Number: 300641-004US
10:8 De livery Mode
This field sp e cif ie s h ow the APICs l iste d in t he destination
field should act upon reception of this signal. Certain D elivery
Modes will only operate as intended when used in conjunction
with a specific trigger mode. These encodings are listed in the
note below:
R/W
7:0 Vector This field contains the interrupt vector for this inte rrup t.
Values range between 10h and F Eh. R/W
NOTE: Delivery Mode encoding:
0 00 = Fixed . Deliver the sign al on the IN TR signal of all proce ssor core s listed in the des tin ation. Trig g e r M od e
c an be edge o r l ev el .
001 = Lowest Priority. Deliv er the signal on the INTR signal of the processor core that is executing at the lowest
priority among all th e pr oce ssors liste d in the spe cified dest ina tion. Trig g er M ode can be edge or le vel.
010 = SMI. This delivery mode is not supported.
011 = Reserv e d.
1 00 = NM I. This deliv e ry mod e is not su p p orte d .
101 = IN IT. This d e livery mode is not sup po rte d.
110 = Reserv e d
111 = ExtINT. Deliver the signal to the INTR signal of all proce ssor cores listed in the destination as an interrupt
that orig inate d in an externally connected 8259A compatible interrup t contr olle r. The INTA cycle that
corre sponds to this ExtIN T de livery will be routed to the exte rnal controlle r that is e x pected to supply the
vector. Requires the interrupt to be prog rammed a s edge trig g er ed. T he Remote IRR bit is never set if
programmed for ExtINT level -trig gered opera tion; a s a re su lt a continuous stream o f interrupts will b e
generated as long as the INTR input is asserted.
Table 581. Redirection Table (Sheet 3 of 3)
Bits Name Description Access
Device: 29 Function: 5
Offset: 10h-11h (v ector 0)
through
3E-3Fh (vector 23) Attribute: Read/Write
Defau lt Value: B it 16-1, Bits[15:12]=0.
All
ot
h
e
r
b
i
ts
u
n
de
fin
ed
Size: 64 bits eac h, accessed as two 32 bit
qua
n
t
i
t
i
es
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 647
18—Intel® 6300ESB ICH
PCI-X Overview (D28:F0) 18
Note: Since the Intel ® 6300ESB ICH supports a PCI interface and a PCI-X interface, the
notat ion PCI -X wi ll be used to refe r t o t he P CI - X interfa ce. Since the PCI -X i nterfa ce c an
support the PCI-X protocol as well as the PCI protocol, the PCI-X terminology is
intended to refer to the interface being described and not to the protocol.
18.1 I/O Wind ow Addressing
This section describes the I/O window that may be set up in the bridge. Refer to
Section 18.3, “VGA Addressing” to see how I/O cycles in the VGA range are handled.
The register bits listed below also modify the response by the Intel® 6300ES B ICH to I/
O transa ct io n s:
I/O Base and Limit Registers
I/O Enable bit in the Command Register
Master enable bit in the Command Register
Enable 1K granularity in the Intel® 6300ESB ICH Configuration Register
To enable outbound I/O transactions, the I/O enable bit must be set in the command
regis ter in the Inte l® 6300ES B ICH config ur ati on spac e (bi t ’0’ at off set 04-0 5h) . When
the I/O ena ble bi t is not set, al l I/O transac tions initi ated on the Hub Inte rface recei ve a
master abort completion. No inbound I/O transactions may cross the bridge and are
therefore master aborted.
The Intel® 6300ESB ICH implements one set of I/O base and limit address registers in
configuration space that define an I/O address range for the bridge. Hub interface I/O
transaction s with addresses that fall inside the range defined by the I/O base and limit
registers are forwarded to PCI-X, and PCI-X I/O transactions with addresses that fall
outside this range are master aborted.
Setting the base address to a value greater than that of the limit address turns off the
I/O range. When the I/O range is turned off, no I/O transactions are forwarded to PCI
even when the I/O enable bit is set. The I/O range has a minimum granularity of 4
Kbytes and is aligned on a 4 Kbyte boundary. The maximum I/O range is 64 Kbytes.
This range may be lowered to 1K granularity by setting the EN1K bit in the Intel®
630 0ESB ICH Configuration register at offset 40h.
The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit
field at address 30h. The top four bits of the 8-bit field define bits [15:12] of the I/O
base address. The bottom four bits read only as 0h to indicate that the Intel® 6300ESB
ICH supp or ts 16- bit I/O ad dre ss i ng. Bi ts [ 11: 0 ] of th e ba se add res s ar e as sum e d to be
’0’, which naturally aligns the base address to a 4 Kbyte boundary. The I/O base upper
16 bits register at offset 30h is reserved. After chip reset, the value of the I/O base
ad dres s is in itial ize d to 0000 h.
The I/O limit register consists of an 8-bit field at offset 1Dh and a 16-bit field at offset
32h . The to p four bits of the 8-bit field define bits [15:12] of the I/O limit address. The
bottom four bits read only as 0h to indicate that 16-bit I/O addressing is supported.
Bits [11:0 ] of the li mit a d dres s ar e ass umed t o b e FFF h, whi c h naturally ali gns the l imi t
addre ss to the to p of a 4 Kbyte I/O add ress bloc k. Th e 16 bi ts containe d in t he I/ O l imi t
upper 16 bits register at offset 32h are reserved. After chip reset, the value of the I/O
limit address is reset to 0FFFh.
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
648 Order Number: 300641-004US
Note: W hen th e EN 1 K bit i s se t in the In t e l ® 6300ESB ICH Configuration register, the base
and limi t re gis ters are ch an ge d so that the top six bits of the 8-bit field defi ne bits
[15:10] of the I/O base/limit address, and the bottom two bits read only as 0h to
indicate support for 16-bit I/O addressing. Bits [9:0] are assumed to be ‘0’ for the base
register and ‘1’ for the limit register, which naturally aligns the address to a 1 Kbyte
boundary.
18.2 Memory Wi ndow Ad dressing
This section describes the memory windows that may be set up in the bridge. Refer to
Section 18.2.2, “Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit
Registers to see how memory cycles in the VGA range are handled.
Memory-mapped I/O Base and Limit registers
Prefetchable Memory Base and Limit registers
Prefetchable Memory Base and Limit upper 32 bits register
Mem ory Enable bit in the Comma n d regis ter
Master Enable bit in the Command register
To enable outbound memory transactions, the memory space enable bit in the
command register must be set (bit 1 of offset 04-05h). To enable inbound memory
transactions, the master enable bit in the command register must be set (bit 2 of offset
04-05h). The Intel® 6300ESB ICH does not prefet ch data from PCI devi ces. The Intel ®
6300ESB ICH supports 64 bits of addressing (DAC cycles) on both interfaces.
18.2.1 Memory Base and Limit Address Registers
The memory base address and memory limit address registers define an address ra nge
th a t th e In t el ® 6300ESB ICH uses to determine when to forward memory commands.
The Intel® 6300ESB I CH forw a rds a me mor y tra ns acti on f rom the Hub Int erfa ce to P CI-
X when the address falls within the range, and forwards it from PCI-X to the Hub
Interface when the address is outside the range, provided that they do not fall into the
prefetchable memory range (see Section 18.2.2, “Prefetchable Memory Base and Limit
Address Registers, Upper 32-Bit Registers). This memory range supports 32-bit
addressing only (addresses 4 Gbytes). It has a granularity and alignment of
1 Mbyte.
This range is defined by a 16-bit base address register at offset 20h in configuration
space and a 16-bit limit address register at offset 22h. The top 12 bits of each of these
registers correspond to bits [31:20] of the memory address. The low four bits are
hardwired to ‘0’. The low 20 bits of the base address are assumed to be all ‘0, which
results in a natural alignment to a 1 Mbyte boundary. The low 20 bits of the limit
address are assumed to be all ‘1 s, which results in an alignment to the top of a 1
Mbyte block.
Setting the base to a value greater than that of the limit turns off the memory range.
18.2.2 Prefetchable Memory Bas e and Limit Address
Regist ers, Upper 32-Bit Registers
The prefetchable memory base and address registers, along with their upper 32-bit
counterparts, define an additional address range that the Intel® 6300ESB ICH uses to
forward accesses. The Intel® 6300ESB ICH forwards a memory transaction from the
Hub Interface to PCI-X when the address falls within the range, and forwa rds
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18—Intel® 6300ESB ICH
transactions from PCI- X to the Hub Interface when the address is outside the range and
do n ot fall into the regular memory range (see S ecti on 18.2.1 , “ Memor y B ase and L imi t
Address Registers”). This memory range supports 64-bit addressing and has a
granularity and alignment of 1 Mbyte.
This lower 32 bits of the range are defined by a 16-bit base register at offset 24h in
configuration space and a 16-bit limit register at offset 26h. The top 12 bits of each of
th es e reg is ter s co rres po nd t o bit s [ 31:2 0] o f th e mem ory add res s. Th e l ow fo ur bi ts a re
hardwired to 1h , indicating 64-bit address support. The low 20 bits of the base address
are assumed to be all ‘0’s, which results in a natural alignment to a 1 Mbyte boundary.
The low 20 bits of the limit address are assumed to be all ‘1’s, which results in an
alignment to the top of a 1 Mbyte block.
The upper 32 bits of the range are defined by a 32-bit base register at offset 28h in
configuration space and a 32-bit limit register at offset 2Ch.
Setting the entire base (with upper 32 bits) to a value greater than that of the li mit
turns off the memory range.
18. 3 VGA Addr es sing
Wh en a VGA-co m pat ib le devi ce exis t s beh ind an Intel ® 6300ESB ICH bridge, th e VGA
ena ble b it in the bri dge contr o l regi st er is s et ( o ffset 3 at 3E-3F h). When se t, the I nte l®
6300ESB ICH forwards all transactions addressing the VGA frame buffer memory and
VGA I/O registers from the Hu b Interface to PCI-X, regardless of the values of the
Intel® 6300ESB ICH base and limit address registers. When set, the Intel® 6300ESB
ICH does not forward VGA frame buffer memory accesses to the Hub Interface
regardless of the values of the memory address ranges. However, the I/O enable and
mem o ry enabl e b it i n t h e c o m ma nd re g is t e r mu s t s t il l be se t . Wh en c l ea r ed , t h e I n t e l®
6300ESB ICH forwards transactions addressing the VGA frame buffer memory and VGA
I/O registers from the Hub Interface to PCI-X when the defined memory address
ranges enable forwarding. When cleared, accesses to the VGA frame buffer memory
are forwarded from PCI-X to the Hub Interface when the defined memory address
ranges enable forwarding. However, the master enable bit must still be set. The VGA I/
O addresses are never forwarded to the Hub Interface.
The VGA frame buffer consists of the following memory address range: 000A 0000h–
00B FFFFh.
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh.
These I/O addresses are aliased every 1 Kbyte throughout the first 64 Kbyte of I/O
space. This means that address bits [9:0] (3B0h-3BBh and 3C0h-3DFh) are decoded,
[15:10] are not decoded and may be any value, and address bits [31:16] must be all
‘0’s.
Intel® 6300ESB ICH—18
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18.4 Confi guratio n Addres si ng
Figure 30 shows how the Intel® 6300ESB ICH appears to configuration software.
As seen in Figure 30, the SM Bus controller does not appear to software. This function
does not have a space visible to software.
Configuration cycles on the Hub Interface have the same address format, with the bus
number, device number, function number and register number present in the address.
Refer to the Hub Interface specification for details of the address.
18.4.1 Type 0 Acce sses to the Intel® 6300ESB I CH
The configuration space of the bridge in the Intel® 6300ESB ICH is a ccessed by a Type
0 configuration transaction on the Hub Interface. The bridge configuration space (the
Intel® 6300ESB ICH) responds to a Type 0 configuration transaction when the following
conditions are met by the Hub Interface address:
The bus command is a configuration read or configuratio n write transaction.
Low 2 address bits AD[1:0] must be 00b.
The device number matc hes one of the Intel ® 6300E SB ICH devices (28).
18.4.2 Type 1 to Type 0 Transl ation
The Intel® 6300ESB ICH performs a Type 1 to Type 0 translation when the Type 1
transaction is generated on the Hub Interface and is intended for a device attached
directly to the secondary bus. The Intel® 6300ESB ICH must convert the configuration
command to a Type 0 format so that the secondary bus device may respond to it. This
Figure 30. Intel® 6300ESB I/O Controller Hub Appearance to Software
Table 582. Configuration Addressing
Function Hub Inte rface
ID PCI-X Bus PCI-X
Dev PCI-X
Func
PCI/PCI-XBus 6 0
(Hub
Interface) 28 h 0
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18—Intel® 6300ESB ICH
translation is done for cycles that originate on the Hub Interface and target PCI/PCI-X.
The Intel® 6300ESB ICH translates a Type 1 configuration transaction into a Type 0
transaction under the following conditions:
The bus command is a Configuration read or write transaction.
The low 2 address bits on AD [1:0] are 01b.
The bus number in address field AD [23:16] is equal to the value in the secondary
bus number register in the Intel® 6300ESB ICH configuration space.
The resulting Type 0 address to be driven on PCI-X is shown in Figure 31. Device
numbers are decoded to generate a single ‘1’ in address bits 31:16. When the device
number is greater than 16, then all bits are ‘0’.
18.4.3 Type 1 to Type 1 Forwarding
The Intel® 6300ESB ICH forwards a type 1 configuration cycle unchanged to the PCI-X
bus under the following conditions.
The bus command is a configuration read or write transaction.
The low two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate
bus num ber re gis ter.
Type 1 to type 1 forwarding is only done for cycles from the Hub Interface to PCI-X.
18.4.4 Type 1 to Special Cycle Forwarding
The Intel® 6300ESB ICH translates a type 1 configuration write transaction on the Hub
Interface into a special cycle on PCI-X, but does not translate a type 1 configuration
access on PCI-X to a special cycle on the Hub Interface. A cycle to be translated has the
following attributes in the address:
The low two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in
configuration space.
The bus command is a Configuration Write command.
The address and data are forwarded unchanged. Devices ignore the address and
decode only the bus command. The data phase contains the special cycle message. The
tr ansa ction do es a mas ter abort b ut resul ts in a norm al c omple ti on on the op posi te bu s
Figure 31. Type ‘1’ to Type ‘0’ Translation
Rese rved '0' Dev ID
Only one '1'
Fnc
Fnc0000
Register
Register
01
00
31 15 27101116 1 0
HL Address
PCI A ddress
Intel® 6300ESB ICH—18
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(normal completion sta tus on the Hub Inte rface, TRDY# on PCI-X). When more than
one data transfer is requested, the Intel® 6300ESB ICH responds with a target
disconnect operation during the first data phase.
18.5 Transaction Ordering
18.5.1 Comparison of Rules vs. a PCI – PCI Bridge
When a PCI segment is in PCI (PCI-X) mode, the Intel® 6300ESB ICH follows the
producer-consumer model of a PCI – PCI bridge. Table 583 is ta ke n fr om Appe ndi x E of
the PCI Specification, Rev 2.2 for PCI, and Section 8.4.4 of the PCI-X Addendum for
PCI-X. The shaded entries represent differences from that table, and an explanation of
the diff erence s:
18.5.2 Othe r Notes
Ordering relationships are established for the following classes of transactions crossing
th e In t e l ® 6300ESB ICH:
The Intel® 6300ESB ICH does no t combine sep ar ate write t rans ac tions into a si ngle
write transaction.
The Intel® 6300ESB ICH does not merge bytes on separate write transactions to
the same dWord addre ss.
The Intel® 6300ESB ICH does not collapse sequential write transactions to the
same address into a single write transaction – the PCI Local Bus Specification does
not permit this.
Table 583. Comparison of Rules vs. A PC I – PCI Bridge
Row Pass Col ? Posted
Write
Delayed
(Split)
Read
Request
Delayed
(Split)
Write
Request3
Delayed
(Split)
Read
Completion
Delayed
(Split)
Write
Completion
3
Posted Write No Yes Yes Yes Yes
Delayed (Split) Read
Request No Yes1No2Yes1No2No2Yes2Yes Yes2
Dela yed (Split)
Write Request No No2No2No3Yes2No3Yes2
Delayed (Split) Read
Completion No Yes Yes No2Yes2No2Yes2
Dela yed (Split)
Write Completion No2Yes Yes No2Yes2No2Yes2
NOTES:
1. Su b se q ue n t re q u e sts only (prefe tche s). All inbound initial requests are in ord e r.
2. In a brid ge, the se are allowed to be yes/no.
3. In a bridge, these are allowed to be yes/no. These particular entries are “No” because the
Intel® 6300ESB ICH does not accept inbound write requests that are not poste d (I/O writes,
config uration writes).
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18.6 Dev i ce 28 – Hub Interface to PC I-X Bridge
18. 6. 1 Conf i guration Spa ce Re gis ters
18.6.1.1 Register Summary
Table 584. Configuration Space Register Summary (Sheet 1 of 2)
Start End Symbol Full Name Default
00 03 ID Identifiers 25AE8086h
04 05 CMD Command 0000h
06 07 PSTS Primary Status 0030h
08 08 RID Revision ID See NOTE:
09 0B CC Class Cod e 0 60400h
0C 0C CLS Cache Line Size 00h
0D 0D PLT Primary Latency Timer 00h
0E 0E HTYPE Header Type 01h
18 1A BNU M B u s Numb e rs 000000h
1B 1B SLT S econd a ry Latency Timer 00h
1C 1D IOB L I/O Base and Lim it 0000h
1E 1F SSTS Secondary St atus 02A0h
20 23 M BL Memory Base and Limit 00000000h
24 27 PM B L Pref e tchab le M e mory Base and Limit 00010001h
28 2B PMBU32 Prefetchable Memory Base Upper 3 2
Bits 00000000h
2C 2F PMLU32 Prefetchable Memory Limit Upper 32
Bits 00000000h
30 33 IOBLU 16 I/O Base and Lim it Upper 16 Bits 0000000 0h
34 34 CAPP Capabilities List P ointer 50h
3C 3D IN T R Inte rrupt Information 0000h
3E 3F BCTRL Brid g e Co ntrol 0000h
40 41 CNF Intel® 6300ESB ICH Conf ig uration 000SSh
42 42 M TT Multi-Transaction Timer 00h
44 47 ST RP PCI Strap Status 00h
50 50 PX_CAPID PCI-X Capab ilities Identifier 07h
51 51 PX _NXTP Next Item Pointer 00h
52 53 PX_SSTS PCI-X Secondary S tatus 0001h
54 57 PX _BS TS PCI-X Bridg e Status 000100D0h
58 5B PX_USTC PCI-X Ups tre a m S p lit Transaction
Control 0000FFFFh
NOTE: Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up-to-
date value of the Revision ID register.
Intel® 6300ESB ICH—18
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654 Order Number: 300641-004US
18.6.1.2 Offset 00: ID—Identifiers
Note: Contains the vendor and device identifiers for software.
5C 5F PX_DSTC PCI-X Downstream Split Transaction
Control 0000FFFFh
60 9F Reserved
E0 E3 ACNF Add itional In te l® 6300ES B ICH
Configuration 0000000Fh
E4 E5 PCR PCI Com pensation Regist er 0002h
F0 F3 HCCR Hu b Interfa ce Comman d/C ontrol
Register 00000000h
F4 F7 Reserved
F8 F9 PC33 Prefetc h Control – 33 MHz 1111h
FA FB PC66 Prefetch Control – 66 MHz 3121h
FC FF Reserved 7B7BBFFFh
Table 585. Offset 00: ID—Identifiers
Bits Name Description Reset
Value Access
31:1
6Dev i ce I D
(DID) Indicates what device number was ass igned by the PCI SIG. 25AEh RO
15:0
0Vendor ID
(VID) 16-b it f ield which ind icates t hat Inte l is the vendor. 8086h RO
Table 584. Configuration Space Register Summary (Sheet 2 of 2)
Start End Symbol Full Name Default
NOTE: Refer to the Intel® 6300ESB I/O Controller Hub Sp ec if icat ion Update for the mos t up-to-
date value of the Revision ID reg ister.
Device 28 Function 0
Offset 00 Attribute: Read-Only
Size: 32-bit
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18.6.1.3 Offs et 04: CMD—Command
This controls how the device behaves on the primary interface and is the same as all
other devices, with the exception of the VGA Palette Snoop bit. As this component is a
bridge, additional command information is located in a separate register called “Bridge
Con tro l” loca te d at offse t 3E.
Table 586. Offset 04: CMD—Command (Sheet 1 of 2)
Bits Name Description Reset
Value Access
15:1
0Reserved Reserved. 00h RO
09
Fast Back-
to-back
enable
(FBE)
This bit has no meaning on the Hub Interface. It is hardwired
to '0'. 0RO
08 SERR#
Enable
(SEE)
Con trols t he ena b le fo r a sse rtion of SERR# (via N MI /S M I#)
when the SSE bit (D2 8:F0:Offset 06h , bit 14 ) is set. See
Section 5.1.4 for more details on this bit.
0 = SERR# disabled
1 = SERR# enab le d
0R/W
07 Wait Cycle
Control
(WCC) Reserved. 0 RO
06
Parity Error
Response
Enable
(PERE)
Controls the Intel® 6300ESB ICH's resp onse whe n a par ity
erro r is dete cted on the Hu b In te rf ace .
0 = The Intel® 6300ESB I CH ignor es t hese erro rs on the Hu b
Interface.
1 = The Intel® 6300ESB ICH reports these errors on the Hub
Interface a nd sets the DPD b it in the status reg ister.
NOTE: The Hub Interface Parity Unsupported bit
(D30:F0:40h:bit 20) must be cleared for the PER bit
to have any effect.
0R/W
05
VGA Palette
Snoop
Enable
(VGA_PSE)
Reserved. 0 RO
04
Memory
Wri t e and
Invalidate
Enable
(MWIE)
The Intel® 6300ESB ICH does not g e nerate memory write
and invalidate transactions, as the Hub Interface does not
have a corresponding transfer type. 0RO
03
Special
Cycle
Enable
(SCE)
Reserved. 0 RO
Device 28 Function 0
Offset 04 Attribute: Read/Write
Size: 16-bit
Intel® 6300ESB ICH—18
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18.6.1.4 Offset 06: PS TS—P rimary Status
Note: For the writable bits in this register, writing a ’1’ clears the bit. Writing a ’0’ has no
effect.
Note: RASERR# will be asserted based on activity of bits 15:11, 8.
02 Bus Master
Enable
(BME)
Contr ols the ability of the Intel® 6300ESB ICH to act as a
master on the Hub Interface when forwarding memory
transa ctions from PCI-X.
When '0': the Intel® 6300ESB ICH does not res pon d to any
memo ry trans actions on the PCI-X inte rf ace that ta rg e t Hu b
Interface.
0R/W
01
Memory
Space
Enable
(MSE)
Contr ols the ability of the Intel® 6300ESB ICH to resp ond as
a target to memory accesses on the Hub Inte rf ace tha t
address a device behind the Intel® 6300E SB ICH. 0R/W
0I/O Space
Enable
(IOSE)
Contr ols the ability of the Intel® 6300ESB ICH to re spond as
a target to I/O transactions on the primary interface that
address a device that resides behind the Intel® 6300ESB ICH. 0R/W
Table 586. Offset 04: CMD—Command (Sheet 2 of 2)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 04 Attribute: Read/Write
Size: 16-bit
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Table 587. Offset 06: PSTS—Primary Status
Bits Name Description Reset
Value Access
15 Detected
Parity Error
(DPE)
When set to 1, this bit indicates that the Intel® 6300ESB ICH
dete cted an add ress parity, d ata par ity, erro r on the Hu b
Interface . T h is bit gets set even when the Parity Error
Response bit (bit 6 of the com mand re giste r) is not set. Note
that each bridge sets this bit, regardless of address.
NOTE: The Hub Interface Parity Unsupported bit
(D30:F0:40h:bit 20) must be cleared for the PER bit
to have any effect.
0R/WC
14 Signaled
System
Error (SSE)
This bit is set to ’1’ whe n the SERR# is reported to the H ub
Interface through the NMI/SMI# a ssertion whe n enable d . 0R/WC
13
Received
Master
Abort
(RMA)
This bit is set whenever the Intel® 6300ESB ICH is acting as
master on the Hub Interface and receives a c ompletion
packet with master abort status. 0R/WC
12 Received
Target
Abort (RTA)
This bit is set whenever the Intel® 6300ESB ICH is acting as
master on the Hub Interface and receives a c ompletion
packet with target abort status. 0R/WC
11 Signaled
Target
Abort (STA)
This bit is set whenev er the Inte l® 6300ESB ICH generates a
comp le tion p a cket with ta rg e t abor t status. 0R/WC
10:0
9
DEVSEL#
Timing
(DVT)
These bits have no meaning on the Hub Interface. Fast
decode timing is reported. 00 RO
08
Data Parity
Error
Detected
(DPD)
This bit is set whe n the Inte l® 6300ESB ICH receives a
comp le tion p ack et from the Hu b Interf ace f rom a prev ious
requ e st and dete cts a parity error, and the Parity Error
Respons e b it in t he Comm and Regi ste r (off s et 04h , bit 6) is
set.
0R/WC
07
Fast Back-
to-Back
Capable
(FBC)
This bit has no meaning on the Hub Interfac e. 0 RO
06 Reserved Reserved. 0 RO
05 66 MHz
Capable
(C66)
This bit has no meaning on the Hub Inte rf a ce but is set to be
true in case of any s oftware dependencies on bandwidth
calculations. 1RO
04
Capabil-
ities Li st
Enable
(CAPE)
Indicates that the Intel® 6300ESB ICH contains the
capab ilities poin te r in th e bri dge . Of fs e t 34h in d ica te s the
offse t f or th e fir st en try in the lin ked list of cap a bi litie s. 1RO
03:0 Reserved Reserved. 0h RO
Device 28 Function 0
Offset 06 Attribute: Re ad/Write Clear
Size: 16-bit
Intel® 6300ESB ICH—18
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658 Order Number: 300641-004US
18.6.1.5 Offset 08: RID—Revision ID
Ta ble 588. Offset 08: RID—Revision ID
Bits Name Description Reset
Value Access
07:0 Revision ID
(RID)
Refer to the Intel® 6300ESB I/O Controller Hub Spec if ica tion
Update for the mo st up -to-d ate value of the Revision ID
register. 00h RO
Device 28 Function 0
Offset 08 Attribute: Read-Only
Size: 8-bit
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18.6.1.6 Offset 09: CC—Clas s Code
Note: This contains the class code, sub class code, and programming interface for the device.
18.6.1.7 Offs et 0C: CLS—Cache Line Size
Note: This indicates the cache line size of the system.
Table 589. Offset 09: CC—Class Code
Bits Name Description Reset
Value Access
23:1
6Base Class
Code (B CC) T he val ue of 06h indicates that this is a bridge device. 06h RO
15:0
8Sub Class
Code (S CC) 8-bit value that indicates this is of typ e PCI-PCI bridg e . 04h RO
07:0
Programmi
ng
Interface
(PIF)
Indic ate s that this is stand a rd (non-subtractive) PCI-PCI
bridge. 00h RO
T abl e 59 0. Of fs e t 0C : CLS —C ac h e Lin e Si ze
Bits Name Description Reset
Value Access
07:0 Cache Line
Size (CLS)
The value in this re gis te r is used by th e Inte l® 6300ESB ICH
to dete rmine the size of packets on the Hu b Interfa ce. This
read/write register specifies the system cache line size in
units of dWo rds. When t he value is ‘08h’, represents a 32-
byte line (8 dWords). A value of ‘10h’ represents a 64-byte
line, and a value o f ‘20h’ represents a 128-byte line.
Any value outside this range defaults to a 64-byte line. When
the Intel® 6300ESB ICH is creating read and write re qu ests
to the Hub Inte rf ace , this value is us ed to partition the
requ e sts such tha t multiple snoop s f or th e sa me line are
avoided in the memory subsystem.
00h R/W
Device 28 Function 0
Offset 09 Attribute: Read-Only
Size: 24-bit
Device 28 Function 0
Offset 0C Attribute: Read/Write
Size: 8-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
660 Order Number: 300641-004US
18.6.1.8 Offset 0D: PLT—Primary Latency Timer
Note: This register does not apply to Hub Interface and is maintained as R/W for software
compatibility.
18.6.1.9 Offset 0E: HTYPE—Header Type
Note: This register determines how the rest of the configuration space is laid out.
Table 591. Offset 0D: PLTPrimary Latency Timer
Bits Name Description Reset
Value Access
07:0
3Time V alue
(TV) Read/writ e for software comp a tib ility only. 00h R/W
02:0 Reserved Reserved. 000 RO
Table 592. Offset 0E: HTYPE—Header Type
Bits Name Description Reset
Value Access
07
Multi-
function
device
(MFD)
Reserved as ’0’ to indicate the bridg e is a single function
device. 0RO
06:0 Header
Type
(HTYPE)
Defines the layout of addresses 10h through 3Fh in
configuration space. Reads as ‘01h’ to indicate that the
register layou t conforms to the standard PCI-to-PCI bridge
layout.
01h RO
Device 28 Function 0
Offset 0D Attribute: Read/Write
Size: 8-bit
Device 28 Function 0
Offset 0E Attribute: Read-Only
Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 661
18—Intel® 6300ESB ICH
18.6.1.10Offset 18: BNUM—Bus Numbers
Note: T his conta i ns th e pr imary, seco ndar y, and ma ximu m sub ord in ate bu s num ber regi st ers .
18.6.1.11Offset 1B: SLT—Secondary Latency Timer
Note: This timer contr ols the amount of time that the Intel® 6300 ESB ICH con tinue s to bur st
data on i ts se co nd ar y i nte r fac e . T he c ounter starts c ount in g do wn fro m t he as se rt ion of
PXFRAME#. When the grant is removed, the expiration of this co unter results in the
deass er tion of PXFR AME#. When the gr ant ha s no t been r emov ed, the Int el® 6300E SB
ICH may continue ownership of the bus. The secondary latency timer's default value
should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X 1.0 Specification).
Table 593. Offset 18: BNUM—Bus Numbers
Bits Name Description Reset
Value Access
23:1
6
Subordinat
e Bus
Number
(SBBN)
Indi c ate s the highest P CI bus number bel ow this bridge. Any
type one configuration cycle on the Hub Interface whose bus
number is greater than the secondary bus number and less
than or eq ual to the subordinate bus number is run as a ty pe
one configuration cycle on the P CI bus.
00h R/W
15:0
8
Secondary
Bus
Number
(SCBN)
Ind ica tes th e bus nu mber of PCI to which the secondary
interfa ce is connected. Any type one configuration cycle
matching this bus num ber is translated to a type 0
configuration cycle and run on the PCI bus.
00h R/W
07:0
0
Primary
Bus
Number
(PBN)
Indicat es the bus number of the Hub In terface. Any type 1
configuration cycle with a bus number less than this number
is not accepted by this portion of the Intel® 6300ESB ICH
(i.e., it still may ma tch th e othe r b ridge).
00h R/W
Table 594. Offset 1B: SLT—Secondary Latency Timer
Bits Name Description Reset
Value Access
07:0
3
Secondary
Latency
Timer (TV)
A five-b it value tha t indi ca te s the n umb e r of PCI clocks, in 8-
clock increments, that the Intel® 6300ES B ICH re mains as a
master of the PCI bus when another master is requesting use
of the PCI bus.
00h R/W
02:0
0Reserved Reserved. 000 RO
Device 28 Function 0
Offset 18 Attribute: Read/Write
Size: 24-bit
Device 28 Function 0
Offset 1B Attribute: Read/Write
Size: 8-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
662 Order Number: 300641-004US
18.6.1.12Offset 1C: IOBL—I/O Base and Limit
Note: Defines the base and limit, aligned to a 4 Kbyte boundary , of the I/O area of the bridge.
Accesses from the Hub Interface that are within th e ranges specified in this register are
sent to PCI-X when the I/O space enable bit is set.
Note: Accesses from PCI-X that are outside the ranges specified result in a master abort.
Table 595. Offset 1C: IOBL—I/O Base and Limit
Bits Name Description Reset
Value Access
15:1
2
I/O Limit
Address
Bits
[15:12]
(IOLA)
Defines the top address of an address range to determine
when to forward I/O tran sactions from one interface to the
other. These bits correspond to address lines 15:12 for 4
Kbyte alignment. Bits 11:0 are assumed to be FFFh.
0h R/W
11:1
0
I/O Limit
Address
Bits
[11:10]
(IOLA1K)
When the EN1K bit is set in the Inte l® 6300ESB ICH
Configuration register (C NF ), the se bi ts become re ad/write
and are compared with I/O address bits 11:10 to determine
the 1K limit address. When the EN1K bit is cleared, this field
becomes Read Only.
00 R/W
09:0
8
I/O Limit
Addressing
Capability
(IOLC)
This is hard-wired to 0h, indicating support for only 16-bit I/O
addressing. 0h RO
07:0
4
I/O Base
Address
Bits
[15:12]
(IOBA)
Defi nes the bottom addr ess of an address rang e to determine
when to forward I/O tran sactions from one interface to the
other. These bits correspond to address lines 15:12 for
4 Kbyte alignment. Bits 11:0 are assumed to be 000h.
0h R/W
03:0
2
I/O Base
Address
Bits
[11:10]
(IOBA1K)
When the EN1K bit is set in the Inte l® 6300ESB ICH
Configuration register (C NF ), the se bi ts become re ad/write
and are c ompared with
I/O addres s bits 11:10 to determine the 1K bas e add ress.
When the EN1K bit is cleared, this field becomes Read Only.
00 R/W
01:0
0
I/O Base
Addressing
Capability
(IOBC)
This is hard-wired to 0h, indicating support for only 16-bit I/O
addressing. 0h RO
Device 28 Function 0
Offset 1C Attribute: Read/Write
Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 663
18—Intel® 6300ESB ICH
18.6.1.13Offset 1E: SSTS—Secondary Status
Note: For the writable bits in this register, writing a ’1’ clears the bit. Writing a ’0’ to the bit
has no effect.
Note: RASERR# will be asserted based on activity of bits 15:11, 8.
T abl e 59 6. O f fse t 1E: SSTS Se co n dar y St at u s (S he et 1 of 2)
Bits Name Description Reset
Value Access
15 Detected
Parity Error
(DPE)
This bit is set to a ’1’ whe ne ver the Inte l® 6300ESB ICH
det e cts a a d dress or da ta p a rity error on the P CI-X bus. T h is
bit gets set even when the Parity Error R esponse bit (bit ’0’ of
offset 3E-3F) is not set.
0R/WC
14 Received
System
Er ror (RS E)
The In tel® 6300ESB ICH sets this bit when a SERR# assertion
is received on PCI-X. 0R/WC
13
Received
Master
Abort
(RMA)
This bit is set whenever the Intel® 6300ESB ICH is acting as
an ini tiato r o n t he P CI -X bus an d th e c ycl e i s mas ter -a b orted.
For Hub Interface packets that have completion required, this
sho u ld al so ca use a targe t a bort comp letion status to be
returned and set the Signaled Target Abort bit in the primary
st a tu s re g i ste r.
0R/WC
12 Received
Target
Abort (RTA)
This bit is set whenever the Intel® 6300ESB ICH is acting as
an initiator on PCI-X and a cycle is targ et-ab orted on P CI-X.
For “completion required” Hub Interface packets, this event
should force a completion status of “target abort” on the Hub
Interface and se t the Signa led Target Abort in the Primary
Stat us Register.
0R/WC
11 Signaled
Target
Abort (STA)
This bit is set to ’1’ when the Intel® 6300ESB ICH is acting as
a target on the PCI-X Bus and signals a target abort. 0R/WC
10:9 DEVSEL#
Timing
(DVT)
Indicates that the Intel® 6300ES B ICH re sponds in med ium
decod e time to a ll cy cles targ e ting the H ub Inter fac e . 01 RO
8
Data Parity
Error
Detected
(DPD)
The Int el ® 6300ESB ICH sets this bit when all of the f ollowing
are true:
•The Intel
® 6300ESB ICH is the initiator on PCI-X.
PE RR # is d etected a sse rted or a p a rity err o r is d e t e cte d
internally.
The Parity Error Response Enable bit in the Bridge Control
Register (bit 0, offset 3Eh) is set.
0R/WC
7
Fast Back-
to-Back
Capable
(FBC)
Indicate s that the secondary interface of the Intel® 6300ESB
ICH may re ce ive fast back-to-back cyc le s. 1RO
6 Reserved Reserved. 0 RO
Device 28 Function 0
Offset 1E Attribute: Re ad/Write Clear
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
664 Order Number: 300641-004US
18.6.1.14Offset 20: MBL—Memory Base and Limit
Note: Defines the base and limit, aligned to a 1 Mbyte boundary, of the memory area of the
bridge. Accesses from the Hub Interface that are within the ranges specified in this
register are sent to PCI-X when the memory space enable bit is set.
Note: Accesses from PCI-X that are outside the ranges specified are forwarded to the Hub
Interface when the bus master enable bit is set.
566 MHz
Capable
(C66)
Indicates the secondary interfac e of the brid g e is 66 MH z
capable. 1RO
4PERR#
Assertion
Detect
This bit is set by hardware whenever the PERR# pin is
asserted on the rising edge of PCI-X clock. This includes cases
in which the chipset is the agent driving PERR#. It re mains
asserted until cle ared by software writin g a ‘1’ to this
location. W he n en abled by the PERR#-to-SERR# Enable bit
(in the Br id ge Control reg iste r), a ‘1’ in th is bit can generate
an internal SERR# and be a source for the NMI logic.
R/WC
3:0 Reserved Reserved. 00h RO
Table 597. Offset 20: MBL—Memory Base and Limit
Bits Name Description Reset
Value Access
31:2
0Memory
Limit (ML)
These bits are compared with bi ts 31:20 of the inco ming
address to det ermine the upper 1 Mbyte aligned value
(excl u siv e) of the rang e . The inc oming add re ss must b e less
than or equa l to this value.
000h R/W
19:1
6Reserved Reserved. 0h RO
15:0
4Memory
Base (MB)
These bits are compared with bi ts 31:20 of the inco ming
addres s to determine th e lowe r 1 Mbyte aligned value
(inclusive) of the rang e . The inc oming address m u st be
greater than or equal to thi s valu e.
000h R/W
03:0
0Reserved Reserved. 0h RO
Table 596. Offset 1E: SSTS—Secondary Status (Sheet 2 of 2)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 1E Attribute: Re ad/Write Clear
Size: 16-bit
Device 28 Function 0
Offset 20 Attribute: Read/Write
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 665
18—Intel® 6300ESB ICH
18.6.1.15Offset 24: PMBL —Prefetchable Memory Base and Limit
Note: Defines the base and limit, aligned to a 1 Mbyte boundary, of the prefetchable memory
area of th e b ridge. Acce sses from the Hu b In terf ace tha t are w ithin the r anges sp ec ified
in this register are sent to PCI-X when the memory space enable bit is set.
Note: Accesses from PCI-X that are outside the ranges specified are forwarded to the Hub
Interface when the bus master enable bit is set.
18.6.1.16Offset 28: PMBU32—Prefetchable M emory Base Upper 32
Bits
Note: This defines the upper 32 bits of the prefetchable address base register.
Table 598. Offset 24: PMBL—Prefetchable Memory Base and Limit
Bits Name Description Reset
Value Access
31:2
0
Prefetchabl
e Memory
Lim it (PM L )
These bits are compared with bits 31 :20 of the incoming
address to determine the upper 1 Mbyte aligned value
(ex clus i ve) of the range . The incoming addr es s must be l e ss
than this value.
000h R/W
19:1
6
64-bit
Indicato r
(IS64L)
Indicates that 32-b it a d dr es sin g is support ed f or the limit.
This value must be in agreement with the IS64B field. 1h RO
15:0
4
Prefetchabl
e Memory
Base (PMB)
These bits are compared with bits 31 :20 of the incoming
add re ss to d e te rmine the low er 1 Mbyt e alig n e d value
(inclu s i ve) of the range. The incoming addr es s must be
greate r than or e q ual to this value.
000h R/W
03:0
0
64-bit
Indicato r
(IS64B)
Indicates that 32-b it a d dr es sin g is support ed f or the limit.
This value must be in agreement with the IS64L field. 1h RO
T abl e 59 9. Of fs e t 28: PMB U 32 —P r ef e tch able Me m o ry Ba s e U pp er 32 Bits
Bits Name Description Reset
Value Access
31:0
0
Prefetchabl
e Memory
Base Upper
Portion
(PMBU)
All bits are read/writable.
This register should always be programmed to 00000000h
since the Intel® 6300ES B ICH only support s 32-b it
downstream addressing and 64-bit upstream addressing
00000000h R/W
Device 28 Function 0
Offset 24 Attribute: Read/Write
Size: 32-bit
Device 28 Function 0
Offset 28 Attribute: Read/Write
Size: 32-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
666 Order Number: 300641-004US
18.6.1.17Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32
Bits
Note: This defines the upper 32 bits of the prefetchable address limit register.
18.6.1.18Offset 30: IOBLU16—I/ O Base and Limit Upper 16 Bits
Note: Since I/O is limited to 64 Kbytes, this register is reserved and not used.
Table 600. Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits
Bits Name Description Reset
Value Access
31:0
0
Prefetchabl
e Memory
Limit Upper
Portion
(PMLU)
All bi ts are read/writ abl e - the Intel® 6300ESB ICH supports
full 64-bit addressing.
NOTE: The upper 32 bits should not be used to determine the
prefetch region. The Intel® 6300ESB ICH sup p orts
onl y 32-bi t downstr eam c ycles, so the up per 3 2 bits of
the prefetch region are ignored. Prefetch regions are
limited to a single 4 Gbyte boundary. The upper 32
bits of the prefetch region cannot be used to extend
this region. The Intel® 6300ESB ICH supports 64-bit
upstream cycles, a lthough the up per 32 b its are not
used to dete rmined the de stina tion if the target lies
within the Intel® 6300ES B ICH.
00000000h R/W
Table 601. Offset 30: IOBLU16—I/O Base and Limit Up per 16 Bits
Bits Name Description Reset
Value Access
31:1
6
I/O Base
High 16
Bits (IOBH) Reserved. 0000h RO
15:0
0
I/O Limit
High 16
Bits (IOLH) Reserved. 0000h RO
Device 28 Function 0
Offset 2C Attribute: Read/Write
Size: 32-bit
Device 28 Function 0
Offset 30 Attribute: Read-Only
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 667
18—Intel® 6300ESB ICH
18.6.1.19Offse t 34: CAPP—Capabilities List Pointer
Note: C ontains the pointer for the first entry in th e capabilities list.
18.6.1.20Offse t 3C: INTR—Interrupt Information
Note: This register contains information on interrupts on the bridge.
18.6.1.21Offset 3E: BCTRL—Bridge Control
Note: This register provides extensions to the Command register that are specific to a bridge.
The Bridge Control register provides many o f the same controls for the secondary
int erfa ce tha t are prov ided by the Com ma nd register fo r the primary in ter fac e. Som e
bi ts aff ect op e ra t io n of bo th i nt er faces of th e b ri dge.
Table 602. Offset 34: CAPP—Capabil ities List P ointer
Bits Name Description Reset
Value Access
07:0
0
Capabil-
ities Pointer
(PTR)
Indicates that the pointer for the first entry in the capabilities
list is at 50h in con f ig u ration sp a ce. 50h RO
T abl e 60 3. O ffs e t 3C: IN TR —I n ter r upt In f or ma t io n
Bits Name Description Reset
Value Access
15:0
8Interrupt
Pin (PIN) B rid g e s do not sup p ort the genera tion of interrupts. 00h RO
07:0
0Interrupt
Line (LINE) The Int el® 6300ESB ICH Bridge does not generate interrupts,
so this is reserved as 00h. 00h RO
Device 28 Function 0
Offset 34 Attribute: Read-Only
Size: 8-bit
Device 28 Function 0
Offset 3C Attribute: Read-Only
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
668 Order Number: 300641-004US
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 1 of 3)
Bits Name Description Reset
Value Access
15:1
1Reserved Reserved. 0h RO
12 PERR# to
SERR#
Enable
When this b it is se t to ‘ 1’, PCI-X PERR NM I re po rting is
enabled. In ad di tion to setting this bit, you also must set b it
’1’ of D30_F0 PN E Register. Section 7.1.28
When this b it is set to a ‘1’ and PERR # is asser ted on PCI-X,
the P ER R# Asser tion d etect statu s bit in t he Secondary
Status Register will indica te a PE RR# inte rnal SERR #
assertion. The SERR # can be a s sou rce on NMI.
11
Discard
Timer
SERR#
Enable
(DTSE)
Controls the gene ration of SERR# on the primary interface in
response to a timer discard on the secondary interface.
Wh e n 0: Do not gen e rate SE RR# on a se c o ndary timer
discard
Whe n 1 : Gen e ra te SERR# in re sp on se to a se condar y timer
discard
0R/W
10
Discard
Timer
Status
(DTSb)
This bit is set to a ’1’ when the secondary dis card time r
expi r es (there is no disca rd time r for the primary i nterface) . 0R/WC
09
Secondary
Discard
Timer
(SDT)
Sets the maximum number of PCI clock cy cles that the Intel®
6300ES B ICH waits for an initiator on PCI to repeat a delayed
tran saction request. The counter starts once the delay ed
transaction completion is at the head of the queue. If the
mast er h a s not re p eated the tra n sa ction at le ast once before
the counter ex p ires, the Intel® 6300ES B ICH discards the
transact ion from its queue s.
When 0: The PCI master timeout value is between 2^15 and
2^16 PCI clocks.
When 1: The PCI master timeout value is between 2^10 and
2^11 PCI clocks
0R/W
08
Primary
Discard
Timer
(PDT)
Not rele vant to Hub Inte rf a ce. This bit is R/W for sof tware
compatibility only. 0R/W
07
Fast Back -
to-Back
Enable
(FBE)
The I n t el® 6300ESB ICH cannot generate fast back -to-back
cycles on the PCI-X bus from Hub Interface initiated
transactions. 0RO
Device 28 Function 0
Offset 3E Attribute: Read/Write
Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 669
18—Intel® 6300ESB ICH
06 Secondary
Bus Reset
(SBR)
Controls PXPCIRST# assertion on PCI- X bus when SBRE is
set. See Section 18.6.1.32, “Offset E4: PCR - PCI
Compensat i on Reg i ster” for SBRE detail s .
1 = The Intel® 6300ESB ICH ass er ts PCIXS BRS T#. When
PCIXSB RS T# is asserte d , the data buff er s betw e en the
Hub Interface and PCI-X and the PCI-X bus are initialized
back t o re se t con d it ions. Th e Hub I nt e rf a ce an d t he
con figu ra tion regis ter s a re n ot a f fected. To be effe ctiv e,
software must keep asserted fo r at least 100 µsecs.
0 = The Intel® 6300ESB ICH d e-asserts PCIXSBRS T#
0R/W
05 Master
Abort Mode
(MAM)
Controls the Intel® 6300ESB ICH's behavior whe n a master
abort occurs on either in ter face.
Master Abor t on Hub In t er f ace:
When 0: The Intel® 6300ESB ICH asserts TRDY# on PCI- X. It
drives all '1's for reads and discards data on writes.
When 1: The Intel® 6300ESB ICH re turns a target abort on
PCI-X.
Ma st er Ab ort PCI/PC I-X: (Completion required packets
only)
When 0: Normal completion status is returned on the Hub
Interface.
When 1: Target abort comp le tion status is returned on the
Hub Interface.
0R/W
04 VGA 16-bit
Decode
Enables the bridge to provide 16 bits decoding of VGA I/O
addres s prec ludin g the de code of VGA al ias addr esses ev ery 1
KB. This bit requires the VGA enable bit (bit 3 of this register)
to be set 1.
0R/W
03 VGA Enable
(VGAE)
Modifies the Intel® 6300ESB ICH's response to VGA
compatible address. When set to a 1, the Intel® 6300ESB ICH
forwards the following transactions from the Hub Interface to
PCI-X regardless of the value of the I/ O bas e and limit
register s. The transactions are qualified by the m emory
enable and I/O enable in the command register.
Memory addresses: 000A0000h-000BFFFFh
I/O addresses: 3B0h-3 BBh and 3C0h-3DFh. For the I/O
addresses, bits [63:16] of the address must be 0, and bi ts
[15:10] of the address are ignored (i.e., aliased).
Th e same holds true from second a ry a cce sses to the primary
interface in reverse. That is, when the bit is 0, memory and I/
O addre sses on th e second a ry interf a ce between the above
ranges are forwar ded to the Hub Interface.
0R/W
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 2 of 3)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 3E Attribute: Read/Write
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
670 Order Number: 300641-004US
02 ISA Enable
(IE)
Modifies the response by the bridge to ISA I/O addresses .
This only applies to I/O addresses that are enabled by the I/O
Base and I/O Limit registers and are in the first 64 Kbytes of
PCI-X I/O sp ace. When this bit is se t, the bridg e block s any
forwarding from primar y to secondary of I/O transactions
addressing the last 768 b y te s in each 1 Kbyte b lock (of f sets
100h to 3FFh). This bit has n o effect on transfe rs or igi nating
on the se condary b u s a s the Intel® 6300ESB ICH does not
forward I/O transactions across the bridge.
0R/W
01 PXSERR#
Enable (SE) When set, the bridge is enabled for SERR reporting. 0 R/W
0
Parity Error
Response
Enable
(PERE)
Controls the Inte l® 6300ES B ICH's resp ons e to address and
data p arit y error s on t he se condary i nt er face. When the bi t is
cleared, the bridge must ignore any parity errors that it
detects and continue normal operation. The Intel® 6300ESB
ICH must generate parity even when parity error reporting is
disabled.
0R/W
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 3 of 3)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 3E Attribute: Read/Write
Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 671
18—Intel® 6300ESB ICH
18.6.1.22Offset 40: CNF—Intel® 6300ESB I/O Controlle r Hub
Configuration
Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration
(Sheet 1 of 3)
Bits Name Description Reset
Value Access
15 Reserved Reserved. 0 RO
14:1
0
Disable
PXPCLKOU
T 4- 0
(DPCLK)
Disables a PCI-X cl ock outp ut tha t is not us ed in the sy stem.
Bit 10 ref e rs to PCL KOUT0, bit 11 to PCLKOUT1, etc. When
disabled, the PCLKOUT pin is tri-stated.
NOTE: B it 14 co ntrols the feedbac k pa th. Thi s bi t should not
be written to a ‘1’.
00h R/W
09
Enab le I/O
Spa ce to
1K
Granularity
(EN1K)
When se t, this enable s the I/O sp ace to be decoded to 1K,
down f rom th e 4K lim it tha t currently exis ts in the I/O bas e
and limi t regist ers. It does thi s by redefinin g bits [11:1 0] and
bits [3: 2] of the IOBL re gis te r at of fs e t 1C to be read/write
and enables them to be compared with I/O address bits
[11:10] to determine if the y are within the bridge 's I/O
range.
0R/W
08 PCI-X Mode
(PMODE)
When set, indicates the b us is oper ating in PCI- X mode. When
cle are d, in di c ate s the bu s is i n PC I mo de. The power up val ue
of this register is written based upon the table below:
PCIXCAP=Bit 7M66EN=Bit 6
PCIXCAP M66EN PCI/XFreq PMODE
0 0 PCI 33 MHz 0
0 1 PCI 66 MHz 0
Mid N/A PCI-X 66 MHz 1
1 N/A PCI-X 66 MHz 1
The def ault v alue (S-selec t va lue) is dete rmined b y the value s
of M66EN and P CIXCAP pins as per the table above.
NOTE: T h is reg iste r should not be wri tten to a nd s hould be
treate d by S of twa re a s Read On ly. Write s will cha nge
the r egis te r va l ue r enderin g th e c on ten ts in v a li d s i nce
the value will not affect the PCI-X Mod e .
R/W
Device 28 Function 0
Offset 40 Attribute: Read/Write
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
672 Order Number: 300641-004US
07:0
6
PCI-X
Frequency
(PFREQ)
Det ermines t he fre quen cy the P CI- X b us operates. The power
up value of this register is writt en based upon the fol lowing
table:
PCIXCAP=Bit 7M66EN=Bit 6
PCIXCAP M66EN PCI/X Freq
0 0 PCI 33 MHz
0 1 PCI 66 MHz
Mid N/A PCI-X 66 MHz
1 N/A PCI-X 66 MHz
After s oftware determines the buses’ cap abilities, it set s this
va lu e an d the P MOD E bi t ( bi t 8 of th i s regis t er ) to the des i red
frequency and resets the PCI-X bus. The values are encoded
as follows:
Bits Freq (MHz)Not es
0 33 Only valid when PMODE is 0.
166
10 not supported
11 not supported
The default value (S-select v alue) is determined by the values
of M66EN and PCIXCAP pins as per the table above.
NOTE: This registe r sh ould not be written to and should be
treated by Software as Read Only. Writes will chan g e
the re gis t er value render i ng th e cont ent s in v alid sin c e
the value will not affect the PCI -X Mode.
0h R/W
05 Restreamin
g Disable
(RSDIS)
When this bit is set, this bridge of the Intel® 6300ESB ICH no
longe r performs res t re aming. This b it only applies wh e n the
bridge is in PCI mode, and not whe n the b rid ge is in PC I-X
mode. When the PCI transaction ends, either due to a PCI
maste r removing PXFRA ME# or the Intel® 6300ESB ICH
asserting ST OP#, the Intel® 63 00ESB ICH di scards al l dat a in
the pr efetc h buffer.
0R/W
Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controlle r Hu b Configuration
(Sheet 2 of 3)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 40 Attribute: Read/Write
Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 673
18—Intel® 6300ESB ICH
18.6.1.23Offset 42: MTT—Multi-Transaction Timer
Note: This register controls the amount of time that the Intel® 6300ESB ICH's arbiter allows
a PCI initiator to perform multiple back-to-back transactions on the PCI-X bus. The
number of clocks programmed in the MT T represents the ensured time slice (measured
in PCI c locks) al lo tted to the cu rrent agen t, after whi ch t he arbit er g rants an other agent
that is requesting the bus.
04:0
3Prefetch
Policy (PP)
Controls how the Intel® 6300ESB ICH prefetches data on
be ha lf o f PCI maste rs:
00: Allo w pref e tching on MRM, M RL, and MR.
01: Allow prefetching on MRM and MRL but not on a memory
read.
1x: Disable all pr efetc h ing.
00 R/W
02
Delayed
Transaction
Depth
(DTD)
Controls the Intel® 6300ESB ICH be havio r relative to the
number and size of the delay ed tra n saction bu ffe rs:
When 0: 4 DTs at 1K for 33/ 66 MH z
When 1: 4 DTs at 1K for all frequencies
This bit is set by platform BIOS, based upon the PCI
frequen c y read from bits 8:6 of this regis t er.
0R/W
01:0
0
Maximum
Delayed
Transac-
tions (MD T)
Contr o ls the maximu m numbe r of de la y ed tra n saction s th e
Intel® 6300ESB ICH is allowed to have:
00: 4 active, 4 p en ding 01: 1 active, 1 pending
10: 2 active, 2 p en ding 11: Re served
00 R/W
Table 606. Offset 42: MTT—Multi-Transaction Timer
Bits Name Description Reset
Value Access
07:0
3
Timer
Count
Value
(MTC)
This f ie ld s pecifies the am oun t of time th at g rant rem a ins
asserted to a ma ste r continuously assertin g its re q u e st f or
multiple tr ansfers. This field specifies the count in an 8-clock
(PCI clock) granularity.
00h R/W
02:0
0Reserved Reserved. 000 RO
Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration
(Sheet 3 of 3)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 40 Attribute: Read/Write
Size: 16-bit
Device 28 Function 0
Offset 42 Attribute: Read/Write
Size: 8-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
674 Order Number: 300641-004US
18.6.1.24Offset 44: STRP—PCI Strap Status
Note: This register indicates the states of various straps for this PCI-X interface.
18.6.1.25Offset 50: PX_CAPID—PCI-X Capabilities Identifier
Note: Identifies this item in the Capabilities list as a PCI-X register set. It returns 07h when
read.
18.6.1.26Offset 51: PX_NXTP—Next Item Pointer
Note: Indicates where the next item in the capabilities list resides. This is the end of the list
and 00h is returned.
Table 607. Offset 44: STRP—PCI Strap Status
Bits Name Description Reset
Value Access
31:0 Reserved Reserved. RO
Table 608. Offset 50: PX_CAPID—PCI-X Capabilities Identifier
Bits Name Description Reset
Value Access
07:0
0Identifier
(ID) Indicates this is a PCI-X ca p a b ilitie s li st. 07h RO
Table 609. Offset 51: PX_NXTP—Next Item Pointer
Bits Name Description Reset
Value Access
07:0
0Reserved Reserved. 00h RO
Device 28 Function 0
Offset 44 Attribute: Read-Only
Size: 32-bit
Device 28 Function 0
Offset 50 Attribute: Read-Only
Size: 8-bit
Device 28 Function 0
Offset 51 Attribute: Read-Only
Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 675
18—Intel® 6300ESB ICH
18.6.1.27Offs e t 52: PX_SSTS—PCI-X Secondary Status
Note: This is the PCI-X command register which controls various modes of the bridge.
Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 1 of 2)
Bits Name Description Reset
Value Access
15:0
9Reserved Reserved. 00h RO
08:0
6
Secondary
Clock
Fre quency
(SCF)
This field is set with the frequen c y of the secondary bu s. The
values are:
Bits M ax Fr equency Clock Period
000 PCI Mode N/A
001 66 15
010 [Not supported]
011 [Not supported]
1xx Reserved Reserved
The default value for this register is given by
PCIXCAP=Bit 7 M66EN=Bit 6
PCIXCAP M66ENPCI/X Freq
0 0 PCI 33 MHz
0 1 PCI 66 MHz
Mid N/A PCI-X 66 MHz
1 N/A PCI-X 66 MHz
xxx RO
05
Split
Request
Delayed.
(SRD)
This b i t is se t b y a b rid ge whe n it can not forward a
transaction on the secondary bus to the primary bus because
there is not enough room within the limit specified in the Split
Transaction Co mmitment Li mit f ie ld in the D ownstream S p lit
Transaction Co ntrol register.
NOTE: The In t el® 6300ESB ICH does not set this bit.
0RO
04
Split
Completion
Overrun
(SCO)
This bit is set when a bridg e terminates a Split Comp letion on
the secondary bus with retry or Disconnect at next ADB
beca u se its buffe rs a re full.
NOTE: The In t el® 6300ESB ICH does not set this bit.
0RO
03
Unexpected
Split
Completion
(USC)
This b it is se t wh e n a n u ne xpe cted split c o mp le tion with a
reque ster ID equal to the Intel® 6300ESB ICH's secondary
bus number, device number 00h , and functi on numbe r 0 is
recei ved on the secondary interfac e. Thi s bit is cleared by
softwar e writing a ‘1’.
0R/WC
Device 28 Function 0
Offset 52 Attribute: Read-Only
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
676 Order Number: 300641-004US
18.6.1.28Offset 54: PX_BSTS - PCI-X Bridge Sta tus
Note: Identifies PCI-X capabilities and current operating mode of the bridge.
02
Split
Completion
Discarded
(SCD)
This bit is set wh en the Intel® 6300ESB ICH d isc ard s a split
completion mov ing toward th e se condary bu s because th e
reques te r would not a cc e pt it. This bit is c le are d by sof twa re
writin g a ‘1’.
0R/WC
01 133 MHz
Capable
(C133)
This bit indica tes that the Inte l® 6300ESB ICH’s secondary
interfa ce is ca p a b le of 133 M Hz op e ration in PCI-X mode.
0 = Not cap abl e
1 = Capable
0RO
00 64-bit
Device
(D64) Indica t e s th e wi d th of the se condary b u s a s 64- b i ts. 1 RO
Table 611. Offset 54: PX_BSTS - PCI-X Bridge Stat us
Bits Name Description Reset
Value Access
31:2
2Reserved Reserved. 0 RO
21
Split
Request
Delayed
(SRD)
The Intel® 6300ESB ICH does not supp ort this bit. 0 RO
20
Split
Completion
Overrun
(SCO)
The Intel® 6300ESB ICH does not set this bit because it does
not reque st more data on the Hub Inter fac e than it may
receive. 0RO
19
Unexpected
Split
Completion
(USC)
This does n ot apply to H ub Inter fac e , wh ich is t he primary
interface. 0RO
Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 2 of 2)
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 52 Attribute: Read-Only
Size: 16-bit
Device 28 Function 0
Offset 54 Attribute: Read-Only
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 677
18—Intel® 6300ESB ICH
18
Split
Completion
Discarded
(SCD)
This doe s not ap pl y to Hub Inte rf ace . 0 RO
17 Reserved Reserved. 0 RO
16 64-bit
Device
(D64)
Default value is 1. The Hub Interface is a 64-bit interface (in
HI2.0, it is 128 bits). 1RO
15:0
8
Bus
Number
(BNUM)
An alias to the PBN field of the BNUM register at offset 18h.
Available for d i agnostic soft ware . 00h RO
07:0
3
Device
Number
(DNUM)
D efau lt value is devi c e 28 . Readable fr om separate PCI-X
diagnosti c sof t wa re . 1Ch RO
02:0
0
Function
Number
(FNUM) Read-only bits for PCI-X diagnostic software. 0h RO
Table 611. Offset 54: PX_BSTS - PCI-X Bridge Status
Bits Name Description Reset
Value Access
Device 28 Function 0
Offset 54 Attribute: Read-Only
Size: 32-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
678 Order Number: 300641-004US
18.6.1.29Offset 5 8: PX_USTC - PCI-X Upstream Split Transaction
Control
Note: This register identifies con trols behavior of the PCI- X Upstream Split Control buff ers for
forwarding Split Transactions from the secondary bus to the Hub Interface.
Note: The Intel® 6300ESB ICH maintains these registers internally; programming is not
required by end users.
18.6.1.30Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction
Control
Note: This register controls behavior of the PCI-X Downstream Split Control buffers for
forwarding Split Transaction s from the Hub Interface to the secondary bus.
Note: The Intel® 6300ESB ICH maintains these registers internally, programming not
required by end users.
Table 612. Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control
Bits Name Description Reset
Value Access
31:1
6
Split
Transaction
Limit (STL)
R/W fi eld available fo r use by diagnostic software.
NOTE: Not used by the Intel® 6300ESB ICH for modifying its
“commitment” level. The Intel® 6300ESB ICH internal
launch algorithms keep buffers from being
overallocated.
0000h R/W
15:0
0
Split
Transaction
Capacity
(STC)
Infinite capacity due to launch algorithm k eeping buffers from
overru nnin g . The In te l® 6300ESB ICH internal launch
algorithms keep buffers from being overallocated. FFFFh RO
Device 28 Function 0
Offset 58 Attribute: Read/Write
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 679
18—Intel® 6300ESB ICH
Ta ble 613. Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control
Bits Name Description Reset
Value Access
31:1
6
Split
Transaction
Limit (STL)
R/W field available for use by diagnostic software.
NOTE: Not used by the Intel® 6300ESB ICH for modifying its
“commit ment” level . The Intel ® 6300ESB ICH internal
launch algorithms keep buffers from being
overallocated.
0000h R/W
15:0
0
Split
Transaction
Capacity
(STC)
Infinite capacity due to launch algorithm keeping b uffers from
overrunning. The Intel® 6300ESB ICH internal launch
algorithms keep buffers from being overallocated FFFFh RO
Device 28 Function 0
Offset 5C Attribute: Read/Write
Size: 32-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
680 Order Number: 300641-004US
18.6.1.31Offset E0: ACNF – Additional Intel® 6300E SB ICH
Configuration
Table 614. Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration
Bits Name Description Reset
Value Access
31:1
6Reserved Reserved. 0 RO
15:1
4Reserved Reserved. 0 R/W
13:1
2
Miscella-
neous
(MSC)
Reserved but maintained as Rea d/Write in case a situation
arises during the project which may require their use. 0R/W
11 Reserved Reserved. 0 R/W
10:0
7Reserved Reserved. 0 R/W
06 Reserved Reserved. 0 RO
05
Bunit
Inbound
Pending
Queue
Bypass
(BUPB)
When 1 , bu ni t by passes i t s r ead pending qu eue w hen empt y.
This bit may only be set to ’1’ when in PCI mode. 0R/W
04 Reserved Reserved. 0 R/W
03:0
0Reserved Reserved. Fh R/W
Device 28 Function 0
Offset E0 Attribute: Read-Only
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 681
18—Intel® 6300ESB ICH
18.6.1.32Offset E4: PCR - PCI Compensation Register
Table 615. Offset E4: PCR - PCI Compensation Register
Bits Name Description Reset
Value Access
15:1
0Reserved Reserved. 0 R/W
09 SBR Enable
(SBRE)
This f i e ld s pecifies the maximum size write a ma ster should
requ e st in a sin g le b
0 = PCI-X secondary bus reset (PCIXSBRST#) disabled and
SBR bit has no effect. See Section 18.6.1.21, “Offset 3E:
BCT RL—Bridge Contr o l”, bit 6, for SBR details.
1 = PCI-X secondary bus reset (PCIXSBRST#) enabled and
SBR is set.
NOTE: Pro cessor always writes a ’1’ into this bit and enables
the se condary bus reset for the P CI-X bus.
0R/W
08:0 Reserved Reserved. 0 R/W
Device 28 Function 0
Offset E4 Attribute: Read/Write
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
682 Order Number: 300641-004US
18.6.1.33Offset F0: HCCR - Hub Interface Command/Control
Register
18.6.1.34Offset F8h Offset FFh: Prefetch Control Registers
The following registers contain prefetch parameters. Each parameter is in 64 byte
cache line quantities. BIOS programs the values in these registers upon power up. The
values in this register are zero-based – a zero means 64 bytes, and ’1’ means 128
bytes, etc.
There is a fifth parameter in the prefetch algorithm, called “D”, which is the delay to
wait before sending a subsequent request of RS when prior requests of RS still have not
brought the prefetch buffers above TS. Its value is in PCI clocks, and is [RS]:111. For
example, when RS = ‘0101’b, then D is ‘0101111b.
Note that for Memory Read (MR) and Memory Read Line (MRL) commands in PCI, no
prefetching is done. A fetch of one cache line (based upon the cache line size register)
is performed and when it drains, the delayed transaction is complete. A new delayed
transaction is established when the master wished the burst to continue.
Table 616. Offset F0: HCCR - Hub Interface Command/Control Register
Bits Name Description Reset
Value Access
31:2
0Reserved Reserved. 0 RO
19:1
6Reserved Reserved. 0h RO
15:1
0Reserved Reserved. 0 RO
09:0
8Reserved Reserved. 0 R/W
07:0
6Reserved Reserved. 00 RO
5:4 Reserved Reserved. 0 RO
03:0
1
Maximum
Data Size
(MAXD)
This field specifies the maximum size write a m aster should
reques t in a sing le bur st, as we ll as the maximum op timal
size read completion a ta rg et shou ld re tu rn. En coding :
000: 32 Byte s
Others: 64 B ytes
000 R/W
00 Reserved Reserved. 0 R
Device 28 Function 0
Offset F0 Attribute: Read/Write
Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 683
18—Intel® 6300ESB ICH
18.6.1.35Offset F8h: PC33 - Prefetch Control – 33 MHz
18.6.1.36Off set FAh: PC66 - Prefetch Control – 66 MHz
Table 617. Offset F8h: PC33 - Prefetch Control – 33 MHz
Bits Name Description Reset
Value Access
15:1
2
Subsequen
t Threshold
(TS) Subsequ e n t t hreshol d size in 64- b yte ca che lin e s 1 h R/W
11:0
8
Subsequen
t Request
(RS)
Subsequent request size in 64-byte c ache lines. Allowable
programmable values are 00h or 01h only. 1h R/W
07:0
4
Initial
Threshold
(TI) Initial threshold size in 64-byte cache lines 1h R/W
03:0
0
Initial
Request
(RI)
Initi al reque st size in 64-b y te cache lin e s. Allowa b le
programmable values are 00h or 01h only. 1h R/W
Table 618. Offset FAh: PC66 - Prefetch Control – 66 MHz
Bits Name Description Reset
Value Access
15:1
2
Subsequen
t Threshold
(TS) Subsequ e n t t h re sh old size in 64 -byte cache lines. 3h R/ W
11:0
8
Subsequen
t Request
(RS)
Subsequent request size in 64-byte c ache lines. Allowable
programmable values are 00h or 01h only. 1h R/W
07:0
4
Initial
Threshold
(TI) Initial threshold size in 64-byte cache lines. 2h R/W
03:0
0
Initial
Request
(RI)
Initi al reque st size in 64-b y te cache lin e s. Allowa b le
programmable values are 00h or 01h only. 1h R/W
Device 28 Function 0
Offset F8h Attribute: Read/Write
Size: 16-bit
Device 28 Function 0
Offset FAh Attribute: Read/Write
Size: 16-bit
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
DS November 2007
684 Order Number: 300641-004US
18.7 PCI Mod e i n th e P C I-X Inte r face
This section discusses the specifics of the PCI interface associated with the PCI-X
interface while operating in PCI mode. The PCI section of this document describes the
“legacy” PCI which is not visible external to the chip. PCI-X is not mentioned in this
section. To see specifics on how the PCI-X interface operates, refer to Secti on 18.8,
“PCI-X Interface”.
18.7.1 Su mmary of Changes
For the most part, the PCI interface of the Intel® 6300ESB ICH is exactly the same as
the PCI interface for the P64H2.
Full 64 bit addressing inbound
Inbound packet size based upon cache line size of the platform.
I/O space may be programmed to 1K granularity through the EN1K bit of the CNF
register.
When inbound reads are retried, they are moved to the side so posted writes and
completion packets may pass. I/O reads and writes on PCI are no longer be
forwarded to the Hub Interface.
18.7.2 Transaction Types
As a PCI master, the Intel® 6300ESB ICH has access to the 32-bit address space. As a
target, the Intel® 6300ESB ICH may accept dual address cycles up to the full 64-bit
address space. The Intel® 6300ESB ICH supports the linear increment address mode
only for bursting memory transfers (indicated when the low two address bits are equal
to ’0’). When either of these address bits is nonzero, the Intel® 6300ESB ICH
disconnects the transaction after the first data transfer.
Table 619. Intel® 6300ESB I/O Controller Hub PCI Transactions
Type of Transaction
Intel®
6300 ESB ICH
as Type of Transac tion
Intel®
6300ESB ICH
as
Maste
rTarge
tMaste
rTarge
t
0000 Interrupt
acknowledge No No 1000 ReservedNo No
0001 Sp e cial cycle Yes No 1001 ReservedNo No
0010 I/O read Y es No 1010 Configuration Read Yes No
0011 I/O write Ye s No 1011 C onfig uration Write Ye s N o
0100 ReservedNo No 1100 Memory Read
Multiple No Yes
0101 ReservedNo No 1101 Dual Addres s Cycl e Yes Y es
0110 Me mory re ad Ye s Yes 1110 Memory Re ad Lin e No Yes
0111 Memory write Yes Yes 1111 Memory Write and
Invalidate No Yes
The Intel® 6300ESB ICH never initi ates a PC I transaction with a rese rve d command code and i gnores
reserved comma nd codes as a target.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 685
18—Intel® 6300ESB ICH
The Intel® 6300ESB ICH decodes all PCI cycles in medium DEVSEL# timing.
18.7.3 Detection of 64-Bit Environment
The Intel® 6300ES B ICH driv es REQ64# low during PXP CI RST# on eac h PCI- X in terface
to signal that the bus is a 64-bit bus.
18.7.4 Data Bus
For supplying data, the Intel® 6300ESB ICH drives the following in the data phase:
The low 32 bits of data on PXAD[31:0]
The low four byte enable bits on PXC/BE#[3:0]
The high 32 bits of data on PXAD[63:3 2 ] (64-bit data phases only)
The high four byte enable bits on PXC/BE#[7:4] (64-bit data phases only)
As a PCI master, when the Intel® 6300ESB ICH drives PXREQ64# and detects
PXACK64# asserted in the same clock that it detects PXDEVSEL# asserted, every data
phase then consists of 64 bits and eight byte enable bits.
On write transactions, when the Intel® 6300ESB ICH does not detect PXACK64#
asserted in the same clock that it detects PXDEVSEL# asserted, it redirects all data to
AD[31:0] and byte enables to C/BE#[3:0]. For 64-bit memory-write transactions that
end at an odd dWord boundary, the Intel® 6300ESB ICH drives the byte enable bits to
’1’, and drives random but stable data on PXAD[63:32].
On r ea d tr ansacti on s , the In t e l® 6300ESB I CH drives eight bits of byte enables on PXC/
BE#[7:0]. It generates byte enables from the Hub Interface byte enables, with the
upper dWord driven on PXC/BE#[7:4]. When ACK64# is not sampled active with
PXDEVSEL# active, then the Intel® 6300ESB ICH downshifts the all byte enables PXC/
BE#[3:0].
The Intel® 6300ESB ICH does not assert REQ64# when initiating a transfer under the
following conditions:
The Intel® 6300ESB ICH is initiating an I/O transaction.
The Intel® 6300ESB ICH is initiating a configuration transaction.
The Intel® 6300ESB ICH is initiating a special cycle transaction.
A 1-dWord or 2-dWord transaction is being performed.
When the address of the Hub Interface initiated transaction is not quad word
aligned.
As a PCI target, the Intel® 6300ESB ICH does not assert PXACK64# when PXREQ64#
was not asserted by the initiator.
18.7.5 Write Transactions
18.7.5.1 Posted
Posted write forwarding is used for memory write and for memory write and invalidate
transactions. When the Intel® 6300ESB ICH decodes a memory write transaction for
the Hub Interface, it asserts PXDEVSEL# and PXTRDY# in the same clock, provided
that enough buffer space is available in the posted data queue. The Intel ® 6300ESB
ICH adds no target wait states.
Intel® 6300ESB ICH—18
Intel® 6300ESB I/O Controller Hub
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686 Order Number: 300641-004US
The Intel® 6300ESB ICH disconnects a write transaction when:
The initiator terminates the transaction by de-asserting PXFRAME# and PXIRDY#.
A 4 Kbyte page boundary is reached.
The posted write data buffer fills up.
18.7.5.2 Non-Posted
Delayed write forwarding is not used. It is only for I/O write transactions. Since the
Intel® 6300ESB ICH does not support I/O write transactions across a bridge, these
cycles all result in a master abort.
Note: Configuration cycles are not allowed to cross a bridge per the PCI br idge specification.
18.7.5.3 Fast Back-to-Back
The Intel® 6300ESB ICH allows fast back-to-back write transactions on PCI.
18.7.6 Read Transactions
18.7.6.1 Prefetchable
Any memory read multiple command on PCI that is decoded by the Intel® 6300ESB
ICH is prefet ched on the Hub Interface. Prefetching may be optionally disabled when bit
4 of the In t el ® 6300ESB ICH Configuration Register (offset 40-41h) is set. The Intel®
6300ESB ICH does not prefetch past a 4 Kbyte page boundary.
18.7.6.2 Delayed
A ll m e mory r ead t r a nsa ctions ar e del a y ed r e ad t r a nsa ctions. When t h e I nt el ® 6300E SB
ICH accepts a delayed read request, it samples the address, command, and address
parity. This information is entered into the delayed transaction queue and all I/O
transactions then master abort.
18.7.7 Transaction Termination
18.7.7.1 Normal Master Termination
As a PCI master, the Intel® 6300ESB ICH uses normal termination when DEVSEL# is
returned by the target within five clock cycles of PXFRAME# assertion. It terminates a
transa ct io n when th e fol lo wi ng cond itio n s are m et:
All write data for the transaction is transferred from the Intel® 6300ESB ICH data
buffers to the target.
The master latency timer expires and the Intel® 6300ESB ICH’s bus grant is de-
asserted.
18.7.7.2 Master Abort Termination
When an Intel® 6300ESB ICH initiated transaction is not responded to with DEVSEL#
within five clocks of PXFRAME# assertion, the Intel® 6300ESB ICH terminates the
transaction with a master abort. The Intel® 6300ESB ICH sets the received master
abort bit in the status register corresponding to the target bus.
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Note: When the Intel® 6300ESB ICH performs a Type 1 to special cyc le translation, a master
abort is the expected termination for the special cycle on the target bus. In this case,
the master abort received bit is not set, and the Type 1 con- figuration transaction is
disconnected after the first data phase.
18.7.7.3 Target Termination Received by the Intel® 63 00 E SB I CH
When th e Intel® 6300ESB ICH receives a retry or disconnect response from a target, it
re-initiates the transfer with the remaining le ngth. When the Intel® 6300ESB ICH
receives a target abort, and the cycle requires completion on the Hub Interface, the
Intel® 6300ESB ICH returns the target abort code to the Hub Interface as the
completion status.
18.7.7.4 Target Termination Initiated by the Intel® 6300ESB I CH
The Intel® 6300ESB ICH returns a target retry to an initiator for memory read
transactions when any of the following conditions are met:
A new transaction for delayed transaction queue.
The request has already been queued, but has not completed on the Hub Interface.
The delayed transaction queue is full, and the transaction cannot be queued.
A LOCK transaction has b ee n esta blishe d from the H ub Interfac e to PCI.
The Intel® 6300ESB I CH disconn ects an i nitiato r w hen one of th e foll owi ng condit ions i s
met:
The Intel® 6300ESB ICH cannot accept any more write data
The Intel® 6300ESB ICH has no more read data to deliver
When the memory address is non-linear
The Intel® 6300ESB ICH returns a target abort to PCI when the cycle master aborted
or target aborted on the Hub Interface.
18.7 .8 LOCK Cycles
A loc k is es tabli shed when a memory read fr om the H ub Inte rfac e t hat targ ets P CI with
the loc k bi t set, and at le ast on e byte enable ac tiv e, i s resp onde d to with a TRDY# b y a
PCI target. The Intel® 6300ESB ICH does not support a split-lock request with no byte
enables are asserted on the initial locked read request. The bus is unlocked when the
Unlock Special Cycle is sent on the Hub Interface.
When the bus is locked, the cy cle is retried when a memory cycle originates on PCI that
is outside the range of the memory windows. No I/O cycles that are destined across the
bridge are accepted, whether the bus is locked or not, and then master abort.
Once the bus is locked, any Hub Interface cycle to PCI is driven with the LOCK# pin,
even when that particular cycle is not locked.
18.7.9 Error Handling
The Intel® 6300ESB ICH checks and generates parity on the Hub Interface and parity
on the PCI interfaces. Parity errors must always be reported to some system level
software, typically the device driver or the OS. This section describes how a standard
PCI bridge handles these errors. For enhanced error detection, see the RAS section
loca t ed se c tio n.
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The Intel® 6300ESB ICH requires that the “Hub Interface Parity Unsupported” bit
(D30:F0:40h:bit 20) is cleared in order to perform any parity checking as described
below. Good Hub Interface parity is presented to all logic in the Intel® 6300ESB ICH
when the bit is set.
To support error reporting on the PCI bus, the Intel® 6300ESB ICH implements the
following:
PERR# and SERR# signals on PCI
Primary status (offset 06-07h) and secondary status registers (offset 1E-1Fh)
The Intel® 6300ESB ICH does not have the PERR# or SERR# pins on the Hub
Interface. The Intel® 6300ESB ICH is capable of generating NMI, and SMI Address
Parity Errors
Address parity errors are very serious an d may abort further data tr ansfers, depending
upon the direction of the transfer and the setting of the Parity Err or Response Enable
bit, as described in the following paragraphs. The Intel® 6300ESB ICH checks address
parit y for all transactions on both the Hub Interface and PCI buses, for all address and
all bus commands.
When the Intel® 6300ESB ICH detects an parity error in the header section of a Hub
Interface packet, it:
Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06-
07h) when t he address is targeting the device. The bridge devices log address
parity errors independ ent of the ta rget address.
Generates NMI/SMI (as enabled) and sets the signaled system error bit in the
primary status register (bit 14 of offset 06-07h), when the parity error response bit
in the command register (bit 6 of offset 04-05h) is set and SERR# is enabled.
Attempts to interpret the cycle as best it can, and forwards the cycle with an
address parity error tag to the internal logic, where it aborts internally. When a
device is not enabled to respond to parity e rrors, it ignores the address parity error
(except for setting the Detected Parity Error bit). When the address targets that
device, the device accepts the cycle and responds as though there was no address
parity error. The cycle is forwarded to PCI with good address parity when the cycle
targets a bridge and it is not enabled to respond to parity errors.
When the Int el® 63 00ESB ICH det ects an address parity error on the PCI int erface, the
following events occur:
The Intel® 6300ESB ICH sets the detected parity error bit in the secondary status
register (bit 15 of offset 1E-1F).
When the parity error response bit is ’0’ in the bridge control register (bit ’0’ of
offset 3E-3F), the address parity errors are ignored. The cycles would be treated as
though no error was observed.
When the parity error response bit is set and the address parity error is observed
on memory cycles, the cycle is accepted as though the address was correct.
Delayed Transactions are established for memory reads and data are posted for
memory writes. The cycles are forwarded to the Hub Int erface with correct addres s
parity.
The Intel® 6300ESB ICH generates NMI/SMI (as enabled) sets the signaled system
error bit in the Primary Status Register, when all of the following conditions are met:
The SERR# enable bit is set in the primary command register.
The parity error response bit is set in the bridge control register.
The SERR# enable bit is set in the bridge control register.
The Intel® 6300ESB ICH generates NMI, if the following conditions are met:
Port70.7 (I/O register at offset 70h, bit 7) is enabled.
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The parity errors response bit is set in the bridge control register (D28:3Eh,0)
18.7.9.1 Data Parity Errors
Unlike address parity errors, data parity errors are not considered as severe and
transactions are aborted. The following sections describe the sequence of events when
a data parity error is detected for the following transactions:
Configuration Write Transactions
Read Transactions (inbound and outbound)
Posted Write Transaction
18.7.9.1.1 Hub Interface Configuration Write Transactions
When the Int el® 6300ESB ICH de tects a data parity error during a Type 0 configuration
write transaction to one of the Intel® 6300ESB ICH configuration spaces, the Intel®
6300ESB ICH:
Does not write the data to the configuration register when parity error response is
enabled.
Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06-
07h).
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit (bit 14) in the Primary status register, when the Parity Error Response
Enable bit in the command register (bit 6 of offset 04-05h) is set.
18.7.9.1.2 Read Transactions from Hub Interface Targeting PCI on the PCI-X
When the Intel® 6300ESB ICH detects a read data parity error on the PCI bus from a
Hub Interface initiated read, it:
Sets the detected parity error bit in the secondary status register (bit 15 of offset
1E-1Fh).
Sets the Da ta pa ri ty d etecte d bi t in t he seco ndary statu s re gis ter ( bit 8 of of fs et 1E-
1Fh), when the secondary interface parity error response bit is set in the bridge
control register (bit ’0’ of offset 3E-3Fh).
Forces bad parity error with the data back to the initiator on the Hub Interface.
18.7.9.1.3 Read Transactions from PCI Targeting Hub Interface
When the Intel® 6300ESB ICH detects a data parity error on a Hub Interface
completion packet from a previous memory read request on PCI, the Intel® 6300ESB
ICH:
Sets the detected parity error bit in the primary status register (bit 15 of offset 06-
07h).
Sets the data parity detected bit in the primary status register (bit 8 of offset 06-
07h) and generates the NMI/SMI (depending on which is enabled), when the
primary interface parity error response bit is set in the command register (bit 6 of
offset 04-05h).
Forwards the bad parity with the data back to PCI.
18.7.9.1.4 Write Transactions on Hub Interface – Intel® 6300ESB ICH as a Hub
Interface Target
When the Intel® 6300ESB ICH detects a data parity error on a Hub Interface write
request, it:
Sets the data parity error detected bit in the status register (bit 15 of offset 06-
07h) of the target interface (PCI bridge primary).
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Forwards the bad parity with the data to PCI when decoded by the bridge.
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit (bit 14) in the Primary status register, when the parity error response bit
(bit 6) is set in the command register.
18.7.9.1.5 Write Transactions on Hub Interface – Intel® 6300ESB ICH as a Hub
Interface Master
There is no way of detecting that a northern device detected a parity error from a Hub
Interface posted write from PCI. Therefore, no action is taken by the Intel® 6300ESB
ICH.
18.7.9.1.6 Write Transactions on PCI – Intel® 6300ESB ICH as PCI Target
When the Intel® 6300ESB ICH detects a data parity error on a PCI write, it:
Asserts PERR# two cycles after the data transfer, when the secondary interface
parity error response bit is set in the bridge control register.
Sets the secondary interface parity error detected bit in the secondary status
register.
Forces bad parity error condition to the primary bus.
18.7.9.1.7 Write Transactions on PCI – Intel® 6300ESB ICH as PCI Master
When a data parity error is reported on the PCI bus from a Hub Interface or PCI peer
initiated write request by the targets assertion of PERR#, the Intel® 6300ESB ICH:
Sets the Detected Parity Detected bit in the secondary status register (bit 8 of
offset 1E-1Fh), when the secondary interface parity error response bit is set in the
bridge control register.
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit in the status register, when all of the following conditions are met:
The SERR# e nab le bit is set in the command register.
The se condar y inte rface parity e rror respo nse bit is set in th e bri dg e control reg ist e r.
The prima ry interface parity error re sponse bi t is se t in th e command register.
—The Intel
® 6300ESB ICH di d not dete ct the p a rity error on the Hub Interface (i.e., the
parity error was not forward e d from the Hu b Inte rf a ce).
18.7.9.2 System Errors
18.7.9.2.1 PCI SERR# Pin Assertion
Whe n SE R R# is sam pl ed as sert ed, the Int el ® 6300ESB ICH sets the received system
error bit in the secondary status register. The Intel® 6300ESB ICH generates NMI/SMI
(depending on which is enabled) when:
The SERR# forward enable bit is set in the bridge control register, and
The primary SERR# enable bit is set in the Primary command register.
18.7.9.2.2 Other System Errors
The Intel® 6300ESB ICH also conditionally NMI or SMI as enabled for any of the
following reasons:
Master timeout on delayed transaction when the primary SERR# enable bit is set
and SERR# due to timeout enable bit (bit 11 of offset 3E-3Fh) is set.
The MAM bit (Master Abort Mode) is set in the bridge control register and a posted
write from the Hub Interface re sults in a master abort on PCI, or a posted write
from one PCI interface results in a master abort on the other PCI interface. (No
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indication is given back on the Hub Interface when a posted PCI write fails on the
Hub Interface – the north Hub Interface agent must handle this condition).
18.8 PCI- X Inte rface
This section is not intended to describe the PCI-X protocol. It is intended to clarify the
Intel® 6300E SB ICH beh avi or in area s of the speci fic atio n whic h are op en to
inte rpr etati on . Ple ase see the PCI -X Add endum to the PCI spec ific ati on, r ev isi on 1. 0 for
all details related to PCI-X operation.
Unless otherwise noted in this section, the Intel® 6300ESB ICH fol lows all rules of the
PCI-X addendum.
18.8 .1 Command Encoding
18.8.2 Attributes
The following table describes how the Intel® 6300ESB ICH fills in attribute fields where
the
PCI-X specification leaves some implementation leeway.
Table 620. PCI-X Interface Command Encoding
Type of Transaction
Intel®
6300ESB ICH
As Type of Transaction
Intel®
6300ESB ICH
As
Maste
rTarge
tMast
er Targe
t
000
0Interrupt
acknowledge No No 100
0Alias to Memory Read
Block No Yes
000
1Special cycle No No 100
1Alia s t o Memory Wr i te
Block No Yes
001
0I/O read Yes No 101
0Configuration Read Yes No
001
1I/O write Y es No 101
1Config urati on Write Y es No
010
0Reserved No No 110
0Split Completion Yes Yes
010
1Reserved No No 110
1Dual Address Cycle Yes Yes
011
0Memory Read dWord Yes Yes 111
0Memory Read Blo ck Yes Yes
011
1Memory Wr ite Yes Yes 111
1Memory Write Block No Yes
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18.8.3 Special Notes for Burst Transactions
The PCI-X specification allows burst transactions to cross page (in the Intel® 6300ESB
ICH’s case, this is 4K) and 4 Gbyte address boundaries. As a PCI-X master, the Intel®
6300ESB ICH ends the transaction at a 4K boundary. As a PCI-X target, the Intel®
6300ESB ICH allows a burst past a 4K page boundary.
The Intel® 6300ESB ICH does not issue an immediate response as a target for a burst
read command, but it must be ready with 128 bytes of d ata space (an ADQ) as an
initiator. When it does not have this space available, it does not issue the transaction.
18.8.4 Device Select Timing
PCI-X targets are required to claim transactions by asserting DEVSEL# as shown in
Table 622. The Intel® 6300ESB ICH responds as a type A target.
18.8.5 Wait States
The Intel® 6300ESB I CH does not gene r ate w ait s ta tes a s a targ e t. I nstea d, i t end s the
transfer.
Table 621. Intel® 6300ESB ICH Imp lementation of Requester Attribute Fields
Attribute Function
No Sno op ( NS)
As a target, this bit is forwarded with the transaction to allow a north bridge to
not snoop the transactio n. It go es to bit ’1’ in the TD Attr field of the Hub
Inter fac e packe t. It is not ge nerated by the Inte l® 6300ESB ICH as a master
from a Hub Interface packet. The Intel® 6300ESB ICH takes no action on this
bit.
Relaxed
Ordering (RO)
This bit allows relaxed ordering of transactions, which the Intel® 6300ESB ICH
does not permit. This bit is simply fo rward e d in the Inte l® 6300ESB ICH, and
is never generated o n PCI-X from a Hub Interface packet.
Tag Since the Intel ® 6300ESB ICH only has one outstanding request on PCI- X at a
time , this f ie ld is be set to 0.
Byte Counts From the Hub Inte rface, this is based upon the length fie ld from the Hub
Inte rfa ce, whic h is dWord ba s ed.
Table 622. DEVSEL# Timing
Decode Speed PCI-X
1 clock after address phase(s) Not Suppo rted
2 clocks after address phase(s) De code A
3 clocks after address phase(s) De code B
4 clocks after address phase(s) De code C
5 clocks after address phase(s) N/A
6 clocks after address phase(s) Sub tractive
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18.8.6 Split Trans actions
18.8.6.1 Completer Attributes
18.8.6.2 Requirements for Accepting Split Completions
The Intel® 6300ESB ICH asserts DEVSEL# and discards the data when the Requester
ID matches the bridge, but the Tag does not match that of any outstanding requests
from this device, or when the byte count exceeds that of the Split Request.
The Hub Interface accepts more than one completion required request from the Hub
Interface, but only one is pending on any PCI/PCI-X interface at a time.
18.8.6.3 Split Completion Messages
The Intel® 6300ESB ICH may only generate error messages for cycles that cross the
bridge that master or target abort. No DWORD cycles cross the bridge that require
completion (i.e., I/O cycles). Therefore, the Intel® 6300ESB ICH generates a “PCI-X
Bridge Error” completion message for the memory read commands as shown in
Table 624.
18.8.6.4 Arbitration Among Multiple Split Completions
The Intel® 6300ESB ICH arbitrates among all active split completions so that each
completion receives consideration for running on PCI. When there are multiple
comple ti on s wai ti ng to us e PC I, th e In te l ® 6300ESB ICH internally arbitrates based
upon its MLT value, even when no other agents are requesting on the bus. Therefore,
the Intel® 6300ESB I CH ends one transaction when its MLT expires, reload, and start
another transaction.
When any particular transaction runs out of data, and there are other active
tr ansaction s to run, the Inte l® 6300ESB ICH switches to the next agent, even when t he
MLT has not expired for that transaction.
Finally , the prefetch algorithm is altered such that several transactions may be active at
one time.
Tab l e 62 3. Int el® 6300ESB ICH Implementation Completer Attribute Fields
Attribute Function
Byte Coun t Modi fied (B CM) This bit i s used for diagnos tic pur poses. The Intel® 6300ESB ICH
never sets this bit.
Split Co mp le tion E rror (SCE) The In tel® 6300ESB ICH is only set this bit when a memory read
command from PCI-X master or target aborted on th e Hub
Interface.
Split Completion Message
(SCM) T h is bit shadows the SCE bit.
Table 624. Split Completion Messages
Index Message
00h Master-Abort: The In t el® 6300ESB ICH encounte re d a Master-Abort on the
destination bus.
01h Target-Abort: The Int el® 6300ESB ICH encountered a Target- Abort on the destination
bus.
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18.8.7 Transaction Termination as a PCI-X Target
18.8.7.1 Retry
The Intel® 6300ESB ICH retries a cycle when the Split Request queue is full (i.e., we
al rea dy ha ve fo ur curr ent and four pend ing Sp l it Trans ac ti ons ). It ha s room to acce p t a
split completion as it has a dedicated buffer for split completions. It also retries a cycle
when the bus is locked. The Intel® 6300ESB ICH stores no state from the transaction
on a retry.
18.8.7.2 Split Response
All cycles that cross the bridge receive this termination, when they are not retried.
18.8.7.3 Master-Abort
Any I /O t ra nsact ion th at wou ld c ross f rom PCI - X to ei the r th e Hub I nter fac e or the p eer
bridge are not decoded and results in a master abort to the PCI-X initiator.
18.8.8 Arbitration
The Intel® 6300ESB ICH parks on the last agent to use PCI. This allows PCI devices
operating as a single stream to stay on PCI bus for the duration of their transfer.
18.8.9 Bridge Buffer Requirements
The Intel® 6300ESB ICH has 128 bytes (one ADQ) available for accepting m emory
write, split completion, and immediate read data. The Intel® 6300ESB ICH contains
1.5K of data total for inbound transactions.
The Intel® 6300ESB ICH PCI-X interface terminates all memory transactions (Memory
Read DWORD, Memory Read Block, and Alias to Memory Read Block) that address a
de vic e no r th of the bri dge wi th a Sp l it Re sponse. Ot he r spl i t transa cti on com ma nds ar e
not decoded by the Intel® 6300ESB ICH.
The Intel® 6300ESB ICH does not implement any split completion buffer allocation
algorithm as listed in the PCI-X specification. This is overhead that is not necessary.
The Intel® 6300ESB I CH does n ot req uest o n the H ub In ter face m ore tha n i t has b uffer
space for on returns, an d does not initiate a cycle from the Hub Interface that it cannot
accept as a return. The bridge rules of the specification already allow the PCI-X
interface to retry split completions when the bridge is temporarily full.
Therefore, the split transaction control registers are not used by the Intel® 6300ESB
ICH.
18.8.10 Locked Transactions
The Intel® 6300ESB ICH is not locked until the target has completed at least the first
data phase as an Immediate Transaction or a Split Transaction (target signals Split
Response).
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18.8.11 Error Support
18.8.11.1General
As a PCI-X Target, the Intel® 6300ESB ICH bridge responds as specified in the PCI-X
Addendum.
18.8.11.2Special Parity Error Rule for Split Response
When the Intel® 6300 ESB ICH ca lcul ates a da ta pa rit y erro r whe n a ta rget s i gnals S pli t
Re sponse for a read tran saction, it reco rds the error as described in section 5. 4.1 of the
PCI/X 1.0 Specification. Furthermore, when the Intel® 6300ESB ICH is enabled to
assert PERR# on the secondary bus and enabled t o assert SERR# on the Hub Interface,
it generates NMI/SMI (depending on which is en abled).
18.9 Transaction Termination Translation
betw een In terfaces
Though Intel® 6300ESB ICH’s primary bus is the Hub Interface, from a register and
software perspective, the Hub Interface is a PCI-X bus and Intel® 6300ESB ICH is a
PCI-X bridge that supports a secondary bus configured as either PCI or PCI-X.
Section 8.7.1.5 of the PCI-X 1.0 Specification modified the behavior of a bridge from
that specified in the PCI to PCI bridge 1.1 spec regarding returning completions on the
pr ima r y bus when the s ec ond a ry bu s transa ct ion ter minates in e it her a mas te r ab or t or
target abort. In general, the PCI-X spec does not honor the Master Abort Mode bit for
cycles requiring completions, and returns to the primary bus the termination that
occurred on the secondary bus without any translation.
The following sections describe the behavior of the Intel® 6300ESB ICH on both the
Hub Interface and the PCI/PCI-X under various termination conditions. For specific
information as to why the Intel® 6300E SB ICH s PCI , P CI - X, or Hub I nte rf ace generates
a specific termination, see the specific sections on the interface above.
18.9.1 Behavior of Hub Interface Initiated Cycles to PCI/
PCI-X
Receiving Immediate Terminations
The behavior described for completion required cycles is independent of the setting of
the Master Abort Mode bit, and is independent of whether the cycle is exclusive
(locked) or not. The Intel® 6300ESB ICH returns all ’ 1 s on data bytes for a read
completion that terminates in either Master Abort or Target Abort.
Table 625. Immediate Terminations of Completion Required Cycles to PCI/PCI -X
PCI/PCI-X Term ination Hub Interface
Completion Status Register Bits Set
The Master Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus.
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18.9.2 Behavior of Hub Interface Initiated Cycles to PCI-
X Receiving Split Terminations
The behavior described in the following table is independent of the Master Abort Mode
bit and whether or not the cycle is exclusive (locked) or not. The Intel® 6300ESB ICH
returns all ’1’s on all data bytes for a read completion that terminates in either Master
Abort or Target Abort on the Hub Interface. Note that when a target or master abort is
returned on the Hub Interface, the attached PCI/PCI-X bus is not locked. This is of
special importance to the completion messages of “data parity error”, “byte count out
of range”, “write data parity error”, “device specific”, and reserved/illegal codes. The
Intel® 6300E SB ICH must not lock its bus on these errors, even thou gh they are not
explicitly master or target aborts on the PCI-X interface.
Successful Successful Master Data Parity Error (Sec)
Master Abort Mas ter Abort Received Mas ter Abort (Sec)
Targ et Abort Tar get Abo rt Received Target Abort (Sec )
Signal ed Target Abort (Pri)
Mast er Data Parity Err or (S e c)
Table 626. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
PCI/PCI-X
Termination MAM Bit Action Statu s Reg ister Bits Se t
Successful N/A None None
Master Abor t 1 Generate NMI/SMI Received Master Abort (Sec)
Signaled System Error (Pri)
Master Abort 0 None Received Master Abort (Sec)
Target Abort N/A Generate NMI/SMI
as enabled Received Target Abort (Sec)
Signaled System Error (Pri)
Table 625. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
The M aster Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus.
Tab l e 627. Sp lit T ermi nat i o ns of Comp le ti on Re q ui red C ycl es to PCI -X ( She et 1 of
2)
PCI-X Split
Termination
Message Hub Interface
Completion Status R egister Bits Se t
Class Index
Successful 0 00h Successful Ma ster Data Parity Err or (S e c),
when encountered
Master Abort 1 00h Master Abort Received Mas ter Abort (Sec)
Target Abort 1 01h Target Abort Received Target Abort (Sec)
Signaled Target Abor t (Pri)
Write Data Pari ty Error 1 02h Ta rg e t Abort Ma ster Data Parity Error (Se c)
Signaled Target Abor t (Pri)
Byte Count Out Of
Range 2 00h Target Abort Signaled Target A bort (Pri)
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18.9.3 Hub Interface Action on Immediate Responses to
PCI-X Split Completions
The following table indicates what the Intel® 630 0ESB ICH does when it is returning a
split completion to PCI-X from a normal Hub Interface completion, and receives an
immediate response indicating some kind of error.
Write Data Parity Error 2 01h Target Abort Master Data Parity Error (Sec)
Signaled Target Abort (Pri)
Device Specific 2 8X h Targe t A bor t Sig na le d Tar get A bort (Pri)
Reserved/Illegal Others Target Abort Signaled Target Abort (Pri)
Table 627. Split Terminati ons of Completion Requir ed Cycles to PCI-X (Sheet 2 of
2)
PCI-X Split
Termination
Message Hub Interface
Completion St atu s R e gister B its Set
Class Index
Table 628. Hub Interface Response to PCI-X Split Completion Terminations of
Completio n Required Cycles
Split Completion Termination Action Status Register Bits
Successful None None
Master Abort Assert SERR# Received Master Abort (Sec)
Split Completion Discarded (Sec)
Signa led Sys t em Erro r (Pri )
Target Abo rt Assert SERR# Rec eived Targ et Abor t (Sec )
Split Completion Discarded (Sec)
Signa led Sys t em Erro r (Pri )
In this case , the assertion of SER R# an d setting of the S ignaled System Error bit only occur whe n the
SERR# En abled in t he prim ary command register is s et.
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18.9.4 Behavior of PCI/PCI-X Initiated Cycles to Hub
Interface
18.10 Delayed/Split Transactions
18.10.1 Number Supported
When in PCI mode, tr ansactions follow the delayed tr ansaction model of PCI 2.2. When
in PCI-X mode, transactions follow the split tran saction model of PCI-X. For each
bridge, the Intel® 6300ESB ICH supports eight delayed / split transactions inbound,
and one delayed/split transaction outbound.
The Hub Interface may take four outbound delayed/split transactions, but only
launches one at a time to each PCI-X interface. Each PCI interface may take eight
delayed/split transactions, but only launches four of those transactions onto the Hub
Interface.
The outbound delayed/split transactions does not prefetch from PCI devices, regardless
of whether the transaction falls in the prefetchable window or the non-prefetchable
window. When in PCI mode, the inbound delayed/split transactions prefetch for all
command types. The “memory read” command may optionally have its prefetch turned
off as specified in the PCI bridge specification. When in PCI-X mode, the inbound
delayed/split transactions do not prefetch – they acquire only the byte count from the
request.
Table 629. Terminations of Completion Required Cycles to Hub Interface
Hub Interface Termination PCI Completion Status Register Bits Set
Successful Successful None
Mas te r Abor t (PCI) Targ e t A bo rt1Received M a ste r Abort (Pri)
Signaled Target Abort (Sec)
Master Abort (PCI-X) Split Master Abort2Rece ived M a ste r Abort (Pri)
Target Abort Target Abort (PCI)1
Split Target Abo r t (PCI -X) 2Received Tar get Abort (Pri)
Signaled Target Abort (Sec)
Master and Target Abort Target Abort (PCI)1
Split Target Abo r t (PCI -X) 2
Rece ived M a ste r Abort (Pri)
Received Target Abort (Pri)
Signaled Target Abort (Sec)
NOTES:
1. Th e Intel® 6300ESB ICH o nly signals Tar get Abort when the error has been logged from the
Hub Interface befor e the initial connect by PCI or when the PCI master reconnects after a
previo us disconn ect. When th e Inte l® 6300ESB ICH receives an abort on the Hub Interface in
the middle of a read completion stream it does not interrupt the str eam to sig na l Ta rg et
Abort.
2. The Intel® 6300ESB ICH issues a Split Completion Error Message with either Master Abort or
Targ e t Abort for th e remaining completion se q uence when an abort is detected on the Hub
Interface. Wh en s ev er al b ytes of dat a r eturned suc cess full y fro m the Hub Inte rface and h ave
not yet been sent back on PCI-X, when the abort is detected on the Hub Interface the Intel®
6300ES B ICH stops the cur re nt seq uen ce for that data (if it was running) and generates the
Split Completion Error Messag e .
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18.10.2 Prefetch Algorithm
Since outbound cycles are not prefetched, there is no algorithm. The algorithm for
inb ound cycl es is b el ow . Note th at the algor ithm changes d ep ending up on whe ther only
one device is requesting or multiple devices are requesting.
18.10.2.1Parameters
Parameters based upon the Prefetch Parameter Registers at offset F8h – FFh
Ri In itial request size ( b its[03:00])
Ti Initial threshold (bits[07:04])
Rs Subseque nt request (bits [11:08])
Ts Subsequent threshold (bits[15:12])
D Delay to wait between next Ts (calculated). The value is
“Rs : 11 1” c locks.
Other Algorithm Parameters
Sb Buff er siz e (either 1 K or 2K, dependi ng upon the del ay ed
tran saction bit (of fset 40h, b it 2 ) )
N Data in buffer + data in flight (requested to SiBUS but not
returned)
B Data in buffer
18.10.2.2Algorithm (Single Device Only)
1. Establish DT, launch request of size Ri. The actual amount fetched is such that the
transfer ends on a naturally aligned 128-byte line. When the initial address is less
than 64-bytes into the 128-byte line, the Ri value is rounded down (i.e., eight 64-
byte lines become seven 64-byte lines + remainder). When the initial address is
more than 64-bytes into the 128-byte line, the Ri value is rounded up (i.e., eight
64-byte lines become nine 64-byte lines + remainder).
Example 1: Ad d r e ss sta rts at 32 b ytes in to a 128-b yte line, and the fetch
length is 4*64 by te lines (256 by te s ). T h e am ount fet c he d is 2 56 - 32 =
224 b ytes (56 d Words).
Example 2: Addres s st arts at 96 bytes into a 128-byte line, and the fetch
length is 4*64-byte lines (256 bytes). The amount fetched is 256 + (128 -
96) = 288 bytes (72 dWords).
2. Wait until at least some data has returned and master has reconnected. In PCI
mode, this is when the first qWord becomes available. In PCI-X, when not running
in 133 MHz mode, or running in 133 MHz mode but the request size is less than or
equal to 256 bytes, this is when the first ADB becomes available.
3. When N < Ti, launc h a req uest of si ze R s (trunc at ed by Sb, wh en neces sa ry). Start
Timer when there are not more active delayed transactions. When there are other
active delayed transactions, go to step 5.
4. Check for size B vs. Ts
When B < Ts, wait for timer to expire before lau nc h of size Rs. Restart
tim e r. Go to Ste p 4.
When B > Ts be fo re ti mer expires, reset timer. Go to Step 5.
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5. Wait for B < Ts; launch request of size Rs (truncated by Sb, when necessary).
Restart timer. Go to ste p 4.
18.10.3 Algorithm (Multiple PCI-X Devices Requesting)
When multiple agents are requesting in PCI-X mode, the definition of TS chan ges.
Instead of just indicating data in b uffer, it becomes like TI, and represents data in
buffer plus data in flight. When multiple agents are requesting in PCI-X mode, the
Intel® 6 300ESB ICH nee ds to switch be twe en these agent s for compl etions. It does this
by utilizing its MLT parameter. When the MLT expires, it stops this stream and switches
to another stream.
Differences from P64H algorithm:
No connect threshold: as soon as the first data is available in the DT buffer, a PCI
device is allowed to connect.
Allows multiple outstanding reads per DT buffer, (so long as restrict size of all
outstanding reads for a DT buffer to remaining capacity in DT buffer), yielding
smaller p refetch overshoot
Periodic subsequent fetch: smaller, more frequent requests reduce prefetch
overshoot
TI and TS as a low watermark takes into account data in flight; not just data
remaining in the DT buffer
Delayed subsequent launch for multi-stream operation to reduce prefetch
overshoot
First subsequent launch threshold
18.10.4 Accesses From Multiple Agents to Same 4K Page
I n order to avoid the need to track the status of the buffers when multiple agents are
asking for data from the same 4K page, the Intel® 6300ESB ICH retries a PCI master
when the same PCI master has already established another delayed transactio n to that
4K p age.
18.11 Intern al Bus/D evice Com mu nica tion
Internally, all devices that reside on the “logical PCI bus” are connected to an internal
bus called “SiBus” (silicon bus). This is a bus architecture developed within PCG that
allows for high code reuse and the ability to connect multiple units together in a
standard manner. It is split transaction based.
By choosing this micro-architecture, cycles may originate from any agent and be
decoded by any other agent. This allows peer-to-peer communication to effectively be
free. For this reason, the SM Bus controller is also connected to this bus, allowing PCI
configuration cycles that originate either from the Hub Interface or SM Bus to use the
same data and control paths to access internal registers.
However, this must be monitored carefully by the micro-architecture. Configuration
cycles from SM Bus must be allowed to reach their destination, even when the Hub
Interface communication to one of the PCI busses is blocked due to a deadlock
condition.
Therefore, the micro-architecture must ensure the following:
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All units that have a configuration space that could be accessed by SM Bus have a
“1 command only” depth. This helps ensure that multiple requests are not
outstanding, minimizing any possibility of SM Bus accesses being stuck.
The Intel® 6300ESB ICH does not launch successive requests that have the same
hub ID/pipe ID on the internal b us, ensuring that no space has to be reserved to
re-order the completion data. Only cycles that have a unique hub ID/pipe ID may
be launched simultaneously, and their completions may return in any order.
Any r equ est fr om SM Bus (o r the Hub Interf ace ) tha t tar gets the I/O xAPIC mus t b e
able to complete, even when the I/OxAPIC has an interrupt to deliver to the Hub
Interface. Otherwise, the completion for the SM Bus/Hub Interface access is
blocked behind the I/OxAPIC request to the Hub Interface, and it does not finish.
System management software must ensure that the SM Bus does not generate
accesses PCI. When this occurs and PCI is blocked, the SM Bus is blocked.
18 .12 Data Re turn Behavior of Hub Inter face
Initiated Reads
For all Hub Interface initiated memory read cycles targeting PCI/PCI-X, the Intel®
6300ES B ICH ensu res a retu rn l eng th of a na tur all y al ign ed 12 8-byt es . When a re quest
is less than 128 bytes and within a single 128-byte line, the Intel® 6300ESB ICH
generates one completion. When the request crosses a line, the Intel® 6300ESB ICH
retu rns mul tiple co mp letio n s, broken on 128-by te line boun da ries , until the r eques t is
fulfilled.
The Intel® 6300ESB ICH does not return a dWord completion on a memory read
command that is longer than a dWord and is qWord aligned.
The Intel® 6300ESB ICH only gener ates qWord aligned reads whose length is a multiple
num ber of qWords . The Intel® 6300ESB ICH requires that the completions for these
requests be returned as qWords and never dwords. For read streaming to work, the
Intel® 6300ESB ICH requires that the driving agent only disconnect read completions
on a cache line boundary (64 or 128 bytes).
18.13 Performance Targe ts
18.13.1 Introduction
This information is organized into three sections. The first section specifies general bus
timings. The second specifies single active master throughputs. The third specifies
concurrent performance when multiple agents are generating requests from both
busses.
18.13.2 Def initions and Assumptions
Band wid th test s ar e s ustai ned throu gh put t ests . The sy stem m ay be r un unti l it r eache s
steady state and then run longer with the bandwidth measured.
The system under test uses 4x, 8 bit, HL 1.5.
Memory bandwidth in the system under test is sufficient to service the requirements of
the PCI-X so that contention for memory and other system resources is not a
performance bottleneck.
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R ef erenc es to si gna l tim ings are sta ted fr om the poi nt of vie w of the bu s itse lf. Intern al
register timings of the individual devices are not considered.
One Megabyte =106 Bytes rather than 220 Bytes.
18.13.3 Active Master Cloc k Counts
This section specifies clock counts for general bus timings and first word latencies for
read requests. Bus timings should be consistent regardless of other system activity.
First word latency specifications only apply in situations where contention for system
resources does not present a performance bottleneck.
First word latency is measured as the number of clocks from the initial assertion of
PXFRAME# (this is clock 0) to the first clock on which valid data is returned in response
to the request.
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Serial I/O Unit 19
The SIU is similar to currently available Super I/O controllers. It is specifically designed
for i nteg ra tion i nto the Intel ® 6300E SB ICH . It is conne cted externa l ly thr ough the LPC
bus and consists of two UARTS, a Serial Interrupt Controller, Port 60/64 Emulation and
the LPC interface.
19.1 Features
LPC Interface
Multiplexed command, address and data bus
8-Bit I/O transfers
16-Bit address qualification for I/O transactions
Serial IRQ interface compatible with serialized IRQ support for PCI systems
Note: Each SIU port must use a dedicated interrupt. SIU interrupts cannot be shared with
each other or with other devices.
Se ria l Port
Two serial ports
Note: The serial ports of the Intel® 6300ESB ICH are not completely compatible with other
16550 standard devices. A system or software designer must follow the specifications
laid out in this document above standard 16550 specifications.
Configurable I/O addresses and interrupts
16-Byte FIFOs
Supports up to 115 Kbps
Programmable baud rate generator
Modem control circuitry
Port 60/64 Emulation
Configurable unit disable
P ositive decode for I/O cycles to 60h and 64h
Read/Write scratchpad registers only (sticky bits)
Configurable interrupt generation on writes to either register
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19.2 Pin Description
19.2.1 Universal Asynchro nou s Receive An d Transmit
(UART0, UART 1)
Figure 32. SIU Block Diagram
Table 630. Universal Asynchronous Receive And Transmit (UART0, UART1)
(Sheet 1 of 2)
Signal N am e T ype Description
UART_CLK I Input clock to the SIU. Th is clock is passe d to t he ba ud clock
gener atio n logic of each UA RT in the SIU.
SIU0_RXD,
SIU1_RXD ISERIAL INPUTs for U ART0 and UART1: Serial data input from
device pin to the re ceiv e port.
SIU0_TXD,
SIU1_TXD OSERIAL OUTPUT for UART0 and UART1: Serial d ata output to the
communication perip he ral/mod e m or d a ta se t. Up on reset, the TXD
pins will be set to M AR K ING c ondition (logic ‘1’ state ).
LP C I/F Registers
Control
APB I/F
SIRQ
Controller
PORT 60/64 UART0
Emulation UART1
SIU_SERIRQ
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SIU0_CTS#,
SIU1_CTS# I
CLEAR TO SEND: Act ive low, this pin indicate s that d ata may be
exchanged between the Intel® 6300ESB ICH and external interface.
These pin s have no effect on the tra nsmi t ter.
NOTE: These pins could be used as Modem Status Input whose
condition may be tested by the pr ocessor by reading bit 4
(CTS ) of the Mode m S ta tus reg ister (MSR). Bi t 4 is the
comp le me nt of the CTS# sign al. B it 0 (D CTS ) of the MSR
indicates w hether the CTS# inp u t h as change d sta t e since the
prev ious read ing of the MSR. When the CTS bi t of the MS R
changes state an interrupt is generated if the Modem Status
Interrupt is enabled.
SIU0_DSR#,
SIU1_DSR# I
DATA SET READY for UART0 and UART1: Active low, this pin
indicat es tha t the exte rnal ag e nt is rea d y to communicate with the
Intel® 6300ESB ICH UARTs. These pins have no effect on the
transmitter.
NOTE: These pins could be used as Modem Status Input whose
condition may be tested by the pr ocessor by reading bit 5
(DSR) of the Mod em Status register. Bit 5 is the complement of
the DSR# sign al. B it 1 (DDS R) of the Modem status register
(MSR) indicates whether the DSR# input has changed state
since t he previou s readin g of the MSR. When t he DSR bi t o f the
MSR chang e s st a te an interrupt is generated if the Mode m
Status Interrup t is ena bled.
SIU0_DCD#,
SIU1_DCD# I
DAT A CARRI ER DE TECT for UART0 and UAR T1: A ctiv e low, this
pin indicates that data carrier ha s be en dete cted by the exte rnal
agent.
NOTE: These pins are Modem Stat us Input whose conditio n may be
tested by the processor by reading bit 7 ( DCD) of the Modem
Status register (MSR). Bit 7 is the complement of the DCD #
signal. Bit 3 (DDCD) of the MSR indicates whether the DCD#
input has changed state s ince the previ ous reading o f the MSR.
When the DCD b it of the MSR chang e s from a ’1’ to 0, an
interr up t is generate d if the Mod e m St a tus Interrupt is
enabled.
SIU0_RI#
SIU1_RI# I
RING INDICATOR for UART0 and UART1: Ac tive low, this pin
indicates that a telephone ringing signal has been received by the
external agent.
NOTE: These pins are Modem Stat us Input whose conditio n may be
tested by the processor by reading bit 6 ( RI) of the Modem
Status register (MSR). Bit 6 is the complement of the RI#
signal. Bit 2 (T ERI) of the MSR indicates whether the RI# input
has transition back to an inactive state. When the RI bit of the
MSR chang e s st a te an interrupt is generated if the Mode m
Status Interrup t is ena bled.
SIU0_DTR#,
SIU1_DTR# O
DATA TER MI N AL READY for UART0 an d UART1: When low these
pins inform s the mod e m or data set that the Inte l® 6300ES B ICH
UART0 and UART1 are re a d y to estab lish a comm u nication link . The
DTR#x(x= 0,1) outp ut signals may be set to an a ctive low by
programming the DTRx (x-0,1) (bit0) of the Modem control register to
a logic ‘1 . A Reset opera tion se ts this signa l to its in a ctiv e st ate (logic
‘1’). LO OP mod e operation hold s th is signal in its ina ctiv e stat e .
SIU0_RTS#,
SIU1_RTS# O
REQUEST TO SEND for UART0 and UART1: When low these pins
inform s the modem or data set tha t Intel® 6300E SB ICH UART0 and
UART1 are ready to establish a communication link. T he
RTS#x(x=0 ,1) output signals may be set to an active low by
programming the RTSx (x-0,1) (bit1) of the Modem control register to
a logic ‘1 . A Reset opera tion se ts this signa l to its in a ctiv e st ate (logic
‘1’). LO OP mod e operation hold s th is signal in its ina ctiv e stat e .
Table 630. Universal Asynchronous Receive And Transmit (UART0, UART1)
(Sheet 2 of 2)
Signal Nam e Ty pe Description
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19.3 Functional Description
19.3.1 Host Processor Interface (LPC)
The host processor communicates with the SIU through the LPC bus. Access is through
a series of read/write registers and accomplished through I/O cycles or DMA transfers.
All registers are 8 bits wide. The SIU registers include global configuration space and
device specific regions accessed by setting the Logical Device Number in the SIU
Configuration Register 07H (SCR7). See Table 631.
See Sectio n 19.8, “Conf igura tion” for configuration register descriptions and setting the
base address.
19.4 LPC Interface
The LPC interface is used to control all the logical blocks on the SIU. LPC bus signals
use PCI 33 MHz electrical signal characteristics. Refer to the Low Pin Count (LPC)
Interface Specification, Rev 1.0.
19.4.1 LPC Cycles
The following cycle types are supported by the LPC protocol.
The SIU ignores cycles that it does not support.
19.4.1.1 I/O Read and Write Cycles
The SIU i s the target for I/O cycles. I/O cycles are initiated by the host for register or
FIFO accesses and will generally have minimal Sync times.
Data transfers are assumed to be exactly 1-byte. If the processor requested a 16- or
32-bit transfer, the host must break it up into 8-bi t transfers.
See the Low Pin Count (LPC) Interface Specification for th e seq uenc e of cycl e s fo r the
I/O Read and Write cycles.
Table 631. Address Map
Address Block N am e Log ical Device
04 Eh Conf ig ura tion Ind e x
04 Fh Configuration Data
Base+(0-7) Serial Port Com 1 04H
Base+(0-7) Serial Port Com 2 05H
060h/064h Port 60/64 Emulation 07h
Table 632. Supported LPC Cycle Types
Cycl e Type Transfer Size
I/O Write 1 Byte
I/O Read 1 Byte
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19.4 .2 Rese t Policy
The following rules govern the reset policy:
The SIU reset (active low) is internally tied to the PCI bus reset.
When the SIU reset goes active (low):
The host drives the LFRAME# signal high, tristates the LAD [3:0] sig nals, and ignores the
LDRQ# signal.
The S IU ignores L FRAME#, tristates the L AD[3:0] pins and driv es the SIU’s LDRQ# signal
inac tive (hig h ).
Note: LPC bus signals from SIU are tied to primary LPC interface external to the Intel®
6300ESB ICH device. Host LPC and SIU LPC names are used interchangeably
throughout.
19.4 .3 LP C Transfers
19.4.3.1 I/O Transfers
These will generally be used for register or FIFO accesses, and will generally have
minimal Sync times. The minimum number of wait-states between bytes is 1. Data
transfers are assumed to be exactly 1 byte. The host is responsible for breaking up
larger data transfers into 8 bit cycles.
19.5 Logical Device 4 and 5: Serial Ports (UARTs)
This section describes the Universal Asynchronous Receiver/Transmitter (UART) serial
port used for the two UARTs integrated into the SIU. The UART may be controlled
through programmed I/O. The basic programming model is the same for both UARTs
with the only difference being the Logical Device Number assigned to each.
19.5.1 Overview
The serial port consists of a UART which supports all the functions of a standard 16550
UART including hardware flow control interface.
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device or a modem and parallel-to-serial conversion on data characters
received from the processor. The processor may read the complete status of the UART
at any time during the functional operation. Available status inf o rmation includes the
type and condition of the transfer operations being performed by the UART and any
error conditions (parity, overrun, framing, or break interrupt).
Table 633. I/O Sync Bits Description
Bits Indication
0000 Sync Achie ved with no e rror.
0101 Indic ate s that Sync not Achi eved yet , but the part is d riv ing the bus .
0110 Indicates that Sync not Achieved yet, but the part is driving the bus, and expect
long Sync.
1010 Special Case: Pe rip h e ral indicating errors.
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The serial port may operate in either FIFO or non-FIFO mode. In FIFO mode, a 16-byte
transmit FIFO holds data from the processor to be transmitted on the serial link and a
16-byte Receive FIFO buffers data from the serial link until read by the processor.
Each UART includes a programmable baud rate generator which is capable of dividing
the baud clock input by divisors o f 1 to (2 16 -1) and producing a 16X clock to drive the
internal transmitter and receiver logic. Each UART has complete modem control
capability and a processor interrupt system. Interrupts may be p rogrammed to the
use r' s req ui reme nts, mi nim izi ng the com puti ng re quire d to ha nd le th e com muni ca tions
link. Each UART may operate in a polled or an interrupt driven environment as
configured by software.
The baud rate generator input is a function of the UART_CLK and a configurable pre-
di vide of 1, 8, or 26. See als o SIU Config ura tion (add ress 29h) in Table 656. The ou tpu t
of the baud rate generator is 16 times the baud rate.
19.5.1.1 UART Feature List
Adds or deletes standard asynchronous communications bits (start, stop, and
parity) to or from the serial data
Independently controlled transmit, receive, line status and data set interrupts
Programmable baud rate generator allows division of clock by 1 to (216 -1) and
generates an internal 16X clock
Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#)
Fully programmable serial-interface characteristics:
Table 634. UART Clock Divider Support
Clock Frequency 14.7456 MHz 48.0 MHz
Pre-Divide Value 826
Generator Frequency 1.8432 MHz 1 .8462 MH z
Note: Some clock chips provide a 14.318x MHz clock output. The Intel® 6 300ES B I CH’s UAR T
clock must use a 14.7456 MHz frequency; most clock chips do not provide this
frequency. An option will be to use the 48.0 MHz clock.
Table 635. Ba ud Rate Examples
Desired Ba ud Rate
UART Clock
Frequency 14.7456
MHz UAR T Clock Freque ncy 48 MHz
Divisor Divisor % err o r
1200 768 2500 0.16
2400 384 1250 0.16
4800 192 625 0.16
7200 128 417 0.16
9600 96 312 0.16
19200 48 156 0.16
38400 24 78 0.16
56000 16 54 3
115200 8 26 0.16
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5, 6, 7 or 8-bit characters
Even, odd, or no parity detection
1, 1-1/2, or 2 stop bit generation
Baud rate generation (up to 115kbps)
False start bit detection
16-byte Receive FIFO
Complete status reporting capability
Line break generation and detection
Internal diagnostic capabilities include:
Loopback controls for communications link fault isolation
Brea k , parity, overrun , an d framing e rror simulation
Fully prioritized in te rrupt system con trols
19.5.1.2 UART Operational Description
The format of a UA RT data frame is shown in Figure 33.
Each data frame is between 7 bits and 12 bits long depending on the size of data
programmed, if parity is enabled and if two stop bits are selected. The frame begins
with a sta rt b it th at i s r eprese nt ed by a hi gh to l ow transiti on . Next , ei ther 5 to 8 bi ts of
data are transmitted, beginning with the least significant bit. An optional parity bit
follows, which is set if even parity is enabled and an odd number of ’1’s exist within the
data byte, or if odd parity is enabled and the data byte contains an even number of1’s.
The data frame ends with one, one and a half or two stop bits as programmed by the
user, which is represented by one or two successive bit periods of a logic ’1.
The unit is disabled upon reset, the user needs to enable the unit by setting bit 6 of
Interrupt Enable Register. When the unit is enabled, the receiver starts looking for the
start bit of a frame; the transmitter starts transmitting data to the transmit data pin if
there is data available in the transmit FIFO. Transmit data may be written to the FIFO
before the unit is enabled. When the unit is disabled, the transmitter/receiver finishes
the current byte being transmitted/received if it is in the middle of transmitting/
receiving a byte and stops transmitting/receiving more data.
An SIU reset will force the internal register and output signals on the serial port to the
values listed in Table 636.
Figure 33. Example UART Data Frame
Star
t
Bit
Dat
a<0
>
Dat
a<1
>
Dat
a<2
>
Dat
a<3
>
Dat
a<4
>
Dat
a<5
>
Dat
a<6
>
Dat
a<7
>
Parit
y Bi t Stop
Bit 1 Stop
Bit 2
TXD3 or RXD3
pin
LSB MSB
Rece ive data sample cou nter frequency = 16x bit frequen cy, each bit is sampled t hree times in the mi ddle.
Shaded bits are opt ion al and m ay be p rogrammed by users.
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
710 Order Number: 300641-004US
19.5.1.3 Internal Register Descriptions
There are 12 registers in the UART. These registers share eight address locations in the
I/O address space. Table 637 shows the registers and their addresses as offsets of a
base address. Note that the state of the Divisor Latch Bit (DLAB), which is the MOST
significant bit of the Serial Line Control Register, affects the selection of certain of the
UART registers. The DLAB bit must be set high by the system software to access the
Baud Rate Generator Divisor Latches.
Table 636. SIU Signal Rese t States
Register/Signal Res et Control Reset State
Interrup t Enable Register RESET All bits are low.
Interrup t ID Register RESET Bit 0 is force d high. Bits 1-3 an d 6-7 are f orced
low. Bits 4-5 are permanently low.
Line Control Register RESET All bits are forced low.
Line Status Register RESET Bits 0-4, and 7 are forced low. Bits 5 and 6 are
forced high.
Modem Control Register RESET Bits 0, 1, 2, 3, 4 are fo rce d low. Bits 5, 6, an d 7
are permanently low.
Modem Stat us Register RE SET/M o dem signal ,
read MSR for bits 3-0. Low
SIU0_TXD
SIU1_TXD RESET High
SIU_SERIRQ RESET/ clear LINE
STATUS REG Low
SIU0_RTS#
SIU1_RTS# RESET High
SIU0_DTR#
SIU1_DTR# RESET High
Table 637. Internal Register Descriptions
UART Register
Addresses
(Base + offset)
DLAB Bit
Value Register Accessed
Base 0 Receive BUFF ER (read only)
Base 0 Transmit BUFFER (write only)
Bas e + 01H 0 Interrupt Enabl e (R/W)
Bas e + 02H X Interru pt I.D. (read only)
Bas e + 02H X FIFO Control (write only)
Bas e + 03H X L in e Contro l (R/ W)
Bas e + 04H X Modem Control (R/W)
Bas e + 05H X Line Status (Read only)
Bas e + 06H X Modem Status (Read only )
Bas e + 07H X Scratch Pad (R/W)
Base 1 Divisor Latch (Lower Byte, R/W)
Bas e + 01H 1 Divisor Latch (Upp er Byte, R/W)
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19.5 .1.3.1 R ec eive Buffe r Registe r (R BR)
In non-FIFO mode, this register holds the character received by the UAR T's Receive
Shift Register. If fewer than eight bits are received, the bits are right-justified and the
leading bits are zeroed. Reading the register empties the register and resets the Data
Ready (DR) bit in the Line Status Register to 0. Other (error) bits in the Line Status
Register are not cleared. In FIFO mode, this register latches the value of the data byte
at the top of the FIFO.
19.5.1.3.2 Transmit Holding Register (THR)
This register holds the next data byte to be transmitted. When the Transmit Shift
Register becomes empty, the contents of the Transmit Holding Register are loaded into
the shi ft registe r and the tr ans mi t data request (TDRQ ) bit in the Li ne S tatus Re gi ster is
set to ’1.
In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom
of the FIFO is loaded to the shift register when it is empty.
19.5.1.3.3 Interrupt Enable Register (IER)
This register enables five types of interrupts which independently activate the int signal
and set a value in the Interrupt Identification Register. Each of the five interrupt types
may be disabled by resetting the appropriate bit of the IER register. Similarly, by
setting the appropriate bits, selected interrupts may be enabled. Receiver time out
interrupt may be configured to be separated from the receive data available interrupt
(using the bit5: COMP) to avoid interrupt controller and DMA controller serving the
receive FI FO at the same time.
Note: T he use of bit 4 and 5 is different from the register definition of standard 16550.
Tab l e 63 8. R ec ei ve Bu ff e r Re gi st e r (R BR )
Recei ve Buffer Register
RBR
read only
Address:
Reset State:
Access:
Base (DLAB=0)
00H
8-bit
Bit
Number Bit Mnemonic Function
7:0 RB[7:0] Data b yte rece iv e d, leas t sig nif ican t b it f irst.
Table 639. Transmit Holding Register (THR)
Tran s m it H o lding Regist er
THR
writ e o nl y
Address:
Reset State:
Access:
Base (DL A B= 0)
00H
8 bi t
Bit Number Bit Mnemonic Function
7: 0 T B [7:0] D ata b yte tran sm itte d, lea st sig nif icant bit first.
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
712 Order Number: 300641-004US
19.5.1.3.4 Interrupt Identification Register (IIR)
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels (listed in Table 641) and records these in the
Interrupt Identification Register. The Interrupt Identification Register (IIR) stores
information indicating that a prioritized interrupt is pending and the source of that
interrupt.
Table 640. Interrupt Enable Register (IER)
Interrupt Enable Register
IER
read/write
Address:
Reset State:
Access:
Bas e + 01H (DLAB=0)
00H
8-bit
Bit Number Bit Mnemon ic Func tion
7:6 RSVD RSVD = 0
5COMP
Compatibility Ena ble:
0 = Bit 0 of this registe r also c ontrols RTOIE and bit 4 is RSVD.
1 = Bit 4 of this register controls RTOIE.
NOTE: The use of bit 5 is different from the register defi nition
of the 16550. The 16550 has this bit always set to 0.
4RTOIE
Receiv er Time Out Interr up t Enable :
0 = Receiver data Time out inte rrupt disabled .
1 = Receiver data Time out inte rrupt enable d .
NOTE: The use of bit 4 is different from the register defi nition
of the 16550. The 16550 has this bit always set to 0.
3MIE
Mo dem Interrupt Ena ble:
0 = Modem Status interrupt disabled.
1 = Modem Status interrupt enabled.
2RLSE
Rece iver Line Status Interrupt Enable:
0 = Receiver Line Status interrupt disa bled .
1 = Receiver Line Status interrupt enable d .
1TIE
Trans mit Data request In terru pt Enab le:
0 = Transmit FIFO Data Request interrupt di sabled.
1 = Transmit FIFO Data Request interrupt enabled.
0RAVIE
Receiver Data Available Interrupt Enable:
When BIT 5 = 1
0 = Receiver Data Available (Tri gger le vel re a che d ) in te rrupt
disabled.
1 = Receiver Data Available (Tri gger le vel re a che d ) in te rrupt
enabled.
When BIT 5 = ’0’ the following additional functionality is used.
0 = Receiver data Time Out Inte rrup t a lso disabled.
1 = Receiver data Time Out Interrupt enable d .
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Table 64 1. Interrupt Conditions
Priority
Level Inter rupt Or igin
1 (highest) R eceiv er L in e Status: One or more error bits were set.
2Received Da ta is availa b le . In FIF O mod e , trig g e r leve l was re a che d ; in non -FIFO
mode, RBR has d ata.
2Receiver Time out occurred. It hap p e ns in FIFO mode only, when there is data in
the receive FIFO b ut no activity for a time per iod .
3Transmi tte r re qu es ts da ta. In FIFO mod e , the tran smi t FI FO is half or more than
half em pty; in non -FIFO mode , THR is read a lre ady.
4Modem Status: One or m ore of the modem input signa ls h a s changed st at e .
Table 642. Interrupt Identification Register (IIR)
Interru pt Identif ica tion
Register
IIR
read-only
Address:
Reset State:
Access:
Base + 02H
01H
8-bit
Bit
Number Bit Mnemonic Function
7:6 FIFOES[1:0]
FIFO Mode Enable Status:
00 = Non-FIFO mod e is selecte d .
01 = Reserved
10 = Reserved
11 = FIFO mode is s el ecte d (TRFIFOE = 1).
5:4 -- Reserved
3TOD
(IID3)
Time Out Detected:
0 = No time out in te rrupt is pending.
1 = Time out inte rru p t is p e nding. (FIFO mode on ly )
2:1 IID[2:1]
Interru pt Sourc e Enc oded:
00 = Modem S tatus (CT S, DS R, RI, DCD modem signals
cha nged stat e)
01 = Transmit F IFO requests data.
10 = Received Da ta Available
11 = Receive error (Overrun, parity, framing, break, FIFO error)
0IP# Interru pt Pendi ng :
0 = Interrup t is p e ndi ng. (Ac tive low)
1 = No interrupt is pending.
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
714 Order Number: 300641-004US
19.5.1.3.5 FIFO Control Register (FCR)
FCR is a write only register that is located at the same address as the IIR (IIR is a read
only register). FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Note: The use of bit 6 and 7 is different from the register definition of standard 16550.
Table 643. Interrupt Identification Register Decode
Interrupt
ID bits Interrupt SET/RESET Function
3210Priority Type Source RESET Control
0001-None No Interrupt is pending. -
0110Highes
tReceiver
Line Status Ove rrun Error , Parity Error,
Framin g Error, B reak Interrupt . Re ading t he L ine Status Register.
0100Secon
d
Highes
t
Received
Data
Available.
Non-FIFO mode: Receive
Buffer is full. Non-FIFO mode: Reading the
Receiver Buffer Register.
FIFO mod e : Trigger level
was reac he d.
FIFO mode: Reading bytes until
Receiver FIFO dr o ps belo w tri gg er
level or setting RESETRF bit in FCR
register.
1100Secon
d
Highes
t
Character
Timeout
indication.
FIFO Mode only: At least one
character is in receiver FIFO
and there was no activity for a
time period.
Readin g the Receiver FIFO or
s ettin g R ESET RF bi t i n FC R re gist er.
0010Third
Highes
t
Transmit
FIFO Data
Request
Non-FIFO mode: Transmit
Holding Register Empty Reading the IIR Register (if the
source of the interrupt) or writing into
the Transmit Holding Register.
FIFO mod e: Transmit FIFO
has half or less than half
data.
Reading the IIR Register (if the
source of the interrupt) or writing to
the Transmitter FIFO.
0000Fourth
Highes
t
Modem
Status
Clear to Send, Data Set
Ready, Ring I ndicator,
Received Line Signal Detect
R eadi n g the modem stat us
register
Table 644. FIFO Control Register (FCR) (Sheet 1 of 2)
FIFO Contro l Reg ister
FCR
write-only
Address:
Reset State:
Access:
Base + 02H
00H
8-bit
Bit
Number Bit Mnemonic Function
7:6 ITL[1:0]
Interrupt Trig ger Level: When the number of bytes in the
rec eive r FIFO equals th e interrupt trigger le vel pro grammed into
this field an d the Received Data Available In te rrupt is enabled
(through IER), an interrup t is generated and appropriate bits are
set in the IIR.
00 = 1 byte or more in FIFO causes interrupt (same as 16550).
01 = RSVD
10 = 8 bytes or more in FIFO causes interrupt and DMA request
(same as 16550 ).
11 = RSVD
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19.5.1.3.6 Line Control Register (LCR)
In the Line Control Register (LCR), the system programmer specifies the format of the
async hronous data comm unications exch ange. Th e s erial da ta forma t consis ts of a sta rt
bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits
(logic 1). The LCR has bits for accessing the Divisor Latch and causing a break
cond ition. T he prog rammer ma y also r ead the co ntents of the Line Contro l R egis ter. The
read capability simplifies system programming and eliminates the need for separate
sto rag e in syst em memo ry.
5:3 Reserved
2RESETTF
Rese t Transmitter FIFO: When RESETTF is set to 1, the
t ransmitte r FIFO counte r logic is set to 0, e f fectively clearin g a ll
the byte s in t he FIFO . The TDRQ bit i n LS R a re s e t and IIR s hows
a transm itte r req u e sts data interrupt if the TIE bit in the IER
register is set. Th e transmitte r shift regis te r is not cleare d; it
comp le te s the current transmis sion. After the FIFO is cle are d,
R ESETTF is au tomatically re set to 0.
0 = Writing ’0’ has no effect.
1 = The tr ansmitter FIFO is cleared (FIFO counter set to 0). After
cle aring , bit is automatically reset to 0.
1 RESETRF
Reset Rece iver FIFO: When RES E TRF is set to 1, the re ceiver
FIFO counter is reset to 0, eff ectively clearing all the bytes in the
FIFO . The DR bit in LS R is reset to 0. All the error bits in the FIFO
an d the FIFOE bit in LSR a re clea red . A ny error bits , OE, PE, FE
or BI, that had been set in LSR are still set. The receiver shift
register is not cleared. If IIR had been set to Received Data
Available, it is cle are d . Afte r th e FIFO is cle are d , R ESET RF is
au toma tically rese t to 0.
0 = Writing ’0’ has no effect.
1 = The r eceiver FIFO is cleared (FIFO counter set to 0). After
cle aring , bit is automatically reset to 0.
0TRFIFOE
Transmit and Receive FIFO Enable: TRFIFOE enables/disables
th e transm itter a nd re ce iver FIFO s. Whe n TRFIFOE = 1, both
FIFOs are enabled (FIFO Mode). When TRFIFOE = 0, the FIFOs
are both disabled (non-FIFO Mode). Writing a ’0’ to this bit clears
all bytes in both FIFOs. Wh en changing from FIFO mode to non-
FIFO mode and vice versa, data is automatically cleared from the
FIFOs. This bit must be 1 when other bits in this register are
writte n or the othe r b its ar e not progra mmed.
0 = FIFOs are disabled.
1 = FIFOs are enabl e d.
Table 644. FIFO Control Register (FCR) (Sheet 2 of 2)
FIFO Control Register
FCR
write-only
Address:
Reset State:
Access:
Base + 02H
00H
8-bit
Bit
Number Bit Mnemonic Function
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Intel® 6300ESB I/O Controller Hub
DS November 2007
716 Order Number: 300641-004US
Table 645. Line Control Register (LCR) (Sheet 1 of 2)
Serial Line Control Register
LCR
read/write
Address:
Reset State:
Access:
Base + 03H
00H
8-bit
Bit Number Bit Mnemonic Function
7DLAB
Divi sor R egi ster Acce s s Bi t: This bit is the Divisor Latch Access
Bit. It mus t be set hig h (log ic 1) to acc es s the Divisor Latches of
the Baud Rate Generator d uring a REA D or WRIT E op eratio n. It
must be set low (logic 0) to acce ss the Receive r Bu ffe r, the
Transmit Holding Register, o r the Inter rupt Enable Registe r.
0 = Acce ss Transmit Hold in g register (THR) , Receive Buf fer
Register (RBR) and Interrup t Enable Register.
1 = Access Divisor Latch Registers (DLL and DLM)
6SB
Set Break : This bit is the set break control bit. It causes a break
condition to be tr ansmitted to the receiving UAR T. When SB is set
to a logic 1, the serial output (TXD) is forced to the spacing (logic
0) sta te and re ma ins there un til S B is set t o a logic 0. This bit
acts only on the TXD pin and has no eff ect on the transmitter
logic.
This feature enables the processor to ale rt a terminal in a
co mp u te r communications sy st e m. I f th e following se q u e nce is
executed, no erroneous characters will b e transmitted because of
the break:
L oa d 00H in the Transmit Ho lding regis te r in res p onse to a
TD RQ in terrupt
After TD RQ goes high (indicating that 00H is being shifted
out), set the break bit before the parity or stop bits reach the
TXD pin
Wait for the transmitte r to be idle (TEMT = 1) and clear the
break b it whe n normal transmission ha s to be restored
During the break, the tran smitter may be used as a character
timer to accurate ly esta b lish the b re ak dura tion. In FIFO mode,
wait for the transmitter to be idle (TEMT=1) to set and clear the
break bi t .
0 = No effect on TXD output.
1 = Force s TXD outp ut to ’0’ (sp ace).
5STKYP
Sticky Parity: Thi s bi t is the “stic ky p a rity ” bi t, which may b e
used in mu ltiproce ssor com mun ications. Whe n PE N and STKYP
are logic 1, the b it that is transmitted in the parity bit locatio n
(the bit jus t before the stop b it) is the complement of the EPS
bit.
If EPS is 0, the bit at the parity bit location will be transmitted as
a 1. In the receiver, if STKYP and PEN are 1, the receiver
comp a res the bi t tha t is rece iv ed in the parity bit location with
the c omplem ent o f t he EP S bit . If th e v a lu es bei ng c o mp ared are
not equal, the receiver sets the P arity Error bit in LSR and causes
an error in ter rupt if line status inte rrupts we re en a bled. For
example, if EPS is 0, the receiver expects the bit received at the
parity bit location to be 1. If it is not, then the pari ty error bit is
set. By forcing the bit value at the parity bit location, rather than
calculating a parity value, a system with a master transmitter
and mu ltip le re ce ivers may iden tif y some transmitted characters
as receiver addresses and the rest of the characters as data. If
PEN = 0, STKYP is ignore d .
0 = No effect on parity bit.
1 = Forces parity bit to be oppo site of EPS bit value.
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19.5.1.3.7 Line Status Register (LSR)
This register provides status information to the processor concerning the data
transfers. Bits 5 and 6 show informat ion about the transmitter section. The rest of the
bits contain information about the receiver.
In non-FI FO mode, three of the L SR regi ster bits, pari ty error, framing error, and break
interrupt, show the erro r status of the character that has just been received. In FIFO
mode, these three bits of status are stored with each received character in the FIFO.
LSR show s the st atus bits of the cha ract er at t he t op of th e FIFO. When th e c har acter at
the top of the FIFO has errors, the LSR error bits are set and are not cleared until
software reads LSR, even if the character in the FIFO is read and a new character is
n ow at th e to p of the FI FO .
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt
when any of the corresponding conditions are detected and the interrupt is enabled.
These bits are not cleared by reading the erroneous byte from the FIFO or receive
buffer. They are cleared only by reading LSR. In FIFO mode, the line status interrupt
4EPS
Even Parity Select: This bit is the eve n parity select bit. When
PEN is a logic ’1’ and EPS is a lo gic ‘0, an odd number of logic ’1’ s
is transmitted or check ed in the data word bits and the parity bit.
When PEN is a log ic ’ 1’ a nd EPS is a logic ‘1 , a n e ven n umb e r of
logi c one s is transmitted or checke d in the d ata word bit s and
parity bit. If PEN = 0, EPS is ignored.
0 = Se n d s or ch e cks for odd parity.
1 = Se n d s or ch e cks for even parity.
3PEN
Parity Enable: This is the parity enable bit. When PEN is a logic
‘1’, a parity bit is generated (transmit data) o r check ed (receiv e
data) b e twe e n the last d ata word bit and Stop bit of the serial
data. (The parity bit is used to produce an even or odd number of
’1’s w he n the data word bits and the par ity bit are summed.)
0 = No parity function
1 = Allows parity generation and c hecking.
2STB
Stop Bits: This bit specifies the numb er of stop bits trans mitted
and received in each serial character. If STB is a logic ‘0’, one
stop bit is gene rate d in the transmitted data. If STB is a logi c ’1’
whe n a 5-bit word length is selected through bits ’0’ and ‘1’, then
one a nd o ne h alf s top bi ts are generated. If STB i s a logic 1
wh en eith er a 6, 7, or 8-bi t word is selected, then two stop bits
are generated. The receiver checks the first stop bit only,
rega rd le ss of the number of sto p bits selecte d.
0 = 1 stop bit
1 = 2 stop bits , excep t fo r 5-b it characte r the n 1-1/2 bits
1:0
WLS[1:0] Wor d Length Select: The Word Length Se le ct b its specify the
numb e r of data b its in each tra nsmitted or received se rial
character.
00 = 5-bit character (def ault)
01 = 6-bit charact er
10 = 7-bit charact er
11 = 8-bit charact er
Table 645. Line Control Register (LCR) (Sheet 2 of 2)
Seri al L ine C o ntr o l R egist er
LCR
read/write
Address:
Reset State:
Access:
Base + 03H
00H
8-bit
Bit Number Bit Mnemonic Function
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Intel® 6300ESB I/O Controller Hub
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occurs only when the erroneous byte is at the top of the FIFO. If the erroneous byte
being receiv ed is not at the top of the FIFO, an inter rup t is g enera ted only after the
previous bytes are read and the erroneous byte is moved to the top of the FIFO.
Table 646. Line Status Register (LSR) (Sheet 1 of 2)
Line Statu s Register
LSR
read-only
Address:
Reset State:
Access:
Base + 05H
60H
8-bit
Bit Number Bit Mnemonic Function
7FIFOE
FIFO Er ro r Sta tus: In non-FIFO mode, this bit is 0. In FIFO
Mode, FIFOE is set to ’1’ when there is at least one parit y error,
framing error, or break indication for any of the characters in the
FIFO. Note that a proc essor read to the Line Stat us regi ster do e s
not res et this bit. FIFOE is reset when all error byte s have been
read fr om the FIFO. FIFOE set to ’1’ d oes not g e nerate interrupt.
0 = No FIFO or no errors in receiver FIFO.
1 = At leas t one cha racte r in re ce iver FIFO has e rrors.
6TEMT
Transmitter Empty: TEMT is set to a logic ’1’ when the Transmit
Holding register and the Transmitter Shift register are both
empty. It is reset to a logic ’0’ when either the Transmit Holding
register or the transmitter shift register contains a data character.
In FIFO mode, T EM T is set to ’1’ whe n the transm itter FIFO and
the Transmit Shift regist er are both emp ty.
5TRDQ
Transmit Data Request: TDRQ indicates that the UART is ready
to acce pt a new charact er for transmiss ion. In a d di tion, this bit
causes the UART to issue an i nterrupt to the processor when the
transm it data request int er rupt enable is set hi gh and gene ra te s
the DM A req ue st to D MA controller to ask fo r data. The TD RQ b it
is set to a logic ’1’ when a charac ter is transfe rred from the
Transmit Holding register into the Transmit Shift register. Th e bit
is res et to logic ’0’ conc urre n tly with the loa d in g of th e Transmit
Holding register by the processor. In FIFO mode, TDRQ is set to
’1’ when the transmit FIFO is emp ty or the RESETTF bit in FCR
has bee n set to 1. It is cleare d whe n at le ast one byte is written
to the transmit FIFO. If more than 16 characters are loaded into
the FIFO, the excess characte rs are lost.
0 = Proc essor ha s loa d e d the Transmit Holdin g Reg iste r.
1 = Transmit FIFO is empty (FIFO mode) or a character has
transferre d fr om the Transmi t Hold ing register into the Transmit
Shift register.
4BI
Break Interrupt: BI is set to a log ic ’1’ when the rece ived data
input is he ld in the spa cing (log ic 0) state for lo n ger than a full
word transmission time (that is, the total time of Start bit + data
bits + parity bit + stop bits). The Break indicator is reset when
the processor reads the Line Status Regi ster. In FIFO mode, only
one character (equal to 00H), is loaded into the FIFO regardless
of the length of the break condition. BI shows the break condition
for the characte r at the top of the FIFO, not the most recently
received character.
0 = No br eak signal has been received.
1 = Bre a k signal occurred
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19.5.1.3.8 Modem Control Register (MCR)
This 8-bit register controls the interf ace with the modem or data set (or a peripheral
device emulating a modem). The contents of the Modem Control register are described
in Table 647.
3FE
Framing Error: FE ind icates that the received character did not
have a valid stop bit. FE is set to a logic ’1’ when the bit following
the las t da t a bi t or pa r it y bi t is dete c ted a s a logi c ’0’ bi t ( sp a cing
leve l). If the Line Control regis te r had be e n set for two stop b it
mode, the receiver does not check for a valid second stop bit. The
FE indicator is reset when the processor reads the Line Status
Regi ster. Th e UART wi ll resynchronize after a framing erro r. To do
th is it assumes that the framing error wa s du e to the next start
bit, s o it samp le s this “start” b it twice and then takes in the
“data”. In FIFO mo de, FE shows a framing error f or the character
at the top of th e FIF O, not for the mo st rece ntly received
character.
0 = No Framing error
1 = Invalid stop bit has been detected.
2PE
Pari ty Error: PE indicates that the re ceived data character doe s
not have the correct even or odd parity, as selected by the even
parity select bit. The PE is set to a logic ’1’ up on detection of a
pari ty erro r and is rese t to a logic ’0’ when the proces s or read s
th e Line Status registe r. In FIF O mode, PE shows a parity e rror
for the character at the top of the FIFO, not the most recently
re ce ived ch a rac t e r.
0 = No Parity error
1 = Parity err or h a s occurred.
1OE
Ove rrun Error: In non-FIFO mode, OE indicates that data in the
receiver buffer register was not read by the processor before the
next chara cter was transferred into the re ce iv e r buff e r register,
thereb y de st r o ying the pre vio us characte r. In F I FO mode, OE
in dica te s tha t all 16 bytes of the FIFO ar e full an d the most
re cently received byte has been discard ed. The OE indicator is set
to a logic ’1 upon de te ction of an overr un cond ition and rese t
when the p r oc esso r r eads the L i ne Statu s r eg i s ter.
0 = No data has been lost
1 = Received data has been lost.
0DR
Dat a Ready: Bit 0 is set to a logic ’1’ when a complete incoming
ch arac te r ha s b e en received and tra n sf e rre d in to the re ce iver
buffer register or the FIFO. In non-FIFO mode, DR is reset to ’0
wh en the receive buffer is rea d . In FI FO mod e , D R is re set to a
logic ’0’ if the FIFO is empty (last character has been read from
RBR) or the RESET RF b it is set in FCR.
0 = No data has been received.
1 = Data is a vailab le in RB R or the FIFO.
Table 646. Line Status Register (LSR) (Sheet 2 of 2)
Line St atus Regist e r
LSR
read-only
Address:
Reset State:
Access:
Base + 05H
60H
8-bit
Bit Number Bit Mnemonic Function
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Table 647. Modem Control Register (MCR) (Sheet 1 of 2)
Mo dem Control Register
MCR
read/write
Address:
Reset State:
Access:
Base + 04H
00H
8-bit
Bit Nu mber Bit Mnemo nic Funct ion
7:5 0 Reserved
4LOOP
Loo p Back Test Mo de: T his bit provides a local Loopback
feature for diagnostic testing of the UART. When LOOP is set to a
logic 1, th e following will occur: The transmitter serial o utput is
set to a log ic ’ 1’ state. The OUT2# sig n a l is forced to a logic ’1’
state. The receiver serial input is disconnected from the pin. The
output of the Transmit ter Shift register is “loop e d bac k” into the
receiv e r sh if t re g i ste r inp u t. The four mod e m cont rol inputs
(CTS#, DSR#, DCD#, and RI#) are disconnected from the pins
and the modem control output pins (RT S# and DTR#) are forced
to their inac tive state.
Coming out of the loop b a ck te st mod e may resu lt in
u npr edic ta b le activation o f the del ta bits (bi ts 3:0) in the
Modem Status Register (MSR). It is recommended that MSR
be re ad once to clear the d el ta bits in the MSR.
The lo we r fo u r bit s of the Mod e m Control reg ister are conne cte d
to t he u pper fo ur Mode m Statu s register b i ts:
DTR = ’1’ forces DS R to a '1'
RTS = ’1’ forces CTS to a '1'
O UT 1 = ’1’ forces RI to a '1'
O UT 2 = ’1’ forces DCD to a '1'
In the diagno stic mod e , data that is trans mitted is immediate ly
receiv ed. This fe at ure a llows t he processor to verify the transmi t
and re ce ive d ata paths of the UART. The transmit, re ce iv e an d
modem control interrupts are operational, exc ept the modem
control inte rrupts are activated by Control register b its , n ot the
modem c ontrol inputs. A break signal may also be transferred
from the transm itte r section to the receiv er section in loopback
mode.
0 = Normal UART operation
1 = Test mode UAR T operation
3OUT2
Out2# Signal Control: This bit cont rols the OUT2# outpu t.
When the OUT2 bit is set, OUT2# is asserted l ow. When the
OUT2 bit is cleared, OUT2# is deasserted (set high). Outside of
the UART module , the OUT2 # sign al is us ed to connect the
UART's interrupt output to the Interrupt Controller unit.
0 = OUT2# signal is '1' , which d isa b le s the UA RT int er rup t.
1 = OUT2# signal is ‘0’.
2OUT1
Test Bit: This bit is used only in Loopback test m ode. See ( LO OP) Above.
1RTS
Request To Send: This bit controls the Request to Send (RTS#)
output pin. B it ’1’ affects the RTS# output in a manner id e ntical
to that described below f or the DTR bit.
0 = RTS# pin is 1
1 = RTS# pin is 0
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19.5.1.3.9 Modem Status Register (MSR)
This 8 bit re giste r provide s the cu rren t state of the co ntro l lines from the mod em or
data set (or a peripheral device emulating a modem) to the processor. In addition to
this current state information, four bits of the Modem Status register provide change
information. These bits, 3:0, are set to a logic ’1’ when a control input from the Modem
changes state. They are reset to a logic ’0’ when the processor writes ’1’s to the bits of
the Modem Status register.
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3
of the Interrupt Enable Register is set.
0DTR
Data Terminal Ready: Th is bit controls the Data Ter mina l
Ready output. W he n bit 0 is set to a logic ‘1’, the DTR# output is
forc e to a logic ‘0’. Whe n b it 0 is reset to a log ic ‘0’, the DTR#
output pin is forced to a logic ‘1.
The DTR# output of the UART may be applied to an EIA
inverting line driver (such as the D S1 488) to ob tain the
prope r po larity input at the su ccee d ing mod e m or d a ta se t.
0 = DTR# pin is 1
1 = DTR# pin is 0
Table 647. Modem Control Register (MCR) (Sheet 2 of 2)
Table 648. Modem Status Register (MSR) (Sheet 1 of 2)
Modem St atu s Regis ter
MSR
read only
Address:
Reset State:
Access:
Base + 06H
00H
8-bit
Bit Number Bit Mnemonic Function
7DCD
Dat a C arri er Detect : T his b it is the complement of the D ata
Carrier Detect (DCD#) input. This bit is equivalent to bit OUT2
of the M od e m Control reg ister if LOOP in the M CR is se t to 1.
0 = DCD# pin is 1
1 = DCD# pin is 0
6RI
Ring Indicator : This bit is th e compleme nt of the rin g
Indic ator (RI#) input. This bit is equivalent to b it OUT1 of the
Mo dem Con trol register if LO OP in th e MCR is se t to 1.
0 = RI# pin is 1
1 = RI# pin is 0
5DSR
Data Set Ready: Th is b it is the com plement of the Data Set
Ready (DSR# ) input. This bit is equivalent to bit DTR of the
Mo dem Con trol register if LO OP in th e MCR is se t to 1.
0 = DSR# p in is 1
1 = DSR# p in is 0
4CTS
Clear to Send: This bit is th e compleme nt of the Cl ear t o
Send (CTS#) inp u t. T h is bit is equivalent to bit RTS of the
Mo dem Con trol register if LO OP in th e MCR is se t to 1.
0 = CTS # pin is 1
1 = CTS # pin is 0
3DDCD
Delta Data Carrier Detect:
0 = No change in DC D# pi n since l ast read of M SR.
1 = DCD# pin has changed sta te.
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19.5.1.3 .10Sc ratchpad Regis te r (SCR)
This 8-bit read/write register has no effect on the UART. It is intended as a scratchpad
register for use by the programmer.
19.5.1.3.11Programmable Baud Rate Generator
The UART contains a programmable Baud Rate Generator that is capable of taking the
UA R T_C LK inp ut an d div idi ng it by an y div iso r fro m 1 to (2 16 -1). The output freq uency
of the Baud Rate Generator is 16 times the baud rate. Two 8-bit latches store the
divisor in a 16-bit binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Rate Generator. If both Divisor
Latches are loaded with 0, the 16X output clock is stopped. Upon loading either of the
Divi so r latc he s, a 16- bi t baud c oun ter i s imm edi atel y lo aded. Thi s prev en ts lon g coun ts
on initial load. Access to the Divisor latch may be done with a word write.
The baud rate of the data shifted in/out of the UART is given by:
Baud Rate = UART_CLK(MHz)/[16X Divisor]
For example, if UART_CLK is 14.7456MHz and the divisor is 96, the baud rate is 9600.
A Divisor value of 0 in the Divisor Latch Register is not allowed. The reset value of the
divisor
is 02.
2TERI
Trailing Edge Ring Indicator:
0 = RI# pin has not changed from ’0’ to ’1’ since last read of
MSR.
1 = RI# pin has changed from ’0’ to 1.
1DDSR
Delta Da ta Set Ready:
0 = No ch an g e in DSR# pi n sin ce last re a d of MS R .
1 = DSR# pin has changed state.
0DCTS
Delta Cle ar To Send:
0 = No change in CTS# pin since last read of MSR.
1 = CTS# pin has change d st a te .
Table 648. Modem Status Register (MSR) (Sheet 2 of 2)
Table 649. Scratch Pad Regist er (SCR)
Scratch Pad Re gi ster
SCR
read/write
Address:
Reset State:
Access:
Base + 07H
00H
8-bit
Bit Number Bit Mnemonic Function
7:0 SP[7:0] No effect on UART function ality
Table 650. Divisor Latch Register Low (DLL)
Divisor Latch Register Low
DLL
read/write
Address:
Reset State:
Access:
Bas e (DLAB=1)
02H
8-bit
Bit Nu mber Bi t Mne moni c Funct ion
7:0 BR[7:0] Low byte compare value to generate baud r ate
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19.5.1.4 FIFO Operation
19.5.1.4.1 FIFO Interrupt Mode Operation
Receiver Interrupt
When the Receive FIFO and receiver interrupts are enabled (FCR[0]=1 and IER[0]=1),
receiver interrupts occur as follows:
The receive data available interrupt is invoked when the FIFO ha s reached its
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
The receiver line status interrupt (IIR = C6H), as before, has the highest priority.
The receiver data available interrupt (IIR=C4H) is lower. The line status interrupt
occurs only when the character at the top of the FIFO has errors.
The data ready bit (DR in LSR register) is set to ’1as soon as a character is
transferred from the shift register to the Receive FIFO. This bit is reset to ’0’ when
the FIFO is empty.
Charact er Ti meout Inter rupt
When the receiver FIFO and receiver time out interrupt are enabled, a character
timeout interrupt occurs when all of the following conditions exist:
At least one character is in the FIFO.
The l as t rec e ived ch ar ac te r wa s lo n ger tha n f our c ont in uou s ch aract er ti me s ag o ( if
2 stop bits are programmed the second one is included in this time delay).
The most recent processor read of the FIFO was longer than four continuous
character times ago.
The receiver FIFO trigger level is greater than one.
The maximum time between a received character and a timeout interrupt is 160 ms at
300 ba ud wit h a 12-bi t re ceiv e char a cter (i .e ., 1 star t, 8 data , 1 pari ty, and 2 stop bits ).
When a time out interrupt occurs, it is cleared and the timer is reset when the
processor reads one character from the receiver FIFO. If a timeout interrupt has not
occurred, the timeout timer is reset after a new character is received or after the
processor reads th e receiver F IFO.
Trans mit Int err upt
When the transmitter FIFO and transmitter interrupt are enabled (FCR[0]=1,
IER[1]=1), transmit interrupts occur as follows:
The Transmit Data Request interrupt occurs when the transmit FIFO is half empty
or more than half empty. The interrupt is cleared as soon as the Transmit Holding
Table 651. Divisor Latch Register High (DLH)
Divi sor L atc h R egiste r High
DLH
read/write
Address:
Reset State:
Access:
Base + 1 (DLAB=1)
00H
8-bit
Bit Number Bit Mnemonic Function
7:0 B R[15:8] High byt e comp are value to generate baud rate
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Register is written (1 to 16 characters may be written to the transmit FIFO while
servicing the interrupt) or the IIR is read.
19.5.1.4.2 FIFO Polled Mode Operation
Wi th the FIF Os e nab l ed ( TR FI FO E bit of FCR se t t o 1 ), s et t in g I ER[ 3:0 ] t o all ze ro s put s
the serial port in the FIFO polled mode of operation. Since the receiver and the
t ransmitter are controlled separately, either one or both may be in the polled mode of
operation. In this mode, software checks receiver and transmitter status through the
LSR. As stated in the register description:
LSR[0] is set as long as there is one byte in the receiver FIFO.
LSR[1] through LSR[4] specify which error(s) has occurred for the character at the
top of the FIFO. Character error status i s handled the same way as interrupt mode.
The IIR is not affected since IER[2] = 0.
LSR[5] indicates when the transmitter FIFO needs data.
LSR[6] indicates that both the transmitter FIFO and shift register are empty.
LSR[7] indicates whether there are any errors in the receiver FIFO.
19.6 Logical Device 7 (07H): Port 60/64
Emulation
This section describes the Port 60/64 Emulation integrated into the SIU.
19.6.1 Feature Lis t
Configurable unit disable
Positive decode for I/O cycles to 60h and 64h
Read/Write Scratchpad Registers Only (sticky bits)
Interrupt on write and self-interrupt clearing
19.6.2 Overview
The Port 60/64 Emulation Unit consists of two 8-bit I/O registers intended to preserve
values written to Port 60 and 64 thus emulating a legacy 8042 device formerly at this
legacy I/O address space. These registers may be enabled by BIOS typically in a pre-
OS environment and may be disabled during run time. These registers may be used for
8042 keyboard controller emulation but in no way support any controlle r or
functionality beyond a scratchpad register and interrupt generation on writes.
Wh en ena b le d, thi s Dev i ce wi ll p os itive ly de co de 8-b it I / O a cce s ses t o ad dre ss 60 h a nd
64h.
Writes to these addresses may generate an interrupt as configured in the Logical
Device 07 Primary Interrupt Register (70h). The interrupt generated from this unit will
drive active (drives a logical 0) for one SIRQ frame. It does not require any further
action (i.e., no EOI required or status bit to clear).
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19.6.2.1 Port 60H Emulation (S CR60 )
This 8-bit read/write register has no effect. It is intended as a scratchpad register for
use by the programmer.
19.6.2.2 Port 64H Emulation (S CR64 )
This 8-bit read/write register has no effect. It is intended as a scratchpad register for
use by the programmer.
19.7 SERIA L IRQ
The SIU supports the serial interrupt to transmit interrupt information to the host
system. The serial interrupt scheme adheres to the Serial IRQ Specification.
19.7 .1 T i ming Diagrams For SIU_SERIRQ Cycle
Tab l e 65 2. Scr a tch Pad Register P60 (SCR60)
Scra tch Pad Regi s ter P60
SCR60
read/write
Address:
Reset State:
Access:
60H
00H
8-bit
Bit
Number Bit Mnemonic Function
7:0 SP60[7:0] N o effe ct on SIU f unctionality
Tab l e 65 3. Scr a tch Pad Register P64 (SCR64)
Scra tch Pad Regi s ter P64
SCR64
read/write
Address:
Reset State:
Access:
64H
00H
8-bit
Bit
Number Bit Mnemonic Function
7:0 SP64[7:0] N o effe ct on SIU f unctionality
Figure 34. Start Frame Timing with Source Sampled a Low Pulse on IRQ1
NOTES:
1. H=Host Con trol; R=Recovery; T=Tur n-Around ; S L=Slave Control; S=Sa mple
2. Start Frame pulse may be 4-8 clocks wide depending on the location of the device in the PCI
bridge h ierarchy in a synchronous bridge design.
R
T
S
R
T
S
S
IUSIRQ
S
IUCLK
Host Controller
IRQ IRQ1
Drive Source
R
T
None
IRQ0 FRAME IRQ1 FRAME
S
R
T
IRQ2 FRAME
None
START
START FRAME
H
SL
or
H
1
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19.7.1.1 SIU_SERIRQ Cycle Control
There are two modes of operation for the SIU_SERIRQ Start Frame.
1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the
SIU_SERIRQ low for one clock, while the SIU_SERIRQ is Idle. After driving low for
one clock the SIU_SERIRQ is immediately tri-stated without at any time driving
high. A Start Frame may not be initiated while the SIU_SERIRQ is Active. The
SIU_SERIRQ is Idle between Stop and Start Frames. The SIU_SERIRQ is Active
between Start and Stop Frames. This mode of operation allows the SIU_SERIRQ to
be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Fram e has been in itiated the Host Co ntroller will take over
driving th e SIU_ SERI RQ low in the next cl o ck and will conti n ue dri vi n g the
SIU_SERIRQ low for a progr ammable period of three to seven clocks. This
makes a total low pulse width of four to eigh t clocks. Finally, the Host
Controller will drive the SIU_SERIRQ back high for one clock, then tri-
state.
Any SIU_SERIRQ Device (i.e., the SIU) which detects any transition on an
IRQ/D a ta line for wh i ch it is r esponsi ble m ust initiate a Star t F ra m e in
order to update the Host Controller unless the SIU_SERIRQ is already in an
SIU_S E RIRQ Cycle and the IRQ/Data tr ans it io n may be delivered in that
SIU_SERIRQ Cycle.
2. Continuous (Idle) Mode: Only the Host controller may initiate a Start Frame to
update IRQ/Data line information. All other SIU_SERIRQ agents become passive
and may not initiate a Start Frame. SIU_SERIRQ will be driven low for four to eight
clocks by Host Controller. This mode has two functions. It may be used to stop or
idle the SIU_SERIRQ or the Host Controller may operate SIU_SERIRQ in a
continuous mode by initiating a Start Frame at the end of every Stop Frame.
An SIU _S ER IRQ mode trans ition m ay only occur du r ing th e S top F rame.
Note: Upon reset, SIU_SERIRQ bus is defaulted to Continuous mode, therefore only the Host
controller may initiate the first Start Frame. Slaves must continuously sample the Stop
Frames pulse width to determine the next SIU_SERIRQ Cycles mode.
Each SIU port must use a dedicated interrupt. SIU interrupts cannot be shared with
each other or with other devices.
Figure 35. Stop Frame Timing with Host Using 17 SIU_SERIRQ Sampling Period
NOTES:
1. H=Hos t Control; R=Recovery; T=Tu rn-Around ; S= Sample; I=Idle
2. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
3. There m ay b e none, one or mo r e Idle sta tes dur ing th e S t op Fra m e.
4. The next SIU_SERIRQ cycle’s Start Frame pulse may or may not start immediate ly after the
turn-ar ound clock of the Sto p Frame.
SRTS
S
ER_IRQ
P
CI_CLK
Host ControllerIRQ15
Driver
RT
None
IRQ14 IRQ15
SRT
IOCHCK#
None
STOP
RT
STO P FRA M E
H
I
START
N EXT CY C LE
1
2
3
FRAMEFRAME
FRAME
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19.7.1.2 SIU_SERIRQ Data Frame
Once a Start Frame has been initiated, the SIU will watch for the rising edge of the
Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is
three clocks: Sample phase, Recovery phase, an d Turn-around phase. During the
Sample phase the SIU drives the SIU_SERIRQ low, if and only if, its last detected IRQ/
Data value was low. If its detected IRQ/Data value is high, SIU_SERIRQ is left tri-
stated. During the Recovery phase the SIU drives the SIU_SERIRQ high, if and only if,
it had driven the SIU_SERIRQ low during the previous Sample Phase. During the Turn-
around Phase the SIU tri-states the SIU_SERIRQ. The SIU will drive the SIU_SERIRQ
line low at the appropriate sample point if its associated IRQ/Data line is low,
regardless of which device initiated the Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start
Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus
one. (e.g. , The IRQ5 Sample c lock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock
after the rising edge of the Start Pulse).
SIU_SERIRQ Period 13 is used to transfer IRQ12.
19.7.1.3 Sto p Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate
SIU_SERIRQ activity by initiating a Stop Frame. Only the Host Controller may initiate
the Stop Frame. A Stop Frame is indicated when the SIU_SERIRQ is low for two or
three clocks. If the Stop Frame’s low time is two clocks, the next SIU_SERIRQ Cycle’s
sampled mode is the Quiet mode; and any SIU_SERIRQ device may initiate a Start
Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If
th e Sto p Fr a me’s low ti me is thr ee cl oc k s, the next SIU_ SER I RQ Cy cl e’s sampl ed mode
is the Continuous mode; and only the Host Controller may initiate a Start Frame in the
second clock or more after the rising edge of the Stop Frame’s pulse.
Table 654. SIU_SERIRQ Sampling Periods
SIU_SERIRQ PERIOD SIGNA L SAMPLED # OF CLOCKS PAST ST ART
1Not Used 2
2IRQ1 5
3IRQ2 8
4IRQ3 11
5IRQ4 14
6IRQ5 17
7IRQ6 20
8IRQ7 23
9IRQ8 26
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38
14 IRQ13 41
15 IRQ14 44
16 IRQ15 47
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19.7.1.4 Latency
Latency for IRQ/Data updates over the SIU_SERIRQ bus in bridge-less systems with
the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks
(2 .88 µs wi th a 33 MHz PC I Bus ). I f one o r more PCI to P CI B ridg e is adde d to a s yst em,
the latency for IRQ/Data updates from the secondary or tertiary buses will be a few
clocks longer for synchronous buses, and ap proximately double for asynchronous
buses.
19.7.1.5 EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency.
I RQ latenc y coul d cause an EOI or ISR R ead to pr ecede an IRQ tran siti on that it shou ld
have followed. This could cause a system fault. The host interrupt controller is
responsible for ensuring that these latency issues are mitigated. The recommended
solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount
as th e SIU_SERIRQ Cycl e laten cy in order to e nsur e that th ese eve nts do not occ ur ou t
of order.
19.7.1.6 Res et and Initializ ation
The SIU_SERIRQ bus uses SIU_LRESET# as its reset signal. The SIU_SERIRQ pin is tri-
stated by all agents while SIU_LRESET# is active. With reset, SIU_SERIRQ Slaves are
put into the (continuous) IDLE mode. The Hos t Controller is responsible for starting the
initial SIU_SERIRQ Cycle to collect system’s IRQ/Data default values. The system then
follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent SIU_SERIRQ Cycles. It is Host Controllers responsibility to provide the
default values to the Interrupt controller and other system logic before the first
SIU_SERIRQ Cycle is performed. For SIU_SERIRQ system suspend, insertion, or
remov al application, the Host controller should be progra mmed into Continuous (IDLE)
mode first. This is to ensure that the SIU_SERIRQ bus is in IDLE state before the
system configuration changes.
19.8 Configuration
The Configuration of the SIU is very flexible and is based on the configuration
architecture implemented in typical Plug-and-Play components. The SIU is designed for
mo the r bo ard ap p lic atio n s in wh ic h the r eso u rce s re qu ir ed by their co mp on en t s are
known. With its flexible resource allocation architecture, the SIU allows the BIOS to
assign resources at POST.
19.8.1 Configuration Port Address Selection
The SIU configuration port addresses for INDEX and DATA are fixed at 4Eh/4Fh.
See also Section 8.1.31, “Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—
D31:F0)” on page 337.
19.8.2 Primary Configuration Address Decoder
After a PCI R eset (SIU_LRESET# pin asserted) or Power On Reset the SIU is in the Run
Mode with the two UARTs disabled. They may be configured through two standard
Configuration I/O Ports (INDEX and DATA) by placing the SIU into Configuration Mode.
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The BIOS uses these configuration ports to initialize the logical devices at POST. The
INDEX and DATA ports are only valid when the SIU is in Configuration Mode.
The INDEX and DATA ports are effective only when the chip is in the Configuration
State. When the SIU is not in the Configuration State, reads return FFh and write data
is ignored.
19.8.2.1 Enterin g the Configuration State
The device enters the Configuration Stat e by the following contiguous sequence:
Write 80H to Configuration Port.
Write 86H to Configuration Port.
19.8.2.2 Exiting the Configuration State
The device exits the Configuration State by the following contiguous sequence:
Write 68H to Configuration Port.
Write 08H to Configuration Port.
19.8.2.3 Configuration Sequence
To program the configuration registers, the following sequence must be followed:
1. Enter Configuration Mode.
2. Configure the Configuration Registers.
3. Exit Configuration Mode.
19.8.2.4 Configuration Mode
The system sets the logical device information and activates desired logical devices
through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located
at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1.
The desired configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (i.e., 07) to
the INDEX PORT and then write the number of the desired logical device to the
DATA PORT.
2. Write the address of the desired configuration register within the logical device to
the INDEX PORT and then write or read the configuration register through the DA TA
PORT.
Note: If accessing the Global Configuration Registers, step (a) is not required.
3. The chip returns to the RUN State.
Note: Only two states are defined: Run and Configuration. In the Run State, the chip will
always be ready to enter the Configuration State.
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
730 Order Number: 300641-004US
19.8.3 SIU Configuration Registers Summary
Table 655. Configuration Registers Summary
Global C onf iguration Reg isters
Index Type Default Configuration Register
07h R/W 00h Log ical D evice Number
20h R 00h Device ID
21h R 00h Device Rev
28h R/W 01h SIU I/F (wait state s)
29h R/W 02h SIRQ Configuration
2Eh R/W 00 Test Mode Conf iguration
Register
Log ical Device 4 Regist ers (Serial Port 0)
30h R/W 00h Enable
60h R/W 00h Base I/O A d dres s MS B
61h R/W 00h Base I/O A d dres s LSB
70h R/W 00h Primary Interrupt Selec t
74h R 04h Reserved
75h R 04h Reserved
F0h R 00h Vendor S p ec if ic
Configuration
Log ical Device 5 Regist ers (Serial Port 1)
30h R/W 00h Enable
60h R/W 00h Base I/O A d dres s MS B
61h R/W 00h Base I/O A d dres s LSB
70h R/W 00h Primary Interrupt Selec t
74h R 04h Reserved
75h R 04h Reserved
F0h R 00h Vendor S p ec if ic
Configuration
Logical Device 7 Registers (Port Emulation)
30h R/W 00h Enable
60h R 00h Base I/O Address MSB
61h R 60h Base I/O Address LSB
7 0h R/W 00h Prim ary I nte rrupt Select
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 731
19—Intel® 6300ESB ICH
19.8.3.1 Global Control/Configura tio n Registers [00h — 2Fh]
The chip-level (global) registers lie in the address range [00h-2Fh]. The design MUST
use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers
and bits ignore writes and return ’0’ when read.
The INDEX PORT is used to select a configuration register in the chip. The DA T A PORT is
then used to access the selected register. These registers are accessible only in the
Configuration Mode.
19.8.3.2 Logical Device Configuration Registers [30h — FFh]
Used to access the registers that are assigned to each logical unit. This chip supports
tw o logic al uni ts and has tw o sets o f l ogi cal de vice r egis ters. T he tw o logic al dev ices a re
UART0 and UART1. A separate set (bank) of control and configuration registers exists
for each logical device and is selected with the Logical Device # Register.
The INDEX PORT is used to select a specific logical device register. These registers are
then accessed through the DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration
State. The logical register addresses are shown in Table 657 through Table 659.
Table 656. Global Control Registers
Register Address
(Type) Description
Log i cal De vice #
Default = 00h 07h
(R/W)
Logical Device Selec t: A write to this register selects the
current logical device. This allows access to the control and
configuration registers for each logical device.
Device I D
Default = 00h 20h
(R) De vice ID: A read only register which provides the Device
ID.
Device Re v
Default = 01h 21h
(R) Devi ce Rev : A rea d only register which p rov id e s dev ice
revision information.
SIU Inte r fac e
Default = 01h
28h
(R/W bits 7:2,
0
R- bi t 1 )
Bit 1 – LPC bus wait states
1 = Long wait states (sync 6)
0 = Not sup ported
Bit 7:2, 0 – R SVD = 0
SIU Configuration
Default = 02h
29h
(R/W bits 3:2,
0
R- bi t 1 )
Bit 0 – SIRQ enable
1 = Enabled; participates in interrupt generation
0 = Disabled; serial interrupts disabled
Bit 1 – IRQ mo de ( Read o n ly, Wr ites ign ored )
1 = Continuous mode
0 = Quiet mo d e
Bit 3:2 – UA R T_CL K pre - divide U ART_CL K input
00 Divide by 1
01 Divide by 8
10 Divide by 26
11 Reserved
Bit 7:4 – RSVD = 0
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
732 Order Number: 300641-004US
Table 657. Logical Device 4 (Serial Port 0)
Logical Device
Register Address Description
Enable
Def a ult = 00h 30h
(R/W)
Bits[7:1] Reserved, set to ’0’.
Bit[0]
1 = Enable the logical device currently selected through
the Logical Device # register.
0 = Lo gical devic e c urre n tly se le cte d is inac tive
I/O Base Address
Def a ult = 00h 60-61h
(R/W)
Registers 60h (MSB) and 61 h (LSB) set the bas e
address for the device.
NOTE: Decode is on 8 Byte boundaries
Intel® 6300ESB I CH Comm Decode Ranges
3F8 - 3FF (COM 1)
2F8 - 2FF (COM 2)
220 - 227
228 - 22F
238 - 23F
2E8 - 2EF (COM 4)
338 - 33F
3E8 - 3EF (COM 3)
Pr imary Interrup t
Select
Def a ult = 00h
70h
(R/W)
Bits[3:0] se le ct which interrup t le vel is us e d for the
pri mary I nte rru pt .
00= No interrupt selected
01= IRQ1
02= IRQ2
03= IRQ3
04= IRQ4
05= IRQ5
06= IRQ6
07= IRQ7
08= IRQ8
09= IRQ9
0A= IRQ1 0
0B= IRQ 11
0C= IRQ12
0D= IRQ13
0E= IRQ14
0F= IRQ15
Bits[7:4] Reserved
NOTE: A n Inte rrup t is activated by setting this reg ister
to a non-z ero value and setting any combination
of bits 0-3 in the cor responding UART IER and
the OUT2 b it in the MCR
NOTE: Each SIU port must use a dedicated interrupt.
SIU interrup ts cannot be shared with each other
or with othe r d evices.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 733
19—Intel® 6300ESB ICH
RSVD
Default = 04h 74h
(R/W - bit
3:0)
(R - bit 7:4)
Bit 7:0 - RSVD
RSVD
Default = 04h 75h
(R/W - bit
3:0)
(R - bit 7:4)
Bit 7:0 - RSVD
RSVD
Default = 00h F0h
(R/W - bit 0)
(R - bit 7:1) Bit 7:0 - R SVD
Table 657. Logical Device 4 (Serial Port 0)
Logical Device
Register Address Description
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
734 Order Number: 300641-004US
Table 658. Logical Device 5 (Serial Port 1)
Logical Device
Register Address Description
Enable
Def a ult = 00h 30h
(R/W)
Bits[7:1] Reser ved, set to ’0’.
Bit[0]
1 = Enable the logical device currently selected through
the Logical Device # register.
0 = Logical device currently selected is inactive
I/O Base Address
Def a ult = 00h 60-61h
(R/W)
Reg isters 60h (M SB) and 61h ( LSB) set the base
addr es s for the device.
NOTE: Decode i s on 8 B yte bou ndaries.
Intel® 6300ESB ICH Comm Decode Ranges
3F8 - 3FF (COM 1)
2F8 - 2FF (COM 2)
220 – 227
228 - 22F
238 - 23F
2E8 - 2EF (COM 4)
338 - 33F
3E8 - 3EF (COM 3)
Pr imary Interrup t
Select
Def a ult = 00h
70h
(R/W)
Bits[3:0] select which interrupt level is used for the
primary In terru p t.
00 = no interrup t se lected
01 = IRQ1
02 = IRQ2
03 = IRQ3
04 = IRQ4
05 = IRQ5
06 = IRQ6
07 = IRQ7
08 = IRQ8
09 = IRQ9
0A = IRQ10
0B = IRQ11
0C = IRQ12
0D = IRQ13
0E = IRQ14
0F = IRQ15
Bits[7:4] Reserved
NOTE: An Interrupt is activated by setting this register
to a non-zero v alu e and setting any combination
of bits 0-3 in the corresponding UAR T IER and
the OUT2 bit in the MCR
NOTE: Each SIU port must use a dedicated interrupt.
SIU interrupts cannot be shared with e ach other
or with other dev ice s.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 735
19—Intel® 6300ESB ICH
RSVD
Default = 04h 74h
(R/W - bit
3:0)
(R - bit 7:4
Bit 7:0 - RSVD
RSVD
Default = 04h 75h
(R/W - bit
3:0)
(R - bit 7:4
Bit 7:0 - RSVD
RSVD
Default = 00h F0h
(R /W - bit 0)
(R - bit 7:1) Bit 7:0 - RSVD
Table 659. Logical Device 7 (Port Emulation)
Logical Devic e
Register Address Description
Table 658. Logical Device 5 (Serial Port 1)
Logical Device
Register Address Description
Intel® 6300ESB ICH—19
Intel® 6300ESB I/O Controller Hub
DS November 2007
736 Order Number: 300641-004US
Enable
Def a ult = 00h 30h
(R/W) Bits[7:1] R e ser v e d, se t to ’0’.
Bit[0]
1 = Enable the logical device currently selected through
the Logical Device # register.
0 = Lo g ica l d e vice curren tly selected is in a ctiv e.
I/O Base Address
Def a ult = 60h 60-61h
(R) Regi sters 60h (MSB ) and 61h (L SB) set the base
addres s for the device.
Decode i s on 8 Byte bounda ries so both 6 0h and 64 h are
captured by the single valu e of 60h in this spac e .
NOTE: This device must ignore accesses to unsupported
byte s (spe cifically 61-63h and 65-67h)
Pr imary Interrup t
Select
Def a ult = 00h
70h
(R/W) Bits[3:0] select which interrupt level is used for the
prim a ry I nte rrupt for Port 60h, Software Not e: Do n o t
se t the int errup t to the same value as the po rt 64h
interrupt.
Bits[7:4] select wh ich interrupt level is use d for the
prim a ry I nte rrupt for Port 64h, Software Not e: Do n o t
se t the int errup t to the same value as the po rt 60h
interrupt.
00 = No inte rrupt selected
01 = IRQ1
02 = IRQ2
03 = IRQ3
04 = IRQ4
05 = IRQ5
06 = IRQ6
07 = IRQ7
08 = IRQ8
09 = IRQ9
0A = IRQ1 0
0B = IRQ1 1
0C = IRQ12
0D = IRQ13
0E = IRQ14
0F = IRQ15
NOTE: An Inte rrupt is activated by e nabl ing this device
(offset 30h),settin g this regis ter to a non-zero
value, and writing to the appropriate I/O address
(60h or 64h).
Table 659. Logical Device 7 (Port Emulation)
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 737
20—Intel® 6300ESB ICH
Seri al ATA Controller Registers
(D31:F2) 20
20.1 P C I Conf i gura ti on Regi ster s (SAT A– D31:F 2)
Note: Registers that are not shown should be treated as reserved.
All of the SATA registers are in the core well. They can never be locked.
Table 660. PCI Configuration Map (SATA–D31:F2) (Sheet 1 of 2)
Offset M n emon ic Regi st er Name/Fu ncti on De fault T ype
00-01h V I D Vendor ID 8086h RO
02-03h D I D Device ID 25A 3h or 25B 0h RO
04-05h CMD Command Regi ster 00h R/W
06-07h STS Device S tatus 02B0h R/W
08h RID Revision ID S ee Note 2 RO
09h PI Programmi ng Interfac e 8Ah R/W
0Ah SCC Sub Class Code 01h or 0 4h RO
0Bh BCC Base Class Code 01h RO
0Dh MLT Master La te ncy Tim er 00h RO
0Eh HT YPE Header Ty p e 00h RO
10-13h PCMD_BAR Primary Co mmand Block Base A ddress 00000001h R/W
14-17h PC NL_B A R Primary Control Bloc k Base A d dr ess 00000001 h R /W
18-1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W
1C -1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W
20-23h BAR Base Address Re gister 00000001h R/W
2C-2Dh SVID Subsystem Vendor ID 00h R/Write-Once
2E -2Fh SID Subsys tem ID 00h R/Write- Once
34h CAP Capabi litie s Pointe r 80h RO
3C INTR _LN Interrup t Li ne 00h R /W
3D INT R_PN Inte rrup t Pin 01h R /W
40-41h IDE_T IM P Primary IDE Timing 0 000h R/W
42-43h IDE_T IMS Secondary IDE T iming 0000h R/W
44h SIDETIM Slave IDE Timing 00h R/W
48h SDMA_CNT Synchronous DMA Control Register 00h R/W
NOTES:
1. The Intel® 6300ESB ICH SATA Controll er is not arb itrated as a PCI device, the refore it does not ne ed a
mas te r late ncy time r.
2. Refer to the Intel® 630 0ES B I/O Control le r Hub Specifica tion Update for the most up-to-date value of the
Revision ID register.
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
738 Order Number: 300641-004US
20.1.1 Offset 00 - 01h: VID—Vendor ID Register (SATA—
D31:F2)
4A-4Bh SDMA_TIM Synchronous DMA Timing Register 0000h R/W
54-57h IDE_CONFIG IDE I/O Config uration Register 00 h R/W
70-71h PID PCI Power Manage me nt Ca p ab ility ID 0001h RO
72-73 h PC PC I Power Manag e me nt Ca p abilities 0002h RO
74-75h PMCS PCI Power Management Con trol and
Status 0000h R/W
80-81h MID Messag e Signaled In terru p t Cap a b ility ID 7005h RO
82-83h MC Message Signaled Interrupt Message
Control 0000h R/W
84-87h MA Message Signaled Interrupt Message
Address 0000h R/W
88-89h MD Mes sage Signaled Interrupt Message Data 0000h R/W
90h MAP Ad d ress Map 00h R/W
92-93h PCS Port S tatus and Control 0000h R/W
A0h SRI SATA Registers Index 00h R/W
A4h SRD SATA Registers Data XXh R/W
E0h–
E3h BFC S BIS T FIS Control/Status 00000 000h R/W,
R/WC
E4h–
E7h BF TD 1 B IS T FIS Transmit Data , DW1 00000000h R/W
E8h–
EBh BFTD2 BIST FIS Transmit Data , DW2 00000000h R/W
Table 661. Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2)
Bits Name Description Access
15:0 Vendor ID Value This is a 1 6-b it value a ssig ne d to Inte l. In tel VID = 8086h RO
Table 660. PCI Configuration Map (SATA–D31:F2) (Sheet 2 of 2)
Offset Mnemonic Register Name/Function Default Type
NOTES:
1. The Intel® 6300ESB ICH SATA Controller is not arbitrated as a PCI device, therefore it does not need a
ma ster late ncy timer.
2. Refer to the Intel® 6300ES B I/O Controller Hub S pecification U pdate f or the most up-to -d ate value of the
Revision ID register.
Device: 31 Function: 2
Offset: 00-01h Attribute: Read-Only
Defau lt Value: 8086h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 739
20—Intel® 6300ESB ICH
20.1.2 Offset 02 - 03h: DID—Device ID Register (SATA—
D31:F2)
20.1.3 Offset 04h - 05h: CMD—Command Register
(SATA–D31:F2)
Table 662. Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2)
Bits Name Description Access
15:0 Device ID Value
In d i cate s wh a t d e v i ce n u mber wa s a ssign e d by th e P CI S I G .
When Device 31 Function 2, Offset AC h, bit 22=0; DID =
25A3h (har d drive )
When Device 31 Function 2, Offset AC h, bit 22=1; DID =
25B0h (RAID)
Table 663. Offset 04h - 05h: CMD—Command Register (SATA–D31:F2) (Sheet
1 of 2)
Bits Name Description Access
15:1
1Reserved Reserved.
10 Interrupt Disable
0 = Enable s the SATA host contr oller to ass ert INTA# (native
mode), IRQ14/15 (legacy mod e ), a nd MS I (whe n MSI is
enabled).
1 = The in te rrupt will be de a sse rted and it may no t gene ra te
MSIs.
R/W
9Fast Back - t o- Bac k
Enable (FBE) Reserved as0’. RO
8 S ERR# Enab le Reserved as ‘0’. RO
7 Wait Cycle Control Res er ved as ‘0’. RO
6 Parity Error Respon se
0 = Disabled . SATA Controller will not generate PERR# whe n
a data parity error is detected.
1 = Enabled . SATA Controller will gene rate PERR# whe n a
data parity error is de te cted .
R/W
5 VGA Palette Snoop Reserved as ‘0’. RO
4Postable Me mory Write
Enable (PMWE) Reserved as0. RO
Device: 31 Function: 2
Offset: 02-03h Attribute: Read-Only
Defau lt Value: 25A 3h or 25B0h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 2
Offset: 04h-05h Attribute: Read-Only, Read/Write
Defau lt Value: 00h Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
740 Order Number: 300641-004US
3Spe cia l Cy cle E na b le
(SCE) Rese rv ed as ‘0’. RO
2Bu s M a st e r En a b l e
(BME)
Controls the Inte l® 6300ES B ICH’s ability to act as a PCI
ma ster for I DE Bu s M a ster tra nsfe r s. Th is b it do e s not impac t
the generation of completions f or split transaction commands. R/W
1Memory Space Enable
(MSE) The SATA Cont ro ller do es not c on tai n memory space. RO
0IOSE - I/O Space Enable
(IOSE)
This bit c on trols access to the I /O sp a ce register s.
0 = Disables access to th e Le g a cy or Native ID E ports (both
Primary and Secondary) as well as the Bus Master IO
registers.
1 = Enabl e. Note that the Base Address register for the Bus
Master regis ter s shoul d be programm ed bef ore this bit is
set.
R/W
Table 663. Offset 04h - 05h: CMD—Command Register (SATA–D31:F2) (Sheet
2 of 2)
Bits Name Description Access
Device: 31 Function: 2
Offset: 04h-05h Attribute: Read-Only, Read/Write
Defau lt Value: 00h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 741
20—Intel® 6300ESB ICH
20.1.4 Of fset 06 - 07h: STS—Device Status Re gis ter
(SATA–D31:F2)
Table 664. Offset 06 - 07h: STS—Device Status Register (SATA–D31:F2)
Bits Name Description Access
15 Dete cte d Parity Error
(DPE) 0 = No Parity e rror dete cte d by SATA controller.
1 = SATA Controller detects a parity error on its interface. R/WC
14 Signa l ed Syst em Erro r
(SSE)
This bit is set by the Intel® 6300ESB ICH whenever it signals
SERR# (internally). The S ERR_E N bit (bit 8 in the Command
Register) must be ’1’ for th is bit to be set. T h e foll owing
conditions can cause the generation of S ERR#:
A parity error is seen on address, command, or data (if the
data was targ e ting the EHC) on the inte rnal inte rf a ce to the
USBe h ost control le r due to a parity error on H ub In te rfac e
and bi t 6 of the Command reg ister is set to 1.
An EHC-initiated memory read results in a completion packet
with a status other than successful on Hub Interface. The
SERR on Aborts Enable bit (bit 3, offset 84h) must also be set
in this case .
Software cle ars th is b it by writing a ‘1’ to this bit location.
R/WC
13 Rece ived M a ste r -Abo rt
Status (RMA )
0 = 0 C l ear ed by wr i t in g a ’1 to i t.
1 = Bus Master IDE interface function, as a master, generated
a master-abort. R/WC
12 Received Target-Abort
Status (RTA) Set when the SATA Controller receives a target abort to a
cycle it g enerated.
11 Signal ed Target - A bo rt
Sta tu s (STA ) Reserved as ‘0. RO
10:9 DEVSEL# Timing Status
(DEVT) 01 = Hardwired; Controls the device select time for the SATA
Con trolle r’s PCI interfac e. RO
8Master Data Parity Error
Detected (DPD)
Set when the SA TA Co nt roll er, as a master, eit her detect s a
parity er ror or sees the parity e rror line asse rte d , a nd the
parity er ror re sponse bit (bit 6 of the command re gis te r) is
set. For the Intel® 63 00ES B ICH, this bit may only be set on
read completions when there is a parity error.
7Fast Back - t o- Bac k
Capable Reserved as1’. RO
6User D efi na ble Features
(UDF) Reserved as ‘0. RO
5 66MHz Capable Reserved as ‘1’. RO
4 Capabilitie s List (CL) Indicates the presence of a capabilities list. This bit is
hardwired to a ‘1’ indicating the p rese nce of a valid
capabilities po in te r at offs et 34h . RO
3:0 Reserved Reserved
Device: 31 Function: 2
Offset: 06-07h Attribute: Read/W rite Clear, Read-Only
Defau lt Value: 02B0h Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
742 Order Number: 300641-004US
20.1.5 Offset 09h: PI—Programming Interface (SAT A–
D31:F2)
20.1.6 Offset 0Ah: SCC—Sub Class Cod e (SATA–D31:F2)
Table 665. Offset 09h: PI—Programming Interface (SATAD31:F2)
Bits Name Description Access
7This rea d- only bit is a ’1’ to indica te that th e SATA Controller
suppo r ts bus mast er operati on RO
6:4 Re serv ed Res er ved . Wil l always retur n 0.
3SOP_MODE_CAP
This read- only bit is a ’1’ to indica te that the sec ond ary
contr oller suppo rts both le gacy and nat iv e m o des. RO
2SOP_MODE_SEL
This rea d-wr ite bit s determines the mode tha t the secondary
IDE chan ne l is op e rati ng in.
0 = Legacy -PCI mode (default )
1 = Native-PCI mod e
R/W
1 POP_MODE_CAP This re ad- only bit is a ’1’ to indica te that th e prim a ry
contr oller suppo rts both le gacy and nat iv e m o des. RO
0 POP_MODE_SEL
This rea d-wr ite bit s determines the mode that the pr ima ry
IDE chan ne l is op e ratin g in.
0 = Legacy -PCI mode (default )
1 = Native-PCI mod e
R/W
Table 666. Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2)
Bits Name Description Access
7:0 Sub Class Code
01h when Dev 31, Func 0, offset ACh, bit 23 is ‘0’; indica te s
IDE controller
04h when Dev 31, Func 0, offset ACh, bit 23 is ‘1’; indica te s
RAID controller
RO
Device: 31 Function: 2
Offset: 09h Attribute: Read/Write
Defau lt Value: 8Ah Size: 8-bit
Device: 31 Function: 2
Offset: 0Ah Attribute: Read-Only
Defau lt Value: 01h or 04h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 743
20—Intel® 6300ESB ICH
20.1 .7 Offset 0Bh: B CC—Base Class Code (SATA–D31:F2)
20.1 .8 Off set 0Dh: MLT—Master Latency Timer (SATA–
D31:F2)
Table 667. Offset 0Bh: BCC—Base Class Code (SATA–D31:F2)
Bits Name Description Access
7 :0 B a se Cla ss Code 01 = Mas s stora g e device RO
T abl e 66 8. O ffs e t 0Dh : MLT—Ma s ter La ten cy Tim e r (SA TA– D3 1 :F2 )
Bits Name Description Access
7:0 Bus Master Latency Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitr ated as a PCI device, so it does not
need a Master Latenc y Timer. RO
Device: 31 Function: 2
Offset: 0Bh Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Device: 31 Function: 2
Offset: 0Dh Attribute: Read-Only
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
744 Order Number: 300641-004US
20.1.9 Offse t 10h - 13h : P CMD_BAR—Primary Comma nd
Block
Base Address Register (SATA–D31:F2)
Note: This 8-byte I/O space is used in native mode for the Primary Controllers Command
Block.
20.1.10 Offset 14h - 17h: PCNL_BAR—Primary Control
Block Base
Address Registe r (SATA–D31:F2 )
Note: This 4-byte I/O space is used in native mode for the Primary Controller’s Control Block.
Table 669. Offset 10h - 13h: PCMD_BAR—Primary Command Block Base
Address Register (SATA–D31:F2)
Bits Name Description Access
31:1
6Reserved Reserved.
15:3 Base Address Base address of the I/O space (8 consecutive I/O locations). R/W
2:1 Reserved Reserved.
0Re so ur ce Typ e In di cat or
(RTE) This bit is set to ‘1’, indicating a request f or IO spa ce. RO
Table 670. Offset 14h - 17h: PCNL_BAR—Primary Control Block Base Address
Register (SATA–D31:F2)
Bits Name Description Access
31:1
6Reserved Reserved.
15:2 Base Address Base address of the I/O space (4 consecutive I/O locations). R/W
1 Reserved Reserved.
0 Re so ur ce Typ e In di cato r
(RTE) This bit is set to ‘1’, indicating a request f or IO spa ce. RO
Device: 31 Function: 2
Offset: 10h-13h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 2
Offset: 14h-17h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 745
20—Intel® 6300ESB ICH
20.1.11 Offset 18h - 1Bh: SCMD _BAR—Secondary
Command Block
Base Address Register (IDE D31:F1)
Note: This 4-byte I/O space is used in native mode for the Secondary Controller’s Control
Block.
20.1.12 Offset 14h - 17h: SCNL_B AR—Secondary Control
Block
Base Address Register (IDE D31:F1)
Note: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
Table 671. Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block Base
Address Register (IDE D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:3 Base Address Base addr ess of the I/ O space (8 consecutive I/O locations). R/W
2:1 Reserved Reserved.
0Resource Type Indicator
(RTE) This bit is set to ‘1’, indicating a re quest for IO space. RO
Table 672. Offset 14h - 17h: SCNL_BAR—Secondary Control Block Base
Address Register (IDE D31:F1)
Bits Name Description Access
31:1
6Reserved Reserved.
15:2 Base Address Base addr ess of the I/ O space (4 consecutive I/O locations). R/W
1 Reserved Reserved.
0Resource Type Indicator
(RTE) This bit is set to ‘1’, indicating a re quest for IO space. RO
Device: 31 Function: 2
Offset: 18h-1Bh Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 2
Offset: 14h-17h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
746 Order Number: 300641-004US
20.1.13 Offse t 20h - 23h: BAR—Legacy Bus Master Base
Address
Register (SATA–D31:F2)
Note: The Bus Master IDE interface functi on uses Base Address register 5 to request a 16-
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
20.1.14 Offse t 2Ch - 2Dh: SVI D—Subsystem Vendor ID
(SATA–D31:F2)
Table 673. Offset 20h - 23h: BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2)
Bits Name Description Access
31:1
6Reserved Reserved.
15:4 Base Address Base address of the I/O space (16 consecutive I/O locations). R/W
3:1 Reserved Reserved.
0Re so ur ce Typ e In di cat or
(RTE) Har dwi r ed to ’1’, i ndi cati ng a reques t for IO space. RO
Table 674. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SATA–D31:F2)
Bits Name Description Access
15:0 Subsyst em Vendor ID
(SVID)
The SVID reg ister, in com bina tion with the S u b syste m ID
(SID) register, enables the operating system (OS) to
distinguish s ubsystems from each other. Software (BIOS)
sets the value in this register. After that, the value may be
read, but su bs e quent wr ite s to this regis te r have no effe ct.
The value written to this register will also be readable through
the corresponding SVID registers for the USB#1, USB#2 and
SMBus func tions .
R/WO
Device: 31 Function: 2
Offset: 20h-23h Attribute: Read/Write
Defau lt Value: 00000001h Size: 32-bit
Device: 31 Function: 2
Offset: 2Ch-2Dh Attribute: Read/Write Once
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 747
20—Intel® 6300ESB ICH
20.1 .15 Offset 2Eh - 2Fh: S I D—Subsystem ID (SATA–
D31:F2)
20.1.16 Off set 34h: CAP —Capabilities Pointer Register
(SATA–D31:F2)
20.1 .17 Off set 3Ch: INTR _LN—Interrupt Line Register
(SATA–D31:F2)
Table 675. Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)
Bits Name Description Access
15:0 Subsystem ID (SID)
The SID register, in combination with the SVID regi ster,
enables the operating system (OS) to distinguish subsystems
from each other. Software (BIOS) sets the value in this
register. After that, the value may be read, but sub se q ue nt
writes to this register have no effect. The value written to this
registe r will also b e re adab le th rough the correspond in g S I D
regi ste rs for th e US B#1, USB# 2 a nd SMB u s fun ctions .
R/WO
Table 676. Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2)
Bits Name Description Access
7: 0 Capability Pointer (CP)
This bit indicates that the first capability pointer offset is 80h,
the MS I cap a bi lity. This value will be 70h if the MAP re g iste r
(offset 90h) indicates that the SATA and IDE functions are
comb ine d (values of 100, 101, 11 0, or 111).
RO
Table 677. Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2)
Bits Name Description Access
7 :0 In te rru p t Line It is to communicate to soft ware the inter rup t line that th e
interrupt pin is connected to. R/W
Device: 31 Function: 2
Offset: 2Eh-2Fh Attribute: Read/Write-Once
Defau lt Value: 00h Size: 16-bit
Lockable: No Power Well: Core
Device: 31 Function: 2
Offset: 34h Attribute: Read-Only
Defau lt Value: 80h Size: 8-bit
Device: 31 Function: 2
Offset: 3Ch Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
748 Order Number: 300641-004US
20.1.18 Offset 3Dh: INTR_PN—Interrupt P in Register
(SATA–D31:F2)
20.1.19 Offse t 4 0 - 41h: IDE_TIMP—Primary IDE Timing
Register
(SATA–D31:F2)
Note: This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
Table 678. Offset 3Dh: INTR_PN—Interrupt Pin Regi ster (SATA–D31:F2)
Bits Name Description Access
7:3 Reserved Reserved.
2:0 Interrupt Pin
The value of 01h indicates to “softwa re” that the Inte l®
6300E SB ICH will drive INTA#. Note that this is only use d in
native mode. Also note tha t the routing to the inte rnal
interrupt controller does not necessarily re late to the value in
this register.
RO
Table 679. Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA
D31:F2)
(Sheet 1 of 2)
Bits Name Description Access
15 IDE Decode Enable
(IDE)
Individ ually enable/disable the Primary or Secondary decode.
0 = Disabl e.
1 = Enables the Intel® 6300ESB ICH to d e code the
associated Comm and Blocks (1F0- 1F7h for primary, 170-
177h for secondary) and Control Block (3F6h for primary
and 376h for secondary).
This bit effec ts the IDE decode ran ges for both legacy and
native-Mode decoding.
R/W
14 Driv e 1 Timing Register
Enable (SITR E)
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:1 2, 9:8 f or d rive 0, and use the Slave IDE
Ti ming re gi ster for dr iv e 1 R/W
13:1
2IORDY Samp le Point
(ISP)
The setting of these bits det ermine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY
sam ple p oin t.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Device: 31 Function: 2
Offset: 3Dh Attribute: Read-Only
Defau lt Value: 01h Size: 8-bit
Device: 31 Function: 2
Offset: Primary: 40-41h
Secon dar y: 42 -43h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 749
20—Intel® 6300ESB ICH
11:1
0Reserved Reserved.
9:8 Recovery Time (RCT)
The setting of these bits determines the minimum number of
PCI clocks b e twe en the last IORDY samp le p oint and the
IOR#/IOW# strobe of the n e xt cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
R/W
7Dri ve 1 DMA Timi n g
Enable (DTE1)
0 = D isa b le .
1 = Enable the fast timing mode for DMA transfers only for
this drive . PIO transf er s to th e IDE d ata p ort will run in
compatible timing.
R/W
6Drive 1 Prefetch/Posting
Enable (PPE1)
0 = D isa b le .
1 = Enable Prefetch and posting to the IDE data port for this
drive. R/W
5Drive 1 IORDY S amp le
Point Enable (IE1) 0 = Disa b le IORDY sampling for this drive.
1 = Ena b le IORDY samp ling for this drive . R/W
4Drive 1 Fast Ti ming Bank
(TIME1)
0 = A cce sses to the d ata por t w ill use compatib le timin g s f or
this drive.
1 = Whe n this bit =’1’ and bit 14 = ’0’, acc esses to the d ata
port will use bits 13:12 for the IORDY sample point, and
bits 9:8 for the recovery time. When this bit = ’1’ and bit
14 = ’1’, accesses to the dat a port will u se th e IORDY
sam pl e poin t an d re cover time sp e cif ie d in th e sl ave IDE
timing register.
R/W
3Dri ve 0 DMA Timi n g
Enable (DTE0)
0 = D isa b le
1 = Enable fast timing mode for DMA transfers only for this
drive. PIO transf e rs to t he IDE data port will run in
compatible timing.
R/W
2Drive 0 Prefetch/Posting
Enable (PPE0)
0 = Disable pr efetc h a nd po sti ng t o the ID E data p ort fo r this
drive.
1 = Enable prefetch and posting to the IDE data port for this
drive.
R/W
1Drive 0 IORDY S amp le
Point Enable (IE0) 0 = Disa b le IORDY sa mp ling is disable d for this drive.
1 = Ena b le IORDY samp ling for this drive . R/W
0Drive 0 Fast Ti ming Bank
(TIME0)
0 = A cce sses to the d ata por t w ill use compatib le timin g s f or
this drive.
1 = A cce sses to the da ta por t will use b its 13:12 for the
IORDY sam pl e point, and b its 9:8 for the re cov e ry time .
R/W
Table 679. Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA–
D31:F2)
(Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 2
Offset: Primary: 40-41h
Secon dar y: 42 -43h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
750 Order Number: 300641-004US
20.1.20 IDE_TIMS—Secondary IDE Timing Re gister
(SATA–D31:F2)
Note: See the above register description for “Primary IDE Timing Register.
20.1.21 Offset 44h: SIDETIM—Slave IDE Timing Register
(SATA–D31:F2)
Table 680. Offset 44h: SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
Bits Name Description Access
7:6 Secondary Drive 1
IORDY Samp le Point
(SISP1)
Determines the number of PCI clocks between IDE IOR#/
IOW# ass ertion a nd the first IORDY sample p oint, whe n the
access is to driv e 1 data po rt a nd bit 14 of the IDE tim ing
reg iste r for seco n d a ry is se t.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
R/W
5:4 Secondary Drive 1
Recovery Ti me (SR CT1)
Determines the minimum number of PCI clocks between the
last IORDY sample poin t and the IOR#/IOW# strobe of the
nex t cycl e, when the access is to dri ve 1 dat a port and bit 14
of the I DE t iming r eg ister for sec ondar y is set .
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
R/W
3:2 Primary Dr ive 1 IORDY
Sample Point ( PISP1)
Determines the number of PCI clocks between IOR#/IOW#
assertion a nd the first IORDY sa mp le p oint, when the access
is to drive 1 dat a port and bi t 14 of the IDE ti ming regis ter for
primary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
R/W
1:0 Prima ry Driv e 1
Re covery Ti me (P RCT1)
Determines the minimum number of PCI clocks between the
last IORDY sample poin t and the IOR#/IOW# strobe of the
nex t cycl e, when the access is to dri ve 1 dat a port and bit 14
of the I DE t iming r eg ister for p rimar y is s et.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
R/W
Device: 31 Function: 2
Offset: 44h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 751
20—Intel® 6300ESB ICH
20.1.22 Offset 48h: SDMA_CN T—Synchronous DMA
Control Register (SATA–D31:F2)
Table 6 81. Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–
D31:F2)
Bits Name Description Access
7:4 Reserved Reserved.
3Secondary Drive 1
Synchronous DMA Mode
Enable (S SDE1)
0 = D isable (default)
1 = Enable Synchronous D MA mode for secondary channel
drive 1. R/W
2Secondary Drive 0
Synchronous DMA Mode
Enable (S SDE0)
0 = D isable (default)
1 = Enable Synchro nous DMA mode for secondary drive 0. R/W
1Primary Dri ve 1
Synchronous DMA Mode
Enable (PSDE1)
0 = D isable (default)
1 = Enabl e Sy nchro nous DMA mode for pr imary channel driv e
1. R/W
0Primary Dri ve 0
Synchronous DMA Mode
Enable (PSDE0)
0 = D isable (default)
1 = Enabl e Sy nchro nous DMA mode for pr imary channel driv e
0. R/W
Device: 31 Function: 2
Offset: 48h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
752 Order Number: 300641-004US
20.1.23 Offs et 4A - 4Bh: SDMA_T IM—Synchronous DMA
Timing Register (SATA–D31:F2)
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2) (Sheet 1 of 2)
Bits Name Description Access
15:1
4Reserved Reserved.
13:1
2Secon dary Driv e 1 Cy cle
Time (SCT1)
For Ultra ATA mode. The setting of these bits determines the
minim um write strobe cyc le time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
SC B1 = 0 ( 33MHz clk)
00 = CT 4 clocks, RP 6 cl ock s
01 = CT 3 clocks, RP 5 cl ock s
10 = CT 2 clocks, RP 4 cl ock s
11 = Reserved
SCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 cl ock s
10 = CT 2 clocks, RP 8 cl ock s
11 = Reserved
FAST _S C B1 = ’1’ (1 33 MH z clk )
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
R/W
11:1
0Reserved Reserved.
9:8 Secon dary Driv e 0 Cy cle
Time (SCT0)
For Ultra ATA mode. The setting of these bits determines the
minim um write strobe cyc le time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
SC B1 = 0 ( 33MHz clk)
00 = CT 4 clocks, RP 6 cl ock s
01 = CT 3 clocks, RP 5 cl ock s
10 = CT 2 clocks, RP 4 cl ock s
11 = Reserved
SCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 cl ock s
10 = CT 2 clocks, RP 8 cl ock s
11 = Reserved
FAST _S C B1 = ’1’ (1 33 MH z clk )
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
R/W
7:6 Reserved Reserved.
Device: 31 Function: 2
Offset: 4A-4Bh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 753
20—Intel® 6300ESB ICH
5:4 Primary Drive 1 Cycle
Ti m e ( P C T1)
For Ultra ATA mode, the setting of these bits determines the
mi ni mum write st robe cycle ti me (CT). The DMA R DY # -to-
STOP (RP) time is also determined by the setting of th ese
bits.
PCB1 = 0 (33MHz c lk )
00 = CT 4 cloc ks , RP 6 cloc ks
01 = CT 3 cloc ks , RP 5 cloc ks
10 = CT 2 cloc ks , RP 4 cloc ks
11 = Reserved
PCB1 = ’1’ (6 6MHz clk)
00 = Reserved
01 = CT 3 cloc ks , RP 8 cloc ks
10 = CT 2 cloc ks , RP 8 cloc ks
11 = Reserved
FAST_PCB1 = ’1’ (133MHz cl k)
01 = CT 3 clks, RP 16 cl ks
00 = Reserved
10 = Reserved
11 = Reserved
R/W
3:2 Reserved Reserved.
1:0 Primary Drive 0 Cycle
Ti m e ( P C T0)
For Ultra ATA mode, the setting of these bits determines the
mi ni mum write st robe cycle ti me (CT). The DMA R DY # -to-
STOP (RP) time is also determined by the setting of th ese
bits.
PCB1 = 0 (33MHz c lk )
00 = CT 4 cloc ks , RP 6 cloc ks
01 = CT 3 cloc ks , RP 5 cloc ks
10 = CT 2 cloc ks , RP 4 cloc ks
11 = Reserved
PCB1 = ’1’ (6 6MHz clk)
00 = Reserved
01 = CT 3 cloc ks , RP 8 cloc ks
10 = CT 2 cloc ks , RP 8 cloc ks
11 = Reserved
FAST_PCB1 = ’1’ (133MHz cl k)
00 = Reserved
01 = CT 3 clks, RP 16 cl ks
10 = Reserved
11 = Reserved
R/W
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 2
Offset: 4A-4Bh Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
754 Order Number: 300641-004US
20 .1.24 Offset 54h: IDE_CONFIG—IDE I/O Confi guration
Register (SATA–D31:F2)
Table 683. Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–
D31:F2) (Sheet 1 of 2)
Bits Name Description Access
31:2
4Reserved Reserved.
23:2
0Sc ra t ch pad ( SP2 ) The I n t el® 6 300ES B ICH do e s not perfo rm any actions on
these bits.
19:1
8Reserved Reserved. R/W
17:1
6Reserved Reserved. R/W
15 FAST_SCB 1: Fast
S eco nda ry Dr i ve 1 Ba se
Clock
This bit is use d in conjunction wi th the SCT 1 b its to e na b le /
disable Ultra ATA/100 timings for the Secondary Slav e drive.
0 = Disabl e Ultra ATA/100 timing for the Secondary Sl ave
drive.
1 = Enabl e Ultra ATA/100 timing for the Second ary Sl ave
drive (overr ides bit 3 in this register).
R/W
14 FAST_SCB 0: Fast
S eco nda ry Dr i ve 0 Ba se
Clock
This bit is use d in conjunction wi th the SCT 0 b its to e na b le /
disable Ultr a AT A/100 timings for the Secondary Master driv e.
0 = Disabl e Ultra ATA/100 timing for the Secondary Ma ster
drive.
1 = Enabl e Ultra ATA/100 timing for the Second ary Ma ster
drive (overr ides bit 2 in this register).
R/W
13 FAST_ PCB 1: Fast
Primary Drive 1 Base
Clock
This bit is used in conjunction wi th th e PCT1 bits to enable/
disable Ultra ATA/100 timings for the P rimar y Slave drive.
0 = Disabl e Ultra ATA/100 timing for the Primary Slave drive .
1 = Enabl e Ultra ATA/100 timi ng for the Primary Slave drive
(overrides b it ’ 1’ in th is re g ister).
R/W
12 FAST_ PCB 0: Fast
Primary Drive 0 Base
Clock
This bit is used in conjunction wi th th e PCT0 bits to enable/
disable Ultra ATA/100 timings for the Primary Master drive.
0 = Disabl e Ultra ATA/100 timing for the Primary Ma ster
drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive
(overrides b it ’ 0’ in th is re g ister).
R/W
11:8 Reserved Reserved.
7:4 Scratchpad (SP1) The Intel® 6300ESB ICH does not perform an y action on
these bits.
3SCB1: Secondary Drive
1 Base Clock 0 = 33 MH z base clock for U ltra ATA tim ings.
1 = 66 MHz ba se cloc k for Ultra ATA timing s R/W
Device: 31 Function: 2
Offset: 54h Attribute: Read-Write
Defau lt Value: 00h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 755
20—Intel® 6300ESB ICH
20.1.25 Offset 70 - 71h: PID—PCI Power Management
Capability ID (SATA–D31:F2)
20.1 .26 Off set 72 - 73h: PC—PCI Power Management
Capabilities (SATA–D31:F2)
2SCBO: Secondar y Drive
0 Base Clock 0 = 33 MH z base clock for Ultra ATA timing s.
1 = 66 MHz base cl ock for Ultra ATA timing s R/W
1PCB1: Pri mary Dr ive 1
Base Clock 0 = 33 MHz ba se clock for Ul tra ATA timings.
1 = 66 MHz base cl ock for Ultra ATA timing s R/W
0PCB0: Pri mary Dr ive 0
Base Clock 0 = 33 MHz ba se clock for Ul tra ATA timings.
1 = 66 MHz base cl ock for Ultra ATA timing s R/W
Table 684. Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–
D31:F2)
Bits Name Description Access
15:8 Next Cap ab ility (NEXT) Indicate s th at this is the la st ite m in the lis t
7: 0 Cap ID (CID) Indicates that this p ointe r is a PCI power managem e nt.
Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA
D31:F2)
Bits Name Description Access
15:1
1PME_Support Indica te s PME# canno t be generated fo rm the SATA ho s t
controller. When in low power state, resume events are not
allowed.
10 D2_Support The D2 state is not supported
9 D1_Support The D1 stat e is not supported
Table 683. Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–
D31:F2) (Sheet 2 of 2)
Bits Name Description Access
Device: 31 Function: 2
Offset: 54h Attribute: Read-Write
Defau lt Value: 00h Size: 32-bit
Device: 31 Function: 2
Offset: 70-71h Attribute: Read-Only
Defau lt Value: 0001h Size: 16-bit
Device: 31 Function: 2
Offset: 72-73h Attribute: Read-Only
Defau lt Value: 0002 Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
756 Order Number: 300641-004US
20.1.27 Offse t 7 4 - 75h: PMCS—PCI Power Man a gement
Control and Status (SATA–D31:F2)
8:6 Aux_Current Reports 375mA maxim u m S u sp e n d well cu rre nt re quired
when in the D 3cold state.
5Device Specific Initial-
ization (DS I) Indicates that no device-specific initialization is required.
4 Reserved Reserved.
3 PM E Clock (PM EC) Indicate s that PCI clock is not required to generate PME#.
2:0 V ersion (V S) Indicate s support for Revision 1.1 of the PCI Power
Manag e me n t S pecification.
Table 686. Offset 74 - 75h: PMCS—PCI Power Management Control and Status
(SATA–D31:F2)
Bits Name Description Access
15 PME Status (PMES) Reserved as ‘0’.
14:9 Reserved Reserved.
8 PME Enable (PMEE). Reserved as ‘0’.
7:2 Reserved Reserved.
1:0 P o we r Stat e (PS)
Pow er St ate (PS ). These bits are used both to determine
the current power state of the SATA Controller and to set a
new powe r state.
00: D0 state
01: D1 state
10: D2 state
11: D3hot stat e
Wh e n in the D3 hot sta te, th e controll er s co n f igurat io n s pa ce
is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked.
Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–
D31:F2)
Bits Name Description Access
Device: 31 Function: 2
Offset: 72-73h Attribute: Read-Only
Defau lt Value: 0002 Size: 16-bit
Device: 31 Function: 2
Offset: 74-75h Attribute: Read-Only, Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 757
20—Intel® 6300ESB ICH
20. 1.28 Offs et 80 - 81h: MID—M essage S ignaled Int errupt
Identifie r s (SATA–D31:F2)
20.1.29 Offset 82 - 83h: MC—Message Sign aled Interrupt
Message Control (SAT A–D31:F2)
Table 687. Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers
(SATA–D31:F2)
Bits Name Description Access
15:8 Next Pointe r (N EX T) Ind icates that the next item in the list th e PCI pow er
m a nageme nt po in ter.
7:0 Capability ID (CID) Capab ility ID indicates MS I.
Table 688. Offset 82 - 83h: MC—Message Signaled Interrupt Message Control
(SATA–D31:F2)
Bits Name Description Access
15:8 Reserved Reserved.
764 Bit Address Capable
(C64) Capable of generating 32-bit message only. RO
6:4 Multiple Message Enable
(MME) These bits are R/W for software compatibility, but only one
message is ever sent by the Intel® 6300ESB ICH. R/W
3:1 Multiple Me ssa g e
Capabl e ( MMC) Only one me ssage is required. RO
0 MS I Enab le (MSIE) 0 = D isa b le d .
1 = MSI is enabled and traditional interrupt pins are not used
to gene rate interr upts . R/W
Device: 31 Function: 2
Offset: 80-81h Attribute: Read-Only
Defau lt Value: 7005h Size: 16-bit
Device: 31 Function: 2
Offset: 82-83h Attribute: Read-Only, Read/Write
Defau lt Value: 0000h Size: 16-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
758 Order Number: 300641-004US
20.1.30 Offset 84 - 87h: MA— Message Signaled Int errupt
Message Address (SATA–D31:F2)
Table 689. Offset 84 - 87h: MA—Message Signaled Interrupt Mess age Address
(SATA–D31:F2)
Bits Name Description Access
31:2 Address (ADDR) Lowe r 3 2 bits of the system spe cif ied message address,
alw a ys DWO R D ali g ne d.
1:0 Reserved Reserved.
Device: 31 Function: 2
Offset: 84-87h Attribute: Read/Write
Defau lt Value: 0000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 759
20—Intel® 6300ESB ICH
20.1.31 Offset 88 - 89h: MD—Message Signaled Interrupt
Message Data (SATA–D31:F2)
20.1.32 Offset 90h: MAP—Address Map (SA TA–D3 1:F2)
Table 690. Offset 88 - 89h: MD—Message Signaled Interrupt Message Data
(SATA–D31:F2)
Bits Name Description Access
15:0 D ata (DATA)
This field is programmed by system software when MSI is
enabled. Its content is driven onto the lower word ( PCI
AD[15:0]) during the data phase of the MSI memory write
transaction.
T abl e 69 1. Of fs e t 90h : MAP Ad dr e ss Map (SA T A– D3 1: F 2 )
Bits Name Description Access
7:3 Reserved Reserved.
2:0 Map Value
The value of these bits indicate the address range the SATA
port responds to, and whe th e r or not the SATA and ID E
functions are combine d.
000 = Non-com bi n ed. P 0 is primar y ma ste r. P1 is se conda ry
master.
001 = Non - combined. P0 is se con d a ry mast er. P 1 is primary
master.
100 = Combined. P0 is primary master. P1 is primary slave.
P-ATA is secondary.
101 = Comb ine d. P0 is primar y slave . P1 is pr ima ry ma ster.
P-ATA is secondary.
110 = Comb ine d. P-ATA is primary. P0 is secondary master.
P1 is secondary slave.
111 = Combined . P-ATA is primary. P0 is seco n dar y slave. P1
is secon d a r y ma s ter.
R/W
Device: 31 Function: 2
Offset: 88-89h Attribute: Read/Write
Defau lt Value: 0000h Size: 16-bit
Device: 31 Function: 2
Offset: 90h Attribute: Read-Only, Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
760 Order Number: 300641-004US
20.1.33 Offset 92h: PCS—Port Status and Control ( SAT A–
D31:F2)
20.1.34 Offset A0h: SRI—SATA Registers Index (SATA
D31:F2)
Ta ble 692. Offset 92h: PCS—Port Status and Control (SATA–D31:F2)
Bits Name Description Access
15:6 Reserved Reserved.
5Reserved
Reserved. Bit is Read Only, re set to ’0’ b u t may be ’1’ at any
given t ime
4Reserved
Reserved. Bit is Read Only, re set to ’0’ b u t may be ’1’ at any
given t ime.
3:2 Reserved Reserved.
1Port 1 Enabled (P1E)
0 = The port is disabled. The port is in the ‘off’ state and
cannot d e t e ct a n y devices.
1 = The port is enabled. The port may transition between the
on, partial, and slumber states and may detect devices.
0Port 0 Enabled (P0E)
0 = The port is disabled. The port is in the ‘off’ state and
cannot d e t e ct a n y devices.
1 = The port is enabled. The port may transition between the
on, partial, and slumber states and may detect devices.
Table 693. Offset A0h: SRI—SATA Registers Index (SATA–D31:F2)
Bits Name Description Access
7 Reserved Reserved.
6:0 Index (IDX) This field is a 7-b it ind e x poin te r in to the SATA Registe rs
space. Data is written into the SRD register (D31:F2:A4h) and
read from the SRD register. R/W
Device: 31 Function: 2
Offset: 92h Attribute: Read/Write
Defau lt Value: 000h Size: 16-bit
Device: 31 Function: 2
Offset: A0h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 761
20—Intel® 6300ESB ICH
20.1.35 Off se t A4h - A7h : SRD—SA TA Regist ers Data
(SATA–D31:F2)
Index Name
00h–01h SATA TX Termination Test Register (STT)
02h–1Dh Reserved
1Eh SAT A TX Output Test Register (ST OT)
1Fh–53h Reserved
54h–57h SError Register Port 0 (SER0)
58h–63h Reserved
64h–67h SError Register Port 1 (SER1)
68h–FFh Reserved
Tabl e 694. Offset A4h - A7h: SR D— SATA Re giste rs Data (SAT A–D3 1:F2 )
Bits Name Description Access
31:0 Data (D TA) This f ield is a 32-bi t data value that is writte n to the re gi ster
pointed to by SRI (D3 1:F2:A0h) or read from the register
pointed to by SRI. R/W
Table 693. Offset A0h: SRI—SA TA Registers Index (SATA –D3 1:F2)
Bits Name Description Access
Device: 31 Function: 2
Offset: A0h Attribute: Read/Write
Defau lt Value: 00h Size: 8-bit
Device: 31 Function: 2
Offset: A4h–A7h Attribute: Read/Write
Defau lt Value: XXh Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
762 Order Number: 300641-004US
20.1.36 STTT—SATA TX Termination Test Re gister A
(SATA–D31:F2)
20.1.37 STOT — SATA TX Output Test Register (SATA–
D31:F2)
Table 695. STTT—SATA TX Termination Test Register A (SATA–D31:F2)
Bits Name Description Access
15:2 Reserved Reserved.
1Port 1 TX Termina tion
Test Enable
Settin g this bi t will e n able testing of the port’s TX
termination. T his b it is on ly to be u sed for syste m board
testing. R/W
0Port 0 TX Termina tion
Test Enable
Settin g this bi t will e n able testing of the port’s TX
termination. T his b it is on ly to be u sed for syste m board
testing. R/W
Table 696. STOT — SATA TX Output Test Register (SATA–D31:F2)
Bits Name Description Access
15:2 Reserved Reserved.
1Force ALIGN TX Bit
This bit will fo rce the In tel® 6300ESB ICH to rep eatedly
tr ansmit the SA TA ALIGN primitive when set. This bit is only
used fo r system board test i ng. R/W
0 Reserved Reserved. R/W
Device: 31 Function: 2
Index
Address: Index 00h–01h Attribute: Read/Write
Defau lt Value: XXXXh Size: 16-bit
Device: 31 Function: 2
Index
Address: Index 1Eh Attribute: Read/Write
Defau lt Value: XXXXh Size: 16-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 763
20—Intel® 6300ESB ICH
20.1.38 Offset Index 54h - 57h: SER0—SATA SError
Regis ter Port 0 ( S ATA–D31:F2)
20.1.39 Offset Index 64h - 67h: SER1—SATA SError
Regis ter Port 1 ( S ATA–D31:F2)
20.1.40 Offset E0h - E3h: BFCS—BIST FIS Control/Status
Register (SATA–D31:F2)
Table 697. Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–
D31:F2)
Bits Name Description Access
31:0 SER0 This regis ter is implemente d in accordan ce with the SERRO R
register description in Section 10.1.2 of the SATA 1.0
Specification.R/W
Table 698. Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–
D31:F2)
Bits Name Description Access
31:0 SER1 This regis ter is implemente d in accordan ce with the SERRO R
register description in Section 10.1.2 of the SATA 1.0
Specification.R/W
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
D31:F2)
(Sheet 1 of 3)
Bits Name Description Access
31:1
2Reserved Reserved.
Device: 31 Function: 2
Offset: Index 54h–57h Attribute: Read/Write
Defau lt Value: XXXXXXXXh Size: 32-bit
Device: 31 Function: 2
Offset: Index 64h–67h Attribute: Read/Write
Defau lt Value: XXXXXXXXh Size: 32-bit
Device: 31 Function: 2
Offset: E0h–E3h Attribute: Re ad/Write, Read /Write Clear
Defau lt Value: 00000000h Size: 32-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
764 Order Number: 300641-004US
11 BIST FIS Successful
(BFS)
0 = Softwar e c lea rs this bit by wr iting a ’1’ to it.
1 = This bit is set any time a BI ST FIS transmitte d by the
Intel® 6300ESB ICH receives an R_OK completion status
from the device.
NOTE: This bit must be cleared b y software prior to initiating
a BIST FIS.
R/WC
10 BIST FIS Failed (BFF)
0 = Softwar e c lea rs this bit by wr iting a ’1’ to it.
1 = This bit is set any time a BI ST FIS transmitte d by the
Intel® 63 00ES B ICH rece ives an R_ER R comp letion
status from the device.
NOTE: This bit must be cleared b y software prior to initiating
a BIST FIS.
R/WC
9Port 1 BIST FIS Initiate
(P1BFI)
When a rising edge is detec te d on thi s bit field, the Inte l®
6300E SB ICH initiates a BIST FIS to the devic e on Port 1,
using the parameters specified in this register and the data
specified in BFTD1 and BFTD2. The BIST FIS will only be
initiated if a device on Port 1 is present and re a d y (not
partial/slumber state). After a BIST FIS is successfully
completed, software must disable and re-enable the port
using the PxE bits at offset 92h prior to attempting add itional
BIST FISes or to return the Inte l® 6300ES B ICH to a normal
operational mod e . If the B IS T FIS fai ls to com p le te , as
indicated by the BF F bit in the register, then softwa re can
clear then set the P1B FI b it to initiate an other BIST FIS. This
can be retrie d unti l th e BIST FIS eventua lly complete s
successfully.
R/W
8Port 0 BIST FIS Initiate
(P0BFI)
When a rising edge is detec te d on thi s bit field, the Inte l®
6300E SB ICH initiates a BIST FIS to the devic e on Port 0,
using the parameters specified in this register and the data
specified in BFTD1 and BFTD2. The BIST FIS will only be
initiated if a device on Port 0 is present and re a d y (not
partial/slumber state). After a BIST FIS is successfully
completed, software must disable and re-enable the port
using the PxE bits at offset 92h prior to attempting add itional
BIST FISes or to return the Inte l® 6300ES B ICH to a normal
operational mod e . If the B IS T FIS fai ls to com p le te , as
indicated by the BF F bit in the register, then softwa re can
clear then set the P0B FI b it to initiate an other BIST FIS. This
can be retrie d unti l th e BIST FIS eventua lly complete s
successfully.
R/W
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
D31:F2)
(Sheet 2 of 3)
Bits Name Description Access
Device: 31 Function: 2
Offset: E0h–E3h Attribute: Read/Write, Read/Write Clear
Defau lt Value: 00000000h Size: 32-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 765
20—Intel® 6300ESB ICH
20.1.41 Offset E4h - E7h: BFTD1—BIST FIS Transmit
Data1 Registe r (SATA–D31:F2)
7:2 BIST FIS Parameters
These 6 bits form the contents of the upper 6 bits of the BIST
FIS Pattern Defi nition in an y BIST FIS transmitted by the
Intel® 6300ESB ICH. This field is not port spe cif ic — its
conten ts will be used for an y BIST FIS initi at ed on port 0 on
port 1. The s pecific bi t definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A Align Bypass mode
Bit 5: S Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Prim itive b it fo r use with Transm it mode
1:0 Reserved Reserved.
Table 700. Offset E4h - E7h: BF TD1—BIST FIS Transmit Data1 Register (SATA
D31:F2)
Bits Name Description Access
31:0 BIST FIS Transmit Data
1
The data progr ammed into this register will form the contents
of the second DWord of any BIST FIS initia te d by the Intel®
6300ESB ICH. This register is not port sp ecific — its contents
wi ll be us ed for BI ST FIS initia ted o n po r t 0 or po rt 1 .
Although the 2nd and 3r d DWs of the BIS T FIS are only
meaningful when the ‘T’ bit of the BIST FIS is set to indic ate
“Far-End Transmit mode , this re g ister’s contents will be
transmitted as the BIST FIS 2nd DW regardless of whether or
not the ‘T’ bit is indic ate d in the BFCS re gi ster.
R/W
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
D31:F2)
(Sheet 3 of 3)
Bits Name Description Access
Device: 31 Function: 2
Offset: E0h–E3h Attribute: Re ad/Write, Read /Write Clear
Defau lt Value: 00000000h Size: 32-bit
Device: 31 Function: 2
Offset: E4h–E7h Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
20—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 766
20.1.42 Offse t E8h - EBh: BFTD2—BIST FIS
Transmit Data2 Register (SATA–D31:F2)
20 .2 Bus M ast er IDE I/O Register s (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated through the BMIBA
register, located in Device 31:Function 1 Configuration space, offset 20h. All bus
master IDE I/O space registers ma y be accessed as byte, word, or DWORD quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no affect (but should not be attempted). The description of the I/O
registers is shown below in Table 702.
Table 701. Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Register (SATA–
D31:F2)
Bits Name Description Access
31:0 BIST FIS Transmit Data
2
The dat a progr ammed into thi s register will f orm the conte nts
of the third DWord of any BIST FIS initiated by the Intel®
6300ES B ICH. This register is not port specific — its contents
will be use d for B IS T FIS initiate d on port 0 or port 1.
Although the 2nd and 3rd DWs of the BIST FIS ar e only
meaningf ul whe n the ‘T’ bit of the BIS T FIS is set to ind icate
“Far-End Transmit mode”, this regis te r’s con te nts wi ll be
tr ansmitted as the BIST FIS 3rd DW regardless of whether or
not the ‘T’ bit is indicated in the BF CS regis ter.
R/W
Device: 31 Function: 2
Offset: E8h–EBh Attribute: Read/Write
Defau lt Value: 00000000h Size: 32-bit
Table 702. Bus Master IDE I/O Registers
Offset Mnemonic Register Default Type
00 BM ICP Comman d Register Primary 00h R/W
01 Reserved RO
02 BMISP Status Register Primary 00h R/WC
03 Reserved RO
04- 07 BMID P Descr ipt or Table Poin te r Prima ry xx R/W
08 B M I CS Co mma n d Reg ister Secondar y 00h R/W
09 Reserved RO
0A BMIS S Sta tus Register Se co ndary 0 0h R/W C
0B Reserved RO
0 C-0F BM I DS De scriptor Tabl e Poin ter Seconda ry x x R/W
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 767
20—Intel® 6300ESB ICH
20.2 .1 BMIC[P,S]—Bus Master IDE Command Register
(D31:F2)
Table 703. BMIC[P,S]— Bus Master IDE Comm and Register (D31:F2)
Bits Name Description Access
7:4 Reserved Reserved. Returns ’0’.
3Read / Write Control
(RWC)
This bit sets the direction of the bus master transfer: This bit
must NOT be ch an ged when the bus m a ster func t i on is a cti ve .
0 = Memory reads
1 = Memory writes
R/W
2:1 Reserved Reserved. Returns ’0’.
0Start/Stop Bus Master
(START)
0 = A ll state in f ormation is lost when this b it is cleared.
Maste r mode operat ion ca nnot be stopped an d the n
resumed. When th is bit is res e t while bus mast er
operation is still active (i.e. , the Bus Master IDE Activ e bit
of the Bus Master IDE Status register for that IDE
channe l is set) and the drive has not yet finished its data
transfer (the Inte rrup t bit in the Bus Maste r IDE Status
register for tha t ID E channe l is not set), the bus master
co mmand is said to b e aborted an d data tr ansf erred from
the dr ive may be discarded instead of being written to
system memory.
1 = Enables bus master operation of the controller. Bus
mas te r op eration begins when this bit is detect ed
chang ing from a ’0’ to a 1’. The controller will transf e r
data between the I D E dev ice and memory onl y w hen th i s
bit is se t. Master operation may be halted by writing a '0'
to this bit.
NOTE: This bit is intended to be cleared by software after the
data transf er is com pl eted, as ind ic a te d by either the
Bus Master IDE Active bi t being clear ed or the
Interrupt bit of the Bus Master IDE Status register for
that IDE channe l b e ing set, or bo th. H ard ware does
not cle ar this b it au tomatically.
R/W
Device: 31 Function: 2
Offset: Primary : 00h
Secondary: 08h Attribute: Read/Write
Defau lt Value: 01h Size: 8-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
768 Order Number: 300641-004US
20.2.2 BMIS[P,S]—Bus Master IDE Status Regis ter
(D31:F2)
Table 704. BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
Bits Name Description Access
7PRD Interrupt Status
(PRDIS)
0 = Wh en this bit is clea re d by softwa re , the inte rrupt is
cleared.
1 = This bit is set when the host cont rol execution of a PRD
that h a s its P RD_INT bit set.
R/WC
6 Drive 1 DMA Capable
0 = Not Capa ble.
1 = Capable. Set by device dependent code (BIOS or device
driver) to indicate that drive 1 for this channel is capable
of DMA trans fers, and th at the controller has been
initialized for optimum performance. The Intel® 6300ESB
ICH does not use this bit. It is intend e d for syste ms th at
do not attach BMIDE to the PCI bus.
R/W
5 Drive 0 DMA Capable
0 = Not Capa ble
1 = Capable. Set by device dependent code (BIOS or device
driver) to indicate that drive 0 for this channel is capable
of DMA trans fers, and th at the controller has been
initialized for optimum performance. The Intel® 6300ESB
ICH does not use this bit. It is intend e d for syste ms th at
do not attach BMIDE to the PCI bus.
R/W
4:3 Reserved Reserved. Re tu rns ’0’.
2Interrupt
Software may use this bit to dete rmine if an IDE device has
asserted its interru p t lin e (IRQ 14 f or the Primary chan ne l,
and IRQ 15 f or Secondary ).
0 = This bit is cleared by software writing a '1' to the bit
position . When this bit is cleare d while the inte rrup t is
still ac tive, this bit will re ma in cle a r until another
assertion e dge is d etec ted on the inter rup t line.
1 = Set by the rising edge of the IDE interrupt line,
regardl ess of whe the r or not the inte rrupt is masked in
the 8259 or the internal I/O APIC. When this bit is rea d
as a ‘1’, all data transferred from the d rive is visible in
syste m memory.
R/WC
1Error
0 = This bit is cleared by software writing a '1' to the bit
position.
1 = This bit is set when the controller encounters a target
abort or master abort when transf er ring data on PCI.
R/WC
0Bus Master IDE Active
(ACT)
0 = This bit is cleared by the Intel® 6300ESB ICH when the
last trans fer for a region is performed, where EOT fo r that
reg ion is s et in the region des cri pto r. It is also clear ed by
the Int el® 6300ES B ICH whe n the S ta rt bit is cleared in
the Command register. When this bit is read as a ’0’, all
data transferre d f rom the d rive d uring the pr evious bus
master command is visible in system memory , unless the
bus master command was aborted.
1 = Set by the Intel® 6300ESB ICH when the Start bi t is
written to the Command reg ister.
RO
Device: 31 Function: 2
Offset: Primary : 02h
Secondary: 0Ah Attribute: Read/Write Clear
Defau lt Value: 00h Size: 8-bit
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 769
20—Intel® 6300ESB ICH
20.2 .3 BMID[P,S]— Bus Master IDE D escrip tor Ta ble
Pointer Register (D31:F2)
Table 705. BM ID[P,S]—Bus Master IDE Descriptor Table Pointer Register
(D31:F2)
Bits Name Description Access
31:2 Ad dr e ss of Descriptor
Table (ADDR)
Corresponds to A[31:2]. The Des criptor Table must be
DWO R D-aligned. The Descriptor Table mu st not cross a 64-K
boundary in me mory. R/W
1:0 Reserved Reserved.
Device: 31 Function: 2
Offset: Primary : 04h
Secondary: 0Ch Attribute: Read/Write
Defau lt Value: All bits undefined Size: 32-bit
Intel® 6300ESB ICH—20
Intel® 6300ESB I/O Controller Hub
DS November 2007
770 Order Number: 300641-004US
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 771
21—Intel® 6300ESB ICH
Package Information 21
21.1 Ball Location
Figure 36. Ball Diagram (Top View - Left Side)
12 34567891011121314
A VSS AD[16] AD[20] PIRQ[B]# VSS GPIO[5] /
PIRQ[H]# PIRQ[C]
#GPIO[3]
/
PIRQ[F]# NC NC NC LAD[3]
B VSS AD[7] AD[11] STOP# AD[22] AD[18] PIRQ[D]# VSS GPIO[2]
/
PIRQ[E]
#REQ[2]# NC NC LFRAME
#
C VSS C/BE[0]# AD[2] VSS Vcc3_3 VSS AD[15] VSS Vcc3_3 VSS GNT[2]# VSS Vcc3_3 VSS
D AD[14] PERR# Vcc3_3 AD[5] AD[9] AD[6] VSS REQ[0]# GNT[1]# GPIO[4]
/
PIRQ[G]
#VSS REQ[3]
#VSS THRM#
E AD[17] AD[10] IRDY# SERR# VSS Vcc3_3 AD[26] AD[24] Vcc3_3 GNT[0]# V5REF PIRQ[A]
#NC VSS
F AD[27] AD[19] VSS C/BE[2]# AD[3] AD[13] VSS VSS TRDY# AD[4] VSS Vcc1_5 NC LDRQ[0]
#
GGPIO[33] /
PXIRQ[0]# AD[31] Vcc3_3 VSS DEVSEL# AD[12] C/BE[1]# AD[1] PAR FRAME# AD[30] REQ[1]
#GNT[3]
#LDRQ[1]
#
HGPIO[34] /
PXIRQ[1]# GPIO[35] /
PXIRQ[2]# Vcc3_3 AD[29] C/BE[3]# VSS AD[23] AD[8] Vcc3_3 VSS AD[0] AD[28]
JGPIO[0] /
PXREQ[2]
#PXPCLKO[0
]GPIO[36] /
PXIRQ[3]# VSS PCICLK PLOCK# Vcc3_3 Vcc1_5
K PXGNT0# PXAD[31] Vcc3_3 PXPCLKO[3
]Vcc3_3 PXPCLKO[
2] AD[25] AD[21]
L PXAD[27] PXREQ[0]# PXAD[28] VSS PXPCLKO[
4] PXREQ[1]
#VSS PXPCLKO[
1]
M PXAD[25] PXAD[26] VSS Vcc3_3 PXAD[30] VSS PXAD[29] Vcc3_3 VSS VSS VSS
N PXAD[22] PXAD[20] PXAD[23] PXAD[24] Vcc3_3 PXC/
BE[3]# Vcc1_5 VSS VSS VSS
P PXAD[17] PXAD[18] VSS Vcc3_3 PXAD[19] VSS PXAD[21] VSS VSS VSS
R PXAD[16] PXC/BE[2]# Vcc3_3 PXIRDY# Vcc3_3 PXFRAME# PXPCIXCAP VSS VSS VSS
TPXPLOCK#PXSTOP# PXDEVSEL
#VSS PXTRDY# VSS PXAD[15] VSS VSS VSS
U PXSERR# PXC/BE[1]# VSS PXPAR Vcc3_3 PXPERR# Vcc3_3 VSS VSS VSS
V PXAD[12] PXAD[11] VSS PXAD[13] VSS VCCREF PXAD[2] Vcc1_5 VSS VSS VSS
W PXAD[8] PXAD[9] Vcc3_3 PXM66EN Vcc3_3 Vcc3_3 PXAD[1] PXAD[5]
Y PXAD[14] PXAD[6] VSS PXAD[3] VSS PXAD[43] GPI O[17] /
PXGNT[3]# GPIO[1] /
PXREQ[3]
#
AA PXC/
BE[0]# PXAD[4] Vcc3_3 PXAD[10] Vcc3_3 PXAD[7] PCIXSBRST
#VCCPLL0
AB PXAD[47] PXAD[45] PXAD[42] VSS PXGNT1# Vcc3_3 PXAD[44] Vcc1_5 PXAD[54
]Vcc1_5 Vcc3_3 VSS
AC PXAD[46] GPIO[16] /
PXGNT[2]# VSS PXPCLKI PXPCICLK PXAD[39] VSS VCCREF Vcc3_3 PXAD[50
]VSS PXRCOM
PVcc1_5 GPIO[13]
AD PXAD[41] PXAD[40] Vcc3_3 PXAD[38] VSS PXAD[37] PXAD[36] PXPAR64 VSS PXAD[48
]VSS VSS NC SLP_S4#
AE RASERR# PXAD[35] PXAD[34] PXAD[33] PXREQ64
#VSS PXC/
BE[4]# Vcc3_3 PXAD[51
]PXAD[49
]Vcc3_3 GPIO[8] VSS GPIO[24]
AF PXAD[32] PXAD[0] VSS PXACK64# Vcc3_3 PXC/
BE[7]# PXC/
BE[6]# VSS PXAD[53
]VSS GPIO[12] VSS VccSus
3_3 VSS
AG VSS PXC/BE[5]# Vcc3_3 VSS PXAD[60] VSS Vcc3_3 VSS VSS GPIO[27] VSS VccSus3
_3 VSS SLP_S3#
AH VSS PXAD[63] PXAD[62] PXAD[59
]PXAD[57] PXAD[55] PXPCIRST
#GPIO[25
]RI# SYSRESE
T# SMLIN
K[1] SMLIN
K[0] SMBCLK
AJ VSS PXAD[61] PXAD[58
]PXAD[56] PXAD[52] PME# GPIO[28
]PWRBTN
#SLP_S5# SUSCL
KSMBD
ATA NC
1234567891011121314
Intel® 6300ESB ICH—21
Intel® 6300ESB I/O Controller Hub
DS November 2007
772 Order Number: 300641-004US
Figure 37. Ball Diagram (Top View - Right Side)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
LAD[2] SIU0_RI# SIU0_TXD UART_CLK SIU1_DCD
#SIU1_CTS
#NC NC VccSus3_3 USBP3P VSS USBP2P VSS A
LAD[1] SIU0_DCD
#SIU0_RXD SIU1_DTR
# SIU1_DSR
#NC NC GPIO[7] VccSus3_3 USBP3N VSS USBP2N VSS VSS B
LAD[0] VSS Vcc3_3 VSS SIU1_TXD VSS GPIO[6] GPIO[56] VccSus3_3 VSS USBP1N VSS USBP0P VSS VSS C
Vcc3_3 SIU0_CTS
#SIU1_RI# SIU1_RXD NC GPIO[37] VccSus1_5 GPIO[57] VccSus3_3 VccSus3_3 USBP1P VSS USBP0N VSS USBRBIAS
ND
SIU0_DTR
#VSS SIU0_DSR
#VSS GPIO[39] AC_SDOU
TAC_SDIN1 AC_SDIN2 AC_RST# OC[3]# VSS VSS VSS USBRBIAS
PCLK48 E
VSS SIU0_RTS
#VSS VSS VSS AC_SYNC VccSus1_5 AC_SDIN0 OC[1]# OC[0]# VSS VSS NC NC GPIO[38] F
Vcc3_3 SIU1_RTS
# SERIRQ NC AC_BIT_C
LK Vcc1_5 VccSus3_3 V5REF_Su
sOC[2]# VccSus1_5 NC VSS NC NC GPIO[42] G
VSS Vcc1_5 VccSus3_3 Vcc1_5 VccSus1_5 VccSus1_5 NC NC GPIO[41] VSS GPIO[20] GPIO[40] H
VCCPLL3 NC VSS VccSus1_5 Vcc3_3 GPIO[18] SATALED# NC J
VSS Vcc3_3 GPIO[43] GPIO[21] VSS SPKR NC NC K
GPIO[23] VSS GPIO[19] VSS CLK14 VSS NC NC L
VSS VSS VSS VSS VSS Vcc3_3 GPIO[32]
/ WDT
_TOUT# NC VSS Vcc3_3 HI11 NC M
VSS VSS VSS VSS Vcc1_5 VccSus1_5 HI9 VSS VccHI HI10 HI8 N
VSS VSS VSS VSS VccHI HIREF VSWING VccHI VSS HI1 HI0 P
VSS VSS VSS VSS VccHI HI7 VccHI VSS VccHI HI3 HI2 R
VSS VSS VSS VSS Vcc1_5 HICLK VSS HI6 HICOMP HI_STB/
HI_STBS HI_STB#/
HI_STBF T
VSS VSS VSS VSS VccSus1_5 IGNNE# V_CPU_IO VSS V_CPU_IO HI5 HI4 U
VSS VSS VSS VSS VSS IRQ[15] SDA[0] VSS RCIN# VSS CPUSLP# SMI# V
SDD[6] Vcc3_3 SIORDY /
(SDRSTB/
SWDMARD
Y#)
SDIOR# /
(SDWSTB/
PRDMARD
Y#) V_CPU_IO A20M# INIT# STPCLK# W
VSS SDD[8] SDDACK# SDIOW# /
(SDSTOP) VRMPWRG
DVSS INTR NMI Y
VCCA PDA[2] SDD[4] VSS SDD[0] SDCS3# THRMTRIP
#FERR# AA
VSS V5REF PDD[9] PDIOR# (/
PDWSTB /
PRDMARD
Y#) PDDACK# PDIOW#
(/PDSTOP) SDD[10] SDD[13] Vcc3_3 SDD[2] SDCS1# A20GATE AB
VSS Vcc1_5 Vcc1_5 VSS VCCRTC PDD[7] Vcc3_3 PDD[10] IRQ[14] VSS Vcc3_3 SDD[11] VSS SDD[15] SDA[2] AC
SUS_STAT
#VCCPLL1 VSS Vcc1_5 VBIAS RTCX2 PDD[5] PDD[3] VSS Vcc3_3 PDCS3# SDD[3] SDD[14] SDDREQ SDA[1] AD
VccSus1_5 VCCPLL2 Vcc1_5 Vcc1_5 VSS Vcc1_5 RTCX1 Vcc3_3 PDD[12] PDD[14] VSS SDD[9] VSS SDD[12] SDD[1] AE
GPIO[11] /
SMBALERT
#Vcc1_5 VSS SATA[0]TX
PVSS SATA[1]TX
PVcc3_3 PWROK PDD[8] PDDREQ PDD[0] PIORDY (/
PDRST B /
PWDMARD
Y#) PDCS1# SDD[7] SDD[5] AF
VccSus1_5 Vcc1_5 VSS SATA[0]TX
NVSS SATA[1]TX
NVSS RTCRST# INTRUDER
#VSS PDD[1] VSS PDA[1] PDA[0] VSS AG
VSS VSS SATACLKP Vcc1_5 SATA[0]RX
PVSS SATA[1]RX
PVSS SATARBIA
SP PDD[6] PDD[11] PDD[2] PDD[15] VSS AH
NC VSS SATACLKN VSS SATA[0]RX
NVSS SATA[1]RX
NVSS SATARBIA
SN RSMRST# PDD[4] PDD[13] VSS AJ
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 773
21—Intel® 6300ESB ICH
Figure 38. Mechanical Drawing
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 774
Table 706. Signal List (Alphabetical
List)
Signal Location
A20GATE AB29
A20M# W27
AC_BIT_CLK G19
AC_RST# E23
AC_SDIN0 F22
AC_SDIN1 E21
AC_SDIN2 E22
AC_SDOUT E20
AC_SYNC F20
AD[0] H11
AD[1] G8
AD[2] C3
AD[3] F5
AD[4] F10
AD[5] D4
AD[6] D6
AD[7] B3
AD[8] H8
AD[9] D5
AD[10] E2
AD[11] B4
AD[12] G6
AD[13] F6
AD[14] D1
AD[15] C7
AD[16] A4
AD[17] E1
AD[18] B7
AD[19] F2
AD[20] A5
AD[21] K8
AD[22] B6
AD[23] H7
AD[24] E8
AD[25] K7
AD[26] E7
AD[27] F1
AD[28] H12
AD[29] H4
AD[30] G11
AD[31] G2
C/BE[0]# C2
C/BE[1]# G7
C/BE[2]# F4
C/BE[3]# H5
CLK14 L26
CLK48 E29
CPUSLP# V28
DEVSEL# G5
FERR# AA29
FRAME# G10
GNT[0]# E10
GNT[1]# D9
GNT[2]# C11
GNT[3]# G13
GPIO[ 0] /
PXREQ[2]# J1
GPIO[ 1] /
PXREQ[3]# Y8
GPIO[ 2] /
PIRQ[E]# B10
GPIO[ 3] /
PIRQ[F]# A10
GPIO[ 4] /
PIRQ[G]# D10
GPIO[ 5] /
PIRQ[H]# A8
GPIO[6] C21
GPIO[7] B22
GPIO[8] AE12
GPIO[11] /
SMBALERT# AF15
GPIO[12] AF11
GPIO[13] AC14
GPIO[16] /
PXGNT[2]# AC2
GPIO[17] /
PXGNT[3]# Y7
GPIO[18] J27
GPIO[19] L24
GPIO[20] H28
GPIO[21] K25
GPIO[23] L22
GPIO[24] AE14
GPIO[25] AH9
GPIO[27] AG10
GPIO[28] AJ9
GPIO[32] / WDT
_TOUT# M24
GPIO[33] /
PXIRQ[0]# G1
GPIO[34] /
PXIRQ[1]# H1
GPIO[35] /
PXIRQ[2]# H2
GPIO[36] /
PXIRQ[3]# J3
GPIO[37] D20
GPIO[38] F29
GPIO[39] E19
GPIO[40] H29
GPIO[41] H26
GPIO[42] G29
Table 706. Signal List (Alphabetical
List)
Signal Location
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 775
GPIO[43] K24
GPIO[56] C22
GPIO[57] D22
HI_STB#/HI_STBF T29
HI_STB/HI_STBS T28
HIREF P24
HIHIHIHI0 P29
HI1 P28
HI2 R29
HI3 R28
HI4 U29
HI5 U28
HI6 T26
HI7 R24
HI8 N29
HI9 N25
HI10 N28
HI11 M28
HICLK T24
HICOMP T27
IGNNE# U24
INIT# W28
INTR Y28
INTRUDER# AG23
IRDY# E3
IRQ[14] AC23
IRQ[15] V23
LAD[0] C15
LAD[1] B15
LAD[2] A15
LAD[3] A14
LDRQ[0]# F14
LDRQ[1]# G14
LFRAME# B14
NC B20
NC B21
NC B13
NC B12
NC A11
NC A12
NC A13
NC A21
NC A22
NC AD13
NC AJ14
NC AJ15
NC D19
NC E13
NC F13
NC F27
NC F28
Table 706. Signal List (Alphabetical
List)
Signal Location NC G18
NC G25
NC G27
NC G28
NC H24
NC H25
NC J23
NC J29
NC K28
NC K29
NC L28
NC L29
NC M25
NC M29
NMI Y29
OC[0]# F24
OC[1]# F23
OC[2]# G23
OC[3]# E24
PAR G9
PCICLK J5
PCIXSBRST# AA7
PDA[0] AG28
PDA[1] AG27
PDA[2] AA23
PDCS1# AF27
PDCS3# AD25
PDD[0] AF25
PDD[1] AG25
PDD[2] AH26
PDD[3] AD22
PDD[4] AJ25
PDD[5] AD21
PDD[6] AH24
PDD[7] AC20
PDD[8] AF23
PDD[9] AB20
PDD[10] AC22
PDD[11] AH25
PDD[12] AE23
PDD[13] AJ26
PDD[14] AE24
PDD[15] AH27
PDDACK# AB22
PDDREQ AF24
PDIOR# (/
PDWSTB /
PRDMARDY#) AB21
PDIOW# (/
PDSTOP) AB23
PERR# D2
Table 706. Signal List (Alphabetical
List)
Signal Location
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 776
PIORDY (/PDRSTB
/PWDMARDY#) AF26
PIRQ[A]# E12
PIRQ[B]# A6
PIRQ[C]# A9
PIRQ[D]# B8
PLOCK# J6
PME# AJ8
PWRBTN# AJ10
PWROK AF22
PXACK64# AF4
PXAD[0] AF2
PXAD[1] W7
PXAD[2] V7
PXAD[3] Y4
PXAD[4] AA2
PXAD[5] W8
PXAD[6] Y2
PXAD[7] AA6
PXAD[8] W1
PXAD[9] W2
PXAD[10] AA4
PXAD[11] V2
PXAD[12] V1
PXAD[13] V4
PXAD[14] Y1
PXAD[15] T7
PXAD[16] R1
PXAD[17] P1
PXAD[18] P2
PXAD[19] P5
PXAD[20] N2
PXAD[21] P7
PXAD[22] N1
PXAD[23] N3
PXAD[24] N4
PXAD[25] M1
PXAD[26] M2
PXAD[27] L1
PXAD[28] L3
PXAD[29] M7
PXAD[30] M5
PXAD[31] K2
PXAD[32] AF1
PXAD[33] AE4
PXAD[34] AE3
PXAD[35] AE2
PXAD[36] AD7
PXAD[37] AD6
PXAD[38] AD4
PXAD[39] AC6
Table 706. Signal List (Alphabetical
List)
Signal Location PXAD[40] AD2
PXAD[41] AD1
PXAD[42] AB3
PXAD[43] Y6
PXAD[44] AB7
PXAD[45] AB2
PXAD[46] AC1
PXAD[47] AB1
PXAD[48] AD10
PXAD[49] AE10
PXAD[50] AC10
PXAD[51] AE9
PXAD[52] AJ7
PXAD[53] AF9
PXAD[54] AB9
PXAD[55] AH7
PXAD[56] AJ6
PXAD[57] AH6
PXAD[58] AJ5
PXAD[59] AH5
PXAD[60] AG5
PXAD[61] AJ4
PXAD[62] AH4
PXAD[63] AH3
PXC/BE[0]# AA1
PXC/BE[1]# U2
PXC/BE[2]# R2
PXC/BE[3]# N6
PXC/BE[4]# AE7
PXC/BE[5]# AG2
PXC/BE[6]# AF7
PXC/BE[7]# AF6
PXDEVSEL# T3
PXFRAME# R6
PXGNT0# K1
PXGNT1# AB5
PXIRDY# R4
PXM66EN W4
PXPAR U4
PXPAR64 AD8
PXPCICLK AC5
PXPCIRST# AH8
PXPCIXCAP R7
PXPCLKI AC4
PXPCLKO[0] J2
PXPCLKO[1] L8
PXPCLKO[2] K6
PXPCLKO[3] K4
PXPCLKO[4] L5
PXPERR# U6
PXPLOCK# T1
Table 706. Signal List (Alphabetical
List)
Signal Location
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 777
PXRCOMP AC12
PXREQ[0]# L2
PXREQ[1]# L6
PXREQ64# AE5
PXSERR# U1
PXSTOP# T2
PXTRDY# T5
RASERR# AE1
RCIN# V26
REQ[0]# D8
REQ[1]# G12
REQ[2]# B11
REQ[3]# D12
RI# AH10
RSMRST# AJ24
RTCRST# AG22
RTCX1 AE21
RTCX2 AD20
SATA[0]RXN AJ19
SATA[0]RXP AH19
SATA[0]TXN AG18
SATA[0]TXP AF18
SATA[1]RXN AJ21
SATA[1]RXP AH21
SATA[1]TXN AG20
SATA[1]TXP AF20
SATACLKN AJ17
SATACLKP AH17
SATALED# J28
SATARBIASN AJ23
SATARBIASP AH23
SDA[0] V24
SDA[1] AD29
SDA[2] AC29
SDCS1# AB28
SDCS3# AA27
SDD[0] AA26
SDD[1] AE29
SDD[2] AB27
SDD[3] AD26
SDD[4] AA24
SDD[5] AF29
SDD[6] W22
SDD[7] AF28
SDD[8] Y23
SDD[9] AE26
SDD[10] AB24
SDD[11] AC26
SDD[12] AE28
SDD[13] AB25
SDD[14] AD27
Table 706. Signal List (Alphabetical
List)
Signal Location SDD[15] AC28
SDDACK# Y24
SDDREQ AD28
SDIOR# /
(SDWSTB/
PRDMA RDY#) W25
SDIOW# /
(SDSTOP) Y25
SERIRQ G17
SERR# E4
SIORDY /
(SDRSTB/
SWDMARDY#) W24
SIU0_CTS# D16
SIU0_DCD# B16
SIU0_DSR# E17
SIU0_DTR# E15
SIU0_RI# A16
SIU0_RTS# F16
SIU0_RXD B17
SIU0_TXD A17
SIU1_CTS# A20
SIU1_DCD# A19
SIU1_DSR# B19
SIU1_DTR# B18
SIU1_RI# D17
SIU1_RTS# G16
SIU1_RXD D18
SIU1_TXD C19
SLP_S3# AG14
SLP_S4# AD14
SLP_S5# AJ11
SMBCLK AH14
SMBDATA AJ13
SMI# V29
SMLINK[0] AH13
SMLINK[1] AH12
SPKR K27
STOP# B5
STPCLK# W29
SUS_STAT# AD15
SUSCLK AJ12
SYSRESET# AH11
THRM# D14
THRMTRIP# AA28
TRDY# F9
UART_CLK A18
USBP0N D27
USBP0P C27
USBP1N C25
USBP1P D25
USBP2N B26
Table 706. Signal List (Alphabetical
List)
Signal Location
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 778
USBP2P A26
USBP3N B24
USBP3P A24
USBRBIASN D29
USBRBIASP E28
V_CPU_IO U25
V_CPU_IO U27
V_CPU_IO W26
V5REF AB19
V5REF E11
V5REF_Sus G22
VBIAS AD19
Vcc1_5 AB10
Vcc1_5 AB8
Vcc1_5 AC13
Vcc1_5 AC16
Vcc1_5 AC17
Vcc1_5 AD18
Vcc1_5 AE17
Vcc1_5 AE18
Vcc1_5 AE20
Vcc1_5 AF16
Vcc1_5 AG16
Vcc1_5 AH18
Vcc1_5 F12
Vcc1_5 G20
Vcc1_5 H19
Vcc1_5 H21
Vcc1_5 J8
Vcc1_5 N23
Vcc1_5 N7
Vcc1_5 T23
Vcc1_5 V8
Vcc3_3 AA3
Vcc3_3 AA5
Vcc3_3 AB11
Vcc3_3 AB26
Vcc3_3 AB6
Vcc3_3 AC21
Vcc3_3 AC25
Vcc3_3 AC9
Vcc3_3 AD24
Vcc3_3 AD3
Vcc3_3 AE11
Vcc3_3 AE22
Vcc3_3 AE8
Vcc3_3 AF21
Vcc3_3 AF5
Vcc3_3 AG3
Vcc3_3 AG7
Vcc3_3 C13
Table 706. Signal List (Alphabetical
List)
Signal Location Vcc3_3 C17
Vcc3_3 C5
Vcc3_3 C9
Vcc3_3 D15
Vcc3_3 D3
Vcc3_3 E6
Vcc3_3 E9
Vcc3_3 G15
Vcc3_3 G3
Vcc3_3 H3
Vcc3_3 H9
Vcc3_3 J26
Vcc3_3 J7
Vcc3_3 K23
Vcc3_3 K3
Vcc3_3 K5
Vcc3_3 M23
Vcc3_3 M27
Vcc3_3 M4
Vcc3_3 M8
Vcc3_3 N5
Vcc3_3 P4
Vcc3_3 R3
Vcc3_3 R5
Vcc3_3 U5
Vcc3_3 U7
Vcc3_3 W23
Vcc3_3 W3
Vcc3_3 W5
Vcc3_3 W6
VCCA AA22
VccHI N27
VccHI P23
VccHI P26
VccHI R23
VccHI R25
VccHI R27
VCCPLL0 AA8
VCCPLL1 AD16
VCCPLL2 AE16
VCCPLL3 J22
VCCREF AC8
VCCREF V6
VCCRTC AC19
VccSus1_5 AE15
VccSus1_5 AG15
VccSus1_5 D21
VccSus1_5 F21
VccSus1_5 G24
VccSus1_5 H22
VccSus1_5 H23
Table 706. Signal List (Alphabetical
List)
Signal Location
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 779
VccSus1_5 J25
VccSus1_5 N24
VccSus1_5 U23
VccSus3_3 B23
VccSus3_3 A23
VccSus3_3 AF13
VccSus3_3 AG12
VccSus3_3 C23
VccSus3_3 D23
VccSus3_3 D24
VccSus3_3 G21
VccSus3_3 H20
VRMPWRGD Y26
VSS B2
VSS B25
VSS B27
VSS B28
VSS B9
VSS A25
VSS A27
VSS A3
VSS A7
VSS AA25
VSS AB12
VSS AB18
VSS AB4
VSS AC11
VSS AC15
VSS AC18
VSS AC24
VSS AC27
VSS AC3
VSS AC7
VSS AD11
VSS AD12
VSS AD17
VSS AD23
VSS AD5
VSS AD9
VSS AE13
VSS AE19
VSS AE25
VSS AE27
VSS AE6
VSS AF10
VSS AF12
VSS AF14
VSS AF17
VSS AF19
VSS AF3
VSS AF8
Table 706. Signal List (Alphabetical
List)
Signal Location VSS AG1
VSS AG11
VSS AG13
VSS AG17
VSS AG19
VSS AG21
VSS AG24
VSS AG26
VSS AG29
VSS AG4
VSS AG6
VSS AG8
VSS AG9
VSS AH15
VSS AH16
VSS AH2
VSS AH20
VSS AH22
VSS AH28
VSS AJ16
VSS AJ18
VSS AJ20
VSS AJ22
VSS AJ27
VSS AJ3
VSS C1
VSS C10
VSS C12
VSS C14
VSS C16
VSS C18
VSS C20
VSS C24
VSS C26
VSS C28
VSS C29
VSS C4
VSS C6
VSS C8
VSS D11
VSS D13
VSS D26
VSS D28
VSS D7
VSS E14
VSS E16
VSS E18
VSS E25
VSS E26
VSS E27
VSS E5
Table 706. Signal List (Alphabetical
List)
Signal Location
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 780
VSS F11
VSS F15
VSS F17
VSS F18
VSS F19
VSS F25
VSS F26
VSS F3
VSS F7
VSS F8
VSS G26
VSS G4
VSS H10
VSS H18
VSS H27
VSS H6
VSS J24
VSS J4
VSS K22
VSS K26
VSS L23
VSS L25
VSS L27
VSS L4
VSS L7
VSS M12
VSS M13
VSS M14
VSS M15
VSS M16
VSS M17
VSS M18
VSS M22
VSS M26
VSS M3
VSS M6
VSS N12
VSS N13
VSS N14
VSS N15
VSS N16
VSS N17
VSS N18
VSS N26
VSS P12
VSS P13
VSS P14
VSS P15
VSS P16
VSS P17
VSS P18
Table 706. Signal List (Alphabetical
List)
Signal Location VSS P27
VSS P3
VSS P6
VSS R12
VSS R13
VSS R14
VSS R15
VSS R16
VSS R17
VSS R18
VSS R26
VSS T12
VSS T13
VSS T14
VSS T15
VSS T16
VSS T17
VSS T18
VSS T25
VSS T4
VSS T6
VSS U12
VSS U13
VSS U14
VSS U15
VSS U16
VSS U17
VSS U18
VSS U26
VSS U3
VSS V12
VSS V13
VSS V14
VSS V15
VSS V16
VSS V17
VSS V18
VSS V22
VSS V25
VSS V27
VSS V3
VSS V5
VSS Y22
VSS Y27
VSS Y3
VSS Y5
VSWING P25
Table 706. Signal List (Alphabetical
List)
Signal Location
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 781
Tab l e 70 7. S ign al List (by Lo cat io n )
Location Signal
A3 VSS
A4 AD[16]
A5 AD[20]
A6 PIRQ[B]#
A7 VSS
A8 GPIO[5] /
PIRQ[H]#
A9 PIRQ[C]#
A10 GPIO[3] /
PIRQ[F]#
A11 NC
A12 NC
A13 NC
A14 LAD[3]
A15 LAD[2]
A16 SIU0_RI#
A17 SIU0_TXD
A18 UART_CLK
A19 SIU1_DCD#
A20 SIU1_CTS#
A21 NC
A22 NC
A23 VccSus3_3
A24 USBP3P
A25 VSS
A26 USBP2P
A27 VSS
AA1 PXC/BE[0]#
AA2 PXAD[4]
AA3 Vcc3_3
AA4 PXAD[10]
AA5 Vcc3_3
AA6 PXAD[7]
AA7 PCIXSBRST#
AA8 VCCPLL0
AA22 VCCA
AA23 PDA[2]
AA24 SDD[4]
AA25 VSS
AA26 SDD[0]
AA27 SDCS3#
AA28 THRMTRIP#
AA29 FERR#
AB1 PXAD[47]
AB2 PXAD[45]
AB3 PXAD[42]
AB4 VSS
AB5 PXGNT1#
AB6 Vcc3_3
AB7 PXAD[44]
AB8 Vcc1_5
AB9 PXAD[54]
AB10 Vcc1_5
AB11 Vcc3_3
AB12 VSS
AB18 VSS
AB19 V5REF
AB20 PDD[9]
AB21 PDIOR# (/
PDWSTB /
PRDMARDY#)
AB22 PDDACK#
AB23 PDIOW# (/
PDSTOP)
AB24 SDD[10]
AB25 SDD[13]
AB26 Vcc3_3
AB27 SDD[2]
AB28 SDCS1#
AB29 A20GATE
AC1 PXAD[46]
AC2 GPIO [16] /
PXGNT[2]#
AC3 VSS
AC4 PXPCLKI
AC5 PXPCICLK
AC6 PXAD[39]
AC7 VSS
AC8 VCCREF
AC9 Vcc3_3
AC10 PXAD[50]
AC11 VSS
AC12 PXRCOMP
AC13 Vcc1_5
AC14 GPIO[13]
AC15 VSS
AC16 Vcc1_5
AC17 Vcc1_5
AC18 VSS
AC19 VCCRTC
AC20 PDD[7]
AC21 Vcc3_3
AC22 PDD[10]
AC23 IRQ[14]
AC24 VSS
AC25 Vcc3_3
AC26 SDD[11]
AC27 VSS
AC28 SDD[15]
AC29 SDA[2]
AD1 PXAD[41]
AD2 PXAD[40]
AD3 Vcc3_3
AD4 PXAD[38]
AD5 VSS
Table 707. Signal List (by Location)
Location Signal
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 782
AD6 PXAD[37]
AD7 PXAD[36]
AD8 PXPAR64
AD9 VSS
AD10 PXAD[48]
AD11 VSS
AD12 VSS
AD13 NC
AD14 SLP_S4#
AD15 SUS_STAT#
AD16 VCCPLL1
AD17 VSS
AD18 Vcc1_5
AD19 VBIAS
AD20 RTCX2
AD21 PDD[5]
AD22 PDD[3]
AD23 VSS
AD24 Vcc3_3
AD25 PDCS3#
AD26 SDD[3]
AD27 SDD[14]
AD28 SDDREQ
AD29 SDA[1]
AE1 RASERR#
AE2 PXAD[35]
AE3 PXAD[34]
AE4 PXAD[33]
AE5 PXREQ64#
AE6 VSS
AE7 PXC/BE[4]#
AE8 Vcc3_3
AE9 PXAD[51]
AE10 PXAD[49]
AE11 Vcc3_3
AE12 GPIO[8]
AE13 VSS
AE14 GPIO[24]
AE15 VccSus1_5
AE16 VCCPLL2
AE17 Vcc1_5
AE18 Vcc1_5
AE19 VSS
AE20 Vcc1_5
AE21 RTCX1
AE22 Vcc3_3
AE23 PDD[12]
AE24 PDD[14]
AE25 VSS
AE26 SDD[9]
AE27 VSS
AE28 SDD[12]
Table 707. Signal List (by Location)
Location Signal
AE29 SDD[1]
AF1 PXAD[32]
AF2 PXAD[0]
AF3 VSS
AF4 PXACK64#
AF5 Vcc3_3
AF6 PXC/BE[7]#
AF7 PXC/BE[6]#
AF8 VSS
AF9 PXAD[53]
AF10 VSS
AF11 GPIO[12]
AF12 VSS
AF13 VccSus3_3
AF14 VSS
AF15 GPIO[11] /
SMBALERT#
AF16 Vcc1_5
AF17 VSS
AF18 SATA[0]TXP
AF19 VSS
AF20 SATA[1]TXP
AF21 Vcc3_3
AF22 PWROK
AF23 PDD[8]
AF24 PDDREQ
AF25 PDD[0]
AF26 PIORDY (/
PDRSTB /
PWDMARDY#)
AF27 PDCS1#
AF28 SDD[7]
AF29 SDD[5]
AG1 VSS
AG2 PXC/BE[5]#
AG3 Vcc3_3
AG4 VSS
AG5 PXAD[60]
AG6 VSS
AG7 Vcc3_3
AG8 VSS
AG9 VSS
AG10 GPIO[27]
AG11 VSS
AG12 VccSus3_3
AG13 VSS
AG14 SLP_S3#
AG15 VccSus1_5
AG16 Vcc1_5
AG17 VSS
AG18 SATA[0]TXN
AG19 VSS
Table 707. Signal List (by Location)
Location Signal
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 783
AG20 SATA[1]TXN
AG21 VSS
AG22 RTCRST#
AG23 INTRUDER#
AG24 VSS
AG25 PDD[1]
AG26 VSS
AG27 PDA[1]
AG28 PDA[0]
AG29 VSS
AH2 VSS
AH3 PXAD[63]
AH4 PXAD[62]
AH5 PXAD[59]
AH6 PXAD[57]
AH7 PXAD[55]
AH8 PXPCIRST#
AH9 GPIO[25]
AH10 RI#
AH11 SYSRESET#
AH12 SMLINK[1]
AH13 SMLINK[0]
AH14 SMBCLK
AH15 VSS
AH16 VSS
AH17 SATACLKP
AH18 Vcc1_5
AH19 SATA[0]RXP
AH20 VSS
AH21 SATA[1]RXP
AH22 VSS
AH23 SATARBIASP
AH24 PDD[6]
AH25 PDD[11]
AH26 PDD[2]
AH27 PDD[15]
AH28 VSS
AJ3 VSS
AJ4 PXAD[61]
AJ5 PXAD[58]
AJ6 PXAD[56]
AJ7 PXAD[52]
AJ8 PME#
AJ9 GPIO[28]
AJ10 PWRBTN#
AJ11 SLP_S5#
AJ12 SUSCLK
AJ13 SMBDATA
AJ14 NC
AJ15 NC
AJ16 VSS
AJ17 SATACLKN
Tab l e 70 7. S ign al List (by Lo cat io n )
Location Signal
AJ18 VSS
AJ19 SATA[0]RXN
AJ20 VSS
AJ21 SATA[1]RXN
AJ22 VSS
AJ23 SATARBIASN
AJ24 RSMRST#
AJ25 PDD[4]
AJ26 PDD[13]
AJ27 VSS
B2 VSS
B3 AD[7]
B4 AD[11]
B5 STOP#
B6 AD[22]
B7 AD[18]
B8 PIRQ[D]#
B9 VSS
B10 GPIO [2] /
PIRQ[E]#
B11 REQ[2]#
B12 NC
B13 NC
B14 L FRAME#
B15 LAD[1]
B16 SIU0_DCD#
B17 SIU0_RXD
B18 SIU1_DTR#
B19 SIU1_DSR#
B20 NC
B21 NC
B22 GPIO[7]
B23 VccSus3_3
B24 USBP3N
B25 VSS
B26 USBP2N
B27 VSS
B28 VSS
C1 VSS
C2 C/BE[0]#
C3 AD[2]
C4 VSS
C5 Vcc3_3
C6 VSS
C7 AD[15]
C8 VSS
C9 Vcc3_3
C10 VSS
C11 GNT[2]#
C12 VSS
C13 Vcc3_3
C14 VSS
Table 707. Signal List (by Location)
Location Signal
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 784
C15 LAD[0]
C16 VSS
C17 Vcc3_3
C18 VSS
C19 SIU1_TXD
C20 VSS
C21 GPIO[6]
C22 GPIO[56]
C23 VccSus3_3
C24 VSS
C25 USBP1N
C26 VSS
C27 USBP0P
C28 VSS
C29 VSS
D1 AD[14]
D2 PERR#
D3 Vcc3_3
D4 AD[5]
D5 AD[9]
D6 AD[6]
D7 VSS
D8 REQ[0]#
D9 GNT[1]#
D10 GPIO[4] /
PIRQ[G]#
D11 VSS
D12 REQ[3]#
D13 VSS
D14 THRM#
D15 Vcc3_3
D16 SIU0_CTS#
D17 SIU1 _RI#
D18 SIU1_RXD
D19 NC
D20 GPIO[37]
D21 VccSus1_5
D22 GPIO[57]
D23 VccSus3_3
D24 VccSus3_3
D25 USBP1P
D26 VSS
D27 USBP0N
D28 VSS
D29 USBRBIASN
E1 AD[17]
E2 AD[10]
E3 IRDY#
E4 SERR#
E5 VSS
E6 Vcc3_3
E7 AD[26]
Table 707. Signal List (by Location)
Location Signal
E8 AD[24]
E9 Vcc3_3
E10 GNT[0]#
E11 V5REF
E12 PIRQ[A]#
E13 NC
E14 VSS
E15 SIU0_DTR#
E16 VSS
E17 SIU0_DSR#
E18 VSS
E19 GPIO[39]
E20 AC_SDOUT
E21 AC_SDIN1
E22 AC_SDIN2
E23 AC_RST#
E24 OC[3]#
E25 VSS
E26 VSS
E27 VSS
E28 USBRBIASP
E29 CLK48
F1 AD[27]
F2 AD[19]
F3 VSS
F4 C/BE[2]#
F5 AD[3]
F6 AD[13]
F7 VSS
F8 VSS
F9 TRDY#
F10 AD[4]
F11 VSS
F12 Vcc1_5
F13 NC
F14 LDRQ[0]#
F15 VSS
F16 SIU0_RTS#
F17 VSS
F18 VSS
F19 VSS
F20 AC_SYNC
F21 VccSus1_5
F22 AC_SDIN0
F23 OC[1]#
F24 OC[0]#
F25 VSS
F26 VSS
F27 NC
F28 NC
F29 GPIO[38]
Table 707. Signal List (by Location)
Location Signal
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 785
G1 GPIO[33] /
PXIRQ[0]#
G2 AD[31]
G3 Vcc3_3
G4 VSS
G5 DEVSEL#
G6 AD[12]
G7 C/BE[1]#
G8 AD[1]
G9 PAR
G10 FRAME#
G11 AD[30]
G12 REQ[1]#
G13 GNT[3]#
G14 LDRQ[1]#
G15 Vcc3_3
G16 SIU1_RTS#
G17 SERIRQ
G18 NC
G19 AC_BIT_CLK
G20 Vcc1_5
G21 VccSus3_3
G22 V5REF_Sus
G23 OC[2]#
G24 VccSus1_5
G25 NC
G26 VSS
G27 NC
G28 NC
G29 GPIO[42]
H1 GPIO[34] /
PXIRQ[1]#
H2 GPIO[35] /
PXIRQ[2]#
H3 Vcc3_3
H4 AD[29]
H5 C/BE[3]#
H6 VSS
H7 AD[23]
H8 AD[8]
H9 Vcc3_3
H10 VSS
H11 AD[0]
H12 AD[28]
H18 VSS
H19 Vcc1_5
H20 VccSus3_3
H21 Vcc1_5
H22 VccSus1_5
H23 VccSus1_5
H24 NC
H25 NC
Tab l e 70 7. S ign al List (by Lo cat io n )
Location Signal
H26 GPIO[41]
H27 VSS
H28 G PIO[20]
H29 G PIO[40]
J1 GPIO [0] /
PXREQ[2]#
J2 PXPCLKO[0]
J3 GPIO [36] /
PXIRQ[3]#
J4 VSS
J5 PCICLK
J6 PLOCK#
J7 Vcc3_3
J8 Vcc1_5
J22 VCCPLL3
J23 NC
J24 VSS
J25 VccSus1_5
J26 Vcc3_3
J27 GPIO[18]
J28 SATALED#
J29 NC
K1 PXGNT0#
K2 PXAD[31]
K3 Vcc3_3
K4 PXPCLKO[3]
K5 Vcc3_3
K6 PXPCLKO[2]
K7 AD[25]
K8 AD[21]
K22 VSS
K23 Vcc3_3
K24 GPIO[43]
K25 GPIO[21]
K26 VSS
K27 SPKR
K28 NC
K29 NC
L1 PXAD[27]
L2 PXREQ[0]#
L3 PXAD[28]
L4 VSS
L5 PXPCLKO[4]
L6 PXREQ[1]#
L7 VSS
L8 PXPCLKO[1]
L22 GPIO[23]
L23 VSS
L24 GPIO[19]
L25 VSS
L26 CLK14
L27 VSS
Table 707. Signal List (by Location)
Location Signal
Pac kage Information
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 786
L28 NC
L29 NC
M1 PXAD[25]
M2 PXAD[26]
M3 VSS
M4 Vcc3_3
M5 PXAD[30]
M6 VSS
M7 PXAD[29]
M8 Vcc3_3
M12 VSS
M13 VSS
M14 VSS
M15 VSS
M16 VSS
M17 VSS
M18 VSS
M22 VSS
M23 Vcc3_3
M24 GPIO[32] / WD T
_TOUT#
M25 NC
M26 VSS
M27 Vcc3_3
M28 HI11
M29 NC
N1 PXAD[22]
N2 PXAD[20]
N3 PXAD[23]
N4 PXAD[24]
N5 Vcc3_3
N6 PXC/BE[3]#
N7 Vcc1_5
N12 VSS
N13 VSS
N14 VSS
N15 VSS
N16 VSS
N17 VSS
N18 VSS
N23 Vcc1_5
N24 VccSus1_5
N25 HI9
N26 VSS
N27 VccHI
N28 HI10
N29 HI8
P1 PXAD[17]
P2 PXAD[18]
P3 VSS
P4 Vcc3_3
P5 PXAD[19]
Table 707. Signal List (by Location)
Location Signal
P6 VSS
P7 PXAD[21]
P12 VSS
P13 VSS
P14 VSS
P15 VSS
P16 VSS
P17 VSS
P18 VSS
P23 VccHI
P24 HIREF
P25 VSWING
P26 VccHI
P27 VSS
P28 HI1
P29 HI0
R1 PXAD[16]
R2 PXC/BE[2]#
R3 Vcc3_3
R4 PXIRDY#
R5 Vcc3_3
R6 PXFRAME#
R7 PXPCIXCAP
R12 VSS
R13 VSS
R14 VSS
R15 VSS
R16 VSS
R17 VSS
R18 VSS
R23 VccHI
R24 HI7
R25 VccHI
R26 VSS
R27 VccHI
R28 HI3
R29 HI2
T1 PXPLOCK#
T2 PXSTOP#
T3 PXDEVSEL#
T4 VSS
T5 PXTRDY#
T6 VSS
T7 PXAD[15]
T12 VSS
T13 VSS
T14 VSS
T15 VSS
T16 VSS
T17 VSS
T18 VSS
T23 Vcc1_5
Table 707. Signal List (by Location)
Location Signal
P ackage Inf ormation
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 787
T24 HICLK
T25 VSS
T26 HI6
T27 HICOMP
T28 HI_STB/
HI_STBS
T29 HI_STB#/
HI_STBF
U1 PXSERR#
U2 PXC/BE[1]#
U3 VSS
U4 PXPAR
U5 Vcc3_3
U6 PXPERR#
U7 Vcc3_3
U12 VSS
U13 VSS
U14 VSS
U15 VSS
U16 VSS
U17 VSS
U18 VSS
U23 VccSus1_5
U24 IGNNE#
U25 V_CPU_IO
U26 VSS
U27 V_CPU_IO
U28 HI5
U29 HI4
V1 PXAD[12]
V2 PXAD[11]
V3 VSS
V4 PXAD[13]
V5 VSS
V6 VCCREF
V7 PXAD[2]
V8 Vcc1_5
V12 VSS
V13 VSS
V14 VSS
V15 VSS
V16 VSS
V17 VSS
V18 VSS
V22 VSS
V23 IRQ[15]
V24 SDA[0]
V25 VSS
V26 RCIN#
V27 VSS
V28 CPUSLP#
V29 SMI#
Tab l e 70 7. S ign al List (by Lo cat io n )
Location Signal
W1 PXAD[8]
W2 PXAD[9]
W3 Vcc3_3
W4 PXM66EN
W5 Vcc3_3
W6 Vcc3_3
W7 PXAD[1]
W8 PXAD[5]
W22 SDD[6]
W23 Vcc3_3
W24 SIORD Y /
(SDRSTB/
SWDMARDY#)
W25 SDIO R # /
(SDWSTB/
PRDMARDY#)
W26 V_CPU_IO
W27 A20M#
W28 INIT#
W29 STPCLK#
Y1 PXAD[14]
Y2 PXAD[6]
Y3 VSS
Y4 PXAD[3]
Y5 VSS
Y6 PXAD[43]
Y7 GPIO [17] /
PXGNT[3]#
Y8 GPIO [1] /
PXREQ[3]#
Y22 VSS
Y23 SDD[8]
Y24 SDDACK#
Y25 SDIOW# /
(SDSTOP)
Y26 VRMPWRGD
Y27 VSS
Y28 INTR
Y29 NMI
Table 707. Signal List (by Location)
Location Signal
21—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 788
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 789
22—Intel® 6300ESB ICH
Electrical Characteristics 22
This chapter provides the absolute maximum ratings, DC characteristics, AC
characteristics and AC timing diagrams for the Intel® 6300ESB ICH component.
22.1 Absolute Maximum Ratings
Voltage on any 3.3 V pin with re spect to Ground = –0.5 to Vcc3_3 +0.5 V
Voltage on any 5 V toleran t pin with respect to Ground (V5REF = 5 V) = –0.5 to V5REF
+ 0.5 V
1.5 V suppl y voltage with respect to Vss = –0.5 to +2.1 V
3.3 V suppl y voltage with respect to Vss = –0.5 to +4.6 V
5.0 V supply voltage (V5REF) with respect to Vss = –0.5 to +5.5 V
Warning:Stressing the device beyond the “Absolute Maximum Ratings” may cause
permanent damage. Th ese are stress ratings o nly. See Section 22.2,
“Functional Operating Range” for th e Functional Ope r ating R ange of the I ntel®
6300ES B ICH.
22.2 Functional Operating Range
All of the AC and DC Characteristics specified in this document assume that the Intel®
6300ESB ICH component is operating within the Functional Operating Range given in
this sectio n. Operation outside of the Functional Oper ating Range is not recommended,
and extended exposure outside of the Functional Operating Range may affect
component reliability.
1.5 V supply voltage (Vcc1_5, VccHI, VccSus1_5) with respect to Vss = 1.425 V to
1.575 V
3.3 V suppl y voltage (Vcc3_3, VccSus3_3) with respect to Vss = 3.135 V to 3.465
V
5 V supply voltage (V5REF, V5REF_Sus) with respect to Vss = 4.75 V to 5.25 V
V_CPU_IO voltage with respect to Vss = 0.8 V—1.75 V
VCCRTC voltage with respect to Vss = 2.0 V to 3.6 V
Case temperature under B ias = 0o C to +105o C
Note: A non-condensing environment is required to maintain RTC accuracy.
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
790 Order Number: 300641-004US
22.3 DC Ch aracteristics
Table 708. DC Current Characteristics (Preliminary)
Pow er Plane Max imu m Po w e r Cons u mption
Symbol SO S1 S3/S4/S5 G3
Vc c1_5 Core 1184 mA 573 mA N/A N/A
Vc c3_3 I/O 875 mA 1.3 mA N /A N/A
Vc cSus1_5 7 5 mA 45 m A 15.6 mA N/A
Vc cSus3_3 142 mA 2.1 mA 2.3 mA N/A
Vcc HI 99 mA 99 m A N/A N/A
V5REF 10 µA 10 µA N/A N/A
V5REF_SUS 10 µA 10 µA 10 µA N/A
VCCREF (3.3 V) 150 µA 150 µA N/A N/A
V_CPU _IO 2.5 mA 2.5 m A N/A N/A
VCCRTC N/A N/A N/A 8.5µA(1)
1. Icc(RTC) data is take n with Vcc(RTC) at 3.0 V while the sys te m is in a me cha nical off
(G3) state at room temperature (25o C).
Table 709. DC Characteristic Input Signal Association (Sheet 1 of 2)
Symb ol Associated Si gnal s
VIH0/VIL0
PCI-X Signals: PXAD[63:0], PXC/BE[7:0]#, PXDEVSEL#, PXFRAME#, PXIRDY#, PXTRDY #,
PXSTOP#, PXPAR, PXPERR#, PX PLOC K#, PX S ERR#, PX REQ[1:0]#,PXR EQ[2]#/GPIO[0],
PXREQ[3]# /G PIO[1], PX RCOMP, PX PAR64, PXREQ64#, PX A CK64#, PXM66EN, PXPCIX CA P,
PXIRQ[3:0]/GPIO[36:33]
Clock Signal s: PXPCLKI, PXPCICL K
VIH1/VIL1
(5V Tole rant) PCI Signals : AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, TRDY #, STO P#, PAR,
PERR#, PLOCK#, SERR#, REQ[3:0] #
VIH2/VIL2
(5V Tole rant) Interrupt Sign als: IRQ[15:14 ], PIRQ[D :A ]#, PIRQ[H:E]#/GPIO[5:2]
Legacy Signals: RCIN#, A20GATE
VIH3/VIL3
Clock Signal s: CLK48, CLK 14
Interru pt Sign als: SERIRQ
Power Management Signals: PME#, PWRBTN#, RI#, SYS_RESET#, THRM#
GPIO Signals: GPIO[4 3:37,31, 28:27, 25:24, 13:12, 8:6]
VIH4/VIL4
Clock Signal s: PCICLK
LPC/FW H Sign al s: LDRQ[1:0]#, LAD[3:0]/FWH[3:0 ], LFRAM E#
SIU Signals: SIU0_CTS#, SIU0_DCD#, SIU0_DSR#, SIU0_RI#, SIU0_RXD, SIU1_CTS#;
SIU1_DCD#, SIU1_DSR#, SIU1_RI#, SIU1_RXD, UART_CLK
VIH5/VIL5
SMB us Signals: SM BCLK, S MBDATA
Syste m M anagem ent Si g n a ls : INTRU D ER#, S M LINK[1:0], SMBALERT#/GPIO[11]
Power Management Signals: RSMR ST#, RTCR ST#, PWR OK
VIL6/VIH6 CPU Si gn als: FERR#, THRMTRIP#
VIL7/VIH7 H ub Interface Signals: HI[11:0], HI_STBS, HI_STBF
VIL8/VIH8 Real Time Clock Sign als: RTCX 1, RT CX 2
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 791
22—Intel® 6300ESB ICH
VIL9/VIH9 SA TA Signal s: SATA[1:0]RX[P,N]
VIL10/VIH10
(5V Tolerant) USB Signals: OC[3:0]#
VIL11/VIH11 AC’97 Signals: AC_BIT CLK, AC_SDIN[2:0]
VIL12/VIH12 Clock Signals: SATACL KP, SATACLKN (CLK100P, CLK100N)
V+/V-/VHYS/
VTHRAVG/VRING
(5V Tolerant)
IDE Signals: PDD[15:0], SDD[15:0], PDDREQ, PIORDY, SDDREQ, SIOR DY
F or Ultra DMA Mode 4 and lower these signals, follow the DC characteristi cs for
VIH2/VIL2.
VDI / VCM / VSE USB Signals: USBP[3:0][P,N ] (Low-speed an d Full -sp eed)
VHSSQ / VHSDSC /
VHSCM USB Signals: USBP[3:0][P,N] (in High-speed Mode )
Table 710. DC Input Characteristics (Sheet 1 of 2)
Symbol Parameter Min Max Unit Notes
VIL0 Input Low Voltage -0.5 0.35Vcc3_3 V
VIH0 Inpu t High Voltag e 0.5Vcc3_3 V cc3_3 + 0.5 V
VIL1 Input Low Voltage -0.5 0.3Vcc3_3 V
VIH1 Input High Voltage 0. 5Vcc 3_ 3 V 5 REF + 0 .5 V
VIL2 Input Low Voltage -0.5 0.8 V
VIH2 Input High Voltage 2.0 V5REF + 0.5 V
VIL3 Input Low Voltage -0.5 0.8 V
VIH3 Inpu t High Voltag e 2.0 Vcc3_3 + 0.5 V
VIL4 Input Low Voltage -0.5 0.3Vcc3_3 V
VIH4 Inpu t High Voltag e 0.5Vcc3_3 V cc3_3 + 0.5 V
VIL5 Input Low Voltage -0.5 0.8 V
VIH5 Inpu t High Voltag e 2.1 VccSus3_3 + 0.5 V
VIL6 Input Low Voltage -0.15 0.58(V_CPU_IO) V
VIH6 Inp ut High V oltage 0.73(V_CPU_IO) V_CPU_IO V
VIL7 Input Low Voltage -0.3 HIREF - 0.1 0 V N ote 7
VIH7 Inpu t High Voltag e HIREF + 0.10 1.2 V Note 7
VIL8 Input Low Voltage -0.5 0.10 V
VIH8 Input High V oltage 0.40 1.0 V
NOTES:
1. Applies to Ultra DMA Modes greate r th an Ultra DMA M od e 4.
2. This is an AC Cha racte ristic that represen ts trans ie nt values fo r these sig nals.
3. VDI = | USBPx[P] - US B Px[ N ].
4. Includes VDI range.
5. Applies to High-speed USB 2.0.
6. SATA Vdiff,rx is measured at the SATA connector on the receive side.
7. When probed at the rece iver pin of the ICH for data/s trobe, the wa veform may sh ow a “knee” due to package
parasitics. Simulation verifies that this “knee” represents no risk, since a clean waveform is present at the
ICH ball in p ut due to in te rnal receiver termination.
Table 709. DC Characteristic Input Signal Association (Sheet 2 of 2)
Sym b o l As s o ciate d Sign al s
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
792 Order Number: 300641-004US
VIL9 D iff er en tia l Inp u t Low Voltage 325 mVp -p Note 6
VIH9 Dif f er en t ial Input High Voltage 60 0 mVp -p Note 6
VIL10 Input Low Voltag e -0.5 0.8 V
VIH10 Input High Voltage 2.0 V5REF_SUS + 0.5 V
VIL11 Input L ow Voltage -0.5 0.35V cc 3_3 V
VIH11 Inp ut H igh Voltage 0.65Vcc3_3 V cc3_3 + 0.3 V
VIL12 Input L ow Voltage -0.15 0 0.150 V
VIH12 Inp ut H igh Voltage 0.660 1.850 V
V+ L ow to hig h input thresh old 1.5 2.0 V Note 1
V- High to low input th re shold 1.0 1.5 V Note 1
VHYS
Difference between input
thresholds:
(V+c urre nt value) - (V-curre nt
value)
320
mV
Note 1
VTHRAVG Average of thresholds:
((V+current value) + (V -current
value))/2 1.3 1.7 VNote 1
VRING AC Voltage at recipient connector -1 6 V Note 1, 2
VDI Differ en tial In p ut Sensitivity 0.2 V Note 3, 5
VCM Differential Common Mode Range 0.8 2.5 V Note 4, 5
VSE Single-Ended Receiver Threshold 0.8 2.0 V Note 5
VHSSQ HS S quelch Detection Threshold 100 150 mV Note 5
VHSDSC HS Discon n ect De t ec t i on
Threshold 525 625 mV Note 5
VHSCM HS Data Signaling Common Mode
Voltage Range -50 500 mV Note 5
VHSSQ HS S quelch detection threshold 100 150 m V Note 5
VHSDSC HS disconne ct detection threshold 525 625 m V Note 5
VHSCM HS data signaling common mode
voltage range -50 500 mV Note 5
Table 710. DC Input Characteri stics (Sheet 2 of 2)
Symbol Parameter Min Max Unit Notes
NOTES:
1. Applies to Ultra DMA Modes grea ter tha n Ultra DM A Mode 4.
2. This is an AC Characteristic that rep resents transient valu es for the se signals.
3. VDI = | USBPx[P] - USBPx[N].
4. Include s VDI range.
5. App lie s to Hig h -spe e d US B 2. 0.
6. SATA Vdiff,rx is measured at the SATA connector on the receive side.
7. When pro bed at the receiver pi n of the ICH for data/st robe, the wav eform may show a “knee” due to pac kage
parasitics. Simulation verifies that this “kne e ” re p rese nts no risk, since a clean wavef orm is pr ese nt a t the
ICH ball inp ut due to interna l re ce iv e r te rmination.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 793
22—Intel® 6300ESB ICH
Table 711. DC Characteristic Output Signal Association
Symbol Associated Signals
VOH1/VOL1
IDE Signals: PDD[15:0], SDD[15:0], PDIOW#/PD S TOP, SDIOW#/SDSTOP, PD IOR#/
PDWSTB/PRDMARDY, SDIOR#/STWSTB/SRDMARDY, PDDAC K#, SDDACK#, PDA[2:0],
SDA[2:0], PDCS[3,1]#, SDCS[3,1 ]#
VOH2/VOL2 CPU Signals: A20M#, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#, S TPC LK# ,
VOH4/VOL4
PC I-X Si gn als : PX A D [63:0], PXC/BE[7:0]#, PX PCIRST#, PXGN T[3] #/G PIO [17],
PXGNT[2]#/GPIO [16], PXGNT[1:0]#, PXPAR, PXDEVSEL#, PXPERR#, PXPLOCK#, PXS TOP#,
PXTRDY# , PXIRDY# , PXFRA M E#, PX S ERR#,PX PCLK[0:4], PXSE RR#, RA S ERR#,PX RCOMP,
PXIRQ[3:0]/GPIO[36:33], PXPAR64, PXREQ64#, PXA CK64#, PCIXSBR ST#
PCI Signals: AD[31:0], C/B E[3:0]#, GNT[ 3:0]#, PAR, DEVS EL#, PE RR#, PLOC K#, S TOP#,
T R DY#, IRDY # , F RAM E # , SERR# (1)
LPC/FWH: LAD[3:0]/FW H [3:0], LFRAME #
AC’97 Signals: AC_RST#, AC_SDOUT, AC_SYNC
SIU Signals: SIU 0_T XD, S I U1_TXD, SIU0_D TR# , SIU 1_DTR#, SIU0_RT S #, S I U1_RT S #
GPIO Signals: GPIO [43:40]
VOL5/VOH5 SMBu s Signals: SMBCLK (1), SMBDATA (1)
System Management Si gnals: SMLINK[1:0](1)
VOL6/VOH6
Power Management Signals : PME#(1), SLP_S3#, SLP_S4#, SLP_S5#, SUS_STAT#,
SUSCLK
GPIO Signals: GPIO[57:56(1), 39:37, 31, 28:27, 25:23 , 21:18];
Interr upt Signals: SERIRQ, PIRQ[D:A]# (1), PIRQ[H:E]#/GPIO[5:2 ] (1)
Other Signals: SPK R , WDT_TOUT# / GPIO [ 3 2 ] , SATALE D#(1)
VOL7/VOH7 USB Signal s: USBP[3:0][P,N ] in Lo w an d Full Spe e d Modes
VOL8/VOH8
Zpd/Zpu Hub Interface Signals: HI[11:0 ], HI_STBS, HI_STBF
VOL9/VOH9 SATA Signals: SATA[1:0]TX[P,N]
VHSOI
VHSOH
VHSOL
VCHIRPJ
VCHIRPK
USB Signals: US B P[3:0][P:N] in High S peed M odes
1. These signals are open drain.
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
794 Order Number: 300641-004US
Table 712. DC Output Characteristics
Symbol Parameter Min Max Unit IOL / IOH Notes
VOL1 Output Low Voltage 0.51 V 6 mA
VOH1 Output H igh Voltage Vcc 3_3 - 0.51 V -6 mA
VOL2 Output Low Voltage -0.15 .25(V_CPU_IO
)V1.5 mA
VOH2 Output H igh Voltage 0.9(V _CPU_IO) V -.5 mA Note 1
VOL4 Output Low Voltage 0.55 V 6 mA
VOH4 Output H igh Voltage 0.9Vc c3_3 V -0.5 mA Note 1
VOL5 Ou tp ut Low Voltage 0.4 V 4 mA
VOH5 Output High Voltage N/A V N/A Note 1
VOL6 Ou tp ut Low Voltage 0.4 V 4 mA
VOH6 Output High Voltage Vcc3_3 - 0.5 V -2 mA Note 1
VOL7 Ou tp ut Low Voltage 0.4 V 5 mA
VOH7 Output High Voltage Vcc3_3 - 0.5 V -2 mA
VOL8 Output Low Voltage 0.05 V 1 mA
VOH8 Output H igh Voltage 0.750 .8 50 V -12 mA
VOL9 Ou tp ut Low Voltage 400 mVp-
pNote 2
VOH9 Output High Voltage 600 mVp-
pNote 2
Zpd P ull Down Impedanc e 48 Ohm
Zpu Pull Up Imp e dance 46 Ohm
VHSOI HS Idle Level -1 0.0 10.0 m V
VHSOH HS Data Signaling
High 360 440 mV
VHSOL HS Data Signaling
Low -10.0 10.0 mV
VCHIRPJ C hirp J Level 700 1100 mV
VCHIRPK C hirp K Level - 900 -500 mV
NOTES:
1. The CPUPWRGD, SERR#, PIRQ[A :H], SATALED#, SMBDATA, SMBCLK, an d SMLIN K[1:0], RASERR# ,
PXSERR# , PME#, GPIO [57:5 6] signals have an open drain driver, and the VOH spec does n o t apply. T hi s
signal must have external pull up resistor.
2. SATA Vdiff,t x is me a su red at the SATA conn e ctor on the transmit side .
Tabl e 713. Other DC Characteristics (Sheet 1 of 2)
Symbol Parameter Min Max Unit Notes
V5REF Intel® 6300ESB ICH Core Wel l
Re feren ce Voltage 4.75 V5REF +
0.5 V
Vcc3_3 I/O B uf f er Voltage 3.135 3.465 V
VCCREF Reference voltage for PCI-X 3.135 3.465 V
NOTES:
1. In cludes CL K14, CLK48, HICLK, PCICLK and PXPCICLK.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 795
22—Intel® 6300ESB ICH
Vcc1_5, VccHI,
VccPLL Inte rnal Logic Voltage 1 .425 1.575 V
HIREF Hu b Interface Reference Voltage 0.343 0 .357 V
HIVSWING Hub Interface Vol tage Swing (Input to
HI_VSWING pin) 0.784 0.816 V
V5REF_Sus Suspend Well Referen ce Voltage 4.75 5.25 V
VccSus3_3 Suspend Well I/O Buffer Voltage 3.135 3.465 V
VccSus1_5 Suspend Well Logic Voltage 1.425 1.575 V
VccRTC Battery Volta g e 2.0 3.6 V
VIT+ Hysteresis Input Rising Threshold 1.9 V Applied to
USBP[3:0][P,N]
VIT- Hysteresis Inp ut Falling Threshold 1.3 V Applied to
USBP[3:0]P,N]
VDI Diff e re n tial In p ut Sensitivity 0.2 V |(USBPx+,USBPx-
)|
VCM Differential Common Mode Range 0.8 2.5 V Includes VDI
VCRS Outp ut Signal Crossover Volt age 1.3 2.0 V
VSE Single Ended Rcvr Threshold 0.8 2.0 V
ILI1 ATA Inp ut Leakage Current -200 200 µA (0 V < VIN < 5 V )
ILI2 PCI_3V Hi-Z State Data Line Leakage -10 10 µA (0 V < VIN <
3.3V)
ILI3 PCI_5V Hi-Z State Data Line Leakage -70 70 µA Max V IN = 2.7 V
Min VIN = 0.5 V
ILI4 Input Leak age Curre nt - Clock signals -100 +100 µA Note 1
ILI5 PCI-X Hi-Z State Data Line Leakage -10 10 µA (0 V < VIN <
3.3V)
CIN Inpu t C a pac i tan c e - H ub i n ter face
Inpu t C a pac i tan c e - A ll Ot her 8
12 pF FC = 1 MHz
COUT Output Cap acitanc e 12 pF FC = 1 MHz
CI/O I/O Cap acitanc e 12 p F FC = 1 MHz
Typical Value
CLXTAL1 6 pF
CLXTAL2 6 pF
Tab l e 71 3. Oth e r DC C ha ra ct e rist i cs ( S he et 2 of 2)
Symbol Parameter Min Max Unit Notes
NOTES:
1. Includes CLK14, CLK48 , HICLK , PCICLK and PXPCICLK.
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
796 Order Number: 300641-004US
22.4 AC Characteristics
Table 714. Clock Timings (Sheet 1 of 3)
Sym Parameter Min Max Unit Notes Figure
PCI-X Clock (PXPCLKO[0:4])
Tcy c CLK Cy cle Time 15 30 ns 7, 9, 10 Figure 39
Thi gh CLK High Ti m e 6 n s Figure 39
Tlow CLK Low Time 6 ns Figure 39
CLK Slew Rate 1.5 4 V/ns 8, 10
Spread Spectrum Requirements
fmod Modula ti on Freq uen cy 30 33 kHz
fspread Frequency Spread -1 0 %
PCI Clock (PCICLK)
Period 30 33.3 ns Figure 44
High Time 11 ns Figure 44
Lo w Ti me 11 ns Figure 44
Rise Time 4 ns Figure 44
Fall Time 4 ns Figure 44
Oscillator Clock (CLK14)
Period 67 70 ns Figure 44
High Time 20 Figure 44
Lo w Ti me 2 0 ns Figure 44
USB Clock (CLK48)
fclk48 Op erating Frequenc y 48 MHz 1
Frequency Tolerance 500 p pm 2
High Time 7 ns Figure 44
Lo w Ti me 7 ns Figure 44
Rise Time 1.2 ns Figure 44
Fall Time 1.2 ns Figure 44
SMBus Clock (SMB CLK)
fsmb Operating Frequency 10 1 6 KHz
t18 High time 4.0 50 us 3Figure59
t1 9 Low time 4.7 us Figure 59
t20 Rise time 1000 ns Figure 59
t21 Fall time 300 ns Figure 59
AC’97 Clock (BITCLK )
fac97 Ope rating Frequenc y 12.288 MHz
t26 Output Jitter 750 ps
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 797
22—Intel® 6300ESB ICH
t27 Hig h time 32.56 48.84 ns Figure 44
t28 L ow time 32.56 48 .84 ns Figure 44
t29 Rise time 2.0 6.0 ns 4Figure44
t30 Fall time 2.0 6.0 ns 4Figure44
Hub Interfac e Clock (HICLK )
fhi Oper ati ng Freq uency 66 MHz
t31 Hig h time 6.0 ns Figure 44
t32 L ow time 6.0 n s Figure 44
t33 Rise time 0.25 1.2 ns Figure 44
t34 Fall time 0.25 1.2 ns Figure 44
t35 HICL K lead s PCICL K 1.0 4.5 ns 5
SAT A Cl ock (SATA CLKP, SATAC LKN)
t36 Period 9.997 10.003 ns
t37 Rise time 175 700 ps
t38 Fall time 175 700 ps
Suspend Clock (SUSCLK)
fsusclk Operating Frequency 32 kHz 6
t39 Hi gh Time 10 us 6
t40a Low T ime 10 us 6
UART Clock (UART_CLK)
t8a Op erating Freque ncy 14.745
648 MHz
t9a Frequency Toleran ce 2500 ppm
t10a Hi gh T ime 7 ns
t11a Low T ime 7 ns
t12a Rise Time 3 ns
t13a Fall Time 3 ns
Tab l e 71 4. Clo ck Timi ng s (Sh eet 2 of 3)
Sym Parameter Min Max Unit Notes Figure
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
798 Order Number: 300641-004US
NOTES:
1. CLK48 is a 48 M H z clock t hat expects a 40 /60% duty cycle.
2. CLK4 8 is a pass-thru clock that is not altered by the Intel® 6300ESB ICH . Thi s frequenc y tol erance
specification is required for USB 2.0 compliance and is affected by external elements such as the clock
generator and the system board.
3. The ma x imu m high time (t18 M ax) provide a simp le e n sured method for devic e s to d et ec t bus idle
conditions.
4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VD D.
5. This specifi cation include s pi n -to-p in sk e w fr om th e clock generat or as we ll a s bo ard skew.
6. SU SC LK d uty cycle ca n range from 30% minimum to 70% m a xim um.
7. For clock frequ encies ab ove 33 MHz, the clock frequen cy may not change bey ond the spr ead-spectrum li mits
exce pt while RST# is asserted.
8. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in
Figure 43.
9. T he min imum cl ock period mu st no t b e violated for a n y sin g le clock cycle, i.e., accountin g f or a ll system
jitter.
10.All PCI-X devices must be capable of operating i n conventional PCI 33 mode and optionally are c apable of
conventional PCI 66 mode.
Table 714. Clock Timings (Sheet 3 of 3)
Sym Parameter Min Max Unit Notes Figure
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 799
22—Intel® 6300ESB ICH
Table 715. PCI-X Interface Timings
Symbol Parameter Min Max Units Notes
Tval PXC LKO[4:0] to Si gna l Val i d D elay-bused s ign al s 0. 7 3. 8 ns 1, 2, 3, 10,
11
Tval(ptp) PXCL KO[4:0] to Signal Valid Del ay-point to po int
signals 0.7 3.8 ns 1, 2, 3, 10,
11
Ton Fl oat to Ac tiv e De lay 0 ns 1, 7, 10, 11
Toff Act ive to Float D e lay 7 ns 1, 7, 11
Tsu Input S e tup Time to PXCLKO[4:0]-Bused sign a ls 1.7 ns 3, 4, 8
Tsu(ptp ) Inp ut S e tup Time to PXCLKO [4:0]-point to point 1.7 ns 3, 4
ThInput Hold Ti me fr om PX CLKO[ 4:0] 0.5 ns 4
Trst Reset Active Ti me after power sta b le 1 ms 5
Trst-clk Reset Active Ti me after PXCLKO[4:0] stable 100 μ s 5
Trst-off Reset Active to output f loat d e la y 40 ns 5, 6
Trrsu PX REQ64# to PXPCIRST # setup time 10 ns
Trrh PXPCIRST# to PX REQ64# hold Time 0 50 ns
Trhfa PXPC IRST# h ig h to f irst conf iguration access 226 clocks
Trhff PX PCIRST# high to f irst PXFRAM E# Ass ertion 5 clocks
Tpvrh Power valid to PXPCIRST# high 100 ms
Tprsu PCI-X initializ a tion p a tte rn to PX PCIRST# setup time 10 clocks
Tprh PXPCIRST# to PCI-X initialization patte rn hold time 0 50 ns 9
Trlcx Delay from P XPCIRS T# low to PXC LKO[4:0]
frequency change 0ns
NOTES:
1. Refer to Figure 41. For timing an d mea surement condition de ta ils, refer to the PCI-X A ddend um to the PCI
Local BUS Specification document.
2. Minimum times are measured at the package pin (not a test point).
3. Setup time for point-to-point si gnals applies to PXREQ[3:0] and PXGNT[3:0] only. All other signals are bused .
4. See timing measurement conditions in Figure 42.
5. PX PCI RST# is asserte d and deas se rte d a sy n ch ronously with respect to PXC LKO[ 4:0].
6. All output dr ivers must be floated when RSTIN# is active.
7. For purpose s of Act ive/Float timing measurements, th e Hi-Z or “off” state is d e fin ed to b e when the tot a l
current delivered through the component pin is less than or equal to the leakage current specification
8. Set up tim e app lie s only when the device is not dr iving the pin. Dev ices cannot d riv e and re ce iv e signals at
the same time.
9. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI -X initialization pattern control
signals after the rising edge of PXPCIRST# must be deas se rted no later than two cl ock s be fo re the first
FRAME# and must be floated no later than one c lock before FRAME# is asserted.
10.A PCI- X device is permitted to hav e the minimum values shown for Tval, Tval(ptp), and Ton only in PCI- X mode.
In conventional mode, the device must meet the requirements s pecified in PCI Local Bus Spec if icat ion,
R evi s ion 2.2, for the appro pr iate cloc k frequ ency.
11.De v ice mu st meet th is sp e cif ica tion inde pen d e n t of how ma n y ou tp ut s switch sim ulta n e ously.
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
800 Order Number: 300641-004US
Table 716. PCI Interface Timing
Sym Parameter Min Max Units Notes Figure
t40 AD[31:0] Valid Delay 2 11 ns Min: 0 pF
Max: 50
pF
Figure 4
5
t41 AD[31:0] Setup Time to PCICLK Rising 7 ns Figure 4
6
t42 AD[31:0] Ho ld Time from PCICLK Rising 0 ns Figure 4
6
t43 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR,
PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK
Rising 211ns
Min: 0 pF
Max: 50
pF
Figure 4
5
t44 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR,
PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay
from PCICLK Rising 2ns Figure 4
9
t45 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, ST OP#, PERR#,
PLOCK #, DEVS EL#, GNT[A: B]# Fl oat Del ay from PCICLK
Rising 228ns Figure 4
7
t46 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#,
PERR#, DEVSEL#, Set up Time to PCICLK Rising 7ns Figure 4
6
t47 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#,
PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCICLK
Rising 0ns Figure 4
6
t48 PXPCIRST# Low Pulse Width 1 ms Figure 4
8
t4 9 GN T[ A:B}#, GNT[5:0]# Va lid Dela y fro m PCICL K Rising 2 12 ns
t50 REQ[A:B]#, REQ[5:0]# Setup Timer to PCICLK R ising 12 ns
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 801
22—Intel® 6300ESB ICH
Table 717. IDE PIO and Multiword DMA ModeT iming
Sym Parameter Min Max Unit
sNotes Figure
t60 PDIOR#/PDIOW#/SDIOR#/SDIOW # A ctive From HICL K
Rising 220ns Figure 50
Figure 51
t61 PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From HICLK
Rising 220ns Figure 50
Figure 51
t62 PD A [2:0]/SDA[2:0] Va lid Delay From HICL K Rising 2 30 ns Figure 50
t63 PDCS1 # / SDCS1 # , PDCS 3#/SDCS3# Activ e From HICL K
Rising 230ns Figure 50
t64 PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From HICLK
Rising 230ns Figure 50
t65 PDDACK#/SDDACK# Active From HICLK Rising 2 20 ns Figure 51
t66 PD D AC K#/S DDACK# Inactive Fro m HICLK Rising 2 20 ns
t67 PDDREQ/SDDREQ Setup Time t o HICLK Rising 7 ns Figure 51
t6 8 PDDREQ / SDDREQ Hold F rom HIC LK Ris i ng 7 ns Figure 51
t69 PDD[15:0]/SDD[15:0] Valid Delay From HICLK Rising 2 30 ns Figure 50
Figure 51
t70 PD D [15:0]/SDD[15:0 ] Setup Tim e to H ICLK Ris ing 1 0 ns Figure 50
Figure 51
t71 PDD[15:0]/SDD[15:0] Hold From HICLK Rising 7 ns Figure 50
Figure 51
t72 PIORDY /SIORDY Setup Time to HICLK Rising 7 ns 1Figure50
t73 PIOR DY/SIORDY Hold From HICLK Rising 7 ns 1Figure50
t74 PIORDY /SIORDY Inactive Pulse Width 48 ns Figure 50
t75 PDIOR#/PDIO W#/SDIOR#/SDIOW# Pulse Width Low 2, 3Figure 50
Figure 51
t76 PDIOR#/PDIO W#/SDIOR#/SDIOW# Pulse Width High 3, 4Figure 50
Figure 51
NOTES:
1. IORDY is inte rna lly synchron ized. This timing is to ensure re cognition on the n e xt clock .
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
clocks when the dri ve mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register.
3. PIORDY sample point from DIOx# a ssertion, PDIOx# active pulse wid th a nd PDIOx # inactive pulse wid th
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing reg ister.
4. PDIOx# in ac t i ve pu l se width i s pr o gramm a ble fr o m 1-4 PC I c lo cks w h en t he drive mode is Mo de 2 o r gr eat er.
Refer to the RCT field in the IDE Timing Register.
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
802 Order Number: 300641-004US
Table 718. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)
Sym Parameter (1) Mode 0
(ns) Mode 1
(ns) Mode 2
(ns) Measurin
g
Location Figure
Min Max Min Max Min Max
t80 Sust aine d Cycle Tim e (T2c yctyp) 240 160 120 Sender
Connector
t8 1 Cycle Ti me (Tcyc ) 112 73 54 End
Recipient
Connector
Figure 5
3
t8 2 Tw o Cyc le Time (T2cyc) 230 153 115 Sender
Connector Figure 5
3
t83a D ata S et up T ime (Td s) 15 10 7 Recipient
Connector Figure 5
3
t83b Recipien t IC data setup time (fro m
data valid u ntil S TROBE edge)
(see Note 2) (Tdsic)
14.
79.7 6.8 Intel®
6300ESB
ICH ball
t84a D ata Hold Time (Tdh) 5 5 5 Recipient
Connector Figure 5
3
t84b Recipien t IC data hold time (from
STROBE edg e until data may be come
invalid) (see Note 2) (Tdhic) 4.8 4.8 4.8 Intel®
6300ESB
ICH ball
t85a D ata Valid Setup Time (Tdvs) 70 48 31 Sender
Connector Figure 5
3
t85b Send er IC data valid setup time
(from da t a val id u n ti l STROBE edg e)
(see Note 2) (Tdvsi c)
72.
950.9 33.9 Intel®
6300ESB
ICH ball
t86a D ata Valid Hold Time (Td vh) 6.2 6.2 6.2 Sender
Connector Figure 5
3
t86b Send er IC data valid hold time (from
STROBE edg e until data may be come
invalid) (see Note 2) (Tdvhic) 999 Intel®
6300ESB
ICH ball
t87 Limited Interlo ck Time (Tli) 0 150 0 150 0 150 See Note 2 Figure 5
5
t88 Interlock Time w/ Minimum (Tmli) 20 20 20 Host
Connector Figure 5
5
t89 Envelope Ti me (Tenv) 20 70 20 70 20 70 Host
Connector Figure 5
2
t90 Ready to Pause Time (Trp) 160 125 100 Recipient
Connector Figure 5
4
t91 DMA CK setup /hold Time (Tac k) 20 20 20 Host
Connector
Figure 5
2,
Figure 5
5
t92a CRC Word S et up Time at H ost (Tcvs) 70 48 31 Host
Connector
NOTES:
1. T he specification sy mb ols in parenth e ses corr es pond to th e AT Atta chment - 6 wit h Packet Interf a ce (ATA/
A TAPI - 6) specification name.
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
me a suring these timing paramete rs.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 803
22—Intel® 6300ESB ICH
t92b
CR C word valid hold time a t se nder
(fr om DMACK# neg ation until CRC
may become invalid) (see Note 2)
(Tcvh)
6.2 6.2 6.2 Host
Connector
t93 ST ROB E outp ut re le ase d -to-driving
to the first transition of critical timing
(Tzfs) 000 Device
Connector Figure 5
5
t94 Data Output Rel eased-to-Driving
Un til the First Tunis ia n of Cr itica l
Timi n g ( Td z f s ) 70 48 31 Sender
Connector Figure 5
2
t95 Unlimited Inter lock Time (Tui) 0 0 0 Host
Connector Figure 5
2
t96a Maximu m time allow ed f or outp ut
drivers to release (from asserted or
negated) (Taz) 10 10 10 See Note 2
t96b Mi ni mu m t ime fo r dr i ve rs t o ass er t or
ne gate (from released) (Tzad) 000 Device
Connector
t97 Ready-to-final-STROBE time (no
STROBE edges shall be sent this long
a fter neg a tion of D M AR DY# ) (Trfs) 75 70 60 Sender
Connector Figure 5
2
t98a Maximum time before releasing
IORDY (Tiord yz ) 20 20 20 Device
Connector
t98b Minimum time before driving IORDY
(see Note 2) (Tziordy) 000 Device
Connector
t99
Time from STROBE edge to negation
of DM A RQ or assertion of S TOP
(when sender te rminates a burst)
(Tss)
50 50 50 Sender
Connector Figure 5
4
Table 718. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2)
Sym Parameter (1) Mode 0
(ns) Mode 1
(ns) Mode 2
(ns) Measurin
g
Location Figure
Min Max Min Max Min Max
NOTES:
1. The sp e cif ication sy mbols in parenth e se s corresp on d t o th e AT Attach me n t - 6 wit h Pac ke t I nterface ( ATA /
ATAPI - 6) sp e cifica tion name.
2. See the AT Attachmen t - 6 wit h Packet Interfa ce (ATA/ATAPI - 6) spec if icat ion for furth er deta ils on
measurin g these timi ng par ameters .
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
804 Order Number: 300641-004US
Table 719. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2)
Sym Parameter (1) Mod e 3
(ns) Mode 4
(ns) Mode 5
(ns) Measuring
Location Figure
MinMaxMinMaxMinMax
t80 Sustained Cycle Time (T2cyctyp) 90 60 40 Sender
Connector
t81 Cycle Time (Tcy c) 39 25 16.8 End
Recipient
Connector
Figure 5
3
t82 Two Cycle Ti me (T2c yc ) 86 57 38 Sender
Connector Figure 5
3
t83 D ata Setup T ime (Tds) 7 5 4.0 Recipient
Connector Figure 5
3
t83b Recipien t IC d ata setup time
(from da ta valid until STROBE
edge) (see Note 2) (Tdsi c) 6.8 4.8 2.3 Intel®
6300ESB
ICH Balls
t84 Data Hold Time (Tdh) 5 5 4. 6 Recipient
Connector Figure 5
3
t84b
Recipient IC data hold time (f rom
STROBE edge until data may
become invalid ) (se e Note 2)
(Tdhic)
4.8 4.8 2.8 Intel®
6300ESB
ICH Balls
t85 Data Valid Setup Time (Tdv s) 20 6.7 4.8 Sender
Connector
Figure 5
2
Figure 5
3
t85b
Sender IC data valid setup t ime
(from da ta valid until STROBE
edge) (
see Note 2) (Tdvsic)
22.6 9.5 6.0 Intel®
6300ESB
ICH Balls
t86 D ata V alid Hold Time (Tdvh) 6.2 6.2 4.8 Sender
Connector
Figure 5
2
Figure 5
3
t86b
Sender IC d a ta valid hold t ime
(fro m STROBE edge until data
may become invalid) (see Note 2)
(Tdvhic)
9.0 9.0 6.0 Intel®
6300ESB
ICH Balls
t87 Limited In te rlock Ti me (Tli) 0 100 0 100 0 75 See Note 2 Figure 5
5
t88 Interloc k Time w/ Min imum (Tmli) 20 20 20 Ho st
Connector Figure 5
5
t89 Envelope Time (Tenv) 20 55 20 55 2 0 50 Host
Connector Figure 5
3
t90 Ready to Pause Time (Trp) 10 0 1 00 85 Recipient
Connector Figure 5
4
NOTES:
1. T he specification sy mb ols in parenth e ses corr es pond to th e AT Atta chment - 6 wit h Packet Interf a ce (ATA/
A TAPI - 6) specification name.
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on
me a suring these timing paramete rs.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 805
22—Intel® 6300ESB ICH
t91 DMACK setup /hold Ti me (Tack) 20 20 20 Host
Connector Figure 5
5
t92a CRC Word Setu p Time at Host
(Tcvs) 20 6.7 10 Host
Connector
t92b
CRC Word Hold Time at Sender
CRC word valid hold time at
sender (from DMACK# negation
until CRC may become invalid)
(see Note 2) (Tcvh)
6.2 6.2 10.0 Host
Connector
t93 STROBE outpu t relea s ed-t o -
driving to the fir st transition of
critical timing (Tzfs) 0035Device
Connector Figure 5
5
t94 Data Outp ut Release d -to-Driving
Until the First Transition of Critical
Timing (Tdzfs) 20.0 6.7 25 Sender
Connector Figure 5
2
t95 Unlimited In te rlock Time (Tui) 0 0 0 Host
Connector Figure 5
2
t96a Maximum time allowed for output
driv er s to re le ase (f rom asserte d
or negat ed) (Taz) 10 10 1 0 See Note 2
t96b Driver s to ass er t or ne gate (f rom
released) (Tzad) 000 Device
Connector
t97
Ready-to-final-STROB E time (no
STROBE edges shall be s ent this
long after negat ion of DMARDY#)
(Trfs)
60 60 50 Sender
Connector Figure 5
2
t98a Max imum time be fore releas ing
IORDY (Tiord y z) 20 20 20 Device
Connector
t98b Minimum time before driving
IORDY (see Note 2) (Tzio rd y) 000 Device
Connector
t99
T i me from STR OBE edge to
negation of DMARQ or assertion of
STOP (when sender terminat es a
burs t) (Tss )
50 50 50 Sender
Connector Figure 5
4
Tab l e 71 9. Ult ra ATA Tim in g (Mo d e 3, Mo d e 4, Mo d e 5) (S he e t 2 of 2)
Sym Parameter (1) Mode 3
(ns) Mode 4
(ns) Mode 5
(ns) Measuring
Location Figure
MinMaxMinMaxMinMax
NOTES:
1. The sp e cif ication sy mbols in parenth e se s corresp on d t o th e AT Attach me n t - 6 wit h Pac ke t I nterface ( ATA /
ATAPI - 6) sp e cifica tion name.
2. See the AT Attachmen t - 6 wit h Packet Interfa ce (ATA/ATAPI - 6) spec if icat ion for furth er deta ils on
measurin g these timi ng par ameters .
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
806 Order Number: 300641-004US
Table 720. Universal Serial Bus Timing
Sy
mParameter Min Max Units Notes Fig
Full Speed Source (Note 7)
t10
0USBP x+, USBPx- Drive r R ise Time 4 20 n s 1, C L = 50 pF Figure 56
t10
1USBP x+ , USBPx- Driver Fall Time 4 20 ns 1, C L = 50 pF Figure 56
t10
2
Source Differential Driver Jitter
To Next Transition
For Pa ire d Transitions -3.5
-4 3.5
4ns
ns 2, 3Figure57
t10
3Source SE0 inte rval of EOP 160 175 ns 4Figure58
t10
4Source Jitter for Differential Transition to SE0
Transition -2 5 ns 5
t10
5
Receiver Data Jitter Tole rance
To Next Transition
For Pa ire d Transitions -18.5
-9 18.5
9ns
ns 3Figure57
t10
6EOP Width: Must accept as EOP 82 ns 4Figure58
t10
7Width of SE0 interval during d ifferential transition 14 ns
Low Speed So urce (Note 8)
t10
8USBPx+ , US B Px- Driver Rise Ti me 75 300 ns 1, 6
CL = 50 pF
CL = 350 pF Figure 56
t10
9USBPx+ , US B Px- Driver Fall Time 75 300 ns 1, 6
CL = 50 pF
CL = 350 pF Figure 56
t11
0
Source Differential Driver Jitter
To Next Transition
For Pa ire d Transitions -25
-14 25
14 ns
ns 2, 3Figure57
t11
1Source SE 0 interval of EOP 1.25 1.50 µs 4Figure58
t11
2Source Jitter for Differential Transition to SE0
Transition -40 100 ns 5
t11
3
Receiver Data Jitter Tolerance
To Next Transition
For Pa ire d Transitions -152
-200 152
200 ns
ns 3Figure57
NOTES:
1. D river output resistance under steady state drive is spec’d at 28 ohms at minimum and 43 ohms at
maximum.
2. T iming difference between the differential data signals.
3. M easured at crossover point of differential data signals.
4. Me a sur ed at 50% swing poin t of dat a sign al s.
5. M easured fro m last crossover point to 50% swing point of data line a t leadin g e d ge of E OP.
6. M easure d from 10% to 90% of the data signal.
7. F ull Spee d Data Rate has minimum of 11.97 Mbp s and max imum of 12. 03 Mbps.
8. Low Sp e ed D ata Rate has a minim um of 1.48 M b p s and a maxi mum of 1.52 Mbp s.
9. Refer to the lates t revis ion of the Universal Se ria l B u s S pecification for High speed source timings
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 807
22—Intel® 6300ESB ICH
t11
4EOP W i d t h : M u st accept as EOP 670 n s 4Figure58
t11
5Width of SE0 interval during differential transition 210 ns
Tab l e 72 0. Uni v er sa l Ser ia l Bu s Ti ming
Sy
mParameter Min Max Units Notes Fig
Fu ll S peed Source (Note 7)
NOTES:
1. Driver output resistance under steady state drive is spec’d at 28 ohms at minimum and 43 ohms at
maximum.
2. Timing difference bet ween the differ ential data signals.
3. Measured at crossover point of differential data signals.
4. Measured at 50% swing point of dat a signals.
5. Measure d fr om la st crossover point to 50 % swing po in t of data line a t le ad in g edg e of EOP.
6. Measured fr om 10% to 90% of the data s ign al.
7. Full Sp eed Data Rate has mini mum of 11.97 Mbps and maximum of 12.03 M b p s.
8. Low Speed Data Rate has a minimum of 1.4 8 Mbps and a max imum of 1.52 Mbps.
9. Refer to the latest re v ision of the Un iv e rsa l Serial B us Specif icat ion for High speed source timings
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
808 Order Number: 300641-004US
Table 721. SATA Interface Timings
Sym Parameter Min Max Units Notes Figure
Operating Data Period 666.4 3 670.1
2ps
Rise Time 0.2 0.41 UI 1
Fall Time 0.2 0.41 UI 2
TX differential skew 20 ps
COMRESET 310.4 329.6 ns 3
COMWAKE transmit spacing 103.5 109.9 ns 3
OOB Operating Data p e riod 646.67 686.6
7ns 4
NOTES:
1. 20% - 80% at transmitter
2. 80% - 20% at transmitter
3. As me asure d fr om 100 mV diff erential crossp oints of last an d firs t edg e s of bur st.
4. O perating data period during Out-Of-Band burst transmi ssions.
Table 722. SMBus Timing
Sy
mParameter Min Max Units Note
sFig
t13
0Bus Tree Ti me Between Stop and Star t Cond ition 4.7 µs Figure 59
t13
1Hold Tim e after (re p e ate d ) Start Conditio n. After this
period , the fir st clo ck is generate d . 4.0 µs Figure 59
t13
2R epeated Start Condition Setup Time 4.7 µs Figure 59
t13
3Stop Con d ition Setup Tim e 4.0 µs Figure 59
t13
4Data Hold Time 0 ns 4Figure59
t13
5Data Setup Ti me 250 ns Figure 59
t13
6De vi ce Ti m e Out 25 35 ms 1
t13
7Cumulative Clock Low Extend Time (slave device) 25 ms 2Figure60
t13
8Cumula tiv e Cl ock Low Extend Tim e (master device) 10 ms 3Figure60
NOTES:
1. A d e vic e will time out when any clock low excee d s th is value .
2. t 137 is the cumulative time a slave device is allowed to extend the c lock cy cles in one me ss ag e from th e
in itial start to stop. If a slave device excee d s this tim e , it is expe cte d to re le ase both its clock and data line s
and reset itse lf.
3. t138 is the cumulative time a ma ster d evic e is allowed to e xtend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
4. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 809
22—Intel® 6300ESB ICH
Tab l e 72 3. AC’ 9 7 Timi ng
Sym Parameter Min Max Units Note
sFig
tsetup ACSDIN [2:0] S etu p to Fallin g Edg e of BI TCLK 10 ns Figure 65
thold ACSD IN [2:0] H old f rom Falling Edge of BITCLK 10 ns Figure 65
tco ACSYNC, ACSDOUT valid delay fr om rising edge of BITCLK 15 ns Figure 65
Tab l e 72 4. LPC Tim in g
Sy
mParameter Min Max Units Notes Fig
t15
0LAD[3:0] Valid Delay from PCICLK Rising 2 11 ns Figure 45
t15
1LAD[3:0] Output Enable Delay from PCICLK R ising 2 ns Figure 49
t15
2LAD[3:0] Float Delay from PCICLK Rising 28 ns Figure 47
t15
3LAD[3:0] Setup Time to PCICLK Rising 7 ns Figure 46
t15
4LAD[3 : 0] Hold Time from PCICLK Risi ng 0 ns Figure 46
t15
5LDRQ[1:0]# Setup Time to PCICLK Risi ng 12 ns Figure 46
t15
6LDRQ [1:0]# Hold Time from PCICLK Rising 0 ns Figure 46
t15
7LFRA ME # Valid Delay from PCICLK Rising 2 12 ns Figure 45
Tab l e 72 5. Mi sc el la ne o us Tim in g s
Sy
mParameter Min Max Units Notes Fig
t16
0SERIRQ Se tup Tim e to PCICLK Ris ing 7 ns Figure 46
t16
1SERIRQ Hold Time from PCIC LK Ris ing 0 ns Figure 46
t16
2RI# Pulse Width 2 RTCCLK Figure 48
t16
3SPKR Valid Delay fr om CLK14 Rising 200 ns Figure 45
t16
4SERR# Active to NMI Ac tive 200 ns
t16
5IGNNE# Inactive from FERR# Inactive 230 ns
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
810 Order Number: 300641-004US
Table 726. U ART Timi ngs
Sym Parameter Min Max Units Notes Fig
t150a S IU0_TXD, SIU1_TXD Valid Delay fr om UA RT_CLK rising 2 13 ns
t151a SIU0_DTR#, SIU0_R TS#, SIU1_DTR#, and SIU1_RTS# Valid
Del a y fr om P C ICLK Rising 213 ns
t15 2a S IU0_RXD, SIU1_RX D Se tup Time to UA RT_CL K Rising 7 ns
t15 3a S IU0_RXD, SIU1_RX D Hold Time to UART_CLK Ris ing 0 ns
t154a SIU0_CTS#, SI U0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_ RI# High
Time 100 ns
t155a SIU0_CTS#, SI U0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_ RI# Low
Time 100 ns
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 811
22—Intel® 6300ESB ICH
Table 727. Power Sequencing and Reset Signal Timings
Sym Parameter Min Max Units Notes Fig
t170 VccRTC active to RTCRST# inacti ve 5 - ms Figure 61
t171 V5RefSus active to VccSus3_3, VccSus1_5 active 0 - ms 1, 2Figure61
t172 VccRTC supply active to VccSus supplies active 0 - ms 3Figure61
t173 VccS us s u pplies active to RS M RS T # ina ctiv e 10 - ms Figure 61
Figure 62
t174 V5 Ref active to Vcc3_3, V cc1_5, VccHI active 0 - ms 1, 2Figure61
t175 VccSus supplie s active to Vcc 3_3, V cc1_5, VccHI
supp lies active 0-ms3Figure61
t176 Vcc3 _3, Vcc1 _5, VccH I su p plies active to PW RO K . 99 - ms Figure 61
Figure 62
Figure 64
t177 PWROK a ctive to SUS _S TAT # ina ctive 32 38 RTCCLK 4Figure 62
Figure 64
t17 8 S US_STAT# in ac t i ve to PXPCIRST # inact ive 1 3 RTC C LK Figure 62
Figure 64
t179 AC_RST# acti ve lo w p ulse wi dth 1 us
t180 AC_RST# inactive to BIT_CLK startup delay 162.8 ns
NOTES:
1. The V 5Ref su p p l y m u st power up bef o re or simultaneou s with its assoc ia ted 3.3 V sup p ly, and m ust power
down simu ltane ous with or a f ter the 3.3 V s upply. S ee the Intel® 6300ESB ICH Desig n Guide for details.
2. The associat ed 3.3 V and 1.5 V supplie s m ust p ower up or down simultaneously.
3. The VccSus s u p plies must never be active while the VccRTC supply is inactive.
4. SYSRESET# is not checke d for PWROK transitions (t177).
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
812 Order Number: 300641-004US
Table 728. Power Management Timings
Sym Parameter Min Max Units Notes Fig
t181 VccSus active to SLP_S5#, SU S_STAT# and PXPCIRST#
active 50 ns Figure 62
t182
t183 RSMRST# inactive to SUSCLK running, SLP_S5# inactive 110 ms 6Figure62
t183a SLPS5# inactive to SLP_S4# inactiv e 1 2 RTCCLK Figure 62
t183b SLPS4# inac tive to SLP_S3# inactive 1 2 RTCCLK Figure 62
t184 50 ns Figure 62
Figure 64
t187 STPCL K # active to Stop Grant cycle N/A N/A 2Figure63
t188 St op Grant cycle to CPUS LP# active 60 63 PCICLK 3Figure 63
Figure 64
t189 S1 Wake Event to CPU S LP# inactive 1 25 PCICL K 4Figure63
t190 CPUSL P# inactive to STPCLK# inac tive 3.87 245 µs Figure 63
t192 CPUS L P # activ e to SU S _STAT# active 2 4 RTCCLK 1Figure64
t193 SUS _S TAT # a ctive to PXPCIRST# active 9 21 RTCCLK 1
t194 PXPCIRS T# active to S LP_S3# active 1 2 RTCCLK 1Figure64
t194a SLP_S3# active to S LP_ S4 # activ e 1 2 RTCCLK 1Figure64
t195 SLP_S 4# ac tive to SLP_S5# active 1 2 RTCCLK 1, 5Figure64
t196 SLP_S3# active to PWROK inactive 0 ms 4Figure64
t197 PWROK ina ctive to Vcc supplies in active 20 ns Figure 64
t198 W ake Event to SLP_S5# inactive 1 10 R T CCLK 1
t198a Wake Event to SLP_S 4# inactive(S4 Wake) 1 10 RTCCLK 1
t198b S3 Wake Event to SLP_ S3 # inactiv e (S 3 Wake) 0 2 RTCCLK 1
t198d SLP_S5# inactive to SLP_S4# inactive 1 2 RTCCLK 1Figure64
t198e SLP_S4# inactive to SLP_S 3# inacti ve 1 2 RTCCLK 1Figure64
t220 THRMTRIP# active to SLP_ S3#, SLP_S4#, SLP_S5#
active 2 PCI CLK
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. The Intel® 6300ES B ICH STPCLK # asse rtion will tr igge r the p roce ssor to send a stop grant ackno wle dge
cyc le. The timing f or this cycl e getting to the Intel® 6300ES B ICH is depend ant on the process or and the
memory controller.
3. T hese transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
4. The Intel® 6300ESB ICH has no maximum timing requ ire ment for this transitio n. It is up to the system
designer to determine if the SLP_S3#, SL P_S4# and SL P_S5# signals are used to control the power planes.
5. If the transition to S5 is due to Power Button Override, SLP_S 3#, S LP_S4# and SLP _S5# are asserted
tog et h er similar to timin g t19 4 (PXPCIRST# active to S LP_S3# active).
6. If there is no RTC battery in the system, so VccR TC and the VccSus supplies come up together, the delay from
RTCRST# and RSMRST# inactive to SUSCLK toggling m ay be as much as 2.5 s.
7. This value is pro gramm ab le in multip le s of 1024 PCI CLKs. Maxim um is 8192 PCI CLKs (245. 6 µs).).
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 813
22—Intel® 6300ESB ICH
22.5 Timing Diagram s and Test Conditions
22.5.1 PCI-X
Figure 39. PCI-X 3.3V Clock
Figure 40. Clock Uncertainty (PXPCLK[0:4])
Table 729. Clock Uncertainty Parameters
Symbol Parameter Units
Vtest-clk 0.4Vcc V
Tskew 0.4(Max) ns
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vc c
0.3 Vcc
T_cyc
T_high T_low 0. 4 Vcc , p-t o-p
(minimum)
3.3 volt Clock
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
814 Order Number: 300641-004US
Figure 41. PCI-X Output Timing
Figure 42. PCI-X Input Timing
CLK
OUTPUT
DELAY
OUTPUT
DELAY
Tri-State
OUTPUT
V_test
T_val
V_th
V_tl
V_tfall
V_trise
T_val
T_on
T_off
CLK
INPUT V_th
V_tl
V_test inputs vali d V_test V_max
T_su T_h
V_test
V_th
V_tl
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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22—Intel® 6300ESB ICH
22.5.2 System Clocks and General Timing
Table 730. PCI-X M easurement Condition Parameters
Symbol Value Units Notes
Vth 0.6 Vcc V 1
Vtl 0.25 V cc V 1
Vtes t 0.4 Vc c V
Vrise 0.2 85 V cc V 2
Vtfall 0.615 Vcc V 2
Vmax 0.4 Vcc V 1
Input Signal Slew Rate 1.5 V/ns 3
NOTES:
1. The test for the 3.3V environment is done with 0.1*Vcc of overdrive. Vmax specifies the
maxi m um peak-to -peak wav e for m al lowe d for measu r in g input timing. Produ c t ion t esti ng is
permitted to use di fferent voltage values but must correlate results back to these
parameters.
2. Vtrise and Vtfall are reference voltages for timing measurements only.
3. Input signal slew rate in PCI-X mode is measured between Vil and Vih.
Figure 43. PCI-X RST# Timing for switching to PCI-X Mode Pull-ups
Figure 44. Clock Timing
T_rlcx T_rst_clk(ref)
T_rhff(ref)
T_prh
T_prsu
T_rst(ref)
PCI_CLK
RST#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
2.0V
0.8V
Period
High Time
Low Time
Fall Time R ise Time
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
816 Order Number: 300641-004US
Figure 45. Valid Delay from Rising Clock Edge
Figure 46. Setup and Hold Times
Figure 47. Float Delay
Figure 48. Pulse Width
Clock 1.5V
Valid Delay
VT
Output
Clock
VTInput
Hold TimeSetup Time
VT
1.5V
Clock VT
Output
Float
Delay
VT
Pulse Width
VT
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22—Intel® 6300ESB ICH
22.5 .3 IDE and Ultra ATA Timing
Figure 49. Output Enable Delay
Figure 50. IDE PIO Mode
Clock
Output
Output
Enable
Delay
VT
1.5V
B3925-01
HICLK
DIO
x
DD[15:0]
Read
DD[15:0]
Write
t60 t61
t76
t71
t70
IORDY
DA[2:0],
CS1#
t75
Write
t69 t69
t74
Read
t64t62, t63
t73
t72
Sample
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
818 Order Number: 300641-004US
Figure 51. IDE Multiword DMA
Figure 52. Ultra ATA Mode (Drive Initiating a Burst Read)
HICLK
idedma.vs
d
t67
DDREQ[1:0]
DDACK[1:0]
t65
DIOx#
DD[15:0] Read
DD[15:0] Write
t60
t61
t75
t76
t70
t71
t69
t69
Read Data
Write Data
Write Data
Read Data
t68
DMARQ
(drive) t91
t89
t89
DMACK# (host)
STOP
(host)
DMARDY#
(host)
STROBE
(drive)
DD[15:0]
DA[2:0], CS[1:0]
t96
t98
t94 t95
t85 t86
t97
t99b
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22—Intel® 6300ESB ICH
Figure 53. Ultra ATA Mode (Sustained Burst)
Figure 54. Ultra ATA Mode (Pausing a DMA Burst)
STROBE @ sender
t81
Data @ sender
t86
t85
t86
t85
t81
t82
t86
STRO BE @ receiver
Data @ receiver
t84
t83
t84
t83
t84
t99e t99e t99e
t99d t99d
t99g t99g t99g
t99f t99f
t90
STROBE
DATA
STOP (host)
DMARDY#
t99
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
820 Order Number: 300641-004US
22.5.4 USB
Figure 55. Ultra ATA Mode (Terminating a DMA Burst)
Figure 56. USB Rise and Fall Times
t88
STOP
(host)
Strobe
(host)
DMARDY#
(drive)
DATA
(host)
DMAC K# (host)
t91
t87
DMARQ
(drive)
CRC
t99c
t87
t99a
t91
t92 t93
Differential
Data Lines
90%
10% 10%
90%
tR tF
Rise Time Fall Time
C
L
C
L
Low Speed: 75 ns at C
L
= 50 pF, 300 ns at C
L
= 350 pF
Full Speed: 4 to 20 ns at C
L
= 50 pF
High Speed: 0.8 to 1.2 ns at C
L
= 10 pF
Intel® 63 00ESB I/O Controller Hub
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22—Intel® 6300ESB ICH
22.5.5 SMBus
Figure 57. USB Jitter
Figure 58. USB EOP Width
Figure 59. SMBus Transaction
Paired
Transitions
Consecutive
Transitions
Crossover
Points
T period
Differential
D ata Lines
Jitter
Differential
Dat a Li nes
EOP
Width
Data
Crossover
Level
Tperiod
t130
SMBCLK
SMBDATA
t131
t19
t134
t20 t21
t135 t132 t18 t13
3
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
822 Order Number: 300641-004US
22.5.6 Power an d Reset
Figure 60. SMBus Timeout
Figure 61. Power Sequencing and Reset Signal Timings
Start Stop
t137
CLK
ack
CLK
ack
t138 t138
SMBCLK
SMBDATA
VccRTC
RTCRST#
V5RefSus
VccSus3_3,
VccSus1_5
RSMRST#
V5Ref
Vcc3_3, Vcc1_5,
VccHI
PWROK
T170
T172
T171
T173
T174
T175 T176
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22—Intel® 6300ESB ICH
Figure 62. G3 (Mechanical Off) to S0 T imings
VccSus
SUSCLK
SLP_S4#
Vcc
PWROK
SUS_STAT#
PXPCIRST#
STPCLK#,
CPUSLP#
Hub interface "CPU
Reset Complete"
message
RSMRST#
G3 S5 S0 S0 stateG3 - S5
System
State S4
SLP_S3#
SLP_S5#
Running
T181
T181
T173
T182
T183
T183b
T183a
T176
T177
T178
T184
Figure 63. S0 to S1 to S0 Timing
T187
T188 T189
T190
ich2_S0_S1D_timing.vsd
S0 S0 S1 S1 S1 S0 S0
STATE
STPCLK#
PCI Stop Grant
Cycle
CPUSLP#
Wake Event
Intel® 6300ESB ICH—22
Intel® 6300ESB I/O Controller Hub
DS November 2007
824 Order Number: 300641-004US
22.5.7 AC’97 and Miscellaneous
Figure 64. S0 to S5 to S0 Timings
Figure 65. AC’97 Data Input and Output Timings
STPCLK#
St op Gr ant
Cycle
CPUSLP#
SUS_STAT#
PXPCIRST#
SLP_S3#
SLP_S5#
Wake Event
PWROK,
VRMPWRGD
Vcc
S0 S0 S3 S3 S5 S0
T188
T192
T193
T194
T196
T197
T176
T177
T178
T184
T187
SLP_S4#
T194a
T195 T198d
T198e
S4 S4 S3 S3/S4/S5 S0
VOH
VOL
AC_SDOUT
AC_SDIN[2:0]
AC_SYNC
AC_BIT_CLK VI H VI L
tco
thold
tsetup
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23—Intel® 6300ESB ICH
Testability 23
23. 1 Test Mode Desc r i ption
The Intel® 6300ESB ICH supports two types of test modes, a tri-state test mode and a
XOR Chain test mode. Driving RTCRST# low for a specific number of PCI clocks while
PWROK is high will activate a particular test mode as described in Table 731.
Note: RTCRST# can be driven low any time after PXPCIRST# is inactive.
.
Figure 66 illustrates entry into a test mode. A particular test mode is entered upon the
rising edge of the RTCRST# after being asserted for a specific number of PCI clocks
while PWROK is active. To change test modes, the same sequence should be followed
again. To restore the Intel® 6300ESB ICH to normal operation, execute the sequence
with RTCRST# being asserted so that no test mode is selected as specified in
Table 731.
Table 731. Test Mode Selection
Number of PCI Clocks
RTCRST# driven low after
PWROK active
Numbe r of PCI Clocks after
RTCR ST# dr iv en high Test Mode
<4 N/A N o Test Mode Selecte d
43XOR Chain 1
53XOR Chain 2
63XOR Chain 3
73XOR Chain 4
8 3 All “Z”
9 - 13 N/A Reserved . DO NOT ATTEMPT
14 3 Long XOR
15 - 42 N/A Reserved. DO NOT ATTEMPT
43 - 51 N/A No Test Mode Selecte d
52 3 X OR Chain 6
53 3 XOR Chain 4 Ba ndgap
59 3 X OR Chain 5
60 3 X OR Chain 7
>60 N/A No Test Mode Selected
Intel® 6300ESB ICH—23
Intel® 6300ESB I/O Controller Hub
DS November 2007
826 Order Number: 300641-004US
23.2 Tri-State M o de
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including
the XOR Chain outputs.
23.3 XOR Ch ai n Mode
In the Intel® 6300E SB ICH , pro vi sions for Auto ma ted Test Equi pmen t (ATE) board lev el
testing are implemented with XOR Chains. The Intel® 6300ESB ICH signals are
grouped into seven independent XOR chains which are enabled individually. When an
XOR chain is enabled, all output and bi-directional buffers within that chain are tri-
stated, except for t he XOR chain output. Every signal in the enabled XOR chain (except
for the XOR chain’s output) functions as an input. All output and bi-directional buffers
for pins not in the selected XOR chain are tri-stated. Figure 67 is a schematic example
of XOR chain circuitry.
23.3.1 XOR Chain Testability Algorithm Example
XOR c hain test in g allow s mother board ma nufa ctur ers to chec k compon ent con necti vi ty
(e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in
Table 732.
Figure 66. Test Mode Entry (XOR Chain Example)
Number of PCI Cl ocks RTCRST# driven low
af ter PW ROK ac tive
Num b er of PCI Clo cks
after RTCRS T # driven high
Test Mode Entered
All Output Signals Tri-Stat ed XOR Chain Output Enabled
RSMRST#
PWROK
RTSRST#
Other Signal
Outputs
Figure 67. Example XOR Chain Circuitry
Input
Pin 2
Vcc
Input
Pin 1 Input
Pin 3 Input
Pin 4 Input
Pin 5 Input
Pin 6
XOR
Chain
Output
Testability
Intel® 63 00ESB I/O Controller Hub
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In this example, Vector 1 applies all “0s”
to the chain inputs. The outputs being
non-inverting, will consistently produce a
“1” at the XOR output on a good board.
One sho rt to Vcc (o r open floating to Vcc)
will result in a “0” at the chain output,
signaling a defect.
Likewise, applying Vector 7 (all “1s”) to the chain inputs (given that there are an even
number of input signals in the chain), will consistently produce a “1” at the XOR chain
output on a good board. One short to Vss (or open floating to Vss) will result in a “0 at
the chain output, signaling a defect. It is important to note that the numb er of inputs
pulled to “1” will affect the expected chain output value. If the number of chain inputs
pul led to “1” is eve n, then exp ect “1” at th e ou tput. If th e nu mber of chain i nputs pu ll ed
to “1” is odd, expect “0” at the output.
Cont in ui ng w it h t he exa mpl e i n Table 732, as the input pins are dri ven to “1” acros s t he
chain in sequence, the XOR Output will toggle between “0” and “1. Any break in the
toggling sequence (e.g., “1011”) will identify the location of the short or open.
Table 732. XOR Test Pattern Example
Vector Input
Pi n 1 Input
Pin 2 Input
Pi n 3 Input
Pin 4 Input
Pi n 5 Input
Pin 6 XOR
Output
10000001
21000000
31100001
41110000
51111001
61111100
71111111
Table 733. XOR Chain #1
(RTCRST# asserted
for 4 PCI clocks
whi le PWR OK act ive)
(Sheet 1 of 2)
Pin Name Ball #
PLOCK# J6
C/BE[3]# H5
PCICLK J5
GPIO [33] / PX IRQ[0]# G1
GPIO [34] / PX IRQ[1]# H1
GPIO [35] / PX IRQ[2]# H2
GPIO [36] / PX IRQ[3]# J 3
PXREQ[1]# L6
GPIO[0] / PXREQ[2]# J1
PXGNT0# K1
PXIRDY# R4
PXFRAME# R6
PXSTOP# T2
PXTRDY# T5
PXSERR# U1
PXC/BE[1]# U2
PXPAR U4
PXPERR# U6
PXC/BE[0]# AA1
RASERR# AE1
PXREQ64# AE5
PXACK64# AF4
OUTPU T IRQ[14] AC23
Table 733. XOR Chain #1
(RTCRST# asserted
for 4 PCI clocks
while PWROK active)
(Sheet 2 of 2)
Pin Name Ball #
Testability
Intel® 63 00ESB I/O Controller Hub
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Table 734. XOR Chain #2
(RTCRST# asserted
for 5 PCI clocks
while PWROK active)
(Sheet 1 of 3)
Pin Na me B all #
PDD[6] AH24
PDD[4] AJ25
PDD[7] AC20
PDD[11] AH25
PDD[5] AD21
PDD[8] AF23
PDD[9] AB20
PDD[13] AJ26
PDD[2] AH26
PDD[3] AD22
PDD[10] AC22
PDDREQ AF24
PDD[12] AE23
PDD[14] AE24
PDD[1] AG25
PDD[15] AH27
PDD[0] AF25
PDIOR# (/PDWSTB /
PRDMARDY#) AB21
PIORDY (/PDRS TB /
PWDMARDY#) AF26
PDDACK# AB22
PDIOW# (/PDSTOP) AB23
IRQ[14] AC23
PDA[1] AG27
PDA[0] AG28
PDCS1# AF27
PDA[2] AA23
PDCS3# AD25
REQ[2]# B11
REQ[3]# D12
GNT[3]# G13
GNT[2]# C11
GPIO[2] / PIRQ[E]# B10
GPIO[3] / PIRQ[F]# A10
PIRQ[C]# A9
PIRQ[A]# E12
GPIO[5] / PIRQ[H]# A8
PIRQ[D]# B8
PIRQ[B]# A6
GPIO[4 ] / PIR Q[G]# D10
REQ[1]# G12
GNT[1]# D9
AD[18] B7
REQ[0]# D8
AD[28] H12
AD[15] C7
GNT[0]# E10
AD[22] B6
AD[30] G11
AD[20] A5
AD[16] A4
AD[4] F10
AD[24] E8
AD[0] H11
STOP# B5
AD[11] B4
AD[26] E7
AD[6] D6
TRDY# F9
FRAME# G10
AD[7] B3
AD[9] D5
AD[2] C3
PAR G9
AD[5] D4
AD[13] F6
AD[1] G8
SERR# E4
C/BE[0]# C2
Tab l e 73 4. XO R Cha in # 2
(RTC RS T# ass erte d
for 5 PCI clocks
wh ile PWR OK ac tiv e)
(Sheet 2 of 3)
Pin Name B all #
Testability
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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C/BE[1]# G7
AD[8] H8
AD[3] F5
IRDY# E3
PERR# D2
AD[14] D1
AD[12] G6
AD[10] E2
AD[23] H7
C/BE[2]# F4
DEVSEL# G5
AD[17] E1
AD[19] F2
AD[21] K8
AD[25] K7
AD[27] F1
AD[29] H4
AD[31] G2
OUTPUT FERR# A A 29
Table 735. XOR Chain #3
(RTCRST# asserted
for 6 PCI clocks
while PWROK active)
(Sheet 1 of 4)
Pin Na m e Ball #
IRQ[15] V23
VRMPWRGD Y26
A20GATE AB29
RCIN# V26
THRMTRIP# AA28
FERR# AA29
A20M# W27
INTR Y28
NMI Y29
IGNNE# U24
INIT# W28
Table 734. XOR Chain #2
(RTCRST# asserted
for 5 PCI clocks
whi le PWR OK act ive)
(Sheet 3 of 3)
Pin Name Ba ll #
STPCLK# W29
SMI# V29
CPUSLP# V28
HL6 T26
HL5 U28
HL7 R24
HL4 U29
HLCOMP T27
HI_STB/HI_STBS T28
HI_STB#/HI_STBF T29
HL3 R28
HL2 R29
HL1 P28
HL0 P29
HL10 N28
HL8 N29
HL9 N25
HL11 M28
NC M29
NC L29
NC L28
NC M25
NC K29
CLK14 L26
GPIO[32] / WDT
_TOUT# M24
SPKR K27
SATALED# J28
GPIO[40] H29
GPIO[18] J27
GPIO[19] L24
GPIO[20] H28
GPIO[21] K25
GPIO[23] L22
GPIO[42] G29
GPIO[38] F29
GPIO[43] K24
GPIO[41] H26
NC G28
Table 735. XOR Chain #3
(RTCRST# asserted
for 6 PCI clocks
while PWROK active)
(Sheet 2 of 4)
Pi n Name Ball #
Testability
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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NC J23
NC H25
NC F28
NC G27
NC F27
NC H24
NC G25
AC_BIT_CLK G19
AC_SYNC F20
AC_SDOUT E20
NC G18
GPIO[6] C21
GPIO[7] B22
NC A22
NC B21
NC A21
NC D19
GPIO[39] E19
GPIO[37] D20
NC B20
SERIRQ G17
SIU1_RXD D18
SIU1_TXD C19
SIU1_CTS# A20
SIU1_DSR# B19
SIU1_DCD# A19
SIU1_RI# D17
SIU1_DTR# B18
SIU1_RTS# G16
UART_CLK A18
SIU0_RXD B17
SIU0_TXD A17
SIU0_CTS# D16
SIU0_DSR# E17
SIU0_DCD# B16
SIU0_RI# A16
SIU0_DTR# E15
SIU0_RTS# F16
LAD[0] C15
Table 735. XOR Chain #3
(RTCRST# asserted
for 6 PCI clocks
while PWROK active)
(Sheet 3 of 4)
Pin Name Ball #
LAD[1] B15
LDRQ[0]# F14
LAD[2] A15
LAD[3] A14
LDRQ[1]# G14
LFRAME# B14
THRM# D14
NC B13
NC A13
NC F13
NC B12
NC A11
NC E13
OU TPUT IRQ[ 1 4] AC 23
Tab l e 73 5. XO R Cha in # 3
(RTC RS T# ass erte d
for 6 PCI clocks
while PWROK active)
(Sheet 4 of 4)
Pin Name Ball #
Testability
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
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Table 736. XOR Chain #4
(RTCRST# asserted
for 7 PCI clocks
while PWROK active)
(Sheet 1 of 2)
Pin Name Ball #
PXPCIRST# AH8
GPIO[25] AH9
GPIO[8] AE12
GPIO[12] AF11
NC AD13
GPIO[27] AG10
GPIO[13] AC14
PME# AJ8
RI# AH10
GPIO[28] AJ9
SLP_S4# AD14
PWRBTN# AJ10
SYSRESET# AH11
SLP_S5# AJ11
SMLINK[1] AH12
GPIO[24] AE14
SUSCLK AJ12
SUS_STAT# AD15
SMLINK[0] AH13
SLP_S3# AG14
SMBDATA AJ13
SMBCLK AH14
GPIO [11] / S M B ALERT# AF15
NC AJ14
NC AJ15
OC[0]# F24
OC[2]# G23
OC[1]# F23
OC[3]# E24
AC_SDIN0 F22
AC_RST# E23
AC_SDIN2 E22
AC_SDIN1 E21
GPIO[56] C22
GPIO[57] D22
OUTPUT FERR# AA29
Table 737. XOR Chain #5
(RTCRST# asserted
for 59 PCI clocks
while PWROK active)
(Sheet 1 of 4)
Pin Name Ball #
PXPCLKO[0] J2
PXPCLKO[1] L8
PXPCLKO[2] K6
PXPCLKO[3] K4
PXPCLKO[4] L5
PXAD[31] K2
PXAD[29] M7
PXAD[28] L3
PXREQ[0]# L2
PXAD[30] M5
PXAD[27] L1
PXAD[26] M2
PXAD[25] M1
PXC/BE[3]# N6
PXAD[24] N4
PXAD[23] N3
PXAD[20] N2
PXAD[22] N1
PXAD[21] P7
PXAD[19] P5
PXAD[18] P2
PXAD[17] P1
PXAD[16] R1
PXC/BE[2]# R2
PXPLOCK# T1
PXDEVSEL# T3
Table 736. XOR Chain #4
(RTCRST# asserted
for 7 PCI clocks
while PWROK active)
(Sheet 2 of 2)
Pin Name Ball #
Testability
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 832
PXAD[15] T7
PXAD[12] V1
PXAD[11] V2
PXAD[13] V4
PXAD[8] W1
PXAD[9] W2
PXAD[14] Y1
PXM66EN W4
PXAD[6] Y2
PXAD[2] V7
PXAD[4] AA2
PXAD[3] Y4
PXAD[47] AB1
PXAD[10] AA4
PXAD[45] AB2
PXAD[1] W7
PXAD[43] Y6
PXAD[46] AC1
PXAD[42] AB3
PXAD[5] W8
GPIO[16] / PXGNT[2]# AC2
GPIO[17] / PXGNT[3]# Y7
PXAD[41] AD1
PXAD[7] AA6
PXAD[40] AD2
GPIO[1] / PXREQ[3]# Y8
PXGNT1# AB5
PXPCLKI AC4
PXPCICLK AC5
PCIXSBRST# AA7
PXAD[44] AB7
PXAD[35] AE2
PXAD[38] AD4
PXAD[32] AF1
PXAD[34] AE3
Table 737. XOR Chain #5
(RTCRST# asserted
f o r 59 P C I cloc ks
while PWROK active)
(Sheet 2 of 4)
Pin Name Ball #
PXAD[39] AC6
PXAD[0] AF2
PXAD[54] AB9
PXAD[33] AE4
PXAD[37] AD6
PXC/BE[5]# AG2
PXAD[36] AD7
PXAD[63] AH3
PXPAR64 AD8
PXAD[50] AC10
PXC/BE[4]# AE7
PXC/BE[7]# AF6
PXAD[60] AG5
PXAD[62] AH4
PXAD[59] AH5
PXAD[48] AD10
PXC/BE[6]# AF7
PXAD[51] AE9
PXAD[61] AJ4
PXAD[57] AH6
PXAD[58] AJ5
PXAD[56] AJ6
PXAD[53] AF9
PXAD[49] AE10
PXAD[55] AH7
PXAD[52] AJ7
SDD[7] AF28
SDD[9] AE26
SDD[5] AF29
SDD[8] Y23
SDD[3] AD26
SDD[6] W22
SDD[10] AB24
SDD[12] AE28
SDD[11] AC26
Tab l e 73 7. XO R Cha in # 5
(RTC RS T# ass erte d
for 59 PCI clocks
wh ile PWR OK ac tiv e)
(Sheet 3 of 4)
Pin Name Ball #
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 833
23—Intel® 6300ESB ICH
SDD[1] AE29
SDD[4] AA24
SDD[13] AB25
SDDREQ AD28
SDD[14] AD27
SDDACK# Y24
SIORDY / ( SDRSTB/
SWDMARDY#) W24
SDA[1] AD29
SDD[15] AC28
SDD[2] AB27
SDA[2] AC29
SDIOW# / (SDST OP) Y25
SDD[0] AA26
SDCS1# AB28
SDIOR# / (SDWSTB/
PRDMARDY#) W25
SDCS3# AA27
SDA[0] V24
OUTPU T IRQ[15] V23
Table 737. XOR Chain #5
(RTCRST# asserted
for 59 PCI clocks
whi le PWR OK act ive)
(Sheet 4 of 4)
Pin Nam e Ball #
23—Intel® 6300ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 834
Table 738. XOR Chain #6 (RTCRST# asserted for 52 PCI clocks while
PWROK active)
Pin Name Ball #
INTRUDER# AG23
RTCX1 AE21
OUTPUT IRQ[15] V23
Table 739. XOR Chain #7 (RTCRST# asserted for 60 PCI clocks while
PWROK active)
Pin Na me Ba ll #
SATACLKN AJ17
SATACLKP AH17
SATA[0]RXN AJ19
SATA[0]RXP AH19
SATA[0]TXN AG18
SATA[0]TXP AF18
SATA[1]RXN AJ21
SATA[1]RXP AH21
SATA[1]TXN AG20
SATA[1]TXP AF20
SATARBIASN AJ23
SATARBIASP AH23
OUTPU T LDRQ[1]# G14
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 835
—Intel® 6300ESB ICH
Index
GP_LVL 432, 433
6 Chan nel Capabili ty 575, 602
64-bit Add ressing Ca pabi lit y 507
A
A20Gate Pass-Through Enable (A20PASSEN) 471
AC ‘97 Co ld Reset# 574, 601
AC ‘97 Int errupt Rout ing 590
AC’97 Warm R eset 574, 601
AC97_EN 404
AC97_STS 403
ACLI NK Sh ut Off 573, 600
AD3 576, 603
ADDRESS 539
Addr ess Incr em ent/Decr em ent Selec t 352
Address of De scriptor Table (ADDR) 459, 769
AD L IB _A C T _STS 412
ADLIB_LPC_EN 337
ADLIB_TRP_EN 414
AF Alarm Flag 380
AFTERG3_EN 387
AIE Alarm I nterrupt Enable 378
ALT_A20_GATE 382
ALTACC _EN Alte rnate Ac cess Mode Enabl e 328
APIC Data 370, 641
APIC ID 37 1 , 64 3
APIC Index 369, 641
APIC_EN 328
APM_STS 409
APMC _EN 406
Asynchronous Schedule Enable 509
Asynchronous Schedule Status 512
AUDIO_ACT_STS 412
AUDIO_TRP_EN 414
Autoinitialize Enable 353
Autom at ic End of Int errupt (AEO I) 364
Automati cally Append CRC (AAC) 544
Aux_ C urrent 493
B
BAR Number 496
Base Address 441, 442, 443, 556, 557, 587, 588, 744, 745, 746
Bas e and Current Ad dress 348
Bas e and Cu rr ent Count 349
Bas e Class Co de 441, 743
Binary/BCD Countdown Select 356
BIOS_EN 407
BIOS_RLS BIOS Release 406
BIOS _STS 409
BIOSWR_STS 419
BIST FIS Fai led 764
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
836 Order Number: 300641-004US
BIST FI S Parameters 765
BIST FIS Succe ss ful 764
BIST FIS Transmit Data 1 765
BIST FIS Transmit Data 2 766
Bit 1 of slo t 12 576, 603
Bit 2 of slo t 12 576, 603
Bit 3 of slo t 12 576, 603
Bit Clock Stopped ( B C S) 575, 602
Block Data (BDTA) 541
BOOT_STS 421
Bu ff er Com pletion Inte rrupt Status (BCIS) 570, 596
Buffer Descriptor Base Address 568
Buffer Descriptor List Base Address 595
Bu ffered Mo de ( B U F ) 364
Bu s Master Enable (BME) 437, 463, 552, 583, 740
Bus Master IDE Active (ACT) 458, 768
BUS_ERR 53 5
BYTE_DONE_STS 535
C
Ca p ID (CA P) 562
Capability ID 499
Ca scaded Interrupt Co ntroller IRQ C onnection 363
Ch annel 1 Selec t 327
Ch annel 2 Selec t 327
Ch annel 3 Selec t 326
Ch annel 5 Selec t 326
Ch annel 6 Selec t 326
Ch annel 7 Selec t 326
Ch annel M ask B it s 355
Channel Mask Select 352
Ch annel Reques t St atus 351
Channel Terminal Count Status 351
Clear Byte Pointer 353
Clear Mask Register 35 4
CNF1_LPC_EN 337
CNF2_LPC_EN 337
Co dec Access Sema phore (C A S) 604
Co dec Wri te In Pr ogress (CWIP) 578
COM A De code Range 332
CO M A _ LPC _EN 338
COM B D ecode Range 332
COMB_LPC_EN 338
Co nfi gure Flag (CF) 47 4
Co nnect Status Change 484, 521
COPR_ERR_EN Coprocessor Error Enable 328
COPROC_ERR 383
Count Register Status 359
COUNT_SIZE_CAP 606
Co untdown Type Status 359
Counter 0 Select 357
Counter 1 Select 357
Counter 2 Select 357
Counter Latch Command 358
Co unter OUT Pi n State 359
Counter Port 360
Counter Select 356
Counter Selection 358
COUNTER_CLK_PER_CAP 606
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 837
—Intel® 6300ESB ICH
COUNTER_VAL 609
CPU Thermal Trip Status (CTS 386
CPU_BIST_EN
Enables CPU BIST 330
CPUPWR_FLR CPU Powe r Failure 386
CPUSLP_EN 385
Cur re nt Connect Status 484, 521
Current Eq uals Las t Valid (CELV) 570, 597
Cur re nt I ndex Va lue 569, 595
D
D1_Support 493
D2_Support 493
D29_F0_Disable 343
D29_F1_Disable 343
D29_F7_Disable 343
D31_F1_Disable 344
D31_F3_Disable 344
D31_F5_Disable 343
D31_F6_Disable 343
Data 761
DATA_HIGH_BYTE 548
DATA_LEN_CNT 524
DATA_LOW_BYTE 548
DATA_MSG0 Data Messag e Byte 0 543
DATA_MSG1 Data Messag e Byte 1 543
DATA0/COUNT 540
DATA1 540
Date Alarm 380
DCB_EN DMA Coll ection Buffer Enable 329
Debug Port Number (DP_N) 505
Deb ug Port Off set 496
Delivery Mode 374
Delivery Sta tus 374, 645
Des ti nat ion 373, 644
Des ti nat ion Mode 374, 6 45
DEV_ERR 536
DEV_TRAP_EN 411
DEV_TRAP_STS 411
Device Connects 231
Device ID value 52 8
DEVICE_ADDRESS 547
DEVMON_STS Device Monitor Status 408
DEVSEL# Timin g Sta tu s (DEVT) 464, 529, 553
DM Data Mode 37 9
DMA Channel Group Enable 350
DMA Cha nnel Se lect 352, 353
DMA Controller Halted (DCH) 570, 597
DMA Group Arbitration Priority 345, 350
DMA Low Page 350
DMA Transfer Mode 352
DMA Transfer Type 353
DONE_STS 523
Driv e 0 D M A C ap abl e 457, 768
Drive 0 DMA Timing Enable (DTE0) 450, 749
Drive 0 Fast Timing Bank (TIME0) 450, 749
Dr iv e 0 IORD Y S amp le Point Enable (IE 0 ) 45 0 , 749
Drive 0 Prefetch/Posting Enable (PPE0) 450, 749
Driv e 1 D M A C ap abl e 457, 768
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
838 Order Number: 300641-004US
Drive 1 DMA Timi ng Enable (DTE1) 449, 749
Drive 1 Fast Timing Ban k (TIME1) 450, 749
Drive 1 IORDY Sample Point Enable (IE1) 449, 749
Dr iv e 1 Prefet ch/Posting Enable (PPE1) 449, 749
Dr iv e 1 Timing Registe r Enable (SITR E) 448, 748
DSE Daylight Savings Enable 379
DSI 493
DT Del iver y Type 3 73, 644
DTE Delayed Tr ans acti on Enable 329
DV Division Ch ain Select 377
E
Edge/Level Ba nk Sel ect (LTIM ) 36 1
EHC Initialization 221
EHC Resets 222
EHCI Exte nded Capabili ti es Pointer (EEC P) 507
Enable 32-by te Buf fer ( E32B ) 544
Enable Special Mask Mode (ESMM) 366
ENABLE_CNF
Overall Enable 607
ENABLED_CNT 522
Enter Global Suspend Mode (EGSM) 475
EOS En d of SMI 407
Erro r 458, 76 8
ERROR_GOOD#_STS 523
EXCEPTIO N _STS 5 23
Extended D estinat ion ID (EDID) 373, 644, 646
F
FAILED 535
Fast Non-Data PIO (FNDPIO) 449
FAST_PCB0 Fast Primary Drive 0 Base Clock 754
FAST_PCB1 Fast Primary Drive 1 Base Clock 754
FAST_SCB0 Fast Secondary Drive 0 Base Clock 754
FAST_SCB1 Fast Secondary Drive 1 Base Clock 754
FDD Decode Range 333
FDD_LPC_EN 338
FIFO error (FIFOE) 570, 596
FIFO Error Interrupt Enable (FEIE) 572, 599
Force Global Resume (FGR) 474
Forc e Por t Res ume 520
FORCE_THTL 398
Fram e Lengt h Timing Value 497
Fr am e Li st Curren t Index/Fr ame Num b er 481, 515
Frame List R oll over 513
Frame List Rollover Enable 514
Frame List Siz e 510
FRE Q _STRA P 330
FULL _R ST 383
FWH_C0_EN 336, 342
FWH_C0_IDSEL 339
FWH_C8_EN 336, 342
FWH_C8_IDSEL 339
FWH_D0_EN 336, 342
FWH_D0_IDSEL 339
FWH_D8_EN 335, 342
FWH_D8_IDSEL 339, 341
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 839
—Intel® 6300ESB ICH
FWH_E0_EN 335
FWH_E0_IDSEL 339, 341
FWH_E8_EN 335
FWH_E8_IDSEL 339, 341
FWH_F0_EN 335
FW H _F0_I D S EL 339, 34 1
FWH_F8_EN 335
FWH_F8_I DSEL 339
G
GAMEH_LPC_EN 337
GAMEL_LPC_EN 337
GBL _STS 395
GBL_EN 396
GBL_RL S Gl obal Rel ease 397
GBL_SMI_EN 407
GEN1_BASE Generic I/O Decode Range 1 Base 336
GEN1_EN Generic Decode Range 1 Enable 336
GEN2_BASE Generic I/O Decode Range 2 Base 340
GEN2_EN Generi c I/O Decode Range 2 Enable 340
Global Reset (GRESET) 476
GO_CNT 523
GP_IO_SEL2 432
GP_LVL2 433
GPE0_STS 409
GPE1_STS 409
GPI Interrupt Enable (GIE) 574, 601
GPI Status Change Interrupt (GSCI) 577, 604
GPI0 Route 389
GPI 15 R out e 389
GPI n_EN 404
GPIn_STS 401
GPIO _SEL 426
GPIO11_ALERT_DISABLE 423
H
HC BIOS Owned Semaphore 4 99
HC OS Owned Semaphor e 499
HCHalt ed 478, 512
HCRESE 223
HIDE_ISA Hide ISA Bridge 327
Hos t Controll er P roc ess Error 478
Hos t Controller Reset 511
Hos t Cont roll er R eset (HCR ESET) 476
Host System Error 478, 513
Host System Error Enable. 514
HOST_BUSY 536
HOST_NOTIFY_INTREN 546
HOST_NOTIFY_STS 546
HOST_NOTIFY_WKEN 546
HOURFORM Hour Format 379
HST_EN SMBus Host Enable 533
HUBNMI_STS 419
HUBSCI _STS 419
HUBSERR_STS 419
HUBSMI_STS 419
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
840 Order Number: 300641-004US
I
I/ O APIC Id e ntif ic at i o n 3 72
I/ O Sp ace (IO S ) 583
I/O Space Enable (IOSE) 463, 528, 562
I2C 246, 249
I2C_EN 533
ICW/OCW select 361
ICW4 Write Required (IC4) 361
IDE De code Enable (IDE ) 448, 748
IDEP0_ACT_STS 413
IDEP0_TRP_EN 415
IDEP1_ACT_STS 413
IDEP1_TRP_EN 415
IDES0_ACT_STS 413
IDES0_TRP_EN 415
IDES1_ACT_STS 413
IDES1_TRP_EN 414
IN_USE_C N T 523
Index 760
INIT_NOW 382
INTEL_USB2_EN 405
INTEL_USB2_STS 408
Int errupt 458, 768
Interrupt Input Pin Polarity 374, 645
Interrupt Level Select (L2, L1, L0) 365
Int errupt Line 446, 747
Interrupt on Async Advance 512
Interrupt on Async Advance Do orbell 509
Interrupt on Async Advance Enable 514
Interrupt On Complete (IOC) Enable 480
Int errupt On Complet ion E nable ( IOC E) 572, 599
Int errupt Pi n 447, 748
Interrupt Request Level 362
Interrupt Request Mask 364
Int errupt Thr eshold C ontrol 509
Interrup t Vector B ase Address 3 62
INTR 536
INTR D_D ET In tr uder Det ect 421
INTR D _ S E L 423
INTREN 539
INUSE_STS 535
IOCHK_NMI_EN 381
IOCHK_NMI_STS IOCHK# NMI Source Status 381
IORDY Sample Point (ISP) 448, 748
IO SE I/O Space Enable (IOS E) 437, 740
IRQ Number 370, 642
IRQ Rou t in g 32 4
IRQ1_CAUSE 424
IRQ 10 ECL 368
IRQ 11 ECL 368
IRQ 12 ECL 367
IRQ12_CAUSE 424
IRQ 12LEN M ouse IRQ 12 Latch Enabl e 328
IRQ 14 ECL 367
IRQ 15 ECL 367
IRQ1LEN Keyb oar d IRQ1 Latch Enab le 328
IRQ3 ECL 367
IRQ4 ECL 367
IRQ5 ECL 367
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 841
—Intel® 6300ESB ICH
IRQ6 ECL 367
IRQ7 ECL 367
IRQ9 ECL 368
IRQ EN 324
IRQF Inter rupt Request Flag 380
Isochronous Scheduling Threshol d 507
K
KBC_ACT_STS 412
KBC_LPC_EN 337
KBC_TRP_EN 414
KILL 539
L
L128LO C K Low er 128-byte Lock 331
Last Codec Rea d Data Input (LDI) 579
Last Valid Buffer Completion Interrupt (LVBCI) 570, 597
Last Val id B uff er Int errupt Enable (LVBIE) 572, 600
Last Val id Index 569, 596
Latch Co unt of Sel ected Counters 357
Latch Stat us o f Sel ected Count ers 357
latency 728
LEG_ACT_STS 413
LEG_IO_TRP_EN 414
LEG_RT_ CAP 606
LEG_RT_ CNF 607
LEGACY_USB_EN 406
LEGACY_USB_STS 409
LEGACY_USB2_EN 405
LEGACY_USB2_STS 408
Light Host Controller Reset 509
Line St atus 484, 519
Lin k Poin ter Low 517
LINK_ID_STS 523
Loop Back Test Mode 474
Low Speed Dev ice Attached (LS) 48 3
LPT Decode Range 333
LPT_LPC_EN 338
M
MAS (Master-A bort Status) 58 4
Mask 374, 645
Master Clear 354
Master /Slave in Buff ered Mode 36 4
Master-Abort Status (M AS) 55 3
Max Packet (M A X P ) 474
Maximum Redirection Entries 372, 643
MC_LPC_EN 337
MCSMI_EN Microcontroller SMI Enable 406
MCSMI_STS Microcontroller SMI# Status 409
MD3 575, 603
Memor y Sp ace (MS) 55 2
Memory Space Enable (M SE) 437, 740
Mi c In In te rrupt (M IN T ) 576, 604
Microphone 2 In I nterrupt (M2INT) 575, 602
Mic roproc essor Mode 364
Intel® 6300 ESB ICH
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 842
MIDI Decode Range 334
MIDI _A CT _STS 412
MIDI_LPC_EN 337
MIDI_TRP_EN 414
MMT_ADDR_EN 328
MMT_ADDR_SEL 328
Mode Selection Status 359
Modem In Interrupt (M II N T ) 577, 604
Modem Out Interrupt (MOINT) 577, 604
MON_TRAP_BASE 391
MON4_FWD_EN 390
MON4_MASK 391
MON5_FWD_EN 390
MON5_MASK 391
MON6_FWD_EN 390
MON6_MASK 391
MON7_FWD_EN 390
MON7_MASK 391
MSS Decode Range 334
MSS_ LPC_EN 337
Mul ti -Func ti on Bit 466
N
GP_BLINK 429
GP_INV 430
GP_LVL 427
N_PORTS 506
NEWCENTURY_STS 420
Ne xt Cap abi lity (NEXT) 562
Next EHCI Capability Pointer 499
NMI_EN 382
NMI_NOW 422
NMI2SMI_EN 420, 422
NO_REBOOT 329
NUM_TIM_CAP 606
Number of Companion Controllers ( N_CC) 506
Number of Ports p er Com panion Controller (N _PCC) 506
O
OCW 2 Select 365
OCW 3 Select 366
Ov er-cur rent A ctive 52 1
Overcurrent Active 483
Over-current Change 520
Overcurrent Indicator 483
OWNER_CNT 522
P
Pass Throu gh St at e (PS TATE) 471
PCB0 75 5
PCB1 75 5
PCI Interrupt Enable (USBPIRQEN) 4 70
PCI_SERR_EN 381
PCM 4/6 Enable 573
PCM In 1, Micr ophone In 1 Data In Li ne (DI1L ) 578
PCM In 2 Interrupt ( P2INT) 575, 602
P CM In 2, Microphone In 2 D at a In Line
(DI2L) 578
P CM In Interrupt (PIINT) 577, 604
PCM Out In te rrupt (POINT) 57 7 , 6 04
PCM Out Mod e (POM) 573
PEC_DATA 542
PEC_EN 537
PE R_SM I_ SEL 385
Periodic List Execution 224
Periodic Schedule Enable 510
Periodic Schedule Status 512
PERIODIC_EN 406
PERIODIC_STS 40 8
PF Periodic Interrupt Flag 380
PIE Periodic Interrupt Enable 378
P IRQA E_A C T_STS 413
PIRQBF_ ACT_STS 41 3
P IRQC G_A C T_STS 413
PIRQDH_ACT_STS 412
PM1_STS_REG 409
P ME Cl ock 494
P ME Status (PMES) 56 3, 59 1
PME_B0_EN 404
PME_B0_STS 401
PME_EN 404, 494
PME_Statu s 494
PME_STS 402
PME_Support 493
Poll Mode Command 366
P OP_MODE_CAP 439, 742
P OP_MODE_SEL 439, 742
Port 0 BIST FI S Ini tiat e 764
Port 1 BIST FI S Ini tiat e 764
P ort Change D etect 513
P ort C hange Interr upt E nabl e 514
Port Enable/Disable Change 484, 521
P ort Enabled/Disabled 521
Port Enabled/Disabled (PORT_EN) 484
Port Owner 518
P ort Pow er (PP) 518
P ort R eset 483, 519
P ort Test Control 518
P ort Wa ke Im pleme nted 498
P ort Wa ke U p C apability Mas k 498
PORT0EN 472
PORT1EN 472
Port-Routing Logic 230
P osition In C urr ent Buffer 571, 597, 599
Power Management Event Enable (PMEE) 564, 59 2
Power Sequencing 811
P ower Stat e (PS) 564, 59 2
PowerState 495
PRBTNOR_STS Power Button Override Status 394
Prefetched Index Value 571
P ri m any R esume I nterr upt Enable 573, 600
Primary Codec Ready (PCR) 576, 603
P ri m ary Drive 0 Cycle Ti me (PC T0) 454, 753
P ri m ary Drive 0 Synchronou s DMA Mode Enable (PSDE0)
452, 751
P ri m ary Drive 1 Cycle Ti me (PC T1) 454, 753
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 843
—Intel® 6300ESB ICH
Primary Drive 1 IORD Y Sam pl e Point (PISP1) 451, 750
Primary Drive 1 Recovery Time (PRCT1) 451, 750
Primar y D ri ve 1 Synchronous DMA Mode Enable (PSDE1 ) 452, 751
Primary Resume In te rr upt 576, 603
programm able baud rate gene rator 722
Programmable F rame List F la g 507
PRQ 372, 643
PWR_FLR Power Fail ure 387
PWRBTN__STS 395
PWRBTN_EN 396
PWRBTN_LVL 38 5
PWROK_FLR PWROK Failur e 386
R
Rea d / Wri te Con tr ol (RWC) 456, 767
Rea d B ack Co mmand 357
Read Completion Status 576, 603
Read Policies for Periodic DMA 224
Read/Write Select 356
Re ad/Wri te Se le ct io n S ta tu s 359
Rec ei ved Master- A bort St atus (RMA 464
Received Master-Abort Status (RM A) 438, 741
RECEI V ED_PID_STS 525
receiver interrupts 723
Recl amat i o n 512
Recovery Time (RCT) 449, 749
Red ir ection Entry Clear 371, 642
REF_TOGGLE Refresh Cycle Toggle 381
Register Read Command 366
Remote IRR 374, 645
Reset Registers(RR) 600
Reset Registers(RR). 572
Resource Type Indicator (RTE) 441, 442, 443, 556, 557, 558, 587, 588, 744, 745, 746
Resume Detect (RSM_DET 4 84
Resume Detect (RSM_D ET) 479
Res um e Inte rrupt Enable 480
RI_EN 404
RI_STS 402
Rotat e and EOI C odes (R, S L, EOI) 365
RS Rate Select 377
RST_CPU 383
RTC_EN RTC Event Enable 396
RTC_INDX Real Time Clock Index Address 382
RTC_PWR_STS 387
RTC_STS 395
Run/Pause Bus master (RPBM) 572, 600
Run/Stop (RS) 476, 51 1
RW 539
S
S/PDIF Interrupt (SPINT) 575, 602
SAFE_ MODE 329
Sample Capabilities 575, 602
SATA Set up D at a A 762
SATA Set up D at a B 762
SB16 Decode Range 334
SB16_LPC_EN 338
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
844 Order Number: 300641-004US
SCB1 75 4
SCBO 755
SCI_EN 397
SECOND_TO_STS 421
Se condary Codec ID (SC ID ) 56 1
Secondary Code c R eady (SC R) 576, 603
Secondary Drive 0 Cycle Time (SCT0) 453, 752
Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) 452, 751
Secondary Drive 1 Cycle Time (SCT1) 453, 752
Secondary Drive 1 IOR D Y Sam ple Point ( SISP1) 451, 750
Secondary Drive 1 Recovery Tim e (S R C T1) 451, 750
Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) 452, 751
Secondary Res um e Interr upt 576, 603
Secondary Res um e Interr upt E nabl e 573, 600
Secondary Slave Channel Cabl e Reporting 754
SEND _P ID _C N T 525
SENDNOW 422
SERIRQ_SMI_STS 408
SE RR #_N M I_STS SERR# NMI Sou rce Status 381
SE T Up dat e C ycle Inhibit 378
Short Packet Interrupt Enable 479
Signaled Target -Abort Stat us 529
Signaled Target -Abort Stat us (STA) 438 , 464, 741
Singl e or Cascade (SNGL) 361
Slave Identification Code 363
SLAVE_ADDR 542
SL P_EN 397
SLP_SMI_EN 406
SL P_SM I_ STS 409
SL P_TYP 397
SMB_CMD 538
SMB_FOR_BIOS 344
SMB_SMI _EN 533
SMB_W AK _STS S MBu s Wake St at us 402
SMBALERT_ DIS 54 6
SMBALERT_STS 535
SMBCLK_CTL 545
SMBCLK_CUR_STS 545
SMBDATA _CUR_STS 545
SMBus SMI Status (SMBUS_SMI _STS) 408
SMI at End of Pass- thr ough Enable (SM IATENDPS) 471
SMI Caused by End of Pass- thr ough (SMIBYEN D PS) 470
SMI Ca used by Port 60 Read (T R A PB Y60R ) 471
SMI Caused by Port 60 Writ e (TRA PB Y 60W) 471
SMI Ca used by Port 64 Read (T R A PB Y64R ) 470
SMI Caused by Port 64 Writ e (TRA PB Y 64W) 470
SMI Ca used by USB Interrupt (SM IBY U SB ) 470
SM I on Asyn c 50 1
SMI on Async Advance 500
SMI on Async Advance Enable 500
SMI on Async Enable 502
SMI on BA R 500
SMI on BA R Enable 500
SM I on CF 502
SMI on CF Enable 502
SM I on Fr ame List Ro l lover 50 0
SM I on Fram e List Rol lover Enabl e 501
SMI on HCHalted 502
SMI on HCHalted Enable 502
SMI on HCReset 502
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 845
—Intel® 6300ESB ICH
SMI on HCReset Enable 502
SMI on Host Sys tem Err or 50 0
SMI on Host System E rr or Ena ble 501
SMI on OS Own e rship Change 500
SMI on OS Ownership Enable 500
SMI on PCI Com m and 500
SMI on PCI Com m and Enable 500
SMI on Peri odi c 502
SMI on Peri odi c Enable 502
SMI on PMCSR 501
SMI on PMSCR Ena bl e 502
SMI on Port 60 Reads Enable (60REN) 472
SMI on Port 60 Writ es Enabl e (60WEN) 472
SMI on Port 64 Reads Enable (64REN) 472
SMI on Port 64 Writ es Enabl e (64WEN) 471
SMI on Port Change Detect 500
SMI on Por t Change Enabl e 501
SMI on PortOwner 501
SMI on PortOwner Enable 502
SMI on USB Com pl et e 500
SMI on USB Complete Enable 501
SMI on USB Error 500
SM I o n US B Error En able 50 1
SM I o n US B IRQ Enable (USBSMI E N) 471
SMLINK_CLK_CTL 544
SMLINK_SLV_SMI_STS— R/W . SMLink Slav e SM I Statu s 421
SMLINK0_CUR_STS 544
SMLINK1_CUR_STS 544
SOF Timing Value 482
So ftwar e Deb u g (S WDBG) 4 74
SOP_MODE_CAP 439, 742
SOP_MODE_SEL 439, 742
Sp ec ia l F ul ly Ne st ed Mo de (S FNM ) 36 4
Special Mask Mode (SMM) 3 66
SPKR_DAT_EN 381
SQWE Square Wave Enable 378
START 537
Star t/ Stop Bus Maste r (START) 456, 767
Steer Enabl e (SE) 579
STPCLK_DE 388
Sub Class Code 440, 742
Subsyst em ID (SID) 446, 747
Subsystem Vendor ID (SV I D ) 445, 746
Suspend 483
SW_TCO_SMI 420
SWSM I_RAT E _SEL 387
SWSMI_TMR_ EN Softw ar e SM I# Timer Enabl e 406
SWSMI_TMR_STS 409
SYS_RST 383
System Reset Statu s (SRS ) 386
T
T00_INT_STS 608
T01_INT_STS 608
T02_INT_STS 608
TCO_EN 406
TCO_INT_STS 420
TCO_MESSAGE 423
TCO_STS 408
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
846 Order Number: 300641-004US
TCO_TMR_HLT TCO Timer Halt 422
TCOSCI_EN 404
TCOSCI_STS 402
Ter tiar y Cod e c ID (T ID 561
Tertiary Codec Ready (TCR) 575, 602
Tertiary Resume Interrupt (TRI) 575, 602
Ter tiar y Res u m e In te rrupt En ab le (TRE ) 57 3 , 6 0 0
THRM#_POL 405
THRM_DTY 39 9
THRM_EN 405
THRM_STS Thermal Interrupt Status 403
THRMOR_STS Thermal Interrupt Override Status 403
THT_EN 39 9
THTL_DTY 399
THTL _STS Thr ot tl e St at us 39 8
TIM_CNT2_EN Timer Counter 2 Enable 381
TIMEOUT 42 0
Timeout/CRC Interrupt Enable 480
TIMERn_32MODE_CNF 611
TIMERn_INT_ENB_CNF 61 2
TIMERn_INT_ROUT_CAP 610
TIMERn_INT_ROUT_CNF 611
TIMERn_INT_TYPE_ CN 612
TIMERn_PER_I NT_CAP 611
TIMERn_SIZE_CAP 611
TIM ER n_TYPE_CNF 612
TIME Rn_VAL_SET_CNF 61 1
TMR_VAL 398
TMR2_OUT_STS Timer Counter 2 OUT St atu s 381
TMR OF _E N T im e r O ve r flo w In terrup t En ab le 39 6
TMROF_STS Timer Over flow St at us 395
TOKEN_PID_CNT 525
TOP_SWAP 33 0
Trig ger Mode 374, 645
U
U12 8E U pper 128-byte Enable 331
U12 8LO CK U pper 128-byte Lock 331
UF Update -ended Flag 380
UHCI v/s EHCI 221
UI E Update-ended I nte rrupt Enable 378
UI P U pdat e In P rogress 377
USB Error Interrupt 479, 513
USB Error Interrupt Enable 514
USB Interr upt 513
USB I nte rr upt (USB I N T) 479
US B Interrupt E n able 5 1 4
USB_ADDRESS_CNF
526
USB_ENDPOINT_CNF 526
USB1_EN 405
USB1_STS 40 3
USB2.0 Con t roller (D29
F7) 221
USB2_EN 405
USB2_STS 40 3
Intel® 63 00ESB I/O Controller Hub
No v ember 20 07 DS
Order Nu mber: 30 06 41-00 4U S 847
—Intel® 6300ESB ICH
V
Vector 374
Vendor ID Value 527
VENDOR_ID_CAP 606
VRT Val id RAM and Ti m e Bit 380
W
WAK_ STS 394
WDSTATUS W atchdog Status 424
Write Policies for Periodic DMA 225
WRITE_ R EA D #_CN T 524
WRT_RDONLY 503
Intel® 6300ESB ICH—
Intel® 6300ESB I/O Controller Hub
DS November 2007
848 Order Number: 300641-004US