APW7120KE-TRL - Anpec Electronics Corp.

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise

customers to obtain the latest version of relevant information to verify before placing orders.

5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller

•Operating with Single 5~12V Supply Voltage

or Two Supply Voltages

•Drive Dual Low Cost N-Channel MOSFETs

- Adaptive Shoot-Through Protection

•Built-in Feedback Compensation

- Voltage-Mode PWM Control

- 0~100% Duty Ratio

- Fast Transient Response

•±2% 0.8V Reference

- Over Line, Load Regulation, and Operating

Temperature

•Programmable Over-Current Protection

- Using RDS(ON) of Low-Side MOSFET

•Hiccup-Mode Under-Voltage Protection

•118% Over-Voltage Protection

•Adjustable Output Voltage

•Small Converter Size

- 300kHz Constant Switching Frequency

- Small SOP-8 Package

•Built-In Digital Soft-Start

•Shutdown Control Using an External MOSFET

•Lead Free and Green Devices Available

(RoHS Compliant)

Features

Applications

General Description

The APW7120 is a fixed 300kHz frequency, voltage

mode, and synchronous PWM controller. The device

drives two low cost N-channel MOSFETs and is de-

signed to work with single 5~12V or two supply

voltage(s), providing excellent regulation for load

transients.

The APW7120 integrates controls, monitoring, and

protection functions into a single 8-pin package to

provide a low cost and perfect power solution.

A power-on-reset (POR) circuit monitors the VCC

supply voltage to prevent wrong logic controls. An

internal 0.8V reference provides low output voltage

down to 0.8V for further applications. An built-in digital

soft-start with fixed soft-start interval prevents the

output voltage from overshoot as well as limits the

input current. The controller’s over-current protection

monitors the output current by using the voltage drop

across the low-side MOSFET’s RDS(ON), eliminating the

need of a current sensing resistor. Additional under

voltage and over voltage protections monitor the

voltage on FB pin for short-circuit and over-voltage

protections. The over-current protection cycles the

soft-start function until 4 over-current events are

counted.

Pulling and holding the voltage on OCSET pin below

0.15V with an open drain device shuts down the

controller.

Pin Configuration

PHASE

OCSET

VCC

BOOT

UGATE

GND

LGATE

SOP-8

•Motherboard

•Graphics Card

•High Current, up to 20A, DC-DC Converters

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw2

Ordering and Marking Information

APW7120

Handling Code

Temperature Range

Package Code

K : SOP-8

Operating Ambient Temperature Range

E : -20 to 70 C

Handling Code

TR : Tape & Reel

Assembly Material

L : Lead Free Device

G : Halogen and Lead Free Device

APW7120 K : APW7120

XXXXX XXXXX - Date Code

Assembly Material °

Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;

which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-

020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and

halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed

1500ppm by weight).

Symbol Parameter Rating Unit

VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V

VBOOT BOOT Voltage (BOOT to PHASE) -0.3 ~ 16 V

UGATE Voltage (UGATE to PHASE)

<400ns pulse width

>400ns pulse width

-5 ~ VBOOT+0.3

-0.3 ~ VBOOT+0.3

LGATE Voltage (LGATE to GND)

<400ns pulse width

>400ns pulse width

-5 ~ VCC+0.3

-0.3 ~ VCC+0.3 V

PHASE Voltage (PHASE to GND)

<400ns pulse width

>400ns pulse width

-10 ~ 30

-3 ~ 16 V

VI/O Input Voltage (OCSET, FB to GND) -0.3 ~ 7 V

Maximum Junction Temperature 150 oC

TSTG Storage Temperature -65 ~ 150 oC

TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings (Note 1)

Symbol Parameter Typical Value Unit

θJA Junction-to-Ambient Resistance in free air (Note 2) 160 oC/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Thermal Characteristics

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw3

Symbol Parameter Range Unit

VCC VCC Supply Voltage 4.5 ~ 13.2 V

OUT Converter Output Voltage 0.8 ~ 80%VIN V

VIN Converter Input Voltage 2.2 ~ 13.2 V

IOUT Converter Output Current 0 ~ 20 A

TA Ambient Temperature -20 ~ 70 oC

TJ Junction Temperature -20 ~ 125 oC

Note 3: Please refer to the typical application circuit.

Recommended Operating Conditions (Note 3)

Electrical Characteristics

Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC.

Typical values are at TA = 25oC.

APW7120

Symbol

Parameter Test Conditions Min.

Typ.

Max.

Unit

SUPPLY CURRENT

IVCC VCC Nominal Supply Current UGATE and LGATE Open - 2.1

6 mA

VCC Shutdown Supply Current - 1.5

4 mA

POWER-ON-RESET

Rising VCC Threshold 3.8

4.1

4.4

Hysteresis 0.1

0.45

0.6

OSCILLATOR

FOSC Free Running Frequency 250

300

350

kHz

∆VOSC

Ramp Amplitude - 1.5

- V

P-P

REFERENCE VOLTAGE

VREF Reference Voltage Measured at FB Pin - 0.8

- V

TA =25°C -0.75

- +0.75

Accuracy TA =-20~70°C, VCC=5V ~ 12V

-1.5

- +1.5

Line Regulation V

CC=5V ~ 12V - 0.05

+0.3

ERROR AMPLIFIER

DC Gain - 86 - dB

FP1 First Pole Frequency - 0.4

- Hz

FZ Zero Frequency - 0.4

- kHz

FP2 Second Pole Frequency - 430

- kHz

Average UGATE Duty Range 0 - 85 %

FB Input Current - - 0.1

µA

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw4

APW7120

Symbol

Parameter Test Conditions Min.

Typ.

Max.

Unit

PWM CONTROLLER GATE DRIVERS

UGATE Source V

BOOT-PHASE =12V, VUGATE-PHASE =6V

1.0

2.0 - A

UGATE Sink VBOOT-PHASE =12V, VUGATE-PHASE=1V - 3.5 7 Ω

LGATE Source VCC=12V, VLGATE=6V 1.0

1.9 - A

LGATE Sink V

CC=12V, VLGATE=1V - 2.6 5 Ω

TD Dead-Time Guaranteed by Design - 40 100

PROTECTIONS

IOCSET

OCSET Current Source V

PHASE=0V, Normal Operation 35 40 45 µA

Over-Current Reference

Voltage

TA =-20~70°C 0.37

0.4 0.43

UVFB FB Under-Voltage Threshold VFB Falling 62 67 72 %

FB Under-Voltage Hysteresis - 45 - mV

Over-Voltage Threshold VFB Rising 114

118

122

SOFT-START AND SHUTDOWN

TSS Soft-Start Interval 2 3.8 5 ms

OCSET Shutdown Threshold Falling VOCSET 0.1

0.15

0.3 V

OCSET Shutdown Hysteresis - 40 - mV

Electrical Characteristics (Cont.)

Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC.

Typical values are at TA = 25oC.

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw5

Function Pin Description

BOOT (Pin 1)

This pin provides ground referenced bias voltage to

the high-side MOSFET driver. A bootstrap circuit with

a diode connected to 5~12V is used to create a

voltage suitable to drive a logic-level N-channel

MOSFET.

UGATE (Pin 2)

Connect this pin to the high-side N-channel MOSFET’s

gate. This pin provides gate drive for the high-side

MOSFET.

GND (Pin 3)

The GND terminal provides return path for the IC’s bias

current and the low-side MOSFET driver’s pull-low

current. Connect the pin to the system ground via very

low impedance layout on PCBs.

LGATE (Pin 4)

Connect this pin to the low-side N-channel MOSFET’s

gate. This pin provides gate drive for the low-side

MOSFET.

VCC (Pin 5)

Connect this pin to a 5~12V supply voltage. This pin

provides bias supply for the control circuitry and the

low-side MOSFET driver. The voltage at this pin is

monitored for the Power-On-Reset (POR) purpose.

FB (Pin 6)

This pin is the inverting input of the internal Gm amplifier.

Connect this pin to the output (VOUT) of the converter

via an external resistor divider for closed-loop operation.

The output voltage set by the resistor divider is deter-

mined using the following formula :

where R1 is the resistor connected from VOUT to FB ,

and R2 is the resistor connected from FB to GND. The

FB pin is also monitored for under and over-voltage

events.

OCSET (Pin 7)

The OCSET is a dual-function input pin for over-

current protection and shutdown control. Connect a

resistor (ROCSET) from this pin to the Drain of the low-

side MOSFET. This resistor, an internal 40µA current

source (IOCSET), and the MOSFET’s on-resistance

(RDSON) set the converter over-current trip level (IPEAK)

according to the following formula:

Pulling and holding this pin below 0.15V with an open

drain device, with very low parasitic capacitor, shuts

down the IC with floating output and also resets the

over-current counter. Releasing OCSET pin initiates a

new soft-start and the converter works again.

PHASE (Pin 8)

The pin provides return path for the high-side MOSFET

driver’s pull-low current. Connect this pin to the high-

side MOSFET’s source.

(V) )

1 (0.8VVOUT +⋅=

(A)

R0.4V-RA40

I DSON

OCSET

PEAK ⋅

=μ

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw6

Block Diagram

VCC

Power-On-

Reset

VCC

OCSET

UGATE

LGATE

Oscillator

Gate

Control

VREF

0.8V

Soft-Start

and Fault

Logic

FOSC

300kHz

PHASE

Amplifier

FB PWM

Inhibit

40uA

COMP

67%VREF UV

GND

POR

Soft-Start

BOOT

Regulator

3VCC

118%VREF

3VCC

0.4V

0.15V

Enable

2.5V

Application Circuit

C3, C4 : 820µF/16V , ESR=25 mΩ

C6, C7 : 1000µF/6.3V, ESR=30 mΩ

VIN

+5/12V

VOUT

1.8V/15A

1uF C3, C4

820uF x2

C6, C7

1000uF x2

1.5uH

APM2512

UGATE

LGATE 4

BOOT

GND

VCC

5PHASE 8

APM2512

1uF

APW7120

OCSET 7

1.2k

0.1uF

2N7002

Shutdown

2.2

1uH

+5V/12V

0.1uF

1.5k

200

1N4148

VBIAS

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw7

-50-250255075100125150 3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

-50-250255075100125150

250

260

270

280

290

300

310

320

330

340

350

-50-250255075100125150

0.788

0.790

0.792

0.794

0.796

0.798

0.800

0.802

0.804

0.806

0.808

0.810

0.812

-50-250255075100125150

Typical Operating Characteristics

Junction Temperature (oC)

Reference Voltage vs Junction Temperature

Reference Voltage, VREF (V)

Switching Frequency vs Junction Temperature

Junction Temperature (oC)

Switching Frequency, FOSC (kHz)

OCSET Current vs Junction TemperatureVCC POR Threshold Voltage vs Junction Temperature

Junction Temperature (oC)

OCSET Current , IOCSET (µA)

Junction Temperature (oC)

VCC POR Threshold Voltage (V)

Rising VCCRising VCC

Falling VCCFalling VCC

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw8

0.10

0.12

0.14

0.16

0.18

0.20

-50-250255075100125150

Typical Operating Characteristics (Cont.)

Junction Temperature (oC)

OCSET Shutdown Threshold Voltage

vs Junction Temperature

OCSET Shutdown Threshold Voltage (V)

Operating Waveforms

(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply)

1. Load Transient Response : IOUT = 0A -> 15A -> 0A

- IOUT slew rate = ±15A/µs

Ch1 : VOUT, 100mV/Div, DC,

Offset = 1.8V

Ch2 : IOUT, 10A/Div

Ch3 : VUGATE, 20V/Div, DC

Time : 2µs/Div

BW = 20 MHz

Ch1 : VOUT, 100mV/Div, DC,

Offset = 1.8V

Ch2 : IOUT, 10A/Div

Ch3 : VUGATE, 20V/Div, DC

Time : 50µs/Div

BW = 20 MHz

Ch1 : VOUT, 100mV/Div, DC,

Offset = 1.8V

Ch2 : IOUT, 10A/Div

Ch3 : VUGATE, 20V/Div, DC

Time : 2µs/Div

BW = 20 MHz

IOUT = 0A -> 15AI

OUT = 0A -> 15A -> 0AI

OUT = 15A -> 0A

Falling VOCSETFalling V OCSET

VOUT

VUGATE

IOUT

OUT

=1.8V

VOUT

VUGATE

OUT

15A15A

0A0A

OUT

VUGATE

IOUT

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw9

Operating Waveforms (Cont.)

2. UGATE and LGATE Switching Waveforms

Rising VUGATE

Ch1 : VUGATE, 5V/Div, DC

Time : 20ns/Div Ch2 : VLGATE, 2V/Div, DC

BW = 500 MHz

Falling VUGATE

Ch1 : VUGATE, 5V/Div, DC

Time : 20ns/Div Ch2 : VLGATE, 2V/Div, DC

BW = 500 MHz

3. Powering ON / OFF

Powering ON Powering OFF

Ch1 : VCC, 2V/Div, DC

Ch3 : IL, 10A/Div, DC

BW = 20 MHz

Ch2 : VOUT, 1V/Div, DC

Time : 10ms/Div

VUGATE

1,21,2

IOUT = 15A

VLGATE

1,21,2

VUGATE

VLGATE

VCC

VOUT

VCC

VOUT

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

VCC=VIN=5V

RL=0.12

Ω

VCC=VIN=5V

RL=0.12

Ω

Ch1 : VCC, 2V/Div, DC

Ch3 : IL, 10A/Div, DC

BW = 20 MHz

Ch2 : VOUT, 1V/Div, DC

Time : 5ms/Div

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw10

3. Powering ON / OFF (Cont.)

Powering ON Powering OFF

VCC

VOUT

VCC

VOUT

Operating Waveforms (Cont.)

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

VCC=VIN=12V

RL=0.12

Ω

4. Enabling and Shutting Down

Enabling by Releasing OCSET Pin

Ch1 : VOUT, 1V/Div, DC

Ch3 : VOCSET, 2V/Div, DC

BW = 20 MHz

Ch2 : VUGATE, 20V/Div, DC

Time : 2ms/Div

Shutting Down by Pulling OCSET Low

Ch1 : VOUT, 1V/Div, DC

Ch3 : VOCSET, 2V/Div, DC

BW = 20 MHz

Ch2 : VUGATE, 20V/Div, DC

Time : 2ms/Div

VOUT

VUGATE

VOCSET

IOUT=2A

VOUT

VUGATE

VOCSET

VCC=VIN=12V

RL=0.12

Ω

Ch1 : VCC, 5V/Div, DC

Ch3 : IL, 10A/Div, DC

BW = 20 MHz

Ch2 : VOUT, 1V/Div, DC

Time : 5ms/Div Ch1 : VCC, 5V/Div, DC

Ch3 : IL, 10A/Div, DC

BW = 20 MHz

Ch2 : VOUT, 1V/Div, DC

Time : 10ms/Div

Rev. A.5 - Jun., 2008

APW7120

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Operating Waveforms (Cont.)

5. Over-Current Protection

No Connecting a shutdown MOSFET

at OCSET Pin

Ch1 : VOUT, 1V/Div, DC

Time : 5ms/Div Ch2 : IL, 10A/Div, DC

BW = 20 MHz

Connecting a shutdown MOSFET

(2N7002) at OCSET Pin

Ch1 : VOUT, 1V/Div, DC

Time : 5ms/Div Ch2 : IL, 10A/Div, DC

BW = 20 MHz

VOUT

ROCSET=15k

APM2512 ROCSET=15k

APM2512

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

6. OCSET Voltage RC Delay

Ch1 : VOCSET, 0.5V/Div, DC

Time : 2µS/Div

Ch2 : IL, 10A/Div, DC

BW = 20 MHz Ch1 : VOCSET, 0.5V/Div, DC

Time : 2µ S/Div

Ch2 : IL, 10A/Div, DC

BW = 20 MHz

VOCSET

CProber=8pF OCPOCP

1,21,2

OCPOCP

1,21,2

VOCSET

No Connecting a shutdown MOSFET

at OCSET Pin Connecting a shutdown MOSFET

(2N7002) at OCSET Pin

CProber=8pF

C2N7002=44pF (measured)

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw12

Operating Waveforms (Cont.)

7. Short-Circuit Test

Ch1 : VOUT, 1V/Div, DC

Time : 5ms/Div Ch2 : IL, 10A/Div, DC

BW = 20 MHz

VOUT

UVP

OCP OCP OCP OCP

Shorted by a wire

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

6. OCSET Voltage RC Delay (Cont.)

Ch1 : VOCSET, 0.5V/Div, DC

Time : 2µS/Div

Ch2 : IL, 10A/Div, DC

BW = 20 MHz

VOCSET OCPOCP

1,21,2

Connecting a shutdown MOSFET

(APM2322) at OCSET Pin

CProber=8pF

CAPM2322=89pF (measured)

Function Description

Power-On-Reset (POR)

The APW7120 monitors the VCC voltage (VCC) for

Power-On-Reset function, preventing wrong logic

operation during powering on. When the VCC voltage

is ready, the APW7120 starts a start-up process and

then ramps the output voltage up to the target voltage.

Soft-Start

The APW7120 has a built-in digital soft-start to control

the output voltage rise and limit the current surge at

the start-up. During the soft-start, an internal ramp con-

nected to the one of the positive inputs of the Gm

amplifier rises up from 0V to 2V to replace the reference

voltage (0.8V) until the ramp voltage reaches the refer-

ence voltage. The soft-start interval is about 3.2ms

typical, independent of the converter’s input and out-

put voltages.

Over-Current Protection (OCP)

The over-current function protects the switching

converter against over-current or short-circuit

conditions. The controller senses the inductor current

by detecting the drain-to-source voltage, product of

the inductor’s current and the on-resistance, of the

low-side MOSFET during it’s on-state. This method

enhances the converter’s efficiency and reduces cost

by eliminating a current sensing resistor.

A resistor (ROCSET), connected from the OCSET to the

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw13

low-side MOSFET’s drain, programs the over-current

trip level. An internal 40 µA (typical) current source

flowing through the ROCSET develops a voltage (VROCSET)

across the ROCSET. When the VOCSET (VROCSET+ VDS of

the low-side MOSFET) is less than the internal over-

current reference voltage (0.4V, typical), the IC shuts

off the converter and then initiates a new soft-start

process. After 4 over-current events are counted, the

device turns off both high-side and low-side MOSFETs

and the converter’s output is latched to be floating.

Please pay attention to the RC delay effect. It causes

the OCP trip level to be the function of the

operating duty. The parasitic capacitance, includ-

ing the capacitance inside the OCSET, external PCB

trace capacitance, and the COSS of the shutdown

MOSFET, must be minimized, especially selecting a

shutdown MOSFET with very small COSS. The OCP

trip level follows the duty to increase a little at low

operating duty, but very much at high operating duty,

like the RC delay curve. Due to load regulation or

current-limit, heavy load normally reduces converter’s

input voltage and increases the power loses. During

heavy load, the APW7120 regulates the output voltage

by expending the duty. This rises up the OCP trip level

at the same time.

Under-Voltage Protection (UVP)

The under-voltage function monitors the FB voltage

(VFB) to protect the converter against short-circuit

conditions. When the VFB falls below the falling UVP

threshold (67% VREF), the APW7120 shuts off the

converter. After a preceding delay, which starts at

the beginning of the under-voltage shutdown, the

APW7120 initiates a new soft-start to resume

regulating. The under-voltage protection shuts off

and then re-starts the converter repeatedly without

Function Description (Cont.)

Over-Current Protection (OCP) (Cont.) latching. The function is disabled during soft-start

process.

Over-Voltage Protection (OVP)

The over-voltage protection monitors the FB voltage to

prevent the output from over-voltage. When the

output voltage rises to 118% of the nominal output

voltage, the APW7120 turns on the low-side MOSFET

until the output voltage falls below the OVP

threshold, regulating the output voltage around the

OVP thresholds.

Adaptive Shoot-Through Protection

The gate driver incorporates adaptive shoot-through

protection to high-side and low-side MOSFETs from

conducting simultaneously and shorting the input

supply. This is accomplished by ensuring the falling

gate has turned off one MOSFET before the other is

allowed to rise.

During turn-off of the low-side MOSFET, the LGATE

voltage is monitored until it reaches a 1.5V threshold,

at which time the UGATE is released to rise after a

constant delay. During turn-off of the high-side

MOSFET, the UGATE-to-PHASE voltage is also

monitored until it reaches a 1.5V threshold, at which

time the LGATE is released to rise after a constant

delay.

Shutdown Control

Pulling the OCSET voltage below 0.15V by an open

drain transistor, shown in typical application circuit,

shuts down the APW7120 PWM controller. In shut-

down mode, the UGATE and LGATE are pulled to

PHASE and GND respectively, the output is floating.

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw14

Application Information

Input Capacitor Selection

Use small ceramic capacitors for high frequency

decoupling and bulk capacitors to supply the surge

current needed each time high-side MOSFET(Q1) turns

on. Place the small ceramic capacitors physically close

to the MOSFETs and between the drain of Q1 and the

source of low-side MOSFET(Q2).

The important parameters for the bulk input capacitor

are the voltage rating and the RMS current rating. For

reliable operation, select the bulk capacitor with voltage

and current ratings above the maximum input voltage

and largest RMS current required by the circuit. The

capacitor voltage rating should be at least 1.25 times

greater than the maximum input voltage and a voltage

rating of 1.5 times is a conservative guideline. The

RMS current of the bulk input capacitor is calculated

as the following equation :

(A) D)-(1DI I OUTRMS ⋅⋅=

For a through hole design, several electrolytic capacitors

may be needed. For surface mount designs, solid

tantalum capacitors can be used, but caution must

be exercised with regard to the capacitor surge current

rating.

VIN

VOUT

CIN

COUT

UGATE

LGATE

ESR

ILIOUT

IQ1

ICOUT

IOUT

VUGATE

T=1/FOSC

IQ1

ICOUT

IOUT

VOUT

Figure 1 Buck Converter Waveforms

Output Capacitor Selection

An output capacitor is required to filter the output and

supply the load transient current. The filtering requirements

are the functions of the switching frequency and the

ripple current. The output ripple is the sum of the

voltages, having phase shift, across the ESR and the

ideal output capacitor. The peak-to-peak voltage of

the ESR is calculated as the following equations :

The peak-to-peak voltage of the ideal output capacitor

is calculated as the following equation :

..(3).......... (V) ESRI V

.(2).......... (A)

LF D)-(1V

(1) ........... (V) VDV

ESR

OSC

OUT

INOUT

⋅∆= ⋅

⋅

=∆

⋅

(4) ....... (V)

CF8 I

VOUTOSC

COUT ⋅⋅ ∆

=∆

For general applications using bulk capacitors, the

∆VCOUT is much smaller than the VESR and can be

ignored. Therefore, the AC peak-to-peak output volt-

age is shown below:

The load transient requirements are the functions of

.(5).......... (V) ESRI VOUT

⋅

∆

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw15

the slew rate (di/dt) and the magnitude of the transient

load current. These requirements are generally met

with a mix of capacitors and careful layout. Modern

components and loads are capable of producing

transient load rates above 1A/ns. High frequency

capacitors initially supply the transient and slow the

current load rate seen by the bulk capacitors. The bulk

filter capacitor values are generally determined by the

ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance

requirements.

High frequency decoupling capacitors should be placed

as close to the power pins of the load as physically

possible. Be careful not to add inductance in the

circuit board wiring that could cancel the usefulness

of these low inductance components.

An aluminum electrolytic capacitor’s ESR value is re-

lated to the case size with lower ESR available in

larger case sizes. However, the Equivalent Series

Inductance (ESL) of these capacitors increases with

case size and can reduce the usefulness of the

capacitor to high slew-rate transient loading. In most

cases, multiple electrolytic capacitors of small case

size perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output

voltage ripple requirements and minimize the

converter’s response time to the load transient. The

inductor value determines the converter’s ripple

current and the ripple voltage, see equations (2) and

(5). Increasing the value of inductance reduces the

ripple current and voltage. However, the large inductance

values reduce the converter’s response time to a load

transient.

One of the parameters limiting the converter’s response

Application Information (Cont.)

Output Capacitor Selection (Cont.)

where: ITRAN is the transient load current step, tRISE is

the response time to the application of load, and tFALL

is the response time to the removal of load. The worst

case response time can be either at the application or

removal of load. Be sure to check both of these

equations at the transient load current. These requirements

are minimum and maximum output levels for the worst

case response time.

MOSFET Selection

The APW7120 requires two N-Channel power

MOSFETs. These should be selected based upon

RDS(ON), gate supply requirements, and thermal

management requirements.

In high-current applications, the MOSFET power

dissipation, package selection, and heatsink are the

dominant design factors. The power dissipation includes

two loss components, conduction loss, and switching

loss. The conduction losses are the largest component

of power dissipation for both the high-side and the

VIL

t ,

VV IL

tOUT

TRAN

FALL

OUTIN

TRAN

RISE ⋅

−

⋅

to a load transient is the time required to change the

inductor current. Given a sufficiently fast control loop

design, the APW7120 will provide either 0% or 85%

(Average) duty cycle in response to a load transient.

The response time is the time required to slew the

inductor current from an initial current value to the

transient current level. During this interval, the difference

between the inductor current and the transient current

level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The response time to a transient is different for the

application of load and the removal of load. The fol-

lowing equations give the approximate response time

interval for application and removal of a transient load:

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw16

low-side MOSFETs. These losses are distributed

between the two MOSFETs according to duty factor

(see the equations below). Only the high-side MOSFET

has switching losses, since the low-side MOSFETs

body diode or an external Schottky rectifier across

the lower MOSFET clamps the switching node before

the synchronous rectifier turns on. These equations

assume linear voltage-current transitions and do not

adequately model power loss due the reverse-recovery

of the low-side MOSFET’s body diode. The gate-

charge losses are dissipated by the APW7120 and

don’t heat the MOSFETs. However, large gate-charge

increases the switching interval, tSW which increases

the high-side MOSFET switching losses. Ensure that

both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating

the temperature rise according to package thermal-

resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power,

package type, ambient temperature, and air flow.

Where : tSW is the switching interval

Application Information (Cont.)

MOSFET Selection (Cont.)

D)-(1RIP

FtVI

DRIP

DSON

OUTSide-Low

OSCSWINOUTDSON

OUTSide-High

⋅⋅=

⋅⋅⋅⋅+⋅⋅=

Feedback Compensation

The figure 2 shows the control system of the

APW7120, which consists of an internal voltage-mode

PWM modulator, an output L-C filter, a resistor-divider

and an internal compensation network. The R and C

are the equivalent series resistance(ESR) and capaci-

tance of the output capacitor; the L is the inductance

of the output inductor.

VOUT

APW7120

VFB

0.8V

VOSC=1.6V

Driver

VPHASE

VIN

VCOMP

Internal

Compensation

Network

UGATE

LGATE

Figure 2. APW7120 Control System

The transfer functions are defined as following :

R2R1

(S)V (S)V

A1(S) O

FB +

on)Compensati (Internal

(S)V (S)V

A2(S) FB

COMP

(S)V (S)V

A3(S) OSC

COMP

PHASE ∆

1SCRSCL 1SCR

(S)V (S)V

A4(S) 2

PHASE

OUT +⋅⋅+⋅⋅ +⋅⋅

OUT

CL O

FBCOMPPHASEOUT

OFBCOMPPHASE

V(S)

A(S) V(S)

V(S)V(S)V(S)V(S)

A1(S)A2(S)A3(S)A4(S)

=⋅⋅⋅

where A1(S) is the transfer function of the resistor-

divider, A2(S) is the transfer function of the feedback

compensation network, A3(S) is the transfer function

of the PWM modulator, A4(S) is the transfer function

of the output LC filter, and ACL(S) is the transfer func-

tion of the closed-loop control system. Refer to figure

3. The Pole and Zero frequencies of the A1(S), A2(S),

A3(S) and ACL(S) are shown or calculated as the fol-

lowing equations:

)(F 0.4kHzF ZZA21 =)(F 430kHzF P2PA21 =

LCx2

FPA41,2 π

=xRxC2 1

FZA41 π

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw17

Application Information (Cont.)

Feedback Compensation (Cont.)

where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole

and Zero frequencies of the A2(S), the FPA41,2, and FZA41

are the double-Pole and Zero frequencies of the A4

(S), the VIN is the input voltage of the PWM converter

and the load resistance of the converter is very large.

For good converter stability, the values of the L, C,

and R must be selected to meet the following criteria:

1.Make sure the double-pole frequency(FPA41,2) of

the output filter is bigger than the zero frequency

(FZA21) of the internal compensation network.

2. The following equation must be true:

01.2)

log(2)

R2R1

log()

log( OSC

IN >+⋅⋅−

∆

3. The converter crossover frequency (FCO) must

be in the range of 10%~30% of minimum F OSC of

the converter. The FCO is calculated by using the

following equations:

72)

log(40

)

R2R1R2

log(20)

log(20F at Gain OSC

ZA41

+⋅⋅−

⋅+

∆

⋅=

OSC_MINZA41

FZA41 at Gain

COOSC_MIN

F 30% F10FF 10%

≤











⋅=≤

4. The values of L, C, and R selected must meet

the equations above over the operaing temperatu-

re, voltage, and current ranges.

Figure 3. Converter Gain vs. Frequency

Layout Consideration

In high power switching regulator, a correct layout is

important to ensure proper operation of the regulator.

In general, interconnecting impedances should be

minimized by using short and wide printed circuit

traces. Signal and power grounds are to be kept sepa-

rating and finally combined using ground plane con-

struction or single point grounding. Figure 4 illustrates

the layout, with bold lines indicating high current

paths. Components along the bold lines should be

placed close together. Below is a checklist for your

layout:

1. Begin the layout by placing the power components

first. Orient the power circuitry to chieve a clean

power flow path. If possible, make all the connections

on one side of the PCB with wide, copper filled

areas.

2. Connect the ground of feedback divider directly

to the GND pin of the IC using a dedicated ground

trace.

3. The VCC decoupling capacitor should be right

next to the VCC and GND pins. Capacitor CBOOT

should be connected as close to the BOOT and

PHASE pins as possible.

-60

-40

-20

100

1001K10K100K1M10M

Compensation Gain

FZA41

FPA41,2

Frequency (f, Hz)

Gain (dB)

FZA21

FPA21

Converter Gain

PWM &Filter Gain

FCO

4. Minimize the length and increase the width of

the trace between UGATE/LGATE and the gates of

the MOSFETs to reduce the impedance driving the

MOSFETs.

5. Use an dedicated trace to connect the ROCSET

and the Drain pad of the low-side MOSFET, Kevin

connection , for accurate current sensing.

6. Keep the switching nodes (UGATE, LGATE, and

PHASE) away from sensitive small signal nodes

since these nodes are fast moving signals. Therefore,

keep tracing to these nodes as short as possible.

7. Place the decoupling ceramic capacitor CHF near

the Drain of the high-side MOSFET as close as

possible. The bulk capacitors CIN are also placed

near the Drain.

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw18

Layout Consideration (Cont.)

Application Information (Cont.)

8. Place the Source of the high-side MOSFET and

the Drain of the low-side MOSFET as close as

possible. Minimizing the impedance with wide lay-

out plane between the two pads reduces the volt-

age bounce of the node.

9. Use a wide power ground plane, with low

impedance, to connect the CHF, CIN, COUT, Schottky

diode, and the Source of the low-side MOSFET

and to provide a low impedance path between the

components for large and high frequency switch-

ing currents.

VIN

VOUT

COUT

CIN

APW7120

UGATE

LGATE

VCC

PHASE

BOOT

CHF

Figure 4. Recommended Layout Diagram

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw19

Package Information

SOP-8

LMIN.MAX.

1.75

0.10

0.170.25

0.25

MILLIMETERS

b0.310.51

SOP-8

0.250.50

0.401.27

MIN.MAX.

INCHES

0.069

0.004

0.0120.020

0.0070.010

0.0100.020

0.0160.050

0.010

1.27 BSC0.050 BSC

A2 1.25 0.049

SEE VIEW A

h X 45

A1 A2

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.

3. Dimension “E” does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

3.80

5.80

4.80

4.00

6.20

5.00 0.1890.197

0.2280.244

0.1500.157

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw20

Carrier Tape & Reel Dimensions

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

12.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

SOP-8

4.0±0.10

8.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

6.40±0.20

5.20±0.20

2.10±0.20

(mm)

Package Type Unit Quantity

SOP-8 Tape & Reel 2500

Devices Per Unit

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw21

t 25 C to Peak

Ramp-up

Ramp-down

Preheat

Tsmax

Tsmin

Temperature

Time

Critical Zone

TL to TP

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec

HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C

PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C

TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles

ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V

Latch-Up JESD 78 10ms, 1tr > 100mA

Reliability Test Program

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average ramp-up rate

(TL to TP) 3°C/second max. 3°C/second max.

Preheat

- Temperature Min (Tsmin)

- Temperature Max (Tsmax)

- Time (min to max) (ts)

100°C

150°C

60-120 seconds

150°C

200°C

60-180 seconds

Time maintained above:

- Temperature (TL)

- Time (tL) 183°C

60-150 seconds 217°C

60-150 seconds

Peak/Classification Temperature (Tp)

See table 1 See table 2

Time within 5°C of actual

Peak Temperature (tp) 10-30 seconds 20-40 seconds

Ramp-down Rate 6°C/second max. 6°C/second max.

Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.

Note: All temperatures refer to topside of the package. Measured on the body surface.

Classification Reflow Profiles

Reflow Condition (IR/Convection or VPR Reflow)

Rev. A.5 - Jun., 2008

APW7120

www.anpec.com.tw22

Table 2. Pb-free Process – Package Classification Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*

1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*

≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*

* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated

classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL

level.

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 240 +0/-5°C 225 +0/-5°C

≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Classification Reflow Profiles (Cont.)