WSF512K32-XXX 512KX32 SRAM / FLASH MODULE FEATURES FLASH MEMORY FEATURES Access Times of 25ns (SRAM) and 70, 90ns (FLASH) 100,000 Erase/Program Cycles Packaging Sector Architecture * 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402) * 8 equal size sectors of 64KBytes each * Any combination of sectors can be concurrently erased. Also supports full chip erase * 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Figure 2). Package to be developed. 5 Volt Programming; 5V 10% Supply Embedded Erase and Program Algorithms 512Kx32 SRAM Hardware Write Protection 512Kx32 5V Flash Page Program Operation and Internal Program Control Time. Organized as 512Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus * This product is subject to change without notice. Note: Programming information available upon request. Low Power CMOS Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 13 grams typical Figure 1 - PIN CONFIGURATION FOR WSF512K32-29H2X PIN DESCRIPTION TOP VIEW I/O0-31 Data Inputs/Outputs A0-18 Address Inputs SWE1-4# 1 12 FWE2# I/O8 11 23 34 I/O15 45 VCC I/O24 56 I/O31 I/O9 SWE2# I/O14 I/O25 SWE4# I/O30 I/O10 GND I/O13 I/O26 FWE4# I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE# A12 A4 A1 A11 A9 A17 SWE1# A5 A2 A0 A15 FWE1# A13 A6 A3 A18 VCC I/O7 A8 FWE3# I/O23 I/O0 FCS# I/O6 I/O16 SWE3# I/O22 I/O1 SCS# I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 22 33 44 55 SRAM Write Enables SCS# SRAM Chip Select OE# Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-4# FCS# Flash Write Enables Flash Chip Select BLOCK DIAGRAM FWE1# SWE1# FWE2# SWE2# FWE3# SWE3# FWE4# SWE4# OE# A0-18 SCS# FCS# 512K x 8 Flash 66 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 2 - PIN CONFIGURATION FOR WSF512K32-29G2TX PIN DESCRIPTION TOP VIEW NC A0 A1 A2 A3 A4 A5 SWE3# GND SWE4# FWE1# A6 A7 A8 A9 A10 VCC Address Inputs SRAM Write Enables SCS# SRAM Chip Select OE# Output Enable VCC Power Supply GND Ground NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Not Connected FWE1-4# FCS# Flash Write Enables Flash Chip Select BLOCK DIAGRAM FWE1# SWE1# FWE2# SWE2# FWE3# SWE3# FWE4# SWE4# OE# A0-18 SCS# FCS# A16 FCS# OE# SWE2# A17 FWE2# FWE3# FWE4# A18 SCS# SWE1# A15 A14 A13 A12 A11 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Data Inputs/Outputs A0-18 SWE1-4# 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O0-31 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 The Microsemi 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 SRAM TRUTH TABLE Max +125 +150 7.0 150 7.0 -0.5 Unit C C V C V SCS# H L L L OE# X L H X SWE# X H H L Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active NOTE: 1. FCS# must remain high when SCS# is low. Parameter Flash Data Retention 20 years Flash Endurance (write/erase cycles) 100,000 NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. CAPACITANCE Ta = +25C Parameter OE# capacitance F/S WE1-4# capacitance F/S CS# capacitance D0-31 capacitance A0-18 capacitance RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 -0.5 Max 5.5 VCC + 0.3 +0.8 Unit V V V Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 80 30 50 30 80 Unit pF pF pF pF pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage Symbol ILI ILO ICCx32 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC SCS# = VIH, OE# = VIH, VOUT = GND to VCC SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5 FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 6mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 FCS# = VIL, OE# = SCS# = VIH FCS# = VIL, OE# = SCS# = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 Min Max 10 10 550 90 0.4 2.4 250 300 0.45 0.85 x VCC VCC -0.4 3.2 4.2 Unit A A mA mA V V mA mA V V V V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX SRAM AC CHARACTERISTICS SRAM AC CHARACTERISTICS VCC = 5.0V, -55C TA +125C VCC = 5.0V, -55C TA +125C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 -25 Min 25 Max 25 0 25 15 3 0 12 12 Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time Units ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. Symbol Min tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH 25 20 20 15 20 3 0 3 -25 Max 15 0 Units ns ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. FIGURE 3 - AC TEST CIRCUIT AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level I OL Current Source Unit V ns V V NOTES: V Z is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. VZ 1.5V D.U.T. (Bipolar Supply) C eff = 50 pf Typ VIL = 0, VIH = 3.0 5 1.5 1.5 I OH Current Source Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 4 - SRAM TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA tRC ADDRESS SCS# tAA tCHZ tACS tCLZ tOH SOE# DATA I/O PREVIOUS DATA VALID DATA VALID tOE tOLZ DATA I/O tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH) READ CYCLE 2, (SWE# = FCS# = VIH) FIGURE 5 - SRAM WRITE CYCLE - SWE# CONTROLLED tWC ADDRESS tAW tAH tCW SCS# tAS tWP SWE# tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH) FIGURE 6 - SRAM WRITE CYCLE - SCS# CONTROLLED tWC ADDRESS tAS tAW tAH tCW SCS# tWP SWE# tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH) Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED VCC = 5.0V, -55C TA +125C Parameter Symbol Min -70 Max Min -90 Max Unit Write Cycle Time tAVAV tWC 70 90 Chip Select Setup Time tELWL tCS 0 0 ns ns Write Enable Pulse Width tWLWH tWP 45 45 ns Address Setup Time tAVWL tAS 0 0 ns Data Setup Time tDVWH tDS 45 45 ns Data Hold Time tWHDX tDH 0 0 ns Address Hold Time tWLAX tAH 45 45 ns Write Enable Pulse Width High tWHWL tWPH 20 Duration of Byte Programming Operation (1) tWHWH1 Chip and Sector Erase Time (2) tWHWH2 Read Recovery Time Before Write tGHWL 20 ns 300 15 VCC Set-up Time tVCS 0 0 50 50 Chip Programming Time 300 s 15 sec s s 11 11 sec Output Enable Setup Time tOES 0 0 ns Output Enable Hold Time (4) tOEH 10 10 ns Chip Erase Time (3) 64 64 sec Max Unit NOTES: 1. Typical value for twhwh1 is 7ns. 2. Typical value for twhwh2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data# Polling. FLASH AC CHARACTERISTICS - READ ONLY OPERATIONS VCC = 5.0V, -55C TA +125C Parameter Symbol Min -70 Max 70 Min -90 Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC 70 90 90 ns ns Chip Select Access Time tELQV tCE 70 90 ns OE# to Output Valid tGLQV tOE 35 35 ns Chip Select to Output High Z (1) tEHQZ tDF 20 20 ns OE# High to Output High Z (1) tGHQZ tDF 20 20 ns Output Hold from Address, FCS# or OE# Change, whichever is first tAXQX tOH 0 0 ns 1. Guaranteed by design, not tested. Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED VCC = 5.0V, -55C TA +125C Parameter Symbol Min -70 Max 70 Min -90 Max 90 Unit Write Cycle Time tAVAV tWC ns FWE# Setup Time tWLEL tWS 0 0 ns FCS# Pulse Width tELEH tCP 45 45 ns Address Setup Time tAVEL tAS 0 0 ns ns Data Setup Time tDVEH tDS 45 45 Data Hold Time tEHDX tDH 0 0 ns Address Hold Time tELAX tAH 45 45 ns FCS# Pulse Width High tEHEL tCPH 20 20 ns Duration of Programming Operation (1) tWHWH1 300 300 s Sector Erase Time (2) tWHWH2 15 15 sec Read Recovery Time tGHEL 0 0 ns Chip Programming Time 11 sec Chip Erase Time (3) 64 sec NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 7 - AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS tRC Addresses Addresses Stable tACC FCS# tDF tOE OE# FWE# Outputs tCE tOH High Z Output Valid High Z NOTE: SCS# = VIH Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 8 - WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED Data# Polling Addresses 5555H PA tWC tAS PA tAH tRC FCS# tGHWL OE# tWP FWE# tWHWH1 tWPH tCS tDH A0H Data tDF tOE D7# PD DOUT tDS tOH 5.0 V tCE NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. 5. 6. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. SCS# = VIH Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 9 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY tAS Addresses 5555H tAH 2AAAH 5555H 5555H 2AAAH SA FCS# tGHWL OE# tWP FWE# tWPH tCS Data tDH AAH 55H 80H AAH 55H 10H/30H tDS VCC tVCS NOTES: 1. SA is the sector address for Sector Erase. 2. SCS# = VIH Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 10 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY t CH FCS# t DF t OE OE# tOEH FWE# tCE t OH D7# D7 High Z D7 = Valid Data tWHWH 1 or 2 D0-D7 Valid Data D0-D6 = Invalid D0-D6 t OE D7 D7 D7 Valid Data High Z tWHWH 1 or 2 NOTE: SCS# = VIH Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX FIGURE 11 - WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED Data# Polling Addresses 5555H PA tWC tAS PA tAH FWE# tGHEL OE# tCP FCS# tWHWH1 tCPH tWS tDH A0H Data D7# PD DOUT tDS 5.0 V NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. 5. 6. DOUT is the output of the data written to the device. Figure indicates the last two bus cycles of a four bus cycle sequence. SCS# = VIH Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 12 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX PACKAGE 509 - 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) 25.15 (0.990) 0.26 (0.010) SQ 4.57 (0.180) MAX 22.36 (0.880) 0.26 (0.010) SQ 0.27 (0.011) 0.04 (0.002) 0.25 (0.010) REF Pin 1 24.03 (0.946) 0.26 (0.010) R 0.25 (0.010) 0.19 (0.007) 0.06 (0.002) 1 / 7 1.0 (0.040) 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) REF The Microsemi 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 13 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX PACKAGE 402 - 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) 0.1 (0.005) 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 14 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX ORDERING INFORMATION W S F 512K32 - 29 X X X MICROSEMI CORPORATION SRAM FLASH ORGANIZATION, 512K x 32 SRAM AND FLASH ACCESS TIME (ns) 29 = 25ns SRAM and 90ns FLASH PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C LEAD FINISH: Blank = Gold plated leads A = Solder dip leads Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 15 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com WSF512K32-XXX Document Title 512Kx32 SRAM / FLASH MODULE Revision History Rev # History Release Date Status Rev 10 Changes (Pg. 1-16) August 2011 Final 10.1 Change document layout from White Electronic Designs to Microsemi 10.2 Add document Revision History page Microsemi Corporation reserves the right to change products or specifications without notice. August 2011 Rev. 10 (c) 2011 Microsemi Corporation. All rights reserved. 16 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com