1
Standard Products
UT54ACS153/UT54ACTS153
Dual 4 to 1 Multiplexers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS153 - SMD 5962-96550
UT54ACTS153 - SMD 5962-96551
DESCRIPTION
The UT54ACS153 and the UT54ACTS153 are dual four to one
line selectors/multiplexers. Common inp uts A and B sel ect a
value from one of four sources for each section and routes the
value from each section to their respective outputs. Separate
strobe inputs, G are provided for each of the two four-line sec-
tions.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
PINOUTS 16-Pin DIP
Top View
16-Lead Flatpa ck
Top View
LOGIC SYMBOL
SELECT
INPUTS DATA INPUTS OUTPUT
CONTROL OUTPUT
B A C0 C1 C2 C3 GY
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H
1
2
3
4
5
7
6
16
15
14
13
12
10
11
1G
B
1C3
1C2
1C1
1C0
1Y
VDD
2G
A
2C3
2C2
2C1
2C0
8 9
VSS 2Y
1
2
3
4
5
7
6
16
15
14
13
12
10
11
VDD
1G
B
1C3
1C2
1C1
1C0
1Y
2G
A
2C3
2C2
2C1
2C0
VSS 2Y
89
(14)
A(2)
B1
0
MUX
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
(1)
1G EN
(6)
1C0 0
(5)
1C1 (4)
1C2 (3)
1C3 (15)
2G (10)
2C0 (11)
2C1
(7) 1Y
2C2 (13)
2C3
(9) 2Y
(12)
1
2
3
G
0
3
---
2
LOGIC DIAGRAM
(7) 1Y
(9) 2Y
(1)
(6)
(5)
(4)
(3)
(2)
(14)
(10)
(11)
(12)
(13)
2C3
2C2
2C1
2C0
A
B
1C3
1C2
1C1
1C0
1G
(15)
OUTPUT
CONTROL
OUTPUT
CONTROL 2G
DATA 1
DATA 2
SELECT
3
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyo nd limits indicated in the opera tional sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Vol t a ge any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input voltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD - 0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 2.1 mW/
MHz
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
IDDQ Quiescent Supply Current VDD = 5.5V 10 μA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
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Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-385 35, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal ampl itude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -5 5 °C < TC < +125°C); Unless otherw ise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPHL Data to output Yn 2 16 ns
tPLH Data to output Yn 2 12 ns
tPHL Strobe to output Yn 1 15 ns
tPLH Strobe to output Yn 1 14 ns
tPHL Select to output Yn 2 16 ns
tPLH Select to output Yn 2 14 ns
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PACKAGING Side-Brazed Packages
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FLATPACK PACKAGES
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UT54ACS153/U T54ACTS153: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96550 = UT54ACS153
96551 = UT54AC TS153
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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