TRANSISTOR OUTLINE PACKAGES Q-TECH TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz CORPORATION Description Q-Tech's Transistor Outline package crystal oscillators consist of a source clock square wave generator, logic output buffers and/or logic divider stages, and a round AT high-precision quartz crystal built in an all metal TO package. Features * * * * * * * * * * * * * * * * * * * * Made in the USA ECCN: EAR99 DFARS (Berry Amendment) Compliant USML Registration # M17677 Wide frequency range from 0.045Hz to 125MHz Available as QPL MIL-PRF-55310/09 and/10 (TTL) and /12 (CMOS) Choice of TO packages and pin outs Choice of supply voltages Choice of output logic options ( CMOS, ACMOS, HCMOS, LVHCMOS, and TTL) AT-Cut crystal All metal hermetically sealed package Tight or custom symmetry available Low height available External tuning capacitor option Fundamental and third overtone designs Tristate function option D Three-point crystal mounts Custom design available tailors to meet customer's needs Q-Tech does not use pure lead or pure tin in its products RoHS compliant Applications * Designed to meet today's requirements for all voltage applications * Wide military clock applications * Industrial controls * Microcontroller driver Ordering Information Model # C AC HC T L N R Z = = = = = = = = QTXX -- XX -- D -- XX -- M -- 60.000MHz CMOS +5V to +15V * ACMOS +5V HCMOS +5V TTL +5V LVHCMOS + 3.3V LVHCMOS + 2.5V LVHCMOS + 1.8V Z output Output frequency Screened to MIL-PRF-55310,level B (Left blank if no screening) Tristate Option D (Left blank if no Tristate) 1 = 100ppm at 0C to +70C 3** = 5ppm at 0C to +50C 4 = 50ppm at 0C to +70C 5 = 25ppm at -20C to +70C 6 = 50ppm at -55C to +105C 9 = 50ppm at -55C to +125C 10 = 100ppm at -55C to +125C 11 = 50ppm at -40C to +85C 12 = 100ppm at -40C to +85C (*) Please specify supply voltage when ordering CMOS (**) Require an external capacitor For frequency stability vs. temperature options not listed herein, please request a custom part number. For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com Packaging Options * Standard packaging in black foam Other Options Available For An Additional Charge * Solder Dip Sn/Pb 60/40% * P. I. N. D. test * Lead trimming All Transistor Outline packages are available in surface mount form. Specifications subject to change without prior notice. Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 1 TRANSISTOR OUTLINE PACKAGES TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz Q-TECH CORPORATION Electrical Characteristics Parameters Output freq. range (Fo) AC C QT1, 14 HC 244Hz -- 15MHz QT2 QT3 0.045Hz -- 85MHz -62C to + 125C F and Vdd dependent 3 mA max. at 5V up to 5MHz 25 mA max. at 15V up to 15MHz 20 mA max. 25 mA max. 35 mA max. 45 mA max. - 45/55% max. Fo < 4MHz 40/60% max. Fo 4MHz (Measured from 10% to 90%) Start-up time (Tstup) 10ms max. Output voltage (Voh/Vol) 1mA typ. at 5V 6.8mA typ. at 15V 0.9 x Vdd min.; 0.1 x Vdd max. Call for details Jitter RMS 1 (at 25C) Aging (at 70C) Available in 2.5Vdc (N) or 1.8Vdc (R) Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf) ECL, PECL, LVPECL are available. Please contact Q-Tech for details. Q-TECH Corporation - 24mA 8 mA VIH 2.2V Oscillation; VIL 0.8V High Impedance 10TTL Fo < 20MHz 6TTL Fo 20MHz 2.4V min.; 0.4V max. -1.6mA / TTL +40A / TTL 8ps typ. - < 40MHz 5ps typ. - 40MHz 15pF // 10k 0.9 x Vdd min.; 0.1 x Vdd max. 4mA . VIH 0.7 x Vdd Oscillation; VIL 0.3 x Vdd High Impedance 15ps typ. - < 40MHz 8ps typ. - 40MHz 5ppm max. first year / 2ppm typ. per year thereafter 10150 W. Jefferson Boulevard, Culver City 90232 Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 3 mA max. - 0.045Hz ~ < 500kHz 6 mA max. - 500kHz ~ < 16MHz 10 mA max. - 16MHz ~ < 32MHz 20 mA max. - 32MHz ~ < 60MHz 30 mA max. - 60MHz ~ < 100MHz 40 mA max. - 100MHz ~ 125MHz 15ns max. Fo < 15kHz 6ns max. Fo 15kHz ~ 39.999MHz 3ns max. Fo 40MHz ~ 125 MHz (Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL) 15pF // 10k Output Load (*) Z 0.045Hz ~ < 16MHz 16MHz ~ < 40MHz 40MHz ~ < 60MHz 60MHz ~ 85MHz 45/55% max. Fo < 12MHz 40/60% max. Fo 12MHz 30ns max. Rise and Fall times (with typical load) Enable/Disable Tristate function Pin 1 3.3Vdc 10% See Option codes Symmetry (50% of ouput waveform or 1.4Vdc for TTL) Output Current (Ioh/Iol) 732.4Hz -- 85MHz See Option codes Operating temp. (Topr) Operating supply current (Idd) (No Load) 0.045Hz -- 85MHz 5.0Vdc 10% Freq. stability (F/T) Storage temp. (Tsto) 732.4Hz -- 125MHz 732.4Hz -- 85MHz 5V ~ 15Vdc 10% Supply voltage (Vdd) L (*) T 732.4Hz -- 85MHz - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech .co m 2 TRANSISTOR OUTLINE PACKAGES Q-TECH TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz CORPORATION Package Configuration Versus Pin Connections A B QT1 C QT2 QT3 .260 (6.60) Q-TECH P/N FREQ. D/C S/N .300 MAX. .500 (12.70) (7.62) .200 MAX. (5.08) .500 .500 MIN. (12.70) MIN. (12.70) MAX. .175 (4.45) .500 MIN. (12.70) MIN. .018 (.457) .018 (.457) .018 (.457) .018 (.457) .540 (13.72) .500 .360 (9.14) QT14 Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N D PIN No. 1 (12.70) PIN No. 1 PIN No. 1 .200 (5.08) .282 (7.16) .300 (7.62) .360 (9.14) PIN No. 1 .200 (5.08) .075 (1.91) Dimensions are in inches (mm) QT # Conf Vcc GND Case Output E/D Ext. Cap QT1 A 8 4 4 5 1 1&2 QT2 B 12 6 6 5 3 9 & 10 QT3 QT14 C D 8 8 4 4 4 4 5 5 1 1 Equivalent MIL-PRF-55310 Configuration /09 = QT1T /12 = QT1C N/A 1&2 /10 = QT3T /13 = QT3C 1&2 N/A Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 3 TRANSISTOR OUTLINE PACKAGES Q-TECH TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz CORPORATION Output Waveform (Typical) Test Circuit TH SYMMETRY = x 100% T TYPICAL TEST CIRCUIT FOR QT1T3 (10TTL) +5VDC 0.01uF Tr Tf OUTPUT 270 Vdd VOH 0.9xVdd D1 8 5 QT1T3 D2 0.5xVdd 6k 1 2 20pF(*) 4 D3 0.1xVdd D4 VOL GND Cext GND D1-D4: 1N4148 or equivalent TH (*) CL includes scope probe capacitance Startup Time Vdd Typical test circuit for TTL logic. T TYPICAL SET-UP FOR START-UP TIME RL + - mA Vdd OUT OUT E/D GND + + POWER SUPPLY - 0.1F or 0.01F Vdc - LOAD 6 TTL CL(*) 12pF RL 430 RS 10k 10 TTL 20pF 270 6k Variable Ramp Oscilloscope 54616B Agilent CL DUT Rs Ts Start-up box (*) CL inclides the loading effect of the oscilloscope probe. Supply Current Typical test circuit for CMOS logic TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD Vdd Out Output 0.1F or E/D GND 0.01F + Vdc - 40 35 30 10k 15pF (*) Icc (mA) + mA + Power supply - 45 Ground 25 20 15 10 5 Tristate Function 0 The Tristate function on pin 1 has a built-in pull-up resistor typical 50k, so it can be left floating or tied to Vdd without deteriorating the electrical performance. 0.5 2 (*) CL includes probe and jig capacitance 8 16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160 Freq(MHz) Icc 3.3V Icc 5V Frequency vs. Temperature Curve 40 FREQUENCY STABILITY VERSUS TEMPERATURE QT1L -36MHz 30 Frequency Stability (PPM) 20 10 0 -10 -20 -30 -40 -50 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (C) SN2 SN3 SN4 SN1 Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 4 TRANSISTOR OUTLINE PACKAGES Q-TECH TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz CORPORATION Thermal Characteristics The heat transfer model in a hybrid package is described in figure 1. Heat spreading occurs when heat flows into a material layer of increased cross-sectional area. It is adequate to assume that spreading occurs at a 45 angle. The total thermal resistance is calculated by summing the thermal resistances of each material in the thermal path between the device and hybrid case. RT = R1 + R2 + R3 + R4 + R5 D/A epoxy Die D/A epoxy 45 Substrate Hybrid Case R1 R2 Die D/A epoxy The total thermal resistance RT (see figure 2) between the heat source (die) to the hybrid case is the Theta Junction to Case (Theta JC) inC/W. R3 (Figure 1) Substrate R4 D/A epoxy T * Theta junction to case (Theta JC) for this product is 30C/W. * Theta case to ambient (Theta CA) for this part is 100C/W. * Theta Junction to ambient (Theta JA) is 130C/W. R5 Hybrid Case A CA T C T J Die JC Maximum power dissipation PD for this package at 25C is: * PD(max) = (TJ (max) - TA)/Theta JA * With TJ = 175C (Maximum junction temperature of die) * PD(max) = (175 - 25)/130 = 1.15W 45 Heat JA JC (Figure 2) CA Environmental Specifications Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Transistor Outline packages. Q-Tech can also customize screening and test procedures to meet your specific requirements. The Transistor Outline packages are designed and processed to exceed the following test conditions: Environmental Test Temperature cycling Constant acceleration Seal Fine Leak Burn-in Aging Vibration sinusoidal Shock, non operating Thermal shock, non operating Ambient pressure, non operating Resistance to solder heat Moisture resistance Terminal strength Resistance to solvents Solderability Test Conditions MIL-STD-883, Method 1010, Cond. B MIL-STD-883, Method 2001, Cond. A, Y1 MIL-STD-883, Method 1014, Cond. A 160 hours, 125C with load 30 days, 70C MIL-STD-202, Method 204, Cond. D MIL-STD-202, Method 213, Cond. I MIL-STD-202, Method 107, Cond. B MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum MIL-STD-202, Method 210, Cond. C MIL-STD-202, Method 106 MIL-STD-202, Method 211, Cond. C MIL-STD-202, Method 215 MIL-STD-202, Method 208 Please contact Q-Tech for higher shock requirements Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 5 TRANSISTOR OUTLINE PACKAGES Q-TECH TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS 1.8 to 15Vdc - 0.045Hz to 125MHz CORPORATION Period Jitter As data rates increase, effects of jitter become critical with its budgets tighter. Jitter is the deviation of a timing event of a signal from its ideal position. Jitter is complex and is composed of both random and deterministic jitter components. Random jitter (RJ) is theoretically unbounded and Gaussian in distribution. Deterministic jitter (DJ) is bounded and does not follow any predictable distribution. DJ is also referred to as systematic jitter. A technique to measure period jitter (RMS) one standard deviation (1) and peak-to-peak jitter in time domain is to use a high sampling rate (>8G samples/s) digitizing oscilloscope. Figure shows an example of peak-to-peak jitter and RMS jitter (1) of a QT1ACD-40MHz, at 5.0Vdc. RMS jitter (1): 4.89ps Phase Noise and Phase Jitter Integration Peak-to-peak jitter: 44.4ps Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source is floated from the ground and isolated from external noise to ensure accuracy and repeatability. In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be done by converting L(f) back to S(f) over the bandwidth of interest, integrating and performing some calculations. L(f) Symbol S (f)=(180/)x2 L(f)df RMS jitter = S (f)/(fosc.360) Definition Integrated single side band phase noise (dBc) Spectral density of phase modulation, also known as RMS phase error (in degrees Jitter(in seconds) due to phase noise. Note S (f) in degrees. The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of phase jitter contributed by the noise in that defined bandwidth. Figure below shows a typical Phase Noise/Phase jitter of a QT1ACD10M, 5.0Vdc, 40MHz clock at offset frequencies 10Hz to 5MHz, and phase jitter integrated over the bandwidth of 12kHz to 1MHz. QT1ACD10M, 5.0Vdc - 40MHz Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Transistor Outline Packages (Revision A, May 2008) (ECO# 9304) 6