5962-9169201M3X - Cirrus Logic, Inc.



Cirrus Logic, Inc. 1997

Cirrus Logic, Inc.

Crystal Semiconductor Products Divisio n

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

CS5101A

CS5102A

16-Bit, 100 kHz / 20 kHz A/D Converters

Features

lMonolithi c CMOS A/D Converters

-Inherent Sampli ng Architecture

-2-Channel Input Mult iplexer

-Flexible Serial Output Port

lUltra-Low Distortion

-S/(N+D): 92 dB

-THD: 0.001%

lConversion Time

-CS5101A: 8 µs

-CS5102A: 40 µs

lLinearity Error: ±0.001% FS

-Guaranteed No Missing Codes

lSelf-Calibration Mai nta ins Accuracy

-Over Time and Temperature

lLow Powe r Consumption

-CS5101A: 320 mW

-CS5102A: 44 mW

-Power-down Mode: <1 mW

lEvaluation Board Available

Description

The CS5101A and CS5102A are 16-bit monolithic

CMOS analog-to-digital converters capable of 100 kHz

(5101A) and 20 kHz (5102A) throughput. The

CS5102A’s low power consump tion of 44 mW, coupled

with a power do wn mode, makes it particula rly suitable

for battery powered operation.

On-chip self-calibration circuitry achieves nonlinearity of

±0.001% of FS an d gua rantees 16- bit n o miss in g co des

over the entire specified temperature range. Superior lin-

earity also leads to 92 dB S/(N+D) with harmonics below

-100 dB . Offse t and fu ll-sc ale error s are m inimize d dur-

ing the calibration cycle, eliminating the need for external

trimming.

The CS5101A an d CS5102A each consist of a 2-cha n-

nel input multiplexer, DAC, conversion and calibration

microcon troller, clock gene rator, comparator , and serial

communications port. The inherent sampling architec-

ture of the device eliminates the need for an external

track and hold amplifier.

The converters' 16-bit data is output in serial form with ei-

ther binary or 2's complement coding. Three output

timing modes are available for easy interfacing to micro-

controllers and shift registers. Unipolar and bipolar input

ranges are digitally selectable.

ORDERING INFORMATION

See page 36.

CLKIN

REFBUF

VREF

AIN1

AGND

HOLD SLEEPRST CODEBP/UP TRK1 TRK2 SSH/SDLSDATA

SCLK

TEST

DGND VD- VD+VA-VA+

12 28 2 5 16 17 8 9 11 15

25 23 716

Clock

Generator Control

Calibration Microcontroller

Comparator

16-Bit Charge

SRAM

Redistribution

DAC

STBY CRS/FIN

XOUT 4

AIN2 24

CH1/2 13

SCKMOD

OUTMOD

MAR ‘95

DS45F2

CS5101A-J,K CS5101A-A,B CS5101A-S,T

Parameter* Min Typ Max Min Typ Max Min Typ Max Units

Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C

Accuracy

Linearity Error -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

0.002

0.001

± 1/4

0.003

0.002

0.001

± 1/4

0.003

0.002

0.001

± 1/2

0.004

0.003

%FS

∆LSB

Differential Linearity (Notes 3, 4) 16 - - 16 - - 16 - - Bi ts

Full Scale Error -J ,A ,S ( No te 1 )

-K,B,T

Drift (Note 2)

± 1

± 4

± 3

± 1

± 4

± 3

± 2

± 5

± 4

LSB

∆LSB

Unipolar Offset -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 2

± 1

± 5

± 4

± 2

± 1

± 5

± 4

± 2

± 5

± 4

LSB

∆LSB

Bipolar Offset -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 2

± 1

± 5

± 3

± 2

± 5

± 3

± 2

± 5

± 3

LSB

∆LSB

Bipolar Negative Fu ll- Sc a le Er ro r

-J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 1

± 4

± 3

± 1

± 4

± 3

± 1

± 2

± 5

± 3

LSB

∆LSB

Dynamic Performance

(Bipolar Mode)

Peak Harmonic or Spurious Noise (Note 1)

1 kHz Input -J,A,S

-K,B,T

12 kHz Input -J,A,S

-K,B,T

100

102

100

102

100

102

Total H armon ic Dist ort ion - J,A, S

-K,B,T -

-0.002

0.001 -

-0.002

0.001 -

-0.002

0.001 -

Signal-to-Noise Ratio (Note 1)

0dB Input -J,A,S

-K,B,T

-60 dB Input -J,A,S

-K,B,T

Noise (Note 5)

Unipolar Mode

Bipolar Mode -

-35

70 -

-35

70 -

-35

70 -

-µVrms

µVrms

CS5101A

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V;

VREF = 4.5V ; Full-Scale Input Si newave, 1 kHz; CLKIN = 4 MHz for -16, 8 MHz for -8; fs = 50 kHz for -16,

100 kHz for -8; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each c hannel tested separately; A nalog

Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified)

Notes: 1. Applies after c alibration at any temperature wi thin the specified temperature r ange. At temp

2. Total drift over specified temperature range after c alibration at power-up at 25 °C.

3. Minimum resolution for which no missi ng codes is guaranteed over the specified temperature range.

4. Clock speeds of less than 1.0 MHz, at temperatures >100°C will degrade DNL performance.

5. Wideband noise aliased into the baseband. Referred to the input.

*Refer to

Parameter Definiti ons

(immediately following the pin descriptions at the end of this data sheet).

Specific ations are subject to change without notice.

2DS45F2

CS5101A

No tes : 6. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.

7. Conversion time scales directly to the master clock speed. The times shown are for synchronous,

intern al lo opback (FRN mo de) wit h 8.0 MH z CLKIN . In PD T, RBT, a nd SSC modes, async hronous d elay

between the falling edge of HOLD and the start of conversion may add to the apparent conversion time.

This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can

be increased as long as the HOLD sample rate is 100 kHz max.

8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge.

FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 µs with an 8 MHz

clock, however; in PDT, RBT, or SSC modes, at clock frequencies of 8 MHz or less, fine charge may

be less than 9 clock cycles. This reflects the typ. specification (6 clock cycles + 1.125 µs).

9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions

affecting acquisition and conversion times, as described above.

10. All outputs unloaded. All inputs at VD+ or DGND.

11. P ower c onsump tion i n the s leep mode ap plies with n o mast er clo ck appl ied (C LKI N held high or low) .

12. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection

impr oves by 6 dB in the uni pola r mode to 90 dB. Figur e 23 show s a pl ot of ty pic al pow er supp ly

reje ction v ersus freque ncy.

ANALOG CHARACTERISTICS (continued)

CS5101A -J,K CS5101A -A,B CS5101A -S,T

Parameter* Symbol Min Typ Max Min Typ Max Min Typ Max Units

Specified Temperature Range - 0 to +70 40 to +85 55 to +125 °C

Ana log Inpu t

Aperture Time - - 25 - - 25 - - 25 - ns

Aperture Jitter - - 100 - - 100 - - 100 - ps

Input Capacitance (Note 6)

Unipolar Mode

Bipolar Mode -

-320

200 425

265 -

-320

200 425

265 -

-320

200 425

265 pF

Conv ersion & Thr oughput

Conversion Time (Note 7)

-8

-16 tc

tc -

-8.12

16.25 -

-8.12

16.25 -

-8.12

16.25 µs

µs

Acquisition Time (Note 8)

-8

-16 ta

ta -

2.6 1.88

3.75 -

2.6 1.88

3.75 -

2.6 2.88

3.75 µs

µs

Throughput (Note 9)

-8

-16 ftp

ftp 100

50 -

-100

50 -

-100

50 -

-kHz

kHz

Power Supplies

Power Supply Current (Note 10)

Positive Analog

Negative Analog

(SLEEP Hi gh) Positive Digital

Negative Digital

IA+

IA-

ID+

ID-

-21

-11

-28

-15

-21

-11

-28

-15

-21

-11

-28

-15

Power Consumption (Notes 10, 11)

(SLEEP High)

(SLEEP Low) Pdo

Pds -

-320

1430

-320

1430

-320

1430

-mW

Power Supply Rejection: (Note 12)

Positive Supplies

Negative Supplies PSR

PSR -

-84

84 -

-84

84 -

-84

84 -

-dB

DS45F2 3

CS5101A

Notes: 13. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency

is 8.0 MHz in FRN mode (100 kHz sample rate).

14. With a 8 MHz crystal, two 10 pF loading capacitors and a 10 M Ω parallel resistor (see Figure 8) .

15. These times are for FRN mode.

16. SSH only works correctly if HOLD falling edge is wi thin +15 to +30 ns of CH1/2 edge or if CH1/2 edge

occurs after HOLD r ises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes.

17. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must

be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after

HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse wi dth may be as

narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after HOLD falls. This

ensures that the HOLD pulse will meet the minimum specifi cation for thcf.

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = V D+; CL = 50 pF)

Parameter Symbol Min Typ Max Units

CLKIN Period (Note 4)

-8

-16 tclk

tclk 108

250 -

-10,000

10,000 ns

CLKIN Low Time tclkl 37.5 - - ns

CLKIN High Time tclkh 37.5 - - ns

Crystal Frequency (Note 13)

-8

-16 fxtal

fxtal 2.0

2.0 -

-9.216

4.0 MHz

MHz

SLEEP Rising to Oscillator S table (Note 14) - - 2 - ms

RST Pulse Width trst 150 - - ns

RST to STBY Falling tdrrs - 100 - ns

RST Rising to STBY Rising tcal - 11,528,160 - tclk

CH1/2 Edge to TRK1, TRK2 Rising (Note 15) tdrsh1 -80-ns

CH1/2 Edge to TRK1, TRK2 Falling (Note 15) tdfsh4 - - 68tclk+260 ns

HOLD to SSH Falling (Note 16) t dfsh2 -60 ns

HOLD to TRK1, TRK2, Falling (Note 16) t dfsh1 66tclk - 68tclk+260 ns

HOLD to TRK1, TRK2, SSH Rising (Note 16) tdrsh - 120 - ns

HOLD Pulse W idth (Note 17) thold 1tclk+20 - 63tclk ns

HOLD to CH1/2 E dge (Note 16) tdhlri 15 - 64tclk ns

HOLD Falling to CLKIN Falling (Note 17) thcf 95 - 1tclk+10 ns

4DS45F2

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V;

VREF = 4.5V ; Full-Scale Input Si newave, 200 Hz; CLKIN = 1.6 MHz; fs = 20 k Hz; Bipolar Mode; FRN Mode;

AIN1 and AIN2 tied together, each channel tested separately; Analog S ource Impedance = 50 Ω with 1000pF to

AGND unless otherwise specified)

CS5102A-J,K CS5102A-A,B CS5102A-S,T

Parameter* Min Typ Max Min Typ Max Min Typ Max Units

Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C

Accuracy

Linearity Error -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

0.002

0.001

± 1/4

0.003

0.0015

0.002

0.001

± 1/4

0.003

0.0015

0.002

0.001

± 1/2

0.004

0.002

%FS

∆LSB

Differential Linearity (Notes 3, 18) 16 - - 1 6 - - 16 - - Bi ts

Full Scale Error -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 2

± 1

± 4

± 3

± 2

± 1

± 4

± 3

± 2

± 5

± 3

LSB

∆LSB

Unipolar Offset -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 1

± 4

± 3

± 1

± 4

± 3

± 1

± 2

± 5

± 3

LSB

∆LSB

Bipolar Offset -J,A,S (Note 1)

-K,B,T

Drift (Note 2)

± 1

± 4

± 3

± 1

± 2

± 4

± 3

± 1

± 2

± 5

± 3

LSB

∆LSB

Bipolar Negative -J, A,S ( No te 1)

Full-Scale Error -K,B,T

Drift (Note 2)

± 2

± 1

± 4

± 3

± 2

± 4

± 3

± 2

± 5

± 3

LSB

∆LSB

Dynamic Performance

(Bipolar Mode)

Peak Harmonic or -J,A,S (Note 1)

Spurious Noise -K,B,T 96

98 100

102 -

-96

98 100

102 -

-94

98 100

102 -

-dB

Total H armon ic Dist ort ion - J,A, S

-K,B,T -

-0.002

0.001 -

-0.002

0.001 -

-0.002

0.001 -

Signal-to-Noise Ratio (Note 1)

0dB Input -J,A,S

-K,B,T

-60 dB Input -J,A,S

-K,B,T

Noise (Note 5)

Unipolar Mode

Bipolar Mode -

-35

70 -

-35

70 -

-35

70 -

-µVrms

µVrms

Note: 18. Clock speeds of less than 1.6 MHz, at temperatures >100°C will degrade DNL performance.

*Refer to

Parameter Definiti ons

(immediately following the pin descriptions at the end of this data sheet).

Specific ations are subject to change without notice.

CS5102A

DS45F2 5

No tes : 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,

internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling

edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will

not exceed 1 master clock cycle + 140 ns.

20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge.

FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with an 1.6 M Hz

clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may

be less than 9 clock cycles.

21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions

affecting acquisition and conversion times, as described above.

22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.

23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection

impr oves by 6 dB in the uni pola r mode to 90 dB. Figur e 23 show s a pl ot of ty pic al pow er supp ly

reje ction v ersus freque ncy.

CS5102A

ANALOG CHARACTERISTICS (continued)

CS5102A -J,K CS5102A -A,B CS5102A -S,T

Parameter* Symbol Min Typ Max Min Typ Max Min Typ Max Units

Specified Temperature Range - 0 to +70 40 to +85 -55 to +125 °C

Ana log Inpu t

Aperture Time - - 30 - - 30 - - 30 - ns

Aperture Jitter - - 100 - - 100 - - 100 - ps

Input Capacitance (Note 6)

Unipolar Mode

Bipolar Mode

-320

200 425

265 -

-320

200 425

265 -

-320

200 425

265 pF

Conv ersion & Thr oughput

Conversion Time (Note 19) tc- - 40.625 - - 40.625 - - 40.625 µs

Acquisition Time (Note 20) ta- - 9.375 - - 9.375 - - 9.375 µs

Throughput (Note 21) f tp 20 - - 20 - - 20 - - kHz

Power Supplies

Power Supply Current (Note 22)

Positive Analog

Negative Analog

(SLEEP Hi gh) Positive Digital

Negative Digital

IA+

IA-

ID+

ID-

2.4

-2.4

2.5

-1.5

3.5

-3.5

3.5

-2.5

2.4

-2.4

2.5

-1.5

3.5

-3.5

3.5

-2.5

2.4

-2.4

2.5

-1.5

3.5

-3.5

3.5

-2.5

Power Consumption (Notes 11, 22)

(SLEEP High)

(SLEEP Low) Pdo

Pds -

-44

165

-44

165

-44

165

-mW

Power Supply Rejection: (Note 23)

Positive Supplies

Negative Suppli es PSR

PSR -

-84

84 -

-84

84 -

-84

84 -

-dB

Typ. Power (mW) CLKIN (MHz)

34 0.8

37 1.0

39 1.2

41 1.4

44 1.6

6DS45F2

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;

VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)

Parameter Symbol Min Typ Max Units

CLKIN Period (Note 18,24) tclk 0.5 - 10 µs

CLKIN Low Time tclkl 200 - - ns

CLKIN High Time tclkh 200 - - ns

Crystal Frequency (Note 24, 25) fxtal 0.9 1.6 2.0 MHz

SLEEP Rising to Oscillator S table (Note 26) - - 20 - ms

RST Pulse Width trst 150 - - ns

RST to STBY Falling tdrrs - 100 - ns

RST Rising to STBY Rising tcal - 2,882,040 - tclk

CH1/2 Edge to TRK1, TRK2 Rising (Note 27) tdrsh1 -80-ns

CH1/2 Edge to TRK1, TRK2 Falling (Note 27) tdfsh4 - - 68tclk+260 ns

HOLD to SSH Falling (Note 28) t dfsh2 -60 ns

HOLD to TRK1, TRK2, Falling (Note 28) t dfsh1 66tclk - 68tclk+260 ns

HOLD to TRK1, TRK2, SSH Rising (Note 28) tdrsh - 120 - ns

HOLD Pulse W idth (Note 29) thold 1tclk+20 - 63tclk ns

HOLD to CH1/2 E dge (Note 28) tdhlri 15 - 64tclk ns

HOLD Falling to CLKIN Falling (Note 29) thcf 55 - 1tclk+10 ns

Note: 24. Minimum CLKIN per iod is 0.625 µs in FRN mode (20 kHz sample rate). A t temperatures >+85 °C,

and with clock frequencies <1.6 MHz, analog per formance may be degraded.

25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency

is 1.6 MHz in FRN mode (20 kHz sample rate).

26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 M Ω parallel resistor (see Figure 8).

27. These times are for FRN mode.

28. SSH only works correctly if HOLD falling edge is wi thin +15 to +30 ns of CH1/2 edge or if CH1/2 edge

occurs after HOLD r ises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes.

29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must

be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN

after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse wi dth may be as

narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This

ensures that the HOLD pulse will meet the minimum specifi cation for thcf.

CS5102A

DS45F2 7

dhlri

hold

CH1/2

HOLD

CLKIN

hcf

HOLD

rst

cal

drrs

RST

STBY

dfsh4

CH1/2

drsh1

HOLD

SSH,TRK1,TRK2

dfsh2

drsh

dfsh1

TRK1,TRK2

SSH/SDL

Control Output Timing

Reset and Calibration Timing

Channel Selection Timing

a. FRN Mode b. PDT, RBT Mode

Start Conversion Timing

CS5101A CS5102A

8DS45F2

SWITCHING CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Units

PDT and RBT Modes

SCLK Input Pulse Period tsclk 200 - - ns

SCLK Input Pulse Width Low tsclkl 50 - - ns

SCLK Input Pulse Width High tsclkh 50 - - ns

SCLK Input Falli ng to SDATA Vali d tdss - 100 150 ns

HOLD Falling to SDATA Valid PDT Mode tdhs - 140 230 ns

TRK1, TRK2 Falling to SDATA Valid (Note 30) tdts - 65 125 ns

FRN and SSC Modes

SCLK Output P ulse Width Low tslkl -2t

clk -t

clk

SCLK Output P ulse Width High tslkh -2t

clk -t

clk

SDATA Valid Before Rising SCLK tss 2tclk-100 - - ns

SDATA Valid After Rising SCLK tsh 2tclk-100 - - ns

SDL Falling to 1st Rising SCLK trsclk -2t

clk -ns

Last Rising SCLK to SDL Rising CS5101A

CS5102A trsdl

trsdl -

-2tclk

2tclk 2tclk+165

2tclk+200 ns

HOLD Falling to 1st Falling SCLK CS5101A

CS5102A thfs

thfs 6tclk

6tclk -

-8tclk+165

8tclk+200 ns

CH1/2 Edge to 1st Falling SCLK t chfs -7tclk-t

clk

Note: 30. Only valid for TRK 1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then

SDATA is valid tdss time after the next fall ing SCLK.

DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-,

VD- = 5V ± 10%)

Parameter Symbol Min Typ Max Units

Calibration Memory Retention (Note 31)

Power Supply Voltage VA+ and VD+ VMR 2.0 - - V

High-Level Input Voltage VIH 2.0 - - V

Low-Level Input Voltage VIL --0.8V

High-Level Output V oltage (Note 32) VOH (VD+)-1.0 - - V

Low-Level Output Voltage IOUT = 1.6 mA VOL --0.4V

Input Leakage Current Iin --10

µA

Digital Output Pin Capacitance Cout -9-pF

Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be

allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+.

This parameter is guaranteed by characterization.

32. IOUT = -100 µA. This specifi cation guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA).

CS5101A CS5102A

DS45F2 9

sclkl

sclkh

dss

SDATA

SCLK

MSB

dhs

HOLD

SDATA MSB

SDATA

dts

sclk

dss

MSB-1

SCLK

TRK1, TRK2

MSB

SCLK

SDATA

slkh

slkl

dss

chfs

CH1/2

HOLD

hfs

SSH/SDL

rsclk

LSB

rsdl

Data T ransmission Timing

a. SCLK input (RBT and PDT mode) b. SCLK output (SSC and FRN modes)

a. Pipelined Data Transmission (PDT ) b. Register Burst T ransmission (RBT) Mode

Serial Data Timing

CS5101A CS5102A

10 DS45F2

Notes: 35. In addition, VD+ must not be greater than (VA +) +0.3V

36. Transient currents of up to 100 mA will not cause S CR latch-up.

*WARNING: Operation beyond these limits may result i n permanent damage to the device.

Notes: 33. All voltages with respect to ground.

34. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They

will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar

mode and -VREF in bi polar mode, with binary coding (CODE = l ow).

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 33)

Parameter Symbol Min Typ Max Units

DC Power Supplies : Positive Digital

Negative Digital

Positiv e Analog

Negative Analog

VD+

VD-

VA+

VA-

4.5

-4.5

4.5

-4.5

5.0

-5.0

5.0

-5.0

VA+

-5.5

5.5

-5.5

Analog Reference Voltage VREF 2.5 4.5 (VA+)-0.5 V

Analog Input Voltage: (Note 34)

Unipolar

Bipolar VAIN

VAIN AGND

-VREF -

-VREF

VREF V

ABSOLUTE MAXIMUM RATINGS* (AGND, DGND = 0V, all voltages with respect to ground)

Parameter Symbol Min Typ Max Units

DC Power Supplies : Positive Digital (Note 35)

Negative Digital

Positiv e Analog

Negative Analog

VD+

VD-

VA+

VA-

-0.3

0.3

-0.3

0.3

6.0

-6.0

6.0

-6.0

Input Current, Any Pin Except Supplies (Note 36) Iin --

±10 mA

Analog Input Vol tage (AIN and V REF pins) VINA (VA-)-0.3 - (VA+)+0.3 V

Digital Input Voltage VIND -0.3 - (VA+)+0.3 V

Ambient Operating Temperature TA-55 - 125 °C

Storage Temperature Tstg -65 - 150 °C

Ambient Operating Temperature TA-55 - 125 °C

Storage Temperature Tstg -65 - 150 °C

CS5101A CS5102A

DS45F2 11

GENERAL DESCRIPTION

The CS5101A and CS5102A are 2-channel, 16-

bit A/D converters. The devices include an

inherent sample/hold and an on-chip analog

switch for 2-channel operation. Both channels

can thus be sampled and converted at rates up to

50 kHz each (CS5101A) or 10 kHz each

(CS5102A). Alternatively, each of the devices

can be operated as a single channel ADC operat-

ing at 100 kHz (CS5101A) or 20 kHz

(CS5102A).

Both the CS5101A and CS5102A can be config-

ured to accept either unipolar or bipolar input

ranges, and data is output serially in either binary

or 2’s complement coding. The devices can be

configured in 3 different output modes, as well as

an internal, synchronous loopback mode. The

CS5101A and CS5102A provide coarse

charge/fine charge control, to allow accurate

tracking of high-slew signals.

THEORY OF OPERATION

The CS5101A and CS5102A implement the suc-

cessive approximation algorithm using a charge

redistribution architecture. Instead of the tradi-

tional resistor network, the DAC is an array of

binary-weighted capacitors. All capacitors in the

array share a common node at the comparator’s

input. As shown in Figure 1, their other terminals

are capable of being connected to AGND, VREF,

or AIN (1 or 2). When the device is not calibrat-

ing or converting, all capacitors are tied to AIN.

Switch S1 is closed and the charge on the array,

tracks the input signal.

When the conversion command is issued, switch

S1 opens. This traps the charge on the compara-

tor side of the capacitor array and creates a

floating node at the comparator’s input. The con-

version algorithm operates on this fixed charge,

and the signal at the analog input pin is ignored.

In effect, the entire DAC capacitor array serves

as analog memory during conversion much like a

hold capacitor in a sample/hold amplifier.

The conversion consists of manipulating the free

plates of the capacitor array to VREF and AGND

to form a capacitive divider. Since the charge at

the floating node remains fixed, the voltage at

that point depends on the proportion of capaci-

tance tied to VREF versus AGND. The

successive-approximation algorithm is used to

find the proportion of capacitance, which when

connected to the reference will drive the voltage

at the floating node to zero. That binary fraction

of capacitance represents the converter’s digital

output.

AIN

C/2 C/32,768

MSB LSB

Bit 15 Bit 14 Bit 13 Bit 0

C = C + C/2 + C/4 + C/8 + ... C/32,768

tot

Dummy

C/32,768 S1

C/4

Fine

VREF

AGND

Coarse

Fine

Coarse

Fine

Figure 1. Coarse Charge Input B uffers and Charge Redistribution DAC

CS5101A CS5102A

12 DS45F2

Calibration

The ability of the CS5101A or the CS5102A to

convert accurately to 16-bits clearly depends on

the accuracy of its comparator and DAC. Each

device utilizes an "auto-zeroing" scheme to null

errors introduced by the comparator. All offsets

are stored on the capacitor array while in the

track mode and are effectively subtracted from

the input signal when a conversion is initiated.

Auto-zeroing enhances power supply rejection at

frequencies well below th e conversion rate.

To achieve 16-bit accuracy from the DAC, the

CS5101A and CS5102A use a novel self-calibra-

tion scheme. Each bit capacitor shown in

Figure 1 actually consists of several capacitors in

parallel which can be manipulated to adjust the

overall bit weight. An on-chip micro controller

precisely adjusts each capacitor with a resolution

of 18 bits.

The CS5101A and CS5102A should be reset

upon power-up, thus initiating a calibration cycle.

The device then stores its calibration coefficients

in on-chip SRAM. When the CS5101A and

CS5102A are in power-down mode (SLEEP

low), they retain the calibration coefficients in

memory, and need not be recalibrated when nor-

mal operation is resumed.

OPERATION OVERVIEW

Monolithic design and inherent sampling archi-

tecture make the CS5101A and CS5102A

extremely easy to use.

Initiating Conversions

A falling transition on the HOLD pin places the

input in the hold mode and initiates a conversion

cycle. The charge is trapped on the capacitor ar-

ray the instant HOLD goes low. The device will

complete conversion of the sample within 66

master clock cycles, then automatically return to

the track mode. After allowing a short time for

acquisition, the device will be ready for another

conversion.

In contrast to systems with separate track-and-

holds and A/D converters, a sampling clock can

simply be connected to the HOLD input. The

duty cycle of th is clock is not critical. The HOLD

input is latched internally by the master clock, so

it need only remain low for 1/fclk + 20 ns, but no

longer than the minimum conversion time minus

two master clocks or an additional conversion cy-

cle will be initiated with inadequate time for

acquisition. In Free Run mode, SCKMOD =

OUTMOD = 0, the device will convert at a rate

of CLKIN/80, and the HOLD input is ignored.

As with any high-resolution A-to-D system, it is

recommended that sampling is synchronized to

the master system clock in order to minimize the

effects of clock feedthrough. However, the

CS5101A and CS5102A may be operated entirely

asynch ronous to the master clock if necessary.

Tracking the Input

Upon completing a conversion cycle the

CS5101A and CS5102A immediately return to

the track mode. The CH1/2 pin directly controls

the input switch, and therefore directly deter-

mines which channel will be tracked. Ideally, the

CH1/2 pin should be switched during the conver-

sion cycle, thereby nullifying the input mux

switching time, and guaranteeing a stable input at

the start of acquisition. If, however, the CH1/2

control is changed during the acquisition phase,

adequate coarse charge and fine charge time must

be allowed before initiating conversion.

When the CS5101A or the CS5102A enters track-

ing mode, it uses an internal input buffer

amplifier to provide the bulk of the charge on the

capacitor array (coarse-charge), thereby reducing

the current load on the external analog circuitry.

Coarse-charge is internally initiated for 6 clock

cycles at the end of every conversion. The buffer

CS5101A CS5102A

DS45F2 13

amplifier is then bypassed, and the capacitor ar-

ray is directly connected to the input. This is

referred to as fine-charge, during which the

charge on the array is allowed to accurately settle

to the input voltage (see Figure 10).

With a full scale input step, the coarse-charge in-

put buffer of the CS5101A will charge the

capacitor array within 1% in 650 ns. The con-

verter timing allows 6 clock cycles for coarse

charge settling time. When the CS5101A

switches to fine-charge mode, its slew rate is

somewhat reduced. In fine-charge, the CS5101A

can slew at 2 V/µs in unipolar mode. In bipolar

mode, only half the capacitor array is connected

to the analog input, so the CS5101A can slew at

4V/µs.

With a full scale input step, the coarse-charge in-

put buffer of the CS5102A will charge the

capacitor array within 1% in 3.75 µs. The con-

verter timing allows 6 clock cycles for coarse

charge settling time. When in fine-charge mode,

the CS5102A can slew at 0.4 V/µs in unipolar

mode; an d at 0.8 V/µs in bipolar mode.

Acquisition of fast slewing signals can be has-

tened if the voltage change occurs during or

immediately following the conversion cycle. For

instance, in multiple channel applications (using

either the device’s internal channel selector or an

external MUX), channel selection should occur

while the CS5101A or the CS5102A is convert-

ing. Multiplexer switching and settling time is

thereby removed from the overall throughput

equation.

If the input signal changes drastically during the

acquisition period (such as changing the signal

source), the device should be in coarse-charge for

an adequate period following the change. The

CS5101A and CS5102A can be forced into

coarse-charge by bringing CRS/FIN high. The

buffer amplifier is engaged when CRS/FIN is

high, and may be switched in any number of

times during tracking. If CRS/FIN is held low,

the CS5101A and CS5102A will only coarse-

charge for the first 6 clock cycles following a

conversion, and will stay in fine-charge until

HOLD goes low. To get an accurate sample using

the CS5101A, at least 750 ns of coarse-charge,

followed by 1.125 µs of fine-charge is required

before initiating a conversion. If coarse charge is

not invoked, then up to 25 µs should be allowed

after a step change input for proper acquisition.

To get an accurate sample using the CS5102A, at

least 3.75 µs of coarse-charge, followed by

5.625 µs of fine-charge is required before initiat-

ing a conversion (see Figure 2). If coarse charge

is not invoked, then up to 125 µs should be al-

lowed after a step change input for proper

acquisition. The CRS/FIN pin must be low prior

to HOLD becoming active and be held low dur-

ing conversion.

Master Clock

The CS5101A and CS5102A can operate either

from an externally-supplied master clock, or from

their own crystal oscillator (with a crystal). To

enable the internal crystal oscillator, simply tie a

crystal across the XOUT and CLKIN pins and

add 2 capacitors and a resistor, as shown on the

system connec tion diag ram in F igure 8.

Calibration and conversion times directly scale to

the master clock frequency. The CS5101A-8 can

operate with clock or crystal frequencies up to

9.216 MHz (8.0 MHz in FRN mo de). This allows

maximum throughput of up to 50 kHz per chan-

nel in dual-channel operation, or 100 kHz in a

single channel configuration. The CS5101A-16

can accept a maximum clock speed of 4 MHz,

with corresponding throughput of 50 kHz. The

CS5102A can operate with clock or crystal frequen-

cies up to 2.0 MHz (1.6 MHz in FRN mode). This

allows maximum throughput of up to 10 kHz per

channel in dual-channel operation, or 20 kHz in a

single channel configuration. For 16 bit performance

a 1.6 MHz clock is recommended. This 1.6 MHz

CS5101A CS5102A

14 DS45F2

clock yields a maximum throughput of 20 kHz in

a single channel configu ration.

Asynchronous Sampling Considerations

When HOLD goes low, the analog sample is cap-

tured immediately. The HOLD signal is latched

by the next falling edge of CLKIN, and conver-

sion then starts on the subsequent rising edge. If

HOLD is asynchronous to CLKIN, then there

will be a 1.5 CLKIN cycle uncertainty as to when

conversion starts. Considering the CS5101A with an

8 MHz CLKIN, with a 100 kHz HOLD signal, then

this 1.5 CLKIN uncertainty will result in a 1.5

CLKIN period possible reduction in fine charge time

for the ne xt conv ersion .

This reduced fine charge time will be less than

the minimum specification. If the CLKIN fre-

quency is increased slightly (for example, to

8.192 MHz) then sufficient fine charge time will

always occur. The maximum frequency for

CLKIN is specified at 9.216 MHz; it is recom-

mended that for asynchronous operation at

100 kHz, CLKIN should be between 8.192 MHz

and 9.216 MHz.

Analog Input Range/Coding Format

The reference voltage directly defines the input

voltage range in both the unipolar and bipolar

configurations. In the unipolar configuration

(BP/UP low), the first code transition occurs 0.5

LSB above AGND, and the final code transition

occurs 1.5 LSB’s below VREF. In the bipolar

configuration (BP/UP high), the first code transi-

tion occurs 0.5 LSB above -VREF and the last

transition occurs 1.5 LSB’s below +VREF.

The CS5101A and CS5102A can output data in

either 2’s complement, or binary format. If the

CODE pin is high, the output is in 2’s comple-

ment format with a range of -32,768 to +32,767.

If the CODE pin is low, the output is in binary

format with a range of 0 to +65,535. See Table 1

for output coding.

CLKIN

CRS/FIN

Internal

Status Conv. Coarse Fine Chg. Coarse Fine Chg. Conv.

TRK1 or

TRK2

HOLD

Min: 1.125

6 clk

2 clk

Min: 750 ns*

3.75

s**

5.625

s**

* Applies to 5101A

** Applies to 5102A

Figure 2. Coarse-Charge/Fine-Charge Control

Unipolar Input

Voltage Offset

Binary Two’s

Complement Bipolar Input

Voltage

>(VREF- 1.5 LSB) FFFF 7FFF >( VREF-1.5 LSB)

VREF-1.5 LSB FFFF

FFFE 7FFF

7FFE VREF-1.5 LSB

VREF/2-0.5 LSB 8000

7FFF 0000

FFFF -0.5 LSB

+0.5 LSB 0001

0000 8001

8000 -VREF+0.5 LSB

<(+0.5 LSB) 0000 8000 <(-VR EF+0.5 LSB)

Table 1. Output Coding

CS5101A CS5102A

DS45F2 15

Output Mode Control

The CS5101A and CS5102A can be configured

in three different output modes, as well as an in-

ternal, synchronous loop-back mode. This allows

great flexibility for design into a wide variety of

systems. The operating mode is selected by set-

ting the states of the SCKMOD and OUTMOD

pins. In all modes, data is output on SDATA,

starting with the MSB. Each subsequent data bit

is updated on the falling edge of SCLK.

When SCKMOD is high, SCLK is an input, al-

lowing the data to be clocked out with an

external serial clock at rates up to 5 MHz. Addi-

tional clock edges after #16 will clock out logic

’1’s on SDATA. Tying SCKMOD low reconfig-

ures SCLK as an output, and the converter clocks

out each bit as it’s determined during the conver-

sion process, at a rate of 1/4 the master clock

speed. Table 2 shows an overview of the different

states of SCKMOD and OUTMOD, and the cor-

responding output modes.

Pipelined Data Transmission (PDT)

PDT mode is selected by tying both SCKMOD

and OUTMOD high. In PDT mode, the SCLK

pin is an input. Data is registered during conver-

sion, and output during the following conversion

cycle. HOLD must be brought low, initiating an-

other conversion, before data from the previous

conversion is available on SDATA. If all the data

has not been clocked out before the next falling

edge of HOLD, the old data will be lost

(Figure 3).

Figure 3. Pipelined Data Transmission Mode (PDT)

CLKIN (i)

HOLD (i)

Internal

Status

SCLK (i)

SDATA (o)

CH1/2 (i)

D15 D14

D0 (Ch. 1)

TRK1 (o)

TRK2 (o)

SSH/SDL (o)

Converting Ch. 2

D15 D14

D0 (Ch. 2)

Converting Ch. 1

D15

68 72 760 4 8 64687276 4 8

60 6000

Tracking Ch . 1 Tracking Ch. 2

SCLK

Input

Output

Input

Output

OUTMOD

SCKMOD

MODE

PDT

RBT

SSC

FRN

Input

Output

CH1/2

Input

HOLD

Table 2. Serial Output M odes

CS5101A CS5102A

16 DS45F2

D15 D14 D1 D0 (Ch. 1)

CLKIN (i)

HOLD (i)

Internal

Status

SCLK (o)

SDATA (o)

CH1/2 (i)

D15 D14 D1 D0 (Ch. 2)

TRK1 (o)

TRK2 (o)

SSH/SDL (o)

72 76048

8640

Converting C h. 2 Tracking Ch. 1 Converting C h. 1 Tracking Ch. 2

CLKIN (i)

HOLD (i)

Internal

Status

SCLK (i)

SDATA (o)

CH1/2 (i)

TRK1 (o)

TRK2 (o)

SSH/SDL (o)

Convert ing Ch. 2 Converting Ch. 1

D0 D0

Chan nel 2 Da ta Channel 1 Data

04 40

68 72

Tracking Ch. 1 Tracking Ch. 2

CLKIN (i)

D15 D1 D0 (Ch. 1)

Internal

Status

SCLK (o)

SDATA (o)

CH1/2 ( o)

D15 D1 D0 (Ch. 2)

TRK1 (o)

TRK2 (o)

SSH/SDL (o)

72 76048

76 4 8 640

7 69 7

Converting Ch. 2 Tracking Ch. 1 Conver t ing C h. 1 Tracking Ch. 2

Figure 5. Synchronous Self-Clocking Mode (SSC)

Figure 4. Registered Burst Transmission Mode (RBT)

Figure 6. Free Run Mode (FRN)

CS5101A CS5102A

DS45F2 17

Registered Burst Transmission (RBT)

RBT mode is selected by tying SCKMOD high,

and OUTMOD low. As in PDT mode, SCLK is

an input, however data is available immediately

following conversion, and may be clocked out

the moment TRK1 or TRK2 falls. The falling

edge of HOLD clears the output buffer, so any

unread data will be lost. A new conversion may

be initiated before all the data has been clocked

out if the unread data bits are not important

(Figure 4).

Synchronous Self-Clocking (SSC)

SSC mode is selected by tying SCKMOD low,

and OUTMOD high. In SSC mode, SCLK is an

output, and will clock out each bit of the data as

it’s being converted. SCLK will remain high be-

tween conversions, and run at a rate of 1/4 the

master clock speed for 16 low pulses during con-

version (Figure 5).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN

cycles after the last rising edge of SCLK. This

signal frames the 16 data bits and is useful for

interfacing to shift registers (e.g. 74HC595) or to

DSP serial ports.

Free Run (FRN)

Free Run is the internal, synchronous loopback

mode. FRN mode is selected by tying SCKMOD

and OUTMOD low. SCLK is an output, and op-

erates exactly the same as in the SSC mode. In

Free Run mode, the converter initiates a new

conversion every 80 master clock cycles, and al-

ternates between channel 1 and channel 2. HOLD

is disabled, and should be tied to either VD+ or

DGND. CH1/2 is an output, and will change at

the start of each new conversion cycle, indicating

which channel will be tracked after the current

conversion is finished (Figure 6).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN

cycles after the last rising edge of SCLK. This

signal frames the 16 data bits and is useful for

interfacing to shift registers (e.g. 74HC595) or to

DSP serial ports.

SYSTEM DESIGN WITH THE CS5101A

AND CS5102A

Figure 7 shows a general system connection dia-

gram f or the CS5101 A an d CS5102A.

Digital Circuit Connections

When TTL loads are utilized the potential for

crosstalk between digital and analog sections of

the system is increased. This crosstalk is due to

high digital supply and signal currents arising

from the TTL drive current required of each digi-

tal output. Connecting CMOS logic to the digital

outputs is recommended. Suitable logic families

include 4000B, 74HC, 74AC, 74ACT, and

74HCT.

System Initialization

Upon power up, the CS5101A and CS5102A

must be reset to guarantee a consistent starting

condition and initially calibrate the device. Due

to each device’s low power dissipation and low

temperature drift, no warm-up time is required

before reset to accommodate any self-heating ef-

fects. However, the voltage reference input

should have stabilized to within 0.25% of its final

value before RST rises to guarantee an accurate

calibration. Later, the CS5101A and CS5102A

may be reset at any time to initiate a single full

calibration.

When RST is brought low all internal logic

clears. When RST returns high on the CS5101A,

a calibration cycle begins which takes 11,528,160

master clock cycles to complete (approximately

1.4 seconds with an 8 MHz master clock). The

CS5101A CS5102A

18 DS45F2

calibration cycle on the CS5102A takes

2,882,040 master clock cycles to complete (ap-

proximately 1.8 seconds with a 1.6 MHz master

clock). The CS5101A’s and CS5102A’s STBY

output remains low throughout the calibration se-

quence, and a rising transition indicates the

device is ready for normal operation. While cali-

brating, the CS5101A and CS5102A will ignore

changes on the HOLD input.

To perform the reset function, a simple power-on

reset circuit can be built using a resistor and ca-

pacitor as shown in Figure 8. The resistor should

be less than or equal to 10 kΩ. The system po wer

supplies, voltage reference, and clock should all

be established prior RST rising.

Single-Channel Operation

The CS5101A and CS5102A can alternatively be

used to sample one channel by tying the CH1/2

input high or low. The unused AIN pin should be

tied to the analog input signal or to AGND. (If

operating in free run mode, AIN1 and AIN2 must

VA+ VD+

+5VA +

4.7

F 0.1

F0.1

23 1

-5VA

4.7

F 0.1

F0.1

0.1

VA- VD-

REFBUF

25 7

CLKIN

XOUT

DGND

SLEEP

STBY

TRK1

TRK2

SSH/SDL

SDATA

RST

CH1/2

SCLK

HOLD

10 M

EXT

CLOCK

C2 = C1

Data

Interface

Control

Logic

CRS/FIN

CODE

SCKMOD

OUTMOD

BP/UP

VD+

Mode Co n t rol

AIN1

AIN2

1 nF

Analog

Sources

VREF

AGND

Voltage Reference

* For best dynamic

S/(N+D) performance.

NPO

Unused Logic inputs should

be tied to VD+ or DGND.

CS5101A

CS5102A

XTAL

XTAL & C1 Table

CS5101A

FRN

CS5102A

FRN

XTAL

8.0 MHz

8.192 M Hz

1.6 MHz

C1, C2

10 pF

30 pF

2.0 MHz

1.6 MHz

TST

PD T, RBT,

SSC

PD T, RBT,

SSC

Figure 7. CS5101A/CS5102A System Connection Diagram

CS5101A CS5102A

DS45F2 19

be tied to the same source, as CH1/2 is reconfig-

ured as an output.)

ANALOG CIRCUIT CONNECTIONS

Most popular successive approximation A/D con-

verters generate dynamic loads at their analog

connections. The CS5101A and CS5102A inter-

nally buffer all analog inputs (AIN1, AIN2,

VREF, and AGND) to ease the demands placed

on external circuitry. However, accurate system

operation still requires careful attention to details

at the design stage regarding source impedances

as well as grounding and decoupling schemes.

Reference Considerations

An application note titled "Voltage References for

the CS501X Series of A/D Converters" is avail-

able for the CS5101A and CS5102A. In addition to

working through a reference circuit design example,

it offers several built-and-tested reference circuits.

During conversion, each capacitor of the cali-

brated capacitor array is switched between VREF

and AGND in a manner determined by the suc-

cessive-approximation algorithm. The charging

and discharging of the array results in a current

load at the reference. The CS5101A and

CS5102A each include an internal buffer ampli-

fier to minimize the external reference circuit’s

drive requirement and preserve the reference’s in-

tegrity. Whenever the array is switched during

conversion, the buffer is used to coarse-charge

the array thereby providing the bulk of the neces-

sary charge. The appropriate array capacitors are

then switched to the unbuffered VREF pin to avoid

any errors due to offsets and/or noise in the buffer.

The external reference circuitry need only pro-

vide the residual charge required to fully charge

the array after coarse-charging from the buffer.

This creates an ac current load as the CS5101A

and CS5102A sequence through conversions. The

reference circuitry must have a low enough out-

put impedance to drive the requisite current

without changing its output voltage significantly.

As the analog input signal varies, the switching

sequence of the internal capacitor array changes.

The current load on the external reference cir-

cuitry thus varies in response with the analog

input. Therefore, the external reference must not

exhibit significant peaking in its output imped-

ance characteristic at signal frequencies or their

harmonics.

A large capacitor connected between VREF and

AGND can provide sufficiently low output im-

pedance at the high end of the frequency

spectrum, while almost all precision references

exhibit extremely low output impedance at dc.

The presence of large capacitors on the output of

some voltage references, however, may cause

peaking in the output impedance at intermediate

frequencies. Care should be exercised to ensure

that significant peaking does not exist or that

some form of compensation is provided to elimi-

nate the effe ct.

The magnitude of the current load on the external

reference circuitry will scale to the master clock

frequency. At the full-rated 9.216 MHz clock

(CS5101A), the reference must supply a maxi-

mum load current of 20 µA peak-to-peak (2 µA

typical). An output impedance of 2 Ω will there-

fore yield a maximum error of 40 µV. At the

full-rated 2.0 MHz clock (CS5102A), the refer-

+5V

1N4148

CS5102A

CS5101A

VD+

RST

____

Figure 8. Power-up Reset Circuit

CS5101A CS5102A

20 DS45F2

ence must supply a maximum load current of

5 µA peak-to-peak (0.5 µA typical). An output

impedance of 2 Ω will therefore yield a maxi-

mum error of 10.0 µV. With a 4.5 V reference and

LSB size of 138 µV this would insure approxi-

mately 1/14 LSB accuracy. A 10 µF capacitor

exhibits an impedance of less than 2 Ω at fre-

quencies greater than 16 kHz. A high-quality

tantalum capacitor in parallel with a smaller ce-

ramic capacitor is recommended.

Peaking in the reference’s output impedance can

occur because of capacitive loading at its output.

Any peaking that might occur can be reduced by

placing a small resistor in series with the capaci-

tors. The equation in Figure 9 can be used to help

calculate the optimum value of R for a particular

reference. The term "fpeak" is the frequency of

the peak in the output impedance of the reference

before the resistor is added.

The CS5101A and CS5102A can operate with a

wide range of reference voltages, but signal-to-

noise performance is maximized by using as

wide a signal range as possible. The recom-

mended reference voltage is 4.5 volts. The

CS5101A and CS5102A can actually accept ref-

erence voltages up to the positive analog supply.

However, the buffer’s offset may increase as the

reference voltage approaches VA+ thereby in-

creasing external drive requirements at VREF. A

4.5V reference is the maximum reference voltage

recommended. This allows 0.5V headroom for

the internal reference buffer. Also, the buffer en-

lists the aid of an external 0.1 µF ceramic

capacitor which must be tied between its output,

REFBUF, and the negative analog supply, VA-.

For more information on references, consult "Ap-

plication Note: Voltage References for the

CS501X Series of A/D Con verters".

Analog Input Connection

The analog input terminal functions similarly to

the VREF input after each conversion when

switching into the track mode. During the first

six master clock cycles in the track mode, the

buffered version of the analog input is used for

coarse-charging the capacitor array. An additional

period is required for fine-charging directly from

AIN to obtain the specified accuracy. Figure 10

shows this operation. During coarse-charge the

charge on the capacitor array first settles to the

buffered version of the analog input. This voltage

may be offset from the actual input voltage. Dur-

ing fine-charge, the charge then settles to the

accurate unbuffered version.

VREF

REFBUF

VA-

0.1

-5V

0.01

CS5101A

CS5102A

ref

Figure 9. Reference Connections

R= 1

(C1 + C2) fpeak

Acquisition Time (us)

Internal Charge Error (LSB’s)

+200

-100

-400

+100

-200

-300

Fine-ChargeCoarse-Charge

0.25 0.5 0.75 1.0

1.0

2.0 3.0 4.0

8 MHz Clock

2.0 MHz Clock

Figure 10. Charge Settling Time

(8 and 2.0 MHz Cl ocks)

CS5101A CS5102A

DS45F2 21

Fine-charge settling is specified as a maximum of

1.125 µs (CS5101A) or 5.625 µs (CS5102A) for

an analog source impedance of less than 50 Ω. In

addition, the comparator requires a source imped-

ance of less than 400 Ω around 2 MHz for

stability. The source impedance can be effectively

reduced at high frequencies by adding capaci-

tance from AIN to ground (typically 200 pF).

However, high dc source resistances will increase

the input’s RC time constant and extend the nec-

essary acquisition time. For more information on

input amplifiers, consult the application note:

Buffer Amplifiers for the CS501X Series of A/D

Converters.

SLEEP Mode Operation

The CS5101A and CS5102A include a SLEEP

pin. When SLEEP is active (low) each device

will dissipate very low power to retain its calibra-

tion memory when the device is not sampling. It

does not require calibration after SLEEP is made

inactive (high). When coming out of SLEEP,

sampling can begin as soon as the oscillator starts

(time will depend on the particular oscillator

components) and the REFBUF capacitor is

charged (which takes about 3 ms for the

CS5101A, 50 ms for the CS5102A). To achieve

minimum start-up time, use an external clock and

leave the voltage reference powered-up. Connect

a resistor (2 kΩ) between pins 20 and 21 to keep

the REFBUF capacitor charged. Conversion can

then begin as soon as the A/D circuitry has stabi-

lized and performed a track cycle.

To retain calibration memory while SLEEP is ac-

tive (low) VA+ and VD+ must be maintained at

greater than 2.0V. VA- and VD- can be allowed

to go to 0 volts. The voltages into VA- and VD-

cannot just be "shut-off" as these pins cannot be

allowed to float to potentials greater than

AGND/DGND. If the supply voltages to VA- and

VD- are removed, use a transistor switch to short

these to the power supply ground while in

SLEEP mode.

Grounding and Power Supply Decoupling

The CS5101A and CS5102A use the analog

ground connection, AGND, only as a reference

voltage. No dc power currents flow through the

AGND connection, and it is completely inde-

pendent of DGND. However, any noise riding on

the AGND input relative to the system’s analog

ground will induce conversion errors. Therefore,

both the analog input and reference voltage

should be referred to the AGND pin, which

should be used as the entire system’s analog

ground reference.

The digital and analog supplies are isolated

within the CS5101A and CS5102A and are

pinned out separately to minimize coupling be-

tween the analog and digital sections of the chip.

All four supplies should be decoupled to their re-

spective grounds using 0.1 µF ceramic capacitors.

If significant low-frequency noise is present on

the supplies, tantalum capacitors are recom-

mended in p arallel with the 0.1 µF capacito rs.

The positive digital power supply of the

CS5101A and CS5102A must never exceed the

positive analog supply by more than a diode drop

or the CS5101A and CS5102A could experience

permanent damage. If the two supplies are de-

rived from separate sources, care must be taken

that the analog supply comes up first at power-

up. The system connection diagram (Figure 7)

shows a decoupling scheme which allows the

CS5101A and CS5102A to be powered from a

single set of ± 5V rails. The positive digital sup-

ply is derived from the analog supply through a

10 Ω resistor to avoid the analog supply dropping

below the digital supply. If this scheme is util-

ized, care must be taken to insure that any digital

load currents (wh ich flow through the 10 Ω resis-

tors) do not cause the magnitude of digital

supplies to drop below the analog supplies by

more than 0.5 volts. Digital supplies must always

remain above the minimum specification.

CS5101A CS5102A

22 DS45F2

As with any high-precision A/D converter, the

CS5101A and CS5102A require careful attention

to grounding and layout arrangements. However,

no unique layout issues must be addressed to

properly apply the devices. The CDB5101A

evaluation board is available for the CS5101A,

and the CDB5102A evaluation board is available

for the CS5102A. The availability of these boards

avoids the need to design, build, and debug a

high-precision PC board to initially characterize

the part. Each board comes with a socketed

CS5101A or CS5102A, and can be reconfigured

to simulate any combination of sampling, calibra-

tion, master clock, and analog input range

conditions.

CS5101A AND CS5102A PERFORMANCE

Differential Nonlinearity

The self-calibration scheme utilized in the

CS5101A and CS5102A features a calibration

resolution of 1/4 LSB, or 18-bits. This ideally

yields DNL of ±1/4 LSB, with code widths rang-

ing from 3/4 to 5/4 LSB’s.

Traditional laser trimmed ADC’s have significant

differential nonlinearities. Appearing as wide and

narrow codes, DNL often causes entire sections

of the transfer function to be missing. Although

their affect is minor on S/(N+D) with high ampli-

tude signals, DNL errors dominate performance

with low-level signals. For instance, a signal 80

dB below full-scale will slew past only 6 or 7

codes. Half of those codes could be missing with

a conventional 16-bit ADC which achieves only

14-bit DNL.

The most common source of DNL errors in con-

ventional ADC’s is bit weight errors. These can

arise due to accuracy limitations in factory trim

stations, thermal or physical stresses after calibra-

tion, and/or drifts due to aging or temperature

variations in the field. Bit-weight errors have a

drastic effect on a converter’s ac performance.

They can be analyzed as step functions superim-

posed on the input signal. Since bits (and their

errors) switch in and out throughout the transfer

curve, their effect is signal dependent. That is,

harmonic and intermodulation distortion, as well

as noise, can vary with different input conditions.

Differential nonlinearities in successive-approxi-

mation ADC’s also arise due to dynamic errors in

the comparator. Such errors can dominate if the

converter’s throughput/sampling rate is too high.

The comparator will not be allowed sufficient

time to settle during each bit decision in the suc-

cessive-approximation algorithm. The worst-case

codes for dynamic errors are the major transitions

(1/2 FS; 1/4, 3/4 FS; etc.). Since DNL effects are

most critical with low-level signals, the codes

around mid-scale (1/2 FS) are most important.

Yet those codes are worst-case for dynamic DNL

errors!

With all linearity calibration performed on-chip

to 18-bits, the CS5101A and CS5102A maintain

accurate bit weights. DNL errors are dominated

by residual calibration errors of ±1/4 LSB rather

than dynamic errors in the comparator. Further-

more, all DNL effects on S/(N+D) are buried by

white broadband noise. (See Figures 17 and 19).

Figure 11 illustrates the DNL histogram plot of a

typical CS5101A at 25°C. Figure 12 illustrates

the DNL of the CS5101A at 138°C ambient after

calibration at 25°C ambient. Figures 13 and 14

illustrate the DNL of the CS5102A at 25°C and

138°C ambient, respectively. A histogram test is a

statistical method of deriving an A/D converter’s

differential nonlinearity. A ramp is input to the

A/D and a large number of samples are taken to

insure a high confidence level in the test’s result.

The number of occurrences for each code is

monitored and stored. A perfect A/D converter

would have all codes of equal size and therefore

equal numbers of occurrences. In the histogram

test a code with the average number of occur-

rences will be considered ideal (DNL = 0). A

CS5101A CS5102A

DS45F2 23

0 65,535

32,768

DNL (LSB)

-1

+1/2

-1/2

TA = 25°C

065,535

Codes

32,768

DNL (LSB)

-1

+1/2

-1/2

TA = 138 °C, CAL @ 25 °C

065,535

Codes

32,768

DNL (LSB)

-1

+1/2

-1/2

TA = 138 °C, CAL @ 25 °C

Figure 14 . CS5102A DNL Plot ; Ambient Temperature at 138°C

Figure 13 . CS5102A DNL Plot ; Ambient Temperature at 25°C

Figure 12 . CS5101A DNL Plot ; Ambient Temperature at 138°C

Figure 11 . CS5101A DNL Plot ; Ambient Temperature at 25°C

065,535

Codes

32,768

DNL (LSB)

-1

+1/2

-1/2

TA = 25°C

CS5101A CS5102A

24 DS45F2

code with more or less occurrences than average

will appear as a DNL of greater or less than zero

LSB. A missing code has zero occurrences, and

will appear as a DNL of -1 LSB.

Figures 15 and 16 illustrate the code width distri-

bution of the DNL plots shown in Figures 11 and

13 respectively. The DNL error distribution plots

indicate that the CS5101A and CS5102A cali-

brate the majority of their codes to tighter

tolerance than the DNL plots in Figures 11 and

13 appear to in dicate.

FFT Tests and Windowing

In the factory, the CS5101A and CS5102A are

tested using Fast Fourier Transform (FFT) tech-

niques to analyze the converters’ dynamic

performance. A pure sinewave is applied to the

device, and a "time record" of 1024 samples is

(Thousands)

-0.65

Number of Codes with Each DNL

-0.55 -0.45 -0.35 -0.25 -0.15 -0.05 0 0.05 0.15 0.25 0.35 0.45 0.55 0.65

0 1 16 115 481

3708

15570

25248

15499

3959

714 175 41 5 2

DNL Error in LSB

# of Missing Codes: 0

Total # of

Codes Analyzed: 65534

Figure 15. CS5101A DNL Error Distribution

(Thousands)

Number of Codes with Each DNL

-0.45 -0.35 -0.25 -0.15 -0.05 0 0.05 0.15 0.25 0.35 0.45

03 86

1775

16047

31047

14592

1892 88 4 0

DNL Error in LSB

# of Missing Codes: 0

Total # of

Codes Analyzed: 65534

Figure 16. CS5102A DNL Error Distribution

CS5101A CS5102A

DS45F2 25

captured and processed. The FFT algorithm ana-

lyzes the spectral content of the digital waveform

and distributes its energy among 512 "frequency

bins." Assuming an ideal sinewave, distribution

of energy in bins outside of the fundamental and

dc can only be due to quantization effects and

errors in the CS5101 A an d CS5102A.

If sampling is not synchronized to the input sine-

wave, it is highly unlikely that the time record

will contain an integer number of periods of the

input signal. However, the FFT assumes that the

signal is periodic, and will calculate the spectrum

of a signal that appears to have large discontinui-

ties, thereby yielding a severely distorted

spectrum. To avoid this problem, the time record

is multiplied by a window function prior to per-

forming the FFT. The window function smoothly

forces the endpoints of the time record to zero,

thereby removing the discontinuities. The effect

of the window in the frequency-domain is to con-

volute the spectrum of the window with that of

the actual inpu t.

The quality of the window used for harmonic

analysis is typically judged by its highest side-

lobe level. A five term window is used in FFT

testing of the CS5101A and CS5102A. This win-

dowing algorithm attenuates the side-lobes to

below the noise floor. Artifacts of windowing are

discarded from the signal-to-noise calculation us-

ing the assumption that quantization noise is

white. Averaging the FFT results from ten time

records filters the spectral variability that can

arise from capturing finite time records without

disturbing the total energy outside the fundamen-

tal. All harmonics are visible in the plots. For

more information on FFT’s and windowing refer

to: F.J. HARRIS, "On the use of windows for

harmonic analysis with the Discrete Fourier

Transform", Proc. IEEE, Vol. 66, No. 1, Jan

1978, pp.51-83. This is available on request from

Crystal Semiconductor.

As illustrated in Figure 17, the CS5101A typi-

cally provides about 92 dB S/(N+D) and

0.001% THD at 25°C. Figure 18 illustrates only

minor degradation in performance when the am-

bient temperature is raised to 138°C. Figure 19

and 20 illustrate that the CS5102A typically

yields >92 dB S/(N+D) and 0.001% THD even

with a large change in ambient temperature. Un-

like conventional successive-approximation

ADC’s, the signal-to-noise and dynamic range of

the CS5101A and CS5102A are not limited by

differential nonlinearities (DNL) caused by cali-

bration errors. Rather, the dominant noise source

is broadband thermal noise which aliases into the

baseband. This white broadband noise also ap-

pears as an idle channel noise of 1/2 LSB (rms).

Sampling Distortion

Like most discrete sample/hold amplifier designs,

the inherent sample/hold of the CS5101A and

CS5102A exhibits a frequency-dependent distor-

tion due to nonideal sampling of the analog input

voltage. The calibrated capacitor array used dur-

ing conversions is also used to track and hold the

analog input signal. The conversion is not per-

formed on the analog input voltage per se, but is

actually performed on the charge trapped on the

capacitor array at the moment the HOLD com-

mand is given. The charge on the array ideally

assumes a linear relationship to the analog input

voltage. Any deviation from this linear relation-

ship will result in conversion errors even if the

conversion process proceeds flawlessly.

At dc, the DAC capacitor array’s voltage coeffi-

cient dictates the converter’s linearity. This

variation in capacitance with respect to applied

signal voltage yields a nonlinear relationship be-

tween the charge on the array and the analog

input voltage and places a bow or wave in the

transfer function. This is the dominant source of

distortion at low input frequencies (Fig-

ures 17,18,19, and 20).

The ideal relationship between the charge on the

array and the input voltage can also be distorted

CS5101A CS5102A

26 DS45F2

at high signal frequencies due to nonlinearities in

the internal MOS switches. Dynamic signals

cause ac current to flow through the switches

connecting the capacitor array to the analog input

pin in the track mode. Nonlinear on-resistance in

the switches causes a nonlinear voltage drop.

This effect worsens with increased signal fre-

quency and slew rate. This distortion is negligible

at signal levels below -10 dB of full-scale.

Noise

An A/D converter’s noise can be described like

that of any other analog component. However,

the converter’s output is in digital form so any

filtering of its noise must be performed in the

digital domain. Digitized samples of analog in-

puts are often considered individual, static snap-

shots in time with no uncertainty or noise. In

reality, the result of each conversion depends on

the analog input level and the instantaneous value

of noise sources in the ADC. If sequential sam-

ples from the ADC are treated as a "waveform",

simple filtering can be implemented in software

to improve noise performance with minimal proc-

essing overhead.

All analog circuitry in the CS5101A and

CS5102A is wideband in order to achieve fast

conversions and high throughput. Wideband

noise in the CS5101A and CS5102A integrates to

35 µV rms in unipolar mode (70 µV rms in bipo-

lar mode). This is approximately 1/2 LSB rms

with a 4.5V reference in both modes. Figure 21

Figure 18. CS5101A FFT (SSC Mode, 1-Channel)

dc 50

Input Frequency (kHz)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Signal Level

Reletive To

Full Scale

(dB)

Figure 17. CS5101A FFT (SSC Mode, 1-Channel)

dc 50

Input Frequency (kHz)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Signal Level

Relative to

Full Scale

(dB)

dc 10

Input Frequency (kHz)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Signal Level

Reletive To

Full Scale

(dB)

S/N+D: 92.01 dB

S/D: 101.8 dB

Figure 19. CS5102A FFT (SSC Mode, 1-Channel)

dc 10

Input Frequency (kHz)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Signal Level

Relative to

Full Scale

(dB)

Figure 20. CS5102A FFT (SSC Mode, 1-Channel)

S/(N+D): 91.06 dB

S/D: 100.5 dB

TA = 138 °C

S/(N+D): 91.71 dB

S/D: 101.6 dB

S/(N+D): 92.01 dB

S/D: 101.8 dB S/(N+D): 92.00dB

S/D: 101.6 dB

TA = 138 °C

CS5101A CS5102A

DS45F2 27

shows a histogram plot of output code occur-

rences obtained from 8192 samples taken from a

CS5101A in the bipolar mode. Hexadecimal code

7FFE was arbitrarily selected and the analog in-

put was set close to code center. With a noiseless

converter, code 7FFE would always appear. The

histogram plot of the device has a "bell" shape

with all codes other than 7FFE due to internal

noise. Figure 22 illustrates the noise histogram of

the CS5102 A.

In a sampled data system all information about

the analog input applied to the sample/hold ap-

pears in the baseband from dc to one-half the

sampling rate. This includes high-frequency com-

ponents which alias into the baseband. Low-pass

(anti-alias) filters are therefore used to remove

frequency components in the input signal which

are above one-half the sample rate. However, all

wideband noise introduced by the CS5101A and

CS5102A still aliases into the baseband. This

"white" noise is evenly spread from dc to one-

half the sampling rate and integrates to 35 µV rm s

in unip olar mode.

Noise in the digital domain can be reduced by

sampling at higher than the desired word rate and

averaging multiple samples for each word. Over-

sampling spreads the device’s noise over a wider

band (for lower noise density), and averaging ap-

plies a low-pass response which filters noise

above the desired signal bandwidth. In general,

the device’s noise performance can be maximized

in any application by always sampling at the

maximum specified rate of 100 kHz (CS5101A)

or 20 kHz (CS5102A) (for lowest noise density)

and digitally filtering to the desired signal band-

width.

Aperture Jitter

Track-and-hold amplifiers commonly exhibit two

types of aperture jitter. The first, more appropri-

ately termed "aperture window", is an input

voltage dependent variation in the aperture delay.

Its signal-dependency causes distortion at high

frequencies. The proprietary architecture of the

CS5101A and CS5102A avoids applying the in-

put voltage across a sampling switch, thus

avoiding any "aperture window" effects. The sec-

ond type of aperture jitter, due to component

noise, assumes a random nature. With only

100 ps peak-to-peak aperture jitter, the CS5101A

and CS5102A can process full-scale signals up to

7FFC 7FFD 7FFE

8000 8001

7FFF7FFB

2048

4096

6144

8192

Count

Noiseless

CS5101A

Code (Hexadecimal)

Counts: 0 0 989 6359 844 0 0

Converter

Figure 21. 51 01A Histogram Plo t of 819 2 Conversion

Inputs

7FFE 7FFF 8000(H) 8002 800380017FFD

Count

Noiseless

CS5102A

Code (Hexadecimal)

Counts:

1727 4988 1467 5

Converter

8192

6144

4096

2048

Figure 22. 51 02A Histogram Plo t of 819 2 Conversion

Inputs

CS5101A CS5102A

28 DS45F2

1/2 the throughput frequency without significant

errors due to aperture jitter.

Power Supply Rejection

The power supply rejection performance of the

CS5101A and CS5102A is enhanced by the on-

chip self-calibration and an "auto-zero" process.

Drifts in power supply voltages at frequencies

less than the calibration rate have negligible ef-

fect on the device’s accuracy. This is because the

CS5101A and CS5102A adjust their offset to

within a small fraction of an LSB during calibra-

tion. Above the calibration frequency the

excellent power supply rejection of the internal

amplifiers is augmented by an auto-zero process.

Any offsets are stored on the capacitor array and

are effectively subtracted once conversion is initi-

ated. Figure 23 shows power supply rejection of

the CS5101A and CS5102A in the bipolar mode

with the analog input grounded and a 300 mV p-

p ripple applied to each supply. Power supply

rejection improves by 6 dB in the unipolar mode.

CS5101A/CS5102A Improvements Over Ear-

lier CS5101/CS5102

The CS5101A/CS5102A are improved versions

of the earlier CS5101/CS5102 devices. Primary

improvements are:

1) Improved DNL at high temperature

(>70 °C)

2) Improved input slew rate, yielding im-

proved full scale settling between

conversions.

3) Modifying the previous SSH pin to

SSH/SDL (Simultaneous Sample Hold/Se-

rial Data Latch). The SSH/SDL new

function provides a logic signal which

frames the 16 data bits in SSC and FRN

serial modes. This signal is ideal for easy

interface to serial to parallel shift registers

(74HC595) and to DSP serial ports.

Table 3 su mmarizes all the improv ements.

Power Supply Ripple Frequency

Power Suppl y R eje ct ion (dB)

1 kHz 10 kHz

100 kHz

1 MHz

Figure 23. Power Supply Rejection

CS5101A CS5102A

DS45F2 29

Function CS5101A/CS5102A CS5101/CS5102

Better DNL No missing codes at +125 °C Some m issed co des at + 125 °C

Faste r Fine Char ge CS51 01A CS5102A CS510 1 CS5102

Slew Rate

(V/µs) Unipolar/Fine 2 0.4 Unipolar/Fine 1.3 0.1

Bipolar/Fine 4 0.8 Bipolar/Fine 2.6 0.2

Impr oved Se rial Has seri al data la tch Doe s not have serial da ta

Interface signal (SSH/SDL). latch (SDL) signal.

CLKIN Rate CS5101A maximum CS5101 maximum

CLKIN is 9.216 MHz CLKIN is 8.0 MHz

CS5102A maximum CS5102 maximum

CLKIN is 2.0 MHz CLKIN is 1.6 MHz

Code and In dependen t settin g of 2’s Sele cting unip olar inp ut range

BP/UP Pin complement or offset binary forces offset binary operation,

Functi on codi ng (CODE ) and bip olar or indepe ndent of t he CODE pin stat e

unipolar input range (BP/UP)

CRS/FIN Pin Can be high or low CRS/FIN must be held

durin g calibra tion low during ca librati on

Table 3. CS5101A/CS5102A Improvements over CS5101/CS5102

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

For Our Free Review Service

Call Applications Engineering.

Call:(512) 445-7222

CS5101A CS5102A

30 DS45F2

PIN DESCRIPTIONS

NEGATIVE DIGITAL POWER VD- SLEEP SLEEP (LOW POWER) MODE

RESET & INITIATE CALIBRATION RST SCKMOD SERIAL CLOCK MODE SELECT

MASTER CLOCK INPUT CLKIN TEST TEST

CRYSTAL OUTPUT XOUT VA+ POSITIVE ANALOG POWER

STANDBY (CALIBRATING) STBY AIN2 CHANNEL 2 ANALOG INPUT

DIGITAL GROUND DGND VA- NEGATIVE ANALOG POWER

POSITIVE DIGITAL POWER VD+ AGND ANALOG GROUND

TRACKING CHANNEL 1 TRK1 REFBUF REFERENCE BUFFER

TRACKING CHANNEL 2 TRK2 VREF VOLTAGE REFERENCE

COARSE/FINE CHARGE CONTROL CRS/FIN AIN1 CHANNEL 1 ANALOG INPUT

SIMULTANEOUS S/H / SERIAL DATA LATCH SSH/SDL OUTMOD OUTPUT MODE SELECT

HOLD & CONVERT HOLD BP/UP BIPOLAR/UNIPOLAR SELECT

INPUT CHANNEL SELECT CH1/2CODEBINARY/2’s COMPLEMENT SELECT

SERIAL DATA CLOCK SCLK SDATA SERIAL DATA OUTPUT

CS5102A

CS5101A

VD-

RST SLEEP

CLKIN SCKMOD

XOUT TEST

STBY VA+

DGND AIN2

VD+ VA-

TRK1 AGND

TRK2 REFBUF

CRS/FIN VREF

SSH/SDL AIN1

HOLD OUTMOD

CH1/2 BP/UP

SCLK CODE

SDATA

top

view

3272426281

12 14 16 1813 15 17

CS5102A

CS5101A

CS5101A CS5102A

DS45F2 31

Power Supply Connections

VD+ - Positive Digital Power, PIN 7.

Positive digital power supply. Nominally +5 volts.

VD- - Negative Digital Power, PIN 1.

Negative digital power supply. Nominally -5 volts.

DGND - Digital Ground, PIN 6.

Digital ground [reference].

VA+ - Positive Analog Power, PIN 25.

Positive analog power supply. Nominally +5 volts.

VA- - Negative Analog Power, PIN 23.

Negative analog power supply. Nominally -5 volts.

AGND - Analog Ground, PIN 22.

Analog ground reference.

Oscillator

CLKIN - Clock Input, PIN 3.

All conversions and calibrations are timed from a master clock which can be externally

supplied by driving CLKIN [this input TTL-compatible, CMOS recommended].

XOUT - Crystal Output, PIN 4.

The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an

external clock is used, XOUT must be left floating.

Digital Inputs

HOLD - Hold, PIN 12.

A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a

conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run

Mode, HOLD is disabled, and should be tied to DGND or VD+.

CRS/FIN - Coarse Charge/Fine Charge Control, PIN 10.

When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into

coarse charge state. This engages the internal buffer amplifier to track the analog input and

charges the capacitor array much faster, thereby allowing the CS5101A or CS5102A to track

high slewing signals. In order to get an accurate sample, the last coarse charge period before

initiating a conversion (bringing HOLD low) must be longer than 0.75 µs (CS5101A) or

3.75 µs (CS5102A). Similarly, the fine charge period immediately prior to conversion must be

at least 1.125 µs (CS5101A) or 5.625 µs (CS5102A). The CRS/FIN pin must be low during

conversion time. For normal operation, CRS/FIN should be tied low, in which case the

CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles immediately

after the end of conversion.

CS5101A CS5102A

32 DS45F2

CH1/2 - Left/Right Input Channel Select, PIN 13.

Status at the end of a conversion cycle determines which analog input channel will be acquired

for the next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate

which channel is being sampled during the current acquisition phase.

SLEEP - Sleep, PIN 28.

When brought low causes the CS5101A or CS5102A to enter a power-down state. All

calibration coefficients are retained in memory, so no recalibration is needed after returning to

the normal operating mode. If using the internal crystal oscillator, time must be allowed after

SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal

operation.

CODE - 2’s Complement/Binary Coding Select, PIN 16.

Determines whether output data appears in 2’s complement or binary format. If high, 2’s

complement; if low, binary.

BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.

When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF.

When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.

SCKMOD - Serial Clock Mode Select, PIN 27.

When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with

OUTMOD to select one of 4 output modes described in Table 2.

OUTMOD - Output Mode Select, PIN 18.

The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The

four modes are described in Table 2.

SCLK - Serial Clock, PIN 14.

Serial data changes status on a falling edge of this input, and is valid on a rising edge. When

SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A

generates its own serial clock at one-fourth the master clock frequency and SCLK is an output.

RST - Reset, PIN 2.

When taken low, all internal digital logic is reset. Upon returning high, a full calibration

sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN

cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The

CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is

maintained during SLEEP mode, and need not be repeated when resuming normal operation.

Analog Inputs

AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.

Analog input connections for the left and right input channels.

VREF - Voltage Reference, PIN 20.

The analog reference voltage which sets the analog input range. In unipolar mode VREF sets

full-scale; in bipolar mode its magnitude sets both positive and negative full-scale.

CS5101A CS5102A

DS45F2 33

Digital Outputs

STBY - Standby (Calibrating), PIN 5.

Indicates calibration status after reset. Remains low throughout the calibration sequence and

returns high upon completion.

SDATA - Serial Output, PIN 15.

Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the

rising edge of SCLK.

SSH/SDL - Simultaneous Sample/Hold / Serial Data Latch, PIN 11.

Used to control an external sample/hold amplifier to achieve simultaneous sampling between

channels. In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch

signal which forms the 16 data bits. This can be used to control external serial to parallel

latches, or to control the serial port in a DSP.

TRK1, TRK2 - Tracking Channel 1, Tracking Channel 2, PINS 8 and 9.

Falls low at the end of a conversion cycle, indicating the acquisition phase for the

corresponding channel. The TRK1 or TRK2 pin will return high at the beginning of conversion

for that channel.

Analog Outputs

REFBUF - Reference Buffer Output, PIN 21.

Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and VA-.

Miscellaneous

TEST - Test, PIN 26.

Allows access to the CS5101A’s and the CS5102A’s test functions which are reserved for

factory use. Must be tied to VD+.

CS5101A CS5102A

34 DS45F2

PARAMETER DEFINITIONS

Linearity Error

The deviation of a code from a straight line passing through the endpoints of the transfer

function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2

LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code

transition to all ones. The deviation is measured from the middle of each particular code. Units

in % Full-Scale.

Differential Linearity

Minimum resolution for which no missing codes is guaranteed. Units in bits.

Full Scale Error

The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSB’s.

Unipolar Offset

The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in

unipolar mode (BP/UP low). Units in LSB’s.

Bipolar Offset

The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 LSB below

AGND) when in bipolar mode (BP/UP high). Units in LSB’s.

Bipolar Negative Full-Scale Error

The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high).

The ideal is defined as lying on a straight line which passes through the final and mid-scale

code transitions. Units in LSB’s.

Signal to Peak Harmonic or Noise

The ratio of the rms value of the signal to the rms value of the next largest spectral component

below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the

signal frequency is a significant proportion of the sampling rate. Expressed in decibels.

Total Harmonic Distortion

The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.

Signal-to-(Noise + Distortion)

The ratio of the rms value of the signal to the rms sum of all other spectral components below

the Nyquist rate (excepting dc), including distortion components. Expressed in decibels.

Aperture Time

The time required after the hold command for the sampling switch to open fully. Effectively a

sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.

Aperture Jitter

The range of variation in the aperture time. Effectively the "sampling window" which ultimately dic-

tates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds.

CS5101A CS5102A

DS45F2 35

CS5101A Ordering Guide

Model Conversion Time Throughput Linearity Temperature Package

CS5101A-JP8 8.13 µs 100 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP

CS5101A-KP8 8.13 µs 100 kHz 0.002% 0 to 70 °C 28-Pin Plastic DIP

CS5101A-JP16 16.25 µs 50 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP

CS5101A-JL8 8.13 µs 100 kHz 0.003% 0 to 70 °C 28-Pin PLCC

CS5101A-KL8 8.13 µs 100 kHz 0.002% 0 to 70 °C 28-Pin P LCC

CS5101A-JL16 16.25 µs 50 kHz 0.003% 0 to 70 °C 28-Pin PLCC

CS5101A-AP8 8.13 µs 100 kHz 0.003% -40 to 85 °C 28-Pin Plastic DIP

CS5101A-BP8 8.13 µs 100 kHz 0.002% -40 to 85 °C 28-Pin Plastic DIP

CS5101A-AL8 8.13 µs 100 kHz 0.003% -40 to 85 °C 28-Pin PLCC

CS5101A-BL8 8.13 µs 100 kHz 0.002% -40 to 85 °C 28-Pin PLCC

CS5101A-SD8 8.13 µs 100 kHz 0.004% -55 to 125 °C 28-Pin CerDIP

CS5101A-TD8 8.13 µs 100 kHz 0.003% -55 to 125 °C 28-Pin CerDIP

CS5101A-SE8 8.13 µs 100 kHz 0.004% -55 to 125 °C 28-Pin LCC

CS5101A-TE8 8.13 µs 100 kHz 0.003% -55 to 125 °C 28-Pin LCC

5962-9169101MXA 8.13 µs 100 kHz 0.004% -55 to 125 °C 28-Pin CerDIP

5962-9169102MXA 8.13 µs 100 kHz 0.003% -55 to 125 °C 28-Pin CerDIP

5962-9169101M3A 8.13 µs 100 kHz 0.004% -55 to 125 °C 28-Pin LCC

5962-9169102M3A 8.13 µs 100 kHz 0.003% -55 to 125 °C 28-Pin LCC

Discontinued Equivalent

Part Number Recommended Device

CS5101A-SD8B 5962-9169101MXA

CS5101A-TD8B 5962-9169102MXA

CS5101A-SE8B 5962-9169101M3A

CS5101A-TE8B 5962-9169102M3A

CS5102A Ordering Guide

Model Conversion Time Throughput Linearity Temperature Package

CS5102A-JP 40 µs 20 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP

CS5102A-KP 40 µs 20 kHz 0.0015% 0 to 70 °C 28-Pin Plastic DIP

CS5102A-JL 40 µs 20 kHz 0.003% 0 to 70 °C 28-Pin PLCC

CS5102A-KL 40 µs 20 kHz 0.0015% 0 to 70 °C 28-Pin PLCC

CS5102A-AP 40 µs 20 kHz 0.003% -40 to 85 °C 28-P in Plastic DIP

CS5102A-BP 40 µs 20 kHz 0.0015% -40 to 85 °C 28-Pin Plastic DIP

CS5102A-AL 40 µs 20 kHz 0.003% -40 to 85 °C 28-P in PLCC

CS5102A-BL 40 µs 20 kHz 0.0015% -40 to 85 °C 28-Pin PLCC

CS5102A-SD 40 µs 20 kHz 0.004% -55 to 125 °C 28-Pin CerDIP

CS5102A-TD 40 µs 20 kHz 0.002% -55 to 125 °C 28-Pin CerDIP

CS5102A-SE 40 µs 20 kHz 0.004% -55 to 125 °C 28-Pin LCC

CS5102A-TE 40 µs 20 kHz 0.002% -55 to 125 °C 28-Pin LCC

5962-9169201MXA 40 µs 20 kHz 0.004% -55 to 125 °C 28-Pin CerDIP

5962-9169202MXA 40 µs 20 kHz 0.002% -55 to 125 °C 28-Pin CerDIP

5962-9169201M3A 40 µs 20 kHz 0.004% -55 to 125 °C 28-Pin LCC

5962-9169202M3A 40 µs 20 kHz 0.002% -55 to 125 °C 28-Pin LCC

Discontinued Equivalent

Part Number Recommended Device

CS5102A-SDB 5962-9169201MXA

CS5102A-TDB 5962-9169202MXA

CS5102A-SEB 5962-9169201M3A

CS5102A-TEB 5962-9169202M3A

CS5101A CS5102A

36 DS45F2



Cirrus Logic, Inc. 1998

Cirrus Logic, Inc.

Crystal Semiconductor Products Divisio n

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

CDB5101A

CDB5102A

Evaluation Board for CS5101A and CS5102A

Features

lSerial to Parallel Conversion

lAdjustable Voltage Reference

l±5 V Regulators

lDigital and Analog Patch Areas

Description

The CDB5101A/5102A Evaluation Board allows fast

evaluation of the CS5101A and CS5102A 2-Channel,

16-bit Analog-to-Digital Converters.

Analog inputs are via BNC connectors. Digital outputs

are available both directly from the ADC in serial form,

and in 16 bit parallel form.

An adjustable monolithic voltage reference is included.

ORDERING INFORMATION

CDB5101A Evaluation Board

CDB5102A Evaluation Board

-15V

+15V

VA+ VA- VD+VD-

VREF

REFBUF

AIN1

AIN2

CODE

BP/UP

SCKMOD

OUTMOD

SLEEP

Voltage

Reference

Serial

Parallel

Conversion

CLKIN

XOUT

HOLD

SDATA

SCLK

SSH/SDL

Digital

Patch

Area

Header

EXT

VA-

AIN1

AIN2

±5V Regulators

AGND

VL+

+5V0V

DGND

Mode

Select

Switches

CH1/CH2

HOLD

Header

CS5101A

CS5102A

Input

Buffers

Serial

Output

Buffers

Analog

Patch

Area

CLKIN

MAR ‘95

DS45DB3

Power Supplies

Figure 1 shows the power supply arrangements.

The analog section of the board is powered by

± 12/15 volts, which is regulated down to ± 5V

for the ADC. A separate +5V digital supply is

required to power the discrete logic.

Analog Input

The CS5101A/02A converters have a two-chan-

nel multiplexer input. Separate amplifiers (see

Figure 2) are provided on the evaluation board

to drive each input independently. If the con-

verter is used in FRN mode, the multiplexer

"ping-pongs" between channels. If only one sig-

nal is to be digitized in FRN mode at full speed,

the AIN1 and AIN2 pins on the converter should

be shorted together. Then the amplifier circuitry

for the unused channel should be disconnected.

For example, if only Analog Input one is used

(in FRN mode) as the input, short the AIN1 and

AIN2 pins of the converter and remove R15 and

C15.

If you do not want to use the on-board amplifi-

ers, connect your signal to TP27 for channel 1

and TP32 for channel 2. Use TP28 and TP31 to

break the connection to the output of the on-

board buffers. Your own buffer amplifiers may

be installed in the 2 analog patch areas. For criti-

cal 2 channel applications, keep the signal path

for the 2 channels identical.

Voltage Reference

Figure 3 shows the LTI019-4.5 voltage refer-

ence, which is buffered and filtered to reduce

output impedance and noise.

+15V

-15V

C20 C19

C21 C18

0.22

0.47

+5VA

- 5VA

C23

C22

0.22

0.47

C25

C24

0.1

+12/15V

-12/15V

AGND

DGND

+5V

Logic

TP GND

+5VL

TP - VA+

TP - VA -

TP +5V

78L05

OUT

COM

79L05

OUT

COM

Figure 1. Power Supplies

CDB5101A/5102A

38 DS45DB3

TP28TP29

TP27

TP31TP30 TP32

2.0k

R27

1.0k

2.0k

1.0k

TP34

TP33

-15V

2.0k

62pF

1.0k

346

2.0k

62pF

1nF

NPO

AIN1

AIN2

OPA627

U10

1.0k

+15V

C34

R17

C31

C30

R19

R14

C16

C15

R15

C32

C33

C38

C37 .1

R22

C35

C36

R20

C39

R21

R28

R18

ANALOG

INPUT 1

ANALOG

INPUT 2

C45 0.01

C48 0.01

*Amplifiers U9 and U10

have gain of +1, as

resistors R18 and R21

are left off the board.

Input

Uni pol ar 0V to +4.5V

Bipolar -4.5V to +4.5V

Fig. 4

Figure 2. Input Buffer Circuit.

0.1

TP77

25 k

OUT

TRIM

GND

+15V

2 k

C1 15

OP27

0.1

0.01

47 k

1 k

+15V

-15V

0.1

1 k

C44

R25

C43

C42

R23

U11

C40

R26

R24

C41

LT1019-4.5

VREF

Fig. 4

Figure 3. Volta ge Refere nce

CDB5101A/5102A

DS45DB3 39

Master Clock

Figure 4 shows the local connections to the

CS5101A or CS5102A. The appropriate crystal

components are installed at the factory, which

utilize the on-chip oscillator. For use with an ex-

ternal clock, cut Jumper J00 and drive a CMOS

level compatible clock into the CLKIN BNC

connector. R30 is an optional 50Ω terminating

resistor if a pulse generator is used.

Sampling Clock (HOLD) Generation

The evaluation board is shipped in FRN mode,

which requires no externally generated HOLD

signal. Alternate modes may be selected using

DIP switch 3 and 4 (See Table 2). An external

HOLD may be connected using the HOLD BNC

connector.

VA+

TST

CLKIN

XOUT

0.1

R11

C13 C14 C12 C11

-5VA

0.1

VA- VD-

VREF

AGND

See

VD+

CS5101A

CS5102A

VD+

VA -

+5VA

C4 C5

0.1

J00

TP00

CLKIN

10M

AIN1

AIN2

TP25

HOLD

R13

10k

R1210k

CRS/FIN

Fig. 3

REFBUF

VA-

0.1

TP00

Reset

0.1

C10

10k

R6 VD+

DGND

RST

CODE

BP/UP

SCKMOD

OUTMOD

SLEEP

CH1/CH2

SDATA

SCLK

SSH/SDL

STBY

TRK1

TRK2

VD+

10k

CODE

BP/UP

OUTMOD

SLEEP

CH1/CH2

SDATA Fig. 5, 6

SCLK Fig. 5, 6

SSH/SDL Fig. 5, 6

R22

C17

TR K1 F ig. 6

TR K2 F ig. 6

CH1/CH2 Fig. 5

R9 47k

R31

R30

See

Fig. 2

See

Fig. 2

SCKMOD

Figure 4. ADC Connections

8.192 MHz 1.6 MHzY1

10 pF 30 pFC8

10 pF 30 pFC9

CDB5101A

CDB5102A

OSCILLATOR

COMPONENT

VALUES

CDB5101A/5102A

40 DS45DB3

Control Signals

Figure 5 shows 2 headers are provided for serial

data output and control signals. JP3 provides

SDATA and SSH/SDL outputs. It also allows ac-

cess to SCLK & CH1/CH2 which may be inputs

or outputs depending on the serial mode selected

by the DIP switches. Jumpers J10, J11, J12, &

J13 must be set to correspond with the appropri-

ate directions of SCLK and CH1/CH2.

JP5 provides output only access to the +5V logic

supply, SCLK, SDATA and SLATCH, the serial

to parallel latching control.

Serial to Parallel Conversion

When operating in the FRN or SSC serial port

modes, the CS5101A/02A readily provides the

three signals (SCLK, SDATA, and SSH/SDL) to

support serial to parallel conversion of its output

data.

Figure 6 Shows 2 74HC595’s provided to con-

vert the serial output of the ADC to parallel. A

handshake flip-flop, U3, is provided for the par-

allel interface if required. When parallel data is

available to read, DRDY goes low. The com-

puter reads the data and sets DACK high and

then low. This resets the flip-flop for the next

word. JP4 selects whether both CH1 and CH2

data appears alternately, or CH1 only, or CH2

only.

SCLK

Direction

J10

Out

JP3

J11

J12

OE1

OE2

74HC365

U12

C48

+5V

Out

R32

HDR5D

HDR10D

+5V

JP5

C47

R33

SSH/SDL

SDATA

SCLK

SLATCH

CH1/CH2

J13

Direction

CH1/CH2

SDATA

SCLK

SSH/SDL

CH1/CH2

+5V

SLATCH

SCLK

SDATA

Fig. 4

Fig. 6

Figure 5. Serial Output Buffers

CDB5101A/5102A

DS45DB3 41

Shift CLK

Lat c h C L K

DATA IN

74HC595

D15 (MSB)

D14

D13

D12

D11

D10

D0 (LSB)

DACK

DRDY

Shift CLK

Lat c h C L K

DATA OUT

DATA IN

74HC595

40 way

header

TP00

GND

10 16

RST

+5VL

0.1

C27

10 16

RST

+5VL

0.1

C29

JP2

GND

+5VL

TP00

7 1 6

TP00

414

+5VL

SDATA

SCLK

TP00

CLK

74HC74

+5V U3

+5V

R16

10k

JP4

HDR8D

10k

R10

10k

TRK1

TRK2

SSH/SDL

SLATCH

BOTH

CH2

CH1

Fig. 5

Fig. 4

Figur e 6. Serial to Parallel C onverter

CDB5101A/5102A

42 DS45DB3

DIP Switches

Tables 1 and 2 show the DIP switch settings.

Miscellaneous Hints on Using the Evaluation

Board

Always depress the reset button after powering

up the board. The CS5101A & CS5102A are self

calibrating ADC’s which require a reset to initi-

ate the internal calibration procedure.

Crystal Semiconductor has software, available on

request, which allows the evaluation board to be

connected to a Metrabyte PIO12 parallel I/O

card (which uses an Intel 8255 PIO chip), which

is plugged into an IBM PC or compatible com-

puter. The software is assembly language drivers

to read the data from the board. Also included is

source code, in Fortran, of an FFT routine.

Table 2. Output Mode Selections

OPEN

CODE

BP/UP

SCKMOD

SLEEP

OUTMOD

CH1/CH2*

2’s Co mple me n t

Bipolar

Selects Serial Port

Mode. See Table 2.

Normal Mode

AIN1

Binary

Unipolar

Sleep Mode

AIN2

OPEN

*SW6 is not active when the conve r te r is operat ing in the FRN mode.

Table 1. DIP Switch Selections

SCKMOD

(SW4) OUTMOD

(SW3) CS5101A/CS5102A

Output Mode

CLOSE CLOSE (FRN) Free Run

CLOSE OPEN (SSC) Synchronous Self Clocking

OPEN CLOSE (RBT) Registered Burst Transmission

OPEN OPEN (PDT) Pipelined Data Transmission

NOTE: CLOSED = LOW = 0; OPEN = HIGH = 1.

CDB5101A/5102A

DS45DB3 43

Figure 7. CDB5101A/02A Rev. B Layout

CDB5101A/5102A

44 DS45DB3

Figure 8. CDB5101A/02A Rev. B Component Side

CDB5101A/5102A

DS45DB3 45

Figure 9. CDB5101A/02A Rev. B Solder Side

CDB5101A/5102A

46 DS45DB3

• Notes •