PIC18F2XK20/4XK20 Flash Memory Programming Specification 1.0 DEVICE OVERVIEW 2.1 In High-Voltage ICSP mode, the PIC18F2XK20/4XK20 devices require two programmable power supplies: one for VDD and one for MCLR/VPP/RE3. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 "AC/DC Characteristics Timing Requirements for Program/Verify Test Mode" for additional hardware parameters. This document includes the programming specifications for the following devices: * * * * * * * * PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20 2.0 2.1.1 LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSP mode, the PIC18F2XK20/4XK20 devices can be programmed using a single VDD source in the operating range. The MCLR/VPP/RE3 does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 "AC/DC Characteristics Timing Requirements for Program/Verify Test Mode" for additional hardware parameters. PROGRAMMING OVERVIEW The PIC18F2XK20/4XK20 devices can be programmed using either the high-voltage In-Circuit Serial ProgrammingTM (ICSPTM) method or the low-voltage ICSP method. Both methods can be done with the device in the users' system. The low-voltage ICSP method is slightly different than the high-voltage method and these differences are noted where applicable. This programming specification applies to the PIC18F2XK20/4XK20 devices in all package types. TABLE 2-1: Hardware Requirements 2.2 Pin Diagrams The pin diagrams for the PIC18F2XK20/4XK20 family are shown in Figure 2-3 and Figure 2-4. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XK20/4XK20 During Programming Pin Name Pin Name Pin Type Pin Description MCLR/VPP/RE3 VPP P Programming Enable VDD(2) VDD P Power Supply VSS(2) VSS P Ground RB5 PGM I Low-Voltage ICSPTM input when LVP Configuration bit equals `1'(1) RB6 PGC I Serial Clock RB7 PGD I/O Serial Data Legend: I = Input, O = Output, P = Power Note 1: See Figure 5-1 for more information. 2: All power supply (VDD) and ground (VSS) pins must be connected. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 1 PIC18F2XK20/4XK20 FIGURE 2-1: 28-PIN SDIP, SSOP AND SOIC PIN DIAGRAMS SDIP, SSOP, SOIC (300 MIL) MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 RC0 RC1 RC2 RC3 PIC18F2XK20 3 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 18 12 17 13 14 16 15 RC7 RC6 RC5 RC4 The following devices are included in 28-pin SDIP, SSOP and SOIC parts: PIC18F23K20, PIC18F24K20, PIC18F25K20, PIC18F26K20. FIGURE 2-2: 28-PIN QFN PIN DIAGRAMS RA1 RA0 28-Pin QFN MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5/PGM RB4 Note: RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS 28 27 26 1 2 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 1 2 3 4 5 6 7 PIC18F2XK20 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 Note: The following devices are included in 28-pin QFN parts: PIC18F23K20, PIC18F24K20, PIC18F25K20, PIC18F26K20. DS41297F-page 2 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 FIGURE 2-3: 40-PIN PDIP PIN DIAGRAMS 40-PIN PDIP (600 MIL) Note: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4XK20 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS OSC1 OSC2 RC0 RC1 RC2 RC3 RD0 RD1 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 The following devices are included in 40-pin PDIP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. FIGURE 2-4: 44-PIN TQFP PIN DIAGRAMS 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 PIC18F4XK20 6 7 8 9 10 11 NC RC0 OSC2 OSC1 VSS VDD RE2 RE1 RE0 RA5 RA4 NC NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC 44-PIN TQFP Note: The following devices are included in 44-pin TQFP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 3 PIC18F2XK20/4XK20 FIGURE 2-5: 44-PIN QFN PIN DIAGRAMS 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 PIC18F4XK20 6 7 8 9 10 11 OSC2 OSC1 VSS VSS VDD VDD RE2 RE1 RE0 RA5 RA4 RB3 NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD VDD RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 44-PIN QFN Note: The following devices are included in 44-pin QFN parts: PIC18F43K20, PIC18F44K20, PIC18F45K20, PIC18F46K20. DS41297F-page 4 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 2.3 TABLE 2-2: Memory Maps For the PIC18FX3K20 devices, the code memory space extends from 0000h to 01FFFh (8 Kbytes) in two 4-Kbyte blocks. Addresses 0000h through 01FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-6: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F23K20 PIC18F43K20 000000h-001FFFh (8K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX3K20 DEVICES 000000h Code Memory 01FFFFh MEMORY SIZE/DEVICE 8 Kbytes (PIC18FX3K20) Boot Block Unimplemented Read as `0' Address Range 000000h 0001FFh 000200h Block 0 000FFFh 001000h Block 1 001FFFh 002000h 200000h Unimplemented Read `0's Configuration and ID Space 01FFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 5 PIC18F2XK20/4XK20 For PIC18FX4K20 devices, the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte blocks. Addresses 000000h through 0007FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-7: TABLE 2-3: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F24K20 000000h-003FFFh (16K) PIC18F44K20 MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX4K20 DEVICES 000000h Code Memory 01FFFFh MEMORY SIZE/DEVICE 16 Kbytes (PIC18FX4K20) 000000h 0007FFh Boot Block Unimplemented Read as `0' Address Range 000800h Block 0 001FFFh 002000h Block 1 003FFFh 004000h 200000h Unimplemented Read `0's Configuration and ID Space 01FFFFh 3FFFFFh Note: DS41297F-page 6 Sizes of memory areas not to scale. Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 For PIC18FX5K20 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. Addresses 000000h through 0007FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-8: TABLE 2-4: IMPLEMENTATION OF CODE MEMORY Device PIC18F25K20 PIC18F45K20 Code Memory Size (Bytes) 000000h-007FFFh (32K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5K20 DEVICES 000000h Code Memory 01FFFFh MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX5K20) Boot Block Unimplemented Read as `0' Address Range 000000h 0007FFh 000800h Block 0 001FFFh 002000h Block 1 003FFFh 004000h Block 2 200000h 005FFFh 006000h Block 3 007FFFh Configuration and ID Space Unimplemented Read `0's 01FFFFh 3FFFFFh Note: Sizes of memory areas not to scale. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 7 PIC18F2XK20/4XK20 For PIC18FX6K20 devices, the code memory space extends from 000000h to 00FFFFh (64 Kbytes) in four 16-Kbyte blocks. Addresses 000000h through 0007FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-9: TABLE 2-5: IMPLEMENTATION OF CODE MEMORY Device PIC18F26K20 PIC18F46K20 Code Memory Size (Bytes) 000000h-00FFFFh (64K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX6K20 DEVICES 000000h Code Memory 01FFFFh MEMORY SIZE/DEVICE 32 Kbytes (PIC18FX6K20) Boot Block Unimplemented Read as `0' Address Range 000000h 0007FFh 000800h Block 0 003FFFh 004000h Block 1 007FFFh 008000h Block 2 200000h 00BFFFh 00C000h Block 3 00FFFFh Configuration and ID Space Unimplemented Read `0's 01FFFFh 3FFFFFh Note: DS41297F-page 8 Sizes of memory areas not to scale. Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 In addition to the code memory space, there are three blocks in the configuration and ID space that are accessible to the user through table reads and table writes. Their locations in the memory map are shown in Figure 2-10. Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses 200000h through 200007h. The ID locations read out normally, even after code protection is applied. Locations 300000h through 30000Dh are reserved for the Configuration bits. These bits select various device options and are described in Section 5.0 "Configuration Word". These Configuration bits read out normally, even after code protection. Locations 3FFFFEh and 3FFFFFh are reserved for the device ID bits. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5.0 "Configuration Word". These device ID bits read out normally, even after code protection. FIGURE 2-10: 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three Pointer registers: * TBLPTRU, at RAM address 0FF8h * TBLPTRH, at RAM address 0FF7h * TBLPTRL, at RAM address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] Addr[7:0] The 4-bit command, `0000' (core instruction), is used to load the Table Pointer prior to using any read or write operations. CONFIGURATION AND ID LOCATIONS FOR PIC18F2XK20/4XK20 DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as `0' 1FFFFFh Configuration and ID Space 2FFFFFh ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ID Location 5 200004h ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 9 PIC18F2XK20/4XK20 2.4 High-Level Overview of the Programming Process 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode Figure 2-11 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code memory, ID locations and data EEPROM are programmed. These memories are then verified to ensure that programming was successful. If no errors are detected, the Configuration bits are then programmed and verified. As shown in Figure 2-12, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/VPP/RE3 to VIHH (high voltage). Once in this mode, the code memory, data EEPROM, ID locations and Configuration bits can be accessed and programmed in serial fashion. Figure 2-13 shows the exit sequence. FIGURE 2-11: The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. HIGH-LEVEL PROGRAMMING FLOW Start FIGURE 2-12: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE Perform Bulk Erase P12 P13 P1 D110 Program Memory MCLR/VPP/RE3 Program IDs VDD PGD Program Data EE PGC PGD = Input Verify Program FIGURE 2-13: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE Verify IDs P16 P17 Verify Data MCLR/VPP/RE3 Program Configuration Bits P1 D110 VDD Verify Configuration Bits Done PGD PGC PGD = Input DS41297F-page 10 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode When the LVP Configuration bit is `1' (see Section 5.3 "Single-Supply ICSP Programming"), the LowVoltage ICSP mode is enabled. As shown in Figure 2-14, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM and then raising MCLR/VPP/RE3 to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. Figure 2-15 shows the exit sequence. The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-14: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P12 P15 MCLR/VPP/RE3 VDD VIH PGM The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are Least Significant bit (LSb) first. 2.7.1 4-BIT COMMANDS All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-6. Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. 2.7.2 PGD CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as appropriate for use with other commands. PGC PGD = Input TABLE 2-6: EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P18 VIH MCLR/VPP/RE3 VDD PGM PGD Serial Program/Verify Operation Throughout this specification, commands and data are presented as illustrated in Table 2-7. The 4-bit command is shown Most Significant bit (MSb) first. The command operand, or "Data Payload", is shown <MSB><LSB>. Figure 2-16 demonstrates how to serially present a 20-bit command/operand to the device. VIH FIGURE 2-15: 2.7 VIH PGC PGD = Input (c) 2009 Microchip Technology Inc. COMMANDS FOR PROGRAMMING Description 4-Bit Command Core Instruction (Shift in16-bit instruction) 0000 Shift out TABLAT register 0010 Table Read 1000 Table Read, post-increment 1001 Table Read, post-decrement 1010 Table Read, pre-increment 1011 Table Write 1100 Table Write, post-increment by 2 1101 Table Write, start programming, post-increment by 2 1110 Table Write, start programming 1111 Advance Information DS41297F-page 11 PIC18F2XK20/4XK20 TABLE 2-7: SAMPLE COMMAND SEQUENCE 4-Bit Command Data Payload 1101 3C 40 FIGURE 2-16: Core Instruction Table Write, post-increment by 2 TABLE WRITE, POST-INCREMENT TIMING DIAGRAM (1101) P2 1 2 3 4 P2A P2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 P3 PGD 1 0 1 1 0 0 0 0 4-bit Command 0 0 0 1 0 0 0 1 4 C 16-bit Data Payload 1 1 1 0 0 n n n n 3 Fetch Next 4-bit Command PGD = Input DS41297F-page 12 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 3.0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. In all cases, except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit only be set immediately prior to a program or erase. 3.1 3.1.1 ICSP Erase HIGH-VOLTAGE ICSP BULK ERASE Erasing code or data EEPROM is accomplished by configuring two Bulk Erase Control registers located at 3C0004h and 3C0005h. Code memory may be erased portions at a time, or the user may erase the entire device in one action. Bulk Erase operations will also clear any code-protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. If data EEPROM is code-protected (CPD = 0), the user must request an erase of data EEPROM (e.g., 0084h as shown in Table 3-1). TABLE 3-1: BULK ERASE OPTIONS Description Data (3C0005h:3C0004h) Chip Erase 0F8Fh Erase User ID 0088h Erase Data EEPROM 0084h Erase Boot Block 0081h Erase Config Bits 0082h Erase Code EEPROM Block 0 0180h Erase Code EEPROM Block 1 0280h Erase Code EEPROM Block 2 0480h Erase Code EEPROM Block 3 0880h The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. Note: TABLE 3-2: BULK ERASE COMMAND SEQUENCE 4-Bit Command Data Payload 0000 0E 3C MOVLW 3Ch 0000 6E F8 MOVWF TBLPTRU 0000 0E 00 MOVLW 00h 0000 6E F7 MOVWF TBLPTRH 0000 0E 05 MOVLW 05h 0000 6E F6 MOVWF TBLPTRL 1100 0F 0F Write 0Fh to 3C0005h 0000 0E 3C MOVLW 3Ch 0000 6E F8 MOVWF TBLPTRU 0000 0E 00 MOVLW 00h 0000 6E F7 MOVWF TBLPTRH 0000 0E 04 MOVLW 04h 0000 6E F6 MOVWF TBLPTRL 1100 8F 8F Write 8F8Fh TO 3C0004h to erase entire device. 0000 00 00 NOP 0000 00 00 Hold PGD low until erase completes. FIGURE 3-1: The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the NOP command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle but PGD must be held low. (c) 2009 Microchip Technology Inc. A Bulk Erase is the only way to reprogram code-protect bits from an "on" state to an "off" state. Advance Information Core Instruction BULK ERASE FLOW Start Write 0F0Fh to 3C0005h Write 8F8Fh to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done DS41297F-page 13 PIC18F2XK20/4XK20 FIGURE 3-2: BULK ERASE TIMING DIAGRAM P10 1 2 3 4 2 1 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2 n n PGC PGD 0 0 1 1 4-bit Command P5 P5A P5 1 1 0 0 16-bit Data Payload 0 0 0 0 4-bit Command P5A 0 0 0 0 16-bit Data Payload P11 0 0 0 0 4-bit Command Erase Time 16-bit Data Payload PGD = Input 3.1.2 LOW-VOLTAGE ICSP BULK ERASE When using low-voltage ICSP, the part must be supplied by the voltage specified in parameter D111 if a Bulk Erase is to be executed. All other Bulk Erase details as described above apply. If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit, refer to the erase methodology described in Section 3.1.3 "ICSP Row Erase" and Section 3.2.1 "Modifying Code Memory". If it is determined that a data EEPROM erase must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.3 "Data EEPROM Programming" and write `1's to the array. 3.1.3 Regardless of whether high or low-voltage ICSP is used, it is possible to erase one row (64 bytes of data), provided the block is not code or write-protected. Rows are located at static boundaries beginning at program memory address 000000h, extending to the internal program memory limit (see Section 2.3 "Memory Maps"). The Row Erase duration is self-timed. After the WR bit in EECON1 is set, two NOPs are issued. Erase starts upon the 4th PGC of the second NOP. It ends when the WR bit is cleared by hardware. The code sequence to Row Erase a PIC18F2XK20/ 4XK20 device is shown in Table 3-3. The flowchart shown in Figure 3-3 depicts the logic necessary to completely erase a PIC18F2XK20/4XK20 device. The timing diagram for Row Erase is identical to the data EEPROM write timing shown in Figure 3-7. Note: DS41297F-page 14 ICSP ROW ERASE Advance Information The TBLPTR register can point at any byte within the row intended for erase. (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 3-3: 4-bit Command ERASE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 8E A6 9C A6 84 A6 0000 0000 0000 BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 2: Point to first row in code memory. 6A F8 6A F7 6A F6 0000 0000 0000 CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 3: Enable erase and erase single row. 88 A6 82 A6 00 00 00 00 0000 0000 0000 0000 BSF BSF NOP NOP EECON1, FREE EECON1, WR Erase starts on the 4th clock of this instruction Step 4: Poll WR bit. Repeat until bit is clear. 0000 0000 0000 0010 50 A6 6E F5 00 00 <MSB><LSB> MOVF EECON1, W, 0 MOVWF TABLAT NOP Shift out data(1) Step 5: Hold PGC low for time P10. Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased. Step 7: Disable writes. 0000 Note 1: 94 A6 BCF EECON1, WREN See Figure 4-4 for details on shift out data timing. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 15 PIC18F2XK20/4XK20 FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Row Erases Perform Erase Sequence Addr = Addr + 64 WR Bit Clear? No Yes No All Rows done? Yes Done DS41297F-page 16 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 3.2 Code Memory Programming Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write and erase buffer sizes shown in Table 3-4 can be mapped to any location of the same size beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the Table Pointer. The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued (4-bit command, `1111'), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. TABLE 3-4: After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence to program a PIC18F2XK20/ 4XK20 device is shown in Table 3-5. The flowchart shown in Figure 3-4 depicts the logic necessary to completely write a PIC18F2XK20/4XK20 device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5. Note: The TBLPTR register must point to the same region when initiating the programming sequence as it did when the write buffers were loaded. WRITE AND ERASE BUFFER SIZES Devices (Arranged by Family) PIC18F26K20, PIC18F46K20 Write Buffer Size (bytes) Erase Size (bytes) 64 64 PIC18F24K20, PIC18F25K20, PIC18F44K20, PIC18F45K20 32 64 PIC18F23K20, PIC18F43K20 16 64 TABLE 3-5: 4-bit Command WRITE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 0000 8E A6 9C A6 84 A6 BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Point to row to write. 0000 0000 0000 0000 0000 0000 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 Step 3: Load write buffer. Repeat for all but the last two bytes. 1101 <MSB><LSB> Write 2 bytes and post-increment address by 2. Step 4: Load write buffer for last two bytes and start programming. 1111 0000 <MSB><LSB> 00 00 Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 17 PIC18F2XK20/4XK20 FIGURE 3-4: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> N=N+1 All bytes written? No Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All locations done? No Yes Done FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING DIAGRAM (1111) P10 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 1 2 3 (1) P9 P5A P5 PGD 1 1 1 1 4-bit Command n n n n n n n n 16-bit Data Payload 0 0 0 0 4-bit Command 0 Programming Time 0 0 16-bit Data Payload PGD = Input Note 1: Use P9A for User ID and Configuration Word programming. DS41297F-page 18 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 3.2.1 MODIFYING CODE MEMORY The previous programming example assumed that the device has been Bulk Erased prior to programming (see Section 3.1.1 "High-Voltage ICSP Bulk Erase"). It may be the case, however, that the user wishes to modify only a section of an already programmed device. The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 "Verify Code Memory and ID Locations") and buffered. Modifications can be made on this buffer. Then, the block of code memory that was read out must be erased and rewritten with the modified data. The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence. TABLE 3-6: MODIFYING CODE MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS Step 2: Read code memory into buffer (Section 4.1 "Read Code Memory, ID Locations and Configuration Bits"). Step 3: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 4: Enable memory writes and setup an erase. 0000 0000 84 A6 88 A6 BSF BSF EECON1, WREN EECON1, FREE 88 A6 82 A6 00 00 00 00 BSF BSF NOP NOP EECON1, FREE EECON1, WR Step 5: Initiate erase. 0000 0000 0000 0000 Erase starts on the 4th clock of this instruction Step 6: Poll WR bit. Repeat until bit is clear. 0000 0000 0000 0000 50 A6 6E F5 00 00 <MSB><LSB> MOVF EECON1, W, 0 MOVWF TABLAT NOP Shift out data(1) Step 7: Load write buffer. The correct bytes will be selected based on the Table Pointer. 0000 0000 0000 0000 0000 0000 1101 * * * 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> * * * <MSB><LSB> 00 00 MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[8:15]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes (see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 8: Disable writes. 0000 94 A6 (c) 2009 Microchip Technology Inc. BCF EECON1, WREN Advance Information DS41297F-page 19 PIC18F2XK20/4XK20 3.3 FIGURE 3-6: Data EEPROM Programming PROGRAM DATA FLOW Start Data EEPROM is accessed one byte at a time via an Address Pointer (register pair EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is written by loading EEADRH:EEADR with the desired memory location, EEDATA with the data to be written and initiating a memory write by appropriately configuring the EECON1 register. A byte write automatically erases the location and writes the new data (erase-before-write). Set Address Set Data Enable Write When using the EECON1 register to perform a data EEPROM write, both the EEPGD and CFGS bits must be cleared (EECON1<7:6> = 00). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done prior to initiating a write sequence. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). Start Write Sequence The write begins on the falling edge of the 24th PGC after the WR bit is set. It ends when the WR bit is cleared by hardware. Yes No done? After the programming sequence terminates, PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. FIGURE 3-7: No WR bit clear? Yes Done DATA EEPROM WRITE TIMING DIAGRAM P10 1 2 3 4 1 2 1 15 16 2 PGC PGD 0 0 0 P5A P5A P5 P11A n 0 4-bit Command 2 NOP commands BSF EECON1, WR Poll WR bit, Repeat until Clear (see below) n 16-bit Data Payload PGD = Input 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 PGC P5 P5 P5A P5A Poll WR bit PGD 0 0 0 0 4-bit Command 0 MOVF EECON1, W, 0 0 0 0 4-bit Command PGD = Input DS41297F-page 20 Advance Information MOVWF TABLAT Shift Out Data (see Figure 4-4) PGD = Output (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 3-7: PROGRAMMING DATA MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 9E A6 9C A6 0000 0000 BCF EECON1, EEPGD BCF EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E <Addr> 6E A9 OE <AddrH> 6E AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH Step 3: Load the data to be written. 0E <Data> 6E A8 0000 0000 MOVLW <Data> MOVWF EEDATA Step 4: Enable memory writes. 0000 84 A6 BSF EECON1, WREN 82 A6 00 00 00 00 BSF EECON1, WR NOP NOP ;write starts on 4th clock of this instruction Step 5: Initiate write. 0000 0000 0000 Step 6: Poll WR bit, repeat until the bit is clear. 0000 0000 0000 0010 50 A6 6E F5 00 00 <MSB><LSB> MOVF EECON1, W, 0 MOVWF TABLAT NOP Shift out data(1) Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 94 A6 BCF EECON1, WREN Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 21 PIC18F2XK20/4XK20 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally even after code protection. Note: The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.1 "Modifying Code Memory". As with code memory, the ID locations must be erased before being modified. When VDD is below the minimum for Bulk Erase operation, ID locations can be cleared with the Row Erase method described in Section 3.1.3 "ICSP Row Erase". Table 3-8 demonstrates the code sequence required to write the ID locations. TABLE 3-8: 4-bit Command WRITE ID SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 0000 8E A6 9C A6 84 A6 BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, WREN Step 2: Set Table Pointer to ID. Load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 DS41297F-page 22 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB><LSB> <MSB><LSB> <MSB><LSB> <MSB><LSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and start programming. hold PGC high for time P9 and low for Advance Information 2. 2. 2. time P10. (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 3.5 Boot Block Programming 3.6 The code sequence detailed in Table 3-5 should be used, except that the address used in "Step 2" will be in the range of 000000h to 0007FFh. Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (`1111') is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-9. See Figure 3-5 for the timing diagram. Note: TABLE 3-9: 4-bit Command The address must be explicitly written for each byte programmed. The addresses can not be incremented in this mode. SET ADDRESS POINTER TO CONFIGURATION LOCATION Data Payload Core Instruction Step 1: Direct access to config memory. 8E A6 8C A6 84 A6 0000 0000 0000 BSF EECON1, EEPGD BSF EECON1, CFGS BSF EECON1, WREN Step 2(1): Set Table Pointer for config byte to be written. Write even/odd addresses. 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB ignored><LSB> 00 00 0E 01 6E F6 <MSB><LSB ignored> 00 00 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 Note 1: MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9A and low for time P10. Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 and P10 Time for Write Delay P9 and P10 Time for Write Done Done (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 23 PIC18F2XK20/4XK20 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, `1001' (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and Configuration registers. Note: When table read protection is enabled, the first read access to a protected block should be discarded and the read repeated to retrieve valid data. Subsequent reads of the same block can be performed normally. The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th TABLE 4-1: READ CODE MEMORY SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Set Table Pointer 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 0000 0000 0000 0000 0000 0000 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory and then shift out on PGD, LSb to MSb 00 00 1001 FIGURE 4-1: TBLRD *+ TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001) 1 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 1 16 2 3 4 PGC P5 P5A P6 P14 (Note 1) PGD 1 0 0 LSb 1 1 2 3 4 5 6 MSb Note 1: n n n Fetch Next 4-bit Command Shift Data Out PGD = Input n PGD = Output PGD = Input Magnification of the high-impedance delay between PGC and PGD is shown in Figure 4-6. DS41297F-page 24 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 4.2 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer's buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer's buffer. Refer to Section 4.1 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading code memory. FIGURE 4-2: The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command can not be used to increment the Table Pointer beyond the code memory space. In a 64-Kbyte device, for example, a post-increment read of address FFFFh will wrap the Table Pointer back to 000000h, rather than point to unimplemented address 010000h. VERIFY CODE MEMORY FLOW Start Set TBLPTR = 0 Set TBLPTR = 200000h Read Low Byte with Post-increment Read Low Byte with Post-Increment Read High Byte with Post-increment Increment Pointer Read High byte with Post-Increment Does Word = Expect data? Does No Word = Expect data? Failure, Report Error Yes No All code memory verified? No Failure, Report Error Yes No All ID locations verified? Yes Yes Done (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 25 PIC18F2XK20/4XK20 4.3 FIGURE 4-3: Verify Configuration Bits READ DATA EEPROM FLOW A configuration address may be read and output on PGD via the 4-bit command, `1001'. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer's memory for verification. Refer to Section 4.1 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading configuration data. 4.4 Start Set Address Read Byte Read Data EEPROM Memory Move to TABLAT Data EEPROM is accessed one byte at a time via an Address Pointer (register pair EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is read by loading EEADRH:EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-4). Shift Out Data No done? Yes Done The command sequence to read a single byte of data is shown in Table 4-2. TABLE 4-2: 4-bit Command READ DATA EEPROM MEMORY Data Payload Core Instruction Step 1: Direct access to data EEPROM. 9E A6 9C A6 0000 0000 BCF EECON1, EEPGD BCF EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0E <Addr> 6E A9 OE <AddrH> 6E AA 0000 0000 0000 0000 MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH Step 3: Initiate a memory read. 80 A6 0000 BSF EECON1, RD Step 4: Load data into the Serial Data Holding register. 50 A8 6E F5 00 00 <MSB><LSB> 0000 0000 0000 0010 Note 1: MOVF EEDATA, W, 0 MOVWF TABLAT NOP Shift Out Data(1) The <LSB> is undefined. The <MSB> is the data. DS41297F-page 26 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 FIGURE 4-4: 1 SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 (Note 1) 2 1 14 15 16 3 4 PGC P5 P5A P6 P14 (Note 1) PGD 0 1 0 LSb 1 0 2 3 4 5 MSb 6 Note 1: PGD = Output HIGH-IMPEDANCE DELAY P3 n PGD = Input PGC MSb n 4.6 Blank Check The term "Blank Check" means to verify that the device has no programmed memory cells. All memories must be verified: code memory, data EEPROM, ID locations and Configuration bits. The device ID registers (3FFFFEh:3FFFFFh) should be ignored. 2 1 A "blank" or "erased" memory cell will read as a `1'. Therefore, Blank Checking a device merely means to verify that all bytes read as FFh except the Configuration bits. Unused (reserved) Configuration bits will read `0' (programmed). Refer to Table 5-1 for blank configuration expect data for the various PIC18F2XK20/ 4XK20 devices. n P19 4.5 n Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 4-5. FIGURE 4-5: PGD n Fetch Next 4-bit Command Shift Data Out PGD = Input n Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, `0000') and then output on PGD via the 4-bit command, `0010' (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer's memory for verification. Refer to Section 4.4 "Read Data EEPROM Memory" for implementation details of reading data EEPROM. Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 "Read Data EEPROM Memory" and Section 4.2 "Verify Code Memory and ID Locations" for implementation details. FIGURE 4-6: BLANK CHECK FLOW Start Blank Check Device Is device blank? Yes Continue No Abort (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 27 PIC18F2XK20/4XK20 5.0 CONFIGURATION WORD 5.2 The device ID word for the PIC18F2XK20/4XK20 devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. See Table 5-2 for a complete list of device ID values. The PIC18F2XK20/4XK20 devices have several Configuration Words. These bits can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting Configuration Words. These bits may be read out normally, even after read or code protection. See Table 5-1 for a list of Configuration bits and device IDs and Table 5-3 for the Configuration bit descriptions. 5.1 Device ID Word FIGURE 5-1: READ DEVICE ID WORD FLOW User ID Locations Start A user may store identification information (ID) in eight ID locations mapped in 200000h:200007h. It is recommended that the Most Significant nibble of each ID be Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte with Post-Increment Done TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value FOSC2 FOSC1 FOSC0 00-- 0111 Bit 3 300001h CONFIG1H IESO FCMEN -- -- FOSC3 300002h CONFIG2L -- -- -- BORV1 BORV0 300003h CONFIG2H -- -- -- 300005h CONFIG3H MCLRE -- -- -- BOREN1 BOREN0 PWRTEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---1 1111 WDTEN ---1 1111 HFOFST LPT1OSC PBADEN CCP2MX 1--- 1011 300006h CONFIG4L DEBUG XINST -- -- -- LVP -- STVREN 10-- -1-1 300008h CONFIG5L -- -- -- -- CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- 30000Ah CONFIG6L -- -- -- -- WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- 30000Ch CONFIG7L -- -- -- -- 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 See Table 5-2 3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 See Table 5-2 Legend: Note 1: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. These bits are only implemented on specific devices. Refer to Section 2.3 "Memory Maps" to determine which bits apply based on available memory. DEVID registers are read-only and cannot be programmed by the user. 2: DS41297F-page 28 EBTR3(1) EBTR2(1) Advance Information -- -- 111- ---- EBTR1 EBTR0 ---- 1111 (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 5-2: DEVICE ID VALUE Device ID Value Device PIC18F23K20 Note: DEVID2 DEVID1 20h 111x xxxx PIC18F24K20 20h 101x xxxx PIC18F25K20 20h 011x xxxx PIC18F26K20 20h 001x xxxx PIC18F43K20 20h 110x xxxx PIC18F44K20 20h 100x xxxx PIC18F45K20 20h 010x xxxx PIC18F46K20 20h 000x xxxx The `x's in DEVID1 contain the device revision code. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 29 PIC18F2XK20/4XK20 TABLE 5-3: Bit Name PIC18F2XK20/4XK20 BIT DESCRIPTIONS Configuration Words Description IESO CONFIG1H Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled FOSC<3:0> CONFIG1H Oscillator Selection bits 11xx = External RC oscillator, CLKOUT function on RA6 101x = External RC oscillator, CLKOUT function on RA6 1001 = HFINTOSC, CLKOUT function on RA6, port function on RA7 1000 = HFINTOSC, port function on RA6, port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKOUT function on RA6 0011 = External RC oscillator, CLKOUT function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator BORV<1:0> CONFIG2L Brown-out Reset Voltage bits 11 = VBOR set to 1.8V 10 = VBOR set to 2.2V 01 = VBOR set to 2.7V 00 = VBOR set to 3.0V BOREN<1:0> CONFIG2L Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software PWRTEN CONFIG2L Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 . DS41297F-page 30 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 5-3: Bit Name PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description WDTEN CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) MCLRE CONFIG3H MCLR Pin Enable bit 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled HFOFST CONFIG3H HFINTOSC Fast Start 1 = HFINTOSC output is not delayed 0 = HFINTOSC output is delayed until oscillator is stable (IOFS = 1) LPT1OSC CONFIG3H Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation PBADEN CONFIG3H PORTB A/D Enable bit 1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset 0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DEBUG CONFIG4L Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug XINST CONFIG4L Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) LVP CONFIG4L Low-Voltage Programming Enable bit 1 = Low-Voltage Programming enabled, RB5 is the PGM pin 0 = Low-Voltage Programming disabled, RB5 is an I/O pin STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled . (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 31 PIC18F2XK20/4XK20 TABLE 5-3: Bit Name PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description CP3 CONFIG5L Code Protection bits (Block 3 code memory area) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected CP2 CONFIG5L Code Protection bits (Block 2 code memory area) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0 CONFIG5L Code Protection bits (Block 0 code memory area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected CPD CONFIG5H Code Protection bits (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected CPB CONFIG5H Code Protection bits (Boot Block memory area) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected WRT3 CONFIG6L Write Protection bits (Block 3 code memory area) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected WRT2 CONFIG6L Write Protection bits (Block 2 code memory area) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRTD CONFIG6H Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB CONFIG6H Write Protection bit (Boot Block memory area) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected WRTC CONFIG6H Write Protection bit (Configuration registers) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected . DS41297F-page 32 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 5-3: Bit Name PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area) 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area) 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area) 1 = Boot Block is not protected from table reads executed in other blocks 0 = Boot Block is protected from table reads executed in other blocks DEV<10:3> DEVID2 Device ID bits These bits are used with the DEV<2:0> bits in the DEVID1 register to identify part number. DEV<2:0> DEVID1 Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. REV<4:0> DEVID1 Revision ID bits These bits are used to indicate the revision of the device. . (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 33 PIC18F2XK20/4XK20 5.3 Single-Supply ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Programming. The LVP bit defaults to a `1' (enabled) from the factory. If Single-Supply Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode, where MCLR/VPP/RE3 is raised to VIHH. Once the LVP bit is programmed to a `0', only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/ VPP/RE3 pin. 2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O. 5.4 Embedding Configuration Word Information in the HEX File To allow portability of code, a PIC18F2XK20/4XK20 programmer is required to read the Configuration Word locations from the hex file. If Configuration Word information is not present in the hex file, then a simple warning message should be issued. Similarly, while saving a hex file, all Configuration Word information must be included. An option to not include the Configuration Word information may be provided. When embedding Configuration Word information in the hex file, it should start at address 300000h. 5.5 Embedding Data EEPROM Information In the HEX File To allow portability of code, a PIC18F2XK20/4XK20 programmer is required to read the data EEPROM information from the hex file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a hex file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 5.6 Checksum Computation The checksum is calculated by summing the following: * The contents of all code memory locations * The Configuration Word, appropriately masked * ID locations (Only if any portion of program memory is code-protected) The Least Significant 16 bits of this sum are the checksum. Code protection limits access to program memory by both external programmer (code-protect) and code execution (table read protect). The ID locations, when included in a code protected checksum, contain the checksum of an unprotected part. The unprotected checksum is distributed: one nibble per ID location. Each nibble is right justified. Table 5-4 describes how to calculate the checksum for each device. Note: Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. DS41297F-page 34 Advance Information The checksum calculation differs depending on the code-protect setting. Since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The Configuration Word and ID locations can always be read. (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 5-4: CHECKSUM COMPUTATION CodeProtect Device Blank Value 0xAA at 0 and Max Address None SUM[0000:01FF]+SUM[0200:0FFF]+SUM[1000:1FFF]+ (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+ (CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+ (CONFIG7L & 03h)+(CONFIG7H & 40h) E33Eh E294h Boot Block SUM[0200:0FFF]+SUM[1000:1FFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 03h)+(CONFIG5H & C0h)+ (CONFIG6L & 03h)+(CONFIG6H & E0h)+(CONFIG7L & 03h)+ (CONFIG7H & 40h)+SUM_ID E520h E4C6h SUM[1000:1FFF]+(CONFIG1L & 00h)+(CONFIG1H & CFh)+ (CONFIG2L & 1Fh)+(CONFIG2H & 1F)+(CONFIG3L & 00h)+ (CONFIG3H & 8Fh)+(CONFIG4L & C5h)+(CONFIG4H & 00h)+ (CONFIG5L & 03h)+(CONFIG5H & C0h)+(CONFIG6L & 03h)+ (CONFIG6H & E0h)+(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID F31Fh F2C5h All (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+ (CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+ (CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID 031Dh 0318h None SUM[0000:07FF]+SUM[0800:1FFF]+SUM[2000:3FFF]+ (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+ (CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+ (CONFIG7L & 03h)+(CONFIG7H & 40h) C33Eh C294h Boot Block SUM[0800:1FFF]+SUM[2000:3FFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 03h)+(CONFIG5H & C0h)+ (CONFIG6L & 03h)+(CONFIG6H & E0h)+(CONFIG7L & 03h)+ (CONFIG7H & 40h)+SUM_ID CB1Eh CAC4h SUM[2000:3FFF]+(CONFIG1L & 00h)+(CONFIG1H & CFh)+ (CONFIG2L & 1Fh)+(CONFIG2H & 1F)+(CONFIG3L & 00h)+ (CONFIG3H & 8Fh)+(CONFIG4L & C5h)+(CONFIG4H & 00h)+ (CONFIG5L & 03h)+(CONFIG5H & C0h)+(CONFIG6L & 03h)+ (CONFIG6H & E0h)+(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID E31Dh E2C3h (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+ (CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+ (CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID 031Bh 0316h PIC18FX3K20 Boot/ Block 0 PIC18FX4K20 Boot/ Block 0 All Legend: Checksum Item CONFIGx SUM[a:b] SUM_ID + & = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 35 PIC18F2XK20/4XK20 TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED) CodeProtect Device Blank Value 0xAA at 0 and Max Address None SUM[0000:07FF]+SUM[0800:1FFF]+SUM[2000:3FFF]+ SUM[4000:5FFF]+SUM[6000:7FFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+ (CONFIG6L & 0Fh)+(CONFIG6H & E0h)+(CONFIG7L & 0Fh)+ (CONFIG7H & 40h) 8362h 82B8h Boot Block SUM[0800:1FFF]+SUM[2000:3FFF]+SUM[4000:5FFF]+SUM[6000:7FFF ]+ (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+ (CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+ (CONFIG7L & 0Fh)+(CONFIG7H & 40h)+SUM_ID 8B35h 8AEAh Boot/ Block 0/ Block 1 SUM[4000:5FFF]+SUM[6000:7FFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+ (CONFIG6L & 0Fh)+(CONFIG6H & E0h)+(CONFIG7L & 0Fh)+ (CONFIG7H & 40h)+SUM_ID C332h C2E7h All (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+ (CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+ (CONFIG7L & 0Fh)+(CONFIG7H & 40h)+SUM_ID 0326h 0330h PIC18FX5K20 Legend: Checksum Item CONFIGx SUM[a:b] SUM_ID + & DS41297F-page 36 = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED) CodeProtect Device Blank Value 0xAA at 0 and Max Address None SUM[0000:07FF]+SUM[0800:3FFF]+SUM[4000:7FFF]+ SUM[8000:BFFF]+SUM[C000:FFFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+ (CONFIG6L & 0Fh)+(CONFIG6H & E0h)+(CONFIG7L & 0Fh)+ (CONFIG7H & 40h) 0362h 02B8h Boot Block SUM[0800:3FFF]+SUM[4000:7FFF]+SUM[8000:BFFF]+SUM[C000:FFF F]+ (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+ (CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+ (CONFIG7L & 0Fh)+(CONFIG7H & 40h)+SUM_ID 0B2Dh 0AE2h Boot/ Block 0/ Block 1 SUM[3000:BFFF]+SUM[C000:FFFF]+(CONFIG1L & 00h)+ (CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+ (CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+ (CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+ (CONFIG6L & 0Fh)+(CONFIG6H & E0h)+(CONFIG7L & 0Fh)+ (CONFIG7H & 40h)+SUM_ID 832Ah 82DFh All (CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+ (CONFIG4L & C5h)+(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+ (CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+ (CONFIG7L & 0Fh)+(CONFIG7H & 40h)+SUM_ID 031Eh 0328h PIC18FX6K20 Legend: Checksum Item CONFIGx SUM[a:b] SUM_ID + & = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 37 PIC18F2XK20/4XK20 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/ VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. D110 Sym. Characteristic Min. Max. Units Conditions VIHH High-Voltage Programming Voltage on MCLR/VPP/RE3 VDD + 4.5 9 V D110A VIHL Low-Voltage Programming Voltage on MCLR/VPP/RE3 1.80 3.60 V D111 VDD Supply Voltage During Programming 1.80 3.60 V Row Erase/Write 2.7 3.60 V Bulk Erase operations D112 IPP Programming Current on MCLR/VPP/RE3 -- 300 A D113 IDDP Supply Current During Programming -- 10 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage -- 0.6 V IOL = X.X mA @ 2.7V D090 VOH Output High Voltage VDD - 0.7 -- V IOH = -Y.Y mA @ 2.7V D012 CIO Capacitive Loading on I/O pin (PGD) -- 50 pF To meet AC specifications P1 TR MCLR/VPP/RE3 Rise Time to enter Program/Verify mode -- 1.0 s (Note 1) P2 TPGC Serial Clock (PGC) Period 100 -- ns VDD = 3.6V 1 -- s VDD = 1.8V P2A P2B TPGCL TPGCH Serial Clock (PGC) Low Time Serial Clock (PGC) High Time 40 -- ns VDD = 3.6V 400 -- ns VDD = 1.8V 40 -- ns VDD = 3.6V 400 -- ns VDD = 1.8V 15 -- ns P3 TSET1 Input Data Setup Time to Serial Clock P4 THLD1 Input Data Hold Time from PGC 15 -- ns P5 TDLY1 Delay between 4-bit Command and Command Operand 40 -- ns P5A TDLY1A Delay between 4-bit Command Operand and next 4-bit Command 40 -- ns P6 TDLY2 Delay between Last PGC of Command Byte to First PGC of Read of Data Word 20 -- ns P9 TDLY5 PGC High Time (minimum programming time) 1 -- ms Externally Timed P9A TDLY5A PGC High Time ms Configuration Word programming time P10 TDLY6 PGC Low Time after Programming (high-voltage discharge time) P11 TDLY7 Delay to allow Self-Timed Data Write or Bulk Erase to occur P11A TDRWT Data Write Polling Time Note 1: 5 200 -- s 5 -- ms 4 -- ms Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. DS41297F-page 38 Advance Information (c) 2009 Microchip Technology Inc. PIC18F2XK20/4XK20 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/ VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym. Characteristic Min. Max. Units 2 -- s P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3 P13 TSET2 VDD Setup Time to MCLR/VPP/RE3 100 -- ns P14 TVALID Data Out Valid from PGC 10 -- ns P15 TSET3 PGM Setup Time to MCLR/VPP/RE3 2 -- s P16 TDLY8 Delay between Last PGC and MCLR/VPP/RE3 0 -- s P17 THLD3 MCLR/VPP/RE3 to VDD -- 100 ns P18 THLD4 MCLR/VPP/RE3 to PGM 0 -- s P19 THIZ Delay from PGC to PGD High-Z 3 10 nS P20 TPPDP Hold time after VPP changes 5 -- s Note 1: Conditions Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. (c) 2009 Microchip Technology Inc. Advance Information DS41297F-page 39 PIC18F2XK20/4XK20 NOTES: DS41297F-page 40 Advance Information (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. 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