PIC18F26K20-I/SO - Microchip Technology

PIC18F2XK20/4XK20

1.0 DEVICE OVERVIEW

This document includes the programming

specifications for the following devices:

• PIC18F23K20

• PIC18F24K20

• PIC18F25K20

• PIC18F26K20

• PIC18F43K20

• PIC18F44K20

• PIC18F45K20

• PIC18F46K20

2.0 PROGRAMMING OVERVIEW

The PIC18F2XK20/4XK20 devices can be pro-

gramme d using either the high-v olt age In-C ircuit Seria l

Programming™ (ICSP™) method or the low-voltage

ICSP method. Both methods can be done with the

device in the users’ system. The low-voltage ICSP

method is slightly different than the high-voltage

method and these differences are noted where appl ica-

ble. This programming specification applies to the

PIC18F2XK20/4XK20 devices in all package types.

2.1 Hardware Requirements

In High-Volta ge IC SP mode , the PIC18F 2XK20 /4XK2 0

devices require two programmable power supplies:

one for VDD and on e for MCL R/VPP/RE3. Both suppl ies

should have a minimum resolution of 0.25V. Refer to

Section 6.0 “AC/DC Characteristics Timing

Requirements for Program/Verify Test Mode” for

additional hardware parameters.

2.1.1 LOW-VOLTAGE ICSP

PROGRAMMING

In Low-Voltage ICSP mode, the PIC18F2XK20/4XK20

device s can be program med using a single V DD source

in the operating range. The MCLR/VPP/RE3 does not

have to be brought to a different voltage, but can

instead be lef t at the no rmal opera ting volt age. Refer to

Section 6.0 “AC/DC Characteristics Timing

Requirements for Program/Verify Test Mode” for

additional hardware parameters.

2.2 Pin Diagrams

The pin diagrams for the PIC18F2XK20/4XK20 family

are shown in Figure 2-3 and Figure 2-4.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XK20/4XK20

Pin Name During Programming

Pin Name Pin Type Pin Description

MCLR/VPP/RE3 VPP P Prog ramming Enable

VDD(2) VDD P Power Supply

VSS(2) VSS PGround

RB5 PGM I Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’(1)

RB6 PGC I Serial Clock

RB7 PGD I/O Serial Data

Legend: I = Input, O = Output, P = Power

Note 1: See Figure 5-1 for more information.

2: All power supply (VDD) and ground (VSS) pins must be connected.

Flash Memory Programming Specification

PIC18F2XK20/4XK20

FIGURE 2-1: 28-PIN SDIP, SSOP AND SOIC PIN DIAGRAMS

FIGURE 2-2: 28-PIN QFN PIN DIAGRAMS

14 15

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5

VSS

OSC1

OSC2

RC0

RC1

RC2

RC3

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

PIC18F2XK20

SDIP, SSOP, SOIC (300 MIL)

Note: The following devices are included in 28-pin SDIP, SSOP and SOIC parts: PIC18F23K20, PIC18F24K20,

PIC18F25K20, PIC18F26K20.

10 11

12 13 14 15

716

232425262728

RC0

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5

VSS

OSC1

OSC2

RC1

RC2

RC3

PIC18F2XK20

Note: The following devices are included in 28-pin QFN parts: PIC18F23K20, PIC18F24K20, PIC18F25K20,

PIC18F26K20.

28-Pin QFN

PIC18F2XK20/4XK20

FIGURE 2-3: 40-PIN PDIP PIN DIAGRAMS

FIGURE 2-4: 44-PIN TQFP PIN DIAGRAMS

40-PIN PDIP (600 MIL)

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RD7

RD6

RD5

RD4

RC7

RC6

RC5

RC4

RD3

RD2

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

VDD

VSS

OSC1

OSC2

RC0

RC1

RC2

RC3

RD0

RD1

PIC18F4XK20

Note: The following devices are included in 40-pin PDIP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,

PIC18F46K20.

44-PIN TQFP

RA3

RA2

RA1

RA0

MCLR/VPP/RE3

RB7/PGD

RB6/PGC

RB5/PGM

RB4

NC RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

OSC2

OSC1

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

VSS

VDD

RB0

RB1

RB2

RB3

RD7 5

4PIC18F4XK20

Note: The following devices are included in 44-pin TQFP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,

PIC18F46K20.

PIC18F2XK20/4XK20

FIGURE 2-5: 44-PIN QFN PIN DIAGRAMS

44-PIN QFN

Note: The following devices are included in 44-pin QFN parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,

PIC18F46K20.

RA3

RA2

RA1

RA0

MCLR/VPP/RE3

RB7/PGD

RB6/PGC

RB5/PGM

NC RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

OSC2

OSC1

VSS

VDD

RA5

RA4

RC7

RD4

RD5

RD6

VSS

VDD

RB0

RB1

RB2

RB3

RD7 5

4VSS

VDD

RB4

RE0

RE1

RE2

PIC18F4XK20

PIC18F2XK20/4XK20

2.3 Memory Map s

For the PIC18FX3K20 devices, the code memory

spa ce extends from 000 0h to 01FFFh (8 Kbytes) in two

4-Kbyte blocks. Addresses 0000h through 01FFh,

however, define a “Boot Block” region that is treated

sep arately from Blo ck 0. All of these blocks define code

protection boundaries within the code memory space.

TABLE 2-2: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-6: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX3K20 DEVICES

Device Code Memory Size (Bytes)

PIC18F23K20 000000h-001FFFh (8K)

PIC18F43K20

000000h

200000h

3FFFFFh

01FFFFh

Note: Sizes of memory areas are not to scale.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

8Kbytes

(PIC18FX3K20) Address

Range

Boot Block 000000h

0001FFh

Block 0 000200h

000FFFh

Block 1 001000h

001FFFh

Unimplemented

Read ‘0’s

002000h

01FFFFh

PIC18F2XK20/4XK20

For PIC18FX4K20 devices, the code memory space

extends from 000000h to 003FFFh (16 Kbytes) in two

8-Kbyte b locks. Addre sses 00000 0h throu gh 0007FF h,

however, define a “Boot Block” region that is treated

separately from Block 0. All of these blocks define code

protection boundaries within the code memory space.

TABLE 2-3: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-7: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX4K20 DEVICES

Device Code Memory Size (Bytes)

PIC18F24K20 000000h-003FFFh (16K)

PIC18F44K20

000000h

200000h

3FFFFFh

01FFFFh

Note: Sizes of memory areas not to scale.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

16 Kbytes

(PIC18FX4K20) Address

Range

Boot Block 000000h

0007FFh

Block 0 000800h

001FFFh

Block 1 002000h

003FFFh

Unimplemented

Read ‘0’s

004000h

01FFFFh

PIC18F2XK20/4XK20

For PIC18FX5K20 devices, the code memory space

extends from 000000h to 007FFFh (32 Kbytes) in four

8-Kbyte bloc ks. Address es 000000h t hrough 000 7FFh,

however, define a “Boot Block” region that is treated

sep arately from Blo ck 0. All of these blocks define code

protection boundaries within the code memory space.

TABLE 2-4: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-8: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5K20 DEVICES

Device Code Memory Size (Bytes)

PIC18F25K20 000000h-007FFFh (32K)

PIC18F45K20

000000h

200000h

3FFFFFh

01FFFFh

Note: Sizes of memory areas not to scale.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

32 Kbytes

(PIC18FX5K20) Address

Range

Boot Block 000000h

0007FFh

Block 0 000800h

001FFFh

Block 1 002000h

003FFFh

Block 2 004000h

005FFFh

Block 3 006000h

007FFFh

Unimplemented

Read ‘0’s

01FFFFh

PIC18F2XK20/4XK20

For PIC18FX6K20 devices, the code memory space

extends from 000000h to 00FFFFh (64 Kbytes) in four

16-Kbyte blocks. Addresses 000000h through

0007FFh, how e ve r, define a “Bo ot Bl ock” region that i s

treated separately from Block 0. All of these blocks

define code protection boundaries within the code

memor y space.

TABLE 2-5: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-9: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX6K20 DEVICES

Device Code Memory Size (Bytes)

PIC18F26K20 000000h-00FFFFh (64K)

PIC18F46K20

000000h

200000h

3FFFFFh

01FFFFh

Note: Sizes of memory areas not to scale.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

32 Kbytes

(PIC18FX6K20) Address

Range

Boot Block 000000h

0007FFh

Block 0 000800h

003FFFh

Block 1 004000h

007FFFh

Block 2 008000h

00BFFFh

Block 3 00C000h

00FFFFh

Unimplemented

Read ‘0’s

01FFFFh

PIC18F2XK20/4XK20

In addition to the code memory space, there are three

blocks in the configuration and ID space that are

accessible to the user through table reads and table

writes . Their locations in the memory ma p are shown in

Figure 2-10.

Users may store identification information (ID) in eight

ID registers. These ID registers are mapped in

addresses 200000h thro ugh 200007h. The ID locations

read out normally , even after code protection is applied.

Locations 300000h through 30000Dh are reserved for

the Confi guratio n bits . These bi t s select var iou s devic e

options and are described in Section 5.0 “Configura-

tion Word”. These Configuration bits read out

normally, even after code protection.

Locatio ns 3FFFF Eh and 3FFF FFh ar e reserved for the

device ID bits. Thes e bits may be us ed by the program-

mer to identify what device type is being programmed

and are described in Section 5.0 “Configuration

Word”. These device ID bits read out normally, even

after code protection.

2.3.1 MEMOR Y ADDRESS POINTER

Memory in the address space, 0000000h to 3FFFFFh,

is addressed via the Table Pointer register, which is

comprised of three Pointer registers:

• TBLPTRU, at RAM address 0FF8h

• TBLPTRH, at RAM address 0FF7h

• TBLPTRL, at RAM address 0FF6h

The 4-bit command, ‘0000’ (core instruction), is used to

load the Table Pointer prior to using any read or write

operations.

FIGURE 2-10: CONFIG URATION AND ID LOCATIONS FOR PIC18F2XK20/4XK20 DEVICES

TBLPTRU TBLPTRH TBLPTRL

Addr[21:16] Addr[15:8] Addr[7:0]

ID Location 1 200000h

ID Location 2 200001h

ID Location 3 200002h

ID Location 4 200003h

ID Location 5 200004h

ID Location 6 200005h

ID Location 7 200006h

ID Location 8 200007h

CONFIG1L 300000h

CONFIG1H 300001h

CONFIG2L 300002h

CONFIG2H 300003h

CONFIG3L 300004h

CONFIG3H 300005h

CONFIG4L 300006h

CONFIG4H 300007h

CONFIG5L 300008h

CONFIG5H 300009h

CONFIG6L 30000Ah

CONFIG6H 30000Bh

CONFIG7L 30000Ch

CONFIG7H 30000Dh

Device ID1 3FFFFEh

Device ID2 3FFFFFh

Note: Sizes of memory areas are not to scale.

000000h

1FFFFFh

3FFFFFh

01FFFFh Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

2FFFFFh

PIC18F2XK20/4XK20

2.4 High-Level Overview of the

Programming Process

Figure 2-11 shows the high-level overview of the

programming process. First, a Bulk Erase is performed.

Next, the code memory, ID locations and data

EEPROM are programmed. These memories are then

verified to ensure that programming was successful. If

no errors are detected, the Configuration bits are then

programmed and verified.

FIGURE 2-11 : HIGH-LEVEL

PROGRAMMING FLOW

2.5 Entering and Exiting High-Voltage

ICSP Program/Verify Mode

As shown in Figure 2-12, the High-Voltage ICSP

Program/Verify mode is entered by holding PGC and

PGD low and then raising MCLR/VPP/RE3 to VIHH

(high voltage). Once in this mode, the code memory,

dat a EEPROM , ID l ocatio ns and Configu rati on bit s ca n

be accessed and programmed in serial fashion.

Figure 2-13 shows the exit sequence.

The sequence that enters the device into the Program/

V erify mode places all unused I/Os in the high-impedance

state.

FIGURE 2-12: ENTERING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

FIGURE 2-13: EXITING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

Start

Program Memory

Program IDs

Program Data EE

Verify Program

Veri fy IDs

Verify Data

Program

Configuration Bits

Verify

Configuration Bits

Done

Perform Bulk

Erase

MCLR/VPP/RE3

P12

PGD

PGD = Input

PGC

VDD

D110

P13

MCLR/VPP/RE3

P16

PGD

PGD = Input

PGC

VDD

D110

P17

PIC18F2XK20/4XK20

2.6 Entering and Exiting Low-Voltage

ICSP Program/Verify Mode

When the LVP Configuration bit is ‘1’ (see Section 5.3

“Single-Supply ICSP Programming”), the Low-

V ol tage ICSP m ode is ena bled. As sho wn in Figure 2-14,

Low-Voltage ICSP Program/Verify mode is entered by

holding PGC and PGD low, placing a logic high on PGM

and then raising MCLR/VPP/RE3 to VIH. In this mode, the

RB5/P GM pin is ded icated to the prog ramming functi on

and ceases to be a general purpose I/O pin. Figure 2-15

show s th e e x it sequen ce .

The sequence that enters the device into the Program/

V erify mode places all unused I/Os in the high-impedance

state.

FIGURE 2-14: ENTERING LOW-VOLTAGE

PROGRAM/VERIFY MODE

FIGU RE 2 -1 5: EXITING LOW-VOLTAGE

PROGRAM/VERIFY MODE

2.7 Serial Program/Verify Operation

The PGC pin is used as a clock input pin and the PGD

pin is used for entering command bits and data input/

output during serial operation. Comman ds and data a re

transmitted on the rising edge of PGC, latched on the

falling edge of PGC and are Least Significant bit (LSb)

first.

2.7.1 4-BIT COMMANDS

All instructions are 20 bits, consisting of a leading 4-bit

command followed by a 16-bit operand, which depends

on the type of command being executed. To input a

command, PGC is cycled four times. The commands

needed for programming and verification are shown in

Table 2-6.

Depending on the 4-bit command, the 16-bit operand

represents 16 bits of input data or 8 bits of input data

and 8 bits of output data.

Throughout this speci fic ati on, co mm an ds and data are

presented as illustrated in Table 2-7. The 4-bit com-

mand is shown Most Significant bit (MSb) first. The

command operand, or “Data Payload”, is shown

<MSB><LSB>. Figure 2-16 demonstrates how to

serially present a 20-bit command/operand to the

device.

2.7.2 CORE INSTRUCTION

The core instruction passes a 16-bit instruction to the

CPU core for execution. This is needed to set up

registers as approp riate for us e with other co mmand s.

TABLE 2-6: COMMANDS FOR

PROGRAMMING

MCLR/VPP/RE3

P12

PGD

PGD = Input

PGC

PGM

P15

VDD

VIH

MCLR/VPP/RE3

P16

PGD

PGD = Input

PGC

PGM

P18

VDD

VIH

Description 4-Bit

Command

Core Instruction

(Shift in16-bit instruction) 0000

Shift out TABLAT register 0010

Table R ead 1000

Table Read, post-increm en t 1001

Table Read, post-decrem ent 1010

Table R ead , pre-in cre men t 1011

Table Write 1100

Table Write, post-increment by 2 1101

Table Write, start programming,

post-increment by 2 1110

Table Write, start programming 1111

PIC18F2XK20/4XK20

TABLE 2-7: SAMPLE COMMAND

SEQUENCE

FIGURE 2-16: TABLE WRITE, POST-INCREMENT TIMING DIAGRAM (1101)

4-Bit

Command Data

Payload Core Instruction

1101 3C 40 Table Write,

post-increment by 2

1234

PGC P5

PGD

PGD = Input

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-bit Command

1011

1234

nnnn

P2 P2A

000000 010001111 0

04C3

4-bit Command 16- bit Data Payload

P2B

PIC18F2XK20/4XK20

3.0 DEVICE PROGRAMMING

Programming includes the ability to erase or write the

various memory regions within the device.

In all cases, except high-voltage ICSP Bulk Erase, the

EECON1 register must be configured in order to

operate on a particular memory region.

When using the EECON1 register to act on code

memory , the EEPGD bit must be set (EECON1<7> = 1)

and the CFGS bit must be cleared (EECON1<6> = 0).

The WREN bit must be set (EECON1<2> = 1) to

enable writes of any sort (e.g., erases) and this must be

done prior to initiating a write sequence. The FREE bit

must be set (EECON1<4> = 1) in order to erase the

program space being pointed to by the Table Pointer.

The erase or write sequence is initiated by setting the

WR bit (EECON1<1> = 1). It is strongl y recom me nde d

that the WREN bit only be set immediately prior to a

program or erase.

3.1 ICSP Erase

3.1.1 HIGH-VOLTAGE ICSP BULK ERASE

Erasing code or data EEPROM is accomplished by

configuring two Bulk Erase Control registers located at

3C000 4h an d 3C 000 5h. Code memo ry may be erase d

portions at a time, or the user may erase the entire

device in one action. Bulk Erase operations will also

clear any code-protect settings associated with the

memory block erased. Erase options are detailed in

Table 3-1. If data EEPROM is code-protected

(CPD = 0), the user must request an erase of data

EEPROM (e.g., 0084h as shown in Table 3-1).

TABLE 3-1: BULK ERASE OPTIONS

The actual Bulk Erase function is a self-timed

operation. Once the erase has started (falling edge of

the 4th PGC after the NOP command), serial execution

will cease until the erase completes (parameter P11).

During this time, PGC may continue to toggle but PGD

must be held low.

The code s equence to eras e the entire devic e is shown

in Table 3-2 and the flowchart is shown in Figure 3-1.

TABLE 3-2: BULK ERASE COMMAND

SEQUENCE

FIGURE 3-1: BULK ERASE FLOW

Description Data

(3C0005h:3C0004h)

Chip Erase 0F8Fh

Erase Us er ID 0088h

Erase Data EEPROM 0084h

Erase Boot Block 0081h

Erase Config Bits 0082h

Erase Code EEPROM Block 0 0180h

Erase Code EEPROM Block 1 0280h

Erase Code EEPROM Block 2 0480h

Erase Code EEPROM Block 3 0880h

Note: A Bulk Erase is the only way to reprogram

code-protect bits from an “on” state to an

“off” state.

4-Bit

Command Data

Payload Core Instruction

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU

0000 0E 00 MOVLW 00h

0000 6E F7 MOVWF TBLPTRH

0000 0E 05 MOVLW 05h

0000 6E F6 MOVWF TBLPTRL

1100 0F 0F Write 0Fh to 3C0005h

0000 0E 3C MOVLW 3Ch

0000 6E F8 MOVWF TBLPTRU

0000 0E 00 MOVLW 00h

0000 6E F7 MOVWF TBLPTRH

0000 0E 04 MOVLW 04h

0000 6E F6 MOVWF TBLPTRL

1100 8F 8F Write 8F8Fh TO 3C0004h

to erase entire device.

0000 00 00 NOP

0000 00 00 Hold PGD low until erase

completes.

Start

Done

Write 8F8Fh to

3C0004h to Erase

Entire Device

Write 0F0Fh

Delay P11 + P10

Time

to 3C0005h

PIC18F2XK20/4XK20

FIGURE 3-2: BULK ERASE TIMING DIAGRAM

3.1.2 LOW-VOLTAGE ICSP BULK ERASE

When using low-voltage ICSP, the part must be

suppli ed by the volta ge specified in para meter D11 1 if a

Bulk Erase is to be executed. All other Bulk Erase

details as described above apply.

If it is determined that a program memory erase must

be perform ed at a sup ply vo lta ge below the Bul k Erase

limit, refer to the erase methodology described in

Section 3.1.3 “ICSP Row Erase” and Section 3.2.1

“Modify ing Code Me mory”.

If it is determined that a data EEPROM erase must be

performed at a supply voltage below the Bulk Erase

limit, follow the methodology described in Section 3.3

“Data EEPROM Programming” and write ‘1’s to the

array.

3.1.3 ICSP ROW ERASE

Regardless of whether high or low-voltage ICSP is

used, i t i s pos s ibl e t o e ras e one row (64 by te s of dat a),

provi ded the bl ock is not c ode or wri te-protecte d. Rows

are located at static boundaries beginning at program

memory address 000000h, extending to the internal

program memory limit (see Section 2.3 “Memory

Maps”).

The Row Erase duration is self-timed. After the WR bit

in EECON1 is set, two NOPs are issued. Erase starts

upon the 4th PG C of the secon d NOP. It ends when th e

WR bit is cleared by hardware.

The code sequence to Row Erase a PIC18F2XK20/

4XK20 device is shown in Table 3-3. The flowchart

shown in Figure 3-3 depicts the logic necessary to com-

pletely era se a PIC18F2XK20/4XK20 device. The tim ing

diagram for Row Erase is identical to the data EEPROM

write timing shown in Figure 3-7.

1234 121516 123

PGC

P5 P5A

PGD

PGD = Input

0011

P11

P10

Erase Time

000000

1 2 15 16

123

P5A

0000 n

4-bit Comm an d 4-bit Command 4-bit Command

16-bit

Data Payload

16-bit

Data Payload 16-bit

Data Payload

Note: The TBLPTR register can point at any byte

within the row intended for erase.

PIC18F2XK20/4XK20

TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE

4-bit

Command Data Payload Core Instruction

Step 1: Direct access to code memory and enable writes.

0000

8E A6

9C A6

84 A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, WREN

Step 2: Point to first row in code memory.

0000

6A F8

6A F7

6A F6

CLRF TBLPTRU

CLRF TBLPTRH

CLRF TBLPTRL

Step 3: Enable erase and erase singl e row.

0000

88 A6

82 A6

00 00

BSF EECON1, FREE

BSF EECON1, WR

NOP

NOP Erase starts on the 4th clock of this instruction

Step 4: Poll WR bit. Repeat until bit is clear.

0000

0010

50 A6

6E F5

00 00

MOVF EECON1, W, 0

MOVWF TABLAT

NOP

Shift out data(1)

Step 5: Hold PGC low for time P10.

Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased.

Step 7: Disable writes.

0000 94 A6 BCF EECON1, WREN

Note 1: See Figure 4-4 for details on shift out data timing.

PIC18F2XK20/4XK20

FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW

Done

Start

All

Rows

done?

Yes

Addr = 0

Configure

Device for

Row Erases

Addr = Addr + 64

Perform Eras e

Sequence

WR Bit

Clear? No

Yes

PIC18F2XK20/4XK20

3.2 Code Memory Programming

Programming code memory is accomplished by first

loading data into the write buffer and then initiating a

programming sequence. The write and erase buffer

sizes shown in Ta ble 3- 4 can be m apped to any loca-

tion of the same size b eginni ng at 000 000h. The ac tual

memory write sequence takes the contents of this buf-

fer and programs the proper amount of code memory

that contains the Table Pointer.

The programming duration is externally timed and is

controlled by PGC. After a Start Programming

command is issued (4-bit command, ‘1111’), a NOP is

issued , where th e 4t h PGC is he ld hig h for the dur ation

of the programming time, P9.

After PGC is brought low, the programming sequence

is terminated. PGC must be held low for the time

specified by parameter P10 to allow high-voltage

discharge of the memory array.

The code sequence to program a PIC18F2XK20/

4XK20 device is shown in Table 3-5. The flowchart

shown in Figure 3-4 depicts the logic necessary to

completely write a PIC18F2XK20/4XK20 device. The

timing diagram that details the Start Programming

command and parameters P9 and P10 is shown in

Figure 3-5.

TABLE 3-4: WRITE AND ERASE BUFFER SIZES

TABLE 3-5: WRITE CODE MEMORY CODE SEQUENCE

Note: The TBLPTR register must point to the

same region when initiating the program-

ming sequence as it did when the write

buffers were loaded.

Devices (Arranged by Family) Write Buffer Size

(bytes) Erase Size (bytes)

PIC18F26K20, PIC18F46K20 64 64

PIC18F24K20, PIC18F25K20, PIC18F44K20, PIC18F45K20 32 64

PIC18F23K20, PIC18F43K20 16 64

4-bit

Command Data Payload Core Instruction

Step 1: Direct access to code memory.

0000

8E A6

9C A6

84 A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, WREN

Step 2: Point to row to write.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 3: Load write buffer. Repeat for all but the last two bytes.

1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.

Step 4: Load write buffer for last two bytes and start programming.

1111

0000 <MSB><LSB>

00 00 Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

To cont inue wr iting dat a, repea t step s 2 through 4, wh ere the Ad dress Pointer i s increm ented b y 2 at e ach it eration of

the loop.

PIC18F2XK20/4XK20

FIGURE 3-4: PROGRAM CODE MEMORY FLOW

FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION

TIMING DIAGRAM (1111)

Start Write Sequence

All

locations

done?

Done

Start

Yes

Hold PGC Low

for Tim e P1 0

Load 2 Bytes

to Wri te

Buffer at <Addr>

All

bytes

written?

Yes

and Hold PGC

High until Done

N = 1

LoopCount = 0

Configure

Device for

Writes

N = 1

LoopCount =

LoopCount + 1

N = N + 1

and Wait P9

1234 1 2 15 16 123 4

PGC

P5A

PGD

PGD = Input

1111

34 65

(1)

P10

Programming Time

nnn nn n n

16-bit

Data Payload

4-bit Command 16-bit Data Payload 4-bit Comm an d

Note 1: Use P9A for User ID and Configuration Word programming.

PIC18F2XK20/4XK20

3.2.1 MODIFYING CODE MEMORY

The previous programming example assumed that the

device has been Bulk Erased prior to programming

(see Section 3.1.1 “High-V olt age ICSP Bulk Erase”).

It may be the case, however, that the user wishes to

modify only a section of an already programmed

device.

The appro priate num ber of byte s required for the eras e

buffer must be read out of code memory (as described

in Section 4.2 “Verify Code Memory and ID Loca-

tions”) and buffered. Modifications can be made on

this buffer. Then, the block of code memory that was

read out must be erased and rewritten with the

modified data.

The WREN bit must be set if the WR bit in EECON1 is

used to initiate a write sequence.

TABLE 3-6: MODIFYING CODE MEMORY

4-bit

Command Data Payload Core Instruction

Step 1: Direct access to code memory.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Read code memory into buffer (Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).

Step 3: Set the Table Pointer for the block to be erased.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 4: Enable memory writes and setup an erase.

0000

0000 84 A6

88 A6 BSF EECON1, WREN

BSF EECON1, FREE

Step 5: Initiat e er ase.

0000

88 A6

82 A6

00 00

BSF EECON1, FREE

BSF EECON1, WR

NOP

NOP Erase starts on the 4th clock of this instruction

Step 6: Poll WR bit. Repeat unti l bit is clear.

0000

50 A6

6E F5

00 00

MOVF EECON1, W, 0

MOVWF TABLAT

NOP

Shift out data(1)

Step 7: Load write buffer. The correct bytes will be selected based on the Table Pointer.

0000

1101

•

1111

0000

0E <Addr[21:16]>

6E F8

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

•

00 00

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2.

Repeat as many times as necessary to fill the write buffer

Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

To continue modifying dat a, repeat Steps 2 through 6, w here the Addre ss Pointer is in cremented by the appro priate numbe r of bytes

(see Table 3-4) at each iteration of the loop. The write cycle must be repeated eno ugh times to completely rewrite the content s of the

erase buffer.

Step 8: Disa ble writes.

0000 94 A6 BCF EECON1, WREN

PIC18F2XK20/4XK20

3.3 Data EEPROM Programming

Data EEPROM is accessed one byte at a time via an

Address Pointer (register pair EEADRH:EEADR) and a

data latch (EEDATA). Data EEPROM is written by

loading EEADRH:EEADR with the desired memory

locatio n, EEDATA with the dat a to be written and initiat-

ing a memory write by appropriately configuring the

EECON1 register . A byte write automatically erases the

location and writes the new data (erase-before-write).

When using the EECON1 register to perform a data

EEPROM write, both the EEPGD and CFGS bits must

be cleared (EECON1<7:6> = 00). The WREN bit must

be set (EECON1< 2> = 1) to enable writes of any sort

and this must be done prior to initiating a write

sequen ce. The write sequence is initiated by setting the

WR bit (EECON1<1> = 1).

The write begins on the falling edge of the 24th PGC

after the WR bit is set. It ends when the WR bit is

cleared by hardware.

After the programming sequence terminates, PGC

must be held low for the time specified by parameter

P10 to allow high-voltage discharge of the memory

array.

FIGURE 3-6: PROGRAM DAT A FL OW

FIGURE 3-7: DATA EEPROM WRITE TIMING DIAGRAM

Start

St art Write

Set Data

Done

Yes

done?

Enable Write

Sequence

Set Address

WR bit

clear? No

Yes

PGC

PGD

PGD = Input

0000

BSF EECON1, WR4-bit Command

1234 121516

P5 P5A

P10 12

Poll WR bit, Repeat until Clear 16-bit Data

Payload

1234 121516 123

P5 P5A

41 2 15 16

P5 P5A

0000

MOVF EECON1, W, 0

4-bit Command

0000

4-bit Command Shift Out Data

MOVWF TABLAT

PGC

PGD

(see below)

(see Figure 4-4)

PGD = Input PGD = Output

Poll WR bit

P11A

P5A

2 NOP commands

PIC18F2XK20/4XK20

TABLE 3-7: PROGRAMMING DATA MEMORY

4-bit

Command Data Payload Core Instruction

Step 1: Direct access to data EEPROM.

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Load the data to be written.

0000

0000 0E <Data>

6E A8 MOVLW <Data>

MOVWF EEDATA

Step 4: Enable memory wri tes .

0000 84 A6 BSF EECON1, WREN

Step 5: Initiate write.

0000

82 A6

00 00

BSF EECON1, WR

NOP

NOP ;write starts on 4th clock of this instruction

Step 6: Poll WR bit, repeat until the bit is clear.

0000

0010

50 A6

6E F5

00 00

MOVF EECON1, W, 0

MOVWF TABLAT

NOP

Shift out data(1)

Step 7: Hold PGC low for time P10.

Step 8: Disable writes.

0000 94 A6 BCF EECON1, WREN

Repeat steps 2 through 8 to write more data.

Note 1: See Figure 4-4 for details on shift out data timing.

PIC18F2XK20/4XK20

3.4 ID Location Programming

The ID locations are programmed much like the code

memory. The ID registers are mapped in addresses

200000h through 200007h. These locations read out

normally even after code protection.

Table 3-8 demonst rates the cod e sequenc e required to

write the ID locations.

In order to modif y the ID l ocations , refer to the me thod-

ology described in Section 3.2.1 “Modifying Code

Memory”. As with code memory, the ID loc ations m ust

be erased before being modified.

When VDD is below the minimum for Bulk Erase

operation, ID locations can be cleared with the Row

Erase method described in Section 3.1.3 “ICSP Row

Erase”.

TABLE 3-8: WRITE ID SEQUENCE

Note: The user only needs to fill the first 8 bytes

of the write buffer in order to write the ID

locations.

4-bit

Command Dat a Payl oad Core Instru ction

Step 1: Direct access to code memory.

0000

8E A6

9C A6

84 A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, WREN

Step 2: Set Ta ble Pointer to ID. Load write buffer with 8 bytes and write.

0000

1101

1111

0000

0E 20

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

MOVLW 20h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 00h

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2.

Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

PIC18F2XK20/4XK20

3.5 Boot Block Programming

The code sequence detailed in Table 3-5 should be

used, except t hat the a ddress u sed in “Step 2” will be i n

the range of 000000h to 0007FFh.

3.6 Configuration Bit s Programming

Unlike code memory, the Configuration bits are

programmed a byte at a time. The Table Write, Begin

Programm ing 4-bi t command (‘1111’) is used, but only

8 bits of the following 16-bit payload will be written. The

LSB of the payload will be written to even addresses

and the MSB will be written to odd addresses. The

code sequence to program two consecutive configura-

tion locations is shown in Table 3-9. See Figure 3-5 for

the timing diagram.

TABLE 3-9: SET ADDRESS POINTER TO CONFIGURATION LOCATION

FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW

Note: The address must be explicitly written for

each byte programmed. The addresses

can not be increm en ted in this mode .

4-bit

Command Dat a Payl oad Cor e Instru c tion

Step 1: Direct access to config memory.

0000

8E A6

8C A6

84 A6

BSF EECON1, EEPGD

BSF EECON1, CFGS

BSF EECON1, WREN

Step 2(1): Set Table Pointer for config byte to be written. Write even/odd addresses.

0000

1111

0000

1111

0000

0E 30

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

0E 01

6E F6

00 00

MOVLW 30h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPRTH

MOVLW 00h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

MOVLW 01h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9A and low for time P10.

Note 1: Enabling the wri te protec tion of Configura tion bi t s (WR TC = 0 in CONFIG6H) will prevent further writing of

Configuration bits. Always write all the Configuration bits before enabling the write protection for

Configuration bits.

Load Even

Configuration

Start

Program Program

MSB

Delay P9 and P10

Time for Write

LSB

Load Odd

Configuration

Address Address

Done

Start

Delay P9 and P10

Time for Write

Done

PIC18F2XK20/4XK20

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations

and Configurati on Bits

Code memory is accessed one byte at a time via the

4-bit command, ‘1001’ (table read, post-increment).

The co ntents of memory p ointed to by the Table Po inter

(TBLPTRU:TB LPTRH:TBLPTRL) are serially output on

PGD.

The 4-bit command is shifted in LSb first. The read is

executed during the next 8 clocks, then shifted out on

PGD during the last 8 clocks, LSb to MSb. A delay of

P6 must be introduced after the falling edge of the 8th

PGC of the op erand to allow PGD to t rans iti on fr om an

input to an output. During this time, PGC must be held

low (see Figure 4-1). This operation also increments

the Table Pointer by one, pointing to the next byte in

code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFFh address s p a ce, s o i t a ls o a ppl ie s

to the reading of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001)

Note: When table read protection is enabled, the

first read access to a protected block

should be discarded and the read repeated

to retrieve valid data. Subsequent reads of

the same block can be performed normally.

4-bit

Command Data Payload Core Instruction

Step 1: Set Ta ble Pointer

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory and then shift out on PGD, LSb to MSb

1001 00 00 TBLRD *+

1234

PGC

PGD

PGD = Input

Shift Data Out

PGD = Output

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-bit Command

1001

PGD = Input

LSb MSb

123456

1234

nnnn

P14

Note 1: Magnification of the high-impedance delay between PGC and PGD is shown in Figure 4-6.

(Note 1)

PIC18F2XK20/4XK20

4.2 Verify Code Memory and ID

Locations

The veri fy step invo lves read ing back the code memo ry

space and comparing it against the copy held in the

programmer’s buffer. Memory reads occur a single byte

at a time, so two bytes must be read to compare

against the word in the programmer’s buffer. Refer to

Section 4.1 “Read Code Memory, ID Locations and

Configuration Bits” for implementation details of

reading co de mem ory.

The Table Pointer must be manually set to 200000h

(base address of the ID locations) once the code

memory has been verified. The post-increment feature

of the table read 4-bit command can not be used to

increment the Table Pointer beyond the code memory

spac e. In a 6 4-Kbyte d evice, fo r example, a post-i ncre-

ment read of address FFFFh will wrap t he Table Pointer

back to 000000h, rather than point to unimplemented

address 010000h.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Read Low Byte

Read High Byte

Does

Word = Expect

data? Failure,

Report

Error

All

code memory

verified?

Yes

Set TBLP TR = 0

Start

Set TBLPTR = 200000h

Yes

Read Low Byte

Read High byte

Does

Word = Expect

data? Failure,

Report

Error

All

ID locations

verified?

Yes

Done

Yes

with Post-increment

with Post-increment Increment

Pointer

with Post-Increment

PIC18F2XK20/4XK20

4.3 Verify Configuration Bits

A configuration address may be read and output on

PGD via th e 4-bit co mmand, ‘1001’. Config uration dat a

is read and written in a byte-wise fashion, so it is not

necessary to merge two bytes into a word prior to a

compare. The result may then be immediately

compared to the appropriate configuration data in the

programmer’s memory for verification. Refer to

Section 4.1 “Read Code Memory, ID Locations and

Configuration Bits” for implementation details of

reading co nfiguration data.

4.4 Read Data EEPROM Memory

Data EEPROM is accessed one byte at a time via an

Address Pointer (register pair EEADRH:EEADR) and a

data latch (EEDAT A). Dat a EEPROM is read by loading

EEADRH:EEADR with the desired memory location

and initi ating a m emory read by approp riat ely con figur-

ing the EECON1 register. The data will be loaded into

EEDATA, where it may be serially output on PGD via

the 4-bit command, ‘0010’ (Shift Out Data Holding

falling edge of the 8th PGC of the operand to allow

PGD to transition from an input to an output. During this

time, PGC must be held low (see Figure 4-4).

The command sequence to read a single byte of data

is shown in Table 4-2.

FIGURE 4-3: READ DATA EEPR OM

FLOW

TABLE 4-2: READ DATA EEPROM MEMORY

Start

Set

Address

Read

Byte

Done

Yes

done?

Mov e to TA BLAT

Shif t Ou t Da ta

4-bit

Command Data Payload Core Instruction

Step 1: Direct access to data EEPROM .

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Initiate a memory read.

0000 80 A6 BSF EECON1, RD

Step 4: Load data into the Serial Data Holding register.

0000

0010

50 A8

6E F5

00 00

MOVF EEDATA, W, 0

MOVWF TABLAT

NOP

Shift Out Data(1)

Note 1: The <LSB> is undefined. The <MSB> is the data.

PIC18F2XK20/4XK20

FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)

FIGURE 4-5: HIGH-IMPEDANCE DELAY

4.5 Verify Data EEPROM

A data EEPROM add res s may b e re ad via a se qu enc e

of core instructions (4-bit command, ‘0000’) and then

output on PGD via the 4-bit command, ‘0010’ (TABLA T

compared to the appropriate data in the programmer’s

memory for verification. Refer to Section 4.4 “Read

Dat a EEPROM Memory ” for i mp lem en t ati on details of

reading data EEPROM.

4.6 Blank Check

The term “Blank C heck” means to verify that the device

has no programmed memory cells. All memories must

be verified: code memory, data EEPROM, ID locations

and Configuration bits. The device ID registers

(3FFFFEh:3FFFFFh) should be ignored.

A “blank” or “erased” memory cell will read as a ‘1’.

Therefore, Blank Checking a device merely means to

verify that all bytes read as FFh except the Configura-

tion bit s. Unuse d (reserved) Config uration bits will rea d

‘0’ (programm ed) . R efer to Table 5-1 for blank con fig u-

ration expect data for the various PIC18F2XK20/

4XK20 devices.

Given that Blank Checking is merely code and data

EEPROM verification with FFh expect data, refer to

Section 4.4 “Read Data EEPROM Memory” and

Section 4.2 “V erify Code Memory and ID Locations”

for implementation details.

FIGURE 4-6: BLANK CHECK FLOW

1234

PGC P5

PGD

PGD = Input

Shift Data Out

PGD = Output

5678 1234

P5A

91011 13 15161412

Fetch Next 4-bit Command

0100

PGD = Input

LSb MSb

123456

1234

nn n n

P14

(Note 1)

Note 1: Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 4-5.

(Note 1)

MSb nn

P19

PGD

PGC

Yes

Start

Blank Check Device

device

blank? Continue

Abort

PIC18F2XK20/4XK20

5.0 CONFIGURATION WORD

The PIC18F2XK20/4XK20 devices have several

Configuration Words. These bits can be set or cleared

to select various device configurations. All other mem-

ory areas should be programmed and verified prior to

setting Configuration Words. These bits may be read

out normally, even after read or code protection. See

Table 5-1 for a list of Configuration bits and device IDs

and Table 5-3 for the Configuration bit descriptions.

5.1 User ID Locations

A user may sto re ide ntif ic atio n inf orm atio n (ID ) in eig ht

ID locations mapped in 200000h:200007h. It is recom-

mended that the Most Significant nibble of each ID be

Fh. In doing so, if the user code inadvertently tries to

execute from the ID space, the ID data will execute as

a NOP.

5.2 Device ID W ord

The device ID word for the PIC18F2XK20/4XK20

devices is located at 3FFFFEh:3FFFFFh. These bits

may be used by the programmer to identify what device

type is b ein g p r ogr am med a nd read out norm all y, even

after code or read protection. See Table 5-2 for a

complete list of device ID values.

FIGURE 5-1: READ DEVICE ID WORD

FLOW

TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs

Start

Set TBLP TR = 3FF FFE

Done

Read Low Byte

Read High Byte

with Post-Increment

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300001h CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111

300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111

300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111

300005h CONFIG3H MCLRE — — — HFOFST LPT1OSC PBADEN CCP2MX 1--- 1011

300006h CONFIG4L DEBUG XINST — — —LVP—STVREN10-- -1-1

300008h CONFIG5L — — — —CP3

(1) CP2(1) CP1 CP0 ---- 1111

300009h CONFIG5H CPD CPB — — — — — — 11-- ----

30000Ah CONFIG6L — — — —WRT3

(1) WRT2(1) WRT1 WRT0 ---- 1111

30000Bh CONFIG6H WRTD WRTB WRTC —————111- ----

30000Ch CONFIG7L — — — —EBTR3

(1) EBTR2(1) EBTR1 EBTR0 ---- 1111

30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----

3FFFFEh DEVID1(2) DEV2 DEV 1 DEV0 REV4 REV3 REV2 REV1 RE V0 See Table 5-2

3FFFFFh DEVID2(2) DEV10 DEV9 D E V8 DEV7 DEV6 DEV 5 DEV4 DEV3 See Table 5-2

Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: These bits are only implemented on specific devices. Refer to Sectio n 2.3 “Memory Maps” to determine which bits

apply based on available memory.

2: DEVID regist ers are read-only and cannot be programmed by the user.

PIC18F2XK20/4XK20

TABLE 5-2: DEVICE ID VALUE

Device Device ID Value

DEVID2 DEVID1

PIC18F23K20 20h 111x xxxx

PIC18F24K20 20h 101x xxxx

PIC18F25K20 20h 011x xxxx

PIC18F26K20 20h 001x xxxx

PIC18F43K20 20h 110x xxxx

PIC18F44K20 20h 100x xxxx

PIC18F45K20 20h 010x xxxx

PIC18F46K20 20h 000x xxxx

Note: The ‘x’s in DEVID1 contain the device revision code.

PIC18F2XK20/4XK20

TABLE 5-3: PIC18F2XK20/4XK20 BIT DESCRIPTIONS

Bit Name Configuration

Words Description

IESO CONFIG1H Internal External Switchover bit

1 = Internal External Switchover mode enabled

0 = Internal External Switchover mode disabled

FCMEN CONFIG1H Fa il- Safe C lock Monitor Enable bit

1 = Fail-Safe Cloc k Mo nito r enabl ed

0 = Fail-Safe Cloc k Mo nitor disabled

FOSC<3:0> CONFIG1H Oscillator Selection bits

11xx = External RC oscillator, CLKOUT function on RA6

101x = External RC oscillator, CLKOUT function on RA6

1001 = HFINTOSC, CLKOUT function on RA6, port function on RA7

1000 = HFINTOSC, port function on RA6, port function on RA7

0111 = External RC oscilla tor, port function on RA6

0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)

0101 = EC oscillator, port function on RA6

0100 = EC osc ill ato r, CLKOUT functi on on RA6

0011 = External RC oscillator, CLKOUT function on RA6

0010 = HS oscillator

0001 = XT osc il lat or

0000 = LP osci lla tor

BORV<1:0> CONFIG2L Brown-out Reset Voltage bits

11 =V

BOR set to 1.8V

10 =V

BOR set to 2.2V

01 =V

BOR set to 2.7V

00 =V

BOR set to 3.0V

BOREN<1 :0> CONFIG2L Brown-ou t Reset Enab le bits

11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)

10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SB O REN is disabled )

01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00 = Brown-out Reset disabled in hardware and software

PWRTEN CONFIG2L Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1 :64

0101 = 1 :32

0100 = 1 :16

0011 = 1 :8

0010 = 1 :4

0001 = 1 :2

0000 = 1 :1

PIC18F2XK20/4XK20

WDTEN CONFIG2H Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on SWDTEN bit)

MCLRE CONFIG3H MCLR Pin Enable bit

1 =MCLR pin enabled, RE3 input pin disabled

0 = RE3 input pin enabled, MCLR pin disabled

HFOFST CONFIG3H HFINTOSC Fast Start

1 = HFINTOSC output is not delayed

0 = HFINTOSC output is delayed until oscillator is stable (IOFS = 1)

LPT1 OSC CONFIG3H Low-Power Timer1 O scillator Enabl e bit

1 = Timer1 configured for low-power operation

0 = Timer1 configured for higher power operation

PBADEN CONFIG3H PORTB A/D Enable bit

1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset

0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset

CCP2MX CONFIG3H CCP2 MUX bit

1 = CCP2 input/output is multiplexed with RC1

0 = CCP2 input/output is multiplexed with RB3

DEBUG CONFIG4L Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general

purpose I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit

Debug

XINST CONFIG4L Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled

(Legacy mode)

LVP CONF IG4L Low-Voltage Prog rammi ng Enable b it

1 = Low-Voltage Programming enabled, RB5 is the PGM pin

0 = Low-Voltage Programming disabled, RB5 is an I/O pin

STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow enabled

0 = Reset on stack overflow/underflow disabled

TABLE 5-3: PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

PIC18F2XK20/4XK20

CP3 CONFIG5L Code Protection bits (Block 3 code memory area)

1 = Block 3 is not code-protected

0 = Block 3 is code-protected

CP2 CONFIG5L Code Protection bits (Block 2 code memory area)

1 = Block 2 is not code-protected

0 = Block 2 is code-protected

CP1 CONFIG5L Code Protection bits (Block 1 code memory area)

1 = Block 1 is not code-protected

0 = Block 1 is code-protected

CP0 CONFIG5L Code Protection bits (Block 0 code memory area)

1 = Block 0 is not code-protected

0 = Block 0 is code-protected

CPD CONFIG5H Code Protection bits (Data EEPROM)

1 = Data EEPROM is not code-protected

0 = Data EEPROM is code-protected

CPB CONFIG5H Code Protection bits (Boot Block memory area)

1 = Boot Block is not code-protected

0 = Boot Block is code-protected

WRT3 CONFIG6L Write Protection bits (Block 3 code memory area)

1 = Block 3 is not write-protected

0 = Block 3 is write- protected

WRT2 CONFIG6L Write Protection bits (Block 2 code memory area)

1 = Block 2 is not write-protected

0 = Block 2 is write- protected

WRT1 CONFIG6L Write Protection bits (Block 1 code memory area)

1 = Block 1 is not write-protected

0 = Block 1 is write- protected

WRT0 CONFIG6L Write Protection bits (Block 0 code memory area)

1 = Block 0 is not write-protected

0 = Block 0 is write-p rotected

WRTD CONFIG6H Write Protection bit (Data EEPROM)

1 = Data EEPROM is not write-protected

0 = Data EEPROM is write-protected

WRTB CONFIG6H Write Protection bit (Boot Block memory area)

1 = Boot Block is not write-prot ected

0 = Boot Block is write-protected

WRTC CONFIG6H Write Protection bit (Configuration registers)

1 = Configuration registers are not write-protected

0 = Configuration registers are write-protected

TABLE 5-3: PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

PIC18F2XK20/4XK20

EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area)

1 = Block 3 is not protected from table reads executed in other blocks

0 = Block 3 is pr otected from table reads executed in other blocks

EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area)

1 = Block 2 is not protected from table reads executed in other blocks

0 = Block 2 is pr otected from table reads executed in other blocks

EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area)

1 = Block 1 is not protected from table reads executed in other blocks

0 = Block 1 is pr otected from table reads executed in other blocks

EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area)

1 = Block 0 is not protected from table reads executed in other blocks

0 = Block 0 is protected from table reads executed in other blocks

EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area)

1 = Boot Block is not protected from table reads executed in other blocks

0 = Boot Block is protected from table reads executed in other blocks

DEV<10:3> DEVID2 Device ID bits

These bits are used with the DEV<2:0> bits in the DEVID1 register to

identify part number.

DEV<2:0> DEVID1 Device ID bits

These bits are used with the DEV<10:3> bits in the DEVID2 register to

identify part number.

REV<4:0> DEVID1 Revision ID bits

These bits are used to indicate the revision of the device.

TABLE 5-3: PIC18F2XK20/4XK20 BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

PIC18F2XK20/4XK20

5.3 Single-Supply ICSP Programming

The LVP bit in Configuration register, CONFIG4L,

enables Single-Supply (Low-Voltage) ICSP Program-

ming. The LVP bit defaults to a ‘1’ (enabled) from the

factory.

If Single-Supply Programming mode is not used, the

LVP bit can be programmed to a ‘0’ and RB5/PGM

becomes a digital I/O pin. However, the LVP bit may

only be programmed by entering the High-Voltage

ICSP m ode, whe re MCLR /VPP/RE 3 is rai sed to VIHH.

Once the LVP bit is programmed to a ‘0’, only the

High-Voltage ICSP mode is available and only the

High-Voltage ICSP mode can be used to progr am the

device.

5.4 Embedding Configuration Word

Info rmatio n in th e H EX Fi le

To allow portability of code, a PIC18F2XK20/4XK20

programmer is required to read the Configuration Word

locations from the hex file. If Configuration Word infor-

mation is not present in the hex file, then a simple warn-

ing message should be issued. Similarly, while saving

a hex file, all Configuration Word information must be

included. An option to not include the Configuration

Word information may be provided. When embedding

Config uration W ord in formati on in the h ex fi le, it shoul d

start at address 300000h.

Microchip Technology Inc. feels strongly that this

featur e is imp orta nt for th e bene fit of t he end cu stome r.

5.5 Embedding Data EEPROM

Info rmati on In th e H EX Fi le

To allow portability of code, a PIC18F2XK20/4XK20

programmer is required to read the data EEPROM

informat ion from the hex fil e. If dat a EEPROM inf orma-

tion is not present, a simple warning message should

be issued. Similarly, when saving a hex file, all data

EEPROM information must be included. An option to

not inc lud e the da t a EEPROM informa tion m ay be pro-

vided. When embedding data EEPROM information in

the hex file, it should start at address F00000h.

Microchip Technology Inc. believes that this feature is

important for the benefit of the end customer.

5.6 Checksum Comput ation

The check s um is cal cu lated by summi ng the foll ow in g:

• The contents of all code memo ry locations

• The Configuration Word, appropriately masked

• ID locations (Only if any portion of program

memory is code-protected)

The Least Significant 16 bits of this sum are the

checksum.

Code protection limits access to program memory by

both external programmer (code-protect) and code

execution (table read protect). The ID locations, when

included in a code protected checksum, contain the

checksum of an unprotected part. The unprotected

checksum is distributed: one nibble per ID location.

Each nibble is right justified.

Table 5-4 describes how to calculate the checksum for

each device.

Note 1: The High-Voltage ICSP mode is always

available, regardless of the state of the

LVP bit, by applying VIHH to the MCLR/

VPP/RE3 pin.

2: While in Low-Voltage ICSP mode, the

RB5 pin can no longer be used as a

general purpose I/O.

Note: The checksum calculation differs depend-

ing on the code-protect setting. Since the

code memory locations read o ut differently

dependi ng on the code-pro tect setting, th e

table describes how to manipulate the

actual code memory values to simulate

the values that would be read from a

protected device. When calculating a

checksum by reading a device, the entire

code memory can simply be read and

summed. The Configuration Word and ID

locations can always be read.

PIC18F2XK20/4XK20

TABLE 5-4: CHECKSUM COMPUTATION

Device Code-

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

PIC18FX3K20

None SUM[0000:01FF]+SUM[0200:0FFF]+SUM[1000:1FFF]+

(CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 03h)+

(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+

(CONFIG7L & 03h)+(CONFIG7H & 40h)

E33Eh E294h

Boot

Block SUM[0 200:0FFF]+ SUM [ 10 00: 1FFF]+(CO NF IG 1L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 03h)+(CONFIG5H & C0h)+

(CONFIG6L & 03h)+(CONFIG6H & E0h)+(CONFIG7L & 03h)+

(CONFIG7H & 40h)+SUM_ID

E520h E4C6h

Boot/

Block 0 SUM[ 1 000:1FFF]+ (CONFIG1L & 00h)+(CO NF IG 1H & CFh)+

(CONFIG 2 L & 1Fh)+(CONFIG2H & 1F)+( C O NFIG3L & 00 h)+

(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+(CONFIG4H & 00h)+

(CONFIG5L & 03h)+(CONFIG5H & C0h)+(CONFIG6L & 03h)+

(CONFIG6H & E0h)+(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID

F31Fh F2C5h

All (CONFIG1L & 00h)+(CONFIG1H & C Fh )+ (CO NFIG2L & 1F h) +

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 03h)+

(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+

(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID

031Dh 0318h

PIC18FX4K20

None SUM[0000:07FF]+SUM[0800:1FFF]+SUM[2000:3FFF]+

(CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 03h)+

(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+

(CONFIG7L & 03h)+(CONFIG7H & 40h)

C33Eh C294h

Boot

Block SUM[0 800:1FFF]+ SUM [ 20 00: 3FFF]+(CO NF IG 1L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 03h)+(CONFIG5H & C0h)+

(CONFIG6L & 03h)+(CONFIG6H & E0h)+(CONFIG7L & 03h)+

(CONFIG7H & 40h)+SUM_ID

CB1Eh CAC4h

Boot/

Block 0 SUM[ 2 000:3FFF]+ (CONFIG1L & 00h)+(CO NF IG 1H & CFh)+

(CONFIG 2 L & 1Fh)+(CONFIG2H & 1F)+( C O NFIG3L & 00 h)+

(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+(CONFIG4H & 00h)+

(CONFIG5L & 03h)+(CONFIG5H & C0h)+(CONFIG6L & 03h)+

(CONFIG6H & E0h)+(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID

E31Dh E2C3h

All (CONFIG1L & 00h)+(CONFIG1H & C Fh )+ (CO NFIG2L & 1F h) +

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 03h)+

(CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+

(CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID

031Bh 0316h

Legend: Item Description

CONFIGx = Configuration Word

SUM[a:b] = Sum of locat ions, a to b inclus ive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+=Addition

& = Bit-wise AND

PIC18F2XK20/4XK20

PIC18FX5K20

None SUM[0000:07FF]+SUM[0800:1FFF]+SUM[2000:3FFF]+

SUM[4 000 :5 FFF]+SUM[ 600 0: 7FFF]+(CO NFI G 1 L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+

(CONFIG 6 L & 0Fh)+(CONFIG6H & E0h )+ (CONFIG7L & 0Fh)+

(CONFIG7H & 40h)

8362h 82B8h

Boot

Block SUM[0800:1FFF]+SUM[2000:3FFF]+SUM[4000:5FFF]+SUM[6000:7FFF

(CONFIG 1 L & 00h)+(CONFIG1H & CFh )+ (CO NFIG2L & 1F h) +

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CO NFIG5L & 0F h) +

(CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+

(CONFIG 7 L & 0Fh)+(CONF IG 7H & 40h)+SUM_ ID

8B35h 8AEAh

Boot/

Block 0/

Block 1

SUM[4 000 :5 FFF]+SUM[ 600 0: 7FFF]+(CO NFI G 1 L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+

(CONFIG 6 L & 0Fh)+(CONFIG6H & E0h )+ (CONFIG7L & 0Fh)+

(CONFIG7H & 40h)+SUM_ID

C332h C2E7h

All (CONFIG1L & 00h)+(CONFIG1H & C Fh )+ (CO NFIG2L & 1F h) +

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CO NFIG5L & 0F h) +

(CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+

(CONFIG 7 L & 0Fh)+(CONF IG 7H & 40h)+SUM_ ID

0326h 0330h

TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)

Device Code-

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CONFIGx = Configuration Word

SUM[a:b] = Sum of locat ions, a to b inclus ive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+=Addition

& = Bit-wise AND

PIC18F2XK20/4XK20

PIC18FX6K20

None SUM[0000:07FF]+SUM[0800:3FFF]+SUM[4000:7FFF]+

SUM[8000:BFFF]+SUM[C000:FFFF]+(CONFIG1L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+

(CONFIG 6 L & 0Fh)+(CONFIG6H & E0h )+ (CONFIG7L & 0Fh)+

(CONFIG7H & 40h)

0362h 02B8h

Boot

Block SUM[0800:3FFF]+SUM[4000:7FFF]+SUM[8000:BFFF]+SUM[C000:FFF

F]+

(CONFIG1L & 00h)+(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 0Fh)+

(CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+

(CONFIG 7 L & 0Fh)+(CON FIG 7H & 40h)+SUM_ ID

0B2Dh 0AE2h

Boot/

Block 0/

Block 1

SUM[3000:BFFF]+SUM[C000:FFFF]+(CONFIG1L & 00h)+

(CONFIG1H & CFh)+(CONFIG2L & 1Fh)+(CONFIG2H & 1F)+

(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+(CONFIG4L & C5h)+

(CONFIG4H & 00h)+(CONFIG5L & 0Fh)+(CONFIG5H & C0h)+

(CONFIG 6 L & 0Fh)+(CONFIG6H & E0h )+ (CONFIG7L & 0Fh)+

(CONFIG7H & 40h)+SUM_ID

832Ah 82DFh

All (CONFIG1L & 00h)+(CONFIG1H & C Fh )+ (CO NFIG2L & 1F h) +

(CONFIG2H & 1F)+(CONFIG3L & 00h)+(CONFIG3H & 8Fh)+

(CONFIG 4L & C5h)+(C ON FIG4H & 00h )+ (CONFIG5L & 0Fh)+

(CONFIG5H & C0h)+(CONFIG6L & 0Fh)+(CONFIG6H & E0h)+

(CONFIG 7 L & 0Fh)+(CON FIG 7H & 40h)+SUM_ ID

031Eh 0328h

TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)

Device Code-

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CONFIGx = Configuration Word

SUM[a:b] = Sum of locat ions, a to b inclus ive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+=Addition

& = Bit-wise AND

PIC18F2XK20/4XK20

6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/

VERIFY TEST MODE

Standard Ope ra ting Condition s

Oper ati ng Tempe rature: 25°C is re commended

Param

No. Sym. Characteristic Min. Max. Units Conditions

D110 VIHH High-Voltage Prog ra m m ing Voltage on

MCLR/VPP/RE3 VDD + 4.5 9 V

D110A VIHL Low-Voltage P ro gr am m i ng Voltage on

MCLR/VPP/RE3 1.80 3.60 V

D111 VDD Su ppl y Voltage During Pro gr am m i ng 1.80 3.60 V Row Eras e/ Writ e

2.7 3.60 V Bulk Erase operations

D112 IPP Programming Current on MCLR/VPP/RE3 — 300 μA

D113 IDDP Supply Curren t During Prog ra m m ing — 10 mA

D031 VIL I npu t L ow Voltage VSS 0.2 VDD V

D041 VIH I npu t Hi gh Voltage 0.8 V DD VDD V

D080 VOL Output Low Voltage — 0.6 V IOL = X.X mA @ 2.7V

D090 VOH Output High Voltage VDD – 0.7 — V IOH = -Y.Y mA @ 2.7V

D012 CIO Capacitive Loading on I/O pin ( PGD) — 50 pF To meet AC spe cifica t ions

P1 TRMCLR/VPP/RE3 Rise Time to enter

Program/Verify mode —1.0μs(Note 1)

P2 TPGC Serial Clock (PGC) Period 100 — ns VDD = 3. 6V

1 — μs VDD = 1.8V

P2A TPGCL Serial Clock (PGC) Low Time 40 —ns VDD = 3.6V

400 —ns VDD = 1.8V

P2B TPGCH Serial Clock (PGC) High Time 40 — n s VDD = 3.6V

400 —ns VDD = 1.8V

P3 TSET1 Input Data Setup Time to Serial Clock ↓15 — ns

P4 THLD1 Input Data Hold Time from PGC ↓ 15 — ns

P5 TDLY1 Delay betwe en 4- bi t Com m and and C om m and

Operand 40 — ns

P5A TDLY1ADelay between 4-bit Command Operand and next

4-bit Command 40 — ns

P6 TDLY2 Delay betwe en La st PG C ↓ of Command Byte to

First PGC ↑ of R ead of Data Word 20 — ns

P9 TDLY5 PGC High Time (m inimum progra m m i ng time ) 1 — ms Exter nally Timed

P9A TDLY5APGC High Time 5 ms Configuration Word

programming time

P10 TDLY6 PGC Low Time after Programming

(high-voltage discha rg e tim e) 200 — μs

P11 TDLY7 Delay to allow Self-T imed Data Write or

Bulk Erase t o oc cur 5—ms

P11A TDRWT Data Write Polling Time 4 — ms

Note 1: Do not allow excess time when tr ans i tioning MCLR between VIL and VIHH; this can c aus e spurious program

executions to occur. The maximum transition time is:

1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only)

+ 1.5 μs (for EC m ode only) wher e TCY is the instruction cycle time, TPWRT i s t he Power-up Timer pe riod and

TOSC is the oscill ator period. For specific values, refer to the El ect r ic al C haracter istic s section of th e device data

sheet for th e parti cular device.

PIC18F2XK20/4XK20

P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3 ↑2—μs

P13 TSET2VDD ↑ Setu p Time to M CLR/VPP/RE3 ↑100 — ns

P14 TVALID Data Out Valid from PGC ↑10 — ns

P15 TSET3PGM ↑ Setup Time to MCLR/VPP/RE3 ↑2—μs

P16 TDLY8 Delay between Last PGC ↓ and MCLR/VPP/RE3 ↓0—s

P17 THLD3MCLR/VPP/RE3 ↓ to VDD ↓— 100 ns

P18 THLD4MCLR/VPP/RE3 ↓ to PGM ↓0—s

P19 THIZ Delay from PGC ↑ to PGD High-Z 3 10 nS

P20 TPPDP Hold time after VPP changes 5 — μs

6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/

VERIFY TEST MODE (CONTINUED)

Standard Ope ra ting Condition s

Oper ati ng Tempe rature: 25°C is re commended

Param

No. Sym. Characteristic Min. Max. Units Conditions

Note 1: Do not allow excess time when tr ans i tioning MCLR between VIL and VIHH; this can c aus e spurious program

executions to occur. The maximum transition time is:

1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only)

+ 1.5 μs (for EC m ode only) wher e TCY is the instruction cycle time, TPWRT i s t he Power-up Timer pe riod and

TOSC is the oscill ator period. For specific values, refer t o the El ect r ic al C haracter istic s section of th e device data

sheet for th e parti cular device.

PIC18F2XK20/4XK20

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by updates . I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Inc orporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on t he market today, when used i n the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® co de hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technic al Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-67 33

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2 100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5 511

Fax: 86-28-8665-7889

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2 460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5 533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2 829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5 300

Fax: 86-27-5980-5118

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Xian

Tel: 86-29-8833-7 252

Fax: 86-29-8833-7256

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53 -63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spai n - Madri d

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

03/26/09