M48T128Y 5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER(R) SRAM Not recommended for new design Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal BCD coded year, month, day, date, hours, minutes, and seconds Automatic power-fail chip deselect and WRITE protection ) s ( ct u d o 32 1 r P e WRITE protect voltage VCC = 4.5 to 5.5 V; 4.1 V VPFD 4.5 V (VPFD = power-fail deselect voltage) PMDIP32 module Conventional SRAM operation; unlimited WRITE cycles Software-controlled clock calibration for high accuracy applications 10 years of data retention and clock operation in the absence of power Self-contained battery and crystal in the DIP package Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant - Lead-free second level interconnect ) (s t e l o s b O t c u d o r P e t e l o s b O September 2011 Doc ID 5746 Rev 7 This is information on a product still in production but not recommended for new designs. 1/23 www.st.com 1 Contents M48T128Y Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ) s ( ct Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 u d o 3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 14 r P e t e l o s b O 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ) (s t c u d o r t e l o 8 s b O 9 2/23 P e Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 5746 Rev 7 M48T128Y List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PMDIP32 - 32-pin plastic module DIP, package mechanical data. . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 5746 Rev 7 3/23 List of figures M48T128Y List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/23 Doc ID 5746 Rev 7 M48T128Y 1 Description Description The M48T128Y TIMEKEEPER(R) RAM is a 128 Kb x 8 non-volatile static RAM and real-time clock. The special DIP package provides a fully integrated battery-backed memory and realtime clock solution. The M48T128Y directly replaces industry standard 128 Kb x 8 SRAM. It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP hybrid houses a controller chip, SRAM, quartz crystal, and a long-life lithium button cell in a single package. Figure 1. Logic diagram ) s ( ct VCC 17 DQ0-DQ7 r P e W M48T128Y t e l o E G Table 1. s ( t c Signal names A0-A16 u d o DQ0-DQ7 s b O e t e ol Pr )- u d o 8 A0-A16 s b O VSS AI02244 Address inputs Data inputs / outputs E Chip enable G Output enable W WRITE enable VCC Supply voltage VSS Ground NC Not connected internally Doc ID 5746 Rev 7 5/23 Description M48T128Y Figure 2. DIP connections NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3. 1 32 2 31 30 3 29 4 28 5 27 6 26 7 8 M48T128Y 25 24 9 23 10 22 11 21 12 13 20 19 14 18 15 17 16 u d o 32,768 Hz CRYSTAL du o r P )- s ( t c LITHIUM CELL t e l o s b O VOLTAGE SENSE AND SWITCHING CIRCUITRY AI02245 r P e 8x8 TIMEKEEPER REGISTERS A0-A16 POWER 131,064 x 8 SRAM ARRAY DQ0-DQ7 E W VPFD VCC G VSS AI01804 s b O 6/23 ) s ( ct Block diagram OSCILLATOR AND CLOCK CHAIN e t e ol VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Doc ID 5746 Rev 7 M48T128Y 2 Operation modes Operation modes Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations consisting of BiPORTTM READ/WRITE memory cells within the static RAM array. The M48T128Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T128Y also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER(R) register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below the battery backup switchover voltage (VSO), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. ) s ( ct u d o Table 2. VCC E Deselect G DQ0-DQ7 Power X High Z Standby X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery backup mode bs VIH WRITE VIL READ s ( t c VSO to VPFD Deselect (min)(1) VSO(1) u d o X O ) 4.5 to 5.5 V READ Deselect t e l o Operating modes Mode r P e W 1. See Table 11 on page 18 for details. Note: r P e X = VIH or VIL; VSO = battery backup switchover voltage. t e l o s b O Doc ID 5746 Rev 7 7/23 Operation modes 2.1 M48T128Y READ mode The M48T128Y is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within tAVQV (address access time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access times (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for tAXQX (output data hold time) but will go indeterminate until the next address access. Figure 4. ) s ( ct READ mode AC waveforms u d o tAVAV VALID A0-A16 t e l o tELQV E tELQX tGLQV G ) (s tGLQX DQ0-DQ7 WE = High. Table 3. READ mode AC characteristics so b O d o r P e let s b O t c u Note: Symbol r P e tAXQX tAVQV Parameter(1) tEHQZ tGHQZ DATA OUT AI01197 M48T128Y Min Max tAVAV READ cycle time tAVQV Address valid to output valid 70 ns tELQV Chip enable low to output valid 70 ns tGLQV Output enable low to output valid 40 ns tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX 70 ns Chip enable low to output transition 5 ns Output enable low to output transition 5 ns Chip enable high to output Hi-Z 25 ns Output enable high to output Hi-Z 25 ns Address transition to output transition 10 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V (except where noted). 2. CL = 5 pF. 8/23 Unit Doc ID 5746 Rev 7 ns M48T128Y 2.2 Operation modes WRITE mode The M48T128Y is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Figure 5. ) s ( ct WRITE enable controlled, WRITE AC waveform tAVAV u d o VALID A0-A16 r P e tAVWH tAVEL tWHAX E t e l o tWLWH tAVWL W tWLQZ ) (s DQ0-DQ7 u d o DATA INPUT AI02382 Chip enable controlled, WRITE AC waveforms r P e s b O tWHQX tWHDX tDVWH ct Figure 6. t e l o s b O tAVAV VALID A0-A16 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI02383 Doc ID 5746 Rev 7 9/23 Operation modes M48T128Y Table 4. WRITE mode AC characteristics M48T128Y Parameter(1) Symbol Unit Min Max tAVAV WRITE cycle time 70 ns tAVWL Address valid to WRITE enable low 0 ns tAVEL Address valid to chip enable low 0 ns tWLWH WRITE enable pulse width 50 ns tELEH Chip enable low to chip enable 1 high 55 ns tWHAX WRITE enable high to address transition 5 ns tEHAX Chip enable high to address transition 10 ns tDVWH Input valid to WRITE enable high 30 tDVEH Input valid to chip enable high 30 tWHDX WRITE enable high to input transition 5 ) s ( ct tEHDX Chip enable high to input transition 10 ns tWLQZ(2)(3) tAVWH Address valid to WRITE enable high tAVEH Address valid to chip enable high tWHQX(2)(3) t e l o WRITE enable high to output transition s b O u d o r P e WRITE enable low to output Hi-Z ns 25 ns ns ns 60 ns 60 ns 5 ns 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V (except where noted). 2. CL = 5 pF. ) (s 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. t c u 2.3 Data retention mode d o r With valid VCC applied, the M48T128Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." P e t e l o Note: s b O A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T128Y/ may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T128Y for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max). 10/23 Doc ID 5746 Rev 7 M48T128Y Clock operations 3 Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' ) s ( ct 3.2 u d o r P e Setting the clock Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 12). Resetting the WRITE bit to a '0' then transfers the values of all time registers 1FFFFh1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur one second later. t e l o s b O 3.3 ) Stopping and starting the oscillator s ( t c u d o r P e t e l The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the oscillator. The M48T128Y is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T128Y oscillator starts after one second. o s b O Doc ID 5746 Rev 7 11/23 Clock operations Table 5. M48T128Y Register map Data Function/range Address D7 D6 1FFFEh 0 0 0 1FFFDh 0 0 10 date 1FFFCh 0 FT 1FFFBh 0 0 1FFFAh 0 1FFF9h ST 1FFF8h W 1FFFFh D5 D4 D3 D2 10 years D1 BCD format D0 Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hours 00-23 10 minutes Minutes Minutes 00-59 10 seconds Seconds Seconds 00-59 10 M 0 0 0 Day 10 hours R S Calibration Keys: u d o S = SIGN bit r P e R = READ bit W = WRITE bit t e l o ST = STOP bit 0 = Must be set to '0' Z = '0' and are Read only Y = '1' or '0' ) (s 3.4 ) s ( ct Control s b O Calibrating the clock t c u The M48T128Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are factory calibrated at 25 C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25 C. The oscillation rate of crystals changes with temperature (see Figure 7 on page 13). The M48T128Y design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in Figure 8 on page 13. d o r P e t e l o bs O 12/23 The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register 1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Doc ID 5746 Rev 7 M48T128Y Clock operations One method is available for ascertaining how much calibration a given M48T128Y may require. This involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in the STMicroelectronics application note, "TIMEKEEPER calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. For example, a deviation of 21 seconds slow over a period of 30 days would indicate a -8 ppm oscillator frequency error, requiring a +2(WR100010) to be loaded into the calibration byte for correction. Figure 7. ) s ( ct Crystal accuracy across temperature ppm u d o 20 r P e 0 t e l o -20 -40 ) (s s b O F = -0.038 ppm (T - T )2 10% 0 F C2 -60 t c u -80 d o r T0 = 25 C -100 P e let O o s b Figure 8. 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C AI02124 Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B Doc ID 5746 Rev 7 13/23 Clock operations 3.5 M48T128Y VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. ) s ( ct u d o Supply voltage protection r P e VCC t e l o VCC bs 0.1F O ) s ( t c u d o r P e t e l o s b O 14/23 Doc ID 5746 Rev 7 DEVICE VSS AI02169 M48T128Y 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Ambient operating temperature TA Storage temperature (VCC off, oscillator off) TSTG TSLD(1)(2) Value Unit 0 to 70 C ) s ( ct -40 to 85 Lead solder temperature for 10 seconds 260 du VIO Input or output voltages -0.3 to 7 VCC Supply voltage -0.3 to 7 IO Output current PD Power dissipation ro P e t e l o C C V V 20 mA 1 W 1. Soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. s b O 2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. Caution: ) (s Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode. t c u d o r P e t e l o s b O Doc ID 5746 Rev 7 15/23 DC and AC parameters 5 M48T128Y DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Parameter Supply voltage (VCC) Ambient operating temperature (TA) Unit 4.5 to 5.5 V ) s ( ct 0 to 70 Load capacitance (CL) 100 Input rise and fall times 5 Input pulse voltages P e 1.5 C du ro 0 to 3 Input and output timing ref. voltages Note: M48T128Y ns V V t e l o Output Hi-Z is defined as the point where data is no longer driven. Figure 10. AC testing load circuit DEVICE UNDER TEST ) (s s b O t c u d o r P e t e l o s b O Table 8. CIN 650 1.75V CL = 100pF CL includes JIG capacitance AI03630 Capacitance Parameter(1)(2) Symbol CIO(3) Min Max Unit Input capacitance - 20 pF Input / output capacitance - 20 pF 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected. 16/23 pF Doc ID 5746 Rev 7 M48T128Y Table 9. DC and AC parameters DC characteristics Symbol M48T128Y Test condition(1) Parameter Unit Min Input leakage current ILI ILO(2) Output leakage current Max 0 V VIN VCC 2 A 0 V VOUT VCC 2 A Outputs open 95 mA E = VIH 8 mA E = VCC - 0.2 V 4 mA ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage -0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1 mA 0.4 V VOH Output high voltage IOH = -1 mA 2.4 u d o 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V (except where noted). 2. Outputs deselected. ) s ( ct V r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 5746 Rev 7 17/23 DC and AC parameters M48T128Y Figure 11. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSS tDR tF tREC tFB INPUTS tRB DON'T CARE RECOGNIZED RECOGNIZED ) s ( ct HIGH-Z VALID OUTPUTS Table 10. tF tFB(3) u d o r P e Power down/up AC characteristics t e l o Parameter(1) Symbol (2) VALID Min VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time tR VPFD (min) to VPFD (max) VCC rise time tRB VSS to VPFD (min) VCC rise time tREC VPFD (max) to inputs recognized )- s b O s ( t c Max AI03612 Unit 300 s 10 s 0 s 1 s 40 200 ms 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V (except where noted). u d o 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). r P e 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 11. Power down/up trip points DC characteristics t e l o Symbol Parameter(1)(2) VPFD Power-fail deselect voltage VSO Battery backup switchover voltage tDR(3) Expected data retention time s b O Min Typ Max Unit 4.1 4.35 4.5 V 3.0 10 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V (except where noted). 3. At 25 C; VCC = 0 V. 18/23 Doc ID 5746 Rev 7 V YEARS M48T128Y 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 1. PMDIP32 - 32-pin plastic module DIP, package outline A A1 B S L e1 u d o e3 D r P e N t e l o E 1 Note: bs O ) Drawing is not to scale. Table 12. s ( t c mm du Typ A1 o r P inches Min Max 9.27 Typ Min Max 9.52 0.365 0.375 0.38 - 0.015 - 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e t e ol B s b O PMDIP PMDIP32 - 32-pin plastic module DIP, package mechanical data Symb A ) s ( ct C eA e3 38.1 1.5 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 Doc ID 5746 Rev 7 32 19/23 Environmental information 7 M48T128Y Environmental information Figure 12. Recycling symbols ) s ( ct u d o r P e This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. t e l o Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. ) (s s b O t c u d o r P e t e l o s b O 20/23 Doc ID 5746 Rev 7 M48T128Y 8 Part numbering Part numbering Table 13. Ordering information scheme Example: M48T 128Y -70 PM 1 Device type M48T Supply voltage and write protect voltage ) s ( ct 128Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.1 to 4.5 V u d o Speed -70 = 70 ns r P e Package t e l o PM = PMDIP32 Temperature range ) (s 1 = 0 to 70C s b O t c u Shipping method blank = Ecopack(R) package, tubes d o r P e 1. Device is not recommended for new design. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. t e l o s b O Doc ID 5746 Rev 7 21/23 Revision history 9 M48T128Y Revision history Table 14. Document revision history Date Revision Jun-1998 1 Changes First issue 31-Jan-2000 1.1 Calibrating the clock paragraph changed 30-Mar-2000 1.2 Storage temperature changed (Table 6) 20-Jul-2001 2 21-Sep-2001 2.1 Corrected speed grade in ordering information 23-May-2002 2.2 Add countries to disclaimer; add marketing status 07-Aug-2002 2.3 Refine marketing status text Reformatted; temperature information added to tables (Table 8, 9, 3, 4, 10, 11) u d o 28-Mar-2003 3 v2.2 template applied; test condition updated (Table 11) 06-Aug-2004 4 Reformatted; updated register map (Table 5) 22-Feb-2005 5 IR reflow update (Table 6) 18-Jun-2010 6 Updated Features, Section 4, Table 12, 13; added ECOPACK(R) text to Section 6; added Section 7: Environmental information; reformatted document. 19-Sep-2011 7 Device is not recommended for new design (updated cover page, Table 13); updated footnote of Table 6; updated Section 7: Environmental information; removed M48T128V. r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 22/23 ) s ( ct Doc ID 5746 Rev 7 M48T128Y ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. 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