Not recommended for new design
This is information on a product still in production but not recommended for new designs.
September 2011 Doc ID 5746 Rev 7 1/23
1
M48T128Y
5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
Features
■Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
■BCD coded year, month, day, date, hours,
minutes, and seconds
■Automatic power-fail chip deselect and WRITE
protection
■WRITE protect voltage
VCC = 4.5 to 5.5 V; 4.1 V ≤ VPFD ≤ 4.5 V
(VPFD = power-fail deselect voltage)
■Conventional SRAM operation; unlimited
WRITE cycles
■Software-controlled clock calibration for high
accuracy applications
■10 years of data retention and clock operation
in the absence of power
■Self-contained battery and crystal in the DIP
package
■Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
■RoHS compliant
– Lead-free second level interconnect
32
1
PMDIP32 module
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Contents M48T128Y
2/23 Doc ID 5746 Rev 7
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Obsolete Product(s) - Obsolete Product(s)
M48T128Y List of tables
Doc ID 5746 Rev 7 3/23
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. PMDIP32 – 32-pin plastic module DIP, package mechanical data. . . . . . . . . . . . . . . . . . . 19
Table 13. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Obsolete Product(s) - Obsolete Product(s)
List of figures M48T128Y
4/23 Doc ID 5746 Rev 7
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Description
Doc ID 5746 Rev 7 5/23
1 Description
The M48T128Y TIMEKEEPER® RAM is a 128 Kb x 8 non-volatile static RAM and real-time
clock. The special DIP package provides a fully integrated battery-backed memory and real-
time clock solution. The M48T128Y directly replaces industry standard 128 Kb x 8 SRAM.
It also provides the non-volatility of Flash without any requirement for special WRITE timing
or limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
hybrid houses a controller chip, SRAM, quartz crystal, and a long-life lithium button cell in a
single package.
Figure 1. Logic diagram
Table 1. Signal names
A0-A16 Address inputs
DQ0-DQ7 Data inputs / outputs
EChip enable
GOutput enable
WWRITE enable
VCC Supply voltage
VSS Ground
NC Not connected internally
AI02244
17
A0-A16 DQ0-DQ7
VCC
M48T128Y
G
VSS
8
E
W
Obsolete Product(s) - Obsolete Product(s)
Description M48T128Y
6/23 Doc ID 5746 Rev 7
Figure 2. DIP connections
Figure 3. Block diagram
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
A16
NC VCC
AI02245
M48T128Y
10
1
2
5
6
7
8
9
11
12
13
14
15
16
30
29
26
25
24
23
22
21
20
19
18
17
A12
A14
W
NC
3
4
28
27
32
31
AI01804
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC VSS
32,768 Hz
CRYSTA L
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8
TIMEKEEPER
REGISTERS
131,064 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
E
W
G
POWER
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Operation modes
Doc ID 5746 Rev 7 7/23
2 Operation modes
Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock
oscillator. The clock locations contain the year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day
months are made automatically. Byte 1FFF8h is the clock control register. This byte controls
user access to the clock information and also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations
consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The
M48T128Y includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. The M48T128Y also has its own
power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an
out of tolerance condition. When VCC is out of tolerance, the circuit write protects the
TIMEKEEPER® register data and external SRAM, providing data security in the midst of
unpredictable system operation. As VCC falls below the battery backup switchover voltage
(VSO), the control circuitry automatically switches to the battery, maintaining data and clock
operation until valid power is restored.
Table 2. Operating modes
Note: X = VIH or VIL; VSO = battery backup switchover voltage.
Mode VCC E G W DQ0-DQ7 Power
Deselect
4.5 to 5.5 V
VIH X X High Z Standby
WRITE VIL XV
IL DIN Active
READ VIL VIL VIH DOUT Active
READ VIL VIH VIH High Z Active
Deselect VSO to VPFD (min)(1)
1. See Table 11 on page 18 for details.
X X X High Z CMOS standby
Deselect ≤ VSO(1) X X X High Z Battery backup mode
Obsolete Product(s) - Obsolete Product(s)
Operation modes M48T128Y
8/23 Doc ID 5746 Rev 7
2.1 READ mode
The M48T128Y is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed.
Valid data will be available at the data I/O pins within tAVQV (address access time) after the
last address input signal is stable, providing the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access times (tELQV) or output enable access time (tGLQV). The state of the eight
three-state data I/O signals is controlled by E and G. If the outputs are activated before
tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs
are changed while E and G remain active, output data will remain valid for tAXQX (output
data hold time) but will go indeterminate until the next address access.
Figure 4. READ mode AC waveforms
Note: WE = High.
Table 3. READ mode AC characteristics
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V (except where noted).
M48T128Y Unit
Min Max
tAVAV READ cycle time 70 ns
tAVQV Address valid to output valid 70 ns
tELQV Chip enable low to output valid 70 ns
tGLQV Output enable low to output valid 40 ns
tELQX(2)
2. CL = 5 pF.
Chip enable low to output transition 5 ns
tGLQX(2) Output enable low to output transition 5 ns
tEHQZ(2) Chip enable high to output Hi-Z 25 ns
tGHQZ(2) Output enable high to output Hi-Z 25 ns
tAXQX Address transition to output transition 10 ns
AI01197
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Operation modes
Doc ID 5746 Rev 7 9/23
2.2 WRITE mode
The M48T128Y is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are
low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or
tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W
falls.
Figure 5. WRITE enable controlled, WRITE AC waveform
Figure 6. Chip enable controlled, WRITE AC waveforms
AI02382
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI02383
tAVAV
tEHAX
tDVEH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
Obsolete Product(s) - Obsolete Product(s)
Operation modes M48T128Y
10/23 Doc ID 5746 Rev 7
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
With valid VCC applied, the M48T128Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF
. The M48T128Y/ may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data and powering the clock. The internal energy source will maintain data in the
M48T128Y for an accumulated period of at least 10 years at room temperature. As system
power rises above VSO, the battery is disconnected, and the power supply is switched to
external VCC. Deselect continues for tREC after VCC reaches VPFD (max).
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V (except where noted).
M48T128Y
Unit
Min Max
tAVAV WRITE cycle time 70 ns
tAVWL Address valid to WRITE enable low 0 ns
tAVEL Address valid to chip enable low 0 ns
tWLWH WRITE enable pulse width 50 ns
tELEH Chip enable low to chip enable 1 high 55 ns
tWHAX WRITE enable high to address transition 5 ns
tEHAX Chip enable high to address transition 10 ns
tDVWH Input valid to WRITE enable high 30 ns
tDVEH Input valid to chip enable high 30 ns
tWHDX WRITE enable high to input transition 5 ns
tEHDX Chip enable high to input transition 10 ns
tWLQZ(2)(3)
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z 25 ns
tAVWH Address valid to WRITE enable high 60 ns
tAVEH Address valid to chip enable high 60 ns
tWHQX(2)(3) WRITE enable high to output transition 5 ns
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Clock operations
Doc ID 5746 Rev 7 11/23
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER registers are updated
simultaneously. A halt will not interrupt an update in progress. Updating is within a second
after the bit is reset to a '0.'
3.2 Setting the clock
Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 12).
Resetting the WRITE bit to a '0' then transfers the values of all time registers 1FFFFh-
1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After
the WRITE bit is reset, the next clock update will occur one second later.
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the
oscillator. The M48T128Y is shipped from STMicroelectronics with the STOP bit set to a '1.'
When reset to a '0,' the M48T128Y oscillator starts after one second.
Obsolete Product(s) - Obsolete Product(s)
Clock operations M48T128Y
12/23 Doc ID 5746 Rev 7
Table 5. Register map
Keys:
S = SIGN bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
3.4 Calibrating the clock
The M48T128Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768
Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock accuracy will
not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to
about ±1.53 minutes per month. When the Calibration circuit is properly employed, accuracy
improves to better than +1/–2 ppm at 25 °C. The oscillation rate of crystals changes with
temperature (see Figure 7 on page 13). The M48T128Y design employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 128 stage, as shown in Figure 8 on page 13.
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120
actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in
the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of
the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75 minutes per month.
Address
Data Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
1FFFFh 10 years Year Year 00-99
1FFFEh 0 0 0 10 M Month Month 01-12
1FFFDh 0 0 10 date Date Date 01-31
1FFFCh 0 FT 0 0 0 Day Day 01-07
1FFFBh 0 0 10 hours Hours Hours 00-23
1FFFAh 0 10 minutes Minutes Minutes 00-59
1FFF9h ST 10 seconds Seconds Seconds 00-59
1FFF8h W R S Calibration Control
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Clock operations
Doc ID 5746 Rev 7 13/23
One method is available for ascertaining how much calibration a given M48T128Y may
require. This involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be
found in the STMicroelectronics application note, “TIMEKEEPER calibration.”
This allows the designer to give the end user the ability to calibrate the clock as the
environment requires, even if the final product is packaged in a non-user serviceable
enclosure. The designer could provide a simple utility that accesses the calibration byte. For
example, a deviation of 21 seconds slow over a period of 30 days would indicate a –8 ppm
oscillator frequency error, requiring a +2(WR100010) to be loaded into the calibration byte
for correction.
Figure 7. Crystal accuracy across temperature
Figure 8. Clock calibration
AI02124
-80
-60
-100
-40
-20
0
20
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
ΔF= -0.038 (T - T0)2 ± 10%
F
ppm
C2
T0 = 25 °C
ppm
°C
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Obsolete Product(s) - Obsolete Product(s)
Clock operations M48T128Y
14/23 Doc ID 5746 Rev 7
3.5 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 9. Supply voltage protection
AI02169
VCC
0.1µF DEVICE
VCC
VSS
Obsolete Product(s) - Obsolete Product(s)
M48T128Y Maximum ratings
Doc ID 5746 Rev 7 15/23
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6. Absolute maximum ratings
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Symbol Parameter Value Unit
TAAmbient operating temperature 0 to 70 °C
TSTG Storage temperature (VCC off, oscillator off) –40 to 85 °C
TSLD(1)(2)
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltages –0.3 to 7 V
VCC Supply voltage –0.3 to 7 V
IOOutput current 20 mA
PDPower dissipation 1 W
Obsolete Product(s) - Obsolete Product(s)
DC and AC parameters M48T128Y
16/23 Doc ID 5746 Rev 7
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7. Operating and AC measurement conditions
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 10. AC testing load circuit
Table 8. Capacitance
Parameter M48T128Y Unit
Supply voltage (VCC) 4.5 to 5.5 V
Ambient operating temperature (TA) 0 to 70 °C
Load capacitance (CL)100pF
Input rise and fall times ≤ 5ns
Input pulse voltages 0 to 3 V
Input and output timing ref. voltages 1.5 V
Symbol Parameter(1)(2)
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
Min Max Unit
CIN Input capacitance - 20 pF
CIO(3)
3. Outputs deselected.
Input / output capacitance - 20 pF
AI03630
CL = 100pF
CL includes JIG capacitance
650Ω
DEVICE
UNDER
TEST
1.75V
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M48T128Y DC and AC parameters
Doc ID 5746 Rev 7 17/23
Table 9. DC characteristics
Symbol Parameter Test condition(1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V (except where noted).
M48T128Y
Unit
Min Max
ILI Input leakage current 0 V ≤ VIN ≤ VCC ±2 µA
ILO(2)
2. Outputs deselected.
Output leakage current 0 V ≤ VOUT ≤ VCC ±2 µA
ICC Supply current Outputs open 95 mA
ICC1 Supply current (standby) TTL E = VIH 8mA
ICC2 Supply current (standby) CMOS E = VCC – 0.2 V 4 mA
VIL Input low voltage –0.3 0.8 V
VIH Input high voltage 2.2 VCC + 0.3 V
VOL Output low voltage IOL = 2.1 mA 0.4 V
VOH Output high voltage IOH = –1 mA 2.4 V
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DC and AC parameters M48T128Y
18/23 Doc ID 5746 Rev 7
Figure 11. Power down/up mode AC waveforms
Table 10. Power down/up AC characteristics
Table 11. Power down/up trip points DC characteristics
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V (except where noted).
Min Max Unit
tF(2)
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
VPFD (max) to VPFD (min) VCC fall time 300 µs
tFB(3)
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
VPFD (min) to VSS VCC fall time 10 µs
tRVPFD (min) to VPFD (max) VCC rise time 0 µs
tRB VSS to VPFD (min) VCC rise time 1 µs
tREC VPFD (max) to inputs recognized 40 200 ms
Symbol Parameter(1)(2)
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V (except where noted).
Min Typ Max Unit
VPFD Power-fail deselect voltage 4.1 4.35 4.5 V
VSO Battery backup switchover voltage 3.0 V
tDR(3)
3. At 25 °C; VCC = 0 V.
Expected data retention time 10 YEARS
AI03612
VCC
INPUTS
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tDR
tREC
tRB
VALID VALID
RECOGNIZEDRECOGNIZED
VPFD (max)
VPFD (min)
VSS
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M48T128Y Package mechanical data
Doc ID 5746 Rev 7 19/23
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 1. PMDIP32 – 32-pin plastic module DIP, package outline
Note: Drawing is not to scale.
Table 12. PMDIP32 – 32-pin plastic module DIP, package mechanical data
PMDIP
A1
A
L
Be1
D
E
N
1
eA
e3
S
C
Symb
mm inches
Typ Min Max Typ Min Max
A 9.27 9.52 0.365 0.375
A1 0.38 – 0.015 –
B 0.43 0.59 0.017 0.023
C 0.20 0.33 0.008 0.013
D 42.42 43.18 1.670 1.700
E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 38.1 1.5
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110
N32 32
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Environmental information M48T128Y
20/23 Doc ID 5746 Rev 7
7 Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
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M48T128Y Part numbering
Doc ID 5746 Rev 7 21/23
8 Part numbering
Table 13. Ordering information scheme
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Example: M48T 128Y –70 PM 1
Device type
M48T
Supply voltage and write protect voltage
128Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.1 to 4.5 V
1. Device is not recommended for new design. Contact local ST sales office for availability.
Speed
–70 = 70 ns
Package
PM = PMDIP32
Temperature range
1 = 0 to 70°C
Shipping method
blank = Ecopack® package, tubes
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Revision history M48T128Y
22/23 Doc ID 5746 Rev 7
9 Revision history
Table 14. Document revision history
Date Revision Changes
Jun-1998 1 First issue
31-Jan-2000 1.1 Calibrating the clock paragraph changed
30-Mar-2000 1.2 Storage temperature changed (Ta b l e 6 )
20-Jul-2001 2 Reformatted; temperature information added to tables (Ta b l e 8 , 9, 3, 4,
10, 11)
21-Sep-2001 2.1 Corrected speed grade in ordering information
23-May-2002 2.2 Add countries to disclaimer; add marketing status
07-Aug-2002 2.3 Refine marketing status text
28-Mar-2003 3 v2.2 template applied; test condition updated (Ta b l e 1 1 )
06-Aug-2004 4 Reformatted; updated register map (Ta bl e 5 )
22-Feb-2005 5 IR reflow update (Tab le 6)
18-Jun-2010 6
Updated Features, Section 4, Ta bl e 1 2 , 13; added ECOPACK® text to
Section 6; added Section 7: Environmental information; reformatted
document.
19-Sep-2011 7
Device is not recommended for new design (updated cover page,
Tab le 1 3 ); updated footnote of Ta bl e 6 ; updated Section 7:
Environmental information; removed M48T128V.
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M48T128Y
Doc ID 5746 Rev 7 23/23
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