LTC3533
1
3533f
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
2A Wide Input Voltage
Synchronous Buck-Boost
DC/DC Converter
The LTC
®
3533 is a wide VIN range, highly effi cient, fi xed
frequency, buck-boost DC/DC converter that operates
from input voltages above, below or equal to the output
voltage. The topology incorporated in the IC provides a
continuous transfer function through all operating modes,
making the product ideal for single cell lithium-ion/polymer
or multi-cell alkaline/NiMH applications where the output
voltage is within the input voltage range.
The LTC3533 features programmable Burst Mode opera-
tion, extended VIN and VOUT ranges down to 1.8V, and
increased output current. Switching frequencies up to
2MHz are programmed with an external resistor. The Burst
Mode threshold is programmed with a single resistor from
the BURST pin to GND.
Other features include 1µA shutdown current, short
circuit protection, programmable soft-start, current limit
and thermal shutdown. The LTC3533 is housed in the
thermally enhanced 14-lead (3mm × 4mm × 0.75mm)
DFN package.
Effi ciency
■ Regulated Output with Input Voltages Above,
Below or Equal to the Output
■ 1.8V to 5.5V (Input) and 5.25V (Output)
Voltage Range
■ 0.8A Continuous Output Current: VIN > 1.8V
■ 2A Continuous Output Current: VIN > 3V
■ Single Inductor
■ Synchronous Rectifi cation: Up to 96% Effi ciency
■ Programmable Burst Mode
®
Operation: IQ = 40µA
■ Output Disconnect in Shutdown
■ Programmable Frequency from 300kHz to 2MHz
■ <1µA Shutdown Current
■ Small Thermally Enhanced 14-Lead (3mm × 4mm ×
0.75mm) DFN package
■ GSM Modems
■ Handheld Instruments
■ Digital Cameras
■ Smart Phones
■ Media Players
■ Miniature Hard Disk Drive Power
SW1
PVIN
VIN
RUN/SS
RT
SW2
PVOUT
VOUT
FB
LTC3533
10µF
VIN
2.4V TO 4.2V
340k 6.49k
100µF
47pF
VOUT
3.3V
1.5A
200k
0.1µF
107k 330pF
4.7pF
3533 TA01
2.2µH
33.2k 200k
PGNDSGND
ONOFF
BURST
VC
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1 10 100 1000 10000
3533 TA01b
30
20
10
0
90
100
Burst Mode
OPERATION
VIN = 3.9V
VIN = 2.2V
VIN = 2.9V
LTC3533
2
3533f
PACKAGE/ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
VIN, PVIN Voltages ...........................................–0.3 to 6V
VOUT, PVOUT Voltages ......................................–0.3 to 6V
SW1, SW2 Voltages
DC ...............................................................–0.3 to 6V
Pulsed < 100ns ...........................................–0.3 to 7V
VC, FB, RUN/SS, BURST Voltages ..................–0.3 to 6 V
Operating Temperature Range (Note 2) ... –40°C to 85°C
Maximum Junction Temperature (Note 3) ............ 125°C
Storage Temperature Range ................... –65°C to 125°C
(Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Operating Range ●1.8 5.5 V
Output Voltage Adjust Range ●1.8 5.25 V
Feedback Voltage ●1.196 1.22 1.244 V
Feedback Input Current VFB = 1.22V 1 50 nA
Quiescent Current – Burst Mode Operation VC = 0V, VBURST = 0V (Note 4) 40 50 µA
Quiescent Current – Shutdown VRUN = 0V, Not Including Switch Leakage 0.1 1 µA
Quiescent Current – Active VC = 0V, BURST = 3.6V (Note 4) 700 1100 µA
Input Current Limit ●3.5 4.5 A
Peak Current Limit 7A
Reverse Current Limit 0.5 A
NMOS Switch Leakage Switches B and C 0.1 5 µA
PMOS Switch Leakage Switches A and D 0.1 10 µA
NMOS Switch On Resistance Switches B and C 60 mΩ
PMOS Switch On Resistance Switches A and D 80 mΩ
Maximum Duty Cycle Boost (% Switch C On)
Buck (% Switch A On)
●
●
80
100
90 %
%
Minimum Duty Cycle ●0%
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VC
FB
RUN/SS
PVIN
VIN
PVOUT
VOUT
RT
BURST
SGND
SW1
PGND
PGND
SW2
TOP VIEW
DE PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
15
TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER DE PART MARKING
LTC3533EDE 3533
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VOUT = 3.3V, unless otherwise noted.
LTC3533
3
3533f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note2: The LTC3533EDE is guaranteed to meet performance specifi cations
from 0ºC to 85ºC. Specifi cations over the –40ºC to 85ºC operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Frequency Accuracy RT = 33.2k ●0.7 1 1.3 MHz
Error Amp AVOL 80 dB
Error Amp Source Current –20 µA
Error Amp Sink Current 250 µA
Burst Threshold 1V
Burst Input Current VBURST = 5.5V, VIN = 5.5V 8 µA
RUN/SS Threshold When IC is Enabled
When EA is at Maximum Boost Duty Cycle
●0.4 0.7
1.3
1.4 V
V
RUN/SS Input Current VRUN = 5.5V 0.01 1 µA
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VOUT = 3.3V, unless otherwise noted.
Note 3: This IC includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when over-temperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may result in device degradation or failure.
Note 4: Current Measurements are performed when the outputs are not
switching.
LTC3533
4
3533f
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs VIN
(Fixed Frequency Mode) Burst Mode Quiescent Current
Peak Current Limit vs
Temperature
Automatic Burst Mode Threshold
vs RBURST
Minimum Start Voltage vs
Temperature
Average Input Current Limit vs
Temperature
Frequency Change vs
Temperature Feedback Voltage vs Temperature
Switch Pins Before Entering
Boost Mode
TA = 25°C, unless otherwise specifi ed.
VIN (V)
2.5
VIN QUIESCENT CURRENT (mA)
4.0 5.0
3533 G01
3.0 3.5 4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 5.5
2.0 MHz
1.5 MHz
1.0 MHz
0.5 MHz
NO SWITCHING
VIN (V)
2.5
VIN QUIESCENT CURRENT (µA)
3.0 3.5 4.0 4.5
3530 G02
5.0
50
45
40
35
30
25
20
15
10
5
0
5.5
TEMPERATURE (°C)
–55
–5
CURRENT LIMIT CHANGE (%)
–4
–2
–1
0
5
2
–15 25 45 125
3533 G03
–3
3
4
1
–35 5 65 85 105
RBURST (kΩ)
100
0
LOAD CURRENT (mA)
50
100
150
200
125 150 175 200
3533 G04
225 250
LEAVE Burst Mode
OPERATION
ENTER Burst Mode
OPERATION
TEMPERATURE (°C)
–45
MINIMUM START VOLTAGE (V)
1.78
1.80
1.82
75
3533 G05
1.76
1.74
–5 35
–25 95
15 55 115
1.72
1.70
1.84
TEMPERATURE (°C)
–55
CHANGE FROM 25°C (%)
5
4
3
2
1
0
–1
–2
–3
–4
–5 –15 25 45 125
3533 G06
–35 5 65 85 105
TEMPERATURE (°C)
–55
1.056
FREQUENCY (MHz)
1.058
1.062
1.064
1.066
1.076
1.070
–15 25 45 125
3533 G07
1.060
1.072
1.074
1.068
–35 5 65 85 105
TEMPERATURE (°C)
–55
1.2100
FEEDBACK VOLTAGE (V)
1.2200
–15 25 45 125
3533 G08
1.2150
–35 5 65 85 105
1.2250
50ns/DIV 3533 G09
SW1
2V/DIV
SW2
2V/DIV
VIN = 2.9V
VOUT = 3.3V AT 500mA
LTC3533
5
3533f
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Pins in Buck-Boost Mode
Switch Pins Entering Buck-Boost
Mode Output Ripple at 1A Load
Load Transient Response in Fixed
Frequency Mode, No Load to 1.5A
Load Transient Response in Auto
Burst Mode, No Load to 600mA
Burst Mode Operation
Transition from Burst Mode
Operation to Fixed Frequency Mode
TA = 25°C, unless otherwise specifi ed.
50ns/DIV 3533 G10
SW1
2V/DIV
SW2
2V/DIV
VIN = 3.3V
VOUT = 3.3V AT 500mA
50ns/DIV 3533 G11
SW1
2V/DIV
SW2
2V/DIV
VIN = 4.2V
VOUT = 3.3V AT 500mA
1µs/DIV 3533 G12
VOUT = 3.3V, 20mV/DIV
COUT = 100µF CERAMIC
VIN = 4.2V
VIN = 3.3V
VIN = 2.7V
20µs/DIV 3533 G15
COUT = 100µF CERAMIC
INDUCTOR
CURRENT
0.5A/DIV
VOUT
50mV/DIV
200µs/DIV 3533 G16
COUT = 100µF CERAMIC
INDUCTOR
CURRENT
0.5A/DIV
VOUT
50mV/DIV
VOUT
100mV/DIV
IL
0.5A/DIV
100µs/DIV
VIN = 3.6V
VOUT = 3.3V
COUT = 100µF X5R CERAMIC
3533 G13
VOUT
100mV/DIV
LOAD
0.5A/DIV
100µs/DIV 3533 G14
VIN = 3.6V
VOUT = 3.3V
COUT = 100µF X5R CERAMIC +
100µF LOW ESR TANTALUM
LTC3533
6
3533f
PIN FUNCTIONS
RT (Pin 1): Programs the Frequency of the Internal Oscil-
lator. Connect a resistor from RT to ground.
f(kHz) = 33,170/RT (kΩ)
BURST (Pin 2): Used to set the Automatic Burst Mode
Threshold. Connect a resistor and capacitor in parallel
from this pin to ground. See the Applications Information
section for component value selection. For manual control,
ground the pin to force Burst Mode operation, connect to
VIN to force fi xed frequency PWM mode.
SGND (Pin 3): Signal ground for the IC.
SW1 (Pin 4): Switch Pin where Internal Switches A and B
are Connected. Connect inductor from SW1 to SW2. An
optional Schottky diode can be connected from SW1 to
ground for a moderate effi ciency improvement. Minimize
trace length to reduce EMI.
PGND1, PGND2 (Pins 5, 6): Power Ground for the Internal
NMOS Power Switches.
SW2 (Pin 7): Switch Pin where Internal Switches C and
D are Connected. An optional Schottky diode can be
connected from SW2 to VOUT for a moderate effi ciency
improvement. For applications with output voltages over
4.3V, this Schottky diode is required to ensure the SW2
pin does not exhibit excess voltage. Minimize trace length
to reduce EMI.
VOUT (Pin 8): Voltage Sensing Pin for PVOUT and Input
Supply Pin for Internal Circuitry Powered by PVOUT. A fi lter
capacitor is placed from VOUT to GND. A ceramic bypass
capacitor is recommended as close to the VOUT and GND
pins as possible.
PVOUT (Pin 9): Output of the Synchronous Rectifi er. A
fi lter capacitor is placed from PVOUT to PGND. A ceramic
bypass capacitor is recommended as close to the PVOUT
and PGND pins as possible.
VIN (Pin 10): Input Supply Pin. Internal VCC for the IC.
PVIN (Pin 11): Power VIN Supply Pin. A 10µF ceramic
capacitor is recommended as close to the PVIN and PGND
pins as possible.
RUN/SS (Pin 12): Combined Enable and Soft-Start. Applied
voltage <0.4V shuts down the IC. Tie to >1.4V to enable
the IC and >1.6V to ensure the error amp is not clamped
from soft-start. An RC from the shutdown command signal
to this pin will provide a soft-start function by limiting the
rise time of VC
FB (Pin 13): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 1.8V to
5.25V. The feedback reference voltage is typically 1.22V.
VRR
R
OUT =+
122 12
2
.•
VC (Pin 14): Error Amp Output. An R-C network is con-
nected from this pin to FB for loop compensation. Refer
to “Closing the Feedback Loop” section for component
selection guidelines. During Burst Mode operation, VC is
internally connected to a hold circuit.
Exposed Pad (Pin 15): IC Substrate Ground. This pin must
be soldered to the PCB ground to provide both electrical
contact and a good thermal contact to the PCB.
LTC3533
7
3533f
BLOCK DIAGRAM
–
+
–
+
–
+
–
+
–
+
–
+
PWM
LOGIC
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTI-CROSS
CONDUCTION
GND
UVLO
4.5A
1.6V
OSC
SUPPLY
CURRENT
LIMIT
SW A
SW1
VIN
1.8V TO 5.5V
SW2
SW D
ERROR
AMP
CLAMP
1.22V
ISENSE
AMP
REVERSE
CURRENT
LIMIT
SW B
RUN
SLEEP
SW C
VOUT
FB
RUN/SS RSS
CSS
VC
VIN
BURST
0 = BURST MODE
1 = FIXED FREQUENCY
RT
RT
3533 BD
PWM
COMPARATORS
BURST MODE
OPERATION
CONTROL
–0.5A
+
R1
R2
OPERATION
The LTC3533 provides high effi ciency, low noise power
for a wide variety of handheld electronic devices. The LTC
proprietary topology allows input voltages above, below
or equal to the output voltage by properly phasing the
output switches. The error amplifi er output voltage on VC
determines the output duty cycle of the switches. Since
VC is a fi ltered signal, it provides rejection of frequencies
well below the switching frequency. The low RDS(ON), low
gate charge synchronous switches provide high frequency
pulse width modulation control at high effi ciency. High
effi ciency is achieved at light loads when Burst Mode
operation is entered and the LTC3533’s quiescent current
drops to a low 40µA.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The frequency of operation is programmed by an external
resistor from RT to ground, according to the following
equation:
f(kHz) = 33,170/RT(k)
LTC3533
8
3533f
OPERATION
Error Amplifi er
The error amplifi er is a voltage mode amplifi er. The loop
compensation components are confi gured around the
amplifi er (from FB to VC) to obtain stability of the converter.
For improved bandwidth, an additional RC feed-forward
network can be placed across the upper feedback divider
resistor. The voltage on the RUN/SS pin clamps the error
amplifi er output, VC, to provide a soft-start function.
Supply Current Limits
There are two different supply current limit circuits in the
LTC3533, working consecutively, each having internally
fi xed thresholds which vary inversely with VIN.
The fi rst circuit is a current limit amplifi er, sourcing cur-
rent into FB to drop the output voltage, should the peak
input current exceed 4.5A typical. This method provides a
closed loop means of clamping the input current. During
conditions where VOUT is near ground, such as during a
short circuit or startup, this threshold is cut to 750mA,
providing a fold-back feature. For this current limit feature
to be most effective, the Thevenin resistance from FB to
ground should be greater than 100k.
Should the peak input current exceed 7A typical, the second
circuit, a high speed peak current limit comparator, shuts
off PMOS switch A. The delay to output of this comparator
is typically 50ns.
Reverse Current Limit
During fi xed frequency operation, the LTC3533 operates in
forced continuous conduction mode. The reverse current
limit comparator monitors the inductor current from the
output through switch D. Should this negative inductor
current exceed 500mA typical, the LTC3533 shuts off
switch D.
Four-Switch Control
Figure 1 shows a simplifi ed diagram of how the four in-
ternal switches are connected to the inductor, VIN, VOUT
and GND.Figure 2 shows the regions of operation for the
LTC3533 as a function of the control voltage, VC.
Dependent on VC’s magnitude, the LTC3533 will operate
in either buck, buck/boost or boost mode. The four power
switches are properly phased so the transfer between op-
erating modes is continuous, smooth and transparent to
the user. When VIN approaches VOUT the buck/boost region
is entered, where the conduction time of the four switch
region is typically 150ns. Referring to Figures 1 and 2, the
various regions of operation will now be described.
Buck Region (VIN > VOUT)
Switch D is always on and switch C is always off during
this mode. When the control voltage, VC, is above volt-
age V1, switch A begins to switch. During the off time of
switch A, synchronous switch B turns on for the remainder
of the period. Switches A and B will alternate similar to a
typical synchronous buck regulator. As the control volt-
age increases, the duty cycle of switch A increases until
the maximum duty cycle of the converter in buck mode
reaches DMAX_BUCK, given by:
D
MAX_BUCK = 100 – D4SW %
where D4SW = duty cycle % of the four switch range.
3
SW1
7
SW2
PMOS A
NMOS B
11
PVIN
PMOS D
NMOS C
3533 F01
9
PVOUT
L1
85%
DMAX
BOOST
DMIN
BOOST
DMAX
BUCK
DUTY
CYCLE
0%
V4 (≈1.5V)
V3 (≈1.15V)
BOOST REGION
BUCK REGION
BUCK/BOOST REGION
V2 (≈1V)
V1 (≈0.7V)
3533 F02
A ON, B OFF
PWM CD SWITCHES
D ON, C OFF
PWM AB SWITCHES
FOUR SWITCH PWM
CONTROL
VOLTAGE, VC
Figure 1. Simplifi ed Diagram of Output Switches Figure 2. Switch Control vs Control Voltage, VC
LTC3533
9
3533f
OPERATION
D4SW = (150ns • f) • 100 %
where f = operating frequency, Hz.
Beyond this point the “four switch,” or buck/boost region
is reached.
Buck/Boost or Four Switch (VIN ~ VOUT)
When the control voltage, VC, is above voltage V2, switch
pair AD remain on for duty cycle DMAX_BUCK, and switch
pair AC begins to phase in. As switch pair AC phases in,
switch pair BD phases out accordingly. When VC reaches
the edge of the buck/boost range, at voltage V3, the AC
switch pair completely phase out the BD pair, and the boost
phase begins at duty cycle D4SW. The input voltage, VIN,
where the four switch region begins is given by:
V
IN = VOUT(1 – D) = VOUT(1 – 150ns • f) V
The point at which the four switch region ends is given
by:
VV
ns f V
IN OUT
=−1 150(•)
where f = operating frequency, Hz.
Boost Region (VIN < VOUT)
Switch A is always on and switch B is always off during
this mode. When the control voltage, VC, is above volt-
age V3, switch pair CD will alternately switch to provide
a boosted output voltage. This operation is typical to a
synchronous boost regulator. The maximum duty cycle
of the converter is limited to 90% typical and is reached
when VC is above V4.
BURST MODE OPERATION
Burst Mode operation reduces the LTC3533’s quiescent
current consumption at light loads and improves overall
conversion effi ciency, increasing battery life. During Burst
Mode operation the LTC3533 delivers energy to the out-
put until it is regulated and then goes into a sleep mode
where the outputs are off and the quiescent current drops
to 40µA. In this mode the output ripple has a variable
frequency component that depends upon load current,
and will typically be about 2% peak-to-peak. Burst Mode
operation ripple can be reduced slightly by using more
output capacitance. Another method of reducing Burst
Mode operation ripple is to place a small feed-forward
capacitor across the upper resistor in the VOUT feedback
divider network (as in Type III compensation).
During the period where the device is delivering energy
to the output, the peak switch current will rise to 450mA
typical and the inductor current will terminate at zero cur-
rent for each cycle. In this mode, the typical maximum
average output currents are given by:
I
MAX(BURST)BUCK ≈ 225mA; VOUT < VIN
I
MAX(BURST)BOOST ≈ 225mA • (VIN/VOUT); VOUT > VIN
IMAX(BURST)BUCK-BOOST ≈ 350mA; VOUT ≈ VIN, since the
input and output are connected together for most of the
cycle.
The effi ciency below 1mA becomes dominated primarily
by the quiescent current. The Burst Mode operation ef-
fi ciency is given by:
Efficiency I
AI
LOAD
LOAD
≅+
η
µ
•
40
where η is typically 90% during Burst Mode operation
Programmable Automatic Burst Mode Operation
Burst Mode operation can be automatic or digitally con-
trolled with a single pin. In automatic mode, the LTC3533
enters Burst Mode operation at the programmed threshold
and returns to fi xed frequency operation when the load
demand increases. The load current at which the mode
transition occurs is programmed using a single external
resistor from BURST to ground, according to the follow-
ing equations:
Enter Burst Mode Operation I R
BURST BURST
:=17
EExit Burst Mode Operation I R
BURST BURST
:=19
Where RBURST is in kΩ and IBURST is the load transition
current in Amps. Do not use values of RBURST greater
than 1MΩ.
LTC3533
10
3533f
OPERATION
For automatic operation a fi lter capacitor must also be
connected from BURST to ground. The equation for the
minimum capacitor value is:
CCV
BURST MIN OUT OUT
()
•
,
≥60 000
where CBURST(MIN) and COUT are in µF.
In the event that a load transient causes FB to drop by
more than 4% from the regulation value while in Burst
Mode operation, the LTC3533 will immediately switch
to fi xed frequency mode and an internal pull-up will be
momentarily applied to BURST, rapidly charging CBURST.
This prevents the IC from immediately re-entering Burst
mode operation once the output achieves regulation.
Manual Burst Mode Operation
For manual control of Burst Mode operation, the RC
network connected to BURST can be eliminated. To force
fi xed frequency mode, BURST should be connected to
VIN. To force Burst Mode operation, BURST should be
grounded. When commanding Burst Mode operation
manually, the circuit connected to BURST should be able
to sink up to 2mA.
For optimum transient response with large dynamic loads,
the operating mode should be controlled digitally by the
host. By commanding fi xed frequency operation prior to a
sudden increase in load, output voltage droop can be mini-
mized. Note that if the load current applied during forced
Burst Mode operation (BURST pin is grounded) exceeds
the current that can be supplied, the output voltage will
start to droop and the LTC3533 will automatically come out
of Burst Mode operation and enter fi xed frequency mode,
raising VOUT. Once regulation is achieved, the LTC3533 will
then enter Burst Mode operation once again (since the user
is still commanding this by grounding BURST), and the
cycle will repeat, resulting in about 4% output ripple.
Burst Mode Operation to Fixed Frequency Transient
Response
In Burst Mode operation, the compensation network is
not used and VC is disconnected from the error amplifi er.
During long periods of Burst Mode operation, leakage
currents in the external components or on the PC board
could cause the compensation capacitor to charge (or
discharge), which could result in a large output transient
when returning to fi xed frequency mode of operation, even
at the same load current. To prevent this, the LTC3533
incorporates an active clamp circuit that holds the voltage
on VC at an optimal voltage during Burst Mode operation.
This minimizes any output transient when returning to
fi xed frequency mode operation. For optimum transient
response, Type 3 compensation is also recommended
to broad band the control loop and roll off past the two
pole response of the output LC fi lter. (See Closing the
Feedback Loop).
Soft-Start
The soft-start function is combined with shutdown. When
the RUN/SS pin is brought above 1V typical, the LTC3533
is enabled but the error amplifi er duty cycle is clamped
from VC. A detailed diagram of this function is shown in
Figure 3. The components RSS and CSS provide a slow
ramping voltage on RUN/SS to provide a soft-start function.
To ensure that VC is not being clamped, RUN/SS must be
raised above 1.6V.
VIN
VC
RUN/SS
3533 F03
Figure 3.
LTC3533
11
3533f
APPLICATIONS INFORMATION
Inductor Selection
The high frequency operation of the LTC3533 allows the
use of small surface mount inductors. The inductor ripple
current is typically set to 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
LVVV
fIV
BOOST
IN MIN OUT IN MIN
L OUT
>−
∆
() ()
•( )
••
2
2HH
LVV V
fIV H
BUCK
OUT IN MAX OUT
LINMAX
>−
∆
•( )
••
()
()
where f = switching frequency, Hz
∆IL = maximum allowable inductor ripple current
VIN(MIN) = minimum input voltage
VIN(MAX) = maximum input voltage
VOUT = output voltage
For high effi ciency, choose a ferrite inductor with a high
frequency core material to reduce core losses. The induc-
tor should have low ESR (equivalent series resistance) to
reduce the I2R losses, and must be able to handle the peak
inductor current without saturating. Molded chokes or chip
inductors usually do not have enough core to support the
peak inductor currents in the 4A to 6A region. To minimize
radiated noise, use a shielded inductor. See Table 1 for a
suggested list of inductor suppliers.
Output Capacitor Selection
The bulk value of the output fi lter capacitor is set to reduce
the ripple due to charge into the capacitor each cycle. The
steady state ripple due to charge is given by:
%_ •( )•
() ()
Ripple Boost IVV
OUT MAX OUT IN MIN
=−100
CCV f
Ripple Buck VV
OUT OUT
IN MAX OUT
•• %
%_ ()•
()
2
=−1100
82
LC V f
OUT IN MAX
••
%
()
where COUT = output fi lter capacitor
IOUT(MAX) = maximum output load current
The output capacitance is usually many times larger than
the minimum value in order to handle the transient response
COMPONENT SELECTION
Figure 4. Recommended Component Placement. Traces Carrying
High Current Should be Short and Wide. Trace Area at FB and VC
Pins are Kept Low. Lead Length to Battery Should be Kept Short.
PVOUT and PVIN Ceramic Capacitors Close to the IC Pins.
Table 1. Inductor Vendor Information
SUPPLIER PHONE FAX WEB SITE
Coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com
CoEv Magnetics (800) 227-7040 (650) 361-2508 www.circuitprotection.com/magnetics.asp
Murata (814) 237-1431
(800) 831-9172
(814) 238-0409 www.murata.com
Sumida USA: (847) 956-0666
Japan: 81(3) 3607-5111
USA: (847) 956-0702
Japan: 81(3) 3607-5144
www.sumida.com
TDK (847) 803-6100 (847) 803-6296 www.component.tdk.com
TOKO (847) 297-0070 (847) 699-7864 www.tokoam.com
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VC
FB
RUN/SS
PVIN
VIN
PVOUT
VOUT
RT
BURST
SGND
SW1
PGND
PGND
SW2
VIN
VOUT
3533 F04
MULTIPLE VIAS
GND
LTC3533
12
3533f
APPLICATIONS INFORMATION
requirements of the converter. As a rule of thumb, the ratio
of the operating frequency to the unity-gain bandwidth of
the converter is the amount the output capacitance will
have to increase from the above calculations in order to
maintain the desired transient response.
The other component of ripple is due to the ESR (equiva-
lent series resistance) of the output capacitor. Low ESR
capacitors should be used to minimize output voltage
ripple. For surface mount applications, Taiyo Yuden or
TDK ceramic capacitors, AVX TPS series tantalum capaci-
tors or Sanyo POSCAP are recommended. See Table 2 for
contact information.
Input Capacitor Selection
Since PVIN is the supply voltage for the IC it is recom-
mended to place at least a 4.7µF, low ESR ceramic bypass
capacitor close to PVIN and GND. It is also important to
minimize any stray resistance from the converter to the
battery or other power source.
Optional Schottky Diodes
Schottky diodes across the synchronous switches B and
D are not required, but do provide a lower drop during the
break-before-make time (typically 15ns), thus improving
effi ciency. Use a surface mount Schottky diode such as an
MBRM120T3 or equivalent. Do not use ordinary rectifi er
diodes since their slow recovery times will compromise
effi ciency.
Output Voltage < 1.8V
The LTC3533 can operate as a buck converter with output
voltages as low as 400mV. The part is specifi ed at 1.8V
minimum to allow operation without the requirement of a
Schottky diode; Since synchronous switch D is powered
from PVOUT, and the RDS(ON) will increase at low output
voltages, a Schottky diode is required from SW2 to VOUT
to provide the conduction path to the output. Note that
Burst Mode operation is inhibited at output voltages below
1V typical.
Output Voltage > 4.3V
A Schottky diode from SW2 to VOUT is required for output
voltages over 4.3V. The diode must be located as close to
the pins as possible in order to reduce the peak voltage on
SW2 due to parasitic lead and trace inductances.
Input Voltage > 4.5V
For applications with input voltages above 4.5V which
could exhibit an overload or short-circuit condition, a
2Ω/1nF series snubber is required between SW1 and
GND. A Schottky diode from SW1 to PVIN should also be
added as close to the pins as possible. For the higher input
voltages, VIN bypassing becomes more critical. Therefore,
a ceramic bypass capacitor as close to the PVIN and GND
pins as possible is also required.
Operating Frequency Selection
Higher operating frequencies allow the use of a smaller
inductor and smaller input and output fi lter capacitors,
thus reducing board area and component height. How-
ever, higher operating frequencies also increase the IC’s
total quiescent current due to the gate charge of the four
switches, as given by:
Buck: IQ = (600e – 12 • VIN • f ) mA
Boost: IQ = [800e – 12 • (VIN + VOUT) • f ] mA
Buck/Boost: IQ = [(1400e – 12 • VIN + 400e – 12 •
V
OUT) • f ] mA
where f = switching frequency in Hz. Therefore frequency
selection is a compromise between the optimal effi ciency
and the smallest solution size.
Table 2. Capacitor Vendor Information
SUPPLIER PHONE FAX WEB SITE
AVX (803) 448-9411 (803) 448-1943 www.avxcorp.com
Sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
TDK (847) 803-6100 (847) 803-6296 www.component.tdk.com
LTC3533
13
3533f
APPLICATIONS INFORMATION
Closing the Feedback Loop
The LTC3533 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck/boost), but is usually no greater than
15. The output fi lter exhibits a double pole response, as
given by:
fLC Hz
in buck e
f
FILTER POLE
OUT
F
_•• •
( mod )
=1
2π
IILTER POLE IN
OUT OUT
V
VLC
Hz
in boost
_••••
(
=2π
mmod )e
where L is in Henries and COUT is in Farads.
The output fi lter zero is given by:
fRC
Hz
FILTER ZERO ESR OUT
_•• •
=1
2π
where RESR is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
fV
ILV
Hz
RHPZ IN
OUT OUT
•• ••
=
2
2π
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth
and slower transient response. To ensure proper phase
margin using Type I compensation, the loop must be
crossed over a decade before the LC double pole. Referring
to Figure 5, the unity-gain frequency of the error amplifi er
with the Type I compensation is given by:
fRCHz
UG P
•• •
=1
21
1
π
Most applications demand an improved transient response
to allow a smaller output fi lter capacitor. To achieve a higher
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double-pole response of
the output fi lter. Referring to Figure 6, the location of the
poles and zeros are given by:
feRC
Hz
which is a
POLE
P
131
1
210 1•• • •
(
=
π
very llow frequency)
•• •
fRC
Hz
f
ZERO ZP
ZERO
11
2
1
2
=π
==
=
1
21
1
2
1
22
•• •
•• •
π
π
RCHz
fRCHz
Z
POLE ZP
where resistance is in Ohms and capacitance is in Farads.
1.22V
R1
R2
3533 F05
FB
12
VCCP1
VOUT
11
–
+
ERROR
AMP
1.22V R1
R2
3533 F06
FB
12
VCCP1
CZ1
RZ
VOUT
11
CP2
–
+
ERROR
AMP
Figure 5. Error Amplifi er with Type I Compensation Figure 6. Error Amplifi er with Type III Compensation
LTC3533
14
3533f
TYPICAL APPLICATIONS
High Effi ciency, High Current LED Driver
1MHz Li-Ion to 3.6V at 2A, Pulsed, with Manual Mode Control
SW1
PVIN
VIN
RUN/SS
RT
SW2
PVOUT
VOUT
FB
VC
BURST
LTC3533
10µF
VIN
3V TO 4.2V
4.7µF
ILED = 1A
301k
47pF
100k
100k
1nF
3533 TA02
3.3µH
44.2k 95.3k
PGNDSGND
ONOFF
536
74
9
8
13
14
2
11
10
12
1
SW1
PVIN
VIN
RUN/SS
RT
SW2
PVOUT
VOUT
FB
VC
BURST
LTC3533
10µF
VIN
3V TO 4.2V
388k 2.2k
200µF
220pF
VOUT
3.6V AT 2A
200k
15k 470pF
3533 TA03
6.8µH
64.9k PGNDSGND
ONOFF
FIXED
FREQUENCY
BURST
536
74
9
8
13
14
2
11
10
12
1
LTC3533
15
3533f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev A)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.30 ±0.05
(2 SIDES)
17
148
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE14) DFN 0905 REV A
0.25 ± 0.05
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
0.50 BSC
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 ±0.05
(2 SIDES)2.20 ±0.05
0.50
BSC
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
LTC3533
16
3533f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0207 • PRINTED IN USA
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PART NUMBER DESCRIPTION COMMENTS
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LTC3411 1.25A (IOUT), 4MHz Synchronous Step-Up DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
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ISD ≤ 1µA, TSSOP16E Package
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ISD < 1µA, QFN Package
LTC3425 5A (ISW), 8MHz Multiphase Synchronous Step-Up DC/DC Converter VIN: 0.5V to 4.5V, VOUT(MAX) = 5.25V, IQ = 12µA,
ISD < 1µA, QFN Package
LTC3429 600mA (ISW), 500kHz Synchronous Step-Up DC/DC Converter VIN: 0.5V to 4.4V, VOUT(MAX: 5V, IQ = 20µA,
ISD < 1µA, ThinSOT Package
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ISD < 1µA, MS, DFN Package
LTC3441 1.2A (IOUT), 1MHz Synchronous Buck-Boost DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MAX): 2.4V to 5.5V, IQ = 25µA,
ISD < 1µA, DFN Package
LTC3442/LTC3443 1.2A (IOUT), Synchronous Buck-Boost DC/DC Converters,
LTC3442 (1MHz), LTC3443 (600kHz)
VIN: 2.4V to 5.5V, VOUT(MAX): 2.4V to 5.25V, IQ = 28µA,
ISD < 1µA, DFN Package
LTC3444 500mA (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 5.5V, VOUT = 0.5V to 5V, DFN Package,
Internal Compensation
LTC3530 600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40µA,
ISD < 1µA, 10-Pin MSOP Package, 3mm × 3mm DFN
LTC3532 500mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.5V, IQ = 35µA,
ISD < 1µA, 10-Pin MSOP Package, 3mm × 3mm DFN
Thin SOT is a trademark of Linear Technology Corporation.
