APA2176/2176A 270mW Stereo Cap-Free Headphone Driver Features General Description * * The APA2176/2176A is a stereo, fixed gain, and cap-free headphone driver which is available in a TQFN4x4 20-pin, No Output Capacitor Required Dual Supply Voltage (PVDD>VDD) TQFN3x3 16-pin (APA2176A) or TSSOP-16 package. Dual supply voltage provides higher efficiency and better power - VDD=1.8 ~4.5V * * - PVDD=2.2 ~ 5.5V ripple rejection. The APA2176/2176A is designed with ground-reference Meeting VISTA Requirements output and no need the output capacitors for DC blocking. The advantages of eliminating the output capacitor are Output Power at 1% THD+N -200mW, at VDD=3.3V, PVDD=5.0V, RL=16 saving the cost, PCB's space, and component height. The built-in gain setting can minimize the external com- -55mW, at VDD=1.8V, PVDD=3.0V, RL=16 at 10% THD+N * * * * * ponent counts and save the PCB space. High PSRR provides increased immunity to noise and RF rectification. In -270mW, at VDD=3.3V, PVDD=5.0V, RL=16 -70mW, at VDD=1.8V, PVDD=3.0V, RL=16 addition to these features, a fast start-up time and small package size make the APA2176/2176A an ideal choice Less External Components Required for portable multimedia devices. Moreover, the APA2176/2176A is also equipped other High PSRR: 80dB at 217Hz Fast Start-Up Time : 120s features. For example, at THD+N=1%, it is capable of driving 200mW at V DD=3.3V, PV DD=5.0V into 16. In Short-Circuit and Thermal Protection addition, it provides thermal and short circuit protections. Surface-Mount Package - TQFN4x4-20B (with Enhanced Thermal Pad) - TSSOP-16 - TQFN3x3-16 (with Enhanced Thermal Pad) Applications * * * * (for APA2176A) * Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit R-CH Input PDAs Portable Multimedia Devices Notebooks RIN ROUT L-CH Input Headsets Stereo Headphone LIN APA2176/2176A LOUT Shutdown Control RSD LSD ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 1 www.anpec.com.tw APA2176/2176A Ordering and Marking Information Package Code QB : TQFN4x4-20B O : TSSOP-16 QB : TQFN3x3-16 (APA2176A) Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2176 APA2176A Assembly Material Handling Code Temperature Range Package Code APA2176 QB : APA2176 O: APA2176 XXXXX XXXXX - Date Code APA2176A QB : APA 2176A XXXXX XXXXX - Date Code XXXXX - Date Code APA2176 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). NC 16 10 VDD GND 17 9 LOUT APA2176 Top View LSD 18 7 VSS NC 20 9 ROUT 10 LIN NC 13 GND 14 8 NC PVDD 19 11 RSD 12 RIN 11 ROUT 12 NC 13 LIN 14 RSD 15 RIN Pin Configuration LSD 15 8 VDD APA2176A Top View 7 LOUT 6 VSS 5 CVSS PVDD 16 NC 4 CP- 3 PGND 2 CP+ 1 CVSS 5 NC 4 CP- 3 PGND 2 CP+ 1 6 NC TQFN3x3-16 TQFN4x4-20B =Thermal Pad (connected the Thermal Pad to ground plane for better heat dissipation) NC 1 16 LSD 15 GND PVDD 2 14 RIN NC 3 CP+ 4 PGND 5 APA2176 Top View 13 RSD 12 LIN 11 ROUT CP- 6 10 VDD CVSS 7 9 LOUT VSS 8 TSSOP-16 Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 2 www.anpec.com.tw APA2176/2176A Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Rating Unit Supply Voltage (VDD to GND) -0.3 to 5.5 V Charge Pump Supply Voltage (PVDD to PGND) -0.3 to 5.5 V VPGND_GND PGND to GND Voltage -0.3 to 0.3 V VRSD, VLSD Input Voltage (RSD and LSD to GND) -0.3 to VDD+0.3 V VSS, CVSS VSS and CVSS to GND and PGND Voltage -5.5 to 0.3 V VSS-0.3 to VDD+0.3 V V VDD PVDD VROUT, VLOUT Parameter ROUT and LOUT to GND Voltage VCP+ CP+ to PGND Voltage -0.3 to PVDD+0.3 VCP- CP- to PGND Voltage CVSS-0.3 to 0.3 TJ Maximum Junction Temperature C 150 TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD V C -65 to +150 C 260 Power Dissipation Internally Limited W Notes 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2,3) Symbol Parameter Typical Value Unit Junction-to-Ambient Resistance in Free Air JA JC TQFN3x3-16 TQFN4x4-20B TSSOP16 55 43 100 TQFN3x3-16 TQFN4x4-20B 10 8 o C/W Junction-to-Case Resistance in Free Air o C/W Note 2: Please refer to "Thermal Pad Consideration". 2 layered 5 in2 printed circuit boards with 2oz trace and copper through several thermal vias. The thermal pad is soldered on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFN3x3-16 and TQFN4x4-20B packages. Recommended Operating Conditions (Note 4) Symbol Parameter Range Unit VDD Supply Voltage 1.8 ~ 4.5 V PVDD Charge Pump Power Supply Voltage 2.2 ~ 5.5 V VIH High Level Threshold Voltage RSD, LSD VIL Low Level Threshold Voltage RSD, LSD VICM Common Mode Input Voltage TA TJ Junction Temperature Headphone Resistance 0 ~ 0.3PVDD ~ VDD-1 Ambient Temperature RL 0.6PVDD ~ PVDD V V V -40 ~ 85 o -40 ~ 125 o 14 ~ C C Note 4 : Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 3 www.anpec.com.tw APA2176/2176A Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=3.3V, PVDD=5V, VPGND=VGND=0V, and CCPO=CCPF=2.2F. Typical values are at TA=25oC. Symbol Parameter APA2176/2176A Test Conditions Unit Min. Typ. Max. VDD Supply Current - 2.0 4.0 mA PVDD Supply Current - 3.2 6.5 mA SUPPLY CURRENT IDD IPVDD ISD(VDD) VDD Shutdown Current VRSD = VLSD = 0 - 1.0 5.0 A ISD(PVDD) PVDD Shutdown Current VRSD = VLSD = 0 - 1.0 5.0 A 450 510 570 kHz 6 7 9 CHARGE PUMP fOSC Switching Frequency Req Charge Pump Equivalent Resistance CCPO=CCPF=2.2F POWER-ON-RESET Rising VDD Threshold PVDD=5V 1.67 1.7 1.73 V Falling VDD Threshold PVDD=5V 1.57 1.6 1.63 V Av Internal Voltage Gain No Load -1.55 -1.5 -1.45 V/V AV Gain Match - 1.0 - % 12 14 16 k AMPLIFIERS Ri Input Resistance SR Slew Rate - 2.5 - V/s CL Maximum Capacitive Load - 400 - pF Start-Up Time from Shutdown - 120 - s 200 150 - 125 Tstart-up VDD=3.3V, PVDD=5.0V, TA=25 C THD+N = 1%, fin=1kHz, in Phase RL = 16 RL = 32 PO Output Power mW THD+N = 10%, fin=1kHz, in Phase RL = 16 RL = 32 170 Total Harmonic Distortion Pulse Noise fin = 1kHz PO = 140mW, RL = 16 PO = 105mW, RL = 32 VO = 1.7Vrms, RL = 10k - Channel Separation fin = 1kHz PO = 140mW, RL = 16 VO = 1.7Vrms, RL = 10k - Power Supply Rejection Ratio RL = 16, fin=217Hz Output Offset Voltage S/N Vn THD+N Crosstalk PSRR Vos 270 200 - 0.04 0.03 0.002 - % 78 90 - dB - 90 - dB RL = 32 -5 - 5 mV Signal to Noise Ratio With A-weighting Filter PO = 105mW, RL = 32 - 95 - dB Noise Output Voltage RL = 32 - 15 - V (rms) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 4 www.anpec.com.tw APA2176/2176A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VDD=3.3V, PVDD=5V, VPGND=VGND=0V, and CCPO=CCPF=2.2F. Typical values are at TA=25oC. Symbol Parameter APA2176/2176A Test Conditions Unit Min. Typ. Max. 55 40 - 35 70 55 - 45 VDD=1.8V, PVDD=3.0V, TA=25 C PO THD+N Crosstalk PSRR Output Power Total Harmonic Distortion Pulse Noise Channel Separation THD+N = 1%, fin=1kHz, in Phase RL = 16 RL = 32 THD+N = 10%, fin=1kHz, in Phase RL = 16 RL = 32 fin = 1kHz PO = 40mW, RL = 16 PO = 30mW, RL = 32 VO = 0.9Vrms, RL = 10k fin = 1kHz PO = 40mW, RL = 16 VO = 0.9Vrms, RL = 10k - 0.04 0.03 0.002 mW - % - 78 90 - dB Power Supply Rejection Ratio RL = 16, fin=217Hz - 82 - dB VOS Output Offset Voltage RL = 32 -5 - 5 mV S/N Signal to Noise Ratio With A-weighting Filter PO = 30mW, RL = 32 - 95 - dB Vn Noise Output Voltage RL = 32 - 15 - V (rms) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 5 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=3.3V PVDD=5.0V RL=16 Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 1 VDD=3.3V PVDD=5.0V RL=32 Cin=1F BW<80kHz Stereo, in Phase fin=20kHz 0.1 fin=20kHz 0.1 fin=1kHz fin=1kHz fin=20Hz fin=20Hz 0.01 0.01 0 50 100 150 200 250 300 350 0 Output Power (mW) VDD=3.3V PVDD=5.0V RL=10k Cin=1F BW<80kHz Stereo, in Phase 200 250 VDD=2.8V PVDD=3.6V RL=16 Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 150 THD+N vs. Output Power 10 1 100 Output Power (mW) THD+N vs. Output Voltage 10 50 0.1 fin =20kHz fin=20kHz 0.1 fin=1kHz 0.01 fin=20Hz fin=1kHz fin=20Hz 0.001 0.01 0 1 2 3 4 0 200 VDD=2.8V PVDD=3.6V RL=10k Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 150 10 VDD=2.8V PVDD=3.6V RL=32 Cin=1F BW<80kHz Stereo, in Phase 1 100 THD+N vs. Voltage THD+N vs. Output Power 10 50 Output Power (mW) Output Voltage (Vrms) fin=20kHz 0.1 0.1 fin=20kHz 0.01 fin=1kHz fin=1kHz fin=20Hz fin=20Hz 0.01 0 30 60 90 120 0.001 150m Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 0 1 2 3 Output Voltage (Vrms) Output Power (mW) 6 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=1.8V PVDD=3.0V RL=16 Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 1 VDD=1.8V PVDD=3.0V RL=32 Cin=1F BW<80kHz Stereo, in Phase fin=20kHz 0.1 fin=20kHz 0.1 fin=1kHz fin=1kHz fin=20Hz fin=20Hz 0.01 0 20 40 60 80 0.01 100 0 THD+N vs. Voltage 10 30 40 50 60 VDD=1.8V PVDD=2.4V RL=16 Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 20 THD+N vs. Output Power 10 VDD=1.8V PVDD=3.0V RL=10k Cin=1F BW<80kHz Stereo, in Phase 1 10 Output Power (mW) Output Power (mW) 0.1 fin=20kHz fin=20kHz 0.1 fin=1kHz 0.01 fin=1kHz fin=20Hz fin=20Hz 0.001 0 0.5 1 1.5 0.01 2 0 10 VDD=1.8V PVDD=2.4V RL=32 Cin=1F BW<80kHz Stereo, in Phase 1 THD+N (%) THD+N (%) 60 80 THD+N vs. Voltage THD+N vs. Output Power 1 40 Output Power (mW) Output Voltage (Vrms) 10 20 fin=20kHz 0.1 VDD=1.8V PVDD=2.4V RL=10k Cin=1F BW<80kHz Stereo, in Phase 0.1 fin=20kHz 0.01 fin=1kHz fin=1kHz fin=20Hz fin=20Hz 0.01 0 10 20 30 40 50 0.001 0 60 1 1.5 2 Output Voltage (Vrms) Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 0.5 7 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=3.3V PVDD=5.0V RL=16 PO=140mW Cin=1F BW<22kHz 1 THD+N (%) THD+N (%) 1 VDD=3.3V PVDD=5.0V RL=32 PO=105mW Cin=1F BW<22kHz 0.1 Right channel 0.1 Right channel Left channel Left channel 0.01 0.01 0.006 0.006 20 100 1k 20 10k 20k 100 THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=3.3V PVDD=5.0V RL=10k VO=1.7Vrms Cin=1F BW<22kHz VDD=2.8V PVDD=3.6V RL=16 PO=70mW Cin=1F BW<22kHz 1 THD+N (%) THD+N (%) 10k 20k Frequency (Hz) Frequency (Hz) 1 1k 0.1 0.1 Right channel 0.01 Right channel Left channel 0.001 0.01 Left channel 0.006 0.0006 20 100 1k 20 10k 20k 100 10 10 VDD=2.8V PVDD=3.6V RL=32 PO=60mW Cin=1F BW<22kHz VDD=2.8V PVDD=3.6V RL=10k VO=1.4Vrms Cin=1F BW<22kHz 1 THD+N (%) THD+N (%) 10k 20k THD+N vs. Frequency THD+N vs. Frequency 1 1k Frequency (Hz) Frequency (Hz) 0.1 Right channel 0.1 0.01 Right channel Left channel 0.01 Left channel 0.001 0.006 0.0006 20 100 1k 10k 20k 20 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 100 1k 10k 20k Frequency (Hz) 8 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=1.8V PVDD=3.0V RL=16 PO=40mW Cin=1F BW<22kHz 0.1 1 THD+N (%) THD+N (%) 1 VDD=1.8V PVDD=3.0V RL=32 PO=30mW Cin=1F BW<22kHz Right channel 0.1 Right channel Left channel 0.01 Left channel 0.01 0.001 20 100 1k 0.001 10k 20k 20 100 Frequency (Hz) 10k 20k THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=1.8V PVDD=3.0V RL=10k 1 VO=0.9Vrms Cin=1F BW<22kHz THD+N (%) THD+N (%) 1k Frequency (Hz) 0.1 VDD=1.8V PVDD=2.4V RL=16 1 PO=23mW Cin=1F BW<22kHz 0.1 Right channel Left channel 0.01 0.01 Right channel 0.001 Left channel 0.0006 20 100 1k 0.001 20 10k 20k 100 Frequency (Hz) 10 VDD=1.8V PVDD=2.4V RL=32 PO=23mW Cin=1F BW<22kHz 1 THD+N (%) THD+N (%) 10k 20k THD+N vs. Frequency THD+N vs. Frequency 10 1 1k Frequency (Hz) 0.1 Right channel VDD=1.8V PVDD=2.4V RL=10k VO=0.9Vrms Cin=1F BW<22kHz 0.1 0.01 Left channel 0.01 Right channel Left channel 0.001 20 100 1k 0.0006 20 10k 20k Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 100 1k 10k 20k Frequency (Hz) Frequency (Hz) 9 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency Crosstalk vs. Frequency +0 +0 VDD=3.3V PVDD=5.0V RL=16 PO=140mW Cin=1F -20 Crosstalk (dB) -30 -40 -30 -60 -70 Right to Left -80 Left to Right -90 -40 -50 -60 -70 -80 -100 -110 -110 100 200 500 1k Left to Right -90 -100 50 VDD=3.3V PVDD=5.0V RL=10k VO=1.7Vrms Cin=1F -20 -50 -120 20 T -10 Crosstalk (dB) -10 2k 5k -120 10k 20k Right to Left 20 50 100 Frequency (Hz) VDD=1.8V PVDD=3.0V RL=16 PO=40mW Cin=1F 2k 5k 10k 20k -30 -40 -20 -30 -50 -60 Right to Left -70 -80 Left to Right -90 -40 -50 -60 -70 -80 -100 -110 -110 50 100 200 500 1k Left to Right -90 -100 -120 20 VDD=1.8V PVDD=3.0V RL=10k VO=0.9Vrms Cin=1F -10 Crosstalk (dB) -20 Crosstalk (dB) 1k +0 -10 2k 5k Right to Left -120 10k 20k 20 50 100 Frequency (Hz) 200 500 1k 2k 5k 10k 20k Frequency (Hz) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50 50 20 Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) 500 Crosstalk vs. Frequency Crosstalk vs. Frequency +0 Right channel Left channel 10 VDD=3.3V PVDD=5.0V RL=16 Cin=1F A-Weighting 1 200 Frequency (Hz) 20 100 1k Right channel Left channel 10 VDD=3.3V PVDD=5.0V RL=10k Cin=1F A-Weighting 1 20 10k 20k 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 20 10 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50 10 Left channel VDD=1.8V PVDD=3.0V RL=16 Cin=1F A-Weighting 1 20 100 1k 10k 20k Left channel 10 VDD=1.8V PVDD=3.0V RL=10k Cin=1F A-Weighting 1 20 Right channel 20 100 Frequency (Hz) 1k Frequency Response Frequency Response +4 +220 +4 +200 +3 +220 Gain +180 Phase VDD=3.3V PVDD=5.0V RL=16 Cin=1F +0 10 100 1k 10k Gain (dB) Gain (dB) +2 Phase (deg) Gain +3 +1 +200 +2 +180 Phase VDD=3.3V PVDD=5.0V RL=10k Cin=1F +1 +160 +0 10 +140 200k 100 +4 +220 +4 +200 +3 VDD=1.8V PVDD=3.0V RL=16 Cin=1F 10k Gain (dB) +180 Phase Phase (deg) Gain (dB) +2 1k +140 200k +220 Gain Gain +3 100 10k Frequency Response Frequency Response +0 10 1k +160 Frequency (Hz) Frequency (Hz) +1 10k 20k Frequency (Hz) Phase (deg) Right channel +2 +180 Phase VDD=1.8V PVDD=3.0V RL=10k Cin=1F +1 +160 +0 10 +140 200k 100 1k 10k +160 +140 200k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 +200 Phase (deg) 20 Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) 50 11 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) PSRR vs. Frequency -20 -20 TT T V =3.3V DD PVDD=5.0V RL=16 Cin=1F Vrr=200mVrms -30 -40 -50 -40 -50 -60 Left channel -70 -80 -90 Right channel -60 -80 -100 -110 1k Right channel -90 -110 100 Left channel -70 -100 -120 20 VDD=3.3V PVDD=5.0V RL=10k Cin=1F Vrr=200mVrms -30 PSRR (dB) PSRR (dB) PSRR vs. Frequency -120 20 10k 20k 100 1k Frequency (Hz) Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency -20 T -40 -50 -30 -40 -50 -60 PSRR (dB) PSRR (dB) -20 T VDD=1.8V PVDD=3.0V RL=16 Cin=1F Vrr=200mVrms -30 -70 Left channel -80 -90 T VDD=1.8V PVDD=3.0V RL=10k Cin=1F Vrr=200mVrms -60 -70 Left channel -80 -90 Right channel Right channel -100 -100 -110 -110 -120 20 100 1k -120 20 10k 20k 100 Charge Pump Supply Current vs. Supply Voltage 10k 20k Supply Current vs. Supply Voltage 4.0 3.0 3.0 Supply Current (mA) Supply Current (mA) 1k Frequency (Hz) Frequency (Hz) 2.0 VDD=3.3V IVDD=2.0mA No Load 1.0 0.0 10k 20k 2.0 1.0 PVDD=5.0V IPVDD=3.2mA No Load 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) Charge Pump Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 2.0 12 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) Charge Pump Shutdown Current vs. Supply Voltage Shutdown Current vs. Supply Voltage RSD=LSD=0V VDD=3.3V ISD(VDD)=0.65A No Load 0.8 RSD=LSD=0V PVDD=5.0V ISD(PVDD)=0.58A No Load 1.0 Shutdown Current (A) Shutdown Current (A) 1.2 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 Charge Pump Supply Voltage (Volt) 3.5 4.0 4.5 Power Dissipation vs. Output Power Power Dissipation vs. Output Power 150 250 RL=16 150 RL=32 100 VDD=3.3V PVDD=5.0V THD+N<1% 50 RL=16 125 Power Dissipation (mW) 200 Power Dissipation (mW) 3.0 Supply Voltage (Volt) 100 75 RL=32 50 VDD=2.8V PVDD=3.6V THD+N<1% 25 0 0 0 50 100 150 200 0 250 20 40 60 80 100 120 Output Power (mW) Output Power (mW) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 100 70 Power Dissipation (mW) Power Dissipation (mW) 60 80 RL=16 60 40 RL=32 VDD=1.8V PVDD=3.0V THD+N<1% 20 RL=16 50 40 RL=32 30 20 VDD=1.8V PVDD=2.4V THD+N<1% 10 0 0 0 10 20 30 40 50 0 60 Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 10 20 30 40 Output Power (mW) Output Power (mW) 13 www.anpec.com.tw APA2176/2176A Typical Operating Characteristics (Cont.) Output Power vs. Load Resistance Output Power vs. Load Resistance 150 300 VDD=3.3V PVDD=5.0V fin=1kHz Cin=1F BW<80kHz Stereo, in Phase 200 150 THD+N=10% 100 VDD=2.8V PVDD=3.6V fin=1kHz Cin=1F BW<80kHz Stereo, in Phase 125 Output Power (mW) THD+N=1% 50 100 75 THD+N=10% 50 THD+N=1% 25 0 0 10 100 10 1000 100 Load Resistance () Output Power vs. Load Resistance Output Power vs. Load Resistance 60 100 VDD=1.8V PVDD=3.0V fin=1kHz Cin=1F BW<80kHz Stereo, in Phase 60 40 THD+N=10% THD+N=1% 20 VDD=1.8V PVDD=2.4V fin=1kHz Cin=1F BW<80kHz Stereo, in Phase 50 Output Power (mW) 80 Output Power (mW) 1000 Load Resistance () 40 30 THD+N=10% 20 THD+N=1% 10 0 0 10 100 10 1000 100 Load Resistance () 1000 Load Resistance () Charge Pump Output Resistance vs. Supply Voltage GSM Power Supply Rejection vs.Frequency 10 +0 IPVDD=10mA No Load -50 8 -100 CF=CCO=1F 7 Output Voltage (dBV) Output Resistance () 9 CF=CCO=2.2F 6 5 4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Charge Pump Supply Voltage (Volt) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 -150 +0 Supply Voltage (dBV) Output Power (mW) 250 -50 -100 -150 0 400 800 1.2k 1.6k 2k Frequency (Hz) 14 www.anpec.com.tw APA2176/2176A Operating Waveforms GSM Power Supply Rejection vs. Time Output Transient at Turn on VDD VDD 1 1 PVDD 2 VOUT VOUT 2 3 CH1: VDD, 500mV/Div, DC VDD Offset = 3.3V CH2: VOUT , 20mV/Div, DC CH1: VDD, 2V/Div, DC CH2: PVDD, 2V/Div, DC CH3: VOUT, 20mV/Div, DC TIME: 20ms/Div TIME: 5ms/Div Output Transient at Power off Output Transient at Shutdown Active VDD 1 VRSD 1 PVDD 2 VOUT 2 VOUT 3 CH1: VDD, 2V/Div, DC CH2: PVDD, 2V/Div, DC CH3: VOUT, 20mV/Div, DC CH1: VRSD, 2V/Div, DC CH2: VOUT, 20mV/Div, DC TIME: 20ms/Div TIME: 100ms/Div Output Transient at Shutdown Release Shutdown Release VRSD VRSD 1 1 VOUT T 2 2 CH1: VRSD, 2V/Div, DC CH2: VOUT, 1V/Div, DC TIME: 200s/Div CH1: VRSD, 2V/Div, DC CH2: VOUT, 20mV/Div, DC TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 VOUT 15 www.anpec.com.tw APA2176/2176A Pin Description NAME NO. TQFN3x3-16 (FOR APA2176A) NO. 1 4 1 CP+ 2 5 2 PGND 3 6 3 CP- Charge pump flying capacitor negative connection. 4,6,8,12, 16,20 1,3 4, 13 NC No Connection. 5 7 5 CVSS 7 8 6 VSS 9 9 7 LOUT Left channel output for headphone. 10 10 8 VDD Supply voltage input pin. 11 11 9 ROUT 13 12 10 LIN Left channel audio signal input pin. 14 13 11 RSD Right channel shutdown mode control pin. A low-level voltage applied on this pin shuts off the right channel headphone driver. 15 14 12 RIN Right channel audio signal input pin. 17 15 14 GND Ground connection for circuitry. 18 16 15 LSD Left channel shutdown mode control pin. A low-level voltage applied on this pin shuts off the left channel headphone driver. 19 2 16 PVDD TQFN4x4-20B TSSOP-16 NO. FUNCTION Charge pump flying capacitor positive connection. Charge pump ground. Charge pump output. Connect this pin to CVSS. Right channel output for headphone. Charge pump power supply voltage input pin. Block Diagram RIN ROUT LIN LOUT PVDD GND CP+ RSD LSD Shutdown circuit GND Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 PGND Charge Pump circuit Power and Depop circuit VSS VDD 16 CP- CVSS www.anpec.com.tw APA2176/2176A Typical Application Circuit R-Ch Input CiR 1F CiL 1F L-CH Input RIN RiR 14k RfR 21k RiL 14k RfL 21k Headphone Jack LIN GND Shutdown control ROUT RSD LSD Shutdown circuit GND PGND VDD Charge Pump circuit Power and Depop circuit VDD Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 PVDD PVDD CP+ CCPB 10F CCPF 2.2F CP- VSS Cs 10F LOUT 0.1F VSS CVSS CCPO 2.2F 17 Recommended Supply Voltage VDD PVDD 3.3V 5.0V 2.2V 3.6V 1.8V 3.0V 1.8V 2.4V www.anpec.com.tw APA2176/2176A Function Description VDD age PVDD to provide maximum device performance. By switching the both RSD and LSD pins to low level, the VDD/2 amplifier enters a low-consumption current circumstance, with charge pump disabled, and very small IDD for the GND APA2176/2176A. The charge pump is enabled once either RSD or LSD pin is pulled to high. In normal operating, the VOUT Conventional Headphone amplifier APA2176/2176A's RSD and LSD pins should be pulled to high level to keep the IC out of the shutdown mode. The RSD and LSD pins should be tied to a definite voltage to avoid unwanted mode changing. VDD VOUT GND VSS Cap-free Headphone amplifier Figure 1. Cap-Free Operation The APA2176/2176A is a stereo, fixed gain, cap-free headphone driver. The gain is set by internal resistors, input resistors (R i), and feedback resistors (R f) with -1.5V/V (See Typical Application Circuit). The APA2176/2176A's headphone drivers use a charge pump to invert the positive power supply (PVDD) to negative power supply (CVSS), see figure1. The headphone drivers operate at this bipolar power supply (VDD and VSS) and the outputs reference refers to the ground. This feature eliminates the output capacitors which are used in conventional single-ended headphone amplifiers. Compared with the single power supply amplifiers, the power supply voltage is almost double. Shutdown Function In order to reduce power consumption, the APA2176/2176A contain two shutdown signal input pins (LSD for left channel and RSD for right channel) to allow respective shutdown which turns off the bias current of the amplifier. This shutdown feature turns the amplifier off when logic low is placed on the RSD or LSD pin for the APA2176/ 2176A. The trigger point between a logic high and logic low level is typically 0.6PVDD and 0.3PVDD. It is highly recommended to switch between ground and the supply volt- Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 18 www.anpec.com.tw APA2176/2176A Application Information The value of Ci is important to consider carefully because Charge Pump Flying Capacitor (CCPF) it directly affects the low frequency performance of the circuit. Consider the example where Ri is 14k and the The flying capacitor (CCPF) affects the load transient of the charge pump. If the capacitor's value is too small, and specification that calls for a flat bass response down to 10Hz. The equation is reconfigured as below: then this increases charge pump's output resistance and degrades the performance of headphone amplifier. Ci = Increasing the flying capacitor's value improves the load transient of charge pump. It is recommend to use the low 1 2RifC (2) When the input resistance variation is considered, the Ci is 1F. Therefore, a value in the range of 1F to 2.2F ESR ceramic capacitors (X7R type is recommended) above 2.2F. would be chosen. A further consideration for this capacitor is the leakage path from the input source through the Charge Pump Output Capacitor (CCPO) The charge pump needs an output capacitor(CCPO) to filter the negative output current pulse flowing into CVSS input network (Ri + Rf, Ci) to the load. pin as well as reduces the output voltage ripple(CVSS). The capacitor also sucks in surge current flowing from input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low- the VSS pin, the negative power input pin for the amplifiers. The output ripple is determined by the capacitance, ESR, leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the negative side of and current ripple of the output capacitor. Increasing the value of output capacitor and decreasing the ESR can the capacitor should face the amplifiers' inputs in most applications because the DC level of the amplifiers' in- reduce the voltage ripple. Using a low-ESR ceramic capacitor greater than 2.2F is recommended. For reduc- puts are held at 0V. Please note that it is important to confirm the capacitor polarity in the application. This leakage current creates a DC offset voltage at the ing the parasitic inductance and improving the noise Power Supply Decoupling (Cs) decoupling, place the capacitor near the CVSS and the PGND pins as close as possible. The APA2176/2176A is a high-performance CMOS audio Charge Pump Bypass Capacitor (CCPB) amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) The bypass capacitor(CCPB) connected with PVDD pin supplies the charge pump with surge current as well as re- as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between duces the voltage ripple on PVDD pin. Using a low-ESR ceramic capacitor 10F(typical) is recommended. For the amplifier and the speaker. reducing the parasitic inductance and improving the noise decoupling, place the capacitor near the PVDD and the ent types of capacitor that targets on different types of noise on the power supply leads. For higher frequency PGND pins as close as possible. transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, The optimum decoupling is achieved by using two differ- Input Capacitor (Ci) In the typical application, an input capacitor (Ci) is required typically 0.1F, is placed as close as possible to the device VDD lead for the best performance. For filtering lower to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power input impedance Ri from a high-pass filter with the cutoff frequency are determined in the following equation: amplifier is recommended. Thermal Consideration fC(highpass) = 1 2RiCi Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 Linear power amplifiers dissipate a significant amount of heat in the package in normal operating condition. The (1) 19 www.anpec.com.tw APA2176/2176A Application Information (Cont.) Thermal Consideration (Cont.) first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipation vs. ThermalVia Diameter 0.3mm X 5 0.9mm Output Power graphs are per channel values, therefore, the dissipation of the IC heat needs to be doubled for 0.35mm pation (PD), and the maximum ambient temperature can be calculated with the following equation. The maximum 4.9mm 2.2mm two-channel operation. Given JA, the maximum allowable junction temperature (TJMax), the total internal dissi- 0.5mm recommended junction temperature for the APA2176/ 2176A is 150C. The internal dissipation figures are taken 2.2mm from the Power Dissipation vs. Output Power graphs. The APA2176/2176A is designed with a thermal shutdown Ground Plane for ThermalPAD protection that turns the device off when the junction temperature surpasses 150C to prevent damaging the IC. Figure 2. TQFN4x4-20B Layout Recommendation Layout Consideration 1. All components should be placed close to the APA2176/ Thermal Via Diameter 0.3mm X 5 2176A. For example, the input capacitor (Ci) should be close to APA2176/2176A's input pins to avoid causing 1mm noise coupling to APA2176/2176A's high impedance inputs; the decoupling capacitor (CS) should be placed 0.3mm 2. The output traces should be short, wide (>50mil), and symmetric. 4.0mm 1.55mm by the APA2176/2176A's power pin to decouple the power rail noise. 0.5mm 1.55mm 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. Ground Plane for Thermal PAD 5. The TQFN Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. Figure 3. TQFN3x3-16 Layout Recommendation Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 20 www.anpec.com.tw APA2176/2176A Package Information TQFN4x4-20B D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L A A1 TQFN4x4-20B MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.008 0.012 D 3.90 4.10 0.154 0.161 D2 2.00 2.70 0.079 0.106 0.161 0.106 E 3.90 4.10 0.154 E2 2.00 2.70 0.079 e 0.50 BSC L 0.35 K 0.20 0.020 BSC 0.014 0.45 0.018 0.008 Note : 1. Followed from JEDEC MO-220 VGGD-5. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 21 www.anpec.com.tw APA2176/2176A Package Information TSSOP-16 D e E E1 SEE VIEW A C 0.25 A A2 b GAUGE PLANE A1 SEATING PLANE VIEW A S Y M B O L L TSSOP-16 INCHES MILLIMETERS MIN. MIN. MAX. A MAX. 0.047 1.20 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 4.90 5.10 0.193 0.201 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 0.26 BSC 6.5 BSC e L 0.45 0.75 0.018 0.030 0 0 8 0 8 Note : 1. Follow from JEDEC MO-153 AB. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 22 www.anpec.com.tw APA2176/2176A Package Information TQFN3x3-16 A b E D Pin 1 D2 A1 A3 k E2 Pin 1 Corner e S Y M B O L TQFN3x3-16 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.50 0.020 0.008 Note : Follow JEDEC MO-220 WEED-4. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 23 www.anpec.com.tw APA2176/2176A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN4x4-20B Application TSSOP-16 Application TQFN3x3-16 A H T1 C d D W E1 F 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.75 0.10 5.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0 0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.300.20 4.30 0.20 1.300.20 4.00.10 8.00.10 A H T1 C d D W E1 F 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.75 0.10 5.500.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.00 0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.900.20 5.40 0.20 1.600.20 4.000.10 8.000.10 A H T1 C d D W E1 F 3302.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.75 0.10 5.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0 0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.300.20 3.30 0.20 1.300.20 4.00.10 8.00.10 (mm) Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 24 www.anpec.com.tw APA2176/2176A Devices Per Unit Package Type TQFN4x4-20B TSSOP-16 TQFN3x3-16 Unit Tape & Reel Tape & Reel Tape & Reel Quantity 3000 2500 3000 Taping Direction Information TQFN4x4-20B USER DIRECTION OF FEED TSSOP-16 USER DIRECTION OF FEED TQFN3x3-16 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 25 www.anpec.com.tw APA2176/2176A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 26 www.anpec.com.tw APA2176/2176A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 C Volume mm 350 220 C 2.5 mm 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV, VMM200V 10ms, 1tr100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - May., 2009 27 www.anpec.com.tw