Me PRELIMINARY CY7C1006 72 CYPRESS - Features Functional Description e High speed The CY7C1006 is a high-performance tay = 12 ns CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. The device has an e CMOS for optimum speed/power e Low active power 910 mW automatic power-down feature that re- Low standby power duces power consumption by more than 275 mW 65% when deselected. @ 2.0V data retention (optional) Writing to the device is accomplished by 100 pW taking chip enable (CE) and write enable . (WE) inputs LOW. Data on the four 1/O Automatic power-down when pins (I/O through I/O3) is then written into the location specified on the address 256K x 4 Static RAM Reading from the device is accomplished by taking chip enable (CE) and output en- able (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four 1/O pins. The four input/output pins (I/O through 1/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C1006 is available in standard e TTL-compatible inputs and outputs pins (Ag through Aj7). 300-mil-wide DIPs and SOJs. Logic Block Diagram Pin Configuration DIP/SOJ Top View INPUT BUFFER Ay Ao ie Oz Ag a 2 A, 1 0 = VO. - Ww 512 x512x4 2 Ay z ARRAY 2 | 0, Ag ia a Ag 1/09 COLUMN DECODER CE qgqornwnmnwyt OO) OB Eee dee Oe C1006-~1 Selection Guide 7C1006-12 7C1006-15 71006-20 7C100625 Maximum Access Time (ns) 12 15 20 25 Maximum Operating Current (mA) | Commercial 165 155 145 130 Military 165 150 140 Maximum Standby Current (mA) Commercial 50 30 30 30 Military 40 30 30 Shaded area contains advanced information. | Cypress Semiconductor Corporation 3901 North First Street @ SanJose @ CA 95134 @ 408943-2600 me 2589bb2 0017223 22) November 1991 Revised February 1996PRELIMINARY CY7C1006 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage ......... 0.0 .seeeeen eens >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................5 65C to +150C ~- Latch-Up Current ......... 00... eee seer eee >200 mA Ambient Temperature with * ni Power Applied .............. 0.000000. 55C to +125C Operating Range . 1 Ambient Supply Voltage on Vee Relative to GND] . -0.5V to +7.0V Range Temperaturel2] Vec DC Voltage Applied to Outputs - 5 ; in High Z Stall) oe eee, 0.5V to Vcc + 0.5V Commercial 0C to +70C 5V + 10% DC Input Voltagel .... 2.2... -0.5V to Vcc + 0.5V Military 55C to +125C 5V + 10% Current into Outputs (LOW) ..................065 20 mA Electrical Characteristics Over the Operating Rangel?) 7C1006-12 | 7C1006-15 | 7C1006-20 | 7C1006-25 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vcc = Min., 2.4 2.4 2.4 2.4 Vv Voltage Ion = 4.0mA VoL Output LOW Vcc = Min., Io, = 8.0mA 0.4 0.4 0.4 0.4 Vv Voltage Ving Input HIGH 2.2 | Vcc 2.2 1 Vcc 2.2 | Vcc 2.2 | Vcc Vv Voltage +0.3 + 0.3 + 0.3 +0.3 Vit Input LOW 03 | 08 | -03] 08 | -03] 08 | -03] 0.8 v Voltagel!] Itx InputLoadCurrent | GND < Vy) < Vcc -1 +1 -1 +1 -1 +1 -1 +1 | pA Ioz, Output Leakage GND < Vi < Vcc, 5 +5 5 +5 -5 +5 5 +5 pA Current Output Disabled Ios Output Short Vcc = Max., 300 300 300 300 | mA Circuit Currentl4l | Voyr = GND Icc Voc Operating Vcc = Max. Com! 165 155 140 130 | mA Supply Current Iout = 0 mA, - f = fwax = Itrc | Mil 165 150 140 Ispi Automatic CE Max. Vcc, Com! 50 30 30 30 | mA Power-Down CE > Vin, Current Vin > Ving or - TTL Inputs Vin < Vi Mil 40 30 30 f = fax Isp Automatic CE Max. Vcc, Com! 10 10 10 10 | mA Power-Down CE > Vac 0.3V, Current Vin = Veo -03V (LL 2 2 2 2 CMOS Inputs | or Vin <.0.3V, f=0 | Mil 10 10 10 L 2 2 2 Shaded area contains advanced information. Capacitancel5! Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF Cin: Controls Voc = 5.0V 10 pF Cout Output Capacitance 10 pF Notes: 1. Vir (min.) = 2.0V for pulse durations of less than 20 ns. 2. Ta is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing in- formation. MM 258%bbe OOL7ec4 166 4. Notmore than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.PF CYPRESS PRELIMINARY CY7C1006 AC Test Loads and Waveforms Ri 480 Rt 4802 ALL INPUT PULSES NV Or 5S Ooo 3.0V OUTPUT P OUTPUT P 90% 20% - | $ $ 10% 10% 30 pF , Re 5 pF 3 Re GND i 2550 I 2550 <3ns . <3ns INCLUDING = = INCLUDING = = = <= JIG AND JIG AND SCOPE SCOPE (a) (b) 1006-3 c10064 Equivalent to: THEVENIN EQUIVALENT OUTPUT O\SaO1.78V Switching Characteristics Over the Operating Rangel: 6] 71006-12 71006-15 7C100620 7C100625 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. { Min. | Max. | Unit READ CYCLE trc Read Cycle Time 12 15 20 25 ns tad Address to Data Valid 12 15 20 25 ns toHA Data Hold from Address Change 3 3 3 3 ns taCE CE LOW to Data Valid 12 15 20 25 ns tpor OE LOW to Data Valid 6 7 8 10 ns tLz0E OE LOW to Low Z 0 0 0 0 ns tHzZ0E OE HIGH to High ZI. 8] 6 7 8 10 ns tLzcR CE LOW to Low Z/7] 3 3 3 3 ns tHZCE CE HIGH to High ZI, 8] 6 7 8 10 ns tpu CE LOW to Power-Up 0 0 0 0 ns tpp CE HIGH to Power-Down 12 15 20 25 ns WRITE CYCLE! 1] twc Write Cycle Time 12 15 20 25 ns tscE CE LOW to Write End 10 12 15 20 ns taw Address Set-Up to Write End 10 12 15 20 ns tHa Address Hold from Write End 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 0 ns tpwE WE Pulse Width 10 12 15 20 ns tsp Data Set-Up to Write End 7 8 10 15 ns typ Data Hold from Write End 0 0 ns tLZwE WE HIGH to Low Z/8] 3 3 ns tyzwE WE LOW to High ZI?, 8] 6 7 8 10 ns Shaded area contains advanced information. Notes: 6. Test conditions assume signal transition time of 3 ns or less, timingref- 9. erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified Ip, /Ioy and 30-pF load capacitance. 7. tyzor, tuzcr, and tyzweare specified with aload capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. 10. 8. At any given temperature and voltage condition, tyzcg is less than tizce, tuzok is less than tLzog, and tyzwe is less than thzwe for any given device. Mm 2549bbe O017e225 OT4 The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tyzwe and tgp.PRELIMINARY CY7C1006 CYPRESS Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!) Min, | Max. | Min. | Max. | Unit VpR Vcc for Data Retention 2.0 2.0 Vv IccpR Data Retention Current Vcc = Vor = 2.0V, 50 70 pA 7 ; - CE > Vcc 0.3V, tcprb! Chip Deselect to Data Retention Time Vin > Vee 0.3V or 0 0 ns tp] Operation Recovery Time Vin < 0.3V tre tre ns Data Retention Waveform DATA RETENTION MODE Vi ce 4.5V Vor > 2V J\ 4 tcepR | i, P} C1006-5 Switching Waveforms Read Cycle No. 112, 13] tRC >| ADDRESS >< taa >| jt tona DATA OUT PREVIOUS DATA VALID KxKxX DATA VALID 1006-6 Read Cycle No. 2 (OE Controlled)U3. 14] ADDRESS CE tooe HIGH IMPEDANCE tLz0E HIGH IMPEDANCE DATA OUT DATA VALID tLZCE Voc SUPPLY Ice CURRENT tpu ISB C1006-7 Notes: 11. No input may exceed Voc + 0.5V. 13. WE is HIGH for read cycle. 12. Device is continuously selected, OE and CE = Vj,.. 14. Address valid prior to or coincident with CE transition LOW. we 2589bbe OOl?ecb T30| =a BF CYPRESS PRELIMINARY _ CY7C1006 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[5, 16] two ADDRESS SK *K <<<<$< tsce ce KU tsa > nt taw tua * tewe > FESR LLL <$<<$<$<<$ << ___ tsp ee tup DATA I/O DATA VALID C1006a Write Cycle No. 2 (WE Controlled, OF HIGH During Write)[5: 16] two ADDRESS 4 mm tsce CANN LZ Le ha taw tHa /<$__ tsa tpwe We RS an EY v tsp $r} tp Pt tHZ0E C1006-S Notes: 15. IfCEgoes HIGH simultaneouslywith WE going HIGH, the outputre- 16. Data I/O is high impedance if OE = Vyy. mains in a high-impedance state. Ge c54%bbe 0017227 477=~ PRELIMINARY CY7C1006 S97 Cypress Switching Waveforms Write Cycle No. 3 (WE Controlled, OF LOW)(!6 16] two > ADDRESS x x tsce = SX, LL VA taw tHa tsa >} * tpwe WE N fo WE Qs / tsp tH DATA I/O xx KKK KOK DATA VALID tHzwe e tl zwe >| 1008-10 Truth Table CE | OE | WE | 1/09 1/03 Mode Power H | X |} X | HighZ Power-Down Standby (Isp) L | L | H | Data Out Read Active (Icc) L | X {| L | DatalIn Write Active (Icc) L | H | 4H J HighZ Selected, Outputs Disabled | Active (Icc) 6 Me 256%bbe O017?22eh 803gg CYPRESS PRELIMINARY CY7C1006 Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C100612PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C100612VC V21 28-Lead (300-Mil) Molded SOJ 15 CY7C100615PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-15VC V21 28-Lead (300-Mil) Molded SOJ CY7C1006-15DMB D22 28-Lead (300-Mil) CerDIP Military 20 CY7C100620PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C100620VC V21 28-Lead (300-Mil) Molded SOJ CY7C100620DMB D22 28-Lead (300-Mil) CerDIP Military 25 CY7C100625PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006~25VC V21 28-Lead (300-Mil) Molded SOJ CY7C100625DMB D22 28-Lead (300-Mil) CerDIP Military Shaded area contains advanced information. Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups Vou 1, 2,3 READ CYCLE VoL 1, 2,3 trc 7, 8, 9, 10, 11 Vint 1, 2,3 taa 7, 8,9, 10, 11 Vy Max. 1, 2,3 toHA 7, 8, 9, 10, 11 Ix 1, 2,3 tacg 7, 8,9, 10, 11 loz 1, 2,3 tpoE 7, 8,9, 10, 11 Icc 1, 2,3 WRITE CYCLE Tspi 1, 2,3 twe 7, 8, 9, 10, 11 Isp2 1, 2,3 tscE 7, 8, 9, 10, 11 taw 7, 8,9, 10, 11 tHaA 7, 8, 9, 10, 11 tsa 7, 8,9, 10, 11 tpwe 7, 8, 9, 10, 11 tsp 7, 8, 9, 10, 11 typ 7, 8,9, 10, 11 Me 2589bbe 0017229 74T Document #: 3800201-CBF Cypress Package Diagrams me 2545bbe PRELIMINARY CY7C1006 28-Lead (300-Mil) CerDIP D22 MILSTD1835 D15 Config. A PIN 1 DIMENSIONS IN INCHES CLipifpirift Clipart MIN. T MAX. 45 -310 | _t WILICLILCICICIUU UU _-| 065 005 MIN. 095 BASE PLANE 290 O15, 320 060 aes lf Hf} 150 "206 MIN. 009 } 945 090 oe - (065 110 eh 015 .330 ar SEATING PLANE 35 a o 28-Lead (300-Mil) Molded DIP P21 PIN 1 fy hh of, nannd. i 250 0,270 | DIMENSIONS IN INCHES MIN. MAX. Pere eet L 0.030 0.080 SEATING PLANE 0017230 4blPRELIMINARY CY7C1006 Sa J Cypress Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 PIN 1 IB DIMENSIONS IN INCHES MIN. MAX. 0.697 0.713 t a) Li ais no07 i 0.013 Ye. as puts 0.025 MIN. o595 Me 2585bbe OOL7e31 ATS | G Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Samiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does /t convey or imply any licanse under patent or other rights. Cypress Semicon- ductor does not authorize Its products for use as critical components in life-support systems where a maifunction ar faiture of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cvpress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies