Ultra37000 CPLD Family
5V and 3.3V ISR™ High Performance
CPLDs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-03007 Rev . *F Revised November 23, 2009
Features
■
In-System Reprogrammable™ (ISR™) CMOS CPLDs
❐
JTAG interface for reconfigurability
❐
Design changes do not cause pinout changes
❐
Design changes do not cause timing changes
■
High Density
❐
32 to 512 macrocells
❐
32 to 264 I/O pins
❐
5 dedicated inputs including 4 clock pins
■
Simple Timing Model
❐
No fanout delays
❐
No expander delays
❐
No dedicated vs. I/O pin delays
❐
No additional delay through PIM
❐
No penalty for using full 16 product terms
❐
No delay for steering or sharing product terms
■
3.3V and 5V Versions
■
PCI Compatible
[1]
■
Programmable Bus-hold Capabilities on All I/Os
■
Intelligent Produc t Term Allocator Provides
❐
0 to 16 product terms to any macrocell
❐
Product term steering on an individual basis
❐
Product term sharing among local macrocells
■
Flexible Clocking
❐
4 synchronous clocks per device
❐
Product term clocking
❐
Clock polarity control per logic block
■
Consistent Package and Pinout Offering across All
Densities
❐
Simplifies de si g n mi gration
❐
Same pinout for 3.3V and 5V devices
■
Packages
❐
44 to 256 Pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA
Packages
❐
Pb-free packages available
General Description
The Ultra37000™ family of CMOS CPLDs provides a range of
high density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to bring
the flexibility , ease of use, and performance of the 22V10 to high
density CPLDs. The architecture i s based on a number of l ogic
blocks that are connected by a Programmable Interconnect
Matrix (PIM). Each logic block features its own product term
array, product term allocator, and 16 macrocells. The PIM
distributes signals from the logic block outputs and all input pins
to the logic block inputs.
All the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JT AG-compliant
serial interface. Data is shifted in and out through the TDI and
TDO pins, respectively. Because of the superio r routability and
simple timing model of the Ultra37000 devices, ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JT AG for ISR and boundary scan, and
is compatible with the PCI Local Bus specification, meeti ng the
electrical and timing requirements. The Ultra37000 family
features user programmable bus-hold capabilities on all I/Os.
Ultra37000 5V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. V
CCO
connections provide the
capability of interfacing to either a 5V or 3.3V bus. By connecting
the V
CCO
pins to 5V the user insures 5V TTL levels on the
outputs. If V
CCO
is connected to 3.3V the output levels meet 3.3V
JEDEC standard CMOS levels and are 5V tolerant. These
devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all V
CCO
pins, reducing the device’s power consumption. These devices
support 3.3V JEDEC standard CMOS output levels, and are
5V-tolerant. These devices allow 3.3V ISR programming.
Note
1. Due to the 5V tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
CC
, PCI V
IH
= 2V.
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 2 of 42
Contents
Features ................................................................................1
General Description ............................................................1
Ultra37000 5V Devices ...................................................1
Ultra37000V 3.3V Devices .............................................1
Contents ...............................................................................2
Selection Guide ...................................................................3
5V Selection Guide .........................................................3
3.3V Selection Guide ......................................................3
Architecture Over view of Ultra37000 Family ....................4
Programmable Interconnect Matrix ................................4
Logic Block .....................................................................4
Product Term Allocator ...................................................5
Ultra37000 Macro c ell .....................................................5
Clocking ..........................................................................7
Timing Model ..................................................................7
JTAG and PCI Standards ....................................................8
PCI Compliance ..............................................................8
IEEE 1149.1-compliant JTAG ........................................8
Development Software Support ........................ .................8
Warp ...............................................................................8
Warp Professional™ ......................................................8
Warp Enterprise™ ..........................................................8
Third-Party Software ......................................................8
Programming ..................................................................8
Third-Party Programmers ...............................................9
Logic Block Diagrams ....................... ..................................10
5V Device Maximum Ratings ..............................................13
5V Device Electrical Characteristics ..................................13
Inductance
............................................................................14
Capacitance .........................................................................14
Endurance Characteristics
.................................................14
3.3V Device Maximum Ratings ........................ ... ................14
Operating Range
..................................................................14
3.3V Device Electrical Characteristics ...............................14
Inductance
............................................................................15
Capacitance
..........................................................................15
Endurance Characteristics
.................................................15
AC Characteristics ............ .................... ... ................... ... .....15
Switching Characteristics Over the Operating Range
.......16
Switching Characteristics Over the Operating Range ......18
Switching Waveforms .........................................................19
Power Consumption ............................................................23
Typical 5V Power Consumption .....................................23
Typical 3.3V Power Consumption ............ ... ... ................26
Pin Configurations ......... ... .................... .................... .. ........29
Ordering Information ...........................................................34
5V Ordering Information ....................... ..............................34
3.3V Ordering Information ................. .................... ... ..........35
Addendum ............................................................................35
3.3V Operating Range ....................................................35
Package Diagrams ...............................................................36
Document History Page ........................ ... ................... ... .....39
Sales, Solutions, and Legal Information ...........................42
Worldwide Sales and Design Support ............................42
Products ......................................................................... 42
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 3 of 42
Selection Guide
5V Selection Guide
Table 1. General Information
Device Macrocells De dicated Inputs I/O Pins Speed (t
PD
)Spee d (f
MAX
)
CY37032 32 5 32 6 200
CY37064 64 5 32/64 6 200
CY37128 128 5 64/128 6.5 167
CY37192 192 5 120 7.5 154
CY37256 256 5 128/160/192 7.5 154
Table 2. Speed Bins
Device 200 167 154 125 100 83
CY37032 X X
CY37064 X X X
CY37128 X X X
CY37192 X X
CY37256 X X
Table 3. Device-Package Offering an d I/O Count
Device 44-Pin TQFP 44-Pin PLCC 100-Pin TQFP 160-Pin TQFP
CY37032 37 37
CY37064 37 37 69
CY37128 69 133
CY37192 125
CY37256 133
3.3V Selection Guide
Table 4. General Information
Device Macrocells Dedicate d Inputs I/O Pins Speed (t
PD
)Speed (f
MAX
)
CY37032V 32 5 32 8.5 143
CY37064V 64 5 32/64 8.5 143
CY37128V 128 5 64/80/128 10 125
CY37192V 192 5 120 12 100
CY37256V 256 5 128/160/192 12 100
Table 5. Speed Bins
Device 143 125 100 83 66
CY37032V X X
CY37064V X X
CY37128V X X
CY37192V X X
CY37256V X X
Table 6. Device-Package Offering an d I/O Count
Device 44-Pin TQFP 100-Pin TQFP 160-Pin TQFP 256-Pin FBGA
CY37032V 37
CY37064V 37 69
CY37128V 69 133
CY37192V 125
CY37256V 133 197
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 4 of 42
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The PIM consists of a completely global routing matrix for signals
from I/O pins and feedbacks from the logic blocks. The PIM
provides extremely robust interconnection to avoid fitting and
density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36 inputs
from the PIM and their complements, allowing for 32-b it opera-
tions to be implemented in a single pass through the device. The
wide number of inputs to the logic block also improves the routing
capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The propa-
gation delay through the PIM is accounted for in the timing speci-
fications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing param-
eters on the Ultra37000 devices. The worst-case PIM delays are
incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no han d routing
is necessary. Warp
®
and third-party development packages
automatically route designs for the Ultra37000 family in a matter
of minutes. Finally, the rich routing resources of the Ultra37000
family accommodate last minute logic changes while maintaining
fixed pin assignments.
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator , 16 macrocells, and a number of I/O cells.
The number of I/O cells varies depending on the device used.
Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product term
array . This array accepts 36 inputs from the PIM, which originate
from macrocell feedbacks and device pins. Active LOW and
active HIGH versions of each of these inputs are generated to
create the full 72-input field. The 87 product terms in the array
can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general -p urpose use for the
16 macrocells in the logic block. Four of the remaining seven
product terms in the logi c block are outp ut enable (O E) product
terms. Each of the OE product terms controls up to eight of the
16 macrocells and is selectable on an individual macrocell basis.
In other words, each I/O cell can sel ect betwee n one o f tw o O E
product terms to control the output buffer. The first two of these
four OE product terms are availab le to the upper half of the I/O
macrocells in a logic block. The other two OE product terms are
available to the lower half of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
Figure 1. Logic Block with 50% Bur ie d Macro cells
I/O
CELL
0
PRODUCT
TERM
ALLOCATOR
I/O
CELL
14
MACRO-
CELL
0
MACRO-
CELL
1
MACRO-
CELL
14
0−16
PRODUCT
TERMS
72 x 87
PRODUCT TERM
ARRAY
8036
8
16
TO
PIM
FROM
PIM
7
32
MACRO-
CELL
15
2
to cells
2, 4, 6 8, 10, 12
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 5 of 42
Low Power Option
Each logic block can operate in high speed mode for critical path
performance, or in low power mode for power conservation. The
logic block mode is set by the user on a logic block by logic block
basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are avail able from
the local product term array . The product term allocator provides
two important capabilities without affecting performance: product
term steering and product term shari ng.
Product Term Steering
Product term steering is the process of assigning product terms
to macrocells as needed. For example, if one macrocell requires
ten product terms while another needs just three, the product
term allocator will “steer” ten product terms to one macrocell and
three to the other. On Ultra37000 devices, product terms are
steered on an individual basis. Any number between 0 and 16
product terms can be steered to any macrocell. Note that 0
product terms is useful in cases where a particular macrocell is
unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same prod uct
term among multiple macrocells. For example, if more than one
output has one or more product terms in its equation that are
common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator allows
sharing across groups of four output macrocells in a variable
fashion. The software automatically takes advantage of this
capability—the user does not have to intervene.
Note that neither product term sharing nor product term steering
have any effect on the speed of the product. All worst-case
steering and sharing configurations are incorporated in the
timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells can
either be I/O Macrocells, which include an I/O Cell which is
associated with an I/O pin, or buried Macrocells, which do not
connect to an I/O. The combination of I/O Macrocells and buried
Macrocells varies from device to device.
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.
The register can be asynchronously set or asynchronously reset
at the logic block level with the separate set and reset product
terms. Each of these product terms features programmable
polarity. T his allows the registers to be set or reset based o n an
AND expression or an OR expression.
Clocking of the register is very flexible. Four global synchronous
clocks and a product term clock are available to clock the
register. Furthermore, each clock features programmable
polarity so that registers can be triggered on falling and rising
edges (see Clocking on page 7). Clock polarity is chosen at the
logic block level.
The buried macrocell also supports input register capability. The
buried macrocell can be configured to act as an input register
(D-type or latch) whose input comes from the I/O pin associated
with the neighboring macrocell. Th e output of all buried macro-
cells is sent directly to the PIM regardless of its configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The I/O
macrocell supports the same functions as the buried macrocell
with the addition of I/O capability. At the output of the macrocell,
a polarity control mux is available to select active LOW or active
HIGH signals. This ha s the added a dvantage of allowing signif-
icant logic reduction to occur in many applications.
The Ultra37000 ma crocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated I/O
pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a high
impedance state, thus reducing system noise in bus-interface
applications. Bus-hold additionally allows unused device pins to
remain unconnected on the board, which is particularly useful
during prototyping as designers can route new signals to the
device without cutting trace connections to V
CC
or GND. For
more information, see the application note Understanding
Bus-Hold—A Feature of Cypress CPLDs.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast o r slow. For desig ns concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance
the fast edge rate provides maximum system performance.
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 6 of 42
Figure 2. I/O and Buried Macrocells
Figure 3. Input Macrocell
C2 C3
DECODE
C2 C3
DECODE
0
1
2
3O
C6 C5
“0”
“1”
0
1O
D/T/L Q
R
P
0
1
2
3O
C0
0
1
O
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
BLOCK RESET
0
−
16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1
O
D/T/L Q
R
P
FROM PTM
1O
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
PRODUCT
0
−
16
TERMS
PRODUCT
C1
4
0
1
2
3Q
4
C24
C0C1C24
C25
C25
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
ASYNCHRONOUS
FAST
SLOW
C26
SLEW
0
1
0
1
0
1
0
1
OE0 OE1
0
1
2
3
O
C12 C13
TO PIM
DQ
DQ
DQ
LE
INPUT PIN
0
1
2O
C10
FROM CLOCK
POLARITY MUXES 3
C11
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 7 of 42
Figure 4. Input/Clock Macrocell
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) and an asynchronous
product term clock PTCLK. Each input macrocell has access to
all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of ded icated inputs on
Ultra37000 devices: input pins and input/clock pins. Figure 3
illustrates the architecture for input pins. Four input options are
available for the user: combinatorial, registered, double-regis-
tered, or latched. If a registered or latched option is selected, any
one of the input clocks can be selected for control.
Figure 4 illustrates the architecture for the input/clock pins.
Similar to the input pins, input/clo ck pins can be combinatorial,
registered, double-registered, or latched. In addition, these pins
feed the clocking structures throughout the device. The clock
path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000 family
also has a product term clock for asynchronous clocking. Each
logic block has an independent product term clock which is
available to all 16 macrocells. Each product term clock also
supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and system
performance is unaffected by the features used. Figure 5 illus-
trates the true timing model for the 167-MHz devices in high
speed mode. For combinatorial paths, any input to any output
incurs a 6.5 ns worst-case delay regardless of the amount of
logic used. For synchronous systems, the input setup time to the
output macrocells for any input is 3.5 ns and the clock to output
time is also 4.0 ns. These measurements are for any output and
synchronous clock, regardless of the lo gic used.
The Ultra37000 features:
■
No fanout delays
■
No expander delays
■
No dedicated vs. I/O pin delays
■
No additional delay through PIM
■
No penalty for using 0–16 product terms
■
No added delay for steering product terms
■
No added delay for sharing product terms
■
No routing delays
■
No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penaltie s.
Figure 5. Timing Model for CY37128
0
1
2
3
O
C10C11
TO PIM
DQ
DQ
DQ
LE
INPUT/CLOCK PIN
0
1
2O
FROM CLOCK
CLOCK PINS
0
1O
C12
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO CLOCK MUX
IN EACH
3
0
1
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
POLARITY INPUT
LOGIC BLOCK
C8 C9
C13, C14, C15 OR C16
O
COMBINATORIAL SIGNAL
REGISTERED SIGNAL
D,T,L O
CLOCK
INPUT
INPUT
OUTPUT
OUTPUT
t
S
= 3.5 ns t
CO
= 4.5 ns
t
PD
= 6.5 ns
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 8 of 42
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except for
the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable timing
model ensures compliance with the PCI AC specifications
independent of the design.
IEEE 1149.1-compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in Figure 6.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing or
device pinout. This combination means design changes during
debug or field upgrades do not cause board respins. The
Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones
pre-optimized for the target device, by implementing logic in
unused memory and by perfect communication between fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulatio n and analysis.
Warp Professional™
Warp Professional contains several additional features. It
provides an extra method of design entry with its graphical block
diagram editor. It allows up to 5 ms timing simulation instead of
only 2 ms. It allows comparison of waveforms before and after
design changes.
Warp Enterprise™
Warp Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simulation as well as a debugger. It has the ability to generate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features are
not available in the UNIX version. For further information see the
War p for PC, Warp for UNIX, Warp Professional and Warp
Enterprise data sheets on Cypress’s web site.
Third-Party Software
Although Warp is a complete CPLD development tool on its own,
it interfaces with nearly every third party EDA tool. All major
third-party software vendors provide support for the Ultra37000
family of devices. Refer to the third-party software data sheet or
contact your local sales office for a list of currently supported
third-party vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000 UltraISR
programming cable and software. With this method, the ISR pins
of the Ultra37000 devices are routed to a connector at the edge
of the printed circuit board. The 37000 UltraISR programming
cable is then connected between the parallel port of the PC and
this connector. A simple configuration file instructs the ISR
software of the programming operations to be performed on
each of the Ultra37000 devices in the system. The ISR software
then automatically complete s all of th e necessary data manipu-
lations required to accomplish the programming, reading,
verifying, and other ISR functions. For more information on the
Cypress ISR Interface, see the CYUSBISRPC Programming
Cable User’s Guide.
Figure 6. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCK
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 9 of 42
The second method for pro gramming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through a
file created by the ISR software. Check the Cypress website for
the latest ISR software download information.
The third programming option for Ultra37000 devices is to utilize
the embedded controller or processor that already exi sts in the
system. The Ultra37000 ISR software assists in this method by
converting the device JEDEC maps into the ISR serial stream
that contains the ISR instruction information and the addresses
and data of locations to be programmed. The embedded
controller then simply directs this ISR stream to the chain of
Ultra37000 devices to complete the desired reconfiguring or
diagnostic operations. Contact your local sales office for infor-
mation on availability of this option.
The fourth method for programming Ultra37000 devices is to use
the same programmer that is currently being used to program
F
LASH
370i devices.
For all pinout, electrical, and timing requirements, refer to device
data sheets. For ISR cable and software specifications, refer to
the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available on
a wide variety of third-party programmers. All major third-party
programmers (including BP Micro, Data I/O, and SMS) support
the Ultra37000 family.
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 10 of 42
Logic Block Diagrams
CY37032/CY37032V
LOGIC
BLOCK
B
LOGIC
BLOCK
A
36
16
36
16
Input Clock/
Input
16 I/Os 16 I/Os
I/O
0
−I/O
15
I/O
16
−I/O
31
4
4
4
16
16
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
PIM
JTAG
EN
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 11 of 42
Logic Block Diagrams
(continued)
LOGIC
BLOCK
H
LOGIC
BLOCK
L
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
K
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
G
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
I/O
0
–I/O
9
I/O
10
–I/O
19
I/O
20
–I/O
29
I/O
30
–I/O
39
I/O
40
–I/O
49
I/O
50
–I/O
59
I/O
110
–I/O
119
I/O
100
–I/O
109
I/O
90
–I/O
99
I/O
80
–I/O
89
I/O
70
–I/O
79
I/O
60
–I/O
69
4
4
4
6060
TDI
TCK
TMS TDO
JTA G Tap
Controller
1
CY37192/CY37192V
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 12 of 42
Logic Block Diagrams
(continued)
CY37256/CY37256V
LOGIC
BLOCK
G
LOGIC
BLOCK
H
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
L
LOGIC
BLOCK
P
LOGIC
BLOCK
M
LOGIC
BLOCK
N
LOGIC
BLOCK
O
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
K
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
0
−I/O
11
I/O
12
−I/O
23
I/O
24
−I/O
35
I/O
36
−I/O
47
I/O
48
−I/O
59
I/O
60
−I/O
71
I/O
72
−I/O
83
I/O
84
−I/O
95
I/O
180
−I/O
191
I/O
168
−I/O
179
I/O
156
−I/O
167
I/O
144
−I/O
155
I/O
132
−I/O
143
I/O
120
−I/O
131
I/O
108
−I/O
119
I/O
96
−I/O
107
4
4
4
96
96
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 13 of 42
5V Device Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage .......... ................... ... ............–0.5V to +7.0V
DC Program Voltage................... .................... .. ....4.5 to 5.5V
Current into Outputs....................................................16 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
[2]
Range Ambient Temperature
[2]
Junction Temperature Output Conditi on V
CC
V
CCO
Commercial 0°C to +70°C 0°C to +90°C 5V 5 V ± 0.25V 5V ± 0.25V
3.3V 5V ± 0.25V 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
5V Device Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ Max Unit
V
OH
Output HIGH Voltage V
CC
= Min I
OH
= –3.2 mA (Com’l/Ind)
[4]
2.4 V
I
OH
= –2.0 mA (Mil)
[4]
2.4 V
V
OHZ
Output HIGH V oltage with
Output Disabled
[5]
V
CC
= Max I
OH
= 0 μA (Com’l)
[6]
4.2 V
I
OH
= 0 μA (Ind/Mil)
[6]
4.5 V
I
OH
= –100 μA (Com’l)
[6]
3.6 V
I
OH
= –150 μA (Ind/Mil)
[6]
3.6 V
V
OL
Output LOW Voltage V
CC
= Min I
OL
= 16 mA (Com’l/Ind)
[4]
0.5 V
I
OL
= 12 mA (Mil)
[4]
0.5 V
V
IH
Input HIGH Voltage Guaranteed Input Logical HIGH V oltage for all Inputs
[7]
2.0 V
CCmax
V
V
IL
Input LOW Voltage Guaranteed Input Logical LOW Volt age for all Inputs
[7]
–0.5 0.8 V
I
IX
Input Load Current V
I
= GND OR V
CC
, Bus-Hold Disabled –10 10 μA
I
OZ
Output Leakage Current V
O
= GND or V
CC
, Output Disabled, Bus-Hold Disabled –50 50 μA
I
OS
Output Short Circuit Current
[5, 8]
V
CC
= Max, V
OUT
= 0.5V –30 –160 mA
I
BHL
Input Bus-Hold LOW
Sustaining Current V
CC
= Min, V
IL
= 0.8V +75 μA
I
BHH
Input Bus-Hold HIGH
Sustaining Current V
CC
= Min, V
IH
= 2.0V –75 μA
I
BHLO
Input Bus-Hold LOW
Overdrive Current V
CC
= Max +500 μA
I
BHHO
Input Bus-Hold HIGH
Overdrive Current V
CC
= Max –500 μA
Notes
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000
Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000.
3. T
A
is the “Instant On” case temper ature.
4. I
OH
= –2
mA, I
OL
= 2 mA for TDO.
5. Tested initially and after any design or process changes that may affect these parameters.
6. When the I/O is output disable d, the bus-hold circuit can weakly pu ll the I/O to above 3. 6V if no leakage current is allowed. Note that al l I/Os are output disabled du ring
ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7. These are absolute values with respect to devi ce ground. All overshoots due to system or tester noise are included.
8. Not more than one ou tput should be te sted at a ti me. Duration of t he sh ort circuit sho uld not exceed 1 se cond. V
OUT
= 0.5V is chosen to avoid test problems caused
by tester ground degradation.
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 14 of 42
3.3V Device Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................... ... ......... –65°C to +150°C
Ambient Temperature with
Power Applied ............ ....................... ......... –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage .......... ................... ... ............–0.5V to +7.0V
DC Program Voltage................... .................... .. ....3.0 to 3.6V
Current into Outputs......................................................8 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Inductance
[5]
Parameter Description Test Conditions 44-Pin
TQFP 44-Pin
PLCC 100-Pin
TQFP 160-Pin
TQFP Unit
L Maximum Pin Inductance V
IN
= 5V at f = 1 MHz 2 5 8 9 nH
Capacitance
[5]
Parameter Description Test Cond iti ons Max Unit
C
I/O
Input/Output Capacitance V
IN
= 5V at f = 1 MHz at T
A
= 25°C 10 pF
C
CLK
Clock Signal Capacitance V
IN
= 5V at f = 1 MHz at T
A
= 25°C 12 pF
C
DP
Dual-Function Pins
[9]
V
IN
= 5V at f = 1 MHz at T
A
= 25°C 16 pF
Endurance Characteristics
[5]
Parameter Description Test Conditions Min Typ Unit
NMinimum Reprogramming Cycles Normal Programming Conditions
[2]
1,000 10,000 Cycles
Operating Range
[2]
Range Ambient Temperature
[2]
Junction Temperature V
CC[10]
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 3.3V ± 0.3V
3.3V Device Electrical Characteristics
Over the Operating Range
Parameter Description Test Cond itions Min Max Unit
V
OH
Output HIGH Voltage V
CC
= Min I
OH
= –4 mA (Com’l)
[4]
2.4 V
I
OH
= –3 mA (Mil)
[4]
V
OL
Output LOW Voltage V
CC
= Min I
OL
= 8 mA (Com’l)
[4]
0.5 V
I
OL
= 6 mA (Mil)
[4]
V
IH
Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for
all Inputs
[7]
2.0 5.5 V
V
IL
Input LOW Voltage Guaranteed Input Logical LOW Voltage for all
Inputs
[7]
–0.5 0.8 V
I
IX
Input Load Current V
I
= GND OR V
CC
, Bus-Hold Disabled –10 10 μA
I
OZ
Output Leakage Current V
O
= GND or V
CC
, Output Disabled,
Bus-Hold Disabled –50 50 μA
I
OS
Output Short Circuit Current
[5, 8]
V
CC
= Max, V
OUT
= 0.5V –30 –160 mA
I
BHL
Input Bus-Hold LOW Sustaining Curren t V
CC
= Min, V
IL
= 0.8V +75 μA
I
BHH
Input Bus-Hold HIGH Sustaining Curre nt V
CC
= Min, V
IH
= 2.0V –75 μA
I
BHLO
Input Bus-Hold LOW O ve r drive Current V
CC
= Max +500 μA
I
BHHO
Input Bus-Hold HIGH Ov erdrive Current V
CC
= Max –500 μA
Notes
9. Dual pins are I/O with JTAG pins.
10.For CY37064VP100-143AXC, CY37064VP44-143AXC; Operating Range: V
CC
is 3.3V± 0.16V.
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 15 of 42
Inductance
[5]
Parameter Description Test Conditions 44- Pin
TQFP 44- Pin
PLCC 100- Pin
TQFP 160-Pin
TQFP Unit
L Maximum Pin Inductance V
IN
= 3.3V
at f = 1 MHz 258 9nH
Capacitance
[5]
Parameter Description Test Conditions Max Unit
C
I/O
Input/Output Capacitance V
IN
= 3.3V at f = 1 MHz at T
A
= 25°C 8pF
C
CLK
Clock Signal Capacitance V
IN
= 3.3V at f = 1 MHz at T
A
= 25°C 12 pF
C
DP
Dual Functional Pins
[9]
V
IN
= 3.3V at f = 1 MHz at T
A
= 25°C 16 pF
Endurance Characteristics
[5]
Parameter Description Test Conditions Min Typ Unit
NMinimum Reprogramming Cycles Normal Programming Conditions
[2]
1,000 10,000 Cycles
AC Characteristics
Figure 7. 5V AC Test Loads and Waveforms
Figure 8. 3.3V AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2 ns
OUTPUT
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL)
99Ω(COM'L)
136Ω(MIL)
Equivalent to: THÉVENIN EQUIVALENT
2.08V (COM'L)
2.13V (MIL)
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL) <2 ns
(c)
5 OR 35 pF
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2 ns
OUTPUT
295Ω(COM'L)
393Ω(MIL)
340Ω(COM'L)
453Ω(MIL)
Equivalent to: THÉVENIN EQUIVALENT
1.77V (COM'L)
1.77V (MIL)
295Ω(COM'L)
393Ω(MIL)
340Ω(COM'L)
453Ω(MIL) <2 ns
(c)
270Ω(MIL)
158Ω(COM’L)
5 OR 35 pF
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 16 of 42
Parameter
[11]
V
X
Output Waveform—Measurement Level
t
ER(–)
1.5V
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
VOH VX
0.5V
VOL VX
0.5V
VXVOH
0.5V
VXVOL
0.5V
Switching Characteristics
Over the Operating Range
[12]
Parameter Description Unit
Combinatorial Mode Parameters
t
PD[13, 14, 15]
Input to Combinatorial Output ns
t
PDL[13, 14, 15]
Input to Output Through Transparent Input or Outp ut Latch ns
t
PDLL[13, 14, 15]
Input to Output Through Transparent Input and Output Latches ns
t
EA[13, 14, 15]
Input to Output Enable ns
t
ER[11, 13]
Input to Output Disable ns
Input Register Parameters
t
WL
Clock or Latch Ena ble Input LOW Time
[8]
ns
t
WH
Clock or Latch Enable Input HIGH Time
[8]
ns
t
IS
Input Register or Latch Set-up Time ns
t
IH
Input Register or Latch Hold T i me ns
t
ICO[13, 14, 15]
Input Register Clock or Latch Enable to Combinatorial Outpu t ns
t
ICOL[13, 14, 15]
Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
Synchronous Clocking Parameters
t
CO[14, 15]
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output ns
t
S[13]
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable ns
t
H
Register or Latch Data Hold Time ns
t
CO2[13, 14, 15]
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array) ns
t
SCS[13]
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array) ns
t
SL[13]
Set-Up Time from Input Through T ransp arent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable ns
t
HL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable ns
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 17 of 42
Product Term Clocking Parameters
t
COPT[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output ns
t
SPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns
t
HPT
Register or Latch Data Hold Time ns
t
ISPT[13]
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK) ns
t
IHPT
Buried Register Used as an Input Register or Latch Data Hold Time ns
t
CO2PT[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns
Pipelined Mode Par amete rs
t
ICS[13]
Input Register Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) to Output Register Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
)ns
Operating Frequency Parameters
f
MAX1
Maximum Frequency with Internal Feedback (Lesser of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[5]
MHz
f
MAX2
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
),
1/(t
S
+t
H
), or 1/t
CO
)
[5]
MHz
f
MAX3
Maximum Frequency with External Feedback (Lesser of 1/(t
CO
+ t
S
) or 1/(t
WL
+ t
WH
)
[5]
MHz
f
MAX4
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
), 1/(t
IS
+ t
IH
),
or 1/t
SCS
)
[5]
MHz
Reset/Preset Parameters
t
RW
Asynchronous Reset Width
[5]
ns
t
RR[13]
Asynchronous Reset Recovery Time
[5]
ns
t
RO[13, 14, 15]
Asynchronous Reset to Output ns
t
PW
Asynchronous Preset Width
[5]
ns
t
PR[13]
Asynchronous Preset Recovery Time
[5]
ns
t
PO[13, 14, 15]
Asynchronous Preset to Output ns
User Option Parameters
t
LP
Low Power Adder ns
t
SLEW
Slow Output Slew Rate Adder ns
t
3.3IO
3.3V I/O Mode Timing Adder
[5]
ns
JTAG T iming Parameters
t
S JTAG
Set-up Time from TDI and TMS to TCK
[5]
ns
t
H JTAG
Hold Time on TDI and TMS
[5]
ns
t
CO
JTAG
Falling Edge of TCK to TDO
[5]
ns
f
JTAG
Maximum JTAG Tap Controller Freq uency
[5]
ns
Switching Characteristics
Over the Operating Range (continued)
[12]
Parameter Description Unit
Notes
11. t
ER
measured with 5 pF AC Test Load and t
EA
measured with 35 pF AC Test Load.
12.All AC parameters are measured with two outputs switching and 35 pF AC Test Load.
13.Logic blocks operating in low power mode, add t
LP
to this specification.
14.Outputs using Slow Output Slew Rate, add t
SLEW
to this specification.
15.When V
CCO
= 3.3V, add t
3.3IO
to this specification.
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 18 of 42
Switching Characteristics
Over the Operating Range
[12]
Parameter 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Mode Parameters
t
PD[13, 14, 15]
6 6.5 7.5 8.5 10 12 15 20 ns
t
PDL[13, 14, 15]
11 12.5 14.5 16 16.5 17 19 22 ns
t
PDLL[13, 14, 15]
12 13.5 15.5 17 17.5 18 20 24 ns
t
EA[13, 14, 15]
8 8.5 11 13 14 16 19 24 ns
t
ER[11, 13]
8 8.5 11 13 14 16 19 24 ns
Input Register Parameters
t
WL
2.5 2.5 2.5 2.5 3 3 4 5 ns
t
WH
2.5 2.5 2.5 2.5 3 3 4 5 ns
t
IS
2222 2 2.5 3 4ns
t
IH
2222 2 2.5 3 4ns
t
ICO[13, 14, 15]
11 11 11 12.5 12.5 16 19 24 ns
t
ICOL[13, 14, 15]
12 12 12 14 16 18 21 26 ns
Synchronous Clocking Parameters
t
CO [14, 15]
4 4 4.5 6 6.5
[16]
6.5
[17]
8
[18]
10 ns
t
S[13]
44555.5
[16]
6
[17]
8
[18]
10 ns
t
H
0000 0 0 0 0ns
t
CO2[13, 14, 15]
9.5 10 11 12 14 16 19 24 ns
t
SCS[13]
566.57 8
[16]
10 12 15 ns
t
SL[13]
7.5 7.5 8.5 9 10 12 15 15 ns
t
HL
0000 0 0 0 0ns
Product Term Clocking Parameters
t
COPT[13, 14, 15]
7101013 13 13 1520ns
t
SPT
2.5 2.5 2.5 3 5 5.5 6 7 ns
t
HPT
2.5 2.5 2.5 3 5 5.5 6 7 ns
t
ISPT[13]
00000000ns
t
IHPT
6 6.5 6.5 7.5 9 11 14 19 ns
t
CO2PT[13, 14,
15]
12 14 15 19 19 21 24 30 ns
Pipelined Mode Parameters
t
ICS[13]
56678
[16]
10 12 15 ns
Operating Frequency Parameters
f
MAX1
200 167 154 143 125
[16]
100 83 66 MHz
f
MAX2
200 200 200 167 154 153
[17]
125
[18]
100 MHz
f
MAX3
125 125 105 91 83 80
[17]
62.5 50 MHz
f
MAX4
167 167 154 125 118 100 83 66 MHz
Reset/Preset Parameters
t
RW
88 8 8 10 12 15 20 ns
t
RR[13]
10 10 10 10 12 14 17 22 ns
Notes
16.For reference only, the following values correspond to the obsolete CY3751 2 devices: t
CO
= 5 ns, t
S
= 6.5 ns, t
SCS
= 8.5 ns, t
ICS
= 8.5 ns, f
MAX1
= 118 MHz.
17.The following values correspond to the CY37192V and CY37256 V devices: t
CO
= 6 ns, t
S
= 7 ns, f
MAX2
= 143 MHz, f
MAX3
= 77 MHz, and f
MAX4
= 100 MHz; and
for the CY37512 devices: t
S
= 7 ns.
18.For reference only, the following values correspond to the obsolete CY37512V devices: t
CO
= 6.5 ns, t
S
= 9.5 ns, and f
MAX2
= 105 MHz.
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 19 of 42
t
RO[13, 14, 15]
12 13 13 14 15 18 21 26 ns
t
PW
88 8 8 10 12 15 20 ns
t
PR[13]
10 10 10 10 12 14 17 22 ns
t
PO[13, 14, 15]
12 13 13 14 15 18 21 26 ns
User Option Parameters
t
LP
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
t
SLEW
3333 3 3 33ns
t
3.3IO[19]
0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns
JTAG Timing Parameters
t
S JTAG
00000000ns
t
H JTAG
20 20 20 20 20 20 20 20 ns
t
CO JTAG
20 20 20 20 20 20 20 20 ns
f
JTAG
20 20 20 20 20 20 20 20 MHz
Switching Characteristics
Over the Operating Range (continued)
[12]
Parameter 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Switching Waveforms
Figure 9. Combi natorial Output
Figure 10. Registered Output with Syn ch ronous Clocking
Note
19.Only applicable to the 5V devices.
t
PD
INPUT
COMBINATORIAL
OUTPUT
t
S
INPUT
SYNCHRONOUS
t
CO
REGISTERED
OUTPUT
t
H
SYNCHRONOUS
t
WL
t
WH
t
CO2
REGISTERED
OUTPUT
CLOCK
CLOCK
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 20 of 42
Figure 11. Registered Output with Product Term Clocking Input Going Through the Array
Figure 12. Registered Output with Produ ct Term Clocking Input Coming From Adjacent Buried Register
Figure 13. Latched Output
Switching Waveforms
(continued)
t
SPT
INPUT
PRODUCT TERM
t
COPT
REGISTERED
OUTPUT
t
HPT
CLOCK
t
ISPT
INPUT
PRODUCT TERM
t
CO2PT
REGISTERED
OUTPUT
t
IHPT
CLOCK
t
SL
INPUT
LATCH ENABLE
t
CO
LATCHED
OUTPUT
t
HL
t
PDL
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 21 of 42
Figure 14. Regist e r ed I np ut
Figure 15. Clock to Clock
Figure 16. Latched Input
Switching Waveforms
(continued)
t
IS
REGISTERED
INPUT
INPUT REGISTER
CLOCK
t
ICO
COMBINATORIAL
OUTPUT
t
IH
CLOCK
t
WL
t
WH
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
t
SCS
t
ICS
t
IS
LATCHED INPUT
LATCH ENABLE
t
ICO
COMBINATORIAL
OUTPUT
t
IH
t
PDL
t
WL
t
WH
LATCH ENABLE
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 22 of 42
Figure 17. Latched Input and Output
Figure 18. Asynchro nous Reset
Switching Waveforms
(continued)
t
ICS
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
t
PDLL
LATCH ENABLE
t
WL
t
WH
t
ICOL
INPUT LATCH
ENABLE
t
SL
t
HL
INPUT
t
RO
REGISTERED
OUTPUT
CLOCK
t
RR
t
RW
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 23 of 42
Power Consumption
Figure 19. Asynchronous Preset
Figure 20. Output Enable/Disab le
Switching Waveforms
(continued)
INPUT
t
PO
REGISTERED
OUTPUT
CLOCK
t
PR
t
PW
INPUT
t
ER
OUTPUTS
t
EA
Typical 5V Power Consumption
CY37032
0
10
20
30
40
50
60
0 50 100 150 200 250
Frequency (M H z)
Icc (mA)
High Speed
Low P ower
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 24 of 42
CY37064
CY37128
Typical 5V Power Consumption (continued)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
0
10
20
30
40
50
60
70
80
90
0 20 40 60 80 100 120 140 160 180
Frequency (MH z)
Icc (mA)
Low Power
High Speed
0
20
40
60
80
100
120
140
160
0 20 40 60 80 100 120 140 160 180
Frequency (M Hz)
Icc (mA)
Low P ower
High S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 25 of 42
CY37192
CY37256
Typical 5V Power Consumption (continued)
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140 160 180
Frequency (M Hz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140 160 180
Frequency (M Hz)
Icc (mA)
Low P ower
High S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 26 of 42
Typical 3.3V Power Consumption
CY37032V
CY37064V
0
5
10
15
20
25
30
0 20 40 60 80 100 120 140 160
Frequency (MH z)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
0
5
10
15
20
25
30
35
40
45
0 20 40 60 80 100 120 140
Frequency (M Hz)
Icc (mA)
Low Pow er
High Speed
The typical pattern is a 16-bit up counter, per logic block, with output s disabled.
V
CC
= 3.3V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 27 of 42
CY37128V
CY37192V
Typical 3.3V Power Consumption (continued)
0
10
20
30
40
50
60
70
80
0 20 40 60 80 100 120 140
Frequency (M Hz)
Icc (mA)
Low P ower
H igh Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
0
20
40
60
80
100
120
0 20 40 60 80 100 120
Frequency (M Hz)
Icc (mA)
Low P ower
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 28 of 42
CY37256V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120
Frequency (M Hz)
Icc (mA)
Low P ower
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 29 of 42
Pin Configurations
[20]
Notes
20.For 3.3V versions (Ultra37000V), V
CCO
= V
CC
.
21.This pin is a N/C, but Cypress recommends that you connect it to V
CC
to ensure future compatibility
44-Pin TQFP (A44)
Top View
I/O2
GND
V
CCO
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O27/TDI
I/O26
I/O25
I/O24
CLK
1
/I4
GND
I3
CLK
3
/I
2
I/O23
I/O22
I/O21
GND
I/O20
V
CC
I/O18
I/O17
I/O16
I/O15
I/O14
I/O12
I/O5/TCK
I/O6
I/O7
CLK
2
/I
0
GND
CLK
0
/I1
I/O8
I/O9
I/O10
I/O11
8
9
7
10
11
3
4
2
5
6
1
18 19 20 222113 14 15 171612
31
30
29
32
33
26
25
24
27
28
23
44 43 42 4041 39 38 37 3536 34
I/O13/TMS
I/O19 /TDO
JTAG
EN
44-Pin PLCC (J67)
Top View
I/O27/TDI
I/O26
I/O25
I/O24
CLK
1
/I4
GND
I3
CLK
3
/I
2
I/O23
I/O22
I/O21
I/O5/TCK
I/O6
I/O7
CLK
2
/I
0
JTAG
EN
GND
CLK
0
/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
V
CCO
V
CC
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
65 34 2
8
9
7
10
11
44
18
15
16
14
13
12
17 19 20 2221 23 24 2726 2825
31
30
29
32
33
34
39
37
38
36
35
43 42 4041
/TMS
/TDO
1
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 30 of 42
Pin Configurations
[20]
(continued)
Top View
100-Pin TQFP (A100)
100 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84 TDI
NC
V
CCO
I/O
55
I/O
54
I/O
53
I/O
52
CLK
3
/I
4
I/O
50
I/O
48
GND
NC
I
/
O
47
I/O
46
I/O
49
GND
TMS
TCK
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
15
V
CCO
GND
CLK
1
/I
1
I/O
16
I/O
17
CLK
0
/I
0
9091
I/O
51
V
CCO
CLK
2
/I
3
I/O
14
N/C
I/O
12
I/O
13
I/O
45
I/O
44
I/O
43
I/O
42
I/O
41
I/O
40
GND
NC
GND
NC
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
V
CCO
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 48 49 50
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
V
CCO
V
CC
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I2
NC
V
CCO
TDO
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
2
1
V
CCO
I/O 0
V
CC
NC
63
I/O 62
61
60
59
58
57
56
V
CCO
N/C
99
37 47
[21 ]
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 31 of 42
Pin Configurations
[20]
(continued)
I/O
77
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
160-Pin TQFP (A160)
125
84
83
42
GND
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
/TCK
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
GND
CLK
0
/I
0
V
CCO
GND
CLK
1
/I
1
GND
GND
GND
GND
GND
V
CCO
I/O
48
I/O
49
I/O
50
I/O
51
I/O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I
2
V
CCO
V
CC
I/O
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
I/O
74
I/O
75
I/O
78
I/O
79
V
CCO
GND
I/O
80
I/O
81
I/O
82
I/O
83
I/O
84
I/O
85
I/O
86
I/O
87
GND
I/O
88
I/O
89
I/O
90
I/O
91
I/O
92
I/O
93
I/O
94
I/O
95
I/O
96
I/O
97
I/O
98
I/O
99
I/O
100
I/O
101
I/O
102
I/O
103
GND
GND
CLK
2
/I
3
V
CCO
CLK
3
/I
4
I/O
104
I/O
105
I/O
106
I/O
107
I/O
108
/TDI
I/O
109
I/O
110
I/O
111
V
CCO
GND
GND
V
CC
GND
I/O
112
GND
V
CCO
V
CCO
I/O
113
I/O
114
I/O
115
I/O
116
I/O
117
I/O
118
I/O
119
I/O
120
I/O
121
I/O
122
I/O
123
I/O
124
I/O
125
I/O
126
I/O
127
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
JTAG
EN
I/O
52
/TMS
I/O
76
/TDO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
41
for CY37128(V) and CY37256(V)
Top View
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 32 of 42
Pin Configurations
[20]
(continued)
I/O
72
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
160-Pin TQFP (A160) for CY37192(V)
125
84
83
42
GND
NC
I/O
16
I/O
17
I/O
18
TCK
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
GND
CLK
0
/I
0
V
CCO
GND
CLK
1
/I
1
GND
GND
GND
GND
GND
V
CCO
NC
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I
2
V
CCO
V
CC
I/O
60
I/O
61
I/O
62
I/O
63
I/O
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
73
I/O
74
V
CCO
GND
NC
I/O
75
I/O
76
I/O
77
I/O
78
I/O
79
I/O
80
I/O
81
GND
I/O
82
I/O
83
I/O
84
I/O
85
I/O
86
I/O
87
I/O
88
I/O
89
I/O
90
I/O
91
I/O
92
I/O
93
I/O
94
I/O
95
I/O
96
I/O
97
GND
GND
CLK
2
/I
3
V
CCO
CLK
3
/I
4
I/O
98
I/O
99
I/O
100
I/O
101
TDI
I/O
102
I/O
103
I/O
104
V
CCO
GND
GND
V
CC
GND
NC
GND
V
CCO
V
CCO
I/O
105
I/O
106
I/O
107
I/O
108
I/O
109
I/O
110
I/O
111
I/O
112
I/O
113
I/O
114
I/O
115
I/O
116
I/O
117
I/O
118
I/O
119
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
NC
TMS
TDO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
41
Top View
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 33 of 42
Pin Configurations
[20]
(continued)
256-Ball Fine-Pitch BGA (BB256)
Top Vie w
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A GND GND I/O
26
I/O
24
I/O
20
V
CC
I/O
11
GND GND I/O
186
V
CC
I/O
177
I/O
172
I/O
167
GND GND
B GND I/O
27
I/O
25
I/O
23
I/O
19
I/O
15
I/O
10
GND GND I/O
185
I/O
181
I/O
176
I/O
171
I/O
166
I/O
165
GND
CI/O
29
I/O
28
NC I/O
22
I/O
18
I/O
14
I/O
9
I/O
4
I/O
191
I/O
184
I/O
180
I/O
175
I/O
170
NC I/O
163
I/O
164
DI/O
32
I/O
31
I/O
30
NC I/O
17
I/O
13
I/O
8
I/O
3
I/O
190
I/O
183
I/O
179
I/O
174
I/O
169
I/O
160
I/O
161
I/O
162
EI/O
35
I/O
34
I/O
33
I/O
21
I/O
16
I/O
12
I/O
7
I/O
2
I/O
189
V
CC
I/O
178
I/O
173
I/O
168
I/O
157
I/O
158
I/O
159
FV
CC
I/O
38
I/O
37
I/O
36
TCK V
CC
I/O
6
I/O
1
I/O
188
I/O
182
V
CC
TDI I/O
154
I/O
155
I/O
156
V
CC
GI/O
43
I/O
42
I/O
41
I/O
40
V
CC
I/O
39
I/O
5
I/O
0
I/O
187
I/O
148
I/O
149
CLK
3
/I
4
I/O
150
I/O
151
I/O
152
I/O
153
H GND GND I/O
47
I/O
46
CLK
0
/I
0
I/O
45
I/O
44
GND GND I/O
144
I/O
145
CLK
2
/I
3
I/O
146
I/O
147
GND GND
J GND GND I/O
51
I/O
50
NC I/O
49
I/O
48
GND GND I/O
140
I/O
141
I
2
I/O
142
I/O
143
GND GND
KI/O
57
I/O
56
I/O
55
I/O
54
CLK
1
/I
1
I/O
53
I/O
52
I/O
91
I/O
96
I/O
101
I/O
135
V
CC
I/O
136
I/O
137
I/O
138
I/O
139
LV
CC
I/O
60
I/O
59
I/O
58
TMS V
CC
I/O
86
I/O
92
I/O
97
I/O
102
V
CC
TDO I/O
132
I/O
133
I/O
134
V
CC
MI/O
63
I/O
62
I/O
61
I/O
72
I/O
77
I/O
82
V
CC
I/O
93
I/O
98
I/O
103
I/O
108
I/O
112
I/O
117
I/O
129
I/O
130
I/O
131
NI/O
66
I/O
65
I/O
64
I/O
73
I/O
78
I/O
83
I/O
87
I/O
94
I/O
99
I/O
104
I/O
109
I/O
113
NC I/O
126
I/O
127
I/O
128
PI/O
68
I/O
67
NC I/O
74
I/O79 I/O
84
I/O
88
I/O
95
I/O
100
I/O
105
I/O
110
I/O
114
I/O
118
NC I/O
124
I/O
125
R GND I/O
69
I/O
70
I/O
75
I/O
80
I/O
85
I/O
89
GND GND I/O
106
I/O
111
I/O
115
I/O
119
I/O
121
I/O
123
GND
T GND GND I/O
71
I/O
76
I/O
81
V
CC
I/O
90
GND GND I/O
107
V
CC
I/O
116
I/O
120
I/O
122
GND GND
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 34 of 42
Ordering Information
5V Ordering Information
Macrocells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
32 154 CY37032P44-154AXI A44 44-Pin Pb-free Thin Quad Flat Pack Industrial
125 CY37032P44-125AXC A44 44-Pin Pb-free Thin Quad Flat Pack Commercial
CY37032P44-125JXC J67 44-Pin Pb-free Plastic Leaded Chip Carrier
64 200 CY37064P100-200AXC A100 100-Pin Pb-free Thin Quad Fl at Pack Commercial
154 CY37064P44-154AXI A44 44-Pin Pb-free Thin Quad Flat Pack Industrial
CY37064P44-154JXI J67 44-Pin Pb-free Plastic Leaded Chip Carrier
125 CY37064P44-125AXC A44 44-Pin Pb-free Thin Quad Flat Pack Commercial
CY37064P44-125JXC J67 44-Pin Pb-free Plastic Leaded Chip Carrier
CY37064P100-125AXC A100 100-Pin Pb-free Thin Quad Fl at Pack
CY37064P44-125AXI A44 44-Pin Pb-free Thin Quad Flat Pack Industrial
CY37064P100-125AXI A100 100-Pin Pb-free Thin Quad Fl at Pack
128 167 CY37128P160-167AXC A160 160-Pin Pb-free Thin Quad Flat Pack Commercial
125 CY37128P100-125AXC A100 100-Pin Pb-free Thin Quad Fl at Pack Commercial
CY37128P160-125AXC A160 160-Pin Pb-free Thin Quad Fl at Pack
CY37128P100-125AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial
CY37128P160-125AXI A160 160-Pin Pb-free Thin Quad Flat Pack
100 CY37128P100-100AXC A100 100-Pin Pb-free Thin Quad Fl at Pack Commercial
CY37128P160-100AXC A160 160-Pin Pb-free Thin Quad Fl at Pack
192 125 CY37192P160-125AXC A160 160-Pin Pb-free Thin Quad Flat Pack Commercial
CY37192P160-125AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
83 CY37192P160-83AXC A160 160-Pin Pb-free Thin Qu ad Fl at Pack Commercial
CY37192P160-83AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
C Y 3 7 256 V P 160 - 10 0 A X C
Cypress Semiconductor ID
Family Type
37 = Ultra37000 Family
Ma c r o c ell D e nsity
32 = 32 Macrocells 192 = 192 M acrocells
64 = 64 Macrocells 256 = 256 M acrocells
128 = 128 Macrocells
Speed
200 = 200 MHz 167 = 167 MHz
154 = 154 M H z 143 = 143 MHz
125 = 125 M H z 100 = 100 MHz
83 = 8 3 MH z 66 = 6 6 MH z
Package Ty p e
A = Thin Quad Flat Pack (T QFP )
J = Plastic Leaded Chip Carrier (PLC C)
BB = Fine-Pitch Ball Grid Array (FBGA)
1.0 mm Lead Pitch
Operating Conditions
Commercial 0°C to +70°C
Indu stria l -4 0°C to +85 ° C
Operating R eferen c e V o ltage
V = 3.3V Supply Voltage
(5.0 V if n o t s pecif ie d)
Pin Count
P44 = 44 Pins
P100 = 100 P ins
P160 = 160 P ins
P256 = 256 P ins
Lead Free
XLead Free
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 35 of 42
Addendum
3.3V Operating Range
CY37064VP100-143AXC, CY37064VP44-143AXC
256 125 CY37256P160-125AXC A160 160-Pin Pb-free Thin Quad Flat Pack Commercial
CY37256P160-125AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
83 CY37256P160-83AXC A160 160-Pin Pb-free Thin Qu ad Fl at Pack Commercial
CY37256P160-83AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
5V Ordering Information
(continued)
Macrocells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
3.3V Ordering Information
Macrocells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
32 143 CY37032VP44-143AXC A44 4 4-Pin Pb-free Thin Quad Flat Pack Commercial
100 CY37032VP44-100AXC A44 44-Pin Pb-free Thin Quad Flat Pack
64 143 CY37064VP44-143AXC A44 4 4-Pin Pb-free Thin Quad Flatpack Commercial
CY37064VP100-143AXC A100 100-Pin Pb-free Thin Quad Flatpack
100 CY37064VP44-100AXC A44 44-Pin Pb-free Thin Quad Flatpack Commercial
CY37064VP100-100AXC A100 100-Pin Pb-free Thin Quad Flatpack
CY37064VP100-100AXI A100 100-Pin Pb-free Thin Quad Flatpack Industrial
128 125 CY37128VP100-125AXC A100 100-Pin Pb-free Thin Quad Flat Pa ck Commercial
CY37128VP160-125AXC A160 160-Pin Pb-free Thin Quad Flat Pack
CY37128VP160-125AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
83 CY37128VP100-83AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial
CY37128VP160-83AXC A160 160-Pin Pb-free Thin Quad Flat Pack
CY37128VP100-83AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial
CY37128VP160-83AXI A160 160-Pin Pb-free Thin Quad Flat Pack
192 100 CY37192VP160-100AXC A160 160-Pin Pb-free Thin Quad Flat Pa ck Commercial
66 CY37192VP160-66AXC A160 160-Pin Pb-free Thin Quad Flat Pack
256 100 CY37256VP160-100AXC A160 160-Pin Pb-free Thin Quad Flat Pa ck Commercial
CY37256VP160-100AXI A160 160-Pin Pb-free Thin Quad Flat Pack Industrial
66 CY37256VP160-66AXC A160 160-Pin Pb-free Thin Quad Flat Pack Commercial
CY37256VP256-66BBC BB256 256-Bal l Fine-Pitch Ball Grid Array
CY37256VP256-66BBI BB256 256-Bal l Fine-Pitch Ball Grid Array Industrial
Range Ambient Temperature
[2]
Junction Temperature V
CC
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.16V
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 36 of 42
Package Diagrams
Figure 21. 44-Pin Pb-free Thin Plastic Qua d Flat Pack A44
Figure 22. 44-Pin Pb-free Plastic Leaded Chip Carrier J67
51-85064-*C
51-85003-*B
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 37 of 42
Figure 23. 100-Pin Pb-free Thin Plastic Quad Flat Pack (TQFP) A100
Figure 24. 160-Pin Pb-free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160
51-85048-*C
51-85049-*B
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 38 of 42
Figure 25. 256-Ball FBGA (17 x 17 mm) BB256
51-85108-*G
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 39 of 42
Document History Page
Document Title: Ultra37000 CPLD Family 5V and 3.3V ISR™ High Perf ormance CPLDs
Document Number: 38-03007
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 106272 04/18/01 SZV Change from Spec number: 38-00475 to 38-03007
*A 124942 03/21/03 OOR Updated 3.3V V
CC
requirements for –144 speeds
Added an Addendum
*B 126262 05/09/03 TEH Changed pinout for CY3712 8V BB100 package
*C 128125 07/16/03 HOM Obsoleted following 3.3V PLCC packaged devices:
CY37032VP44-143JC
CY37032VP44-100JC
CY37032VP44-100JI
CY37064VP44-143JC
CY37064VP84-143JC
CY37064VP44-100JC
CY37064VP84-100JC
CY37064VP44-100JI
CY37064VP84-100JI
CY37128VP84-125JC
CY37128VP84-83JC
CY37128VP84-83JI
*D 282709 11/08/04 YDT Changed package diagrams and labels for consistency
Added Pb-free logo on first page, and a note in Features
Added Pb-free package diagram labels
Added Pb-free Parts to Ordering Information
CY37032P44-200AXC, CY37032P44-200JXC, CY37032P4 4-154 AXI,
CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC,
CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC,
CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125 AXC,
CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI,
CY37064P100-125AXI, CY37128P84 -167JXC, CY37128P100-167AXC ,
CY37128P160-167AXC, CY37128 P84-125JXC, CY37128P100-125AXC,
CY37128P160-125AXC, CY37128 P84-125JXI, CY37128P100-125AXI,
CY37128P160-125AXI, CY37128P84 -100JXC, CY37128P100-100AXC ,
CY37128P160-100AXC, CY37128P100-100AXI, CY37192P1 60-154AXC,
CY37192P160-125AXC, CY37192P160-125AXI, CY37192P1 60-83AXC,
CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC,
CY37256P160-125AXI, CY37256P16 0-83AXC, CY37256P160-83AXI,
CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI,
CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC,
CY37064VP44-100AXC, CY37064VP100-100 AXC, CY37064VP44-100AXI,
CY37064VP100-100AXI, CY37128VP100-125AXC, CY37128VP160-125AXC,
CY37128VP160-125AXI, CY37128VP100-83AXC, CY37128VP160-83AXC,
CY37128VP100-83AXI, CY37128VP160-83AXI, CY37192VP160-100AXC,
CY37192VP160-66AXC, CY37256VP160-100AXC, CY37256VP160-100AXI,
CY37256VP160-66AXC
*E 321635 03/14/05 PCX Added Package Diagram BG292
Updated all PBGA package type information (BG292 & BG 388)
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 40 of 42
*F 2813051 12/04/09 AAE a.In the features section, redu ced the maximum number of pins from 400 to 256 in
reference to current package pin count in production.
b. 5V Selection Guide: Removed CY37384 and CY37512 options from the general
information table, removed CY37384 and CY37512 options from the Speed Bins
table, removed all in-active speed bin options, removed all in-active device-package
offering and I/O count options.
c. 3.3V Selection Guide: Removed CY37384V and CY37512V options from the
general information table, remo ved CY37384V and CY37512V options from the
Speed Bins table, removed all in-active speed bin options, removed all in-active
device-package offering and I/O count options.
d. Updated the development software support specific to Programming in which the
CY3700i (ISR Programming Kit) reference had been replaced with the CYUSBISRPC
Programming Cable User’s Guide.
e. Logic diagrams: Removed references to CY37384/ CY37384V and CY37512/
CY37512V.
f. 5V Device Electrical Characteristics specific to the Inductance table: Removed 44
pin CLCC, 84 pin PLCC, 84 pin CLCC and 208 pin PQFP from the table.
g. 3.3V Device Electrical Characteristics specific to the Inductance table: Removed
44 pin CLCC, 84 pin PLCC, 84 pin CLCC and 208 pin PQFP from the table.
h. Note 10: Updated CY37064VP100-AC to CY37064VP100-AXC and
CY37064VP44-143AC to CY37064VP44-143AXC. Removed references to
CY37064VP100-143BBC and CY37064VP48-143BAC because these are obsolete
device-package options.
i. Note 16: Removed CY37384 device as a reference.
j. Note 18: Removed CY37384V device as a reference.
k. Power Consumption graphs: Removed reference graphs for CY37384, CY37512,
CY37384V and CY37512V.
l. Pin Configurations: Removed reference pin-outs for 44 Pin CLCC, 48B FBGA, 84
Pin PLCC, 84 Pin CLCC, 100B FBGA, 160 pin CQFP, 208 pin CQFP, 208 pin PQFP,
292B PBGA, 388B PBGA, and 400B FBGA.
m. Updated the 5V Ordering In formation: Removed the following obsolete part
numbers: CY37032P44-200AC, CY37032P44-200 AXC, CY37032P44-200JC,
CY37032P44-200JXC, CY37032P44-154AC, CY37032P44-154JC,
CY37032P44-154AI, CY37032P44-154JI, CY37032P44-154JXI,
CY37032P44-125AC, CY37032P44-125 JC, CY37032P44-125AI,
CY37032P44-125JI, CY37064P44-200AC, CY37064P44-200AXC,
CY37064P44-200JC, CY37064P44-200 JXC, CY37064P84-200JC,
CY37064P100-200AC, CY37064P44-154AC, CY37064P44-154JC,
CY37064P84-154JC, CY37064P100-154AC, CY37064P44-154AI,
CY37064P44-154JI, CY37064P100-154AI, CY37064P44-125AC,
CY37064P44-125JC, CY37064P84-125 JC, CY37064P100-125AC,
CY37064P44-125AI, CY37064P44-125JI, CY37064P84-125JI,
CY37064P100-125AI, 5962-995 1901QYA, CY37128P84-167JC,
CY37128P84-167JXC, CY37128P100-167AC, CY37128P100-167AXC,
CY37128P160-167AC, CY37128P84-125JC, CY37128P84-125JXC,
CY37128P100-125AC, CY37128P160-125AC, CY37128P84-1 25JI,
CY37128P84-125JXI, CY37128P100-125AI, CY37128P160-125AI,
5962-9952102QYA, CY37128P84-100JC, CY37128P84-100JXC,
CY37128P100-100AC, CY37128P160-100AC, CY37128P84-1 00JI,
CY37128P100-100AI, CY37128P10 0-100AXI, CY37128P160-100AI,
5962-9952101QYA, CY37192P160-154AC, CY37192P160-154AXC,
CY37192P160-125AC, CY37192P160-125AI, CY37192P160-83AC,
CY37192P160-83AI, CY37256P160-154AC, CY37256P160-154AXC,
CY37256P208-154NC, CY37256P256-154BGC, CY37256P160-125AC,
CY37256P208-125NC, CY37256P256-125BGC, CY37256P160-125AI,
CY37256P208-125NI, CY37256P2 56-125BGI, 5962-9952302QZC,
CY37256P160-83AC, CY37256P208-83NC, CY37256P256-83BGC,
Document Title: Ultra37000 CPLD Family 5V and 3.3V ISR™ High Perf ormance CPLDs
Document Number: 38-03007
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
[+] Feedback
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *F Page 41 of 42
CY37256P160-83AI, CY37256P208-83NI, CY37256P256-83BGI,
CY37384P208-125NC, CY37384P256-125BGC, CY37384P208-83NC,
CY37384P256-83BGC, CY37384P208-83NI, 5962-9952301QZC,
CY37384P256-83BG, CY37512P208-125NC, CY37512P256-125BGC,
CY37512P208-100NC, CY37512P256-100BGC, CY37512P352-100BGC,
CY37512P208-100NI, CY37512P2 56-100BGI, CY37512P352-100BGI,
5962-9952502QZC, CY37512P208-83NC, CY37512P256-83BGC,
CY37512P352-83BGC, CY37512P208-83NI, CY37512P256-83BGI,
CY37512P352-83BGI, 5962-9952501QZC.
n. Updated the 3.3V Ordering Information: Removed the following obsol ete part
numbers: CY37032VP44-143AC, CY37032VP48-143BAC, CY37032VP44-100AC,
CY37032VP48-100BAC, CY37032VP44-100AI, CY37032 VP44-100AXI,
CY37032VP48-100BAI, CY37032VP44-100JI, CY37032VP44-100JXI,
CY37064VP44-143AC, CY37064VP48 -143BAC, CY37064VP100-143AC,
CY37064VP100-143BBC, CY37064VP44-100AC, CY37064VP48-100BAC,
CY37064VP100-100AC, CY37064 VP100-100BBC, CY37064VP44-100AI,
CY37064VP44-100AXI, CY37064VP48-100BAI, CY37064VP100-100BBI,
CY37064VP100-100AI, 5962-995 2001QYA, CY37128VP100-125AC,
CY37128VP100-125BBC, CY37128VP160-125AC, CY37128VP160-125AI,
CY37128VP100-83AC, CY37128VP100-83BBC, CY37128VP160-83AC,
CY37128VP100-83AI, CY37128VP100-83BBI, CY37128VP160-83AI,
5962-9952201QYA, CY37192VP160-100AC, CY37192VP160-66AC,
CY37192VP160-66AI, CY37256VP160-100AC, CY37256VP208-100NC,
CY37256VP256-100BGC, CY37256VP256-100BBC, CY37256VP160-100AI,
CY37256VP160-66AC, CY37256VP208-66NC, CY37256VP256-66BGC,
CY37256VP160-66AI, CY37256VP256-66BGI, 5962-9952401QZC,
CY37384VP208-83NC, CY37384 VP256-83BGC, CY37384VP208-66NC,
CY37384VP256-66BGC, CY37384VP208-66NI, CY37384VP256-66BGI,
CY37512VP208-83NC, CY37512 VP256-83BGC, CY37512VP352-83BGC,
CY37512VP400-83BBC, CY37512VP208-66NC, CY37512VP256-66BGC,
CY37512VP352-66BGC, CY37512VP400-66BBC, CY37512VP208-66NI,
CY37512VP256-66BGI, CY37512VP352-66BGI, CY37512VP400-66BBI,
5962-9952601QZC.
o. Updated package diagram drawing revisions on the following: 51-85064, 51-85003,
51-85048.
p. Removed package diagram drawing re ferences for obsoleted part numbers:
44 pin CLCC (51-80014), 48FBGA (51-85109), 84 pin CLCC (51-80095), 100B FBGA
(51-85107), 160 pin CQFP (5 1-80106), 208 pin PQFP (51-85069), 208 pin CQ FP
(51-80105), 292B PBGA (51-85097), 388B PBGA (51-85103), 400B FBGA
(51-85111).
q. Addendum for 3.3V Operating Range: Update d CY37064VP100-AC to
CY37064VP100-AXC and CY37064VP4 4-143 AC to CY37064VP44-143AXC.
Removed references to CY37064VP100-143BBC and CY37064VP48-143BAC
because these are obsolete device-package options.
r. Removed Military Operating Range because all Military Part numbers have been
obsoleted.
Document Title: Ultra37000 CPLD Family 5V and 3.3V ISR™ High Perf ormance CPLDs
Document Number: 38-03007
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
[+] Feedback
Document #: 38-03007 Rev. *F Revised November 23, 2009 Page 42 of 42
ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp
Professional, Warp Enterprise, and Ultra37000 are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their
respective holders.
Ultra37000 CPLD Family
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress p roducts are not warranted nor int ended to be used for med ical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furth ermore, Cypress do es not auth orize its prod ucts for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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