LXT901A/907A
Universal 3.3V Ethernet Transceiver
Datasheet
The LXT 901A an d L XT 907A are ne w generati on Universal Ethernet Transce ive rs with
impr oved noise immunity an d outpu t filtering. The feature set of the LXT901A/907A has been
str e a mlined, re moving Remote Signa ling capabi lities. The LXT901A a nd LXT907A provide all
the active circuitry to interface most standard IEEE 802.3 con trollers to either the 10BASE-T
media or Attachment Unit Inter face (AUI).
The LXT901A and LXT907A are identical excep t fo r th e function of one pin. The LXT901A,
with s e lectabl e term inatio n impedance, allows the use of either shielded or uns hielded twis ted-
pai r c a ble. The LXT907A offers a Signal Qualit y E rror Disabl e (DSQE) function .
LXT901A and LXT907A functions include Manchester encodin g/decoding, receiv er squ elch
and transmit pulse shaping, jabber, link testing, and reversed polarity detection/correction.
Applications
Product Features
■Access devices (DSL, Cable Modems, and
Set-top Boxe s)
■Routers/Bridges/Switches/Hubs
■Telecom Backplane
■USB to Ethernet Converters
Functional Features
■Integr ated Filters - Simp lify FCC
Compliance
■Integrated Manchester Encoder/Decoder
■10BASE-T Transceiver
■AUI Transce i ve r
■Full-Duplex Capable (20 Mbps)
Diagnostic Features
■Four LED Drivers
■AUI/RJ -45 Loopback
Convenience Features
■Automatic/Manual AUI/RJ-45 Sel ection
■Automatic Polarity Correction
■SQE Disable function (LXT907A)
■Programmable Impedance Driver
(LXT901A)
■Single 3.3V operation
■Power-Down Mode and four loop ba c k
modes
■Available in 64-pin LQFP and 44-pin
PLCC packages
■Com mercial (0 t o + 7 0oC)
For technical assistance on this product, please call Order Number: 249098-002
1-800-628-8686, or send an e-mail to support@mailbox.intel.com. June 2001
2 Datashe et
Docu men t #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Information in this document is provided in connection with I ntel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this docum ent. E xcept as prov ide d in Intel’s Terms and Co ndi tions of Sale fo r such products , Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpos e, merch antability, or infringement of any patent, copyright or oth er intellect ual proper ty right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make cha nges to speci ficatio ns and prod uct descript io ns at any time, without noti ce.
Designer s mus t not rely on the absen ce or charact erist ic s of any featu res or instruc tions m ark ed "res erved" or "undefined." In tel reserves these for
future definition and shall have no responsibi lity wha tsoeve r for conf licts or incompatibil ities arisi ng from futu re chang es to them .
The LXT901A/907A may contain design defects or errors known as errata which may cause the product to devi ate from publ is hed specifications.
Current charac teri zed errata are available on requ est .
Contact your local Intel sale s office or your distributor to obtain the latest specificat ion s and befo re placing your product order.
Copies of documents which have an ordering numb er and are referenc ed in this docume nt, or other Intel literature may be obtained by call ing
1-800-548-4725 or by visiting Intel’s website at http://www.intel .com.
Copyrigh t © Intel Corpor at ion, 2001
*Third-party brands and nam es are the propert y of their respect ive owne rs.
Datasheet 3
Docu me nt #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Contents
Contents
1.0 Pin Assignments and Signal Des criptions ....................................................................8
2.0 Functional Descriptio n ..................................................................................................11
2.1 Controller Compatibility Modes ...........................................................................11
2.2 Transmit Function................................................................................................12
2.2.1 Jabber Control Function.........................................................................13
2.2.2 SQE Function.........................................................................................13
2.2.2.1 SQE Disable Function (LXT907A only).....................................14
2.3 Receive Function.................................................................................................14
2.3.1 Polarity Reverse Function......................................................................15
2.3.2 Collision Detection Function...................................................................15
2.4 Loopback Functions............................................................................................16
2.4. 1 Standar d TP Loopbac k.......... ... ............. ................. ... .............. ...............16
2.4.2 Forced TP Loopback..............................................................................16
2.4.3 AUI Loopback.........................................................................................17
2.4. 4 Extern al Loo pbac k....... ....................... ................. ... ............. ................. ..17
2.5 Link Integ r ity T es t Functi o n...... .............................. ................ .... .........................17
2.6 Link Puls e Trans mi ssion ... ............. ................. ... .............. ....................... ............19
3.0 Application In format i on.................................................................................................19
3.1 Twisted-Pair Impedance Matching......................................................................19
3.2 Cryst al In fo rma tio n..... ....... ... .............. ....................... ....................... ................. ..19
3.3 Magnetics Information.........................................................................................19
3.4 Typical Applications .............................................................................................20
3.4.1 Auto Port Select with External Loopback Control ...................................20
3.4.2 Full-Duplex Support................................................................................22
3.4.3 Dual Network Support - 10Base-T and Token Ring...............................23
3.4.4 Manual Port Select with Link Test Function...........................................24
3.4.5 Three Media Application .........................................................................26
3.4.6 AUI Encoder/Decoder Only....................................................................27
3.4.7 150W Shielded Twisted-Pair Only (LXT901A only)................................28
4.0 T est Specifications.........................................................................................................29
4.1 Timi ng Diagr am s for Mode 1 (MD1 = Low, MD 0 = L o w) Figures 17 - 22............33
4.2 Timi ng Diagr am s for Mode 2 (MD1 = Low, MD 0 = H i gh) Figures 23 - 28...........35
4.3 Timi ng Diagr am s for Mode 3 (MD1 = High, MD 0 = Low) F i gures 29 - 36...........37
4.4 Timi ng Diagrams for M ode 4 (MD1 = High, MD 0 = H i gh) Figures 37 - 42..........40
5.0 M echani cal Specifi cation s.............................................................................................42
A Ordering Inf ormation .....................................................................................................45
Contents
4 Datashe et
Docu men t #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Figures 1 LXT901A/907A Block Diagram .............................................................................7
2 LXT901A/907A Pin Assignments .........................................................................8
3 TPO Output Waveform .......................................................................................12
4 Jabber Control Function .....................................................................................13
5 SQE Function .....................................................................................................14
6 Collision Detection Function ...............................................................................16
7 Link Integrity Test Function ................................................................................18
8 Transmitted Link Integrity Pulse Timing .............................................................19
9 LAN Adapter Board - Auto Port Select with External LPBK C ontrol ..................2 1
10 Full-Duplex Operation ........................................................................................22
11 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ......23
12 LAN Adap ter Board - Manual Port Sele ct wi th Link Test Func ti on............. ... ......24
13 Manual Port Select with Seeq 8005 Controller ..................................................25
14 Three Medi a Applic at ion ...................... ... ............. ................. ... .............. ............26
15 AUI Encoder/Decoder Only Application .............................................................27
16 150 W Shielded Twisted-Pair Only Application (LXT901A) ...............................28
17 Mode 1 RCLK/Start-of-Frame Timing ................................................................33
18 Mode 1 RCLK/End-of-Frame Timing ..................................................................33
19 Mode 1 Transmit Timing ....................................................................................3 4
20 Mode 1 Collision Detect Timing .........................................................................34
21 Mode 1 COL/CI Output Timing ...........................................................................34
22 Mode 1 Loopback Timing ...................................................................................34
23 Mode 2 RCLK/Start-of-Frame Timing ................................................................35
24 Mode 2 RCLK/End-of-Frame Timing ..................................................................35
25 Mode 2 Transmit Timing ....................................................................................3 6
26 Mode 2 Collision Detect Timing .........................................................................36
27 Mode 2 COL/CI Output Timing ...........................................................................36
28 Mode 2 Loopback Timing ...................................................................................36
29 Mode 3 RCLK/Start-of-Frame Timing (LXT901A) ..............................................37
30 Mode 3 RCLK/End-of-Frame Timing (LXT901A) ...............................................37
31 Mode 3 RCLK/Start-of-Frame Timing (LXT907A) ..............................................38
32 Mode 3 RCLK/End-of-Frame Timing (LXT907A) ...............................................38
33 Mode 3 Transmit Timing ....................................................................................3 9
34 Mode 3 Collision Detect Timing ..........................................................................39
35 Mode 3 COL/CI Output Timing ...........................................................................39
36 Mode 3 Loopback Timing ...................................................................................39
37 Mode 4 RCLK/Start-of-Frame Timing .................................................................40
38 Mode 4 RCLK/End-of-Frame Timing ..................................................................40
39 Mode 4 Transmit Timing ....................................................................................4 1
40 Mode 4 Collision Detect Timing .........................................................................41
41 Mode 4 COL/CI Output Timing ...........................................................................41
42 Mode 4 Loopback Timing ...................................................................................41
43 44-Pin PLCC.......................................................................................................42
44 64-Pin LQFP ......................................................................................................43
45 Ordering Information - Sample............................................................................45
Datasheet 5
Docu me nt #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Contents
Tables 1 LXT901A/907A Signal Descriptions......................................................................9
2 Controller Compatibility Modes ...........................................................................12
3 Suitable Crystals .................................................................................................19
4 Absolute Maximum Values..................................................................................29
5 Recommended Operating Conditions.................................................................29
6 I/O Electrical Characteristics...............................................................................29
7 AUI Electrical Characteristics..............................................................................30
8 TP Electrical Characteristics ...............................................................................30
9 Switching Characteristics....................................................................................31
10 RC LK/ S ta rt -of- F ram e Timi ng.................... .... ............. ................. ... ......................31
11 RCLK/End-of-Frame Timing................................................................................32
12 Transmit Timing...................................................................................................32
13 Collision, COL/CI Output and Loopback Timing ..................................................32
14 Product Informatio n.............................................................................................45
Contents
6 Datashe et
Docu men t #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Revision History
Date Revision Page Description
June 2001 002
1New items under “Applications”
21 Figure 9: Added 0.1 µF label to capacitor at bottom of graphic.
22 Figure 10: Added 0.1 µF label to capacitor at bottom of graphic.
23 Figure 11Added 0.1 µF label to capacitor at bottom of graphic.
24 Figure 12: Added 0.1 µF label to capacitor at bottom of graphic.
25 Figure 13: Added 0.1 µF label to capacitor at bottom of graphic.
29 Added 2nd para under Test Specification regarding Quality and
Reliability information.
29 Removed “Ambient operating tem perature” from Abso lute
Maximum Values t able.
45 Added Appendix: Product Ordering Information
Universal 3.3V E thernet Transceiv er — L X T 901A/ 907A
Datasheet 7
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 1. LXT901A/907 A Block Diagram
MODE SELECT LOGIC
Controller Compatibility
Port Select
Loopback
Link test
SQUELCH / LINK
DETECT
MANCHESTER
DECODER
COLLISION LOGIC
WATCHDOG
TIMER
XTAL
OSC
MANCHESTER
ENCODER
Select:
PLS Only
or
PLS / MAU
DO
AUTOSEL
PAUI
LBK
LI
TCLK
CLKO
CLKI
TEN
TXD
CD
LEDL
MD0
TPOPA
TPONA
TPONB
TPIP
TPIN
PULSE SHAPER
AND FILTER
TWISTED PAIR
INTERFACE
COLLISION/
POLARITY
DETECT
CORRECT
RC
RC
DI
LPBK
COLLISION
RECEIVER
RXD
RCLK
COL
CI
MD1
TPOPB
DOP
DON
DIP
DIN
CIP
CIN
LEDR LEDT/PDN LEDC/FDE NTH JAB PLR
+
-
DROP CABLE
INTERFACE
ECL
TX
AMP
RX SLICER
RX
SLICER
CMOS
TX
AMP
DSQE
(LXT907A only)
(LXT901A only)
STP
LXT901A/907A — Universal 3.3V Ethernet Transceiver
8Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
1.0 Pin Assignments and Signal Descriptions
Figure 2. LX T901A/907A Pin Assignm ents
7
8
9
10
11
12
13
14
15
16
17
n/c
LI
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
TPIN
TPIP
DSQE (907 A) or STP (901A)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
n/c
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
LEDR
LEDT/PDN
LEDL
LEDC/FDE
LBK
GND1
RBIAS
n/c
RXD
CD
RCLK
MD1
MD0
NTH
CIN
CIP
VCC1
DON
DOP
DIN
DIP
PAUI
6
5
4
3
2
1
44
43
42
41
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
CIN
NTH
MD0
MD1
n/c
n/c
n/c
TPIN
TPIP
n/c
DSQE (907A) or STP (901A)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
n/c
n/c
n/c
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
n/c
n/c
LI
n/c
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
n/c
n/c
n/c
n/c
RCLK
CD
RXD
n/c
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LXT901A/907A PC X X
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
Rev #
LXT901A/907 ALC XX
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
Rev #
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 9
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Ta bl e 1. LXT901A/907 A Sign al Descriptions
Pin # Symbol I/O1 Description
PLCC LQFP
1
34 10
56 VCC1
VCC2 –
–Power Supply 1 and 2. Power supply inputs of +3.3 volts.
–9VCCA–Analog Supply. (+3.3V)
2
311
12 CIP
CIN I
IAUI Collision Pair . Differ enti al input to the AUI transc eiver C I circuit . The input is
collis ion signaling or SQE.
413 NTHI
Normal Threshold. Selects normal or reduced threshold.
When NTH is High, the normal TP squelch threshold is in effect.
When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB.
5
614
15 MD0
MD1 I
IMode Select 0 (MD0) and Mode Select 1 ( MD1). Mode sel ect pins determine the
controller compatibility mode in accordance with Table 2.
819 LII
Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
921 JABOJabber Indicator. Output goes High to indicate Jabber state.
10 22 TEST I Test. For Intel internal use only.
It is recommended to tie this pin High externally.
11 23 TCLK O Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
12 24 TXD I Transmit Data. Input signal containing NR Z data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
13 25 TEN I Transmit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
14
15 26
27 CLKO
CLKI O
ICrystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
16 28 COL O Collision Detect. Output which drives the collision detect input of the controller.
17 29 AUTOSEL I
Automatic Port Select.
When High, automatic port selection is enabled (the 901A/907A defaults to the
AUI port only if TP link integrity = Fail).
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
18 34 LEDR OD Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
19 35 LEDT/
PDN OD Transmit LED (LEDT)/Pow er-Down (PDN). O pen drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
If externally pulled Low, the LXT901A/907A goes to power-down state.
20 36 LEDL OD
Link LED. Open drain driver for link integrity indicator. Output is pulled Low
during link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and the
LXT901A/907A transmits link test pulses continuously.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
LXT901A/907A — Universal 3.3V Ethernet Transceiver
10 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
21 37 LEDC/
FDE OD
Collision LED (LEDC)/Full-Duplex Enable (FDE). O pen drain driver for the
collision indicator pulls Low during collision.
LED “On” (i.e., Low output) time is extended by approximately 100 ms.
If externally tied Low, enables full-duplex operation by disabling the internal TP
loopback and collision detection circuits in anticipation of external twisted-pair
loopback or full-duplex operation.
If this pin is not used, tie High or directly to Vcc.
22 38 LBK I Loopback. Enables internal loopback mode. Refer to Functional Description for
details.
23
33 39
55 GND1
GND2 –
–Ground Returns 1 and 2. Grounds
–40 GNDA –Analog Ground.
24 42 RBIAS I Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating
circuit bias.
26 45 RXD O Receive Data. Output signal. Connect directly to the receive data input of the
controller.
27 46 CD O C arrier Detect. An output to notify the controller of activity on the network.
28 47 RCLK O Receive Clock. A recovered 10 MHz clock that is synchronous to the received
data. Connect to the controller receive clock input.
30 52 PLR O Polarity Reverse. Output goes High to indicate reversed polarity at the twisted-
pair input.
31
36
32
35
53
58
54
57
TPOPB
TPONB
TPOPA
TPONA
O
O
O
O
T w isted-Pair Transmit Pairs A & B. Two dif fer ential driver pair output s (A and B)
to the twisted-pair cable. The outputs are pre-equalized.
Each pair must be shorted together and tied to the transformer through a
24.9Ω 1% series resistor to match impedance of 100Ω.
Refer to Figure 16 on page 28 in the Applic ations Secti on for information on 150Ω
configurations.
37 59 STP I
STP Select (LXT901A only).
When STP is Low, 150Ω termination for shielded twisted-pair is selected.
When STP is High, 100Ω termination for unshielded twisted-pair is selected.
LXT907A is designed for 100Ω unshielded twisted-pair termination (not
selectable).
DSQE I
Disable SQE (LXT907A only).
When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled.
SQE must be disabled for normal operation in Hub/Switch applications.
LXT901A operates with SQE enabled (not selectable).
38
39 61
62 TPIP
TPIN I
ITwisted-Pair Receive Pair. A differential input pair from the twisted-pair cable.
Receive filter is integrated on-chip. No external filters are required.
40 3 PAUI I
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the
active port.
When PAUI is High, the AUI port is selected.
When PAUI is Low, the TP port is selected.
In Auto Port Select mode, PAUI must be tied to ground.
Tab le 1. LXT9 01 A/90 7A Signa l Descri ptions (Continued)
Pin # Symbol I/O1 Description
PLCC LQFP
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 11
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.0 Function al Description
The LXT901A/907A Universal Ethernet Interface Transceivers perform the physical layer
signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3
specific a tion. They function as a PLS-Only de vice (for us e with 10BASE -2 or 10BASE-5 coaxia l
cable networks) or as an Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks). In
addition to standard 10 Mbps opera tion, the y als o support ful l -duple x 20 Mbps operation.
The LXT901A/907 A interfaces a back-end controller to either an AUI drop cable or a twis ted-pair
(TP) cabl e . The controller interface includes a transmi t and receive clock and NRZ data channel s,
as well as mode control logic and signaling. The AUI inter face comprises three circuits: Data
Output (DO), Data Input (DI) and Collision (CI). Th e twis ted-pair int e rface is compr ised of two
circuits: Twisted-P air Input (TPI) and Twisted- Pair Outp ut (TPO). In addition to the thre e basic
inter faces, the LXT901A/907 A con tains an internal crystal oscillator and four LED drivers for
visual sta tus report ing.
Functions are defined f rom the back-end controller side of the interf ace. The Transmit fun ction
refers to da ta transm itted by the back- e nd to the AUI ca ble (PLS-Only mode) or to the twist e d-pair
network (Integrated P LS/MAU mode). The Receive function refers to dat a received by the back-
en d from the AUI cable (PLS-Only) or from the twisted-pair ne twork (Integrat e d PL S/MAU
mode). In the integrated PLS/MAU mode , the L XT 9 01A/907A performs all requ ired MAU
functions defined by the IEEE 802.3 10BASE–T specification, such as collision detection, link
inte grity te sting, signal qu a lity error messa ging, jabber control, and loopback. In the PLS- only
mode, the LX T901A/907A rec e ive s inc oming signal s from th e AUI DI circ uit, wi th ± 18 ns of
jitter, and drives the AUI DO circuit.
2.1 Controller Compatibility Modes
The LXT901A/907A are compatible with mos t ind us try standard control lers, including devices
pro duced by Mo torola, A MD, Intel, Fu jitsu, Na tional Sem iconduc tor , Seeq, and Texas Instr uments.
Four differe nt control signal timing and pola rity schemes (Modes 1 through 4) are re quired to
41
42 4
5DIP
DIN I
IAUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The
input is Manchester encoded.
43
44 7
8DOP
DON O
OAUI Transmit Pair. A differential output driver pair for the AUI transceiver cable.
The output is Manchester encoded.
7, 25,
29
1, 2, 6, 1 6,
17, 18, 20,
30, 31, 32,
33, 41, 43,
44, 48, 49,
50, 51, 60,
63, 64
N/C –No Connect (Internally tied to ground).
Ta bl e 1. LXT901A/907 A Signal Descri pt ions (Conti nued)
Pin # Symbol I/O1 Description
PLCC LQFP
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
LXT901A/907A — Universal 3.3V Ethernet Transceiver
12 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
achieve this compati bility. Mode select pins (M D0 and MD1) determine contr oller compatibility
mode s as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for
each mode.
2.2 Transmit Function
The LXT901A/907A receives NRZ data from the controller at the TXD input, as shown in
Figure 1, “LXT901A/907A Block Diagram” on page 7 , and pa sses it t hrough a Ma nchester
encoder. The encoded data is then transferred to either the AUI cab le (the DO circuit) or the
twisted-pa ir network (the TP O c ircuit). The a dvanced integra te d pulse shaping and filtering
net work produces the outp ut signa l on TPON and TPOP as show n in Figure 3. The TPO outp ut is
pre-d istorted and pre-filter ed to meet the 10BASE-T jitter template. An inter nal continuous
resistor-capa c itor filter is used to re move a ny high-frequen c y c l ocking noise from the pul se
shaping ci rcuitry. Integr ated filter s simplify the de si gn w ork required for FCC compliant EMI
performance. During idle per iods, the LXT901A/907A transm its link integr ity tes t pulses on the
TPO circuit (if LI is enabled and integrated, PLS/ MAU mode is selected). External resistors
contro l the termination impeda nce for the LXT907A. External resistors and the STP pin con t rol
terminati on impe dance on the LXT9 01A.
Table 2. Controll er Co m pati b i lity Modes
Controller Mode Setting
MD1 MD0
Mode 1
For Motorola 68EN360, MPC860, Advanced
Micro Devices AM7990 or compatible
controllers
Low Low
Mode 2
For Intel 82596 or
compatible controllers1Low High
Mode 3
For Fujitsu MB86950, MB86960 or
compatible controllers (Seeq 8005)2High Low
Mode 4
For National Semiconductor 8390 or
compatible controllers
(TI TMS380C26)
High High
1. Refer to Intel Application Note 51 when designing with Intel
Controllers.
2. SEEQ controllers r equire inver ters on CL K1, LBK, RCLK and
COL.
Figure 3. TPO Output Waveform
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 13
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.2.1 Ja bber Control Function
Figure 4 is a state diagram of the LXT901A/907A jabber control function. The on-chip watchdog
timer preven ts the DTE from lockin g into a continuous transmit mode. When a transmission
exceeds the time limit, the watchdog tim er di sab les the transmit and loopback functions, and
activa tes th e JAB pin. On ce the LX T901A/907A is i n the j abber state, t he TXD ci rcuit must r emain
idle f or a perio d of 250 to 750 ms before it exits the jabber state.
2.2.2 S QE Function
In the integrat e d PLS/MAU mode, the LX T901A/907A supports t he signa l qua lity error (SQE)
function as shown in Figure 5 on page 14, a l though the SQE function ca n be disabled on the
LXT907A. After every succes sful transmission on the 10BASE-T network, when SQE is enabled,
the L XT901A/907A transmits the SQE sign al for 10 bit times ± 5 bit times over the int e rnal CI
circu it, which is indicated on the COL pin of the device. When using the AUI of the
LXT9 01A/907A, the SQE f unction is determined by the external MA U attached.
Figure 4. Ja bber C ontrol Function
No Output
Nonjabber Output
Start_XMIT_MAX_Timer
Power On
DO=Active
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Active ∗
XMIT_Max_Timer_Done
DO=Idle
DO=Idle
Unjab_ Timer_Done DO=Active ∗
Unjab_Timer_Not_Done
LXT901A/907A — Universal 3.3V Ethernet Transceiver
14 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.2.2.1 SQE Disable Function (LXT907A only)
SQE mus t be disabl e d for normal operation in hub and switch applicatio ns. Th e LX T907A is
con figured with an SQE Disable function. T he SQE fu nc tion is disab l e d when D SQE is set High,
and enabled when DSQE is Low.
2.3 Receive Function
The LXT901A/907A receiv e func tion acquires timing and data from the twisted- pair network (the
TPI ci rcu it) or from the AUI (the DI circ uit). Valid received s i gnals are passed t hrough the on-c hip
filters and Manchester decoder, then output as decoded NRZ data and receive timing on the RXD
an d R C L K pi ns, re s pe c t i ve l y.
An inter nal RC filt er and an intelligent squelc h function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squel c h level and with proper timing. If the diffe rential signal at the TPI or the DI cir cuit inputs
fal l s below 75 percent of the thre shold level (unsquelched) for 8 bit times (typica l), the LXT901A/
907A receive functio n e nters the idle state. If the polari ty of the TPI c i rcuit is reve rsed, LXT901A/
907A de tects the pola rity reve rse and reports i t via the PLR output. The LXT901 A/907A
automatically corrects reversed polarity.
Figure 5. S QE Function
Ou tp ut Idle
Output Detected
Pow e r On
DO=Active
SQE Wait Test
Start_SQE_Test__Wait_Timer
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test__Wait_Timer_Done ∗
XMIT=Enable
DO=Idle
SQE_Test_Timer_Done
XMIT=Disable
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 15
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.3.1 Polarity Reverse Function
Th e LX T901A/907A polarity reverse function uses both link pulses and end-of-frame data to
determine th e polar ity of t he receive d signal. A reversed po larity condition is detected when eight
opposite receiv e link pulses are detected without re ceipt of a link puls e of th e expected polarity.
Reversed polarity is als o detected if four fr am es are received with a reversed start-of -idle.
Whenever a correct po larity frame or a co rrect lin k pulse is r eceived, these t wo counters are r eset to
zero. If the LXT901A /907A enters the link fail state and no valid da ta or link pulses are received
within 96 to 128 ms, the polarity is reset to the default non- flippe d condition. If Link Integrity
Testing is disabled, polarity detection is based only on received data. Polar ity correction is always
enabled.
2.3.2 Collision Detection Function
The collision detection functio n operates on the twis ted- pair side of th e interface. For standard
(hal f- duplex) 10BASE -T operation, a col lis ion is defined a s the simultaneous presence of valid
sig nals on both the TPI circuit and the TPO cir cuit. The LXT901 A/907A reports collisions to the
back-end via the COL pin. If the TPI circuit becomes active while there is act ivity on the TPO
circu it, the TPI data is pas sed to the back-end over the RXD circuit, disabling normal loopback.
Fig ure 6 on pa ge 16 is a stat e diag ram of the L XT901A /90 7A coll ision detect ion functi on. Ref er to
Test Spe c i fications for collision detection and COL/CI output timing.
Note: For full-duplex opera tion on the TP or AUI port, the c ollision detectio n c i rcui try must be disabled
by s e tting FDE Lo w.
LXT901A/907A — Universal 3.3V Ethernet Transceiver
16 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.4 Loopback Functions
2.4.1 S tandard TP Loopback
The LXT 901A/907A provides the standard loopback f unction define d by the 10BASE-T
specification for the twis ted-p air port. The loopback function operates in conjunction with the
transm it functi on. Data transm itt ed by the back-en d is internal ly loo ped back with in the LXT9 01A/
907A from the TXD pin through the Mancheste r e ncoder/d e c oder to the RXD pin an d re turned to
the back- end. This st andard lo opback fu nction is disab led when a data c ollisio n oc curs, cle aring the
RXD circ uit for the T PI data. St a ndard loopba c k is also dis a bled during link fail and ja bbe r stat e s.
The LXT901A/907A also provides three additional loopback function s.
2.4.2 Forced TP Loopback
“Forced” twis ted-pai r loopback is controlled by the LBK pin. W hen the twi sted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisi ons on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
Figure 6. Collision Detectio n Function
Idle
Power On
A
Collision
TPO=DO
DI=TPI
CI=SQE
Output
TPO=DO
DI=DO
Input
DI=TPI
DO=Active ∗
TPI=Idle ∗
XMIT=Enable
DO=Active ∗
TPI=Active ∗
XMIT=Enable
A A
DO=Active ∗
TPI=Active ∗
XMIT=Enable
DO=Active ∗
TPI=Idle
DO=Idle+
XMIT=Disable
DO=Idle
TPI=Idle
TPI=Active
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 17
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.4.3 AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data tr ans mitted by the back-end is internally looped back fr om the TXD pin th rou gh the
Ma nc hester enc oder/decoder to the RXD pin. When L B K is Low, no AUI loopback occurs.
2.4.4 External Loopback
An extern al loopback mode, usefu l fo r system -level testing, is controlled by the LEDC/ FD E pin.
When LEDC/FDE is t ie d Low, the LXT901A/ 907A disables the co llision dete c tion and int ernal
loop back circuits, to allow external loopback. External loo pback mode can be set on either
twis ted-pair or AUI ports.
2.5 Link Integrity Test Function
Figure 7 on page 18 is a state diag ram of the L XT90 1A/907 A L ink Int egr ity tes t func ti on. The link
integrity test is used to determ ine the status of the receive side twisted -pair cable. Link integrit y
tes ting i s enabled when the LI pi n is tied H igh. When enab led , the receiv er reco gnizes l ink in teg rity
pulses wh ich are transmitted in the absence of receive traff ic. If no serial dat a st ream or link
integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the
tran smit and nor ma l loop back functi ons . The L XT901 A/9 07A ign or es any lin k integ rit y puls e with
an interval les s than 2 - 7 ms. Th e LXT 901A/907A will remain in the link fail state until it detects
either a serial data packet or two or more link integrity pulses.
LXT901A/907A — Universal 3.3V Ethernet Transceiver
18 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 7. Li nk Integrity Test Function
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Pow e r On
Link Test Fail Reset
Link_Count=0
XMIT=Disable
RCVR=Disable
Link_Loss_Timer_Done
∗ TPI=Idle
∗ Link_Test_Rcvd=False
TPI=Active+
(Link_Test_Rcvd=True
∗ Link_Test_Min_Timer_Done)
Link Test Fail Wait
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active
TPI=Active Link_Test_Rcvd=Idle
∗ TPI=Idle
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
∗ Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 19
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
2.6 Link Pulse Transmission
When not transmitting data, the LXT901 A/907A transmits IEEE 802.3 -compliant standard link
pulses. Fi gure 8 shows the link integrity pulse timing.
3.0 A pplication Information
3.1 Twisted-Pair Impedance Matching
Resi stors must be in stall ed on each i nput an d output pai r to m atch impe dance of the netw ork media
being used. The LXT907A is configured with 100Ω termination for Unshielded Twisted-Pair
(UTP). In this case, the positive and negative sides of both output pairs are shor te d together
(TPOPA/TPOPB and TPONA/TPONB) and tied to the transformer through a 24.9Ω 1% se ries
resistor.
Th e LXT901 A is designed with an STP Select pin tha t allows the device to match bot h 100Ω and
150Ω media. A dual r es is tor combinatio n can be configured to accommodate eit her line
termination as shown in Fi gure 16 on page 28 . When 100Ω termination is selected, both A an d B
pairs are driven in parallel. When 150Ω termination is s elected, the B pair is tri-stated and only t he
A pai r is dr iven.
3.2 Crystal Information
Des igners should test and validate cryst a ls before com mitting to a specific c om ponent. Based on
limited evaluation, Table 3 lists s ome suit a b le crystals.
3.3 Magnetics Info rmation
The LXT901A and LXT907A require a 1: 1 ratio fo r the receive transfo rmer and a 1:√2 ratio for the
transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for the
da ta -in, da ta-out, and c ollision-pai r transformers. A cross-re ference list of s uitable magneti c s and
Figure 8. Transmitted Link Integ rity Pulse Timing
10-20 ms 10-20 ms
10-20 ms
10-20 ms 10-20 ms
10-20 ms
10-20 ms 10-20 ms
10-20 ms
Tabl e 3. Suita b le Crystals
Manufacturer Part Number
MTRON MP-1
MP-2
LXT901A/907A — Universal 3.3V Ethernet Transceiver
20 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
part numbe rs is available in Applica tion Note 73, Magnetic Manuf a c t urer s (248991-001), which
can be found on the In te l web si te (developer.intel.com / desi gn/network/). Des i gners must tes t a nd
validate all components for suitability in their applications.
3.4 Typical Applications
Figure 9 on p a ge 21 through Figure 16 on page 28 show typica l LX T901A/907A a pplications.
3.4.1 Auto Port Select with External Loopback Control
Figure 9 on p a ge 21 is a typica l LXT 901A/907A application . T he diagram groups similar pins
togeth er, but does not represent the actual LXT901A/90 7A pinou t. The contr oller interface pins
(trans mit data, clock and enable; receive da ta and clock; and th e collision detect, car rier dete ct and
loopback control pins) are shown a t the top left of the diagram.
Programm a ble option pi ns are grouped at the ce nter left of the diagram. T he PAUI pin is tied Lo w
and all other option pins are tied High. This setup selects the fo llowing options:
•Autom a tic Port S election
(PAUI Low a nd AUTO SEL High)
•Normal Receive Thres hold (NTH High)
•Mode 4, compat ible with Na tional NS8390 controllers (MD0 High, MD1 High)
•SQE Disabled (DSQE High for LXT907A only)
•UTP is selected (STP High for LXT 901A only)
•Lin k Testing E nabled (L I High)
St atus outputs are grouped at th e lower left of the diagram. Local status outpu ts dri ve LED
indicators.
Power and gr ound pins are shown at the bottom of the diagram. A s ingle power supply is used for
both VCC1 and VCC2, with a decoupling ca pacitor in stall e d be tween the power and ground
busse s. An add itional po we r and ground pin (VCCA and GNDA) is supported i n designs using the
64-pin LQF P package. A single power supply is used for all three power and ground pin s (VCC1,
VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling cap acitor between each po wer
an d grou n d buss.
The twisted-pair and AUI interfaces are shown at the upper and lower right of the diagra m,
respectively. Impedance matching resist ors for 100Ω UTP are installed in each I/O pair and no
external filters are required.
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 21
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 9. LAN Ada pte r Board - Auto Port Select with Ext erna l LPBK C ontrol
LXT901A/907A
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NE TW ORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CAB LE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD0
MD1
DSQE (907A)
STP (901A)
LI
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
NS8390 BACK-END
CONTROLLER
INTERFACE
LOOPBACK
ENABLE
PROGRAMMING
OPTIONS
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330330
TEST
TPONA
TPONB
TPOPA
TPOPB
24.9 Ω 1%
24.9 Ω 1%
Bias resistor RB IAS sh ould be located close to the pin and isolat ed from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
1
2
1
1 : 1
1 : 2
1 : 1
0.1 µF
LXT901A/907A — Universal 3.3V Ethernet Transceiver
22 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.2 Full-Duplex Support
Figure 10 shows the L XT907A with a Texas Inst rumen ts 380C24 CommProcessor. The 380C24 is
compatible with Mode 4 (MD0 a nd MD1 bot h High). When used with the 380C24, or othe r full-
duplex capa ble controller, the LXT 907A supports full-duple x Ethe rnet, e ffec t ively doubling the
available band width of the network. In this application, the SQE function is enab led (DSQE tied
Low), and the AU I po rt is not us ed .
Figure 10. Ful l -Dupl ex Operation
LXT907A
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
RJ45
3
6
8
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
3
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
LEDC/FDE
TXD
TXEN
TXC
RXC
RXD
CSN
COLL
LPBK
1 %
+3.3 V VCC1
VCC2
CLKO
TMS380C24
1 : 2
To 10 BASE-T TWISTED-
PAIR NET WORK
20 MHz 20 pF20 pF
*TEST0 1N914
10 KΩ
4
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
1
2
3
4
Half/Full Dup lex Selec tion controlled by TMS380C2 4 Pins
Test0 and OUTSEL0.
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
Green Red Red
PROGRAMMING
OPTIONS
LINE STATUS
LEDR
LEDT/PDN
LEDL
330 330
OUTSEL0
PAUI
330
1
4.7 KΩ
TEST
DSQE
(907A)
*Open Collector
Driver
TPONA
TPONB
TPOPA
TPOPB
24.9 Ω 1%
24.9 Ω 1%
The TMS3 80C 26 may be substitute d for dual net w ork
suppor t of 10BASE-T and To ken Ring.
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
2
0.1 µF
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 23
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.3 Dual Network Support - 10Base-T and Token Ring
Figure 11 shows the LXT901A/907A with a Texas Instr uments 380C26 C ommProc e ssor. T he
380C2 6 is c ompa tib le wi th Mo de 4 ( MD0 a nd MD1 bo th Hi gh) . Whe n use d with the 38 0C2 6, both
the LXT901A/907A and a TMS38054 Token Ring transceiver can be tied to a single RJ-45,
al lowing dual netwo rk support from a single connector. The LXT901A/907A AUI port is not used.
The DSQE pin on the LXT907A is tied Low and the STP pin on the LX T901A is tie d High .
Figure 11. 38 0C 26 Inte rfa ce for Dua l Network Support of 10BASE-T and Token Ring
LXT901A/907A
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
From TI TMS38054 Token
Ri ng Transceiver
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
1
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
PROGRAMMING
OPTIONS
LINE ST ATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330330
380C26 2
To TI TMS38054 Token Ring
Transceiver
1 : 2
To 10 BASE-T TWISTED-
PAIR NETWORK
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
1
2
3
Additional magnetics and switching logic (not shown)
are required to implement the dual network solution.
24.9 Ω 1%
24.9 Ω 1%
TEST
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
3
DS QE 907A only
STP 901A onl y
0.1 µF
LXT901A/907A — Universal 3.3V Ethernet Transceiver
24 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.4 Manual Port Select with Link Test Function
Wit h MD0 ti e d L ow and MD1 tied High, the LXT901A/907A logic and framing are set to Mode 3
(compati ble with Fujits u MB86950 and MB86960, and Seeq 8005 co ntroll e rs ). Figur e 12 shows
the s etup for Fujit su co ntrol lers. F igur e 13 on p age 25 s hows the four in vert ers re quire d to in ter fac e
with the S eeq 800 5 controll er. As seen in Fi gur e 9 on pa ge 21 both t hes e M ode 3 app lic ations show
the LI pi n tied High, ena bling Link Testing; and the STP (LXT 901A o n ly) and NTH pins are both
tied High, selecti ng the standard receiver thresho ld and 100Ω t erm ination for unshielded TP cable.
Howeve r , in thes e applic atio ns A UT OSEL is t ied Low, allowin g exter nal port select ion thro ugh the
PAUI pin.
Figure 12. LA N A dapt er Bo ard - Manual Po rt Selec t with Link Test Funct ion
LXT901A/907A
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETW ORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CA BLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD0
MD1
DSQE (907A)
STP (901A)
LI
JAB
PLR
TXD
TEN
TCKN
RCKN
RXD
XCD
LBC
Red Red Red
MB 86 950 or MB 86 96 0
BACK-END/
CONTROLLER
INTERFACE
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330
1 : 2
Green
330
Port Selection
Bi as r esistor RBI A S should be loc ated c l ose t o the pin and isolated f r om oth er s ignal s .
TEST
24.9 Ω 1%
24.9 Ω 1%
XCOL
Opt ional : Centertap c apacit or m ay improve E MC depending on board lay out and syst em desig n.
2
1
1
2
1 : 1
1 : 1
0.1 µF
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 25
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 13. Manual Port Select with Seeq 8005 Controller
LXT901A/907A
CLKI
LBK TPIN 50 Ω
50 Ω
TPIP
1 : 1
116
14
6
5
4
3
2
1
11
0.1 µF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
CD
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78
>
12. 4 kΩ
RXD
RCLK
COL
TEN
TCLK
TXD
PAUI
AUTOSEL
NTH
MD0
MD1
DSQE (907A)
STP (901A)
LI
JAB
PLR
Red Red Red
LIN E ST ATUS
1 %
+3. 3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
330 330 330
1 : 2
Green
330
Por t Selection
CLKO
8005
CLKI
LPBK
CSN
RxD
RxC
COLL
TxEN
TxC
TxD
External
20 MHz
Source Left Open
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
TEST
24.9 Ω 1%
24.9 Ω 1%
Op ti onal : Cen t ertap c ap ac i t o r may im prov e EM C dep end ing on boar d la yo ut and s ys t em design.
2
1
2
1
1 : 1
1 : 1
0.1 µF
LXT901A/907A — Universal 3.3V Ethernet Transceiver
26 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.5 Th ree Media Application
Figure 14 s hows the LXT 907A in Mode 2 (compatible with Intel 82596 controllers) with
additional media options for the AUI port. Two tra nsformers are used to c ouple the AUI port to
either a D- connector or a BN C connector. A DP8392 coax transceiver with PM6044 power suppl y
are required to dr ive the th in coax network through the BNC.
Figure 14. Thre e Media Applicat io n
CLKI
TXD TPIN 50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10BASE-T
TWISTED-
PAIR
NETWORK
1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIP
RBIAS GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CABL E
(Thi ck Coa x)
Chassis
Gnd
Fuse
78 Ω
78 Ω
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
LI
MD1
MD0
JAB
PLR
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
82596 BACK-END/
CONTROLLER
INTERFACE
PROGRAMMING
OPTIONS
MODE SELECT
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
1 : 2
20 MHz
System
Clock
CLK
LinkTest
Enable
Po wer Down
1
2
4
5
7
89
10
12
13
15
16
78 Ω
1
2
4
5
7
89
10
12
13
15
16
DIN
CD-
CD+
TX-
VEE
TX+
RX-
RX+
VEE
CDS
TXD
RXI
VEE
RR-
RR+
GND
HBE
1N916
0V
B NC to TH IN
COAX
NETWORK
1 kΩ 1%
-9V
V+
N/C
V-
5V
5V
EN
GND
GND
12
13
9
1+5 V
2
3
23
1 MΩ
1/2 W
24
TEST
1.5 kΩ
0.01 µF75µF / 1 kV
2
1
Bias resistor RBIAS should be located close to the pin and isolated
from other signals.
PM6044
DP8392
10 k Ω
DSQE (907A)
10 k Ω
F0.1 µ
F0.1µ
50 Ω
Optional: Centertap capacitor may improve EMC depending on board
layout and system design.
24.9 Ω 1%
24.9 Ω 1%
LXT907A
2
1
1:1
1:1
12.4 kΩ
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 27
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.6 AUI Encoder/Decoder Only
In th is application (Figure 15), the DTE is connected to a coaxial network through the AUI.
AUTOSEL is tied Low and PAUI is tied High to manu ally select the AUI por t . The twist e d-pair
port is not used. With MD1 and MD0 both Low, the logic and framing are set to Mode 1
(compati ble with AMD AM7990 co ntrolle rs ). The LI pin is tied Low, disa bling the link t est
functio n. The DSQE pin is also Lo w, ena bling the SQE func tion on the LXT907A. Th e L B K input
controls loopback . A 20 MHz system clock is supplied at CLK1, with CLK0 left open.
Figure 15. AUI Enco der/ De coder Only Application
LXT907A
TXD
RBIAS
GND2
GND1
TEN
TCLK
RCLK
RXD
CD
COL
LBK
AUTOSEL
NTH
MD0
MD1
DSQE (907A)
LI
JAB
PLR
TX
TENA
TCLK
RCLK
RX
RENA
CLSN
LBK
Red Red Red
AM7990 BACK-END/
CONTROLLER
INTERFACE
LOOPBACK
CONTROL
PROGRAMMING
OPTIONS
LINE STATUS
1 %
GREEN
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKI
330 330 330330
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 kΩ
CLKO
PAUI
Bias resistor RBIAS should be
located close to the pin an d
isolated from the other signals
20 MHz Left Open
SYSTEM
CLOCK
TEST 1
1
LXT901A/907A — Universal 3.3V Ethernet Transceiver
28 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
3.4.7 150Ω Shielded Twisted-Pair Only (LXT901A only)
Figure 1 6 s hows the LXT901A in a typical twisted-pair on ly applicat ion. The DTE is connected to
a 10 BASE-T net wo rk thr oug h th e twis ted -pa ir R J-45 con necto r. Not e th at the AUI po rt is not us ed.
With MD0 tied High and MD1 Low, the LXT901A lo gic and framing are set to Mode 2
(compa tible with Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the cry st al os cillator. (CLK 0 is left
open). The L 1 pin externa lly c ontrols the l ink tes t function. The STP and NTH pins are both tie d
Low, selecting the reduced receiver threshold and 150 Ω term ination for shielded twisted -pair
cable. The switch at LEDT/PDN manual ly c ontrols the powe r down mode.
Figure 16. 15 0 Ω Shielded Twisted-Pair Only Application (LXT901A)
LXT901A
TPIN 75 Ω
75 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
RBIAS
GND2GND1
PAUI
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
1 : 2
TEST
75 Ω 1%
37.5 Ω 1%
12.4 kΩ 1%
2
20 MHz
SYSTEM
CLOCK
82596
BACK-END/
CONTROLLER
INTERFACE
CLK0
RCLK
75 Ω 1%
37.5 Ω 1%
+3.3 V
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
1
10K
LINE STATUS
10K
Link Test E nable
PROGRAMMING
OPTIONS STP
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
CLK1
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
Left Ope n
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 29
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
4.0 Test Specifications
Note: Table 4 thr ough Table 13 and Figur e 1 7 th rough F igure 42 represen t th e perf ormance sp ecificat ion s
of the LXT901A/907A . The se specifications ar e guaranteed by test except where no ted “by
design.” Minimum and maxi mum values liste d in Table 6 through Table 13 apply ove r the
recommended operating conditions sp ecified in Table 5.
For all Quality and Reliability is sues (for example, parts packaging and thermal specif ications),
pleas e send your questions to Int el at the foll owing e-m ail addre ss: qr.requests@intel.com.
Table 4. Absolute Maximum V alues
Parameter Symbol Min Max Units
Supply voltage VCC -0.3 6 V
Storage temperature TSTG -65 +150 ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Ta bl e 5. Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Recommended supply voltage1VCC 3.13 3.3 3.47 V
Recommended operating temperature
(Commercial) TOP 0–+70 ºC
1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress
high frequency transients, consis tent with good PCB design.
Table 6. I/O Elec tri cal Characte ri stics
Parameter Sym Min Typ1Max Units Test Conditions
Input Low voltage2VIL ––0.8 V –
Input High voltage2VIH 2.0 ––V–
Output Low voltage VOL ––0.4 V IOL = 1.6 mA
VOL ––10 %VCC IOL < 10 µA
Output Low voltage
(Open drain LED driver) VOLL ––0.7 %VCC IOLL = 10 mA
Output High voltage VOH 2.4 ––VIOH = 40 µA
VOH 90 ––%VCC IOH < 10 µA
Output rise
time
TCLK & RCLK
CMOS ––712nsC
LOAD = 20 pF
TTL ––78ns –
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
LXT901A/907A — Universal 3.3V Ethernet Transceiver
30 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Output fall time
TCLK & RCLK CMOS ––712nsC
LOAD= 20 pF
TTL ––78ns –
CLKI rise time (externally driven) –––10 ns –
CLKI duty cycle (externally
driven) –– 40/60 % –
Supply current Normal Mode
ICC –65 85 mA Idle Mode
ICC –95 120 mA Transmitting on TP
ICC –95 120 mA Transmitting on
AUI
Pow er Down
Mode ICC –0.03 2 mA –
Table 7. AUI Electrical Characteristics
Parameter Symbol Min Typ1Max Units Test Conditions
Input Low current IIL ––-700 µA–
Input High current IIH ––500 µA–
Differential output voltage VOD ±550 –±1200 mV –
Differential squelch threshold VDS 150 250 350 mV 5 MHz square wave
input
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. TP Electrical Characteristics
Parameter Symbol Min Typ1Max Units Test Conditions
Transmit output impedance ZOUT –5– Ω–
Transmit timing jitter addition2––±3.3 ±10 ns 0 line length for
internal MAU
Transmit timing jitter added by the
MAU and PLS sections2, 3 ––±3.3 ±5.5 ns
After line model
specified by IEEE
802.3 for 10BASE-T
internal MAU
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Par ameter is guaranteed by design; not subject to production testing.
3. IEE E 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and
3.5 ns from the MAU.
Table 6. I/O Electrical Characteristics (Continued)
Parameter Sym Min Typ1Max Units Test Conditions
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. T he majority of functional tests are performed
at levels of 0V and 3V.
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 31
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Receive input impedance ZIN –20 –kΩBetween TPIP/TPIN,
CIP/CIN & DIP/DIN
Differential squelch
Threshold
Normal
threshol
d; NTH =
1VDS 300 400 585 mV 5 MHz square wave
input
Reduced
threshol
d; NTH =
0VDS 180 250 345 mV 5 MHz square wave
input
Table 9. Switch ing Characteristics
Parameter Symbol Minimum Typical1Maximum Units
Jabber Timing Maximum transmit time –20 –150 ms
Unjab time –250 –750 ms
Link Integrity
Timing
Time link loss receive –50 –150 ms
Link min receive –2–7ms
Link max receive –50 –150 ms
Link transmit period –81024ms
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Ta bl e 10 . RCLK/Start-of-Frame Timing
Parameter Symbol Minimum Typical1Maximum Units
Decoder acquisition
time AUI tDATA –900 1100 ns
TP tDATA –1200 1500 ns
CD turn-on delay AUI tCD –25 200 ns
TP tCD –425 550 ns
Receive data setup
from RCLK Mode 1 tRDS 60 70 –ns
Modes 2, 3 and 4 tRDS 30 45 –ns
Receive data hold
from RCLK Mode 1 tRDH 10 20 –ns
Modes 2, 3 and 4 tRDH 30 45 –ns
RCLK shut off delay from CD assert
(LXT907A only; Mode 3) tsws –±100 –ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. TP Electrical Characteristics (Continued)
Parameter Symbol Min Typ1Max Units Test Conditions
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and
3.5 ns from the MAU.
LXT901A/907A — Universal 3.3V Ethernet Transceiver
32 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Table 11. RCLK/End-of-Frame Timing
Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Units
RCLK after CD off Min tRC 51275BT
Rcv data throughput delay Max tRD 400 375 375 375 ns
CD turn off delay2Max tCDOFF 500 475 475 475 ns
Receive block out after TEN off Typ1tIFG 550––BT
RCLK switching delay after CD
off (LXT907A only; Mode 3) Typ1tSWE ––120(±80) –ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn- of f delay measured from middl e of las t bit: tim ing spec ific ation is unaf fected b y the va lue of the l ast
bit.
Table 12. Tra n sm it Tim in g
Parameter Symbol Minimum Typical1Maximum Units
TEN setup from TCLK tEHCH 22 ––ns
TXD setup from TCLK tDSCH 22 ––ns
TEN hold after TCLK tCHEL 5––ns
TXD hold after TCLK tCHDU 5––ns
Transmit start-up delay - AUI tSTUD –220 450 ns
Transmit start-up delay - TP tSTUD –430 450 ns
Transmit through-put delay - AUI t TPD ––300 ns
Transmit through-put delay - TP tTPD –300 350 ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Tab le 13. Collision, COL/ CI Output and Loopback Timing
Parameter Symbol Minimum Typical1Maximum Units
COL turn-on delay tCOLD –40 500 ns
COL turn-off delay tCOLOFF –420 500 ns
COL (SQE) Delay after TEN off t SQED 0.65 1.2 1.6 µs
COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns
LBK setup from TEN tKHEH 10 25 –ns
LBK hold after TEN tKHEL 10 0 –ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 33
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
4.1 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figures 17 - 22
Figure 17. Mode 1 RCLK/St a rt-of-Frame Timing
Figure 18. Mode 1 RCLK/ End -of -Frame Timing
11 0 1 0 1 0 1 0 1 1
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tDATA
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tRDS tRDH
0 1 0 0 0 1 0 1 0
1 0 1 0 1 0 1 0 0
1 01 0 1 0 1 00
tRD
tCDOFF
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tRC
LXT901A/907A — Universal 3.3V Ethernet Transceiver
34 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 19. Mode 1 Transmit Timing
Figure 20. Mode 1 Collisio n Detec t Timing
Figure 21. Mode 1 COL/CI Output Timing
Figure 22. Mode 1 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tTPD
tDSCH
tSTUD
t
COLOFF
t
COLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 35
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
4.2 Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)
Figures 23 - 28
Figure 23. Mode 2 RCLK/St a rt-of-Frame Timing
Figure 24. Mode 2 RCLK/ End -of -Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tRDS tRDH
CD
RCLK
RXD
tDATA
TPIP/TPIN
or DIP/DIN
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0
101010100
tRD
TPIP/TPIN
or DIP/D IN
CD
RCLK
RXD
1 01 0 1 0 1 00
tCDOFF
LXT901A/907A — Universal 3.3V Ethernet Transceiver
36 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 25. Mode 2 Transmit Timing
Figure 26. Mode 2 Collisio n Detec t Timing
Figure 27. Mode 2 COL/CI Output Timing
Figure 28. Mode 2 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tTPDtSTUD
tCOLOFFtCOLD
CI
COL
tSQED
TEN
COL
tIFG
tSQEP
tKHEL
tKHEH
LBK
TEN
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 37
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
4.3 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36
Figure 29. Mode 3 RCLK/St a rt-of-Frame Timing (LXT901A)
Figure 30. Mode 3 RCLK/ End -of -Frame Timing (LXT901A)
101010111010 1
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
11010101011 01000101
tCD
tRD
tCDOFF
CD
RCLK
RXD
1 0 1 0 1 0 1 0 0
TPIP/TPIN
or DIP/DIN
1 01 0 1 0 1 00
27 bits
LXT901A/907A — Universal 3.3V Ethernet Transceiver
38 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT90 7A )
Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907A)
1 0 1 0 1 0 1 1 1 01 0 1
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
11010101011 01000101
tCD
tSWS Recovered from Input Data Stream
Generated from TCLK
tRD
tCDOFF
CD
RCLK
RXD
tSWE
Recov ered Cl ock G ene rated from TCLK
1 0 1 0 1 0 1 0 0
TPIP/TPIN
or DIP/DIN
1 01 0 1 0 1 00
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 39
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 33. Mode 3 Tr ansmi t Timing
Figure 34. Mode 3 Collision Dete ct Timing
Figure 35. Mode 3 COL/CI Output Timing
Figure 36. Mode 3 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tSTUD
tDSCH
tTPD
tCOLOFF
tCOLD
CI
COL
tSQED
TEN
COL
tSQEP
tKHEL
tKHEH
LBK
TEN
LXT901A/907A — Universal 3.3V Ethernet Transceiver
40 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figur es 37 - 42
Figure 37. Mode 4 RCLK/Start-of-Frame Timing
Figure 38. Mode 4 RCLK/End-of-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
tRDS tRDH
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
1 0 1 0 1 0 1 0 0
1 01 0 1 0 1 00
tRD
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tCDOFF
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 41
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 39. Mode 4 Tr ansmi t Timing
Figure 40. Mode 4 Collision Dete ct Timing
Figure 41. Mode 4 COL/CI Output Timing
Figure 42. Mode 4 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tSTUD tTPD
tCOLOFF
tCOLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
LXT901A/907A — Universal 3.3V Ethernet Transceiver
42 Datasheet
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
5.0 Mechanical Specifications
Figure 43. 44 -Pi n PL CC
Dim Inches Millimeters
MinMaxMinMax
A 0.165 0.180 4.191 4.572
A10.090 0.120 2.286 3.048
A20.062 0.083 1.575 2.108
B 0.050 –1.270 –
C 0.026 0.032 0.660 0.813
D 0.685 0.695 17.399 17.653
D10.650 0.656 16.510 16.662
F 0.013 0.021 0.330 0.533
44-Pin Plastic Leaded Chip Carrier
•Part Number LXT901APC and LXT907APC (Commercial Temperature Range)
A
2
A
D
F
A
1
C
B
D
1
D
C
L
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 43
Document #: 249098
Revision #: 002
Rev. Date: June 19, 2001
Figure 44. 64-Pin LQFP
64-Pin Low-Profile Quad Fl at Package
•Part Number L XT 901ALC and LXT 907ALC (Commerc ia l Temperature Ra nge )
Dim Inches Millimeters
Min Max Min Max
A–0.063 –1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.007 .011 0.17 0.27
D 0.472 BSC 12.00 BSC
D1 0.394 BSC 10.00 BSC
E 0.472 BSC 12.00 BSC
E1 0.394 BSC 10.00 BSC
e 0.020 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
L1 0.039 REF 1.00 REF
θ311
o13o11o13o
θ0o7o0o7o
D
D1
A1
A2
L
A
B
L1
θ3
θ3
θ
E
E1
e/2
e
Universal 3.3V E thernet Transceiv er — L X T 901A/907A
Datasheet 45
Docu me nt #: 249098
Revision #: 002
Rev. D ate: June 19, 2001
Appendix A Ordering Info rmatio n
Ta bl e 14 . Product Information
Number Revision Qualificatio n Tray MM Tape & Reel MM
DJLXT901ALC.A4 A4 S 831684 831801
DJLXT907ALC.A4 A4 S 831647 831806
NLXT901APC.A4 A4 S 831653 831811
NLXT907APC.A4 A4 S 831664 831820
Figure 45. Ordering Information - Sample
Temperature Range
A
C
E
= Ambient (0 - 55° C)
= Commercial (0 - 70° C)
= Ext ended (-40 - +85° C)
Product Revision
xn = 2 Alphanumeric characters
Build Format
E000
E001 = Tray
= Tape and reel
DJ SA4CL901A
LXT E001
Internal Package Designator
L
P
N
Q
H
T
B
E
K
= LQFP
= PLCC
= DIP
= PQFP
= QFP with heat spreader
= TQFP
= BGA
= TBGA
= HSBGA (BGA wi th heat slug)
Qualification
Q
S= Pre-production material
= Production material
IXA Product Prefix
LXT
IXE
IXF
IXP
= PHY layer device
= Switching engine
= Formatting device (MAC)
= Network processor
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HG
S
GC
N
= LQFP
= TQFP
= PBGA (<1.0 m m pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= SOI C
= QFP
= TBGA
= PLCC
xxxx = 3-5 Digit Alphanumeric Product Code
