K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
Revision 1.4
December 2002
4Mx16
Mobile SDRAM
(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR)
52CSP
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
The K4S64163LF is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabri-
cated with SAMSUNG’s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. TCSR (Temperature Compenasted Self Refresh).
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Extended Temperature Operation (-25 °C ~ 85 °C).
• 52balls CSP (GXXX - Pb, AXXX - Pb Free)
GENERAL DESCRIPTIONFEATURES
1M x 16Bit x 4 Banks Mobile SDRAM in 52CSP
* Samsung Electronics reserves the right to change products or specification without notice.
Bank Select
Data Input Register
1M x 16
1M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row DecoderCol. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
1M x 16
1M x 16
Timing Register
ORDERING INFORMATION
-G(A)S ; Super Low Power, Operating Temp : -25 °C ~ 85 °C.
-G(A)G ; Low Power, Operating Temp : -25 °C ~ 85 °C.
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
Part No. Max Freq. Interface Package
K4S64163LF-G(A)G/S75 133MHz(CL=3)
105MHz(CL=2)
LVCMOS 52 CSP
Pb
(Pb Free)
K4S64163LF-G(A)G/S1H 105MHz(CL=2)
K4S64163LF-G(A)G/S1L 105MHz(CL=3)*1
K4S64163LF-G(A)G/S15 66MHz(CL=2/3)*2
FUNCTIONAL BLOCK DIAGRAM
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
Symbol Min Typ Max
A0.90 0.95 1.00
A1-0.35 -
E-6.60 -
E1-3.75 -
D-11.00 -
D1-9.0 -
e-0.75 -
b0.40 0.45 0.5
z- - 0.10
F
E
D
C
B
N
L
J
H
G
52Ball(4x13) CSP
1 2 5 6
AVss DQ15 DQ0 VDD
BDQ14 VSSQ VDDQ DQ1
CDQ13 VDDQ VSSQ DQ2
DDQ12 DQ11 DQ4 DQ3
EDQ10 VSSQ VDDQ DQ5
FDQ9 VDDQ VSSQ DQ6
GDQ8 VDD Vss DQ7
HCLK UDQM LDQM WE
JCKE CS RAS CAS
KA11 A9 BA1 BA0
LA8 A7 A0 A10
MA6 A5 A2 A1
NVss A4 A3 VDD
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A11 Address
BA0 ~ BA1Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0 ~ 15 Data Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
A
Package Dimension and Pin Configuration
M
K
< Bottom View*1 >
E1
5 2 16 34
e
D1
D
D/2
EE/2
#A1 Ball Origin Indicator
< Top View*2 >
< Top View*2 >
A
A1
bz
*1: Bottom View
*2: Top View
[Unit:mm]
Max. 0.20 Encapsulant
K4S64163LF
SEC Week XXXX
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85°C)
Notes :
1. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 2.3 2.5 2.7 V
VDDQ 1.65 -2.7 V
Input logic high voltage VIH 0.8 x VDDQ -VDDQ + 0.3 V1
Input logic low voltage VIL -0.3 00.3 V2
Output logic high voltage VOH VDDQ - 0.2V - - VIOH = -0.1mA
Output logic low voltage VOL - - 0.2 VIOL = 0.1mA
Input leakage current ILI -10 -10 uA 3
ABSOLUTE MAXIMUM RATINGS
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 3.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1W
Short circuit current IOS 50 mA
CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin Symbol Min Max Unit Note
Clock CCLK 2.0 4.0 pF
RAS, CAS, WE, CS, CKE, DQM CIN 2.0 4.0 pF
Address CADD 2.0 4.0 pF
DQ0 ~ DQ15 COUT 3.5 6.0 pF
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C)
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S64163LF-G(A)G**
4. K4S64163LF-G(A)S**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Parameter Symbol Test Condition Version Unit Note
-75 -1H -1L -15
Operating Current
(One Bank Active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 50 50 45 40 mA 1
Precharge Standby Current
in power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 0.5 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞0.5
Precharge Standby Current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 10
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 7
Active Standby Current
in power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 5mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞5
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 20 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 20 mA
Operating Current
(Burst Mode) ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
80 65 65 55 mA 1
Refresh Current ICC5 tRC ≥ tRC(min) 115 110 100 80 mA 2
Self Refresh Current ICC6 CKE ≤ 0.2V
TCSR Range Max 45
°
CMax 85
°
C
°
C
-G(A)G
4 Banks 235 350
uA
3
2 Banks 210 290
1 Bank 195 270
-G(A)S
4 Banks 130 230
4
2 Banks 105 170
1 Bank 90 150
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V, TA = -25° to 85°C)
Parameter Value Unit
AC input levels (Vih/Vil) 0.9 x VDDQ / 0.2 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Fig. 2
VDDQ
500Ω
500Ω
Output
30pF
Vtt=0.5 x VDDQ
50Ω
Output
30pF
Z0=50Ω
(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit
VOH (DC) = VDDQ-0.2V, IOH = -0.1mA
VOL (DC) = 0.2V, IOL = 0.1mA
OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter Symbol Version Unit Note
- 75 -1H -1L -15
Row active to row active delay tRRD(min) 15 19 19 30 ns 1
RAS to CAS delay tRCD(min) 19 19 24 30 ns 1
Row precharge time tRP(min) 19 19 24 30 ns 1
Row active time tRAS(min) 45 50 60 60 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 65 70 84 90 ns 1
Last data in to row precharge tRDL(min) 2CLK 2,3
Last data in to Active delay tDAL (min) tRDL + tRP -3
Last data in to new col. address delay tCDL(min) 1CLK 2
Last data in to burst stop tBDL(min) 1CLK 2
Col. address to col. address delay tCCD(min) 1CLK 4
Number of valid output data
CAS latency=3 2
ea 5
CAS latency=2 1
CAS latency=1 -0
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter Symbol - 75 -1H -1L - 15 Unit Note
Min Max Min Max Min Max Min Max
CLK cycle time
CAS latency=3
tCC
7.5
1000
9.5
1000
9.5
1000
15
1000 ns 1
CAS latency=2 9.5 9.5 12 15
CAS latency=1 - - 25 30
CLK to valid output delay
CAS latency=3
tSAC
5.4 7 7 9
ns 1,2
CAS latency=2 7 7 8 9
CAS latency=1 - - 20 24
Output data hold time
CAS latency=3
tOH
2.5 2.5 2.5 2.5
ns 2
CAS latency=2 2.5 2.5 2.5 2.5
CAS latency=1 - - 2.5 2.5
CLK high pulse width tCH 2.5 3 3 3.5 ns 3
CLK low pulse width tCL 2.5 3 3 3.5 ns 3
Input setup time tSS 2.0 2.5 2.5 3.5 ns 3
Input hold time tSH 1.0 1.5 1.5 2.0 ns 3
CLK to output in Low-Z tSLZ 1 1 1 1 ns 2
CLK to output in Hi-Z
CAS latency=3
tSHZ
5.4 7 7 9
ns
CAS latency=2 7 7 8 9
CAS latency=1 - - 20 24
Note :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is
potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product con-
tained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
K4S64163LF-G(A)G/S
Rev. 1.4 Dec. 2002
CMOS SDRAM
SIMPLIFIED TRUTH TABLE(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Note :
1. OP Code : Operand Code
A0 ~ A11 & BA 0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A 11,
A9 ~ A0Note
Register Mode Register Set HXL L L L XOP CODE 1, 2
Refresh
Auto Refresh HHLL LHX X 3
Self
Refresh
Entry L 3
Exit LHLH H H X X 3
HX X X 3
Bank Active & Row Addr. HXL L H H X V Row Address
Read &
Column Address Auto Precharge Disable HXLHLHX V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Write &
Column Address Auto Precharge Disable HXLHLLX V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Burst Stop HXLH H LX X 6
Precharge Bank Selection HXL L HLXVLX
All Banks XH
Clock Suspend or
Active Power Down Entry HLHX X X XXLV V V
Exit LHX X X X X
Precharge Power Down Mode
Entry HLHX X X X
X
LH H H
Exit LHHX X X X
LV V V
DQM HX V X 7
No Operation Command HXHX X X X X
LH H H
