L64108 - LSI Logic Corporation

L64108 Transport with Embedded CPU and Control

Overview

The L64108 combines a 32-bit 54 MHz RISC CPU, a programmable transport

demultiplexer, a DVB Descrambler, a DRAM controller and other peripherals

on a single chip. This versatile device interfaces to all of the other members of

the Integra™ 1100 set-top product family. This includes a serial or parallel

input from the L64724 satellite modem or the L64768 cable modem and an

output of multiplexed audio and video PES streams to the L64105 MPEG-2

A/V Decoder. The L64108 is suitable for worldwide use in DBS, CATV, or

telco set-top boxes.

Intelligence,Flexibility,Performance

The on-chip high performance CW4001 MiniRISC®32-bit RISC MIPS CPU

subsystem provides the set-top with intelligence, flexibility and performance.

The CPU subsystem includes 8 KB of instruction cache and 4 KB of data

cache to substantially enhance performance as well as timers and counters

that are needed by real-time operating systems. The powerful 54 MHz CPU is

capable of processing all of the set-top application and control needs. These

include complete set-top system initialization and testing, security handling,

communication ports protocol processing, remote control handling, PCR

recovery and locking, audio/video synchronization, subtitles, OSD overlay,

closed caption, teletext, and electronic program guide (EPG).

Features and Benefits

•ISO/IEC 13818-1 (MPEG-2) compliant trans-

port demultiplexer

-32 PIDs support

-Sustained input rate up to 60 Mbits/sec

serial and 9 Mbytes/sec parallel

-Extensive and fully programmable

hardware sec tion filtering scheme

-Robust error handling and recovery

-Support of a Program Clock Reference

(PCR) PID

-Automatic detecting and switching of

audio and video PIDs on splice points

•Integrated high per formance 54 MHz

CW4001 MiniRISC MIPS CPU

-Host CPU for set-top box;power ful enough

to also handle transport,graphics,ATM SAR

layer processing and other func tions

-4 KB Data (Direct Mapped);8 KB Instruction

(2-way set associative) Cache

-Timers,interrupt controller

-BBCC- Basic Bus and Cache Controller Unit

-Interfaces to external Set-top components

through Motorola 68K st yle ex tension bus

-MIPS-II instruction set compatible

•On-chip DVB,NDS,and Multi2-compliant

descramblers

-Support for transport-level and PES-level

descrambling

-Seamless suppor t of scrambled and

unscrambled data

-Support of up to 12 pairs of 64-bit keys

L64108 Block Diagram

L64108 Transport with Embedded CPU and Control

LSI Logic logo design, ATMized, ATMizer, BitBuster, CAS-

CADE, CoreWare and CoreWare logo design, FlexCore,

G10 and G10 logo design, GigaBlaze, HYDRA, Integra, It

Takes Two To Make One Of A Kind, Logically Speaking,

LSI Links, MiniRISC, MiniSIM, SeriaLink, The System on a

Chip Company and VISC are registered trademarks, and

Cablestream, Cafe, C-MDE, Compacted Array, Cream,

DCAM, DiscRISC, DiskRISK, Espresso, First-Time-Right,

FlexStream and FlexStream logo design, G11 and G11 logo

design, G12 and G12 logo design, Grounds, Hyper-LVDS,

HyperPHY, Internet on a Chip, Merlin, Mint, Mint

Technology, Mint logo design, Mocha, Netcore, Planet LSI,

PowerPlay, Right-First-Time, Scenario, SerialICE, Sugar,

Taking Cameras Digital, TinyRISC, TinySIM and WINS are

trademarks of LSI Logic Corporation. ARM is a registered

trademark of Advanced RISC Machines Limited, used under

license; OakDSPCore is a registered trademark of DSP

Group Inc., used under license; SparKIT is a trademark of

SPARC International, Inc. and is exclusively licensed to LSI

Logic Corporation. All other brand and product names may

be trademarks of their respective companies.

LSI Logic Corporation reserves the right to make changes to

any products and services herein at any time without notice.

LSI Logic does not assume any responsibility or liability aris-

ing out of the application or use of any product or service

described herein, except as expressly agreed to in writing by

LSI Logic; nor does the purchase, lease, or use of a product

or service from LSI Logic convey a license under any patent

rights, copyrights, trademark rights, or any other of the intel-

lectual property rights of LSI Logic or of third parties.

For more information please call:

U.S. 1.800.574.4286

Canada 1.800.574.4286

Europe +32.11.300.351

408.433.7700 Dept. JDS

www.lsilogic.com

LSI Logic Corporation

North American Headquarters

Milpitas, CA

Tel: 408.433.8000

Fax: 408.433.8989

LSI Logic Europe Ltd

European Headquarters

United Kingdom

Tel: 44.1344.426544

Fax: 44.1344.481039

LSI Logic KK Headquarters

Tokyo, Japan

Tel: 81.3.5463.7821

Fax: 81.3.5463.7820

Order No. 120054

1298.1K.CM.L – Printed in USA

ISO 9000 Certified

Intelligence,Flexibility,Performance (continued)

In addition, the CPU will support transport-related software processing

including handling operations such as PSI and DVB SI tables maintenance

and private section filtering.

Compatibility and Security

The Transport Demultiplexer with 32 PID (Packet ID) is MPEG-2, DVB- and

JSAT-compliant and features a very extensive hardware-assisted PSI section

filtering scheme. This functionality is not only a superset of the standard

MPEG-2 section filtering scheme but also covers worldwide service providers'

specific filtering requirements. The integration of the DVB descrambler block

into the chip substantially increases the security of the set-top box since the

interface to the descrambler is no longer observable at the board level. In

addition to the common DVB descrambler, L64108 has integrated NDS

(News Data Service) and Multi2 (required for Japanese Market) Conditional

Access Module.

The L64108 integrates several on-chip peripherals including three RS232 seri-

al communication ports, two SmartCard ports, an IEEE1284 parallel commu-

nication port, I2C-like serial communication port, a teletext port and general

purpose I/Os.

Features and Benefits

(Continued)

•DRAM controller with support for up to 16 Mbits

EDO/FPM DRAM

•On-chip Peripherals

-Three 8251-compatible serial ports (RS232)

-IEEE 1284 parallel port

-Two ISO7816 SmartCard interfaces

-I2C-compatible inter face por t supporting

multimaster or slave modes

-Teletext serial interface to NTSC/PAL

encoder

-Auxiliary (AUX) fast output port that can

output transport packets after PID filtering

or after descrambling

-50 General Purpose I/Os

•Support of direct inter face to LSI single-chip

channel decoder devices,such as the L64724 for

DBS and the L64768 for CATV

•A/V serial or parallel output for a direct interface to

the L64005 or L64105 MPEG-2 A/V decoder devices

•Supported by industr y-standard RTOS and software

vendors like Nucleus+,Integrated Systems (pSOS),

OpenTV and WindRiver Systems (VxWorks)

•Supported by Integra™ SDP1100 set-top box

hardware and soft ware development platform

•JTAG Support

•Uses low-power 0.35 micron,3.3 V process

•Packaged in 240-pin Plastic Quad Flat Package