MAX 10 FPGA Device Overview
2016.12.20
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MAX® 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate
the optimal set of system components.
e highlights of the MAX 10 devices include:
• Internally stored dual conguration ash
• User ash memory
• Instant on support
• Integrated analog-to-digital converters (ADCs)
• Single-chip Nios II so core processor support
MAX 10 devices are the ideal solution for system management, I/O expansion, communication control
planes, industrial, automotive, and consumer applications.
Related Information
MAX 10 FPGA Device Datasheet
Key Advantages of MAX 10 Devices
Table 1: Key Advantages of MAX 10 Devices
Advantage Supporting Feature
Simple and fast conguration Secure on-die ash memory enables device conguration in
less than 10 ms
Flexibility and integration • Single device integrating PLD logic, RAM, ash memory,
digital signal processing (DSP), ADC, phase-locked loop
(PLL), and I/Os
• Small packages available from 3 mm × 3 mm
Low power • Sleep mode—signicant standby power reduction and
resumption in less than 1 ms
• Longer battery life—resumption from full power-o in
less than 10 ms
20-year-estimated life cycle Built on TSMC's 55 nm embedded ash process technology
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, NIOS, Quartus and Stratix words and logos are
trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Advantage Supporting Feature
High productivity design tools • Quartus® Prime Lite edition (no cost license)
• Qsys system integration tool
• Digital Signal Processing (DSP) Builder
• Nios® II Embedded Design Suite (EDS)
Summary of MAX 10 Device Features
Table 2: Summary of Features for MAX 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process
technology
Packaging • Low cost, small form factor packages—support multiple
packaging technologies and pin pitches
• Multiple device densities with compatible package footprints
for seamless migration between dierent device densities
• RoHS6-compliant
Core architecture • 4-input look-up table (LUT) and single register logic element
(LE)
• LEs arranged in logic array block (LAB)
• Embedded RAM and user ash memory
• Clocks and PLLs
• Embedded multiplier blocks
• General purpose I/Os
Internal memory blocks • M9K—9 kilobits (Kb) memory blocks
• Cascadable blocks to create RAM, dual port, and FIFO
functions
User ash memory (UFM) • User accessible non-volatile storage
• High speed operating frequency
• Large memory size
• High data retention
• Multiple interface option
Embedded multiplier blocks • One 18 × 18 or two 9 × 9 multiplier modes
• Cascadable blocks enabling creation of lters, arithmetic
functions, and image processing pipelines
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Feature Description
ADC • 12-bit successive approximation register (SAR) type
• Up to 17 analog inputs
• Cumulative speed up to 1 million samples per second ( MSPS)
• Integrated temperature sensing capability
Clock networks • Global clocks support
• High speed frequency in clock network
Internal oscillator Built-in internal ring oscillator
PLLs • Analog-based
• Low jitter
• High precision clock synthesis
• Clock delay compensation
• Zero delay buering
• Multiple output taps
General-purpose I/Os (GPIOs) • Multiple I/O standards support
• On-chip termination (OCT)
• Up to 830 megabits per second (Mbps) LVDS receiver,
800 Mbps LVDS transmitter
External memory interface (EMIF) (1) Supports up to 600 Mbps external memory interfaces:
• DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40,
and 10M50.)
• SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is
required. Performance varies according to device
grade (commercial, industrial, or automotive) and
device speed grade (–6 or –7). Refer to the MAX 10
Device Data Sheet or External Memory Interface Spec
Estimator for more details.
Conguration • Internal conguration
• JTAG
• Advanced Encryption Standard (AES) 128-bit encryption and
compression options
• Flash memory data retention of 20 years at 85 °C
(1) EMIF is only supported in selected MAX 10 device density and package combinations. Refer to the External
Memory Interface User Guide for more information.
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Feature Description
Flexible power supply schemes • Single- and dual-supply device options
• Dynamically controlled input buer power down
• Sleep mode for dynamic power reduction
MAX 10 Device Ordering Information
Figure 1: Sample Ordering Code and Available Options for MAX 10 Devices
V : Wafer-Level Chip Scale (WLCSP)
E : Plastic Enhanced Quad Flat Pack (EQFP)
M : Micro FineLine BGA (MBGA)
U : Ultra FineLine BGA (UBGA)
F : FineLine BGA (FBGA)
Family Signature
Package Type
WLCSP Package Type
36 : 36 pins, 3 mm x 3 mm
81 : 81 pins, 4 mm x 4 mm
EQFP Package Type
144 : 144 pins, 22 mm x 22 mm
UBGA Package Type
169 : 169 pins, 11 mm x 11 mm
324 : 324 pins, 15 mm x 15 mm
FBGA Package Type
256 : 256 pins, 17 mm x 17 mm
484 : 484 pins, 23 mm x 23 mm
672 : 672 pins, 27 mm x 27 mm
MBGA Package Type
153 : 153 pins, 8 mm x 8 mm
Package Code
Operating Temperature
FPGA Fabric
Speed Grade Optional Suffix
Indicates specific device
options or shipment method
6 (fastest)
7
8
10M 16 DA U 484 I 7 G
SC : Single supply - compact features
:
:
:
:
SA : Single supply - analog and flash features
with RSU option
DC Dual supply - compact features
DF Dual supply - flash features with RSU option
DA Dual supply - analog and flash features
with RSU option
Feature Options
02 : 2K logic elements
04 : 4K logic elements
08 : 8K logic elements
16 : 16K logic elements
25 : 25K logic elements
40 : 40K logic elements
50 : 50K logic elements
Member Code
10M : MAX 10
G : RoHS6
ES : Engineering sample
P : Leaded package
C : Commercial (T = 0° C to 85° C)
I : Industrial (T = - 40° C to 100° C)
A : Automotive (T = - 40° C to 125° C)
J
J
J
Note: e –I6 and –A6 speed grades of the MAX 10 FPGA devices are not available by default in the
Quartus Prime soware. Contact your local Altera sales representatives for support.
Related Information
Altera Product Selector
Provides the latest information about Altera products.
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MAX 10 Device Feature Options
Table 3: Feature Options for MAX 10 Devices
Option Feature
Compact Devices with core architecture featuring single conguration image with self-congu‐
ration capability
Flash Devices with core architecture featuring:
• Dual conguration image with self-conguration capability
• Remote system upgrade capability
• Memory initialization
Analog Devices with core architecture featuring:
• Dual conguration image with self-conguration capability
• Remote system upgrade capability
• Memory initialization
• Integrated ADC
MAX 10 Device Maximum Resources
Table 4: Maximum Resource Counts for MAX 10 Devices
Resource
Device
10M02 10M04 10M08 10M16 10M25 10M40 10M50
Logic Elements (LE) (K) 2 4 8 16 25 40 50
M9K Memory (Kb) 108 189 378 549 675 1,260 1,638
User Flash Memory
(Kb) (2)
96 1,248 1,376 2,368 3,200 5,888 5,888
18 × 18 Multiplier 16 20 24 45 55 125 144
PLL 2 2 2 4 4 4 4
GPIO 160 246 250 320 360 500 500
LVDS
Dedicated
Transmitter
9 15 15 22 24 30 30
Emulated
Transmitter
73 114 116 151 171 241 241
Dedicated
Receiver
73 114 116 151 171 241 241
(2) e maximum possible value including user ash memory and conguration ash memory. For more
information, refer to MAX 10 User Flash Memory User Guide.
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Resource
Device
10M02 10M04 10M08 10M16 10M25 10M40 10M50
Internal Conguration
Image
1 2 2 2 2 2 2
ADC — 1 1 1 2 2 2
MAX 10 Devices I/O Resources Per Package
Table 5: Package Plan for MAX 10 Single Power Supply Devices
Device
Package
Type M153
153-pin MBGA
U169
169-pin UBGA
E144
144-pin EQFP
Size 8 mm × 8 mm 11 mm × 11 mm 22 mm × 22 mm
Ball Pitch 0.5 mm 0.8 mm 0.5 mm
10M02 112 130 101
10M04 112 130 101
10M08 112 130 101
10M16 — 130 101
10M25 — — 101
10M40 — — 101
10M50 — — 101
Table 6: Package Plan for MAX 10 Dual Power Supply Devices
Device
Package
Type V36
36-pin
WLCSP
V81
81-pin
WLCSP
U324
324-pin
UBGA
F256
256-pin
FBGA
F484
484-pin
FBGA
F672
672-pin FBGA
Size 3 mm × 3
mm
4 mm × 4
mm
15 mm × 15
mm
17 mm × 17
mm
23 mm × 23
mm
27 mm × 27 mm
Ball
Pitch
0.4 mm 0.4 mm 0.8 mm 1.0 mm 1.0 mm 1.0 mm
10M02 27 — 160 — — —
10M04 — — 246 178 — —
10M08 — 56 246 178 250 —
10M16 — — 246 178 320 —
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Device
Package
Type V36
36-pin
WLCSP
V81
81-pin
WLCSP
U324
324-pin
UBGA
F256
256-pin
FBGA
F484
484-pin
FBGA
F672
672-pin FBGA
Size 3 mm × 3
mm
4 mm × 4
mm
15 mm × 15
mm
17 mm × 17
mm
23 mm × 23
mm
27 mm × 27 mm
Ball
Pitch
0.4 mm 0.4 mm 0.8 mm 1.0 mm 1.0 mm 1.0 mm
10M25 — — — 178 360 —
10M40 — — — 178 360 500
10M50 — — — 178 360 500
Related Information
•MAX 10 General Purpose I/O User Guide
•MAX 10 High-Speed LVDS I/O User Guide
MAX 10 Vertical Migration Support
Vertical migration supports the migration of your design to other MAX 10 devices of dierent densities in
the same package with similar I/O and ADC resources.
MAX 10 I/O Vertical Migration Support
Figure 2: Migration Capability Across MAX 10 Devices
•e arrows indicate the migration paths. e devices included in each vertical migration path are
shaded. Some packages have several migration paths. Devices with lesser I/O resources in the same
path have lighter shades.
• To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to
match the product line with the lowest I/O count.
Device
Package
V36 V81 M153 U169 U324 F256 E144 F484 F672
10M02
10M04
10M08
10M16
10M25
10M40
10M50
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Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus
Prime soware Pin Planner.
MAX 10 ADC Vertical Migration Support
Figure 3: ADC Vertical Migration Across MAX 10 Devices
e arrows indicate the ADC migration paths. e devices included in each vertical migration path are
shaded.
Device
Package
M153 U169 U324 F256 E144 F484 F672
10M04
10M08
10M16
10M25
10M40
10M50
Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.
Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 16 dual function pins.
Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 8 dual function pins.
Table 7: Pin Migration Conditions for ADC Migration
Source Target Migratable Pins
Single ADC device Single ADC device You can migrate all ADC input pins
Dual ADC device Dual ADC device
Single ADC device Dual ADC device • One dedicated analog input pin.
• Eight dual function pins from the ADC1
block of the source device to the ADC1
block of the target device.
Dual ADC device Single ADC device
Logic Elements and Logic Array Blocks
e LAB consists of 16 logic elements and a LAB-wide control block. An LE is the smallest unit of logic in
the MAX 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and
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output logic. e four-input LUT is a function generator that can implement any function with four
variables.
Figure 4: MAX 10 Device Family LEs
Row, Column,
And Direct Link
Routing
data 1
data 2
data 3
data 4
labclr1
labclr2
Chip-Wide
Reset
(DEV_CLRn)
labclk1
labclk2
labclkena1
labclkena2
LE Carry-In
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
Row, Column,
And Direct Link
Routing
Local
Routing
Register Chain
Output
Register Bypass
Programmable
Register
Register Chain
Routing from
previous LE
LE Carry-Out
Register Feedback
Synchronous
Load and
Clear Logic
Carry
Chain
Look-Up Table
(LUT)
Asynchronous
Clear Logic
Clock &
Clock Enable
Select
DQ
ENA
CLRN
Analog-to-Digital Converter
MAX 10 devices feature up to two ADCs. You can use the ADCs to monitor many dierent signals,
including on-chip temperature.
Table 8: ADC Features
Feature Description
12-bit resolution • Translates analog signal to digital data for information
processing, computing, data transmission, and control
systems
• Provides a 12-bit digital representation of the observed
analog signal
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Feature Description
Up to 1 MSPS sampling rate Monitors single-ended external inputs with a cumulative
sampling rate of 25 kilosamples per second to 1 MSPS in
normal mode
Up to 17 single-ended external inputs for
single ADC devices
One dedicated analog and 16 dual function input pins
Up to 18 single-ended external inputs for
dual ADC devices • One dedicated analog and eight dual-function input pins
in each ADC block
• Simultaneous measurement capability for dual ADC
devices
On-chip temperature sensor Monitors external temperature data input with a sampling
rate of up to 50 kilosamples per second
User Flash Memory
e user ash memory (UFM) block in MAX 10 devices stores non-volatile information.
UFM provides an ideal storage solution that you can access using Avalon Memory-Mapped (Avalon-MM)
slave interface protocol.
Table 9: UFM Features
Features Capacity
Endurance Counts to at least 10,000 program/erase cycles
Data retention • 20 years at 85 ºC
• 10 years at 100 ºC
Operating frequency Maximum 116 MHz for parallel interface and 7.25
MHz for serial interface
Data length Stores data up to 32 bits length in parallel
Embedded Multipliers and Digital Signal Processing Support
MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports one individual
18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.
With the combination of on-chip resources and external interfaces in MAX 10 devices, you can build DSP
systems with high performance, low system cost, and low power consumption.
You can use the MAX 10 device on its own or as a DSP device co-processor to improve price-to-perform‐
ance ratios of DSP systems.
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You can control the operation of the embedded multiplier blocks using the following options:
• Parameterize the relevant IP cores with the Quartus Prime parameter editor
• Infer the multipliers directly with VHDL or Verilog HDL
System design features provided for MAX 10 devices:
• DSP IP cores:
• Common DSP processing functions such as nite impulse response (FIR), fast Fourier transform
(FFT), and numerically controlled oscillator (NCO) functions
• Suites of common video and image processing functions
• Complete reference designs for end-market applications
• DSP Builder interface tool between the Quartus Prime soware and the MathWorks Simulink and
MATLAB design environments
• DSP development kits
Embedded Memory Blocks
e embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of
a MAX 10 device provides 9 Kb of on-chip memory capable of operating at up to 284 MHz.
You can congure the M9K memory blocks as RAM, FIFO buers, or ROM.
e MAX 10 device memory blocks are optimized for applications such as high throughput packet
processing, embedded processor program, and embedded data storage.
Table 10: M9K Operation Modes and Port Widths
Operation Modes Port Widths
Single port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
Simple dual port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
True dual port ×1, ×2, ×4, ×8, ×9, ×16, and ×18
Clocking and PLL
MAX 10 devices oer the following resources: global clock (GCLK) networks and phase-locked loops
(PLLs) with a 116-MHz built-in oscillator.
MAX 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to
450 MHz. e GCLK networks have high drive strength and low skew.
e PLLs provide robust clock management and synthesis for device clock management, external system
clock management, and I/O interface clocking. e high precision and low jitter PLLs oers the following
features:
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• Reduction in the number of oscillators required on the board
• Reduction in the device clock pins through multiple clock frequency synthesis from a single reference
clock source
• Frequency synthesis
• On-chip clock de-skew
• Jitter attenuation
• Dynamic phase-shi
• Zero delay buer
• Counter reconguration
• Bandwidth reconguration
• Programmable output duty cycle
• PLL cascading
• Reference clock switchover
• Driving of the ADC block
FPGA General Purpose I/O
e MAX 10 I/O buers support a range of programmable features.
ese features increase the exibility of I/O utilization and provide an alternative to reduce the usage of
external discrete components such as a pull-up resistor and a PCI clamp diode.
External Memory Interface
Dual-supply MAX 10 devices feature external memory interfaces solution that uses the I/O elements on
the right side of the devices together with the UniPHY IP.
With this solution, you can create external memory interfaces to 16-bit SDRAM components with error
correction coding (ECC).
Note: e external memory interface feature is available only for dual-supply MAX 10 devices.
Table 11: External Memory Interface Performance
External Memory Interface(3) I/O Standard Maximum Width Maximum Frequency (MHz)
DDR3 SDRAM SSTL-15 16 bit + 8 bit ECC 303
DDR3L SDRAM SSTL-135 16 bit + 8 bit ECC 303
DDR2 SDRAM SSTL-18 16 bit + 8 bit ECC 200
LPDDR2 SDRAM HSUL-12 16 bit without ECC 200(4)
(3) e device hardware supports SRAM. Use your own design to interface with SRAM devices.
(4) To achieve the specied performance, constrain the memory device I/O and core power supply variation to
within ±3%. By default, the frequency is 167 MHz.
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Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to nd and compare the performance of the supported external
memory interfaces in Altera devices.
Conguration
Table 12: Conguration Features
Feature Description
Dual conguration • Stores two conguration images in the conguration ash memory
(CFM)
• Selects the rst conguration image to load using the CONFIG_SEL
pin
Design security • Supports 128-bit key with non-volatile key programming
• Limits access of the JTAG instruction during power-up in the JTAG
secure mode
• Unique device ID for each MAX 10 device
SEU Mitigation • Auto-detects cyclic redundancy check (CRC) errors during congu‐
ration
• Provides optional CRC error detection and identication in user
mode
Dual-purpose conguration pin • Functions as conguration pins prior to user mode
• Provides options to be used as conguration pin or user I/O pin in
user mode
Conguration data compression • Decompresses the compressed conguration bitstream data in real-
time during conguration
• Reduces the size of conguration image stored in the CFM
Instant-on Provides the fastest power-up mode for MAX 10 devices.
Table 13: Conguration Schemes for MAX 10 Devices
Conguration Scheme Compression Encryption Dual Image
Conguration
Data Width
Internal Conguration Yes Yes Yes —
JTAG — — — 1
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Power Management
Table 14: Power Options
Power Options Advantage
Single-supply device Saves board space and costs.
Dual-supply device • Consumes less power
•Oers higher performance
Power management controller
scheme • Reduces dynamic power consumption when certain applications are
in standby mode
• Provides a fast wake-up time of less than 1 ms.
Document Revision History for MAX 10 FPGA Device Overview
Date Version Changes
December 2016 2016.12.20 • Updated EMIF information in the Summary of Features for MAX 10
Devices table. EMIF is only supported in selected MAX 10 device
density and package combinations, and for 600 Mbps performance,
–6 device speed grade is required.
• Updated the device ordering information to include P for leaded
package.
May 2016 2016.05.02 • Removed all preliminary marks.
• Update the ADC sampling rate description. e ADC feature
monitors single-ended external inputs with a cumulative sampling
rate of 25 kilosamples per second to 1 MSPS in normal mode.
November 2015 2015.11.02 • Removed SF feature from the device ordering information gure.
• Changed instances of Quartus II to Quartus Prime.
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Date Version Changes
May 2015 2015.05.04 • Added clearer descriptions for the feature options listed in the
device ordering information gure.
• Updated the maximum dedicated LVDS transmitter count of
10M02 device from 10 to 9.
• Removed the F672 package of the MAX 10 10M25 device :
• Updated the devices I/O resources per package.
• Updated the I/O vertical migration support.
• Updated the ADC vertical migration support.
• Updated the maximum resources for 10M25 device:
• Maximum GPIO from 380 to 360.
• Maximum dedicated LVDS transmitter from 26 to 24.
• Maximum emulated LVDS transmitter from 181 to 171.
• Maximum dedicated LVDS receiver from 181 to 171.
• Added ADC information for the E144 package of the 10M04
device.
• Updated the ADC vertical migration diagram to clarify that there
are single ADC devices with eight and 16 dual function pins.
• Removed the note about contacting Altera for DDR3, DDR3L,
DDR2, and LPDDR2 external memory interface support. e
Quartus Prime soware supports these external memory interfaces
from version 15.0.
December 2014 2014.12.15 • Changed terms:
• "dual image" to "dual conguration image"
• "dual-image conguration" to dual conguration"
• Added memory initialization feature for Flash and Analog devices.
• Added maximum data retention capacity of up to 20 years for UFM
feature.
• Added maximum operating frequency of 7.25 MHz for serial
interface for UFM feature.
September 2014 2014.09.22 Initial release.
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10M02SCM153C8G 10M08SAM153C8G 10M04SAE144I7G 10M04SAM153C8G 10M50DAF484C8G
10M02SCU169A7G 10M02SCE144I7G 10M04DAF256I7G 10M04SCE144A7G 10M04DCF256I7G
10M08DCU324I7G 10M04DCU324C8G 10M04DCU324I7G
