NCV3020BDR2G - ON Semiconductor

June, 2011 − Rev. 5

1Publication Order Number:

NCP3020/D

NCP3020A, NCP3020B,

NCV3020A, NCV3020B

Synchronous PWM Controller

The NCP3020 is a PWM device designed to operate from a wide

input range and is capable of producing an output voltage as low as

0.6 V. The NCP3020 provides integrated gate drivers and an internally

set 300 kHz (NCP3020A) or 600 kHz (NCP3020B) oscillator. The

NCP3020 also has an externally compensated transconductance error

amplifier with an internally fixed soft−start. Protection features

include lossless current limit and short circuit protection, output

overvoltage protection, output undervoltage protection, and input

undervoltage lockout. The NCP3020 is currently available in a

SOIC−8 package.

Features

•Input Voltage Range from 4.7 V to 28 V

•300 kHz Operation (NCP3020B – 600 kHz)

•0.6 V Internal Reference Voltage

•Internally Programmed 6.8 ms Soft−Start (NCP3020B – 4.4 ms)

•Current Limit and Short Circuit Protection

•Transconductance Amplifier with External Compensation

•Input Undervoltage Lockout

•Output Overvoltage and Undervoltage Detection

•NCV Prefix for Automotive and Other Applications Requiring Site

and Change Controls

•This is a Pb−Free Device

Figure 1. Typical Application Circuit

COMP

VCC BST

HSDR

VSW

LSDR

GND

Vout

CC1

CC2

CIN

RISET

CBST

RFB1

RFB2

VIN

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Device Package Shipping†

ORDERING INFORMATION

NCP3020ADR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

SOIC−8 NB

CASE 751

MARKING DIAGRAM

3020x

ALYW

3020x = Specific Device Code

x = A or B

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

PIN CONNECTIONS

LSDRGND

VSWFB

HSDRCOMP

BST

VCC

NCP3020BDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCV3020ADR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCV3020BDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP3020A, NCP3020B, NCV3020A, NCV3020B

http://onsemi.com

GATE

DRIVE

LOGIC

CLK/

DMAX/

SOFT

START

OOV

BOOST

CLAMP

LEVEL

SHIFT

SAMPLE &

HOLD

HSDR

LSDR

GND

−

VCC

COMP

REF

RAMP

OSCILLATOR

BST

VSW

VCC

Figure 2. NCP3020 Block Diagram

INTERNAL BIAS

ISET

1.5 V

BST_CHRG

THERMAL SD

POR/STARTUP

OTA

PWM

COMP

OUV

CURRENT

LIMIT

PIN FUNCTION DESCRIPTION

Pin Pin Name Description

1 VCC The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current

in the high side MOSFET.

2 COMP The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive

terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage

mode control feedback loop.

3 FB The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to

compensate the voltage mode control feedback loop.

4 GND Ground Pin

5 LSDR The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side

N−FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR

to GND.

6 VSW The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense

current in the high side MOSFET.

7 HSDR The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side

N−FET.

8 BST The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the

VSW pin.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted)

Rating Symbol VMAX VMIN Unit

High Side Drive Boost Pin BST 45 −0.3 V

Boost to VSW differential voltage BST−VSW 13.2 −0.3 V

COMP COMP 5.5 −0.3 V

Feedback FB 5.5 −0.3 V

High−Side Driver Output HSDR 40 −0.3 V

Low−Side Driver Output LSDR 13.2 −0.3 V

Main Supply Voltage Input VCC 40 −0.3 V

Switch Node Voltage VSW 40 −0.6 V

Maximum Average Current

VCC, BST, HSDRV, LSDRV, VSW, GND

Imax 130

Operating Junction Temperature Range (Note 1) TJ−40 to +140 °C

Maximum Junction Temperature TJ(MAX) +150 °C

Storage Temperature Range Tstg −55 to +150 °C

Thermal Characteristics (Note 2)

SOIC−8 Plastic Package

Thermal Resistance Junction−to−Air RqJA 165 °C/W

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free

(Note 3)

RF260 Peak °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The maximum package power dissipation limit must not be exceeded.

PD+

TJ(max) *TA

RqJA

2. When mounted on minimum recommended FR−4 or G−10 board

3. 60−180 seconds minimum above 237°C.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)

Characteristic Conditions Min Typ Max Unit

Input Voltage Range −4.7 28 V

SUPPLY CURRENT

VCC Supply Current NCP3020A VFB = 0.55 V, Switching, VCC = 4.7 V −5.5 8.0 mA

VFB = 0.55 V, Switching, VCC = 28 V −7.0 11 mA

VCC Supply Current NCP3020B VFB = 0.55 V, Switching, VCC = 4.7 V −5.9 10 mA

VFB = 0.55 V, Switching, VCC = 28 V −7.8 13 mA

UNDER VOLTAGE LOCKOUT

UVLO Rising Threshold VCC Rising Edge 4.0 4.3 4.7 V

UVLO Falling Threshold VCC Falling Edge 3.5 3.9 4.3 V

OSCILLATOR

Oscillator Frequency NCP3020A TJ = +25°C, 4.7 V v VCC v 28 V 250 300 350 kHz

TJ = −40°C to +125°C, 4.7 V v VCC v 28 V 240 300 360 kHz

Oscillator Frequency NCP3020B TJ = +25°C, 4.7 V v VCC v 28 V 550 600 650 kHz

TJ = −40°C to +125°C, 4.7 V v VCC v 28 V 530 600 670 kHz

Ramp−Amplitude Voltage Vpeak − Valley (Note 4) −1.5 −V

Ramp Valley Voltage 0.46 0.70 0.88 V

PWM

Minimum Duty Cycle (Note 4) −7.0 −%

Maximum Duty Cycle NCP3020A

NCP3020B

−

Soft Start Ramp Time NCP3020A

NCP3020B

VFB = VCOMP −

−

6.8

4.4

−

ERROR AMPLIFIER (GM)

Transconductance 0.9 1.4 1.9 mS

Open Loop dc Gain (Notes 4 and 6) −70 −dB

Output Source Current VFB = 545 mV 45 75 100 mA

Output Sink Current VFB = 655 mV 45 75 100 mA

FB Input Bias Current −0.5 500 nA

Feedback Voltage TJ = 25 C

4.7 V < VCC < VIN < 28 V, −40°C < TJ < +125°C

0.591

0.588

0.6

0.609

0.612

COMP High Voltage VFB = 0.55 V 4.0 4.4 5.0 V

COMP Low Voltage VFB = 0.65 V −72 250 mV

OUTPUT VOLTAGE FAULTS

Feedback OOV Threshold 0.66 0.75 0.84 V

Feedback OUV Threshold 0.42 0.45 0.48 V

OVERCURRENT

ISET Source Current 7.0 13 18 mA

Current Limit Set Voltage (Note 5) RSET = 22.5 kW140 240 360 mV

4. Guaranteed by design.

5. The voltage sensed across the high side MOSFET during conduction.

6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW.

7. This is not a protection feature.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)

Characteristic UnitMaxTypMinConditions

GATE DRIVERS AND BOOST CLAMP

HSDRV Pullup Resistance VCC = 8 V, VBST = 7.5 V, VSW = GND

100 mA out of HSDR pin

5.0 11 20 W

HSDRV Pulldown Resistance VCC = 8 V, VBST = 7.5 V, VSW = GND

100 mA into HSDR pin

2.0 5.0 11.5 W

LSDRV Pullup Resistance VCC = 8 V, VBST = 7.5 V, VSW = GND

100 mA out of LSDR pin

5.0 9.0 16 W

LSDRV Pulldown Resistance VCC = 8 V, VBST = 7.5 V, VSW = GND

100 mA into LSDR pin

1.0 3.0 6.0 W

HSDRV Falling to LSDRV Rising

Delay

VIN = 12 V, VSW = GND, VCOMP = 1.3 V 50 80 110 ns

LSDRV Falling to HSDRV Rising

Delay

VIN = 12 V, VSW = GND, VCOMP = 1.3 V 60 80 120 ns

Boost Clamp Voltage VIN = 12 V, VSW = GND, VCOMP = 1.3 V 5.5 7.5 9.6 V

THERMAL SHUTDOWN

Thermal Shutdown (Notes 4 and 7) −165 −°C

Hysteresis (Notes 4 and 7) −20 −°C

4. Guaranteed by design.

5. The voltage sensed across the high side MOSFET during conduction.

6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW.

7. This is not a protection feature.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. Efficiency vs. Output Current and Input

Voltage

Figure 4. Load Regulation vs. Input Voltage

Figure 5. Switching Waveforms (VIN = 9 V) Figure 6. Switching Waveforms (VIN = 18 V)

Figure 7. Feedback Reference Voltage vs. Input

Voltage and Temperature

Figure 8. Switching Frequency vs. Input Voltage

and Temperature (NCP3020A)

Iout (A)

106420

EFFICIENCY (%)

Iout (A)

106420

3.25

3.255

3.26

3.265

3.27

3.275

3.28

Vout (V)

TEMPERATURE (°C)

125110505−40

594

596

598

600

602

604

606

VFB (mV)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

TEMPERATURE (°C)

125110505−40

260

270

280

290

300

310

320

fSW (kHz)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

330

340

VCC = 5 V

18 V

15 V

12 V

9 V

18 V

15 V

12 V

9 V

VCC = 5 V

Typical Application Circuit

Figure 37

Typical Application Circuit

Figure 37

NCP3020A

Input = 9 V, Output = 3.3 V, Load = 10 A

C4 (Green) = VIN, C2 (Red) = VOUT

C1 (Yellow) = VSW, C3 (Blue) = HSDR

Input = 18 V, Output = 3.3 V, Load = 10 A

C4 (Green) = VIN, C2 (Red) = VOUT

C1 (Yellow) = VSW, C3 (Blue) = HSDR

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. Switching Frequency vs. Input Voltage

and Temperature (NCP3020B)

Figure 10. Transconductance vs. Input Voltage

and Temperature

Figure 11. Input Undervoltage Lockout vs.

Temperature

Figure 12. Output Overvoltage and Undervoltage

vs. Input Voltage and Temperature

Figure 13. Supply Current vs. Input Voltage and

Temperature (NCP3020A)

Figure 14. Supply Current vs. Input Voltage and

Temperature (NCP3020B)

TEMPERATURE (°C)

125110505−40

540

560

580

600

620

640

660

fSW (kHz)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

VCC = 5 V

TEMPERATURE (°C)

125110505−40

1.00

1.05

1.10

1.15

1.20

1.25

1.30

gm (mS)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

VCC = 5 V

1.35

1.40

1.45

1.50

TEMPERATURE (°C)

125110505−40

3.8

3.9

4.0

4.1

4.2

4.3

4.4

UVLO (V)

UVLO Rising

−25 −10 20 35 65 80 95

TEMPERATURE (°C)

125110505−40

400

440

480

520

560

600

640

THRESHOLD VOLTAGE (mV)

−25 −10 20 35 65 80 95

680

720

760

800

UVLO Falling

OOV, VCC = 5 − 28 V

OUV, VCC = 5 − 28 V

TEMPERATURE (°C)

125110505−40

4.0

4.5

5.0

5.5

6.0

6.5

7.5

ICC, SWITCHING (mA)

VCC = 28 V

−25 −10 20 35 65 80 95

7.0

VCC = 12 V

VCC = 5 V

NCP3020A

NCP3020B

TEMPERATURE (°C)

125110505−40

5.0

5.5

6.0

6.5

7.0

7.5

9.0

ICC, SWITCHING (mA)

−25 −10 20 35 65 80 95

8.0

8.5

VCC = 28 V

VCC = 4.7 V

NCP3020B

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. Ramp Valley Voltage vs. Input Voltage

and Temperature

Figure 16. Soft−Start Time vs. Input Voltage and

Temperature

Figure 17. Current Limit Set Current vs.

Temperature

Figure 18. Soft−Start Waveforms

Figure 19. Shutdown Waveforms Figure 20. Startup into a Current Limit

TEMPERATURE (°C)

125110505−40

400

450

500

550

600

650

700

VALLEY VOLTAGE (mV)

−25 −10 20 35 65 80 95

750

800

850

900

VCC = 5 − 28 V

950

1000

TEMPERATURE (°C)

125110505−40

5.0

5.5

6.0

6.5

7.0

7.5

8.0

NCP3020A tSoft−Start (ms)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

VCC = 5 V

TEMPERATURE (°C)

125110505−40

13.2

13.4

13.6

13.8

ISET (mA)

VCC = 12 V, 28 V

−25 −10 20 35 65 80 95

VCC = 5 V

NCP3020B tSoft−Start (ms)

4.0

4.5

5.0

5.5

6.0

6.5

7.0

VCC = 12 V, 28 V

VCC = 5 V

Input = 12 V, Output = 3.3 V, Load = 5 A

C1 (Yellow) = VIN, C4 (Green) = VOUT

C2 (Red) = HSDR, C3 (Blue) = LSDR

Input = 12 V, Output = 3.3 V, Load = 5 A

C1 (Yellow) = VIN, C4 (Green) = VOUT

C2 (Red) = HSDR, C3 (Blue) = LSDR

Input = 12 V

C1 (Yellow) = FB, C3 (Blue) = LSDR

C2 (Red) = HSDR, C4 (Green) = VIN

NCP3020A

NCP3020B

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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DETAILED DESCRIPTION

OVERVIEW

The NCP3020A/B operates as a 300/600 kHz, voltage

mode, pulse width modulated, (PWM) synchronous buck

converter. It drives high−side and low−side N−channel power

MOSFETs. The NCP3020 incorporates an internal boost

circuit consisting of a boost clamp and boost diode to provide

supply voltage for the high side MOSFET gate driver. The

NCP3020 also integrates several protection features including

input undervoltage lockout (UVLO), output undervoltage

(OUV), output overvoltage (OOV), adjustable high−side

current limit (ISET and ILIM), and thermal shutdown (TSD).

The operational transconductance amplifier (OTA)

provides a high gain error signal from Vout which is

compared to the internal 1.5 V pk-pk ramp signal to set the

duty cycle converter using the PWM comparator. The high

side switch is turned on by the positive edge of the clock

cycle going into the PWM comparator and flip flop

following a non-overlap time. The high side switch is turned

off when the PWM comparator output is tripped by the

modulator ramp signal reaching a threshold level

established by the error amplifier. The gate driver stage

incorporates fixed non− overlap time between the high−side

and low−side MOSFET gate drives to prevent cross

conduction of the power MOSFET’s.

POR and UVLO

The device contains an internal Power On Reset (POR) and

input Undervoltage Lockout (UVLO) that inhibits the internal

logic and the output stage from operating until VCC reaches its

respective predefined voltage levels (4.3 V typical).

Startup and Shutdown

Once VCC crosses the UVLO rising threshold the device

begins its startup process. Closed−loop soft−start begins

after a 400 ms delay wherein the boost capacitor is charged,

and the current limit threshold is set. During the 400 ms delay

the OTA output is set to just below the valley voltage of the

internal ramp. This is done to reduce delays and to ensure a

consistent pre−soft−start condition. The device increases the

internal reference from 0 V to 0.6 V in 24 discrete steps

while maintaining closed loop regulation at each step. Each

step contains 64 switching cycles. Some overshoot may be

evident at the start of each step depending on the voltage

loop phase margin and bandwidth. The total soft−start time

is 6.8 ms for the NCP3020A and 4.4 ms for the NCP3020B.

Figure 21. Soft−Start Details

Internal Reference Voltage

0 V

0.7 V

OTA Output

Internal Ramp

24 Voltage Steps

25 mV Steps 0.6 V

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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OOV and OUV

The output voltage of the buck converter is monitored at

the feedback pin of the output power stage. Two

comparators are placed on the feedback node of the OTA to

monitor the operating window of the feedback voltage as

shown in Figures 22 and 23. All comparator outputs are

ignored during the soft−start sequence as soft−start is

regulated by the OTA and false trips would be generated.

After the soft−start period has ended, if the feedback is

below the reference voltage of comparator 2 (VFB < 0.45 V),

the output is considered “undervoltage” and the device will

initiate a restart. When the feedback pin voltage rises

between the reference voltages of comparator 1 and

comparator 2 (0.45 < VFB < 0.75), then the output voltage

is considered “Power Good.” Finally, if the feedback voltage

is greater than comparator 1 (VFB > 0.75 V), the output

voltage is considered “overvoltage,” and the device will

latch off. To clear a latch fault, input voltage must be

recycled. Graphical representation of the OOV and OUV is

shown in Figures 24 and 25.

Vref = 0.6 V

Vref*75%

Vref*125%

Comparator 1

Comparator 2

LOGIC

Soft Start Complete

Restart

Latch off

Figure 22. OOV and OUV Circuit Diagram

Power Good = 1

Vref = 0.6 V

Voov = Vref * 125%

OUVP & Power Good = 0

OOVP & Power Good = 0

Hysteresis = 5 mV

Power Not good High

Power Not Good Low

Figure 23. OOV and OUV Window Diagram

Vouv = Vref * 75%

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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0.6 V (vref *100%)

0.45 V (vref *75%)

0.75 V (vref *125%)

FB Voltage

Latch off

Reinitiate Softstart

Softstart Complete

Figure 24. Powerup Sequence and Overvoltage Latch

0.6 V (vref *100%)

0.45 V (vref *75%)

0.75 V (vref *125%)

FB Voltage

Latch off

Reinitiate Softstart

Softstart Complete

Figure 25. Powerup Sequence and Undervoltage Soft−Start

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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CURRENT LIMIT AND CURRENT LIMIT SET

Overview

The NCP3020 uses the voltage drop across the High Side

MOSFET during the on time to sense inductor current. The

ILimit block consists of a voltage comparator circuit which

compares the differential voltage across the VCC Pin and the

VSW Pin with a resistor settable voltage reference. The sense

portion of the circuit is only active while the HS MOSFET

is turned ON.

CONTROL

Vset

RSet

Iset

13 uA

DAC /

COUNTER

Ilim Out HSDR

LSDR

VSW

VIN

VCC

Itrip Ref

VSense

Switch

Cap

Figure 26. Iset / ILimit Block Diagram

Itrip Ref−63 Steps, 6.51 mV/step

Current Limit Set

The ILimit comparator reference is set during the startup

sequence by forcing a typically 13 mA current through the

low side gate drive resistor. The gate drive output will rise

to a voltage level shown in the equation below:

Vset +Iset *R

set (eq. 1)

Where ISET is 13 mA and RSET is the gate to source resistor

on the low side MOSFET.

This resistor is normally installed to prevent MOSFET

leakage from causing unwanted turn on of the low side

MOSFET. In this case, the resistor is also used to set the

ILimit trip level reference through the ILimit DAC. The Iset

process takes approximately 350 ms to complete prior to

Soft−Start stepping. The scaled voltage level across the ISET

resistor is converted to a 6 bit digital value and stored as the

trip value. The binary ILimit value is scaled and converted to

the analog ILimit reference voltage through a DAC counter.

The DAC has 63 steps in 6.51 mV increments equating to a

maximum sense voltage of 403 mV. During the Iset period

prior to Soft−Start, the DAC counter increments the

reference on the ISET comparator until it crosses the VSET

voltage and holds the DAC reference output to that count

value. This voltage is translated to the ILimit comparator

during the ISense portion of the switching cycle through the

switch cap circuit. See Figure 26. Exceeding the maximum

sense voltage results in no current limit. Steps 0 to 10 result

in an effective current limit of 0 mV.

Current Sense Cycle

Figure 27 shows how the current is sampled as it relates

to the switching cycle. Current level 1 in Figure 27

represents a condition that will not cause a fault. Current

level 2 represents a condition that will cause a fault. The

sense circuit is allowed to operate below the 3/4 point of a

given switching cycle. A given switching cycle’s 3/4 Ton

time is defined by the prior cycle’s Ton and is quantized in

10 ns steps. A fault occurs if the sensed MOSFET voltage

exceeds the DAC reference within the 3/4 time window of

the switching cycle.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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1/4 1/2

Ton−1

1/4

3/4

Ton

Ton−2

Ton−1

No Trip:

Vsense < Itrip Ref at 3/4 Point

Trip:

Vsense > Itrip Ref at 3/4 Point

3/4

3/4 Point Determined by

Prior Cycle

Vsense

1/2

Current Level 2

Current Level 1

Itrip Ref

Figure 27. ILimit Trip Point Description

Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time

value is held and used for the following cycle’s limit sample time

Soft−Start Current limit

During soft−start the ISET value is doubled to allow for

inrush current to charge the output capacitance. The DAC

reference is set back to its normal value after soft−start has

completed.

VSW Ringing

The ILimit block can lose accuracy if there is excessive

VSW voltage ringing that extends beyond the 1/2 point of the

high−side transistor on−time. Proper snubber design and

keeping the ratio of ripple current and load current in the

10−30% range can help alleviate this as well.

Current Limit

A current limit trip results in completion of one switching

cycle and subsequently half of another cycle Ton to account

for negative inductor current that might have caused

negative potentials on the output. Subsequently the power

MOSFETs are both turned off and a 4 soft−start time period

wait passes before another soft−start cycle is attempted.

Iave vs Trip Point

The average load trip current versus RSET value is shown

the equation below:

IAveTRIP +Iset Rset

RDS(on)

4ƪVIN *VOUT

VOUT

VIN

FSWƫ

(eq. 2)

Where:

L = Inductance (H)

ISET = 13 mA

RSET = Gate to Source Resistance (W)

RDS(on) = On Resistance of the HS MOSFET (W)

VIN = Input Voltage (V)

VOUT = Output Voltage (V)

FSW = Switching Frequency (Hz)

Boost Clamp Functionality

The boost circuit requires an external capacitor connected

between the BST and VSW pins to store charge for supplying

the high and low−side gate driver voltage. This clamp circuit

limits the driver voltage to typically 7.5 V when VIN > 9 V,

otherwise this internal regulator is in dropout and typically

VIN − 1.25 V.

The boost circuit regulates the gate driver output voltage

and acts as a switching diode. A simplified diagram of the

boost circuit is shown in Figure 28. While the switch node

is grounded, the sampling circuit samples the voltage at the

boost pin, and regulates the boost capacitor voltage. The

sampling circuit stores the boost voltage while the VSW is

high and the linear regulator output transistor is reversed

biased.

VIN

8.9 V

BST

VSW

LSDR

Figure 28. Boost Circuit

Switch

Sampling

Circuit

NCP3020A, NCP3020B, NCV3020A, NCV3020B

http://onsemi.com

Reduced sampling time occurs at high duty cycles where

the low side MOSFET is off for the majority of the switching

period. Reduced sampling time causes errors in the

regulated voltage on the boost pin. High duty cycle / input

voltage induced sampling errors can result in increased

boost ripple voltage or higher than desired DC boost voltage.

Figure 29 outlines all operating regions.

The recommended operating conditions are shown in

Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor

can be placed on the boost pin without causing damage to the

device or MOSFETS. Larger boost ripple voltage occurring

over several switching cycles is shown in Region 2 (Yellow).

The boost ripple frequency is dependent on the output

capacitance selected. The ripple voltage will not damage the

device or $12 V gate rated MOSFETs.

Conditions where maximum boost ripple voltage could

damage the device or $12 V gate rated MOSFETs can be

seen in Region 3 (Orange). Placing a boost capacitor that is

no greater than 10X the input capacitance of the high side

MOSFET on the boost pin limits the maximum boost

voltage < 12 V. The typical drive waveforms for Regions 1,

2 and 3 (green, yellow, and orange) regions of Figure 29 are

shown in Figure 30.

Region 1

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

11 .5V

Region 2

22V

Region 3

Duty Cycle

Input Voltage

Normal Operation Increased Boost Ripple

(Still in Specification)

Increased Boost Ripple

Capacitor Optimization

Required

71%

Maxi

mum

Duty

Cycle

Boost Voltage Levels

Max

Duty

Cycle

Figure 29. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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VBOOST

VIN 7.5V

Normal

Maximum

VBOOST

VIN

Normal

Maximum

VBOOST

VIN

7.5V

Figure 30. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom)

7.5V

To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications

for the driver supply voltage. See Figure 31.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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Boost Voltage

4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5

Input Voltage (V)

Boost Voltage (V)

Figure 31. Boost Voltage at 80% Duty Cycle

Voltage Ripple

Maximum Allowable Voltage

Maximum Boost Voltage

Inductor Selection

When selecting the inductor, it is important to know the

input and output requirements. Some example conditions

are listed below to assist in the process.

Table 1. DESIGN PARAMETERS

Design Parameter Example Value

Input Voltage (VIN)9 V to 18 V

Nominal Input Voltage (VIN)12 V

Output Voltage (VOUT)3.3 V

Input ripple voltage (VINRIPPLE)300 mV

Output ripple voltage (VOUTRIPPLE)50 mV

Output current rating (IOUT)10 A

Operating frequency (Fsw) 300 kHz

A buck converter produces input voltage (VIN) pulses that

are LC filtered to produce a lower dc output voltage (VOUT).

The output voltage can be changed by modifying the on time

relative to the switching period (T) or switching frequency.

The ratio of high side switch on time to the switching period

is called duty cycle (D). Duty cycle can also be calculated

using VOUT, VIN, the low side switch voltage drop VLSD,

and the High side switch voltage drop VHSD.

F+1

T(eq. 3)

D+

TON

T(*DǓ+

TOFF

T(eq. 4)

D+

VOUT )VLSD

VIN *VHSD )VLSD

[D+

VOUT

VIN (eq. 5)

³27.5% +3.3 V

12 V

The ratio of ripple current to maximum output current

simplifies the equations used for inductor selection. The

formula for this is given in Equation 6.

ra +DI

IOUT

(eq. 6)

The designer should employ a rule of thumb where the

percentage of ripple current in the inductor lies between

10% and 40%. When using ceramic output capacitors the

ripple current can be greater thus a user might select a higher

ripple current, but when using electrolytic capacitors a lower

ripple current will result in lower output ripple. Now,

acceptable values of inductance for a design can be

calculated using Equation 7.

L+

VOUT

IOUT @ra @FSW

@(1*D)³3.3 mH

(eq. 7)

+3.3 V

10 A @24% @300 kHz @(1*27.5%)

The relationship between ra and L for this design example

is shown in Figure 32.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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10% 15% 20% 25% 30% 35% 40%

VIN, (V)

L, INDUCTANCE (mH)

18 V Vout = 3.3 V

15 V

12 V

9 V

Figure 32. Ripple Current Ratio vs. Inductance

To keep within the bounds of the parts maximum rating,

calculate the RMS current and peak current.

IRMS +IOUT @1)ra2

Ǹ³10.02 A

(eq. 8)

+10 A @1)(0.24)2

IPK +IOUT @ǒ1)ra

2Ǔ³11.2 A +10 A @ǒ1)(0.24)

2Ǔ

(eq. 9)

An inductor for this example would be around 3.3 mH and

should support an rms current of 10.02 A and a peak current

of 11.2 A.

The final selection of an output inductor has both

mechanical and electrical considerations. From a

mechanical perspective, smaller inductor values generally

correspond to smaller physical size. Since the inductor is

often one of the largest components in the regulation system,

a minimum inductor value is particularly important in

space−constrained applications. From an electrical

perspective, the maximum current slew rate through the

output inductor for a buck regulator is given by Equation 10.

SlewRateLOUT +

VIN *VOUT

LOUT

³2.6 A

(eq. 10)

+12 V *3.3 V

3.3 mH

This equation implies that larger inductor values limit the

regulator’s ability to slew current through the output

inductor in response to output load transients. Consequently,

output capacitors must supply the load current until the

inductor current reaches the output load current level. This

results in larger values of output capacitance to maintain

tight output voltage regulation. In contrast, smaller values of

inductance increase the regulator’s maximum achievable

slew rate and decrease the necessary capacitance, at the

expense of higher ripple current. The peak−to−peak ripple

current for the NCP3020A is given by the following

equation:

IPP +

VOUT(1*D)

LOUT @FSW

(eq. 11)

Ipp is the peak to peak current of the inductor. From this

equation it is clear that the ripple current increases as LOUT

decreases, emphasizing the trade−off between dynamic

response and ripple current.

The power dissipation of an inductor consists of both

copper and core losses. The copper losses can be further

categorized into dc losses and ac losses. A good first order

approximation of the inductor losses can be made using the

DC resistance as they usually contribute to 90% of the losses

of the inductor shown below:

LPCU +IRMS 2@DCR (eq. 12)

The core losses and ac copper losses will depend on the

geometry of the selected core, core material, and wire used.

Most vendors will provide the appropriate information to

make accurate calculations of the power dissipation then the

total inductor losses can be capture buy the equation below:

LPtot +LPCU_DC )LPCU_AC )LPCore (eq. 13)

Input Capacitor Selection

The input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so it

must have a low ESR to minimize the losses. The RMS value

of this ripple is:

IinRMS +IOUT @D@(1*D)

Ǹ(eq. 14)

D is the duty cycle, IinRMS is the input RMS current, and

IOUT is the load current.

The equation reaches its maximum value with D = 0.5.

Loss in the input capacitors can be calculated with the

following equation:

PCIN +ESRCIN @ǒIIN*RMSǓ2(eq. 15)

PCIN is the power loss in the input capacitors and ESRCIN

is the effective series resistance of the input capacitance.

Due to large dI/dt through the input capacitors, electrolytic

or ceramics should be used. If a tantalum must be used, it

must by surge protected. Otherwise, capacitor failure could

occur.

Input Start−up Current

To calculate the input startup current, the following

equation can be used.

IINRUSH +

COUT @VOUT

tSS

(eq. 16)

Iinrush is the input current during startup, COUT is the total

output capacitance, VOUT is the desired output voltage, and

tSS is the soft start interval. If the inrush current is higher than

the steady state input current during max load, then the input

fuse should be rated accordingly, if one is used.

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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Output Capacitor Selection

The important factors to consider when selecting an

output capacitor is dc voltage rating, ripple current rating,

output ripple voltage requirements, and transient response

requirements.

The output capacitor must be rated to handle the ripple

current at full load with proper derating. The RMS ratings

given in datasheets are generally for lower switching

frequency than used in switch mode power supplies but a

multiplier is usually given for higher frequency operation.

The RMS current for the output capacitor can be calculated

below:

CoRMS +IO@ra

Ǹ(eq. 17)

The maximum allowable output voltage ripple is a

combination of the ripple current selected, the output

capacitance selected, the equivalent series inductance (ESL)

and ESR.

The main component of the ripple voltage is usually due

to the ESR of the output capacitor and the capacitance

selected.

VESR_C +IO@ra @ǒESRCo )1

8@FSW @CoǓ(eq. 18)

The ESL of capacitors depends on the technology chosen

but tends to range from 1 nH to 20 nH where ceramic

capacitors have the lowest inductance and electrolytic

capacitors then to have the highest. The calculated

contributing voltage ripple from ESL is shown for the switch

on and switch off below:

VESLON +

ESL @IPP @FSW

(eq. 19)

VESLOFF +

ESL @IPP @FSW

(1*D)

(eq. 20)

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,

for the first few microseconds it supplies the current to the

load. The controller immediately recognizes the load

transient and sets the duty cycle to maximum, but the current

slope is limited by the inductor value.

During a load step transient the output voltage initially

drops due to the current variation inside the capacitor and the

ESR (neglecting the effect of the effective series inductance

(ESL)).

DVOUT−ESR +DITRAN @ESRCo (eq. 21)

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The

voltage drop due to output capacitor discharge is

approximated by the following equation:

DVOUT−DISCHG +ǒITRANǓ2@LOUT

COUT @ǒVIN *VOUTǓ(eq. 22)

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. It should be noted

that DVOUT−DISCHARGE and DVOUT−ESR are out of

phase with each other, and the larger of these two voltages

will determine the maximum deviation of the output voltage

(neglecting the effect of the ESL).

Conversely during a load release, the output voltage can

increase as the energy stored in the inductor dumps into the

output capacitor. The ESR contribution from Equation 18

still applies in addition to the output capacitor charge which

is approximated by the following equation:

DVOUT−CHG +ǒITRANǓ2@LOUT

COUT @VOUT

(eq. 23)

Power MOSFET Selection

Power dissipation, package size, and the thermal

environment drive MOSFET selection. To adequately select

the correct MOSFETs, the design must first predict its power

dissipation. Once the dissipation is known, the thermal

impedance can be calculated to prevent the specified

maximum junction temperatures from being exceeded at the

highest ambient temperature.

Power dissipation has two primary contributors:

conduction losses and switching losses. The control or

high−side MOSFET will display both switching and

conduction losses. The synchronous or low−side MOSFET

will exhibit only conduction losses because it switches into

nearly zero voltage. However, the body diode in the

synchronous MOSFET will suffer diode losses during the

non−overlap time of the gate drivers.

Starting with the high−side or control MOSFET, the

power dissipation can be approximated from:

PD_CONTROL +PCOND )PSW_TOT (eq. 24)

The first term is the conduction loss of the high−side

MOSFET while it is on.

PCOND +ǒIRMS_CONTROLǓ2

@RDS(on)_CONTROL (eq. 25)

Using the ra term from Equation 6, IRMS becomes:

IRMS_CONTROL +IOUT @D@ǒ1)ǒra2

12ǓǓ

Ǹ(eq. 26)

The second term from Equation 24 is the total switching

loss and can be approximated from the following equations.

PSW_TOT +PSW )PDS )PRR (eq. 27)

The first term for total switching losses from Equation 27

includes the losses associated with turning the control

MOSFET on and off and the corresponding overlap in drain

voltage and current.

PSW +PTON )PTOFF

(eq. 28)

2@ǒIOUT @VIN @fSWǓ@ǒtON )tOFFǓ

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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where:

tON +

QGD

IG1

QGD

ǒVBST *VTHǓńǒRHSPU )RGǓ(eq. 29)

and:

tOFF +

QGD

IG2

QGD

ǒVBST *VTHǓńǒRHSPD )RGǓ(eq. 30)

Next, the MOSFET output capacitance losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control MOSFET.

PDS +1

2@QOSS @VIN @fSW (eq. 31)

Finally the loss due to the reverse recovery time of the

body diode in the synchronous MOSFET is shown as

follows:

PRR +QRR @VIN @fSW (eq. 32)

The low−side or synchronous MOSFET turns on into zero

volts so switching losses are negligible. Its power

dissipation only consists of conduction loss due to RDS(on)

and body diode loss during the non−overlap periods.

PD_SYNC +PCOND )PBODY (eq. 33)

Conduction loss in the low−side or synchronous

MOSFET is described as follows:

PCOND +ǒIRMS_SYNCǓ2

@RDS(on)_SYNC (eq. 34)

where:

(eq. 35)

IRMS_SYNC +IOUT @(1*D)@ǒ1)ǒra2

12 ǓǓ

The body diode losses can be approximated as:

PBODY +VFD @IOUT @fSW @ǒNOLLH )NOLHLǓ(eq. 36)

Vth

Figure 33. MOSFET Switching Characteristics

IG1: output current from the high−side gate drive (HSDR)

IG2: output current from the low−side gate drive (LSDR)

ƒSW: switching frequency of the converter. NCP3020A is

300 kHz and NCP3020B is 600 kHz

VBST: gate drive voltage for the high−side drive, typically

7.5 V.

QGD: gate charge plateau region, commonly specified in the

MOSFET datasheet

VTH: gate−to−source voltage at the gate charge plateau

region

QOSS: MOSFET output gate charge specified in the data

sheet

QRR: reverse recovery charge of the low−side or

synchronous MOSFET, specified in the datasheet

RDS(on)_CONTROL: on resistance of the high−side, or

control, MOSFET

RDS(on)_SYNC: on resistance of the low−side, or

synchronous, MOSFET

NOLLH: dead time between the LSDR turning off and the

HSDR turning on, typically 85 ns

NOLHL: dead time between the HSDR turning off and the

LSDR turning on, typically 75 ns

Once the MOSFET power dissipations are determined,

the designer can calculate the required thermal impedance

for each device to maintain a specified junction temperature

at the worst case ambient temperature. The formula for

calculating the junction temperature with the package in free

air is:

TJ+TA)PD@RqJA

TJ: Junction Temperature

TA: Ambient Temperature

PD: Power Dissipation of the MOSFET under analysis

RqJA: Thermal Resistance Junction−to−Ambient of the

MOSFET’s package

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading, and component

variations (i.e. worst case MOSFET RDS(on)).

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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Figure 34. MOSFETs Timing Diagram

High−Side

Logic Signal

Low−Side

Logic Signal

High−Side

MOSFET

Low−Side

MOSFET

RDSmax

RDS(on)min

RDSmax

RDS(on)min

NOLHL NOLLH

td(on)

trtd(off)

trtf

td(on) td(off)

Another consideration during MOSFET selection is their

delay times. Turn−on and turn−off times must be short

enough to prevent cross conduction. If not, there will be

conduction from the input through both MOSFETs to

ground. Therefore, the following conditions must be met.

td(ON)_CONTROL )NOLLH utd(OFF)_SYNC )tf_SYNC

(eq. 37)

t(ON)_SYNC )NOLHL utd(OFF)_CONTROL )tf_CONTROL

and

The MOSFET parameters, td(ON), tr, td(OFF) and tf are can

be found in their appropriate datasheets for specific

conditions. NOLLH and NOLHL are the dead times which

were described earlier and are 85 ns and 75 ns, respectively.

Feedback and Compensation

The NCP3020 is a voltage mode buck convertor with a

transconductance error amplifier compensated by an

external compensation network. Compensation is needed to

achieve accurate output voltage regulation and fast transient

response. The goal of the compensation circuit is to provide

a loop gain function with the highest crossing frequency and

adequate phase margin (minimally 45°). The transfer

function of the power stage (the output LC filter) is a double

pole system. The resonance frequency of this filter is

expressed as follows:

fP0 +1

2@p@L@COUT

Ǹ(eq. 38)

Parasitic Equivalent Series Resistance (ESR) of the

output filter capacitor introduces a high frequency zero to

the filter network. Its value can be calculated by using the

following equation:

fZ0 +1

2@p@COUT @ESR (eq. 39)

The main loop zero crossover frequency f0 can be chosen

to be 1/10 − 1/5 of the switching frequency. Table 2 shows

the three methods of compensation.

Table 2. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type

fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum

fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic

fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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Compensation Type II

This compensation is suitable for electrolytic capacitors.

Components of the Type II (Figure 35) network can be

specified by the following equations:

Figure 35. Type II Compensation

RC1 +

2@p@f0@L@VRAMP @VOUT

ESR @VIN @Vref @gm (eq. 40)

CC1 +1

0.75 @2@p@fP0 @RC1

(eq. 41)

CC2 +1

p@RC1 @fS

(eq. 42)

R1 +

VOUT *Vref

Vref

@R2 (eq. 43)

VRAMP is the peak−to−peak voltage of the oscillator ramp

and gm is the transconductance error amplifier gain.

Capacitor CC2 is optional.

Compensation Type III

Tantalum and ceramics capacitors have lower ESR than

electrolytic, so the zero of the output LC filter goes to a

higher frequency above the zero crossover frequency. This

requires a Type III compensation network as shown in

Figure 36.

There are two methods to select the zeros and poles of this

compensation network. Method I is ideal for tantalum

output capacitors, which have a higher ESR than ceramic:

Figure 36. Type III Compensation

fZ1 +0.75 @fP0 (eq. 44)

fZ2 +fP0 (eq. 45)

fP2 +fZ0 (eq. 46)

fP3 +

2(eq. 47)

Method II is better suited for ceramic capacitors that

typically have the lowest ESR available:

fZ2 +f0@1*sinqmax

1)sin qmax

Ǹ(eq. 48)

fP2 +f0@1)sin qmax

1*sin qmax

Ǹ(eq. 49)

fZ1 +0.5 @fZ2 (eq. 50)

fP3 +0.5 @fS(eq. 51)

qmax is the desired maximum phase margin at the zero

crossover frequency, ƒ0. It should be 45° − 75°. Convert

degrees to radians by the formula:

qmax +qmaxdegress @ǒ2@p

360 Ǔ:Units+radians (eq. 52)

The remaining calculations are the same for both methods.

RC1 uu 2

gm (eq. 53)

CC1 +1

2@p@fZ1 @RC1

(eq. 54)

CC2 +1

2@p@fP3 @RC1

(eq. 55)

CFB1 +

2@p@f0@L@VRAMP @COUT

VIN @RC1

(eq. 56)

RFB1 +1

2p@CFB1 @fP2

(eq. 57)

R1 +1

2@p@CFB1 @fZ2

*RFB1 (eq. 58)

R2 +

Vref

VOUT *Vref

@R1 (eq. 59)

If the equation in Equation 60 is not true, then a higher value

of RC1 must be selected.

R1 @R2 @RFB1

R1 @RFB1 )R2 @RFB1 )R1 @R2 u1

gm (eq. 60)

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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TYPICAL APPLICATION CIRCUIT

9−18 V

VCC BST

HSDR

VSW

LSDR

COMP

3.3

CBST

3.3 uH

RISET

RFB1

COUT −2/3

Cc1

Cc2

GND

RFB2

CIN−1/2

RGS

RFB3

CFB

CIN−3/4 CIN−5

COUT−1

NCP3020A

Figure 37. Typical Application, VIN = 9 − 18 V, VOUT = 3.3 V, IOUT = 10 A

Reference Designator Value

CIN−1470 mF

CIN−2470 mF

CIN−322 mF

CIN−422 mF

CIN−51 mF

CC1 33 pF

CC2 8.2 nF

CFB 1.8 nF

COUT1 470 mF

COUT2 22 mF

COUT3 22 mF

CBST 0.1 mF

RC 4.75 kW

RG 8.06 W

RGS 1.0 kW

RISET 22.1 kW

RFB1 4.53 kW

RFB2 1.0 kW

RFB3 2.49 kW

Q1 NTMFS4841N

Q2 NTMFS4935

D1 BAT54

NCP3020A, NCP3020B, NCV3020A, NCV3020B

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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