Rev. 2.4 - 5/27/98 1
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PRELIMINARY
4 Megabit 3.3V Static RAM
512K x 8-Bit
Features
n
High-speed access times
Com’l: 8, 10, 12, 15, and 20 ns
Ind’l.: 12, 15 and 20 ns
n
Low power operation
- PDM31096SA
Active: 300 mA (Max)
Standby: 25mW
n
Single +3.3V (
±
0.3V) power supply
n
TTL-compatible inputs and outputs
n
Packages
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Description
The PDM31096 is a high-performance CMOS static
RAM organized as 524,288 x 8 bits. Writing is
accomplished when the write enable (WE) and chip
enable CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31096 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31096 is available in a 36-pin 400-mil plas-
tic SOJ package and a 44-pin plastic TSOP (II)
package.
PDM31096
A
•
•
•
•
•
A
0
18
I/O
•
•
I/O
0
7
•
•
•
•
•
•
Addresses
Decoder Memory
Matrix
Input
Data
Control
Column I/O
•••••
•
•
•
CE
WE
OE
Functional Block Diagram
PDM31096
2 Rev. 2.4 - 5/27/98
PRELIMINARY
T ruth Table(1)
NOTE: 1. H = VIH, L = VIL, X = DON’T CARE
OE WE CE I/O MODE
X X H Hi-Z Standby
X X X Hi-Z Standby
LHLD
OUT Read
XLLD
IN Write
H H L Hi-Z Output Disable
Pin Description
Name Description
A18-A0 Address Inputs
I/O7-I/O0 Data Inputs/Outputs
OE Output Enable Input
WE Write Enable Input
CE Chip Enable Inputs
NC No Connect
VCC Power (+3.3V)
VSS Ground
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
23
24
25
26
27
28
A4
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A18
A17
A16
A15
A14
NC
A5
A6
A7
A8
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A9
A10
A11
A12
A13
NC
13
14
29
30
31
36
32
33
34
35
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
15
16 29
30
31
32
NC
NC
A4
A3
A2
A1
A0
CE
I/OO
I/O1
Vcc
Vss
I/O2
I/O3
WE
A18
A17
A16
A15
A14
NC
NC
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A9
A10
A11
A12
A13
NC
NC
NC
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
SOJ
TSOP (II)
Absolute Maximum Ratings
(1)
NO TE:1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS ma y cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient temperature, P
is average operating power and
θ
ja
the thermal resistance of the package. For this
product, use the following
θ
ja
value:
SOJ: 59
o
C/W
TSOP : TBD
Symbol Rating Com’l. Ind. Unit
V
TERM
Terminal Voltage with Respect to V
SS
–0.5 to +4.6 –0.5 to +4.6 V
T
BIAS
Temperature Under Bias –55 to +125 –65 to +135
°
C
T
STG
Storage Temperature –55 to +125 –65 to +150
°
C
P
T
Power Dissipation 1.0 1.0 W
I
OUT
DC Output Current 50 50 mA
T
j
Maximum Junction Temperature
(2)
125 145
°
C
Pin Configuration
PDM31096
Rev. 2.4 - 5/27/98 3
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PRELIMINARY
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns
Power Supply Characteristics
NOTES: All values are maximum guaranteed values.
Capacitance
(1)
(T
A
= +25
°
C, f = 1.0 MHz)
NOTE: 1.This parameter is determined by device characterization but is not production tested.
Symbol Parameter Test Conditions Min. Max. Unit
I
LI
Input Leakage Current V
CC
= Max., V
IN
= V
SS
to V
CC
–5 5
µ
A
I
LO
Output Leakage Current V
CC
= Max.,
CE = V
IH
V
OUT
= V
SS
to V
CC
–5 5
µ
A
V
IL
Input Low Voltage –0.3
(1)
0.8 V
V
IH
Input High Voltage 2.2 Vcc+0.3 V
V
OL
Output Low Voltage I
OL
= 8 mA, V
CC
= Min. — 0.4 V
V
OH
Output High Voltage I
OH
= –4 mA, V
CC
= Min. 2.4 — V
-8 -10 -12 -15 -20
Symbol Parameter Com’l. Com’l. Com’l Ind. Com’l Ind. Com’l Ind. Unit
I
CC
Operating Current
CE = V
IL
230 215 200 220 160 200 120 160 mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
50 45 40 45 35 40 30 35 mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
CC
– 0.2V 10 10 10 15 10 15 10 15 mA
f = 0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
Symbol Parameter Max. Unit
C
IN
Input Capacitance 8 pF
C
OUT
Output Capacitance 8 pF
PDM31096
4 Rev. 2.4 - 5/27/98
PRELIMINARY
Recommended DC Operating Conditions
AC Test Conditions
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply V oltage 3.0 3.3 3.6 V
V
SS
Supply V oltage 0 0 0 V
Industrial Ambient Temperature –40 25 85
°
C
Commercial Ambient Temperature –0 25 70
°
C
Input pulse levels V
SS
to 3.0V
Input rise and fall times 2.5 ns
Input timing reference levels 1.5V
Output reference levels 1.5V
Output load See Figures 1 and 2
Figure 1. Output Load Equivalent Figure 2. Output Load Equivalent
(for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE,
tHZOE)
+3.3V +3.3V
317Ω317Ω
351Ω351Ω
D
OUT
D
OUT
30 pF 5 pF
PDM31096
Rev. 2.4 - 5/27/98 5
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PRELIMINARY
Read Cycle No. 1
(4, 5)
Read Cycle No. 2
(2, 4, 6)
AC Electrical Characteristics
* V
cc
= 3.3V +5%
Description -8* -10* –12 –15 –20
READ Cycle Sym Min Max Min Max Min Max Min Max Min Max Units
READ cycle time t
RC
8 —10—12—15—20— ns
Address access time tAA — 8 —10—12—15—20ns
Chip enable access time tACE — 8 —10—12—15—20ns
Output hold from address change tOH 3—3—3—3—3—ns
Chip enable to output in low Z(1,3) tLZCE 3—3—3—3—3—ns
Chip disable to output in high Z(1,2,3) tHZCE —4—5—6—7—7ns
Output enable access time tAOE —4—5—6—7—8ns
Output Enable to output in low Z (1,3) tLZOE 0—0—0—0—0—ns
Output disable to output in high Z(1,3) tHZOE —4—4—5—6—7ns
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE
OE
D
OUT DATA VALID
PDM31096
6 Rev. 2.4 - 5/27/98
PRELIMINARY
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Write Enable Controlled)
tWC
tAW
tWP
tCW
tAH
tAS
tDH
tDS
tLZWE
tHZWE
ADDR
CE
WE
DOUT HIGH-Z
DIN DATA VALID
NOTE: Output Enable (OE) is inactive (high)
tWC
tAW
tWP
tCW
tAH
tAS
tDH
tDS
ADDR
CE
WE
DOUT HIGH-Z
DIN DATA VALID
PDM31096
Rev. 2.4 - 5/27/98 7
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PRELIMINARY
Write Cycle No. 3 (Chip Enable Controlled)
AC Electrical Characteristics
* VCC = 3.3V +5%
NOTES: (For two previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. All the Chip Enables are held in their active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
Description -8* -10* -12 -15 -20
WRITE Cycle Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time tWC 8 —10—12—15—20— ns
Chip enable to end of write tCW 8 —10—10—11—13—ns
Address valid to end of write tAW 8 —10—10—11—13— ns
Address setup time tAS 0—0—0—0—0—ns
Address hold from end of write tAH 0—0—0—0—0—ns
Write pulse width tWP 7—8—8—9—10—ns
Data setup time tDS 5—6—7—8—9—ns
Data hold time tDH 0—0—0—0—0—ns
Write disable to output in low Z(1,3) tLZWE 0—0—0—0—0—ns
Write enable to output in high Z(1,3) tHZWE —4 5—6—7—9ns
NOTE: Output Enable (OE) is inactive (high)
tWC
tAW
tWP
tCW
tAH
tAS
tDH
tDS
ADDR
CE
WE
DOUT HIGH-Z
DIN DATA VALID
PDM31096
8 Rev. 2.4 - 5/27/98
PRELIMINARY
Device Type Power Speed Package
Type
Process
Temp. Range Preferred
Shipping
Container
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
8/10 Commercial Only
12
15
20
SA
Standard Power
Blank
I
A Automotive (
–40°C to +105°C)
Blank Tubes
TR  Tape & Reel
TY  Tray
PDM31096 - (512Kx8) Static RAM
XXXXX X XX X X X
SO 36-pin 400-mil Plastic SOJ
T 44-pin 400-mil Plastic TSOP (II)
Ordering Information
Faster Memories for a Faster World ™