AT93C46/56/57/66
6
Functional Description
The AT93C46/56/57 /66 is accessed v ia a simple an d ver-
satile 3-wire se rial comm unicat ion inter face. Dev ice oper a-
tion is controlle d by se ven in structio ns iss ued by th e host
processor. A v alid instruction starts with a rising edge
of CS and consists of a Start Bit (logic ‘1’) followed by the
appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instructio n contains
the Addr ess c ode fo r the me mory l oc ation to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 8- or 16-bit data output
string.
ERASE/WRITE (EWEN): To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or V CC power is removed
from the part.
ERASE (ERASE): The Erase (E RASE) instruction pro-
grams all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and addres s are decoded. The DO pin outputs
the READY/BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (tCS). A logic
‘1’ at pin DO indicates that the selected memory location
has be en er ase d, and the part is r eady fo r an other instr uc-
tion.
WRITE (WRITE): The Write (WRITE) instruct ion contains
the 8 or 16 bits of data to be written into the specified mem-
ory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin
DI. The DO pin outputs the READY/BUSY status of the part
if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic ‘0’ at DO indicates that programming is
still in progress. A logic ‘1’ indicates that the memory loca-
tion at the s pe cif ie d ad dres s h as been written with the da ta
pattern contained in the instruction and the part is ready for
further instructions. A READY/BUSY status cannot be
obtained if the CS is brought high after the end of the
self-timed programming cycle, tWP.
ERASE ALL (ERA L): The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is pr imar ily u sed for te sting p urpos es. The DO pin out-
puts the RE ADY/BUSY status of the pa rt if CS is brought
high after being kept low for a minimum of 250 ns (tCS). The
ERAL inst ruc ti on is va li d only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
ified in the instruction. The DO pin outputs the
READY /BUSY s tatus of th e part if C S is brought h igh after
being kept low for a minimum of 250 ns (tCS). The WRAL
instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISAB LE (EWDS): To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all progr amming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
Instruction Set for the AT93C56 and AT 93C66
Instruction SB Op
Code
Address Data
Commentsx 8 x 16 x 8 x 16
READ 1 10 A8 - A0A7 - A0Reads data stored in memory, at
specified address.
EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all
programming modes.
ERASE 1 11 A8 - A0A7 - A0Erases memory loca tion An - A0.
WRITE 1 01 A8 - A0A7 - A0D7 - D0D15 - D0Wr ites memory location An - A0.
ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
WRAL 1 00 01XXXXXXX 01XXXXXX D7 - D0D15 - D0Writes all memory locations. Valid
when VCC = 5.0V ± 10% and Disable
Regist er cle are d.
EWDS 1 00 00XXXXXXX 00XXXXXX Disab les all prog r amming i nstructions.