ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
- 1 -
AK6420A / 40A / 80A
2K / 4K / 8Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
Wide Vcc (1.8V ∼ 5.5 V) operatio n
AK6420A • • 2048 bits: 128 × 16 organization
AK6440A • • 4096 bits: 256 × 16 organization
AK6480A • • 8192 bits: 512 × 16 organization
ONE CHIP MICROCOMPUTER INTERFACE
- Interface with one chip microcomputer's serial communication port directly
LOW POWER CONSUMPTION
- 0.75mA Max (Read operation)
- 0.8
µ
A Max (Standby mode)
HIGH RELIABILITY
-Endurance : 100K cycles
-Data Retention : 10 years
SPECIAL FEATURES
- High speed operation ( fMAX=1MHz: Vcc=2.5V )
- Automatic write cycle time-out with auto-ERASE
- Automatic address increment (READ)
- Ready/Busy status signal
- Software and Hardware controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (SOP, SSOP)
Block diagram
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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General Description
The AK6420A/40A /80A is a 2048/4096/8192 bit, serial, read/write, non-v olatile m emory de vice f abricated u sing an
adv anced CMOS EEPROM technology. The AK6420A has 2048bi ts of memory organized i nto 128 registers of 16
bits each. The AK6440A has 4096bits of me mory organized into 25 6 regi sters of 16 bits each. The AK6480A has
8192bits o f memory organized int o 512 regi sters of 16 bits each. The AK6420A/40A/80A can ope rate f ull function
under wide operati ng voltage range f rom 1.8V to 5. 5V. The charge up circui t is integ r ated for high v oltage gene ra tion
that i s used for write operation.
The AK6420A/40A /80A can conne ct to the serial comm unication po rt of popular one chip mi crocomputer dir ectly ( 3
line negative cloc k synchronous inte rf ace) . At write operation, AK6420A /40A/80A ta k es in the write data f rom data
input pin (DI) to a regi ster synchronousl y with rising edge of input pul se of serial cloc k pin (SK). And at read ope ration,
AK6420A/40A/80A tak es out the read data from a registe r to data output pin (DO) synchronousl y with falling edge of
SK.
The AK6420A/40A /80A has 4 instructions such as READ, WRITE, WREN (write enable ) and WRDS (write disab le).
Each instruction i s organiz ed b y op-code b lo c k (8bits), add ress b lo c k (8bits) and da ta (8bi ts × 2). When input le v el of
SK pin is high le v el and input le v el of chip select (CS) pin i s changed from high level to lo w level, AK6420A/40A/80A
can receiv e t he instructions.
Special features of the AK64 20A/40A/80A incl ude : automatic write time-o ut with auto- ER ASE, Ready/Busy status
signal outp ut and ul tra-lo w st andb y po wer mode when de selected ( CS=high).
• Softw are an d Hardw are co ntrolled w rite protection
The AK6420A/40A /80A has 2 (hardwa re and softw are) write protection function s.
After po we r on or a fter exe cution of WRDS (write disab le) in struction, execution o f WRITE instructio n will be disab led.
This write protection conditio n continues until WREN instruction is e x ecuted or V cc is remov ed from the pa rt.
Ex e cution of READ i nstruction is independ ent of b oth WREN and WRDS instructions.
Reset pin should be lo w le v el when WRITE instruction is ex ecuted. When the Reset pin i s high level, the WRITE
instruction is not exe cuted.
• Ready/Busy status signal
During the autom atic write ti me-out period (B USY statu s), the AK6420A/4 0A/80A can't accept the other i nstructions.
The AK6420A/40A /80A has 2 functions to kno w the Busy status f rom e xterior.
The RDY/BUSY pin indi cates the Busy status regardless of the CS pin status . The RDY/B USY pin outputs the lo w
level regardless of the CS pin status during Busy status. Except the above status, this pin outputs high le vel.
Also the DO pin indicates the Busy statu s. When input level of SK pin i s lo w level and inp ut le v el o f CS pin i s changed
from high l e v el to lo w level, th e AK6420A/40A/80A i s in t he statu s output mode and the DO pi n indicates the
Ready/Busy statu s. The Ready/Busy statu s outputs on DO pin until CS pin i s changed from lo w level to high level, or
first bit ("1") o f op-code of next instruction i s giv en to the pa rt. Except when the device is in the statu s output mode o r
outputs data, the D O pin i s in the high i mpedance state .
Type of Products
Model Memory size Temp.Range Vcc Package
AK6420AF
AK6420AM 2Kbits -40°C∼85°C
-40°C∼85°C1.8V ∼ 5.5V
1.8V ∼ 5.5V 8pin Plastic SO P
8pin Plastic SSOP
AK6440AF
AK6440AM 4Kbits -40°C∼85°C
-40°C∼85°C1.8V ∼ 5.5V
1.8V ∼ 5.5V 8pin Plastic SO P
8pin Plastic SSOP
AK6480AF
AK6480AM 8Kbits -40°C∼85°C
-40°C∼85°C1.8V ∼ 5.5V
1.8V ∼ 5.5V 8pin Plastic SO P
8pin Plastic SSOP
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Pin arrangement
Pin Function
Pin No. Pin name I/O
SOP / SSOP
1 / 7 RDY/BUSY O
2 / 8 Vcc
3 / 1 CS I
4 / 2 SK I
5 / 3 DI I
6 / 4 DO O
7 / 5 GND
8 / 6 RESET I
Note
I : Input pin
O: Output pin
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Pin Description
CS (Chip Select)
When SK is high level and CS is chan ged from hi gh level to low level, AK642 0A/ 40A /80 A ca n rec eive the
instructions. CS should be kept low level while receiving op-code, address and data and while outputting data.
If CS is changed to high level during the above period, AK6420A/40A/80A stops the instruction execution.
When SK is low and CS is changed from high level to low level, AK6420A/40A/80A will be in status output
mode. The CS need not be low level during the automatic write time-out period (BUSY status).
SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation, AK6420A/40A/80A
takes in the write data from data input pin (DI) synchronously with rising edge of input pulse of serial clock pin
(SK). And at read operation, AK6420A/40A/80A takes out the read data to data output pin (DO)
synchronously with falling edge of SK. The SK clock is not needed during the automatic write time-out period
(BUSY status), the status output period and when the device isn't selected (CS = high le vel).
DI (Data Input)
The op-code, address and write data is input to the DI pin.
DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for this timing.
RDY/BUSY (Ready/Busy status)
This pin outputs the internal programming status. When the AK6420A/40A/80A is in the automatic write time-
out period, this pin outputs the low level (BUSY status), and outputs the high level e xcept for this timing.
RESET (Reset)
The AK6420A/40A/80A stops executing the write instruction when the RESET pin is high level. The RESET
pin should be low level while the write instruction input period and the automatic write time-out period. If the
RESET pin is high level while the automatic write time-out period, the AK6420A/40A/80A stops execution of
internal programming and the device returns to ready status. In this case the word data of the specified
address will be incomplete. When inputting the new instruction after RESET, the CS should be set to high
level. The read, write enable and write disable instructions are not affected by RESET pin status.
Vcc (Power Supply)
GND (Ground)
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Functional Description
The AK6420A/40A/80A has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write
disable). Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bits × 2).
When input level of SK pin is high level and input level of chip select (CS) pin is changed from high level to low
level, AK6420A/40A/80A can receive the instructions.
When the instructions are executed consecutively, the C S pin should be brought to high level for a minimum of
250ns(Tcs) between consecutive instruction cycle.
Instruction Set For 6420A
Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0
WRITE 1 0 1 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0
WREN 1 0 1 0 0 0 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
WRDS 1 0 1 0 0 0 0 0 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
( WRAL ) 1 0 1 0 1 1 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0
Instruction Set For 6440A
Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WRITE 1 0 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WREN 1 0 1 0 0 0 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
WRDS 1 0 1 0 0 0 0 0 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
( WRAL ) 1 0 1 0 1 1 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0
Instruction Set For 6480A
Instruction Op-Code Address Data
READ 1 0 1 0 1 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WRITE 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0
WREN 1 0 1 0 0 0 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
WRDS 1 0 1 0 0 0 0 0 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
( WRAL ) 1 0 1 0 1 1 1 1 ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0
Õ:don't care
(Note) The WRAL instruction is used for factory function test only. User can't use this instruction .
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Write
The write instruction is followed by 16 bits of data to be written into the specified address. After the 32nd
rising edge of SK to read D0 in, the AK6420A/40A/80A will be put into the automatic write time-out period.
During the automatic write time-out period (Busy status)and while entering write instruction, the RESET pin
should be low level. If the RESET pin is set to high level during the automatic write time-out period, the
AK6420A/40A/80A stops execution of internal programming and the device returns to ready status. In this
case the word data of the specified address will be incomplete. When inputting the new instruction after
RESET, the CS should be set to high level. When the RESET pin is kept at high level, the write is not
executed. This becomes write protection function.
The CS pin need not be high level during automatic write time-out period (BUSY status).
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Read
The read instruction is the only instruction which outputs serial data on the DO pin. When the 17th falling
edge of SK is received , the DO pin will come out of high impedance state and shift out the data from D15 first
in descending order which is located at the address specified in the instruction.
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
AK6420A • • When the highest address is reached ($7F), the address counter rolls over to
address $00 allowing the read cycle to be continued indefinitely.
AK6440A • •When the highest address is reached ($FF), the address counter rolls over to
address $00 allowing the read cycle to be continued indefinitely.
AK6480A • •When the highest address is reached ($1FF), the address counter rolls over to
address $000 allowing the read cycle to be continued indefinitely.
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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WREN / WRDS ( Write Enable and Write Disable )
When Vcc is applied to the part, it powers up in the programming disable (WRDS) state. Programming must
be preceded by a programming enable (WREN) instruction. Programming remains enabled until a
programming disable (WRDS) instruction is executed or Vcc is removed from the part. The programming
disable instruction is provided to protect against accidental data disturb . Execution of a read instruction is not
affected by both WREN and WRDS instructions.
WREN/WRDS (AK6420A/40A/80A)
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Power Supply VCC -0.6 +7.0 V
All Input Voltages
with Respect to Ground VIO -0.6 VCC+0.6 V
Ambient storage temperature Tst -65 +150 °C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum conditions for extended
periods may affect device reliability.
Recommended Operating Condition
Parameter Symbol Min Max Unit
Power Supply VCC 1.8 5.5 V
Ambient Operating Temperature Ta -40 +85 °C
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS ( 1.8V≤Vcc≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
ICC1 VCC=5.5V, tSKP=500ns, *1 4.0 mA
6420A 2.0 mAICC2 VCC=2.5V, *1
tSKP=500ns 6440A/80A 2.5 mA
6420A 1.5 mA
Current Dissipation
(WRITE)
ICC3 VCC=1.8V, *1
tSKP=1.5us 6440A/80A 2.0 mA
ICC4 VCC=5.5V, tSKP=500ns, *1 0.75 mA
ICC5 VCC=2.5V, tSKP=500ns, *1 0.3 mA
Current Dissipation
(READ,WREN,
WRDS) ICC6 VCC=1. 8V, tSKP=1.5us, *1 0. 15 mA
Current Dissipation
(Standby) ICCSB VCC=5.5V *2 0.8 uA
Input High Voltage1
CS, SK, RESET pin VIH1 1.8V≤VCC≤5.5V 0.8 Õ VCC VCC+0.5 V
VIH2 2.5V≤VCC≤5.5V 0.7 Õ VCC VCC+0.5 VInput High Voltage2
DI pin VIH3 1.8V≤VCC<2.5V 0.8 Õ VCC VCC+0.5 V
Input Low Vo lt age1
CS, SK, RESET pin VIL1 1.8V≤VCC≤5.5V 00.2ÕVCC V
VIL2 2.5V≤VCC≤5.5V 00.3 Õ VCC VInput Low Volt age2
DI pin VIL3 1.8V≤VCC<2.5V 00.2 Õ VCC V
VOH1 2.5V≤VCC≤5.5V
IOH=-50
µ
AVCC-0.3 V
Output High Volt age
VOH2 1.8V≤VCC<2.5V
IOH=-50
µ
AVCC-0.3 V
VOL1 2.5V≤VCC≤5.5V
IOL=1.0mA 0.4 VOutput Low Voltage
VOL2 1.8V≤VCC<2.5V
IOL=0.1mA 0.4 V
Input Leakage ILI VCC=5.5V, VI N=5.5V 1.0 uA
Output Leakage ILO VCC=5.5V
VOUT=5.5V, CS=VCC 1.0 uA
*1: VIN=VIH/VIL,DO=RDY/BUSY=Open
*2: CS=Vcc, SK/DI/RESET=Vcc/GND,DO=RDY/BUSY=Open
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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(2) A.C. ELECTRICAL CHARACTERISTICS ( 1.8V≤Vcc≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
tSKP1 2.5V≤VCC≤5.5V 500 nsSK Cycle Time
tSKP2 1.8V≤VCC<2.5V 1.5 us
tSKW1 2.5V≤VCC≤5.5V 250 nsSK Pulse Width
tSKW2 1.8V≤VCC<2.5V 750 ns
tSKH1 4.5V≤VCC≤5.5V 250 ns
tSKH2 2.5V≤VCC<4.5V 500 ns
SK High Pulse Widt h
*3 tSKH3 1.8V≤VCC<2.5V 750 ns
CS Setup Time tCSS 100 ns
CS Hold Time tCSH 100 ns
SK Setup Time tSKSH
/tSKSL 100 ns
RESET Setup Tim e tRESS 0 ns
RESET Hold Time tRESH 0 ns
tDIS1 4.5V≤VCC≤5.5V 100 nsData Setup Time
tDIS2 1.8V≤VCC<4.5V 200 ns
tDIH1 4.5V≤VCC≤5.5V 100 nsData Hold Time
tDIH2 1.8V≤VCC<4.5V 200 ns
tPD1 4.5V≤VCC≤5.5V, *4 150 ns
tPD2 2.5V≤VCC<4.5V, *4 300 ns
DO pin
Output delay tPD3 1.8V≤VCC<2.5V. *4 500 ns
RDY/BUSY pin
Output delay
tPD CL=100pF 1 us
Selftim ed Programming
Time
tE/W 10 ms
Wr ite Recovery Time tRC 100 ns
Min CS High Time tCS 250 ns
DO High-Z Time tOZ 500 ns
*3: tSKH is the high pulse width of 16th SK pulse in READ operation. When the data in the next
address are read sequentially by continuing to provide clock, tSKH are applied to the high
pulse width of 32nd and 48th (multiple of 16) SK pulse in READ operation.
*4: CL=100pF
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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Synchronous Data Timing
Instruction Input
(note) * = "A0" for AK6420A, "A1" for AK6440A/80A
+ = "0" f or AK6420A, "A0" for AK6440A/80A
Data Output (READ)
ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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ASAHI KAS EI [AK6420A/ 40 A/8 0A]
DAS01E-00 1999/05
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IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to funct ion or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
