SAR Control
DOUT
Comparator
S/H Amp CS/SHDN
DCLOCK
+IN
VREF
–IN
CDAC
Serial
Interface
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
16-BIT, HIGH-SPEED, 2.7-V TO 5-V, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8320-HT
1FEATURES SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
2• 100-kHz Sampling Rate • Controlled Baseline
• Micropower: • One Assembly/Test Site
– 3.8 mW at 100 kHz and 2.7 V • One Fabrication Site
– 0.3 mW at 10 kHz and 2.7 V • Available in Extreme (–55°C/210°C)
• Power Down: 6 µA max Temperature Range(1)
• 8-Pin Ceramic Package • Extended Product Life Cycle
• Pin Compatible to ADS7816 and ADS7822 • Extended Product-Change Notification
• Serial ( SPI™/SSI) Interface • Product Traceability
APPLICATIONS • Texas Instruments' high temperature products
utilize highly optimized silicon (die) solutions
• Down-Hole Drilling with design and process enhancements to
• High Temperature Environments maximize performance over extended
• Vibration/Modal Analysis temperatures.
• Multi-Channel Data Acquisition
• Acoustics/Dynamic Strain Gauges
• Pressure Sensors (1) Custom temperature ranges available
DESCRIPTION
The ADS8320 is a 16-bit, sampling analog-to-digital (A/D) converter with ensured specifications over a 2.7-V to
5.25-V supply range. It requires very little power even when operating at the full 100-kHz data rate. At lower data
rates, the high speed of the device enables it to spend most of its time in the power-down mode—the average
power dissipation is less than 100 mW at 10-kHz data rate.
The ADS8320 also features operation from 2 V to 5.25 V, a synchronous serial (SPI/SSI compatible) interface,
and a differential input. The reference voltage can be set to any level within the range of 500 mV to VCC.
Ultra-low power and small size make the ADS8320 ideal for portable and battery-operated systems. It is also a
perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data
acquisition. The ADS8320 is available in 8-pin ceramic surface-mount packages, specified for the –55°C to
210°C temperature range.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola, Inc..
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
a
b
c
d
Origin
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TAPackage ORDERABLE PART NUMBER TOP-SIDE MARKING
HKJ ADS8320SHKJ ADS8320SHKJ
–55°C to 210°C HKQ ADS8320SHKQ ADS8320SHKQ
KGD ADS8320SKGD1 NA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
BARE DIE INFORMATION
BACKSIDE BOND PAD
DIE THICKNESS BACKSIDE FINISH POTENTIAL METALLIZATION COMPOSITION
15 mils Silicon backgrind GND Al-Si-Cu
2Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
VREF
+IN
-IN
GND CSn/SHDN
Dout
DCLOCK
+Vcc
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
Table 1. Bond Pad Coordinates in Microns - Rev A
DISCRIPTION PAD NUMBER a b c d
VREF 1 157.3 1437.4 259.5 1669.6
+IN 2 157.3 1149.4 256.6 1248.7
-IN 3 157.3 432.3 256.6 531.6
GND 4 171.2 137.4 270.4 366.6
CS/SHDN 5 1183.1 141.3 1282.4 240.6
DOUT 6 1183.1 448.6 1282.4 547.8
DCLOCK 7 1183.1 1011.1 1282.4 1110.4
+VCC 8 1183.1 1462.8 1282.4 1692
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): ADS8320-HT
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
UNIT
VCC 6 V
Analog input voltage -0.3 to 6 V
Case temperature 100 °C
Junction temperature –55 to 210 °C
Storage temperature –55 to 210 °C
External referance voltage 5.5 V
Input current to any pin except supply ±10 mA
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS FOR HKJ OR HKQ PACKAGE
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
to ceramic side of case 5.7
θJC Junction-to-case thermal resistance °C/W
to top of case lid (metal side of case) 13.7
ELECTRICAL CHARACTERISTICS
VCC = 2.7 V, VREF = 2.5 V, -IN = GND, fSAMPLE = 100 kHz and fCLK = 24 x fSAMPLE, unless otherwise noted.
CONDITIONS TA= -55°C to 125°C TA= 210°C(1) UNIT
PARAMETER MIN TYP MAX MIN TYP MAX
Resolution 16 16 Bits
Analog Input
Full-zcale input span +IN – (–IN) 0 VREF 0 VREF V
+IN –0.1 VCC + 0.1 –0.1 VCC + 0.1
Absolute input range V
–IN –0.1 0.5 –0.1 0.5
Capacitance 45 45 pF
Leakage current 1 1 nA
System Performance
No missing codes 14 14 Bits
Integral linearity error ±0.008 ±0.032 ±0.018 ±0.034 % of FSR
Offset error VIN = 3 V ±0.6 ±3.8 ±0.5 ±3.8 mV
Offset temperature drift VIN = 3 V ±3 ±4 μV/°C
Gain error VIN = 3 V ±0.05 ±0.05 % of FSR
Gain temperature drift VIN = 3 V ±0.3 ±0.3 ppm/°C
Noise 20 21 μVrms
Power-supply rejection ratio 2.7 V < VCC < 3.3 V 3 5 LSB(2)
(1) Minimum and maximum parameters are characterized for operation at TA= 210°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) LSB means least significant bit. With VREF = 2.5 V, one LSB is 0.038 V.
4Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
VCC = 2.7 V, VREF = 2.5 V, -IN = GND, fSAMPLE = 100 kHz and fCLK = 24 x fSAMPLE, unless otherwise noted.
CONDITIONS TA= -55°C to 125°C TA= 210°C(1) UNIT
PARAMETER MIN TYP MAX MIN TYP MAX
Sampling Dynamics
Conversion time 16 16 Clk cycles
Acquisition time 4.5 4.5 Clk cycles
Throughput rate 100 100 kHz
Clock frequency range 0.02 2.4 0.02 2.4 MHz
Dynamic Characteristics
Total harmonic distortion VIN = 2.7 x Vp-p at 1 kHz -86 -82 dB
SINAD VIN = 2.7 x Vp-p at 1 kHz 84 79 dB
Spurious-free dynamic range VIN = 2.7 x Vp-p at 1 kHz 86 82 dB
SNR 88 83 dB
Reference Input
Voltage range 0.5 VCC 0.5 VCC V
CS = GND, fSAMPLE = 0 Hz 5 5
Resistance GΩ
CS = VCC 5 5
20 50 25 55
Current drain µA
CS = VCC 0.1 7 0.9 12
Digital Input/Output
Logic family CMOS CMOS
VIH IIH = 5 µA 2 VCC + 0.3 2 VCC + 0.3 V
VIL IIL = 5 µA -0.3 0.8 -0.3 0.8 V
Logic Levels VOH IOH = –250 µA 2.1 2.1 V
VOL IOL = 250 µA 0.4 0.4 V
Data format Straight binary
Power Supply Requirements
VCC Specified performance 2.7 3.3 2.7 3.3 V
2 5.25 2 5.25
VCC range(3) V
See (4) 2 2.7 2 2.7
850 1300 650 1300
Quiescent current µA
fSAMPLE = 10 kHz(5)(6) 100 100
Power dissipation 2.3 3.8 1.75 3.8 mW
Power-down CS = VCC 0.3 4 6 µA
Temperature Range
Specified performance -55 125 -55 210 °C
(3) See the Typical Performance Curves for more information.
(4) The maximum clock rate of the ADS8320 is less than 2.4 MHz in this power supply range.
(5) fCLK = 2.4 MHz, CS = VCC for 216 clock cycles out of every 240.
(6) See the Power Dissipation section for more information regarding lower sample rates.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS8320-HT
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC = 5 V, VREF = 5 V, -IN = GND, fSAMPLE = 100 kHz and fCLK = 24 x fSAMPLE, unless otherwise noted.
CONDITIONS TA= -55°C to 125°C TA= 210°C(1) UNIT
PARAMETER MIN TYP MAX MIN TYP MAX
Resolution 16 16 Bits
Analog Input
Full-zcale input span +IN – (–IN) 0 VREF 0 VREF V
+IN –0.1 VCC + 0.1 –0.1 VCC + 0.1
Absolute input range V
–IN –0.1 0.5 –0.1 0.5
Capacitance 45 45 pF
Leakage current 1 1 nA
System Performance
No missing codes 14 14 Bits
Integral linearity error ±0.008 ±0.032 ±0.018 ±0.034 % of FSR
Offset error ±0.6 ±3.8 ±0.5 ±3.8 mV
Offset temperature drift ±3 ±4 μV/°C
Gain error ±0.05 ±0.05 % of FSR
Gain temperature drift ±0.3 ±0.3 ppm/°C
Noise 20 21 μVrms
Power-supply rejection ratio 4.7 V < VCC < 5.25 V 3 35 LSB(2)
Sampling Dynamics
Conversion time 16 16 Clk cycles
Acquisition time 4.5 4.5 Clk cycles
Throughput rate 100 100 kHz
Clock frequency range 0.02 2.4 0.02 2.4 MHz
Dynamic Characteristics
Total harmonic distortion VIN = 5 x Vp-p at 10 kHz -84 -83 dB
SINAD VIN = 5 x Vp-p at 10 kHz 82 81 dB
Spurious-free dynamic range VIN = 5 x Vp-p at 10 kHz 84 83 dB
SNR 90 88 dB
Reference Input
Voltage range 0.5 VCC 0.5 VCC V
CS = GND, fSAMPLE = 0 Hz 5 5
Resistance GΩ
CS = VCC 5 5
40 80 50 80
Current drain fSAMPLE = 10 kHz 0.8 0.8 µA
CS = VCC 0.1 5 2 5
Digital Input/Output
Logic family CMOS CMOS
VIH IIH = 5 µA 3 VCC + 0.3 3 VCC + 0.3 V
VIL IIL = 5 µA -0.3 0.8 -0.3 0.8 V
Logic Levels VOH IOH = –250 µA 4 4 V
VOL IOL = 250 µA 0.4 0.4 V
Data format Straight binary
(1) Minimum and maximum parameters are characterized for operation at TA= 210°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) LSB means least significant bit. With VREF = 5 V, one LSB is 0.076 V.
6Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
1
2
3
4
8
7
6
5
+V
CC
DCLOCK
D
OUT
CS/SHDN
V
REF
+IN
–IN
GND
ADS8320
HKJ PACKAGE
(TOP VIEW)
HKQ PACKAGE
(TOP VIEW)
8
54
1
HKQ as formed or HKJ mounted dead bug
V
REF
+IN
-IN
GND
+V
CC
DCLOCK
D
OUT
CS/SHDN
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
VCC = 5 V, VREF = 5 V, -IN = GND, fSAMPLE = 100 kHz and fCLK = 24 x fSAMPLE, unless otherwise noted.
CONDITIONS TA= -55°C to 125°C TA= 210°C(1) UNIT
PARAMETER MIN TYP MAX MIN TYP MAX
Power Supply Requirements
VCC Specified performance 4.75 5.25 4.75 5.25 V
VCC range(3) 2 5.25 2 5.25 V
1150 1700 850 1700
Quiescent current µA
fSAMPLE = 10 kHz(4)(5) 200 200
Power dissipation 5.5 8.5 4.5 8.5 mW
Power-down CS = VCC 0.3 3 5 µA
Temperature Range
Specified performance -55 125 -55 210 °C
(3) See the Typical Performance Curves for more information.
(4) fCLK = 2.4 MHz, CS = VCC for 216 clock cycles out of every 240.
(5) See the Power Dissipation section for more information regarding lower sample rates.
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN # NAME DESCRIPTION
1 VREF Reference input
2 +IN Noninverting input
3 -IN Inverting input. Connect to ground or to remote ground sense point.
4 GND Ground
5 CS/SHDN Chip select when LOW, shutdown mode when HIGH.
The serial output data word is comprised of 16 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
6 DOUT second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 16
edges.
7 DCLOCK Data clock synchronizes the serial data transfer and determines conversion speed.
8 +VCC Power supply
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): ADS8320-HT
2 0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
Integral Linearity Error (LSB)
0000H8000HC000H
4000HFFFFH
Hex Code
3.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
Differential Linearity Error (LSB)
0000H8000HC000H
4000HFFFFH
Hex Code
0
200
400
600
800
1000
1200
1400
−55 0 55 110 165 220
Temperature (°C)
Supply Current (µA)
5V
2.7V
−1000
0
1000
2000
3000
4000
5000
6000
−55 0 55 110 165 220
Temperature (°C)
Supply Current (nA)
5V
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
xxx TYPICAL CHARACTERISTICS
At TA= 25°C, VCC = 5 V, VREF = 5 V, fSAMPLE = 100 kHz, and fCLK = 24 x fSAMPLE, unless otherwise specified.
INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs vs
CODE (25°C) CODE (25°C)
Figure 1. Figure 2.
SUPPLY CURRENT POWER-DOWN SUPPLY CURRENT
vs vs
TEMPERATURE TEMPERATURE
Figure 3. Figure 4.
8Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
1000
100
10
1
Sample Rate (kHz)
12345
VCC (V)
6
5
4
3
2
1
0
–1
–2
–3
Change in Offset (LSB)
1 2 3 4 5
Reference Voltage (V)
VCC = 5V
−55 0 55 110 165 220
−6
−5
−4
−3
−2
−1
0
1
Temperature (°C)
Delta from 25°C (LSB)
2.7V
5V
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 5 V, VREF = 5 V, fSAMPLE = 100 kHz, and fCLK = 24 x fSAMPLE, unless otherwise specified.
QUIESCENT CURRENT MAXIMUM SAMPLE RATE
vs vs
VCC VCC
Figure 5. Figure 6.
CHANGE IN OFFSET CHANGE IN OFFSET
vs vs
REFERENCE VOLTAGE TEMPERATURE
Figure 7. Figure 8.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): ADS8320-HT
5
4
3
2
1
0
–1
–2
Change in Gain (LSB)
12345
Reference Voltage (V)
VCC = 5V
−55 0 55 110 165 220
−7
−6
−5
−4
−3
−2
−1
0
1
Temperature (°C)
Delta from 25°C (LSB)
2.7V
5V
0
–20
–40
–60
–80
–100
–120
–140
Amplitude (dB)
Frequency (kHz)
0 10 20 30 40 50
10
9
8
7
6
5
4
3
2
1
0
Peak-to-Peak Noise (LSB)
Reference Voltage (V)
VCC = 5V
0.1 110
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 5 V, VREF = 5 V, fSAMPLE = 100 kHz, and fCLK = 24 x fSAMPLE, unless otherwise specified.
CHANGE IN GAIN CHANGE IN GAIN
vs vs
REFERENCE VOLTAGE TEMPERATURE
Figure 9. Figure 10.
PEAK-TO-PEAK NOISE
FREQUENCY SPECTRUM vs
(8192 Point FFT, FIN = 10.120 kHz, –0.3 dB) REFERENCE VOLTAGE
Figure 11. Figure 12.
10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
100
90
80
70
60
50
40
30
20
10
0
Spurious-Free Dynamic Range
and Signal-to-Noise Ratio (dB)
50
Frequency (kHz)
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
110 100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Total Harmonic Distortion (dB)
Frequency (kHz)
110 100
100
90
80
70
60
50
40
30
20
10
0
Signal-to-(Noise + Distortion) (dB)
Frequency (kHz)
110 50 100
90
80
70
60
50
40
30
20
Signal-to-(Noise + Distortion) (dB)
–40 –35 –30 –25 –20 –15 –10 –5 0
Input Level (dB)
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 5 V, VREF = 5 V, fSAMPLE = 100 kHz, and fCLK = 24 x fSAMPLE, unless otherwise specified.
SPURIOUS-FREE DYNAMIC RANGE AND SIGNAL-TO-
NOISE RATIO TOTAL HARMONIC DISTORTION
vs vs
FREQUENCY FREQUENCY
Figure 13. Figure 14.
SIGNAL-TO-(NOISE + DISTORTION) SIGNAL-TO-(NOISE + DISTORTION)
vs vs
FREQUENCY INPUT LEVEL
Figure 15. Figure 16.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): ADS8320-HT
70
60
50
40
30
20
10
0
Reference Current (µA)
Sample Rate (kHz)
5V
2.7V
0 20 40 60 80 100
10
20
30
40
50
60
70
−55 0 55 110 165 220
Temperature (°C)
Reference Current (µA)
5V
2.7V
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= 25°C, VCC = 5 V, VREF = 5 V, fSAMPLE = 100 kHz, and fCLK = 24 x fSAMPLE, unless otherwise specified.
REFERENCE CURRENT REFERENCE CURRENT
vs vs
SAMPLE RATE TEMPERATURE
Figure 17. Figure 18.
12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
THEORY OF OPERATION
The ADS8320 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The
architecture is based on capacitive redistribution, which inherently includes a sample/hold function. The converter
is fabricated on a 0.6μCMOS process. The architecture and process allow the ADS8320 to acquire and convert
an analog signal at up to 100,000 conversions per second while consuming less than 4.5 mW from+VCC.
The ADS8320 requires an external reference, an external clock, and a single power source (VCC). The external
reference can be any voltage between 500 mV and VCC. The value of the reference voltage directly sets the
range of the analog input. The reference input current depends on the conversion rate of the ADS8320.
The external clock can vary between 24 kHz (1-kHz throughput) and 2.4 MHz (100-kHz throughput). The duty
cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200 ns
(VCC = 2.7 V or greater). The minimum clock frequency is set by the leakage on the capacitors internal to the
ADS8320.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant
bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in
progress—there is no pipeline delay. It is possible to continue to clock the ADS8320 after the conversion is
complete and to obtain the serial data least significant bit first. See the digital timing section for more information.
ANALOG INPUT
The +IN and –IN input pins allow for a differential input signal. Unlike some converters of this type, the –IN input
is not re-sampled later in the conversion cycle. When the converter goes into the hold mode, the voltage
difference between +IN and –IN is captured on the internal capacitor array.
The range of the –IN input is limited to –0.1 V to 1 V (–0.1 V to 0.5 V when using a 2.7-V supply). Because of
this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –IN
input is best used to sense a remote signal ground that may move slightly with respect to the local ground
potential.
The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source
impedance, and power-down mode. Essentially, the current into the ADS8320 charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling
level within 4.5 clock cycles. When the converter goes into the hold mode or while it is in the powerdown mode,
the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
–IN input should not drop below GND – 100 mV or exceed GND + 1 V. The +IN input should always remain
within the range of GND – 100 mV to VCC + 100 mV. Outside of these ranges, the converter linearity may not
meet specifications. To minimize noise, low bandwidth input signals with lowpass filters should be used.
REFERENCE INPUT
The external reference sets the analog input range. The ADS8320 operates with a reference in the range of
500 mV to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is
often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536.
This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB
size, as the reference voltage is reduced.
The noise inherent in the converter also appears to increase with lower LSB size. With a 5-V reference, the
internal noise of the converter typically contributes only 1.5 LSB peak-to-peak of potential error to the output
code. When the external reference is 500 mV, the potential error contribution from the internal noise will be 10
times larger—15 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by
averaging consecutive conversion results.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS8320-HT
SINAD = ENOB6.02 + 1.76·
2
2510
3
2490
4
Code
5 6
0 00 0
1
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
For more information regarding noise, consult the typical performance curve “Peak-to-Peak Noise vs Reference
Voltage.” Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-
(noise + distortion) ratio with a 1-kHz, 0-dB input signal. SINAD is related to ENOB as follows: (1)
With lower reference voltages, extra care should be taken to provide a clean layout including adequate
bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is
lower, the converter is also more sensitive to external sources of error such as nearby digital signals and
electromagnetic interference.
NOISE
The noise floor of the ADS8320 itself is extremely low, as can be seen in Figure 19 and Figure 20, and is much
lower than competing A/D converters. It was tested by applying a lownoise DC input and a 5-V reference to the
ADS8320 and initiating 5000 conversions. The digital output of the A/D converter varies in output code due to the
internal noise of the ADS8320. This is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the
output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal
code for the input value. The ±1σ, ±2σand ±3σdistributions represents the 68.3%, 95.5%, and 99.7%,
respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6
and this yields the ±3σdistribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the
distribution when executing 1000 conversions. The ADS8320, with < 3 output codes for ±3σdistribution, yields a
< ±0.5 LSB transition noise. Remember, to achieve this low noise performance, the peak-to-peak noise of the
input signal and reference must be < 50 µV.
Figure 19. Histogram of 5000 Conversions of a DC Input at the Code Transition
14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
2
72
3
4864
4
Code
5 6
64 00 0
1
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
Figure 20. Histogram of 5000 Conversions of a DC Input at the Code Center
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS8320-HT
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
DIGITAL INTERFACE
SIGNAL LEVELS
The digital inputs of the ADS8320 can accommodate logic levels up to 5.5 V regardless of the value of VCC.
Thus, the ADS8320 can be powered at 3 V and still accept inputs from logic powered at 5 V.
The CMOS digital output (DOUT) swings 0 V to VCC. If VCC is 3 V and this output is connected to a 5-V CMOS
logic input, then that IC may require more supply current than normal and may have a slightly longer propagation
delay.
SERIAL INTERFACE
The ADS8320 communicates with microprocessors and other digital systems via a synchronous 3-wire serial
interface, as shown in Figure 21 and Table 2. The DCLOCK signal synchronizes the data transfer with each bit
being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising
edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge
of DCLOCK to capture each bit.
A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion
cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and outputs a
LOW value for one clock period. For the next 16 DCLOCK periods, DOUT outputs the conversion result, most
significant bit first. After the least significant bit (B0) has been output, subsequent clocks repeat the output data
but in a least significant bit first format.
After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect
on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW.
Table 2. Timing Specifications (VCC = 2.7 V and Above, –55°C to 210°C)
SYMBOL DESCRIPTION MIN TYP MAX UNIT
tSMPL Analog input sample time 4.5 5 Clk cycles
tCONV Conversion time 16 Clk cycles
tCYC Throughput rate 100 kHz
tCSD CS falling to DCLOCK LOW 0 ns
tSUCS CS falling to DCLOCK Rising 20 ns
thDO DCLOCK falling to current DOUT not valid 5 15 ns
tdDO DCLOCK falling to next DOUT valid 30 50 ns
tdis CS rising to DOUT tri-state 70 100 ns
ten DCLOCK falling to DOUT enabled 20 50 ns
tfDOUT fall time 5 25 ns
trDOUT rise time 7 25 ns
DATA FORMAT
The output data from the ADS8320 is in straight binary format, as shown in Table 3. This table represents the
ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise.
Table 3. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION ANALOG VALUE BINARY CODE HEX CODE
Full-scale range VREF
Least significant bit (LSB) VREF/65,536
Full scale VREF – 1 LSB 1111 1111 1111 1111 FFFF
Midscale VREF/2 1000 0000 0000 0000 8000
Midscale – 1 LSB VREF/2 – 1 LSB 0111 1111 1111 1111 7FFF
Zero 0 V 0000 0000 0000 0000 0000
16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
CS/SHDN
DOUT
DCLOCK
Complete Cycle
Power Down
ConversionSample
Use positive clock edge for data transfer
tSUCS
tCONV
tSMPL
NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
B15
(MSB) (LSB)
B7 B1B6 B2
B5 B3
B4
Hi-Z
0Hi-Z
tCSD
B14 B13 B12 B11 B10 B9 B8 B0
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrication process, and a careful design allow the
ADS8320 to convert at up to a 100-kHz rate while requiring very little power. Still, for the absolute lowest power
dissipation, there are several things to keep in mind.
The power dissipation of the ADS8320 scales directly with conversion rate. Therefore, the first step to achieving
the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system.
In addition, the ADS8320 is in power-down mode under two conditions: when the conversion is complete and
whenever CS is HIGH (as shown in Figure 21). Ideally, each conversion should occur as quickly as possible,
preferably at a 2.4-MHz clock rate. This way, the converter spends the longest possible time in the power-down
mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for
digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The
analog section dissipates power continuously, until the power-down mode is entered.
Figure 21. ADS8320 Basic Timing Diagrams
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS8320-HT
DOUT
1.4V
Test Point
3kΩ
100pF
CLOAD
Load Circuit for tdDO, tr, and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Voltage Waveforms for DOUT Delay Times, tdDO
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
Voltage Waveforms for ten
Load Circuit for tdis and ten
tr
DOUT
VOH
VOL
tf
DOUT
Test Point
tdis Waveform 2, ten
VCC
tdis Waveform 1
100pF
CLOAD
3kΩ
tdis
CS/SHDN
DOUT
Waveform 1(1)
DOUT
Waveform 2(2)
90%
10%
VIH
41
B11
5
ten
CS/SHDN
DCLOCK
VOL
DOUT
tdDO
DOUT
DCLOCK
VOH
VOL
VIL
thDO
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
Figure 22. Timing Diagrams and Test Circuits for the Parameters in Table 2
Figure 23 shows the current consumption of the ADS8320 versus sample rate. For this graph, the converter is
clocked at 2.4 MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 24 also
shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/24th of the
sample period—CS is HIGH for one DCLOCK cycle out of every 16.
18 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
1000
100
10
1
Supply Current (µA)
Sample Rate (kHz)
VCC = 5.0V
VREF = 5.0V
VCC = 2.7V
VREF = 2.5V
TA= 25°C
fCLK = 2.4MHz
0.1 110 100
1000
100
10
1
Supply Current (µA)
Sample Rate (kHz)
TA= 25°C
VCC = 5.0V
VREF = 5.0V
fCLK = 24 • fSAMPLE
0.1 110 100
1000
800
600
400
200
0.0
0.00
Supply Current (mA)
Sample Rate (kHz)
T
A
= 25 C°
V
CC
= 5.0V
V
REF
= 5.0V
f
CLK
= 24 • f
SAMPLE
CS LOW (GND)
CS HIGH (V
CC
)
0.250
0.1 110 100
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
Figure 23. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly With
Sample Rate
Figure 24. Scaling fCLK Reduces Supply Current Only Slightly With Sample Rate
There is an important distinction between the power-down mode that is entered after a conversion is complete
and the full power-down mode which is enabled when CS is HIGH. CS LOW will shut down only the analog
section. The digital section is completely shut down only when CS is HIGH. Thus, if CS is left LOW at the end of
a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is
HIGH. Figure 25 shows more information.
Figure 25. Shutdown Current With CS HIGH is 50 nA Typically, Regardless of the Clock. Shutdown
Current With CS LOW Varies With Sample Rate
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS8320-HT
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
Power dissipation can also be reduced by lowering the power-supply voltage and the reference voltage. The
ADS8320 operates over a VCC range of 2.0 V to 5.25 V. However, at voltages below 2.7 V, the converter will not
run at a 100-kHz sample rate. See the typical performance curves for more information regarding power supply
voltage and maximum sample rate.
SHORT CYCLING
Another way of saving power is to utilize the CS signal to short cycle the conversion. Because the ADS8320
places the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term
means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result
are needed, then the conversion can be terminated (by pulling CS HIGH) after the 14th bit has been clocked out.
This technique can be used to lower the power dissipation (or to increase the conversion rate) in those
applications where an analog signal is being monitored until some condition becomes true. For example, if the
signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion
can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation
in both the converter and the rest of the system, as they spend more time in the power-down mode.
20 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
ADS8320-HT
www.ti.com
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
LAYOUT(1)
For optimum performance, care should be taken with the physical layout of the ADS8320 circuitry. This is
particularly true if the reference voltage is low and/or the conversion rate is high. At a 100-kHz conversion rate,
the ADS8320 makes a bit decision every 416 ns. That is, for each subsequent bit decision, the digital output
must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged,
and the input to the comparator settled to a 16-bit level all within one clock cycle.
The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that
occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter,
there are n “windows” in which large external transient voltages can easily affect the conversion result. Such
spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This
particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter
DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic
misoperation.
With this in mind, power to the ADS8320 should be clean and well bypassed. A 0.1-μF ceramic bypass capacitor
should be placed as close to the ADS8320 package as possible. In addition, a 1-μF to 10-μF capacitor and a 5-Ω
or 10-Ωseries resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1-μF capacitor. Again, a series resistor and large capacitor
can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, be
careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this
case). Keep in mind that while the ADS8320 draws very little current from the reference on average, there are
still instantaneous current demands placed on the external input and reference circuitry.
Texas Instruments' OPA627 op amp provides optimum performance for buffering both the signal and reference
inputs. For low-cost, low-voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are
recommended.
Also, keep in mind that the ADS8320 offers no inherent rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz), can be difficult
to remove.
The GND pin on the ADS8320 should be placed on a clean ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection
point. The ideal layout includes an analog ground plane for the converter and associated analog circuitry.
(1) OPA627, OPA2350 and OPA2340 have not been characterized or tested at 210°C.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): ADS8320-HT
ADS8320
VCC
CS
DOUT
DCLOCK
VREF
+IN
–IN
GND
+
+
5Ω
1µF to
10µF
1µF to
10µF
0.1µF
Microcontroller
2.7V to 5.25V
ADS8320-HT
SBAS521A –DECEMBER 2010–REVISED APRIL 2012
www.ti.com
APPLICATION CIRCUITS
Figure 26 shows a basic data acquisition system. The ADS8320 input range is 0 V to VCC, as the reference input
is connected directly to the power supply. The 5-Ωresistor and 1-μF to 10-μF capacitor filter the microcontroller
“noise” on the supply, as well as any high-frequency noise from the supply itself. The exact values should be
picked such that the filter provides adequate rejection of the noise.
Figure 26. Basic Data Acquisition System
22 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS8320-HT
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS8320SHKJ ACTIVE CFP HKJ 8 1 TBD Call TI N / A for Pkg Type
ADS8320SHKQ ACTIVE CFP HKQ 8 1 TBD AU N / A for Pkg Type
ADS8320SKGD1 ACTIVE XCEPT KGD 0 240 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS8320-HT :
•Catalog: ADS8320
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 29-Aug-2012
Addendum-Page 2
•Catalog - TI's standard catalog product
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated