UltraLogic™ High-Density Flash CPLDs
CPLD Family
FLASH370™
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 20, 2000
Features
• Flash erasab le CMOS CPLDs
• High density
—32–128 m acrocell s
—32–128 I/O pins
—Multiple clock pins
• Bus Hold capabilities on all I/Os and dedicat ed input s
• High speed
—tPD = 8 .5–12 ns
—tS = 5–7 ns
—tCO = 6–7 ns
•Fast Progra mmable Interconnect Matrix ( PIM)
—Uniform predi ctable delay, independent of routing
• Intell igent product ter m allocator
—0–16 product terms to any macrocell
—Provides product term st eering on an individual
basis
—Provides product term sharing among local
macrocells
—Doesn’t strand macrocells
• Sim ple t iming model
—No fanout del ays
—No e xpander delays
—No dedicated vs. I /O pin delays
—No ad dit ional delay thr ough PI M
—No penalty for using full 16 product terms
—No delay for steering or sharing product terms
• Flexible clocking
—2–4 clock pins per devi ce
—Clock polarity cont rol
• Sec uri ty bit and user I D supported
• Packages
—44–160 pins
—PLCC, CLCC, PGA, and TQFP packages
General Description
The FLASH370™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
performance. Eac h mem ber of the fam il y is designed with Cy-
press’s state -of -the-art Flas h technolog y . All of the de vices are
electric all y erasable and reprogr am m able, simpli fying product
inventory and reduci ng costs.
The FLASH370 family is designed to bring the flexibility, ease
of use and performance of the 22V10 to high-density CPLDs.
The architectur e is bas ed on a number of logic block s that are
connected by a Programmable Interconnect Matrix (PIM).
Each logic block features it s own product term array, product
term allocator array, and 16 macrocells. The PIM distributes
signals from one logic block to another as well as all inputs
from pins.
The family features a wide variet y of densities and pin counts
to choose from. At each density there are two packaging op-
tions to choose from—one that is I/O intensive and another
that is register intensive. For example, the CY7C374 and
CY7C375 both feature 128 macrocells. On the CY7C374,
availa ble in an 84-pin pac kage, ha lf of the macrocells are bur -
ied and half are available on I/O pins. On t he CY7C375 all of
the macrocell s are fed to I/O pins and the device is available
in the 160-pin pac kage. Fi gure 1 sh ows a blo c k diag ra m of the
CY7C374/5.
Functional Descri pti on
Program mable Interc onnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals fr om I/O pins and
feedbacks from the logic blocks. The PIM is an extremely ro-
bust interconnect that avoids fitting and density limitations.
Routing is automatically accomplished by software and the
propagation delay through the PIM is transparent to t he user.
Signal s from an y pi n or an y l ogic b loc k can be routed t o any o r
all logic b lock s.
Table 1. FLASH370 Select ion Guid e
Device Pins Macrocells Dedi cated Inputs I/O Pins Flip-Flops Speed (tPD)Speed (fMAX)
371 44 32 632 44 8.5 143
372 44 64 632 76 10 125
373 84 64 664 76 10 125
374 84 128 664 140 12 100
375 160 128 6128 140 12 100
CPLD Family
FLASH370™
2
Functional Description (c ontinued)
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
num ber of PIM inputs i ncr eases wi th pin count an d t he num ber
of logic blocks. The outputs from the PIM are signals rout ed to
the appropriate logic block(s). Each logic block receives 36
input s fr om the PIM and the ir compl ements , a llo wing f or 3 2-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also im-
proves t he routing capacit y of the FLASH370 fami ly.
An important fe ature of the PI M inv ol ves ti ming. The prop aga-
ti on dela y th rough the PI M is accounte d for in the tim ing spec-
ificati ons for each device. There is no addit ional delay for trav-
eli ng thr ough the PIM. I n f act , al l i nputs tr av e l th rough t he PIM.
Likewise, ther e are no route-dependent timing parameters on
the FLASH370 devi ces. The worst-case PIM delays are incor-
porated in all appropriate FLASH370 specifications.
Routing signals through the PIM is completely invisible to the
user . All rou ting is a ccomplished by so ftware—no hand r outing
is necessary. Warp™ and t hird-part y development packages
automat ically route des ig ns for the FLASH370 f amily in a matt er
of minutes . Finall y, the ric h routing resources of the FLASH370
family accommodate last minute logic changes while maintain-
ing fixed pin assignments.
Logic Block
The logic block is the basic building block of the FLASH370
archit ecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used.
There ar e two types o f logic b locks in the FLASH3 70 fam ily. The
first type features an equal number (16) of I/O cells and mac-
r oce ll s an d i s show n i n Figure 2. This archit ect ure is best for
I/O-i ntensive applica ti ons. The second type o f l ogic blo ck fea -
tures a b uried macr oce ll along with ea ch I /O mac rocell. In oth -
er words, in each logic block, ther e are eight macrocells t hat
are connected t o I/ O cell s and eight macrocells that are inter-
nally fed back to the PIM only. This organization is designed
fo r regist er-i ntensi v e appli cati ons and is dis pla y ed in Figure 3.
Note that at each FLASH370 densit y (except the smallest), an
I/O intensive and a register-int ensive device is avai lable.
Product T erm Array
Each logic block features a 72 x 86 programmable product
term arr ay. This ar ra y is f e d with 36 input s fro m the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 86 product
terms in the array can be created from an y of the 72 inputs.
Figure 1. CY7C375 Block Diagram
PIM
INPUT
MACROCELLS
CLOCK
INPUTS
INPUTS
LOGIC
BLOCK LOGIC
BLOCK
44
36
16 16
36
LOGIC
BLOCK LOGIC
BLOCK
36
16 16
36
16 I/Os
LOGIC
BLOCK LOGIC
BLOCK
36
16 16
36
LOGIC
BLOCK
LOGIC
36
16 16
36
64 64
42
INPUT/CLOCK
MACROCELLS
A
B
C
E
F
G
H
Logic Block Diagram
I/O0–I/O15
I/O16–I/O31
I/O32–I/O47
I/O48–I/O63
I/O112–I/O127
I/O96–I/O111
I/O80–I/O95
I/O64–I/O79
LOGIC
BLOCK
D
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
CPLD Family
FLASH370™
3
Figure 2. Logic Bloc k for CY7C371, CY7C373, and CY7C375 ( I/O Intensive)
flash370–2
I/O
CELL
1
PRODUCT
TERM
ALLOCATOR
I/O
CELL
8
I/O
CELL
9
I/O
CELL
16
MACRO-
CELL
1
MACRO-
CELL
8
MACRO-
CELL
9
MACRO-
CELL
16
72 x 86
PRODUCT TERM
ARRAY
8036
16
16
TO
PIM
FROM
PIM
22
6
0–16
PRODUCT
TERMS
2
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
Figure 3. Logic Block for CY7C372 and CY7C374 (Register Intensive)
flash370–3
I/O
CELL
1
PRODUCT
TERM
ALLOCATOR
I/O
CELL
9
MACRO-
CELL
1
MACRO-
CELL
2
MACRO-
CELL
9
0–16
PRODUCT
TERMS
72 x 86
PRODUCT TERM
ARRAY
8036
8
16
TO
PIM
FROM
PIM
6
22
MACRO-
CELL
16
2
to cells
to cells
3,5,7
11,13,15
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
0–16
PRODUCT
TERMS
CPLD Family
FLASH370™
4
Of the 86 product terms, 80 are for general-purpose use for the
16 macrocells in the logic block. Four of the remaining six prod-
uct terms in the logic block are output enable (OE) product
terms. Each of the OE prod uct terms contr ols up to eigh t of the
16 ma crocel ls and i s se lecta ble o n an i ndivi dual macr ocell ba-
sis . In ot her words , each I/ O cell c an select bet ween one of tw o
OE product terms to control the output buffer. The first two of
these four OE product terms are avail able to the upper half of
the I/O macrocel ls in a logic block. The other two OE product
terms are available to the lower half of the I/ O macrocells in a
logi c b loc k. The fi nal tw o product terms in each l ogic b l ock ar e
dedicated asynchronous set and asynchronous reset product
terms.
Product Term Allocator
Through the product term allocator, software automatically dis-
tributes product terms among the 16 macrocells in the logic
bl ock as needed. A total of 80 product terms ar e avai labl e from
the local product term array. The product term allocator pro-
vide s two imp ortant capabilit ies with out aff ecting perf ormance:
product term steeri ng and product term sharing.
Product Term Steeri ng
Product term steering is the process of assigning product
terms to macroc ell s as needed. F or example, if one m acrocell
requires ten product terms while another needs just three , the
product term allocator will “steer” ten product terms to one
macr ocell and three to the other . On FLASH370 dev ices, prod-
uct ter ms are steered on an individual basis. Any number be-
tween 0 and 16 product terms can be steered to any macrocell.
Note t hat 0 pr oduc t terms is usef ul in case s where a pa rticular
macr ocell is unused or used as an input regist er.
Product Term Sharing
Produc t term sharing is the p rocess of us ing t he sam e prod uct
term among multiple macrocells. For example, if more than
one output has one or more product terms in i ts e quation that
are common to other outputs, those product terms are only
programmed once. The FLASH370 product term allocator al-
lows s haring acr oss groups o f f our output macro cells in a v ari-
able fashion. The software automatically takes advantage of
this capa bility —t he user does not have to intervene. Note that
greater usable density can often be achieved if the user “floats”
the pin assignment. This allows the compiler to group macro-
cell s that hav e com m on product terms adjacently.
Note that neit her produ ct term sharing nor pr oduct te rm st eer-
ing ha v e any ef f ect on the spee d of t he pr oduct. All worst -case
steeri ng and s haring conf igur ation s h av e b een incorpor ated i n
the ti ming specificat ions fo r the FLASH370 devices.
FLASH370 Macrocell
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells de-
pending on the device used. Figure 4 illust rates the architec-
ture of the I/O macrocell. The macrocell features a register that
can be configured as combinatorial, a D flip-flop, a T flip-flop,
or a level-t riggered latch .
The regi ster c an be a synchron ousl y set o r asynchr onou sly re -
set at th e logic b lock l evel with t he separ ate set and res et prod-
uct ter ms. Each of these product terms features programm a-
ble polar ity. This allows the regist ers to be set or reset based
on an AND expression or an OR e xpression.
Clocking of the register is very flexible. Depending on the de-
vice , either two or f our glo bal synchron ous clock s are av ailab le
to clock the register. Furthermore, each clock features pro-
gramm able pol arity so t hat regi ste rs c an be triggered on f alling
as wel l as rising edges (see the Dedicated/Clock Inputs sec-
tion) . Cl ock polarity i s chosen a t the logi c bloc k level.
Notes:
1. C1 is not used on the CY7C371 and CY7C372.
Figure 4. I/O Macrocell
flash370–4
0
1
2
3Q
C5 C6
“0”
“1”
0
1Q
D/T/L Q
C2 C3
P
0
1
2
3Q
S1 S0
C0
0
1Q
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
2 BANK OE TERMS
4 SYSTEM CLOCKS (CY7C373 - CY7C375)
BL OCK RESET
BL OCK PRESE T
0−16
TERMS
I/O MACROCELL
I/O CELL
R
DECODE
ASYNCHRONOUS
ASYNCHRONOUS 2 SYSTEM CLOCKS (CY7C371 - CY7C372)
C1[1]
PRODUCT
CPLD Family
FLASH370™
5
At the output of the macrocell, a polarity control mux is avail-
abl e t o selec t activ e LO W or act iv e HIGH sign als. This has th e
added advantage of allowing signi ficant logic reduction to oc-
cur in man y applicatio ns.
The FLASH370 macroc ell feat ures a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back inter nally only), the associated
I/O pin can still be used as an input.
Buried Macrocell
Some of the devi ce s i n t he FLASH370 fami ly feature add it ional
macrocells that do not feed individual I/O pins. Figure 5 dis-
plays the architecture of the I/O and buried macrocells for
these devices. The I/O macrocell is identical to the one on
devices without b uried macrocel ls.
The buried macrocell is very similar to the I/O macrocell.
Again, i t includes a register t hat can be conf igured as combi-
natori al, a D flip-flop, a T flip-fl op, or a latch. The clock for this
register has the same options as describ ed for the I/O ma cro-
cell . The primary diff erence betwee n the I/O macrocell and t he
burie d macrocell is that th e buried mac rocell d oes not ha ve t he
ability to output dat a directly to an I/O pin.
One addi tional difference on the buried macrocell is the addi-
tion of input register capability. The buried macrocell can be
configur ed to act as an input register (D-type or latch) whose
input comes from the I/O pin associated with the neighbor ing
macrocell. The output of all buried macroc ell s is sent directly
to the PIM rega rdl ess o f it s configuration.
FLASH370 I/O Ce ll
The I/O cell on the FLASH370 devices is illustrated along with
the I/O macro cell in Figures 4 and 5. The user can program
the I/O cell to change the way the three-state output buffer is
enabl ed and/ or disab led. Each o utput can be set permanen tly
on (output only) , permanently off (input only) , or dynam ically
controlled by one of two O E product terms.
Figure 5. I/O and Buried Macrocells
C2 C3
DECODE
C2 C3
DECODE
flash370–5
0
1
2
3Q
C5 C6
“0”
“1”
0
1
Q
D/T/L Q
R
P
0
1
2
3Q
0
1Q
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
2 BANK OE TERMS
4 SYSTEM CLOCKS (CY7C373–CY7C375)
BLOCK RESET
BL OCK PRESE T
0–16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1Q
D/T/L Q
R
P
0
1
2
3Q
C0
FROM PTM
1Q
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
ASYNCHRONOUS
2 SYSTEM CLOCKS (CY7C371–CY7C372)
C1 [1]
C1C0[1]
PRODUCT
0–16
TERMS
PRODUCT
CPLD Family
FLASH370™
6
Dedicated/Clock Inputs
Six pi ns on each member of t he FLASH370 fami ly are desi gnat-
ed as input-only. There are two types of dedicated inputs on
FLASH370 devices: input pins and input/clock pins. Figure 6
il lus trates t he archit ecture f or input pins. Four i nput option s are
avail able for the user: combi natorial, registered, doubl e-regis-
tered, or latched. If a r egistered or l atched option i s selected,
any one of the input clocks can be selected for control.
Figure 7 illustrates the architecture of input/clock pins. There
are either two o r f our input/clock pins available, depending on
the device selected. (The CY7C371 and CY7C372 have two
input/clock pi ns while t he other devices have four input/clock
pins.) Like the input pins, input/ clock pins can be c om binatori -
al, registered, double regi stered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input i s user-confi gurabl e in polarit y. The po-
larity of the clock signal can also be controlled by the user.
Note that this polarity is separately controlled for input regis-
ters and out put registers.
Timing Model
One of the most impor tant features of the FLASH370 family is
the simpli city of its timing. All delays are worst case and sys-
tem performance is unaffected by the features used or not
used on t he p arts . Fi gure 8 illustrates the true timing model for
the 8.5-ns devices. For combinatorial paths, any input to any
output incurs an 8.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input
set-up time t o t he output macrocel ls for any i nput is 5. 0 ns and
the clock to output tim e is also 6.0 ns. Agai n, t hese measure-
ments are for any output and clock, regardless of the logic
used.
Notes:
2. C9 is not used on the CY7C371 and CY7C372.
3. C8 and C9 are not included on the CY7C371 and CY7C372 since each input/clock pin has the other input/clock pin as its clock.
4. C15 and C16 are not used on the CY7C371 and CY7C372 since there are two clocks.
Figure 6. input Pins
flash370-6
0
1
2
3
O
C10 C11
TO PIM
DQ
DQ
DQ
LE
INPUT PIN
0
1
2O
C8
FROM CLOCK
POLARITY MUXES 3
C9[2]
Figure 7. Input/Clock Pins
flash370–7
0
1
2
3
O
C10C11
TO PIM
DQ
DQ
DQ
LE
INPUT/CLOCK PIN
0
1
2O
FROM CLOCK
CLOCK PINS
0
1Q
C12
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO CLOCK MUX
IN EACH
3
0
1
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
POLAR IT Y INPU T
LOGIC BLOCK
C8[3] C9[3]
C13, C14, C15[4],ORC16
[4]
CPLD Fa mily
FLASH370™
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or im ply an y li ce nse under patent or oth er rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support systems where a malfunc tion or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies Cypress Semiconductor against all charges.
Stated another way, the FLASH370 fe atures:
•no fanout delays
•no expander delays
•no dedicated vs. I/O pin delays
•no additional delay through PIM
•no penalty for using 0–16 pro duc t t e rms
•no added delay for steering product terms
•no added delay for sharing product terms
•no routing delays
•no output bypass delays
The simple timing model of the FLASH370 family eliminates
unexpected performance penalties.
Bus Hold Capabi li ties on all I/ Os and Dedicated Inputs
A f eature called bus -hold has been adde d to al l FLASH370 I/ Os
and dedicated input pins. Bus-hold, which is an improved ve r-
sion of the popular internal pull-up resistor, is a weak latch
connected to the pin that does not degrade the device’s per -
formance. As a latch, bus-hold recalls the last state of a pin
when it is three-stated, t hus reducing system noise in bus-in-
terface applications. Bus-hold additionally allows unused de-
vice pins t o r emain unco nnect ed on th e boar d, whi ch is pa rtic-
ularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to VCC
or GND.
Development Software Support
Warp™
W arp is a s tate-of- the-art c ompiler an d complete CPLD d esign
tool. For design entry , Warp provides an IEEE-STD-1076/1164
VHDL te xt ed itor, an IEEE-STD-136 4 Veril og te xt edi tor, and a
grap hical finite state machine edi tor. It provide s optimiz ed syn-
thesis and fitting by replacing basic ci rcuits with ones pre-op-
timized for the target device, by i mplementing logic in unused
memory and by perfect communication between fitting and
synthesis. Warp provides other tools such a s graphical timing
simulation and analysis.
Warp Professional™
Warp Professional contains severa l additiona l features. It pro-
vides an extra method of design entry with its graphical block
diagram editor. It al lows up to 5 m s timing simulation instead
of only 2 ms. It allows comparing of waveforms before and after
design changes.
Warp Enterprise™
Warp Enterpr ise provides even more features. It provides un-
limited timing simulation and source-level behavioral simula-
tion a s well as a deb ugg er . It has th e abil ity to gen er ate gr aph -
ical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platfor ms. Some features
are not available in the UNIX version. For fur ther inform ation
see the Warp for PC, Wa rp f or UNIX, Warp Pro f essi on al a nd
Warp Enterprise data sheets.
Third-Party S o ftware
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
FLASH370 f amily of de vi ce s. To e xpedit e this support , Cypre ss
suppli es ve ndor s with al l pertinent archit ectur al in fo rmatio n as
well as design fitters for our products.
Document #: 38-00215-G
FLASH370, Warp, Warp Professional, Warp Enterprise, and Ultra Logi c are tr adema rk s of Cypre ss Semicondu cto r Corp orat ion.
ABEL is a tradem ark of Data I/O Corporati on.
LOG/iC is a trademark of Isdata Corporati on.
CUPL is a trademark of Logical Devices, Inc.
Figure 8. Timing Model for CY7C371
flash370–8
COMBINATORIALSIGNAL
tPD=8.5 ns
REGISTEREDSIGNAL
D,T,L Q
tS=5.0ns tCO=6.0ns
CLOCK
