LTC2412
1
2412fa
For more information www.linear.com/LTC2412
TYPICAL APPLICATION
FEATURES DESCRIPTION
2-Channel Differential Input
24-Bit No Latency ∆Σ ADC
The LTC
®
2412 is a 2-channel differential input micropower
24-bit No Latency ∆Σ™ analog-to-digital converter with an
integrated oscillator. It provides 2ppm INL and 0.16ppm
RMS noise over the entire supply range. The two differ-
ential channels are converted alternately with channel ID
included in the conversion results. It uses delta-sigma
technology and provides single conversion settling of the
digital filter. Through a single pin, the LTC2412 can be
configured for better than 110dB input differential mode
rejection at 50Hz or 60Hz ±2%, or it can be driven by an
external oscillator for a user defined rejection frequency.
The internal oscillator requires no external frequency set-
ting components.
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and re-
mote sensing measurement configurations. The full-scale
differential input range is from –0.5VREF to 0.5VREF. The
reference common mode voltage, VREFCM, and the input
common mode voltage, VINCM, may be independently set
anywhere within the GND to VCC. The DC common mode
input rejection is better than 140dB.
The LTC2412 communicates through a flexible 3-wire digi-
tal interface which is compatible with SPI and MICROWIRE
protocols.
APPLICATIONS
n 2-Channel Differential Input with Automatic Chan-
nel Selection (Ping-Pong)
n Low Supply Current: 200µA, 4µA in Autosleep
n Differential Input and Differential Reference with
GND to VCC Common Mode Range
n 2ppm INL, No Missing Codes
n 2.5ppm Full-Scale Error and 0.1ppm Offset
n 0.16ppm Noise, 22.5 Effective Number of Bits
n No Latency: Digital Filter Settles in a Single Cycle and
Each Channel Conversion is Accurate
n Internal Oscillator—No External Components Re-
quired
n 110dB Min, 50Hz or 60Hz Notch Filter
n Narrow SSOP-16 Package
n Single Supply 2.7V to 5.5V Operation
n Direct Sensor Digitizer
n Weight Scales
n Direct Temperature Measurement
n Gas Analyzers
n Strain-Gage Transducers
n Instrumentation
n Data Acquisition
n Industrial Process Control
n 6-Digit DVMs
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Total Unadjusted Error vs Input
VCC
REF+
FO
CH0+
CH0–SCK
REF–
CH1+
SDO
GND
CS
1 14
4
13
3
5
THERMOCOUPLE
6
CH1–
7
12
8, 9, 10, 15, 16
11
2412 TA01
2
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2412
VCC
V
IN
(V)
–1.5
TUE (ppm OF V
REF
)
–0.5
0.5
1.5
–1.0
0
1.0
–1.5 –0.5 0.5 1.5
2412 TA02
2.5–2–2.5 –1 0 1 2
TA = 90°C
TA = –45°C
TA = 25°C
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
VINCM = 2.5V
FO = GND
LTC2412
2
2412fa
For more information www.linear.com/LTC2412
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) to GND ....................... –0.3V to 7V
Analog Input Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Reference Input Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND .......–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2412C ................................................ 0°C to 70°C
LTC2412I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Notes 1, 2)
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
RE
F+
RE
F–
CH0
+
CH0
–
CH1
+
CH1
–
GND
GND
GND
FO
SCK
SDO
CS
GND
GND
TJMAX = 125°C, θJA = 110°C/W
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2412CGN#PBF LTC2412CGN#TRPBF 2412 16-Lead Plastic SSOP 0°C to 70°C
LTC2412IGN#PBF LTC2412IGN#TRPBF 2412I 16-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) l24 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
l
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Note 14)
l0.5 2.5 µV
Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
10 nV/°C
Positive Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
l2.5 12 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+0.03 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
l2.5 12 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+0.03 ppm of VREF/°C
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
3
3
4
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 13)
0.8 µVRMS
LTC2412
3
2412fa
For more information www.linear.com/LTC2412
CONVERTER CHARACTERISTICS
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage lGND – 0.3 VCC + 0.3 V
IN–Absolute/Common Mode IN– Voltage lGND – 0.3 VCC + 0.3 V
VIN Input Differential Voltage Range
(IN+ – IN–)
l–VREF/2 VREF/2 V
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND VCC – 0.1 V
VREF Reference Differential Voltage Range
(REF+ – REF–)
l0.1 VCC V
CS (IN+) IN+ Sampling Capacitance 18 pF
CS (IN–) IN– Sampling Capacitance 18 pF
CS (REF+) REF+ Sampling Capacitance 18 pF
CS (REF–) REF– Sampling Capacitance 18 pF
IDC_LEAK (IN+) IN+ DC Leakage Current CS = VCC = 5.5V, IN+ = GND l–10 1 10 nA
IDC_LEAK (IN–) IN– DC Leakage Current CS = VCC = 5.5V, IN– = 5.5V l–10 1 10 nA
IDC_LEAK (REF+) REF+ DC Leakage Current CS = VCC = 5.5V, REF+ = 5.5V l–10 1 10 nA
IDC_LEAK (REF–) REF– DC Leakage Current CS = VCC = 5.5V, REF– = GND l–10 1 10 nA
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC (Note 5)
l130 140 dB
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Notes 5, 7)
l140 dB
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Notes 5, 8)
l140 dB
Input Normal Mode Rejection
60Hz ±2%
(Notes 5, 7) l110 140 dB
Input Normal Mode Rejection
50Hz ±2%
(Note 5, 8) l110 140 dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
l130 140 dB
Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB
Power Supply Rejection, 60Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB
Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB
LTC2412
4
2412fa
For more information www.linear.com/LTC2412
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l2.7 5.5 V
ICC Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CS = 0V
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V
(Note 12)
l
l
200
4
2
300
13
µA
µA
µA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
l2.5
2.0
V
V
VIL Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
l0.8
0.6
V
V
VIH High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
l2.5
2.0
V
V
VIL Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
l0.8
0.6
V
V
IIN Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC l–10 10 µA
IIN Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9) l–10 10 µA
CIN Digital Input Capacitance
CS, FO
10 pF
CIN Digital Input Capacitance
SCK
(Note 9) 10 pF
VOH High Level Output Voltage
SDO
IO = –800µA lVCC – 0.5 V
VOL Low Level Output Voltage
SDO
IO = 1.6mA l0.4 V
VOH High Level Output Voltage
SCK
IO = –800µA (Note 10) lVCC – 0.5 V
VOL Low Level Output Voltage
SCK
IO = 1.6mA (Note 10) l0.4 V
IOZ Hi-Z Output Leakage
SDO
l–10 10 µA
LTC2412
5
2412fa
For more information www.linear.com/LTC2412
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive
(CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external
oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external
oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range l2.56 500 kHz
tHEO External Oscillator High Period l0.25 390 µs
tLEO External Oscillator Low Period l0.25 390 µs
tCONV Conversion Time FO = 0V
FO = VCC
External Oscillator (Note 11)
l
l
l
130.86
157.03
133.53
160.23
136.20
163.44
ms
ms
ms
20510/fEOSC (in kHz)
f ISCK Internal SCK Frequency Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
19.2
fEOSC/8
kHz
kHz
DISCK Internal SCK Duty Cycle (Note 10) l45 55 %
fESCK External SCK Frequency Range (Note 9) l2000 kHz
tLESCK External SCK Low Period (Note 9) l250 ns
tHESCK External SCK High Period (Note 9) l250 ns
tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
1.64 1.67 1.70 ms
ms
256/fEOSC (in kHz)
tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 9) l32/fESCK (in kHz) ms
t1CS ↓ to SDO Low Z l0 200 ns
t2CS ↑ to SDO High Z l0 200 ns
t3CS ↓ to SCK ↓(Note 10) l0 200 ns
t4CS ↓ to SCK ↑(Note 9) l50 ns
tKQMAX SCK ↓ to SDO Valid l220 ns
tKQMIN SDO Hold After SCK ↓(Note 5) l15 ns
t5SCK Set-Up Before CS ↓l50 ns
t6SCK Hold After CS ↓l50 ns
LTC2412
6
2412fa
For more information www.linear.com/LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 5V)
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 2.5V)
Integral Nonlinearity vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 5V)
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 2.5V)
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 5V)
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 2.5V)
Total Unadjusted Error vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
VIN (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
TUE (ppm OF V
REF
)
2412 G01
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 90°C
TA = 25°C
TA = –45°C
VIN (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
INL ERROR (ppm OF V
REF
)
2412 G04
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
VINCM = 2.5V
FO = GND
TA = –45°C
TA = 25°C
TA = 90°C
VIN (V)
–1 –0.5 0 0.5 1
TUE (ppm OF V
REF
)
2412 G02
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 2.5V
REF– = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
TA = 90°C
TA = 25°C
TA = –45°C
VIN (V)
–1 –0.5 0 0.5 1
INL ERROR (ppm OF V
REF
)
2412 G05
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 2.5V
REF– = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
TA = 25°C
TA = –45°C
TA = 90°C
VIN (V)
–1 –0.5 0 0.5 1
TUE (ppm OF V
REF
)
2412 G03
10
8
6
4
2
0
–2
–4
–6
–8
–10
VCC = 2.7V
REF+ = 2.5V
REF– = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
TA = 90°C
TA = 25°C
TA = –45°C
VIN (V)
–1 –0.5 0 0.5 1
INL ERROR (ppm OF V
REF
)
2412 G06
10
8
6
4
2
0
–2
–4
–6
–8
–10
VREF = 2.5V
VINCM = 1.25V
FO = GND
VCC = 2.7V
REF+ = 2.5V
REF– = GND
TA = 25°C
TA = –45°C
TA = 90°C
OUTPUT CODE (ppm OF VREF)
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8
NUMBER OF READINGS (%)
2412 G07
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.105ppm
σ = 0.153ppm
OUTPUT CODE (ppm OF VREF)
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8
NUMBER OF READINGS (%)
2412 G08
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
FO = 460800Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.067ppm
σ = 0.151ppm
OUTPUT CODE (ppm OF VREF)
–1.6 –0.8 0 0.8 1.6
NUMBER OF READINGS (%)
2412 G10
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF+ = 2.5V
REF– = GND
IN+ = 1.25V
IN– = 1.25V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.033ppm
σ = 0.293ppm
LTC2412
7
2412fa
For more information www.linear.com/LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
Long-Term Noise Histogram
(Time = 60 Hrs, VCC = 5V,
VREF = 5V)
Consecutive ADC Readings
vs Time
RMS Noise
vs Input Differential Voltage
RMS Noise vs VINCM RMS Noise vs Temperature (TA) RMS Noise vs VCC
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 2.5V)
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
Noise Histogram (Output Rate =
22.5Hz, VCC = 2.7V, VREF = 2.5V)
OUTPUT CODE (ppm OF VREF)
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6
NUMBER OF READINGS (%)
2410 G11
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF+ = 2.5V
REF– = GND
IN+ = 1.25V
IN– = 1.25V
FO = 460800Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.014ppm
σ = 0.292ppm
OUTPUT CODE (ppm OF VREF)
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8
NUMBER OF READINGS (%)
2412 G16
12
10
8
6
4
2
0
ADC CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
FO = GND
TA = 25°C
GAUSSIAN DISTRIBUTION
m = 0.101837ppm
σ = 0.154515ppm
VINCM (V)
–0.5 0 10.5 1.5 2 2.5 3 3.5 4 4.5 5
5.5
RMS NOISE (nV)
2412 G19
850
825
800
775
750
725
700
675
650
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
IN+ = VINCM
IN– = VINCM
VIN = 0V
FO = GND
TA = 25°C
TIME (HOURS)
05 10 15 20 25 30 35 40 45 50 55 60
ADC READING (ppm OF V
REF
)
2412 G17
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
TA = 25°C
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
TEMPERATURE (°C)
RMS NOISE (nV)
2412 G20
850
825
800
775
750
725
700
675
650
–50 –25 0 25 50 75 100
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
VIN = 0V
FO = GND
INPUT DIFFERENTIAL VOLTAGE (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
RMS NOISE (ppm OF V
REF
)
2412 G18
0.5
0.4
0.3
0.2
0.1
0
VCC = 5V
VREF = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = 25°C
VCC (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
RMS NOISE (nV)
2412 G21
850
825
800
775
750
725
700
675
650
REF+ = 2.5V
REF– = GND
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
OUTPUT CODE (ppm OF VREF)
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6
NUMBER OF READINGS (%)
2412 G13
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF+ = 2.5V
REF– = GND
IN+ = 1.25V
IN– = 1.25V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.079ppm
σ = 0.298ppm
OUTPUT CODE (ppm OF VREF)
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6
NUMBER OF READINGS (%)
2412 G14
12
10
8
6
4
2
0
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF+ = 2.5V
REF– = GND
IN+ = 1.25V
IN– = 1.25V
FO = 460800Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.177ppm
σ = 0.297ppm
LTC2412
8
2412fa
For more information www.linear.com/LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
+Full-Scale Error vs VCC +Full-Scale Error vs VREF
–Full-Scale Error
vs Temperature (TA)
VREF (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RMS NOISE (nV)
2412 G22
850
825
800
775
750
725
700
675
650
VCC = 5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
VCC (V)
OFFSET ERROR (ppm OF V
REF
)
2412 G25
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
REF+ = 2.5V
REF– = GND
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC (V)
+FULL-SCALE ERROR (ppm OF V
REF
)
2412 G28
3
2
1
0
–1
–2
–3
REF+ = 2.5V
REF– = GND
VREF = 2.5V
IN+ = 1.25V
IN– = GND
FO = GND
TA = 25°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VINCM (V)
–0.5 0 10.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5
OFFSET ERROR (ppm OF V
REF
)
2412 G23
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
IN+ = VINCM
IN– = VINCM
VIN = 0V
FO = GND
TA = 25°C
VREF (V)
OFFSET ERROR (ppm OF V
REF
)
2412 G26
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VCC = 5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VREF (V)
+FULL-SCALE ERROR (ppm OF V
REF
)
2412 G29
3
2
1
0
–1
–2
–3
VCC = 5V
REF+ = VREF
REF– = GND
IN+ = 0.5 • REF+
IN– = GND
FO = GND
TA = 25°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
OFFSET ERROR (ppm OF V
REF
)
2412 G24
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = 2.5V
VIN = 0V
FO = GND
TEMPERATURE (°C)
+FULL-SCALE ERROR (ppm OF V
REF
)
2412 G27
3
2
1
0
–1
–2
–3
–45 –30 –15 0 15 30 45 60 75 90
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = GND
FO = GND
TEMPERATURE (°C)
–FULL-SCALE ERROR (ppm OF V
REF
)
2412 G30
3
2
1
0
–1
–2
–3
–45 –30 –15 0 15 30 45 60 75 90
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = GND
IN– = 2.5V
FO = GND
Offset Error vs VREF
Offset Error vs VCC
+Full-Scale Error
vs Temperature (TA)
RMS Noise vs VREF Offset Error vs VINCM Offset Error vs Temperature (TA)
LTC2412
9
2412fa
For more information www.linear.com/LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC PSRR vs Frequency at VCC
Conversion Current
vs Temperature
Conversion Current
vs Output Data Rate
Sleep Mode Current
vs Temperature
–Full-Scale Error vs VCC –Full-Scale Error vs VREF PSRR vs Frequency at VCC
VCC (V)
–FULL-SCALE ERROR (ppm OF V
REF
)
2412 G31
3
2
1
0
–1
–2
–3
REF+ = 2.5V
REF– = GND
VREF = 2.5V
IN+ = GND
IN– = 1.25V
FO = GND
TA = 25°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2412 G34
10 100 10k
1M
REJECTION (dB)
VCC = 4.1VDC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
VREF (V)
–FULL-SCALE ERROR (ppm OF V
REF
)
2412 G32
3
2
1
0
–1
–2
–3
VCC = 5V
REF+ = VREF
REF– = GND
IN+ = GND
IN– = 0.5 • REF+
FO = GND
TA = 25°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY AT VCC (Hz)
0
REJECTION (dB)
–60
–40
–20
120 210
2412 G35
–80
–100
30 60 150 180
–120
–140
0
90
240
VCC = 4.1VDC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
CONVERSION CURRENT (µA)
200
210
220
75
2412 G37
190
180
160 –15 15 45
–30
90
030 60
170
240
230 VCC = 5.5V
VCC = 2.7V
VCC = 3V
VCC = 5V
FO = GND
CS = GND
SCK = NC
SDO = NC
OUTPUT DATA RATE (READINGS/SEC)
0
100
SUPPLY CURRENT (µA)
200
400
500
600
1000
2412 G38
300
10 205 15
25
700
800
900
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
CS = GND
FO = EXT OSC
TA = 25°C
VCC = 5V
VCC = 3V
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
1
3
4
5
–15 15 30 90
2412 G39
2
–30 0 45 60 75
6
VCC = 5.5V
VCC = 2.7V
VCC = 5V
VCC = 3V
FO = GND
CS = VCC
SCK = NC
SDO = NC
FREQUENCY AT VCC (Hz)
REJECTION (dB)
2412 G33
0
–20
–40
–60
–80
–100
–120
–140
0.01 0.1 1 10
100
VCC = 4.1VDC 1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
15250
–60
–40
0
15400
2412 G36
–80
–100
15300 15350
15450
–120
–140
–20
REJECTION (dB)
VCC = 4.1VDC ±0.7VP-P
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
LTC2412
10
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF–, by at least 0.1V.
CH0+ (Pin 4): Positive Input for Differential Channel 0.
CH0– (Pin 5): Negative Input for Differential Channel 0.
CH1+ (Pin 6): Positive Input for Differential Channel 1.
CH1– (Pin 7): Negative Input for Differential Channel 1.
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and VCC. Within these limits
the converter bipolar input range (VIN = IN+ – IN–) extends
from –0.5 • (VREF) to 0.5 • (VREF). Outside this input range
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and VCC decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All five
pins must be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. A weak internal pull-up is
automatically activated in Internal Serial Clock Operation
mode. The Serial Clock Operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO is
driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
LTC2412
11
2412fa
For more information www.linear.com/LTC2412
FUNCTIONAL BLOCK DIAGRAM
TEST CIRCUIT
AUTOCALIBRATION
AND CONTROL
DECIMATING FIR
CH0/CH1
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
PING-PONG
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
+ –
MUX
GND
RE
F+
CH0
+IN+
IN–
CH0
–
CH1
+
CH1
–
REF
–
VCC
SCK
SDO
CS
FO
(INT/EXT)
2412 FD
Figure 1. Functional Block Diagram
1.69k
SDO
2412 TA03
Hi-Z TO VOH
VOL TO VOH
V
OH
TO Hi-Z
CLOAD
= 20pF
1.69k
SDO
2412 TA04
Hi-Z TO VOL
VOH TO VOL
V
OL
TO Hi-Z
CLOAD
= 20pF
V
CC
LTC2412
12
2412fa
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APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2412 is a low power, ∆Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2412 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
formed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK).
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2412 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require programming
configuration registers; moreover, they do not disturb the
cyclic operation described above. These modes of opera-
tion are described in detail in the Serial Interface Timing
Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus
their harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock. The
LTC2412 incorporates a highly accurate on-chip oscillator.
This eliminates the need for external frequency setting
components such as crystals or oscillators. Clocked by
the on-chip oscillator, the LTC2412 achieves a minimum of
110dB rejection at the line frequency (50Hz or 60Hz ±2%).
Ease of Use
The LTC2412 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
Figure 2. LTC2412 State Transition Diagram
CONVERT
POWER UP
IN+ = CH0+, IN– = CH0–
SLEEP
DATA OUTPUT
SWITCH CHANNEL
2412 F02
TRUE
FALSE CS = LOW
AND
SCK
LTC2412
13
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For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
The LTC2412 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2412 automatically enters an internal reset state
when the power supply voltage VCC drops below ap-
proximately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selection.
(See the 2-wire I/O sections in the Serial Interface Timing
Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers and selects channel 0. Following the
POR signal, the LTC2412 starts a normal conversion cycle
and follows the succession of states described above. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage specification
for the REF+ and REF– pins covers the entire range from
GND to VCC. For correct converter operation, the REF+ pin
must always be more positive than the REF– pin.
The LTC2412 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in nanovolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance. A reduced reference
voltage will also improve the converter performance when
operated with an external conversion clock (external FO
signal) at substantially higher output data rates (see the
Output Data Rate section).
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0+/CH0– or CH1+/CH1–
input pins extending from GND – 0.3V to VCC + 0.3V.
Outside these limits, the ESD protection devices begin
to turn on and the errors due to input leakage current
increase rapidly. Within these limits, the LTC2412 con-
verts the bipolar differential input signal, VIN = IN+ – IN–,
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF–, with the selected channel referred as IN+
and IN–. Outside this range, the converter indicates the
overrange or the underrange condition using distinct
output codes.
Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between these
series resistors and the corresponding pins as low as pos-
sible; therefore, the resistors should be located as close as
practical to the pins. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
Output Data Format
The LTC2412 serial output data stream is 32 bits long.
The first 3 bits represent status information indicating the
conversion state, selected channel and sign. The next 24
bits are the conversion result, MSB first. The remaining
5 bits are sub LSBs beyond the 24-bit level that may be
included in averaging or discarded without loss of reso-
lution. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the dif-
ferential input voltage is above +FS).
LTC2412
14
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Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is the selected channel indica-
tor. The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2412 Status Bits
Input Range
Bit 31
EOC
Bit 30
CH0/CH1
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 • VREF 0 0 or 1 1 1
0V ≤ VIN < 0.5 • VREF 0 0 or 1 1 0
–0.5 • VREF ≤ VIN < 0V 0 0 or 1 0 1
VIN < –0.5 • VREF 0 0 or 1 0 0
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0
may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and any externally gener-
ated SCK clock pulses are ignored by the internal data
out shift register.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the analog input pins is main-
tained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Figure 3. Output Data Timing
APPLICATIONS INFORMATION
MSBSIGCH0/CH1
1 2 3 4 5 26 27 32
BIT 0BIT 27 BIT 5
LSB24
BIT 28BIT 29BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2412 F03
Hi-Z
LTC2412
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APPLICATIONS INFORMATION
Frequency Rejection Selection (FO)
The LTC2412 internal oscillator provides better than
110dB normal mode rejection at the line frequency and
all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz
rejection, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2412 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator.
The frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The external
clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2412 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin,
the converter automatically activates its internal oscilla-
tor and enters the Internal Conversion Clock mode. The
LTC2412 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
Figure 4. LTC2412 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
Table 2. LTC2412 Output Data Format
Differential Input Voltage
VIN*
Bit 31
EOC
Bit 30
CH0/CH1
Bit 29
SIG
Bit 28
MSB
Bit 27 Bit 26 Bit 25 … Bit 0
VIN* ≥ 0.5 • VREF** 0 0/1 1 1 0 0 0 … 0
0.5 • VREF** – 1LSB 0 0/1 1 0 1 1 1 … 1
0.25 • VREF** 0 0/1 1 0 1 0 0 … 0
0.25 • VREF** – 1LSB 0 0/1 1 0 0 1 1 … 1
0 0 0/1 1 0 0 0 0 … 0
–1LSB 0 0/1 0 1 1 1 1 … 1
–0.25 • VREF** 0 0/1 0 1 1 0 0 … 0
–0.25 • VREF** – 1LSB 0 0/1 0 1 0 1 1 … 1
–0.5 • VREF** 0 0/1 0 1 0 0 0 … 0
VIN* < –0.5 • VREF** 0 0/1 0 0 1 1 1 … 1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC
/2560(%)
–12 –8 –4 0 4 8 12
NORMAL MODE REJECTION (dB)
2412 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
LTC2412
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APPLICATIONS INFORMATION
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2412 transmits the conversion results and receives
the start of conversion command through a synchronous
3-wire interface. During the conversion and sleep states,
this interface can be used to assess the converter status
and during the data output state it is used to read the
conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2412 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up
and then reselected every time a HIGH-to-LOW transition
is detected at the CS pin. If SCK is HIGH or floating at
power-up or during this transition, the converter enters the
internal SCK mode. If SCK is LOW at power-up or during
this transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the convert
or sleep state, SDO will output EOC. If CS is LOW during
the conversion phase, the EOC bit appears HIGH on the
SDO pin. Once the conversion is complete, EOC goes LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2412 will abort any serial data
transfer in progress and start a new conversion cycle any-
Table 3. LTC2412 State Duration
State Operating Mode Duration
CONVERT Internal Oscillator FO = LOW
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
FO = HIGH
(50Hz Rejection)
160ms, Output Data Rate ≤ 6.2 Readings/s
External Oscillator FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
SLEEP As Long As CS = HIGH
DATA OUTPUT Internal Serial Clock FO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
LTC2412
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time a LOW-to-HIGH transition is detected at the CS pin
after the converter has entered the data output state (i.e.,
after the first rising edge of SCK occurs with CS=LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2412’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and auto-start. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW or FO = HIGH)
or an external oscillator connected to the FO pin. Refer to
Table4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of
CS. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CS falling edge.
Figure 5. External Serial Clock, Single Cycle Operation
Table 4. LTC2412 Interface Timing Modes
Configuration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
APPLICATIONS INFORMATION
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
TEST EOC
SUB LSBMSBSIGCH0/CH1
BIT 0
LSB
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP
SLEEP
TEST EOC
(OPTIONAL)
DATA OUTPUT CONVERSION
2412 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
LTC2412
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APPLICATIONS INFORMATION
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC=1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its conver-
sion result is held in an internal static shift register. Data
is shifted out the SDO pin on each falling edge of SCK.
This enables external circuitry to latch the output on the
rising edge of SCK. EOC can be latched on the first rising
edge of SCK and the last bit of the conversion result can
be latched on the 32nd rising edge of SCK. On the 32nd
falling edge of SCK, the device begins a new conversion.
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 32nd falling edge of SCK, see Figure 6. On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
Figure 6. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP SLEEP
TEST EOC (OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2412 F06
MSBSIGCH0/CH1
BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30
EOC
BIT 31BIT 0
EOC
Hi-Z
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP
LTC2412
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APPLICATIONS INFORMATION
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is ready.
EOC = 1 while the conversion is in progress and EOC=0
once the conversion ends. On the falling edge of EOC,
the conversion result is loaded into an internal static shift
register. Data is shifted out the SDO pin on each falling
edge of SCK enabling external circuitry to latch data on the
rising edge of SCK. EOC can be latched on the first rising
edge of SCK. On the 32nd falling edge of SCK, SDO goes
HIGH (EOC=1) indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23µs if the device is using its internal
oscillator (FO = logic LOW or HIGH). If FO is driven by an
external oscillator of frequency fEOSC, then tEOCtest is 3.6/
fEOSC. If CS is pulled HIGH before time tEOCtest, the device
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSBSIGCH0/CH1
BIT 0
LSB24
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
DATA OUTPUT CONVERSION
2412 F07
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
2-WIRE
INTERFACE
REF–
LTC2412
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APPLICATIONS INFORMATION
returns to the sleep state and the conversion result is held
in the internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising edge
of SCK will occur and the conversion result is serially shifted
out of the SDO pin. The data output cycle concludes after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to the
SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2412’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2412’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the
internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin,
the internal pull-up may not be adequate to return SCK
Figure 8. Internal Serial Clock, Single Cycle Operation
SDO
SCK
(INTERNAL)
CS
MSBSIGCH0/CH1
BIT 0
LSB24
BIT 5 TEST EOC
BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSIONCONVERSION
2412 F08
<tEOCtest
V
CC
10k
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
(OPTIONAL)
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP
LTC2412
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APPLICATIONS INFORMATION
to a HIGH level before CS goes low again. This is not a
concern under normal conditions where CS remains LOW
after detecting EOC = 0. This situation is easily overcome
by adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is not externally driven LOW (if SCK is loaded such that
the internal pull-up cannot pull the pin HIGH, the external
SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the first
rising edge of SCK and ends after the 32nd rising edge.
Data is shifted out the SDO pin on each falling edge of
SCK. The internally generated serial clock is output to the
SCK pin. This signal may be used to shift the conversion
result into external circuitry. EOC can be latched on the
first rising edge of SCK and the last bit of the conversion
result can be latched on the 32nd rising edge of SCK. After
the 32nd rising edge, SDO goes HIGH (EOC = 1) indicat-
ing a new conversion is in progress. SCK remains HIGH
during the conversion.
Figure 9. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSBSIGCH0/CH1
BIT 8
TEST EOC BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
EOC
BIT 0
DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA
OUTPUT
CONVERSIONCONVERSIONSLEEP
2412 F09
<tEOCtest
VCC
10k
TEST EOC
(OPTIONAL)
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP SLEEP
LTC2412
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APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY
The LTC2412 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling, PCB
layout, anti-aliasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the extreme
accuracy capability of this part, some simple precautions
are desirable.
Digital Signal Levels
The LTC2412’s digital interface is easy to use. Its digital
inputs (FO, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to
take advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC–0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range,
the LTC2412 power supply current may increase even if
the signal in question is at a valid logic level. For micro-
power operation, it is recommended to drive all digital
input signals to full CMOS levels [VIL < 0.4V and VOH >
(VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2412
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2412.
For reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces and
170ps/inch for surface traces. Thus, a driver generating a
control signal with a minimum transition time of 1ns must
be connected to the converter pin through a trace shorter
than 2.5 inches. This problem becomes particularly difficult
when shared control lines are used and multiple reflec-
tions may occur. The solution is to carefully terminate all
transmission lines close to their characteristic impedance.
Figure 10. Internal Serial Clock, Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB24
MSBSIGCH0/CH1
BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
DATA OUTPUT CONVERSIONCONVERSION
2412 F10
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
1 14
2
313
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
LTC2412
2-WIRE
INTERFACE
REF–
LTC2412
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APPLICATIONS INFORMATION
Parallel termination near the LTC2412 pin will eliminate
this problem but will increase the driver power dissipa-
tion. A series resistor between 27Ω and 56Ω placed near
the driver or near the LTC2412 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the FO signal when the LTC2412 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals may result into a DC offset error. Such
perturbations may occur due to asymmetric capacitive
coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation be-
tween the FO signal trace and the input/reference signals.
When the FO signal is parallel terminated near the converter,
substantial AC current is flowing in the loop formed by
the FO connection trace, the termination and the ground
return path. Thus, perturbation signals may be inductively
coupled into the converter input and/or reference. In this
situation, the user must reduce to a minimum the loop
area for the FO signal as well as the loop area for the dif-
ferential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2412 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differen-
tial input voltage and the differential reference voltage,
these capacitors are switching between these four pins
transferring small amounts of charge in the process. A
simplified equivalent circuit is shown in Figure 11, where
IN+ and IN– refer to the selected differential channel and
the unselected channel is omitted for simplicity.
Figure 11. LTC2412 Equivalent Analog Input Circuit
VREF+
VIN+
V
CC
RSW (TYP)
20k
ILEAK
ILEAK
VCC
ILEAK
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2412 F11
ILEAK
VCC
ILEAK
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
f
SW
= 0.5 • f
EOSC
EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
I IN+
( )
AVG =
V
IN
+V
INCM
−V
REFCM
0.5•REQ
I IN−
( )
AVG =−VIN +VINCM −VREFCM
0.5•REQ
I REF+
( )
AVG =1.5•VREF −VINCM +VREFCM
0.5•REQ
−VIN
2
VREF •REQ
I REF−
( )
AVG =−1.5•VREF −VINCM +VREFCM
0.5•REQ
+VIN
2
VREF •REQ
where:
VREF =REF+−REF−
VREFCM =REF++REF−
2
VIN =IN+−IN−
VINCM =IN+−IN−
2
REQ =3.61MΩINTERNAL OSCILLATOR 60Hz Notch FO=LOW
( )
REQ =4.32MΩINTERNAL OSCILLATOR 50Hz Notch FO=HIGH
( )
REQ =0.555•1012
( )
/ fEOSC EXTERNAL OSCILLATOR
LTC2412
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APPLICATIONS INFORMATION
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can
be considered to form, together with R
SW and CEQ (see
Figure 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
When using the internal oscillator (FO = LOW or HIGH),
the LTC2412’s front-end switched-capacitor network is
clocked at 76800Hz corresponding to a 13µs sampling
period. Thus, for settling errors of less than 1ppm, the
driving source impedance should be chosen such that
τ ≤ 13µs/14 = 920ns. When an external oscillator of
frequency fEOSC is used, the sampling period is 2/fEOSC
and, for a settling error of less than 1ppm, τ ≤ 0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2412 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 13 and 14. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
by Figures 13 and 14. For simplicity, two distinct situations
can be considered.
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the source
impedance result in only small errors. Such values for CIN
Figure 12. An RC Network at IN+ and IN–
Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 13. +FS Error vs RSOURCE at IN+ or IN (Small CIN)
will deteriorate the converter offset and gain performance
without significant benefits of signal filtering and the user
is advised to avoid them. Nevertheless, when small val-
ues of CIN are unavoidably present as parasitics of input
CIN
2412 F12
V
INCM + 0.5VIN
R
SOURCE
IN+
LTC2412
CPAR
≅20pF
CIN
V
INCM – 0.5VIN
RSOURCE
IN–
CPAR
≅20pF
RSOURCE (Ω)
1 10 100 1k 10k
100k
+FS ERROR (ppm OF V
REF
)
2412 F13
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 5V
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.001µF
CIN = 100pF
CIN = 0pF
RSOURCE (Ω)
1 10 100 1k 10k
100k
–FS ERROR (ppm OF V
REF
)
2412 F14
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.001µF
CIN = 100pF
CIN = 0pF
LTC2412
25
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
multiplexers, wires, connectors or sensors, the LTC2412
can maintain its exceptional accuracy while operating
with relative large values of source resistance as shown in
Figures 13 and 14. These measured results may be slightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small CIN values, the
settling on IN+ and IN– occurs almost independently and
there is little benefit in trying to match the source imped-
ance for the two pins.
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for anti-aliasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN+ or
IN. When FO = HIGH (internal oscillator and 50Hz notch),
the typical differential input resistance is 2.16MΩ which
will generate a gain error of approximately 0.23ppm at
full-scale for each ohm of source resistance driving IN+
or IN. When FO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.28 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN– will
result in 1.78 • 10–6 • fEOSCppm gain error at full-scale.
The effect of the source resistance on the two input pins
is additive with respect to this gain error. The typical +FS
and –FS errors as a function of the sum of the source
resistance seen by IN+ and IN– for large values of CIN are
shown in Figures 15 and 16.
In addition to this gain error, an offset error term may
also appear. The offset error is proportional with the
mismatch between the source impedance driving the two
input pins IN+ and IN– and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large
CIN capacitor values, it is advisable to carefully match the
source impedance seen by the IN+ and IN– pins. When
FO = LOW (internal oscillator and 60Hz notch), every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.28ppm. When FO = HIGH (internal oscillator
and 50Hz notch), every 1Ω mismatch in source impedance
transforms a full-scale common mode input signal into
a differential mode input signal of 0.23ppm. When FO is
driven by an external oscillator with a frequency fEOSC, every
1Ω mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10–6 • fEOSCppm. Figure 17 shows the
typical offset error due to input common mode voltage for
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 16. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
+FS ERROR (ppm OF V
REF
)
2412 F15
300
240
180
120
60
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.1µF
CIN = 1µF, 10µF
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
–FS ERROR (ppm OF V
REF
)
2412 F16
0
–60
–120
–180
–240
–300
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.1µF
CIN = 1µF, 10µF
LTC2412
26
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
various values of source resistance imbalance between the
IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are used
for the external source impedance seen by IN+ and IN–,
the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
values over the entire temperature and voltage range). Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2412 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sampling
charge and the external source resistance will see a quasi
constant reference differential impedance. When FO =
LOW (internal oscillator and 60Hz notch), the typical dif-
ferential reference resistance is 1.3MΩ which will gener-
ate a gain error of approximately 0.38ppm at full-scale
for each ohm of source resistance driving REF+ or REF–.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential reference resistance is 1.56MΩ which
will generate a gain error of approximately 0.32ppm at
full-scale for each ohm of source resistance driving REF+
or REF–. When FO is driven by an external oscillator with
a frequency fEOSC (external conversion clock operation),
the typical differential reference resistance is 0.20 • 1012/
fEOSCΩ and each ohm of source resistance driving REF+
or REF– will result in 2.47 • 10–6 • fEOSCppm gain error at
full-scale. The effect of the source resistance on the two
reference pins is additive with respect to this gain error.
The typical +FS and –FS errors for various combinations
of source resistance seen by the REF+ and REF– pins and
external capacitance CREF connected to these pins are
shown in Figures 18, 19, 20 and21.
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
VINCM (V)
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OFFSET ERROR (ppm OF V
REF
)
2412 F17
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
FO = GND
TA = 25°C
RSOURCEIN– = 500Ω
CIN = 10µF
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = IN– = VINCM
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
A
B
C
D
E
F
G
LTC2412
27
2412fa
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APPLICATIONS INFORMATION
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– trans-
lates into about 1.34ppm additional INL error. When FO
= HIGH (internal oscillator and 50Hz notch), every 100Ω
of source resistance driving REF+ or REF– translates into
about 1.1ppm additional INL error. When FO is driven by
an external oscillator with a frequency fEOSC, every 100Ω
of source resistance driving REF+ or REF– translates
into about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on
the two reference pins is additive with respect to this INL
error. In general, matching of source impedance for the
REF+ and REF– pins does not help the gain or the INL er-
ror. The user is thus advised to minimize the combined
source impedance driving the REF+ and REF– pins rather
than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
RSOURCE (Ω)
1 10 100 1k 10k
100k
+FS ERROR (ppm OF V
REF
)
2412 F18
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 5V
IN– = 2.5V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
1 10 100 1k 10k
100k
–FS ERROR (ppm OF V
REF
)
2412 F19
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
+FS ERROR (ppm OF V
REF
)
2412 F20
0
–90
–180
–270
–360
–450
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.1µF
CREF = 1µF, 10µF
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
–FS ERROR (ppm OF V
REF
)
2412 F21
450
360
270
180
90
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.1µF
CREF = 1µF, 10µF
LTC2412
28
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2412 can produce
up to 7.5 readings per second with a notch frequency of
60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH). The actual output
data rate will depend upon the length of the sleep and
data output phases which are controlled by the user and
which can be made insignificantly short. When operated
with an external conversion clock (FO connected to an
external oscillator), the LTC2412 output data rate can be
increased as desired. The duration of the conversion phase
is 20510/fEOSC. If fEOSC = 153600Hz, the converter behaves
as if the internal oscillator is used and the notch is set at
60Hz. There is no significant difference in the LTC2412
performance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent per-
formance degradation can be substantially reduced by
relying upon the LTC2412’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used,
the previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2412 typical
performance can be inferred from Figures 13, 14, 18 and
19 in which the horizontal axis is scaled by 153600/fEOSC.
Third, an increase in the frequency of the external oscillator
above 460800Hz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
auto-calibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
25 readings per second are shown in Figures23, 24, 25,
26, 27, 28, 29 and 30. In order to obtain the highest pos-
sible level of accuracy from this converter at output data
rates above 7.5 readings per second, the user is advised
to maximize the power supply voltage used and to limit
the maximum ambient operating temperature. In certain
circumstances, a reduction of the differential reference
voltage may be beneficial.
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
VINDIF/VREFDIF
–0.5–0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
INL (ppm OF V
REF
)
15
12
9
6
3
0
–3
–6
–9
–12
–15
VCC = 5V
REF+ = 5V
REF– = GND
V
INCM
= 0.5 • (IN+ + IN–) = 2.5V
FO = GND
CREF = 10µF
TA = 25°C
RSOURCE = 1000Ω
RSOURCE = 500Ω
RSOURCE = 100Ω
2412 F22
LTC2412
29
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For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Figure 23. Offset Error vs Output Data Rate and Temperature Figure 24. +FS Error vs Output Data Rate and Temperature
Figure 25. –FS Error vs Output Data Rate and Temperature Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 28. Offset Error vs Output
Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0 10 205 15
25
OFFSET ERROR (ppm OF V
REF
)
2412 F28
250
225
200
175
150
125
100
75
50
25
0
VCC = 5V
REF+ = GND
VINCM = 2.5V
VIN = 0V
TA = 25°C
FO = EXTERNAL OSCILLATOR
VREF = 2.5V
VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
2412 F26
24
23
22
21
20
19
18
17
16
15
14
13
12
TA = 85°C
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
TA = 25°C
0 10 205 15
25
0 10 205 15
25
OUTPUT DATA RATE (READINGS/SEC)
+FS ERROR (ppm OF V
REF
)
2412 F24
7000
6000
5000
4000
3000
2000
1000
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = EXTERNAL OSCILLATOR
TA = 25°C
TA = 85°C
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
2412 F27
22
20
18
16
14
12
10
8
TA = 85°C
TA = 25°C
0 10 205 15
25
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/INLMAX)
0 10 205 15
25
OUTPUT DATA RATE (READINGS/SEC)
–FS ERROR (ppm OF V
REF
)
2412 F25
0
–1000
–2000
–3000
–4000
–5000
–6000
–7000
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = EXTERNAL OSCILLATOR
TA = 25°C
TA = 85°C
0 10 205 15
25
OUTPUT DATA RATE (READINGS/SEC)
OFFSET ERROR (ppm OF V
REF
)
2412 F23
500
450
400
350
300
250
200
150
100
50
0
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
TA = 85°C
LTC2412
30
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Input Bandwidth
The combined effect of the internal Sinc4 digital filter and of
the analog and digital auto-calibration circuits determines
the LTC2412 input bandwidth. When the internal oscillator
is used with the notch set at 60Hz (FO = LOW), the 3dB
input bandwidth is 3.63Hz. When the internal oscillator
is used with the notch set at 50Hz (FO = HIGH), the 3dB
input bandwidth is 3.02Hz. If an external conversion clock
generator of frequency fEOSC is connected to the FO pin,
the 3dB input bandwidth is 0.236 • 10–6 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2412 input bandwidth is shown in
Figure31 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2412 input bandwidth can be derived from Figure31,
FO = LOW curve in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (800nVRMS typical for VREF = 5V) can
be modeled by a white noise source connected to a noise
free converter. The noise spectral density is 62.75nV/√Hz
for an infinite bandwidth source and 86.1nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2412, the
ADC input referred system noise calculation can be
simplified by Figure 32. The noise of an amplifier driving
the LTC2412 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency fi. The amplifier noise spectral density
is ni. From Figure32, using fi as the x-axis selector, we
can find on the y-axis the noise equivalent bandwidth freqi
Figure 29. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 30. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
0 10 205 15
25
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
2412 F29
24
23
22
21
20
19
18
17
16
15
14
13
12
VREF = 5V
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
VREF = 2.5V
0 10 205 15
25
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
2412 F30
22
20
18
16
14
12
10
8
RESOLUTION =
LOG2(VREF/INLMAX)
TA = 25°C
VCC = 5V
REF– = GND
VINCM = 0.5 • REF+
–0.5V • VREF < VIN < 0.5 • VREF
FO = EXTERNAL OSCILLATOR
VREF = 2.5V
VREF = 5V
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT SIGNAL ATTENUATION (dB)
2412 F31
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
FO = HIGH FO = LOW
LTC2412
31
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APPLICATIONS INFORMATION
of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
be calculated as N= ni • √freqi. The total system noise
(referred to the LTC2412 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2412 internal noise
(800nV), the noise of the IN+ driving amplifier and the
noise of the IN– driving amplifier.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if
the x-axis is scaled by fEOSC/153600. For large values of
the ratio fEOSC/153600, the Figure 32 plot accuracy begins
to decrease, but in the same time the LTC2412 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Anti-Aliasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2412 significantly
simplifies anti-aliasing filter requirements.
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2412’s auto-calibration circuits further simplify the
anti-aliasing requirements by additional normal mode
signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for
the external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure35 (rejection near DC) and
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
0.1 1 10 100 1k 10k 100k
1M
2412 F32
0.1
100
FO = HIGH
FO = LOW
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS
11fS
12f
S
INPUT NORMAL MODE REJECTION (dB)
2412 F33
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FO = HIGH
FO = LOW OR
FO
= EXTERNAL
OSCILLATOR,
fEOSC = 10 • fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS
INPUT NORMAL MODE REJECTION (dB)
2412 F34
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2fS3fS4fS5fS6fS7fS8fS9fS10fS
LTC2412
32
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Figure36 (rejection at fS = 256fN) where fN represents
the notch frequency. These curves have been derived for
the external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 37 and 38. Typical measured values of
the normal mode rejection of the LTC2412 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 37 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2412 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure
38 superimposed over the theoretical calculated curve.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) anti-alias filtering is required in front
of the LTC2412. If passive RC components are placed in
front of the LTC2412, the input dynamic current should
be considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects
of dynamic input current.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from poten-
tial instabilities at large input signal levels. The proprietary
architecture used for the LTC2412 third order modulator
resolves this problem and guarantees a predictable stable
behavior at input signal levels of up to 150% of full-scale.
Figure 35. Input Normal Mode Rejection Figure 36. Input Normal Mode Rejection
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2412 F35
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 fN
0 2fN3fN4fN5fN6fN7fN8fN
INPUT SIGNAL FREQUENCY (Hz)
250fN252fN254fN256fN258fN260fN262f
N
INPUT NORMAL MODE REJECTION (dB)
2412 F36
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2412 F37
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
MEASURED DATA
CALCULATED DATA
LTC2412
33
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For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Figure 38. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (50Hz Notch)
In many industrial applications, it is not uncommon to have
to measure microvolt level signals superimposed over
volt level perturbations and LTC2412 is eminently suited
for such tasks. When the perturbation is differential, the
specification of interest is the normal mode rejection for
large input signal levels. With a reference voltage VREF=5V,
the LTC2412 has a full-scale differential input range of
5V peak-to-peak. Figures 39 and 40 show measurement
results for the LTC2412 normal mode rejection ratio with a
7.5V peak-to-peak (150% of full-scale) input signal super-
imposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full-scale)
input signal. In Figure 39, the LTC2412 uses the internal
oscillator with the notch set at 60Hz (FO = LOW) and in
Figure 40 it uses the internal oscillator with the notch set
at 50Hz (FO = HIGH). It is clear that the LTC2412 rejection
performance is maintained with no compromises in this
extreme situation. When operating with large input signal
levels, the user must observe that such signals do not
violate the device absolute maximum ratings.
Measuring Barometric Pressure and Temperature with
a Single Sensor
Figure 41 shows the LTC2412 measuring both tempera-
ture and pressure from an Intersema model MS5401-BM
absolute pressure sensor. The bridge has a nominal im-
pedance of 3.4kΩ, a temperature coefficient of resistance
of 2900ppm/°C and a temperature coefficient of span of
–1900ppm/°C. R1 provides first order temperature com-
pensation of the output span by causing the bridge voltage
to increase by 1900ppm/°C, offsetting the –1900ppm/°C
TC of span. R1 should have a much smaller TC than that
of the bridge resistance; 50ppm/°C or less is satisfactory.
In addition to compensating the bridge output span, this
circuit also provides a convenient way to measure ambi-
ent temperature. Channel 1 of the LTC2412 measures the
bridge excitation voltage, which has a slope of approxi-
mately 3.2mV/°C. Channel 0 measures the bridge output,
which has a slope of 50mV/bar. The temperature reading
can also be used for second order compensation of the
pressure reading.
INPUT FREQUENCY (Hz)
012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
NORMAL MODE REJECTION (dB)
2412 F38
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
LTC2412
34
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (60Hz Notch)
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2412 F39
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL-SCALE)
LTC2412
35
2412fa
For more information www.linear.com/LTC2412
APPLICATIONS INFORMATION
Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (50Hz Notch)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2412 F40
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
FO = 5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL-SCALE)
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
LTC2412
36
2412fa
For more information www.linear.com/LTC2412
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN16 REV B 0212
1 2 345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC2412
37
2412fa
For more information www.linear.com/LTC2412
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Updated fEOSC maximum to 500kHz and all associated information 5, 6, 7, 9, 28,
29, 30
LTC2412
38
2412fa
For more information www.linear.com/LTC2412
LINEAR TECHNOLOGY CORPORATION 2002
LT 0815 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2412
RELATED PARTS
TYPICAL APPLICATION
0.1µF4.7µF 1
2
4
5
6
7
3
8, 9, 10, 15, 16
14
13
12
11
VCC
REF+
CH0+
CH0–
CH1+
CH1¯
REF–
GND
FO
SCK
SDO
CS
LTC2412
FO SELECTED
FOR 60Hz
REJECTION
INTERSEMA
MSS401-BM
1 BAR FS
4
3
2
1
R1
6.8k
50ppm/°C
5V
2412 TA05
PART NUMBER DESCRIPTION COMMENTS
LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max
LTC1043 Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift
LT1461 Micropower Precision LDO Reference High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411 24-Bit, No Latency ∆Σ ADC in MSOP 1.45µVRMS Noise, 2ppm INL
LTC2411-1 24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC 0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
LTC2413 24-Bit, No Latency ∆Σ ADC Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2414/LTC2418 8-/16-Channel, 24-Bit No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2415 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate Pin Compatible with the LTC2410
LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
LTC2440 High Speed, Low Noise 24-Bit ADC 4kHz Output Rate, 200nV Noise, 24.6 ENOBs
Figure 41. Measure Barometric Pressure and Temperature with a Single Sensor
