THC63LVD823B - THine Electronics, Inc.

THC63LVD823B_Rev.3.1_E

THC63LVD823B

160MHz 51Bits LVDS Transmitter

General Description

The THC63LVD823B transmitter is designed to sup-

port Single Link transmission between Host and Flat

Panel Display and Dual Link transmission between

Host and Flat Panel Display up to 1080p/QXGA resolu-

tions.

The THC63LVD823B converts 5 1bits of CMOS/ TTL

data into LV DS (Low Voltage Differential Signaling)

data stream. The transmitter can be programmed for ris-

ing edge or fal li ng edge clocks through a dedicated pin.

In Dual Link, the t ransmit clock freq uency of 160MHz,

51bits of RGB data are transmitted at an effective rate

of 1.12Gbps per LVDS channel.

Features

•Wide dot clock range suited for TV Signal (480p-

1080p), PC Signal (VGA-QXGA)

TTL/CMOS Input: 10-160MHz

LVDS Output: 20-160MHz

•PLL requires No external components

•Flexible Input/Output mod e

1. Single/Dual TTL IN, Single/Dual LVDS OUT

2. Double edge input for Single TTL IN/Dual LVDS OUT

•Clock edge selectable

•2 LVDS data mapping for simplifying PCB layout.

•Pseudo Random pattern generation circuit

•Supports Reduced swing LVDS for Low EMI

•Power down mode

•Low power single 3.3V CMOS design

•1.2 up to 3.3V tolerant data inputs to connect

directly to low power,low voltage application and

graphic processor.

•Backward compatible with THC63LVD823/

THC63LVD823A

•100pin TQFP

Block Diagram

PARALLEL TO SERIAL

PLL

TA1 +/-

TB1 +/-

TC1 +/-

TD1 +/-

TCLK1 +/-

/PDWN

(20 to 160MHz)

TRANSMITTER CLOCK IN

(10 to 160MHz)

R1[7:0]

LVDS OUTPUT

24

DATA Port1

TCLK2 +/- (N/C)

Port1

G1[7:0]

B1[7:0]

HSYNC

28

Data Formatter

28

R/F

1) DEMUX

2) MUX

VSYNC

DE

MAP

R2[7:0] 24

DATA Port2 G2[7:0]

B2[7:0]

3

RS

MODE[1:0]

PRBS

PARALLEL TO SERIAL

TA2 +/-

TB2 +/-

TC2 +/-

TD2 +/-

LVDS OUTPUT

Port2

O/E

DDRN

THC63LVD823B_Rev.3.1_E

Pin Out (top view)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

B24

B25

VCC

GND

B26

B27

HSYNC

VSYNC

DE

CLKIN

R/F

RS

DDRN

MAP

MODE1

MODE0

O/E

GND

/PDWN

PRBS

Reserved

N/C

PGND

PVCC

PGND

LGND

TD2+

TD2-

TCLK2-

TC2+

TC2-

TB2+

TB2-

TA2+

TA2-

LGND

B14

GND

VCC

B13

B12

B11

B10

G17

G16

G15

G14

G13

G12

G11

G10

R17

R16

R15

R14

GND

VCC

R13

R12

R10

B15

B16

B17

R20

R21

R22

R23

R24

R25

R26

R27

VCC

GND

G20

G21

G22

G23

G24

G25

G26

G27

B20

B21

B22

B23

TCLK2+

TD1+

TD1-

TC1+

TC1-

TCLK1+

TCLK1-

TB1+

TB1-

TA1-

TA1+

LVCC

R11

THC63LVD823B_Rev.3.1_E

Pin Description

Pin Name Pin # Type Description

TA1+, TA1- 48, 49

LVDS OUT The 1st Link .

The 1st pixel output data when Dual-Link.

TB1+, TB1- 46, 47

TC1+, TC1- 43, 44

TD1+, TD1- 39, 40

TCLK1+, TCLK1- 41, 42 LVDS OUT LVDS Clock Out for 1st and 2nd Link.

TA2+, TA2- 36, 37

LVDS OUT The 2nd Link.

These pins are disabled when Single Link.

TB2+, TB2- 34, 35

TC2+, TC2- 31, 32

TD2+, TD2- 27, 28

TCLK2+, TCLK2- 29, 30 LVDS OUT Additional LVDS Clock Out. Identical to TCLK1+,-.

No connect if not used.

R17 ~ R10 60 -57, 54 - 51 IN The 1st Pixel Data Inputs.G17 ~ G10 68 - 61

B17 ~ B10 78 - 73, 70, 69

R27 ~ R20 86 - 79

IN The 2nd Pixel Data Inputs.

G27 ~ G20 96 - 89

B27 ~ B20 6, 5, 2, 1,

100 - 97

DE 9 IN Data Enable Input.

VSYNC 8 IN Vsync Input.

HSYNC 7 IN Hsync Input.

CLKIN 10 IN Clock Input.

R/F 11 IN Input Clock Triggering Edge Select.

H: Rising edge, L: Falling edge

RS 12 IN

LVDS swing mode, VREF select. See Fig4 - 5.

MAP 14 IN

LVDS mapping table select. See Fig7 to 8 and Table4 to 7.

MODE1, MODE0 15, 16 IN

RS LVDS

Swing Small Swing

Input Support

VIHM 350mV N/A

VIMM 350mV RS=VREFa

a. VREF is Input Reference Voltage.

VILM 200mV N/A

MAP Mapping Mode

VIHM Mapping MODE1

VILM Mapping MODE2

VIMM Reserved

Pixel Data Mode.

MODE

1MODE0 Mode

L L Dual Link (Dual-in/Dual-out)

H L Dual Link (Single-in/Dual-out)

L H Single Link (Dual-in/Single-out)

H H Single Link (Single-in/Single-out)

THC63LVD823B_Rev.3.1_E

a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequen ce of

223-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and seria lized

into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission

channel including PCB traces, connectors, and cables.

O/E 17 IN Output enable.

H: Output enable,

L: Output disable (all outputs are Hi-Z).

/PDWN 19 IN H: Normal operation,

L: Power down (all outputs are Hi-Z)

PRBS a20 IN

PRBS (Pseudo-Random Binary Sequence) generator is

active in order to evaluate eye patterns when

MODE<1:0> = LL (Dual-in/Dual-out mode).

H: PRBS generator is enable.

L: Normal Operation

Reserved 21 IN Must be tied to GND.

DDRN 13 IN

DDR function is active when

MODE<1:0> = HL (Single-in/Dual-out mode).

Open or H: DDR (Double Edge input) function disable.

L: DDR (Double Edge input) function enable.

N/C 22 Must be Open.

VCC 3, 55, 71, 87 Power Power Supply Pins for TTL inputs and digital circuitry.

GND 4, 18, 56,

72, 88 Ground Ground Pins for TTL inpu ts and digital circuitry.

LVCC 33, 45 Power Power Supply Pins for LVDS Outputs.

LGND 26, 38, 50 Ground Ground Pins for LVDS Outputs.

PVCC 24 Power Power Supply Pin for PLL circuitry.

PGND 23, 25 Ground Ground Pins for PLL circuitry.

Pin Name Pin # Type Description

Pin Description (Continued)

THC63LVD823B_Rev.3.1_E

Absolute Maximum Ratings

Recommended Operating Conditions

Supply Voltage (VCC)-0.3V ~ +4.0V

CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)

LVDS Transmitter Output Voltage -0.3V ~ (VCC + 0.3V)

Output Current -30mA ~ 30mA

Junction Temperature +125

Storage Temperature Range -55 ~ +125

Reflow Peak Temperature / Time +260 / 10sec.

Maximum Power Dissipation @+25 2.4W

Parameter Min. Typ Max Units

All Supply Voltage 3.0 3.3 3.6 V

Operating Ambient Temperature -20 70

Clock

Frequency

MODE<1:0>=LL

Dual-in/Dual-out Input 20 160 MHz

LVDS Output 20 160 MHz

MODE<1:0>=LH

Dual-in/Single-out Input 10 80 MHz

LVDS Output 20 160 MHz

MODE<1:0>=HL

Single-in/Dual-out

Single Edge Input

(DDRN =Open/H) Input 40 160 MHz

LVDS Output 20 80 MHz

Double Edge Input

(DDRN=L) Input 20 80 MHz

LVDS Output 20 80 MHz

MODE<1:0>=HH

Single-in/Single-out Input 20 160 MHz

LVDS Output 20 160 MHz

°C

°C°C

°C

THC63LVD823B_Rev.3.1_E

Electrical Characteristics

CMOS/TTL DC Specifications

VCC = VCC=PVCC=LVCC

LVDS Transmitter DC Specifications VCC = VCC=PVCC=LVCC

Symbol Parameter Conditions Min. Typ. Max. Units

VIHa

a. CLKIN,R10~R17,G10~G17,B10~B17,R20~R27,G20~G27,B20~B27,DE,HSYNC,VSYNC

High Level Data Input Voltage RS=VIHMor VILM 2.0 VCC V

RS=VIMM VREFb+0.1

b. VREF is input voltage of RS pin.

V

VILaLow Level Data Input Voltage RS=VIHMor VILM GND 0.8 V

RS=VIMM VREF-0.1 V

VIHCc

c. R/F,DDRN,MODE0,MODE1,O/E,PDWN,PRBS

High Level Control Input Voltage 2.0 VCC V

VILCcLow Level Control Input Voltage GND 0.8 V

VIHMdHigh Level Control Input Voltage 0.8VCC VCC V

VIMMd

d. RS,MAP

Middle Level Control Input Voltage 0.6 1.4 V

VILMdLow Level Control Input Voltage GND 0.08VCC V

IINC Input Current (except DDRN) μA

IINCD Input Current (Only DDRN) μA

Symbol Parameter Conditions Min. Typ. Max. Units

VOD Differential Output Voltage RL=100Ω

Normal swing

RS= VCC 250 350 450 mV

Reduced swing

RS= GND 100 200 300 mV

ΔVOD Change in VOD between

complementary output states RL=100Ω

35 mV

VOC Common Mode Voltage 1.125 1.25 1.375 V

ΔVOC Change in VOC between

complementary output states 35 mV

IOS Output Short Circuit Current VOUT=GND, RL=100Ω-24 mA

IOZ Output TRI-State current /PDWN=GND,

VOUT=GND to VCC μA

GND VIN VCC

≤≤ 10±

GND VIN VCC

≤≤ 20±

10±

THC63LVD823B_Rev.3.1_E

Electrical Characteristics (Continued)

Supply Current VCC = VCC=PVCC=LVCC

Symbol Parameter Condition Typ. Max. Units

ITCCW

Transmitter Supply

Current

(Worst Case

Pattern) Fig1.

RL=100Ω

CL=5pF

RS=VCC

MODE<1:0>=HH

Single-in/Single-out

CLKIN=65MHz 86 mA

CLKIN=85MHz 100 mA

CLKIN=135MHz 122 mA

CLKIN=160MHz T.B.D mA

MODE<1:0>=HL

Single-in/Dual-out

DDRN=H or Open

DDR Input Off

CLKIN=65MHz 114 mA

CLKIN=85MHz 116 mA

CLKIN=135MHz 155 mA

CLKIN=150MHz 168 mA

CLKIN=160MHz T.B.D mA

MODE<1:0>=HL

Single-in/Dual-out

DDRN=L

DDR Input On

CLKIN=32.5MHz 114 mA

CLKIN=42.5MHz 118 mA

CLKIN=67.5MHz 155 mA

CLKIN=75MHz 167 mA

CLKIN=80MHz T.B.D mA

MODE<1:0>=LH

Dual-in/Single-out

CLKIN=32.5MHz 84 mA

CLKIN=42.5MHz 98 mA

CLKIN=67.5MHz 120 mA

CLKIN=80MHz T.B.D mA

MODE<1:0>=LL

Dual-in/Dual-out

CLKIN=65MHz 144 mA

CLKIN=85MHz 171 mA

CLKIN=135MHz 217 mA

CLKIN=160MHz T.B.D mA

ITCCS

Transmitter Power

Down Supply

Current /PDWN = L, All Inputs = Fixed L or H 50 μA

Fig1. Test Pattern

Txy+

x= A, B, C, D

y=1,2

TCLK1+

(LVDS Output Full Toggle Pattern)

THC63LVD823B_Rev.3.1_E

Switching Characteristics

VCC = VCC=PVCC=LVCC

Symbol Parameter Min. Typ. Max. Units

tTCIP CLK IN Period(Fig4,5) 6.25 100 ns

tTCH CLK IN High Time(Fig4,5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns

tTCL CLK IN Low Time(Fig4,5) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns

tTS TTL Data Setup to CLK IN(Fig4,5) 2.5 ns

tTH TTL Data Hold from CKL IN(Fig4,5) 0.0 ns

tTCD

CLK IN to TCLK+/- Delay(Fig4,5)

MODE<1:0>=LL

Dual-in/Dual-out

(4+3/7)tTCIP

+2.6

(4+3/7)tTCIP

+7.5 ns

tTCOP CLK OUT Period(Fig6) 6.25 50 ns

tLVT LVDS Transition Time(Fig2) 0.6 1.5 ns

tTOP1 Output Data

Position0 (Fig6)

tTCOP =

6.25ns~20ns

-0.15 0.0 +0.15 ns

tTOP0 Output Data

Position1 (Fig6) ns

tTOP6 Output Data

Position2 (Fig6) ns

tTOP5 Output Data

Position3 (Fig6) ns

tTOP4 Output Data

Position4 (Fig6) ns

tTOP3 Output Data

Position5 (Fig6) ns

tTOP2 Output Data

Position6 (Fig6) ns

tTPLL Phase Lock Time(F ig 3) 10.0 ms

tDEINT

DE input period (Fig3-1)

Single-in / Dual-out, DDR Off mode

only(MODE<1:0>=HL,

DDRN =Open or H)

4tTCIP tTCIP*(2n) a

a. Refer to Fig3-1 for details.

ns

tDEH

DE High time (Fig3-1)

Single-in / Dual-out, DDR Off mode

only(MODE<1:0>=HL,

DDRN =Open or H)

2tTCIP tTCIP*(2m)ans

tDEL

DE Low time(Fig3-1)

Single-in / Dual-out, DDR Off mode

only(MODE<1:0>=HL,

DDRN =Open or H)

2tTCIP ns

tTCOP

7

--------------- 0.15–tTCOP

7

--------------- tTCOP

7

--------------- 0.15+

2tTCOP

7

--------------- 0.15–2tTCOP

7

--------------- 2tTCOP

7

--------------- 0.15+

3tTCOP

7

--------------- 0.15–3tTCOP

7

--------------- 3tTCOP

7

--------------- 0.15+

4tTCOP

7

--------------- 0.15–4tTCOP

7

--------------- 4tTCOP

7

--------------- 0.15+

5tTCOP

7

--------------- 0.15–5tTCOP

7

--------------- 5 tTCOP

7

--------------- 0.15+

6tTCOP

7

--------------- 0.15–6tTCOP

7

--------------- 6tTCOP

7

--------------- 0.15+

THC63LVD823B_Rev.3.1_E

AC Timing Diagrams

2.0V

tTPLL

CLKIN

/PDWN

TCLKx+/-

Vdiff=0V

Fig3. PLL Lock Time

x=1,2

5pF 20%

80%

20%

80%

tLVT tLVT

Vdiff

100Ω

Vdiff=(TA+)-(TA-)

TA+

TA-

LVDS Output Load

Fig2. LV DS Ou tpu t Lo a d an d Transition Time

CLKIN

DE

tDEINT

tDEH tDEL

Note: In single-in/dual-out, DDR off mode (MODE<1:0>=HL, DDRN =Open or H),

the period between rising edges of DE (tDEINT), high time of DE (tDEH)

tTCIP

Fig3-1. Single IN / Dual OUT, DDR off mode DE input timing

should always satisfy following equations.

tDEINT = tTCIP * (2n)

m, n =integ e r

tDEH = tTCIP * (2m)

THC63LVD823B_Rev.3.1_E

AC Timing Diagrams (Continued)

Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing

tTCIP

tTS tTH

tTCH tTCL

CLKIN

t

TCD

VOC

VREF VREF

VREF

Note:

CLKIN: for R/F=GND, denote as solid line,

for R/F=VCC, denote as dashed line.

GND

Rxn, Gxn, Bxn

HSYNC

VSYNC

DE

x=1,2 n=0-7

Current Data

TCLKx+/-

x=1,2

Current Data

Txy+/-

x=1,2

y= A, B, C, D

VOD

VCC

RS pin VOD VREF

VIHM 350mV VCC/2

VIMM Input Voltage of RS pin

VILM 200mV VCC/2

Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR)

Note:

CLKIN: for R/F=GND, denote as solid line,

for R/F=VCC, denote as dashed line.

MODE<1:0>=HL,DDRN=L

Current Data

Txy+/-

x=1,2

y= A, B, C, D

VREF VREF

1st Pixel

Data 2nd Pixel

Data GND

VOD

VCC

tTS tTH tTS tTH

tTCIP

tTCH tTCL

CLKIN

t

TCD

VOC

VREF VREF VREF

GND

Rxn, Gxn, Bxn

VSYNC

DE

x=1,2 n=0-7

TCLKx+/-

x=1,2

RS pin VOD VREF

VIHM 350mV VCC/2

VIMM Input Voltage of RS pin

VILM 200mV VCC/2

HSYNC

THC63LVD823B_Rev.3.1_E

AC Timing Diagrams (Continued)

Vdiff = 0V

Tyx+/- Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1

Vdiff = 0V

tTOP2

tTOP3

tTOP4

tTOP5

tTOP6

tTOP0

tTOP1

tTCOP

TCLKx+

x = 1,2

y = A,B,C,D Note:

Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-)

Fig6. LVDS Output Data Position

THC63LVD823B_Rev.3.1_E

Input Data Mapping

•Table1. Input Color Data naming rule

•Table2. TTL/CMOS Input Data Mapping (Single-in mode, MODE1=H)

X Y Z Description

X=R Red Color Data

X=G Green Color Data

X=B Blue Color Data

Y= None Single Pixel

Y=E Dual Pixel 1st Pixel Data

Y=O 2nd Pixel Data

Z=0-7 Bit number 0: LSB (Least Significant Bit)

7: MSB (Most Significant Bit)

Data Signals Transmitter

Input Pin Names

R0 R10

R1 R11

R2 R12

R3 R13

R4 R14

R5 R15

R6 R16

R7 R17

G0 G10

G1 G11

G2 G12

G3 G13

G4 G14

G5 G15

G6 G16

G7 G17

B0 B10

B1 B11

B2 B12

B3 B13

B4 B14

B5 B15

B6 B16

B7 B17

THC63LVD823B_Rev.3.1_E

Input Data Mapping (Continued)

•Table3. TTL/CMOS Input Data Mapping (Dual-in mode, MODE1=L)

Data Signals Transmitter

Input Pin Names Data Signals Transmitter

Input Pin Names

RE0 R10 RO0 R20

RE1 R11 RO1 R21

RE2 R12 RO2 R22

RE3 R13 RO3 R23

RE4 R14 RO4 R24

RE5 R15 RO5 R25

RE6 R16 RO6 R26

RE7 R17 RO7 R27

GE0 G10 GO0 G20

GE1 G11 GO1 G21

GE2 G12 GO2 G22

GE3 G13 GO3 G23

GE4 G14 GO4 G24

GE5 G15 GO5 G25

GE6 G16 GO6 G26

GE7 G17 GO7 G27

BE0 B10 BO0 B20

BE1 B11 BO1 B21

BE2 B12 BO2 B22

BE3 B13 BO3 B23

BE4 B14 BO4 B24

BE5 B15 BO5 B25

BE6 B16 BO6 B26

BE7 B17 BO7 B27

THC63LVD823B_Rev.3.1_E

LVDS Output Data Mapping

Tx1+/-

TCLK1+

Previous Cycle Current Cycle

Fig7. TTL Data Inputs Mapped to LVDS outputs

MODE0= H (Single-out Mode)

x= A, B, C, D

Tx11(n-1) Tx10(n-1) Tx16(n) Tx15(n) Tx14(n) Tx13(n) Tx12(n) Tx11(n) Tx10(n) Tx16(n+1)

(2nd Pixel Data) (1st Pixel Data) Next Cycle

(2nd Pixel Data)

Tx1+/-

TCLK1+

Previous Cycle Current Cycle

Fig8. TTL Data Inputs Mapped to LVDS outputs

MODE0= L (Dual-out Mode)

x= A, B, C, D

Tx11(n-1) Tx10(n-1) Tx16(n) Tx15(n) Tx14(n) Tx13(n) Tx12(n) Tx11(n) Tx10(n) Tx16(n+1)

Tx21(n-1) Tx20(n-1) Tx26(n) Tx25(n) Tx24(n) Tx23(n) Tx22(n) Tx21(n) Tx20(n) Tx26(n+1)

Tx2+/-

x= A, B, C, D

THC63LVD823B_Rev.3.1_E

LVDS Output Data Mapping (Continued)

•Table4. LVDS Output Data Mapping (Single-in/Single-out, MODE<1:0>=HH)

LVDS

Output

Data

Mapping Mode (Input Pin Name)

Mode1

MAP=H Mode2

MAP=L

TA10 R12 R10

TA11 R13 R11

TA12 R14 R12

TA13 R15 R13

TA14 R16 R14

TA15 R17 R15

TA16 G12 G10

TB10 G13 G11

TB11 G14 G12

TB12 G15 G13

TB13 G16 G14

TB14 G17 G15

TB15 B12 B10

TB16 B13 B11

TC10 B14 B12

TC11 B15 B13

TC12 B16 B14

TC13 B17 B15

TC14 HSYNC HSYNC

TC15 VSYNC VSYNC

TC16 DE DE

TD10 R10 R16

TD11 R11 R17

TD12 G10 G16

TD13 G11 G17

TD14 B10 B16

TD15 B11 B17

TD16 N/A N/A

THC63LVD823B_Rev.3.1_E

LVDS Output Data Mapping (Continued)

•Table5. LVDS Output Data Mapping (Single-in/Dual-out, DDR On/Off, MODE<1:0>=HL, DDRN =Open/H/L)

LVDS

Output Data

(1st Link)

Mapping Mode (Input Pin Name) LVDS

Output Data

(2nd Link)

Mapping Mode (In pu t Pin Name)

Mode1

MAP=H Mode2

MAP=L Mode1

MAP=H Mode2

MAP=L

TA10 R12 R10 TA20 R12 R10

TA11 R13 R11 TA21 R13 R11

TA12 R14 R12 TA22 R14 R12

TA13 R15 R13 TA23 R15 R13

TA14 R16 R14 TA24 R16 R14

TA15 R17 R15 TA25 R17 R15

TA16 G12 G10 TA26 G12 G10

TB10 G13 G11 TB20 G13 G11

TB11 G14 G12 TB21 G14 G12

TB12 G15 G13 TB22 G15 G13

TB13 G16 G14 TB23 G16 G14

TB14 G17 G15 TB24 G17 G15

TB15 B12 B10 TB25 B12 B10

TB16 B13 B11 TB26 B13 B11

TC10 B14 B12 TC20 B14 B12

TC11 B15 B13 TC21 B15 B13

TC12 B16 B14 TC22 B16 B14

TC13 B17 B15 TC23 B17 B15

TC14 HSYNC HSYNC TC24 HSYNC HSYNC

TC15 VSYNC VSYNC TC25 VSYNC VSYNC

TC16 DE DE TC26 DE DE

TD10 R10 R16 TD20 R10 R16

TD11 R11 R17 TD21 R11 R17

TD12 G10 G16 TD22 G10 G16

TD13 G11 G17 TD23 G11 G17

TD14 B10 B16 TD24 B10 B16

TD15 B11 B17 TD25 B11 B17

TD16 N/A N/A TD26 N/A N/A

DE

R1n,G1n,B1n

Fig9. The decision rule of 1st Pixel data in Single IN/Dual Out DDR Off

1st Pixel Data 2nd Pixel Data 1st Pixel Data 2nd Pixel Data

n=0 - 7

Hsync

Vsync

GND

VCC

GND

(MODE<1:0>=HL, DDRN =Open or H)

THC63LVD823B_Rev.3.1_E

LVDS Output Data Mapping (Continued)

•Table6. LVDS Output Data Mapping (Dual-in/Single-out, MODE<1:0>=LH)

LVDS

Output Data

(1st Pixel)

Mapping Mode (Input Pin Name) LVDS

Output Data

(2nd Pixel)

Mapping Mode (Input Pin Name)

Mode1

MAP=H Mode2

MAP=L Mode1

MAP=H Mode2

MAP=L

TA10(n) R12 R10 TA10(n+1) R22 R20

TA11(n) R13 R11 TA11(n+1) R23 R21

TA12(n) R14 R12 TA12(n+1) R24 R22

TA13(n) R15 R13 TA13(n+1) R25 R23

TA14(n) R16 R14 TA14(n+1) R26 R24

TA15(n) R17 R15 TA15(n+1) R27 R25

TA16(n) G12 G10 TA16(n+1) G22 G20

TB10(n) G13 G11 TB10(n+1) G23 G21

TB11(n) G14 G12 TB11(n+1) G24 G22

TB12(n) G15 G13 TB12(n+1) G25 G23

TB13(n) G16 G14 TB13(n+1) G26 G24

TB14(n) G17 G15 TB14(n+1) G27 G25

TB15(n) B12 B10 TB15(n+1) B22 B20

TB16(n) B13 B11 TB16(n+1) B23 B21

TC10(n) B14 B12 TC10(n+1) B24 B22

TC11(n) B15 B13 TC11(n+1) B25 B23

TC12(n) B16 B14 TC12(n+1) B26 B24

TC13(n) B17 B15 TC13(n+1) B27 B25

TC14(n) HSYNC HSYNC TC14(n+1) HSYNC HSYNC

TC15(n) VSYNC VSYNC TC15(n+1) VSYNC VSYNC

TC16(n) DE DE TC16(n+1) DE DE

TD10(n) R10 R16 TD10(n+1) R20 R26

TD11(n) R11 R17 TD11(n+1) R21 R27

TD12(n) G10 G16 TD12(n+1) G20 G26

TD13(n) G11 G17 TD13(n+1) G21 G27

TD14(n) B10 B16 TD14(n+1) B20 B26

TD15(n) B11 B17 TD15(n+1) B21 B27

TD16(n) N/A N/A TD16(n+1) N/A N/A

THC63LVD823B_Rev.3.1_E

LVDS Output Data Mapping (Continued)

•Table7. LVDS Output Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL)

LVDS

Output Data

(1st Link)

Mapping Mode (Input Pin Name) LVDS

Output Data

(2nd Link)

Mapping Mode (Input Pin Name)

Mode1

MAP=H Mode2

MAP=L Mode1

MAP=H Mode2

MAP=L

TA10 R12 R10 TA20 R22 R20

TA11 R13 R11 TA21 R23 R21

TA12 R14 R12 TA22 R24 R22

TA13 R15 R13 TA23 R25 R23

TA14 R16 R14 TA24 R26 R24

TA15 R17 R15 TA25 R27 R25

TA16 G12 G10 TA26 G22 G20

TB10 G13 G11 TB20 G23 G21

TB11 G14 G12 TB21 G24 G22

TB12 G15 G13 TB22 G25 G23

TB13 G16 G14 TB23 G26 G24

TB14 G17 G15 TB24 G27 G25

TB15 B12 B10 TB25 B22 B20

TB16 B13 B11 TB26 B23 B21

TC10 B14 B12 TC20 B24 B22

TC11 B15 B13 TC21 B25 B23

TC12 B16 B14 TC22 B26 B24

TC13 B17 B15 TC23 B27 B25

TC14 HSYNC HSYNC TC24 HSYNC HSYNC

TC15 VSYNC VSYNC TC25 VSYNC VSYNC

TC16 DE DE TC26 DE DE

TD10 R10 R16 TD20 R20 R26

TD11 R11 R17 TD21 R21 R27

TD12 G10 G16 TD22 G20 G26

TD13 G11 G17 TD23 G21 G27

TD14 B10 B16 TD24 B20 B26

TD15 B11 B17 TD25 B21 B27

TD16 N/A N/A TD26 N/A N/A

THC63LVD823B_Rev.3.1_E

Note

1)Cable Connection and Disconnection

Don't connect and disconnect the LVDS cable, when the power is suppl ied to the system.

2)GND Connection

Connect the each GND of the PCB which THC63LVD823B and LVDS-Rx on it. It is better for EMI reduction to

place GND cable as close to LVDS cable as possible.

3)Multi Drop Connection

Multi drop connection is not recommended.

4)Asynchronous use

Asynchronous use such as following systems are not recommended.

LVDS-Rx

THC63LVD823B LVDS-Rx

TCLK+

TCLK-

THC63LVD823B

IC

CLKOUT

DATA

DATA LVDS-Rx

LVDS-Rx

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

THC63LVD823B

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

IC

THC63LVD823B_Rev.3.1_E

Package

SEATING PLANE

0.25mm

GAGE

PLANE

16.00 BSC

14.00 BSC

16.00 BSC

14.00 BSC

0°～7.0°

S

0.10 S

0.20 BSC

0.60 +/-0.15

0.08R MIN

0.08R～0.20R

1.20 MAX

1.00 +/-0.05

0.05～0.15

1.00 REF

0.09～0.20

Unit：mm

0.50 BSC 0.20 +0.07/-0.03

THC63LVD823B_Rev.3.1_E

Notices and Requests

1.)The product specifications described in this material are subject to change without prior notice.

2.)The circuit diagrams described in this material are examples of the a pplication which may not

always apply to the customer's design. We are not responsible for possible errors and omissions in

this material. Please note if errors or omissions should be found in this material, we may not be able

to correct them immediately.

3.)This material contains our copy right, know-how or other proprietary. Copying or disclosing to

third parties the contents of this material without our prior permission is prohibited.

4.)Note that if infringement of any third party's industrial ownership should occur by using this

product, we will be exempted from the responsibility unless it directly relates to the production pro-

cess or functions of the product.

5.)This product is presumed to be used for general electric equipment, not for the applications

which require very high reliability (including medical equipment directly concerning people's life,

aerospace equipment, or nuclear control equipment). Also, when using this product for the equip-

ment concerned with the control and safety of the transportation means, the traffic signal equip-

ment, or various Types of safety equipment, please do it after applying appropriate measures to the

product.

6.)Despite our utmost efforts to improve the quality and reliability of the product, faults will occur

with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are

encouraged to have sufficiently redundant or error preventive design applied to the use of the prod-

uct so as not to have our product cause any social or public damage.

7.)Please note that this product is not designed to be radiation-proof.

8.)Customers are asked, if required, to judge by themselves if this product falls under the category

of strategic goods under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

E-mail: sales@thine.co.jp