1. General description
The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit,
bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19
signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and
ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to
interface 3.3 V or 5.0 V devices.
The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the
B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR.
The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs,
depending on the state of the high drive enable pin HD. The A-bus has only totem pole
style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at
VCC = 3.3 V.
2. Features
nAsynchronous operation
n8-bit transceivers
nSix additional buffer/driver lines peripheral to cable
nFive additional control lines from cable
n5 V tolerant
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nLatch-up current protection exceeds 500 mA per JEDEC Std 19
nInput hysteresis
nLow-noise operation
nIEEE 1284 compliant level 1 and 2
nOvervoltage protection on B/Y side for off-state
nA side 3-state option
nB side active or resistive pull-up option
nCable side supply voltage for 5 V or 3 V operation
PDI1284P11
3.3 V parallel interface transceiver/buffer
Rev. 03 — 25 August 2008 Product data sheet
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 2 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
PDI1284P11DL 0 °C to 70 °C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
PDI1284P11DGG 0 °C to 70 °C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 3 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
4. Functional diagram
Fig 1. Logic symbol
001aai290
CNTLHD
A9
DIR
Y9
OEA
HD
HD
PLHI PLHO
A14 C14
HD
A10 Y10
HD
A11 Y11
HD
A12 Y12
HD
A13
A1
Y13
B1
HD
HD
CNTL
A2 B2
HD
CNTL
A3 B3
HD
CNTL
A4 B4
HD
CNTL
A5 B5
HD
CNTL
A6 B6
HD
CNTL
A7 B7
HD
CNTL
A15 C15
A16 C16
A17 C17
HLHO HLHI
A8 B8
HD
CNTL
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 4 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Pin configuration
PDI1284P11
HD DIR
A9 Y9
A10 Y10
A11 Y11
A12 Y12
A13 Y13
VCC VCC(B)
A1 B1
A2 B2
GND GND
A3 B3
A4 B4
A5 B5
A6 B6
GND OEA
A7 B7
A8 B8
VCC VCC(B)
PLHI PLHO
A14 C14
A15 C15
A16 C16
A17 C17
HLHO HLHI
001aai291
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Table 2. Pin description
Symbol Pin Description
HD 1 high drive enable/disable input
A1 to A8 8, 9, 11, 12, 13,
14, 16, 17 data input/output
B1 to B8 41, 40, 38, 37,
36, 35, 33, 32 IEEE 1284 standard output/input[1]
A9 to A13 2, 3, 4, 5, 6 data input
Y9 to Y13 47, 46, 45, 44, 43 IEEE 1284 standard output[1]
C14 to C17 29, 28, 27, 26 control input (cable)[1]
A14 to A17 20, 21, 22, 23 control output (peripheral)
VCC 7, 18 supply voltage
GND 10, 15, 39 ground (0 V)
PLHI 19 peripheral logic high input (peripheral)
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 5 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
[1] Pin with pull-up resistor to load cable.
6. Functional description
6.1 Function selection
[1] An = side driving internal IC;
Bn = side driving external cable (bidirectional);
Cn = side receiving control signals from external cable;
H = HIGH voltage level;
L = LOW voltage level;
OC = Open Collector;
X = don’t care (control signals in);
Yn = side driving external cable (unidirectional);
Z = high impedance (high-Z) or 3-state;
TP = totem pole output;
RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and VCC. However, while a B/Y side output is LOW as driven by a LOW
signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it.
[2] When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩon
the input for this mode.
HLHO 24 host logic high output (cable)
HLHI 25 host logic high input (cable)
PLHO 30 peripheral logic high output (cable)
VCC(B) 31, 42 supply voltage B (cable side 3 V/5 V)
OEA 34 A side output enable input (active LOW)
DIR 48 direction selection input
Table 2. Pin description
…continued
Symbol Pin Description
Table 3. Function table[1]
DIR OEA HD Input Output Output type
X X X C14 to C17 A14 to A17 TP
X X X HLHI HLHO TP
X X L A9 to A13 Y9 to Y13 RP
X X H A9 to A13 Y9 to Y13 TP
X X L PLHI PLHO OC
X X H PLHI PLHO TP
H X L A1 to A8 B1 to B8 RP
H X H A1 to A8 B1 to B8 TP
L L X B1 to B8 A1 to A8 TP
L H X - A1 to A8 Z[2]
L H X B1 to B8 - RP[2]
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 6 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
7. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3] Vtrt guarantees only that the PDI1284P11 will not be damaged by reflections in application so long as the voltage levels remain in the
specified range.
[4] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
VCC supply voltage pins VCC −0.5 +4.6 V
VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V −0.5 +6.5 V
IIK input clamping current VI < 0 V - ±20 mA
IOK output clamping current VO < 0 V - ±50 mA
VIinput voltage [2] −0.5 +5.5 V
VOoutput voltage B/Y side [2] −0.5 +5.5 V
A side −0.5 VCC + 0.5 V
Vtrt transient voltage B/Y side; 40 ns transient [3] −2+7V
ICC supply current - 200 mA
IGND ground current −200 - mA
IOoutput current output HIGH or LOW - ±50 mA
Tstg storage temperature −60 +150 °C
Ptot total power dissipation Tamb =0°C to +70 °C[4] - 500 mW
Table 5. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage pins VCC 3.0 3.6 V
VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V 3.0 5.5 V
VIH HIGH-level input voltage 2.0 - V
VIL LOW-level input voltage - 0.8 V
VOoutput voltage pins Bn, Yn −0.5 +5.5 V
pins An 0 VCC V
IOH HIGH-level output current pins Bn, Yn - −14 mA
IOL LOW-level output current pins Bn, Yn - 14 mA
Tamb ambient temperature free-air 0 70 °C
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 7 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
9. Static characteristics
[1] Typical values at Tamb =25°C.
[2] Includes extra ICC(B) current from pull-up resistors, i.e. ICC(B) = (total number of LOW inputs on B and C sides) ×(VCC(B) /R
PU).
[3] The pull-up resistor on the B side outputs makes it impossible to test IOZ on the B side. This applies to the input current on the C side
inputs as well.
Table 6. Static characteristics
T
amb
= 0
°
C to 70
°
C; ground = 0 V; unless specified otherwise.
Symbol Parameter Conditions Min Typ Max Unit
VIL LOW-level input
voltage An, Bn, Cn and PLHI inputs; VCC = 3.0 V to 3.6 V - - 0.8 V
HLHI input; VCC = 3.0 V - - 1.55 V
VIH HIGH-level input
voltage An, Bn, PLHI inputs; VCC = 3.0 V to 3.6 V 2.0 - - V
Cn inputs; VCC = 3.0 V to 3.6 V 2.3 - - V
HLHI input; VCC = 3.6 V 2.6 - - V
VHhysteresis
voltage An, Bn inputs; VCC = 3.3 V; VIL = 0.8 V; VIH = 2.0 V [1] 0.4 0.47 - V
Cn inputs; VCC = 3.3 V [1] 0.8 0.47 - V
VOL LOW-level
output voltage pins An, HLHO; IOL = 50 µA; VCC = 3.0 V - - 0.2 V
pins An, HLHO; IOL = 4 mA; VCC = 3.0 V - - 0.4 V
pins Bn, Yn; IOL = 14 mA; VCC = 3.0 V - - 0.77 V
pin PLHO; IOL = 500 µA; VCC = 3.0 V - - 0.8 V
VOH HIGH-level
output voltage pins An, HLHO; IOH = −500 µA; VCC = 3.0 V 2.8 - - V
pins An, HLHO; IOH = −4 mA; VCC = 3.0 V 2.4 - - V
pins Bn, Yn; IOH =−14 mA; VCC = 3.0 V 2.23 - - V
pin PLHO; IOH = 500 µA; VCC = 3.15 V 3.1 - - V
ICC supply current VI=0 VorV
CC; IO = 0 A [1] -5- µA
pins VCC and VCC(B); VCC = 3.6 V; VCC(B) = 3.6 V to 5.5 V;
VI=0 VorV
CC; pins Bn = VCC(B); pins Cn = VCC(B) or
floating
- 0.1 100 µA
pins VCC(B); VCC = 3.6 V; VI=0 VorV
CC; pins Cn = 0 V [2]
pin DIR = 3.6 V; VCC(B) = 3.6 V - 10 15 mA
pin DIR = 3.6 V; VCC(B) = 5.5 V - 16 20 mA
pin DIR = 0 V; VCC(B) = 3.6 V; pins Bn = 0 V - 30 40 mA
pin DIR = 0 V; VCC(B) = 5.5 V; pins Bn = 0 V - 47 60 mA
IOFF power-off
leakage current pins Bn, Cn, Yn; VO= 5.5 V; VCC =0 V
VCC(B) =0V - - ±100 µA
VCC(B) = 4.5 V - - ±100 µA
IIinput leakage
current VI=0VtoV
CC [3] --±1µA
IOZ OFF-state
output current 3-state; VO=V
CC or 0 V [3] --±20 µA
Rooutput
resistance VCC = 3.3 V; see Figure 9
VO= 1.65 V ±0.1 V; B/Y side [1] 35 45 55 Ω
RPU pull-up
resistance B/Y side; VCC = 3.3 V; output in high-Z with resistive pull-up [1] 1.15 1.4 1.65 kΩ
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 8 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
10. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL.
[2] Value at Tamb =25°C and VCC = 3.3 V.
[3] tdis is the same as tPHZ and tPLZ.
[4] ten is the same as tPZH and tPZL.
Table 7. Dynamic characteristics
V
CC
= 3.0 V to 3.6 V; ground = 0 V; C
L
= 50 pF; R
L
= 500
Ω
; T
amb
= 0
°
C to 70
°
C; unless specified otherwise.
Symbol Parameter Conditions Min Typ[2] Max Unit
tPLH LOW to HIGH
propagation delay An to Bn or Yn; see Figure 3 and 80 12.5 20 ns
tPHL HIGH to LOW
propagation delay An to Bn or Yn; see Figure 3 and 80 13.9 23 ns
tpd propagation delay see Figure 4 and 8[1]
Bn to An 0 - 12 ns
Cn to An - - 15 ns
PLHI to PLHO - - 20 ns
HLHI to HLHO - - 15 ns
SR slew rate Bn/Yn; RL =62Ω; see Figure 5 and 80.05 0.2 0.4 V/ns
tdis disable time HD to Yn or Bn; see Figure 6 and 8[3] - - 20 ns
HD to PLHO; see Figure 6 and 7[3] - - 20 ns
RL= 250 Ω; see Figure 6 and 7[3]
DIR to Bn; TP load on B/Y side - - 50 ns
DIR to An - - 15 ns
OEA to An - - 6 ns
ten enable time HD to Yn or Bn; see Figure 6 and 7[4] - - 20 ns
HD to PLHO; see Figure 6 and 7[4] - - 20 ns
RL= 250 Ω; see Figure 6 and 7[4]
DIR to Bn; TP load on B/Y side - - 30 ns
DIR to An - - 50 ns
OEA to An - - 12 ns
∆tPD propagation delay
difference tPZH − tPHZ; HD to output - - 10 ns
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 9 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
11. Waveforms
Fig 3. Input An to output Bn or Yn propagation delays
001aai293
2.4 V
0.4 V
VO
tPLH tPHL
VO − 1.4 V1.4 V
1.4 V 1.4 Vinput
output
VM = 1.5 V.
VCC never goes below 3.0 V.
VOL and VOH are the typical voltage output levels that occur with the output load.
Fig 4. Input Bn, Cn to output An propagation delays
001aai292
VM
input
output
tPHL tPLH
GND
VI
VOH
VOL
VM
Measurement data is given in Table 8.
SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition.
Fig 5. Slew rate on B/Y side
001aai295
t1
1.9 V
2.4 V
0.4 V
2.4 V
0.9 V
0.4 V
output
input
t2 t1 t2
Table 8. Slew rate measurements
trtftWRLVO transition (see Figure 8)
Rising Falling
3 ns 3 ns 150 ns < tW < 10 µs62Ωfrom VO= 0.4 V to VO= 0.9 V from VO= 2.4 V to VO= 1.9 V
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 10 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
Test circuit is shown in Figure 7.
Measurement points are given in Table 9.
VOL and VOH are the typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
001aai294
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
HD to B
DIR to B
DIR to A
VI
VOL
VOH
VCC
VM
VM
VM
GND
GND
tPZL
tPZH
VM
VM
Test conditions are given in Table 9.
Fig 7. Test circuit for measuring enable and disable times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 9. Test data for test circuit measuring enable disable times Bn to An
Parameter VCC Input Output VEXT
VIVMVMVXVYtPZH, tPHZ tPZL, tPLZ
DIR to Bn, An;
OEA to An < 2.7 V VCC 1.5 V 1.5 V VOL ± 0.3 V VOH − 0.3 V GND 2VCC
2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL ± 0.3 V VOH − 0.3 V GND 2VCC
HD to Yn or Bn;
HD to PHLO < 2.7 V VCC 1.5 V 1.5 V - VOH − 0.3 V open -
2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V - VOH − 0.3 V open -
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 11 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
a. Input pulse definition
b. Test circuit
CL = load capacitance includes jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance of the pulse generator.
Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8
Fig 8. Test circuit for An, Bn and Yn outputs; slew rate B/Y side
001aai298
VMVM
tW
tW
10 %
90 % 90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
90 %
10 % 10 %
tf
tr
tr
tf
RL
CL
001aai296
VCC
VIVOVEXT
GND
RT
DUT
G
Table 10. Test conditions for An, Bn and Yn outputs
Output VIVMRepetition
rate tWtrtfSwitch position
tPLH, tPZH tPHL, tPHZ
An 3.0 V 1.5 V 1 MHz 500 ns 3ns 3ns GND GND
Bn, Yn 3.0 V 1.5 V 1 MHz 500 ns 3ns 3ns GND VEXT = 2.8 V
IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro= 0.5VCC /|IO|.
Fig 9. Output impedance
001aai299
VCC / 2
DUT IO
VCC
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 12 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
12. Package outline
Fig 10. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 13 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
Fig 11. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 14 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ECP Extended Capability Port
EPP Enhanced Parallel Port
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PDI1284P11_3 20080825 Product data sheet - PDI1284P11_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Quick reference table removed.
•Table 7, tPHL: Maximum value of 20 ns replaced by 23 ns.
•Table 11: Abbreviations list added.
PDI1284P11_2 19990917 Product specification - PDI1284P11_1
PDI1284P11_1 19970915 Product specification - -
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 15 of 16
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PDI1284P11
3.3 V parallel interface transceiver/buffer
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 August 2008
Document identifier: PDI1284P11_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
