DSP56303 USER’S MANUAL
DSP56303UM
Rev. 2, October 2005
Document Order Number: DSP56303UM
Rev. 2
10/2005
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1
DSP 56303 Overview
2
Signals/Connections
4
C ore Co nf igu ra tion
B
Pr ogram m ing Re feren ce
Triple Timer Mo dule
H o st Inte rface (HI08)
Ser ial Co mmunication Interface (SCI)
9
6
8
A
Bootstr ap P r ogram
7
Enhanced Synchronous Serial Interface (ESSI)
I
Index
Programming the P eripherals
5
Me m o ry Co n figu ra tion
3
1
DS P56303 Over view
2
Signals/Connections
4
Core Configuration
B
Pro gra mming R ef ere nce
Tr iple Ti mer M odu le
H o st Inte rfac e (HI08 )
Serial Communi cation I nte rface (SC I)
9
6
8
A
Bootstrap Program
7
Enhanced Synchronous Serial Interface (ESSI)
I
Index
Pro gramming the Periph er als
5
Me m o ry Co n figu ra tion
3
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor v
Contents
1DSP56303 Overview
1.1 Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1- 2
1.3 Manual Revision History for Revision 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.4 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.5 DSP56300 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6 DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.6.1 Data ALU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.1.2 Multiplier-Accumulator (MAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.6.2 Address Ge neration Unit (AGU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.6.3 Program Control Unit (PCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.4 PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.5 JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.6 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.7 External Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.7 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 0
1.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1
1.9 Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2
1.9.1 GPIO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.9.2 HI08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -1 2
1.9.3 ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -1 2
1.9.4 SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.9.5 Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13
2Signals/Connections
2.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 External Memory Expansion Port (Port A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5.1 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5.2 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5.3 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7 Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.7.1 Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.7.2 Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8 Enhanced S ynchronous Serial Interface 0 (ESSI0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.9 Enhanced S ynchronous Serial Interface 1 (ESSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.10 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
DSP56303 User’s Manual, Rev. 2
vi Freescale Semiconductor
Contents
2.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -1 7
2.12 JTAG/OnCE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
3Memory Configuration
3.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Internal Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.2 Memory Switch Modes—Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.3 Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.1.4 Program Bootstrap ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.1 Internal X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.2 Memory Switch Modes—X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.3 Internal I/O Space—X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.1 Internal Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.2 Memory Switch Modes—Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.3 External I/O Space—Y Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Dynamic Memory Configuration Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Sixteen-Bit Compatibility Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.6 RAM Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -5
3.7 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
4Core Configuration
4.1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3 Central Processor Unit (CPU) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
4.3.1 Status Register (SR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4 Configuring Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5
4.4.1 Interrupt Priority Registers (IPRC and IPRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.4.2 Interrupt Table Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16
4.4.3 Processing Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.5 PLL Control Register (PCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.6 Bus Interface Unit (BIU) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.6.1 Bus Control Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.6.2 DRAM Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.6.3 Address Attribute Regist ers (AAR[ 0–3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4.7 DMA Control Registers 5–0 (DCR[5–0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.8 Device Identification Register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-33
4.9 JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 3 4
4.10 JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
5Programming the Pe ripherals
5.1 Peripheral Initialization Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 1
5.2 Mapping the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 Reading Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.4 Data Transfer Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.4.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor vii
Contents
5.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.4.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4.4 Advantages and Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5 General-Purpose I nput/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.1 Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.2 Port C Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.5.3 Port D Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.5.4 Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.5.5 Triple Timer Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
6Host Interface (HI08)
6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 DSP Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.2 Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2 Host Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -5
6.4.1 Software Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.4.2 Core Interrupts and Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.4.3 Core DMA Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
6.4.4 Host Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.4.5 Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.5 Boot-up Using the HI08 Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
6.6 DSP Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.1 Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 1 2
6.6.2 Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 1 3
6.6.3 Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.6.4 Host Data Register (HDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.6.5 Host Base Address Register (HBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.6.6 Host Port Control Register (HPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6.7 Host Transmit (HTX) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
6.6.8 Host Receive (HRX) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
6.6.9 DSP-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20
6.7 Host Programmer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 2 0
6.7.1 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.7.2 Command Vector Register (CVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.7.3 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.7.4 Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.7.5 Receive Data Registers (RXH:RXM:RXL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.7.6 Transmit Data Registers (TXH:TXM:TXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.7.7 Host-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 2 7
6.8 Programming Model Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
7Enhanced Synchronous Serial Interface (ESSI)
7.1 ESSI Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2 ESSI Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 Serial Transmit Data Signal (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 2
7.2.2 Serial Receive Data Signal (SRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.2.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
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7.2.4 Serial Control Signal (SC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2.5 Serial Control Signal (SC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.6 Serial Control Signal (SC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.3 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -6
7.3.1 ESSI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.3.2 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.3.3 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7- 7
7.4 Operating Modes: Normal, Network, and On-Demand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.1 Normal/Network/On-Demand Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.2 Synchronous/Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.4.3 Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.4.4 Frame Sync Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 0
7.4.5 Frame Sync Length for Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7. 4 .6 Word Length Fra me Sync and D ata Word Ti min g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 1
7.4.7 Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.4.8 Byte Format (LSB/MSB) for the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.4.9 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -1 2
7.5 ESSI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.5.1 ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
7.5.2 ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
7.5.3 ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.5.4 ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.5.5 ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.5.6 ESSI Transmit Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.5.7 ESSI Transmit Data Registers (TX[2–0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.5.8 ESSI Time Slot Register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.5.10 Receive Slot Mask Registers (RSMA, RSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
7.6 GPIO Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.6.1 Port Control Registers (PCRC and PCRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.6.2 Port Direction Registers (PRRC and PRRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
7. 6 .3 Port D ata Regi s t ers (PDRC an d PDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-34
8Serial Communication Interface (SCI)
8.1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.2 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 2
8.1.3 Multidrop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3.1 Tra nsmitting Data and Address C haracters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.3.2 Wired-OR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
8.1.3.3 Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 3
8.1.3.4 Address Mode Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2.2 Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3 SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.4 SCI Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.4.1 Preamble, Break, and Data Transmission Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode $2 or RA) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
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8.5 Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.6 SCI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
8.6.1 SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 1 0
8.6.2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 1 5
8.6.3 SCI Clock Control Register (SCCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.6.4 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19
8.6.4.1 SCI Receive Register (SRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20
8.6.4.2 SCI Transmit Register (STX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21
8.7 GPIO Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.7.1 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
8.7.2 Port E Direction Register (PRRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
8.7.3 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
9Triple Timer Module
9.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.2 Individual Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -2
9.2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -3
9.2.1 Timer After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.2 Timer Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.3 Timer Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.1 Triple Timer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.1.1 Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.3.1.2 Timer Pulse (Mode 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.1.3 Ti mer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.1.4 Ti mer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.3.2 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
9.3.2.1 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.3.2.2 Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.3.2.3 Measurement Capture (Mode 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.3.3 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16
9.3.4 Watchdog Mo des. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 8
9.3.4.1 Watc hdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9
9.3.4.2 Watc hdog Toggle ( Mode 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.3.4.3 Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20
9.3.5 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.3.6 DMA Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 1
9.4 Triple Timer Module Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.4.1 Prescaler Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21
9.4.2 Timer Prescaler Load Register (TPLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.4.3 Timer Prescaler Count Regis ter (TPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
9. 4 .4 Time r Con t rol/Status Regi s t er ( T CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
9.4.5 Timer Load Register (TLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 8
9.4.6 Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.4.7 Timer Count Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
DSP56303 User’s Manual, Rev. 2
xFreescale Semiconductor
Contents
ABootstrap Program
A.1 Bootstrap Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Equates for I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.3 Host Interface (HI08) Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A.4 Serial Communications Interface (SCI) Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A.5 Enhanced S ynchronous Serial Interface (ESSI) Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.6 Exception Processing Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.7 Timer Module Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A. 8 Direct Mem o ry Access ( D MA) Equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
A.9 Phase Locked Loop (PLL) equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.10 Bus Interface Unit (BIU) Equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
A.11 Interrupt Equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
BPr ogrammin g Refe rence
B.1 Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B- 2
B.2 Interrupt Sources and Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
B.3 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B- 1 0
INDEX
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-1
DSP56303 Overview 1
This manual describes the DSP56303 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56303 is an implementation of the DSP56300
core with a unique configuration of internal memory, cache, and peripherals.
Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM), which
describes the CPU, core programming models, and instruction set. The DSP56303 Technical
Data (DSP56303)—referred to as the data sheet—provides DSP56303 electrical spe cifications,
timing, pinout, and packaging descriptions.
You can obtain these documents—and the Freescale DSP development tools—through a local
Freescale Semiconductor Sales Office or authorized distributor. To receive the latest information
on this DSP, access the Freescale web site at the address listed on the back cover of this manual.
1.1 Manual Organi zati on
This manual contains the following sections and appendices:
Chapter 1, Overview. Features list and block diagram, related documentation,
organization of this manual, and the notational conventions used.
Chapter 2, Signals/Connections. DSP56303 signals and their functional groupings.
Chapter 3, Memory Configuration. DSP56303 memory spaces, RAM configuration,
memory configuration bit settings, memory configurations, and memory maps.
Chapter 4, Core Configuration. Registers for configuring the DSP56300 core when
programming the DSP56303, in particular the interrupt vector locations and the operation
of the interrupt priority registers; operating modes and how they affect the processor’s
program and data memories.
Chapter 5, Programming the Peripherals. Guidelines on initializing the DSP56303
peripherals, including mapping control registers, specifying a method of transferring data,
and configuring for general-purpose input/output (GPIO).
Chapter 6, Host Interface (HI08). Signals, architecture, programming model, reset,
interrupts, external host programming model, initialization, and a quick reference to the
HI08 programming model.
DSP56303 User’s Manual, Rev. 2
1-2 Freescale Semiconductor
DSP56303 O verview
Chapter 7, Enhanced Synchronous Serial Interface (ESSI). Enhancements, data and
control signals, programming model, operating modes, initialization, exceptions, and
GPIO.
Chapter 8, Serial Communication Interface (SCI). Signals, programming model,
operating modes, reset, initialization, and GPIO.
Chapter 9, Triple Timer Module. Architecture, programming model, and operating modes
of three identical timer devices available for use as internals or event counters.
Appendix A, Bootstrap Code . Bootstrap code and equates for the DSP56303.
Appendix B, Programming Reference. Peripheral addresses, interrupt addresses, and
interrupt priorities for the DSP56303; programming sheets listing the contents of the
major DSP56303 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
Bits within registers are always listed from most significant bit (MSB) to least significant
bit (LSB).
Bits within a register are indicated AA[n – m], n > m, when more than one bit is involved
in a description. For purposes of description, the bits are presented as if they are
contiguous within a register. However, this is not always the case. Refer to the
programming model diagrams or to the programming s heets to see t he exact location of
bits within a register.
When a bit is “set, ” its value is 1. When a bit is “cleared,” its value is 0.
The word “assert” means that a high true (active high) signal is pulled high to VCC or that
a low true (active low) signal is pulled low to ground. The word “deassert” means that a
high true signal is pulled low to ground or that a low true signal is pulled high to VCC. See
Table 1-1.
Table 1-1. High True/Low True Signal Conventions
Signal/Symbol Logic Stat e Signal State Voltage
PIN1True Asserted Ground2
PIN False Deasserted VCC3
PIN True Asserted VCC
PIN False Deasserted Ground
Notes: 1. PIN is a gener ic term for any pin on the chip.
2. Ground is an acceptabl e low volt age level. See the appr opriate data sheet for the range of acceptable low
voltage level s (t ypically a TTL logic low).
3. VCC is an acceptable high vo lt age level. See the appropriat e data sheet for the range of acceptable hig h
voltage levels (typ i ca ll y a TT L log i c hig h ).
Manua l Revi sion Histo ry for Revision 2
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-3
Pins or signals that are asserted low (made active when pulled to ground) are indicated like
this:
— In text, they have an overbar: for example, RESET is asserted low.
— In code examples, they have a tilde in front of their names. In Example 1-1, line 3
refers to the SS0 signal (shown as ~SS0).
Sets of signals are indicated by the first and last signals in the set, for instance HAD[0–7].
“Input/Output” indicates a bidirectional signal. “Input or Output” indicates a signal that is
exclusively one or the other.
Code examples are displayed in a monospaced font, as shown in Example 1-1.
Hexadecimal values are indicated with a $ preceding the value, as follows: $FFFFFF is the
X memory address for the core interrupt priority register.
The word “reset” is used in four different contexts in this manual:
— the reset signal, written as RESET
— the reset instruction, written as RESET
— the reset operating state, written as Reset
— the reset function, written as reset
1.3 Manual Revision History for Revisio n 2
Table 1-2 lists the changes made in this manual from Revision 1 to Revision 2.
Example 1-1. Sample Code Listing
BFSET#$0007,X:PCC; Configure: line 1
; MISO0, MOSI0, SCK0 for SPI master line 2
; ~SS0 as PC3 for GPIO line 3
Table 1-2. Change History, Revision 1 to Revision 2
Change Revision 1
Page Number Revision 2
Page Number
Mod ified signal defi niti ons. Changed all fi ve notes in Table 2-1. All in te r na l
keepers are disabled and do not af fect device operation. Page 2-1 Page 2-1
Modified si gnal definitions. Added a note 4, pertaining to GND, at the bottom of
Figure 2-1.Page 2- 2 Page 2-2
Mod if ied signal definitions . Changed the not e at the end of Table 2- 3. Page 2-4 Page 2-4
Modified si gnal definit ions. I n Table 2- 8, changed the Stat e Du ring Reset, Stop,
or Wait descript ions for th e BR and BB signals. Pages 2-7 to
2-8 Pages 2-6 to
2-7
Modified si gnal definit ions. I n Table 2- 11, changed the ti tle of the third colum n to
State During Reset1,2 Added a new note 1 and changed the old note 1 t o note 2.
Changed the State During Re set of all signals to “ Ignored input .” Changed the
signal description for PB14.
Pages 2-11 to
2-14 Pages 2-1 0 to
2-12
DSP56303 User’s Manual, Rev. 2
1-4 Freescale Semiconductor
DSP56303 O verview
1.4 Features
The Freescale DSP56303, a member of the DSP56300 core family of programmable DSPs,
supports wireless infrastructure applications with general filtering operations. Like the other
family members, the DSP56303 uses a high-performance, single-clock-cycle- per-instruction
engine (code compatible with Freescale’s popular DSP56000 core family), a barrel shifter, 24-bit
addressing, instruction cache, and DMA controller. The DSP56303 offers 100 million
instructions per second (MIPS) performance using an internal 100 MHz clock with 3.3 V core
and input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A standard
interface between the DSP56300 core and the internal memory and peripherals supports a wide
variety of memory and peripheral configurations. In particular, the DSP56303 includes a JTAG
port integrated with the Freescale OnCE™ module.
The DSP56303 is intended for use in telecommunication applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general digital
signal processing
Modified si gnal definit ions. I n Table 2- 12, delet ed the Stop column. Changed the
title of the third column to Stat e During Reset1,2 Added a new note 1 and
changed the old note 1 to note 2.
Page 2-15 to
2-16 Page 2-13 to
2-15
Operating M ode Register l ayout and definition. Replaced Figure 4-2. Page 4-15 Page 4-13
Operating M ode Register l ayout and definition. In Table 4-3, changed the
defi niti on for bi t 7. Specifi cally, changed the th ird line in Note 1. Page 4-17 Page 4-16
Bus Control Register ( BCR) layout and definition. Replaced Figure 4-6. Page 4-25 Page 4-23
Bus Control Register ( BCR) layout and definition. In Table 4-8, changed the r ow
con te n ts fo r bi t 22 to “R e se r ve d . Write to 0 fo r fu tu r e c om pa t ib ility.” Page 4-26 Page 4-23
In Section 8.6. 4.1, chan ged the beginning of th e fourth paragr aph from “I n
Synchronous mode” to “In Asynchronous mode.” Page 8-23 Page 8-21
Update d prog ramming sheet s. Repl aced the pr ogra mming sheets for the f ollowing
registers:
•Figure B- 2, Operating Mode Regi ster ( O MR)
•Figure B- 6, Bus Cont rol Register (BCR)
•Figure B- 8, Address Attribute Registers (AAR[3–0])
•Figure B- 22, Ti m er Load, Compare, and Count Regi sters (TLR, TCPR, and
TCR)
Page B-13
Page B-17
Page B-19
Page B-33
Page B-11
Page B-16
Page B-18
Page B-30
Table 1-2. C hange History, Revision 1 to Revision 2 (Continued)
Change Revision 1
Page Number Revision 2
Page Number
DSP56300 Core
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-5
1.5 DSP56300 Core
Core features are fully described in the DSP56300 Family M anual. This manual, in contrast,
documents pinout, memory, and peripheral features. Core features are as follows:
100 million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V
Highly parallel instruction set
Data arithmetic logic unit (Data ALU)
— Fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software contro l
Program control unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— Instruction cache controller
— Internal memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
Direct memory access (DMA)
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circ ular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
Phase lock loop (PLL)
— Allows change of low power Divide Factor (DF) without loss of lock
— Output clock with skew elimination
Hardware debugging support
— On-chip emulation (OnCE) module
— Joint Test Action Group (JTAG) Test Access Port (TAP)
— Address Trace mode reflects internal program RAM accesses at the external port
Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate down to 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent, peripheral-dependent,
and mode-dependent)
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1-6 Freescale Semiconductor
DSP56303 O verview
1.6 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
Data arithmetic logic unit (ALU)
Address generation unit
Program control unit
PLL and clock oscillator
JTAG TAP and OnCE module
Memory
In addition, the DSP56303 provides a set of internal peripherals, discussed in
Section 1.9, Peripherals, on page 1-12.
1.6.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
Fully pipelined 24 × 24-bit parallel multiplier-accumulator
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit
stream generation and parsing)
Conditional ALU instructions
Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
Four 24-bit or 48-bit input general-purpose registers: X1 , X0, Y1, and Y0
Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
Two data bus shifter/limiter circuits
1.6.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or 32-bit
operands. The source operands for the data ALU can be 16, 32, or 40 bits and always originate
from data ALU registers. The results of all data ALU operations are stored in an accumulator.
Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction
can be initiated in every clock cycle, yielding an effective execution rate of one instruction per
clock cycle. The destination of every arithmetic operation can be a source operand for the
immediately following operation without penalty.
1.6.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations o n data operands. For arithmetic instructions, the unit accepts as
DSP56300 Core Functional Blocks
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-7
many as three input operands and outputs one 56-bit result of the following form: extension:most
significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit parallel, fractional multiplies between twos-complement
signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit
contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The
LSP is either truncated or rounded into the MSP. Rounding is pe rformed if specified.
1.6.2 Ad dres s Gen erat io n Unit (AGU)
The AGU performs the effective address calculat ions using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU has
four sets of register triplets, and each register triplet includes an address register, offset register,
and modifier register. Each contains a 24-bit full adder (called an offset adder). A second full
adder (called a modulo adder) adds the summed result of the first full adder to a modulo value
that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is
also provided. The offset adder and the reverse-carry adder work in parallel and share common
inputs. The only difference between them is that the carry propagates in opposite directions. Test
logic determines which of the three summed results of the full adders is output.
Each address ALU can update one address register from its own address re gister file during one
instruction cycle. The contents of the associated modifier register specify the type of arithmetic
used in the address register update calculation. The modifier value is decoded in the address
ALU.
1.6.3 Pro gram Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loop s, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
Program decode controller. Decodes the 24-bit instruction loaded into the instruction
latch and generates all signals for pipeline control.
Program address generator. Contains all the hardware needed for program address
generation, system stack, and loop control.
Program interrupt controller. Arbitrates among all interrupt requests (internal interrupts,
as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and generates the
appropriate interrupt vector address.
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1-8 Freescale Semiconductor
DSP56303 O verview
PCU features include the following:
Position-independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
Instruction cache controller
Internal memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Hardware system stack
The PCU uses the following registers:
Program counter register
Status register
Loop address register
Loop counter register
Vector base address register
Size register
Stack pointer
Operating mode register
Stack counter register
1.6.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator,
which performs low-power division and clock pulse generation. These features allow you to:
Change the low-power divide factor without losing the lock
Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a low-frequency
clock input, a feature that offers two immediate benefits:
A lower-frequency clock input reduces the overall electromagnetic interference generated
by a system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
DSP56300 Core Functional Blocks
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-9
1.6.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems with testing
high-density circuit boards led to the development of this standard under the sponsorship of the
Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard. The test logic includes a TAP with
four dedicated signals, a 16-state controller, and three test data registers. A boundary scan
register links all device signals into a single shift register. The test logic, imple mented utilizing
static logic design, is independent of the device system logic. For details on the JTAG port,
consult the DSP56300 Family Manual.
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that
you can examine registers, memory, or internal peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are provided
through the JTAG TAP signals. For details on the OnCE module, consult the DSP56300 Family
Manual.
1.6.6 Internal Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to work
with the two address ALUs and to feed two operands simultaneously to the data ALU. Memory
space includes internal RAM and ROM and can be expanded off-chip under software control. For
details on internal memory, see Chapter 3, Memory Configuration. Program R AM, instruction
cache, X data RAM, and Y data RAM size are programmable, as shown in Table 1-2.
There is an internal 192 × 24-bit bootstrap ROM.
1.6.7 External Memory Expansion
Memory can be expanded externlly as follows:
Data memory expansion to two 256 K × 24-bit word memory spaces using the standard
external address lines
Table 1-3. Internal Memory
Instruction
Cache Switch
Mode Program RAM
Size Instruction
Cache Siz e X Data RAM Size Y Data RAM Size
disabled disabled 4096 × 24-bit 0 20 48 × 24-bit 2048 × 24- bit
enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24- bit 2048 × 24-bit
disabled enabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit
enabled enabled 1024 × 24- bit 1024 × 24-bi t 3072 × 24- bit 3072 × 24-bit
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1-10 Freescale Semiconductor
DSP56303 O verview
Program memory expansion to one 256 K × 24-bit words memory space usin g the
standard external address lines
Further features of external memory include the following :
External memory expansion port
Simultaneous glueless interface to static random access memory (SR AM) and dynamic
random access memory (DRAM)
1.7 Internal Buses
To provide data exchange between the blocks, the DSP56303 implements the following buses:
Peripheral I/O expansion bus to peripherals
Program memory expansion bus to program ROM
X memory expansion bus to X memory
Y memory expansion bus to Y memory
Global data bus between PCU and other core structures
Program data bus for carrying program data throughout the core
X memory data bus for carrying X data throughout the core
Y memory data bus for carrying Y data throughout the core
Program address bus for carrying program memory addresses throughout the core
X memory address bus for carrying X memory addresses throughout the core
Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components. All internal
buses on the DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit
bus.
DMA
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 1-11
Note: See Section 1.6.6, Internal Memory, on page 1-9 for memory size details.
1.8 DMA
The DMA block has the following features:
Six DMA channels supporting internal and external accesses
One-, two-, and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
Figure 1-1. DSP56303 Block Dia gram
PLL OnCE
Clock
Generator
Internal
Data
Bus
Switch
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
External
Data Bus
Switch
13
MODD/IRQD
DSP56300
616
24-Bit
24
18
DDB
DAB
Peri pheral
Core
YM_EB
XM_EB
PM_EB
PIO_EB
Expansion Area
6
SCI
Interface
JTAG 5
3
RESET
MODA/IRQA
PINIT/NMI
2
Bootstrap
ROM
EXTAL
XTAL
Address
Control
Data
Triple
Timer Host
Interface
HI08
ESSI
Interface
Address
Generation
Unit
Six-Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I-Cache
Control
External
Address
Bus
Switch
Memory
Expansion
Area
DE
Program RAM
4096 × 24 bits
(default)
X Data
RAM
2048 × 24
bits
(default)
Y Data
RAM
2048 × 24
bits
(default)
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1-12 Freescale Semiconductor
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1.9 Peripherals
In addition to the core features, the DSP56303 provides the following peripherals:
As many as 34 user-configurable GPIO signals
HI08 to external hosts
Dual ESSI
SCI
Triple timer module
Memory switch mode
Four external interrupt/mode control lines
1.9.1 GPIO Functionality
The GPIO port consists of up to 34 programmable signals, also used by the peripherals (HI08,
ESSI, SCI, and timer). There are no dedicated GPIO signals. After a reset, the signals are
automatically configured as GPIO. Three memory-mapped registers per peripheral control GPIO
functionality. Programming techniques for these registers to control GPIO functionality are
detailed in Chapter 5, Programming the Peripherals.
1.9.2 HI08
The HI08 is a byte-wide, full-duplex, double-buffered parallel port that can connect directly to
the data bus of a host processor. The HI08 supports a variety of buses and provides connection
with a number of industry-standard DSPs, microcomputers, and mi croprocessors without
requiring any additional logic. The DSP core treats the HI08 as a memory-mapped peripheral
occupying eight 24-bit words in data memory space. The DSP can use the HI08 as a
memory-mapped peripheral, using either standard polled or interrupt programming techniques.
Separate double-buffered transmit and receive data registers allow the DSP and host processor to
transfer data efficiently at high speed. Memory mapping allows you to program DSP core
communication with the HI08 registers using standard instructions and addressi ng modes.
1.9.3 ESSI
The DSP56303 provides two independent and identical ESSIs. Each ESSI has a full-duplex serial
port for communication with a variety of serial devi ces, including one or more industry-standard
codecs, other DSPs, microprocessors, and peripherals that implement the Freescale SPI. The
ESSI consists of independent transmitter and receiver sections and a common ESSI clock
generator. ESSI capabilities include the following:
Independent (asynchronous) or shared (synchronous) transmit and receive sections with
separate or shared internal/external clocks and frame syncs
Normal mode operation using frame sync
Peripherals
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Freescale Semiconductor 1-13
Network mode operation with as many as 32 time slots
Programmable word length (8, 12, or 16 bits)
Program options for frame synchronization and clock generation
One receiver and three transmitters per ESSI
1.9.4 SCI
The SCI provides a full-duplex port for serial communication with other DSPs, microprocessors,
or peripherals such as modems. The SCI interfaces without additional logic to peripherals that
use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral
interfaces that have non-TTL level signals, such as the RS-232C, RS-422, etc. This interface uses
three dedicated signals: transmit data, receive data, and SCI serial clock. It supports
industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data
transmission (up to 12.5 Mbps for a 100 MHz clock). SCI asynchronous protocols include a
multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bi t
capability. This mode allows the DSP56303 to share a single serial line efficiently with other
peripherals.
Separate SCI transmit and receive sections can operate asynchronously with respect to each
other. A programmable baud-rate generator provides the transmit and receive clocks. An enable
vector and an interrupt vector allow the baud-rate generator to function as a general-purpose
timer when the SCI is not using it or when the interrup t timing is the same as that used by the
SCI.
1.9.5 Timer Module
The triple timer module is composed of a common 21-bit prescaler and three independent and
identical general-purpose 24-bit timer/event counters, each with its own memory-mapped
register set. Each timer has the following properties:
A single signal that can function as a GPIO signal or as a timer signal
Uses internal or external clocking and can interrupt the DSP after a specified number of
events (clocks) or signal an external device after counting internal events
Connection to the external world through one bidirectional signal. When this signal is
configured as an input, the timer functions as an external event counter or measures
external pulse width/signal period. When the signal is used as an output, the timer
functions as either a timer, a watchdog, or a pulse width modulator.
DSP56303 User’s Manual, Rev. 2
1-14 Freescale Semiconductor
DSP56303 O verview
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-1
Signals/Connections 2
The DSP56303 input and output signals are organized into functional groups, as shown in Table
2-1 and illustrated in Figure 2-1. The DSP56303 operates from a 3 V supply; however, some of
the inputs can tolerate 5 V. A special notice f or this feature is added to the signal descriptions of
those inputs.
Ta ble 2-1. DSP56303 Functional Signal Groupings
Functional Group Number of Signal s Description and Page
Power (VCC)18Table 2-2 on page -3
Ground (GND) 19 Table 2-3 on page -3
Clock 2Table 2-4 on page -4
PLL 3Table 2-5 on page -5
Addr e ss bu s Port A118 Table 2-6 on page -5
Data bus 24 Table 2-7 on page -6
Bus control 13 Table 2-8 on page -6
Interrupt and mode control 5 Table 2-9 on page -8
HI08 Po rt B2 16 Table 2-11 on page -10
ESSI Ports C and D312 Table 2-12 on page -13
Table 2-13 on page -15
SCI Port E43Table 2-14 on page - 17
Timer53Table 2-15 on page -17
OnCE/JTAG Port 6 Table 2-16 on page -18
Notes: 1. Port A si gnals define the external memory int erface port, incl uding the external addr ess bus, data bus, and
control signals.
2. Port B si gnals are the HI08 port signals mult iplexed with the GPIO signa ls.
3. Port C and D signals are th e two ESSI por t si gnals multiplexed with the GPIO si gnals.
4. Port E si gnals are the SCI port si gnals multiplexed with the GPIO signals.
5. The numb er of Ground signals listed are fo r the 144-pi n TQ FP package. For th e 196-ball M AP-BGA package,
there are 66 GND connections.
DSP56303 User’s Manual, Rev. 2
2-2 Freescale Semiconductor
Signals/Connections
Figure 2-1. Signals Identified by Functional Group
DSP56303
24
18 External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)2
Timers3
PLL
JTAG/OnCE
Port
Power Inputs:
PLL
Internal Logi c
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA0/RAS0–
AA3/RAS3
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK
TCK
TDI
TDO
TMS
TRST
DE
CLKOUT
PCAP
PINIT/NMI
VCCP
VCCQ
VCCA
VCCD
VCCC
VCCH
VCCS
4
Serial
Communications
Interface (SCI) Port2
4
2
2
Grounds4:
PLL
PLL
Internal Logi c
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
GNDP
GNDP1
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
4
4
4
2
Interrupt/
Mode
Control
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Host
Interface
(HI08) Port1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
4
2
EXTAL
XTAL Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
D oub le DS
HRD/HRD
HWR/HWR
D oub le HR
HTRQ/HTRQ
HRRQ/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
Not e: 1. The H I08 port supports a non-multiplexed or a multiplexed b us, sing le or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each mode is configured independently, any combination of these
modes i s possible. These HI08 signals can a lso be con figured as GPIO signal s (PB[0–15]). Signals with dual
designations (for example, HAS/HA S) have configurable p olarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respecti vely.
3. TIO[0–2] can be con figured as GPIO signals.
4. The G ND signals are listed for the 144-pin TQFP pack age. For the 196-ball MAP-BGA package, all grounds except
GNDP an d GNDP1 are connect ed toeg ether and refer enced as GND. There ar e 64 GND connections.
Power
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-3
2.1 Power
2.2 Ground
Tabl e 2-2. Power Inputs
Power Name Description
VCCP PLL Power
VCC dedicated for use with Phase Lock Loop (PLL). The voltage should be wel l-regula ted and the i nput
should be provided wit h an extremely low impedance path to the VCC power rail.
VCCQ (4) Quiet Power
An isol ated power for the internal processing lo gic. This input must be ti ed externally to all other chi p
power inputs, exc ept for VCCP. The user must provide adequate external decoupl ing capacitors .
VCCA (4 ) Address Bus Power
An isol ated powe r for s ection s of the addre ss bus I/ O drive rs. Thi s input must be tied e xterna lly t o all other
chip power inputs , except f or VCCP. The user must provi de adequate external decouplin g capacitors.
VCCD (4) Data Bus Power
An isol ated power for sections of the dat a bus I/O dri vers. This input must be tied externall y to al l ot her
chip power inputs , except f or VCCP. The user must provide adequate external decouplin g capacitors.
VCCC (2) Bus Control Power
An isol ated power for the bus control I/O drivers. Thi s input must be tied ext ernally to all other chip power
inputs, except for VCCP. The user must provide adequat e external decoupling capacitors.
VCCH Host Power
An isol ated power for th e HI08 I/ O drivers. Th is inpu t must be ti ed exte rnall y to all ot her c hip power inputs,
except for VCCP. The user must provide adequate external decoupling capacitors.
VCCS (2 ) ESSI, SCI, and Timer Power
An isol ated power f or th e ESSI, SCI, and timer I/ O dri vers. Thi s input must be tied externally to all other
chip power inputs , except f or VCCP. The user must provi de adequate external decouplin g capacitors.
Note: These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other
inter nally. On thos e packages, all power input except VCCP are la beled VCC. The numbers of connections ind icated
in this tabl e are minimum values ; th e total VCC connecti ons are package-dependent.
Tabl e 2-3. Grounds
Ground Name Description
GNDPPLL Ground
Ground ded icated for PLL use. The connecti on should be provided with an extremely low-im pedance
path to ground. VCCP shoul d be bypassed to GN DP by a 0.47 µF capa citor l ocated as close as possible
to t he chi p package.
GNDP1 PLL Ground 1
Ground ded icated for PLL use. The connecti on should be provided with an extremely low-im pedance
path to ground.
GNDQ (4) Quiet Ground
An isol ated ground for the internal pr ocessing l ogic. This connection must be tied externally to all other
chip ground connections, except GNDP and GNDP1. The user must provide adequate external
de coupli ng capacitors.
DSP56303 User’s Manual, Rev. 2
2-4 Freescale Semiconductor
Signals/Connections
2.3 Clock
GNDA (4) Address Bus Ground
An is olated gro und for secti ons o f the a ddress bu s I /O dri vers. T his conn ect ion m ust be t ied ext ernal ly to
all other chip gr ound c onnecti ons, except GNDP and GNDP1. The user must provide adequate exter nal
de coupli ng capacitors.
GNDD (4 ) Data Bus Ground
An isol ated groun d for sections of the data bus I/O drivers . This connec tion must be tied ext ernall y to all
other chip ground connecti ons, except GNDP and GNDP1. The user must provide adequate external
de coupli ng capacitors.
GNDC (2 ) Bus Control Ground
An isol ated ground for the bus cont rol I/O driver s. Thi s connection must be tied externally to al l ot her
chip ground connections, except GNDP and GNDP1. The user must provide adequate external
de coupli ng capacitors.
GNDHHost Ground
An isol ated ground for the HI08 I/O dri vers. This con nection must be tied externall y to al l ot her chip
ground connections, except GNDP and GNDP1. The user must provide adequate exte rnal decoupling
capaci tors.
GNDS (2) ESSI, SCI, and Timer Ground
An is olated grou nd for the ESSI , SCI, and ti mer I/O dr iver s. This conn ection must be ti ed externa lly to al l
other chip ground connecti ons, except GNDP and GNDP1. The user must provide adequate external
de coupli ng capacitors.
Note: The subsystem GND signals (GNDQ, GN DA, GND D, GNDC, GNDH, and GNDS) are listed for the 144-pin TQFP
package. Fo r the 196-ball MAP-BGA packa ge, all groun ds ex cept G NDP and GND P1 are connecte d toget her inside
the package and referenced as GND .
Table 2-4. Clock Sign als
Signal
Name Type State During
Reset Signal Descr ipt ion
EXTAL Input Input External Clock/Cryst al Input
Inter faces the inter nal crystal oscillator inp ut to an external crystal or an
external cl ock.
XTAL Output Chip-driven Crystal Ou tput
Connects the i nternal crystal osc il lator out put to an external cr ystal. I f an
external clock i s used, leave XTAL unconnected.
Table 2-3. Grounds (Continued)
Ground Name Description
Phase Lock Loop (PLL)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-5
2.4 Phase Lock Loop (PLL)
2.5 External Memory Expansion Port (Port A)
Note: When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases bus
mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],
AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
2.5.1 External Address B u s
Table 2-5. Phase Lock Loop Signals
Signal Name Type State During
Reset Signal Descripti on
PCAP Input Input PLL Capacitor
Connects an off-chip capacitor to the PLL f ilter. See the DSP56303
Technical Data sheet to determine the correct PLL cap acitor value.
Connect one capacitor terminal t o PCAP and the other termina l t o VCCP.
If the PLL is not used, PCAP can be tied to VCC, GND, or left float ing.
CLKOUT Output Chip-driven Clock Output
Provides an output clock synchronized to the internal core cloc k phase.
If th e PLL is enabled and both the multi pli cation and division factors
equal one, th en CLKO UT is also synchronized to EXTAL.
If th e PLL is disabled, the CLKOUT frequ ency is half the frequency of
EXTAL.
PINIT/NMI Input Input PLL Initial/Non-Maskable I nterr upt
Durin g asser tion of RESET, the value of PINIT/NMI is written into the PLL
Enable (PEN) bit of the PLL control register, deter m ining whether the
PLL is enabl ed or disabled. After RESET deassertion and during normal
instruction processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered Non-Ma skable Int errupt ( N M I) request int ernally
synchronized to CLKOUT.
PINIT/NMI can tolerate 5 V.
Table 2-6. External Address Bus Signals
Signal
Name Type State During Reset ,
Stop, or Wait S ignal Description
A[0–17] Output Tri-stated Address Bus
When the DSP is the bus master, A[0–17] specify t he address for
externa l progr am and dat a mem ory acc esse s. Otherwi se, th e signal s
are tri-stated. To minimize power dissipation, A[0–17] do not change
state when ext ernal mem ory spaces are not bei ng accessed.
DSP56303 User’s Manual, Rev. 2
2-6 Freescale Semiconductor
Signals/Connections
2.5.2 External Data Bus
2.5.3 External Bus Control
Table 2-7. External Data Bus Signals
Signal
Name Type State During Reset,
Stop, or Wait Signal Descripti on
D[0–23] Input/Output Tri-stated Data Bus
When the DSP is the bus mast er, D[0– 23] provi de the bidirect ional
data bus for external program and data memory acc e sses. Otherwise,
D[0–23] are t ri-stated.
Table 2-8. External Bus Control Signals
Signal
Name Type State During Reset,
Stop, or Wait S ignal Description
AA0/RAS0–
AA3/RAS3 Output Tri-stated Address Att ribute or Row Address Strobe
As AA, these signals functi on as chip selects or additional address li nes.
Unli ke address lines, however, th e AA lin es do not hold t heir st ate afte r a
read or wr it e operati on. As RAS, these signal s can be used for Dynamic
Random Access M em ory (DRAM) i nter face. These signals hav e
programmable polarity.
RD Output Tri-stated Read Enable
When the DSP is t he bus master , RD is asser ted to r ead exter nal memo ry
on the data bus (D[0–23]). Otherwise, RD is tri- stated.
WR Output Tri-stated Write Enable
When the DSP is the bus master , WR is assert ed to write external
memor y on the data bus (D[0–23]). Oth erwise, WR is tri-stated.
TA Input Ignored Input Transfer Acknowledge
If the DSP56303 is the bus m aster and there i s no external bus activity, or
the DSP563 03 i s not t he bus m aster, t he TA input i s ignor ed. The TA input
is a Data Transfer Acknowledge ( DT ACK) function that can extend an
external bus cycle indefinit ely. Any number of wai t stat es (1, 2,..., inf inity)
can be added to the wait states insert ed by the BCR by keeping TA
deasserted. In typical operatio n, TA is deassert ed at the start of a bus
cycle, asserted t o enable comp letion of the bus cycle, and dea sserted
before the next bus cycle. The current bus cycle completes one clock
period after TA is asserted synchronous t o CLKOUT. The num ber of wait
stat es is d ete rmined by th e TA input or by the Bus Contr ol Regi ster ( BCR),
whichever is longer. The BCR can set t he minimum number of wait states
in external bus cycles.
To use the TA function ali ty, the BCR must be programm ed to at least one
wait state. A zero wai t state access cannot be extended by TA
deassertion; otherwise improper operatio n may resul t. TA can operate
synchr onou sly or asy nchronou sly , dependi ng on the set ting of the TAS bit
in t he Operating Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses; otherwise
improper oper ation may result.
Interrupt and Mode Control
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-7
2. 6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
BR Output Output
(deasserted)
State duri ng Stop/Wai t
depends on the BRH
bit setting:
• BRH = 0: Output,
deasserted.
• BRH = 1: Maintains
last st ate (th at is, if
asserted, remains
asserted)
Bus Request
Asserted when the DSP reques ts bus mastership and deasserted when
the DSP no longer needs the bus. BR can be asserted or deasser ted
independently of whether the DSP56303 is a bus mast er or a bus slave.
Bus “parking” allows BR to be deasserted even though the DSP56303 is
the bus master (see the description of bus “parking” in the BB signal
descr ipti on). The Bus Reque st Hold (BRH) bit i n the BCR allows BR to be
asserted under soft ware control, even though the DSP does not need the
bus. BR is typically sent to an ext ernal bus arbitrator that contr ols the
priority, parking and tenure of each mast er on the same external bus. BR
is affected only by DSP request s for the external bus, never for the
int ernal bus. During hardwar e reset, BR is deassert ed and the arbi trat ion
is res et to the bus slave stat e.
BG Input Ignored Input Bus Grant
Must be asserted/deasserted synchronous to CLKOUT for proper
operation. An external bus arbitration circuit asserts BG when the
DSP56303 becom es the next bus master. When BG is asserted, t he
DSP56303 m ust wait unt il BB i s deasser ted before t aking bu s mast ership .
When BG is deasserted, bus mastership is typi cally giv en up at the end of
the current bus cycle. Thi s may o ccur in t he middle of an inst ructi on that
requires more than one external bus cycle for execution.
BB Input/
Output Ignored Input Bus Busy
Indicates that the bus is acti ve and must be asserted and deassert ed
synchronous to CLKOUT. Only after BB is deasserted can t he pending
bus master become the bus master (and then assert the si gnal again).
The bus master can keep BB asserted after ceasing bus acti vity,
regardless of whether BR i s asserted or deasserted. Thi s is called “bus
parking” and allows the current bus master to reuse the bus with out
re-arbitration unt il another devi ce requires the bus. BB is deasserted by
an “active pull-up” method (that is, BB is driven high and then rel eased
and held high by an external pull-up resi stor).
BB requires an exter nal pull -up resistor.
CAS Output Tri-stated Column Address Strobe
When the DSP is the bus master , DRAM uses CAS to s tr o be th e co lu m n
address . Otherwise, if t he Bus Mastership Enable ( BME) bit in the DRAM
Control Register is cl eared, t he signal i s tri-stated.
BCLK Output Tri-stated Bus Clock
When the DSP is the bus master, BCLK is active when the OM R[ATE] is
set. When BCLK is active and synchronized to CLKOUT by the int ernal
PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
BCLK Output Tri-stated Bus Clock Not
When the DSP is the bus mast er, BCLK is the inv erse of the BCLK signal .
Otherwi se, the signal is tri-stated.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name Type State During Reset,
Stop, or Wait S ignal Description
DSP56303 User’s Manual, Rev. 2
2-8 Freescale Semiconductor
Signals/Connections
Ta ble 2-9. Interrupt and Mode C ontrol
Signal Name Type State During
Reset Signal Descr ipt ion
RESET Input Input Reset
Deassert ion of RESET is internall y synchronized t o the clock out
(CLKOUT). When ass ert ed, the chi p is plac ed in the Reset stat e and the
inter nal phase generator i s reset. The Schmit t- trigger i nput all ows a slowly
rising input (such as a capacitor charging) to reset the chip reliably. If
RESET is deasserted synchronous to CLKOUT, exact star t-up timing is
guaranteed, allowing multipl e processors to start and operat e
synchronously. When the RESET signal is deasserted, th e ini tial chip
operating mode is latched from the MO DA, MODB, MODC, and MODD
input s. The RESET signal must be asserted af ter power-up.
RESET can tolerate 5 V.
MODA/IRQA Input Input Mode Select A/External Interrupt Request A
Selects the ini tial chip operati ng m ode during hardware reset and becomes
a level -sensitive or negative-edge-t riggered, maskable int errupt request
input duri ng norma l i nstruction processing. MODA/IRQA MODA, MODB,
MODC, and MODD select one of si xteen initial chip operat ing modes,
latched int o th e OMR when the RESET signal is deasserted.
Inter nally synch ronized to CLKOUT. I f IRQA is asserted synchronous to
CLKOUT, multi ple processors can be re-s ynchronized usi ng the W AIT
instr uction and assert ing IRQA to exit the Wait st ate. If a STOP instruction
puts t he processor is in the Stop st andby state and IRQA is asserted, the
processor exi ts the St op state.
MODA/IRQA can tolerate 5 V.
MODB/IRQB Input Input Mode Select B/External Interrupt Request B
Selects the ini tial chip operati ng m ode during hardware reset and becomes
a level -sensitive or negative-edge-t riggered, maskable int errupt request
input during normal i nstruction processing. MODA, MODB, MODC, and
MODD sel ect one of sixteen i nitial chip operatin g m odes, l atched into O MR
when the RESET signal is deasser ted.
Inter nally synch ronized to CLKOUT. I f IRQB is asserted synchronous to
CLKOUT, multi ple processors can be re-s ynchronized usi ng the W AIT
instr uction and assert ing IRQB to exit the Wait st ate.
MODB/IRQB can tolerate 5 V.
MODC/IRQC Input Input Mode Select C/Exter nal Inte rru pt Request C
Selects the ini tial chip operati ng m ode during hardware reset and becomes
a level -sensitive or negative-edge-t riggered, maskable int errupt request
input during normal i nstruction processing. MODA, MODB, MODC, and
MODD sel ect one of sixteen i nitial chip operatin g m odes, l atched into O MR
when the RESET signal is deasser ted.
Inter nally synch ronized to CLKOUT. I f IRQC i s asserted synchronous to
CLKOUT, multi ple processors can be re-s ynchronized usi ng the W AIT
instr uction and assert ing IRQC to exit the W ait state.
MODC/IRQC can tolerate 5 V.
Host Inte rface (HI08)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-9
2.7 Host Interface (HI08)
The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus. The
HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1 Host Port Usag e Considerations
Careful synchronization is required when the system reads multiple-b it registers that are written
by another asynchronous system. This is a common problem when two asynchronous systems are
connected (as they are in the Host port). The considerations for proper operation are discussed in
Table 2-10.
2.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as
determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the Chapter 6,
Host Interface (HI08), for detailed descriptions of HI08 configuration registers.
MODD/IRQD Input Input Mode Select D/Exter nal Inte rru pt Request D
Selects the ini tial chip operati ng m ode during hardware reset and becomes
a level -sensitive or negative-edge-t riggered, maskable int errupt request
input during normal i nstruction processing. MODA, MODB, MODC, and
MODD sel ect one of sixteen i nitial chip operatin g m odes, l atched into O MR
when the RESET signal is deasser ted.
Inter nally synch ronized to CLKOUT. I f IRQD i s asserted synchronous to
CLKOUT, multi ple processors can be re-s ynchronized usi ng the W AIT
instr uction and assert ing IRQD to exit the W ait state.
MODD/IRQD can tolerate 5 V.
Tabl e 2-10. Host Port Usage Considerations
Action Description
Asynchr onous read of receive
byte registers To assure that the data in the receive byte regi sters is valid when you are readi ng the r
Receive regi ster Hi gh (RXH), Recei ve register Middle (RXM) , or Receive r egister Low ( RXL),
use interrupts or poll the Receive Register D ata Full (RXDF) flag that indicat es dat a is
available.
Asynchronous write t o
transmit byte registers To ensure that the tr ansmit byte r egisters t ransfer valid data to the Host Recei ve (HRX)
register, do not write to th e Transmit regist er Hi gh (TXH), Transmi t registe r Middle (TXM), or
Transmit r egister Low (TXL) regis ters unless t he Transmit register Data Empty (TXDE) bit i s
set i ndicating that the transm it byte registers are empty.
Asynchronous write t o host
vector To ens ure that the DSP int errupt control l ogic receives a stable vec tor, change the Host
Vector (HV) register only when the Host Comm and bit (HC) is clear.
Table 2-9. Interrupt and Mode Control (Continued)
Signal Name Type State During
Reset Signal Descr ipt ion
DSP56303 User’s Manual, Rev. 2
2-10 Freescale Semiconductor
Signals/Connections
Table 2-11. Host Interface
Signal Name Type State During
Reset1,2 Signal Description
H[0–7]
HAD[0–7]
PB[0–7]
Input/Output
Input/Output
Input or
Output
Ignored input Host Data
When the HI08 is programme d to in terface with a non-multip lexed host
bus and the HI funct ion i s select ed, t hese s ignals are li nes 0–7 of the Data
bus.
Host Address
When the HI08 is programme d to interface wit h a multiplex ed host bus
and the HI function is selected, these signals are l ines 0–7 of the
Address/Data bus.
Port B 0–7
When the HI08 is con fi gured as GPIO through the HPCR, these signals
are individually programm ed through the HI08 Data Direction Register
(HDDR). This input is 5 V tolerant.
HA0
HAS/HAS
PB8
Input
Input
Input or
Output
Ignored input Host Address Input 0
When the HI08 is programme d to in terface with a non-multip lexed host
bus and the HI fun cti on is selected, this signal is line 0 of t he Host
Address bus.
Host Address Strobe
When the HI08 is programme d to interface wit h a multiplex ed host bus
and the HI function is selected, this signal is the Host Address Strobe
(HAS) Schmitt-tr igger input. The polarity of the addr ess st robe is
programmable, but is configured active-low (HAS) follo wing re s e t.
Port B 8
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
HA1
HA8
PB9
Input
Input
Input or
Output
Ignored input Host Address Input 1
When the HI08 is programme d to in terface with a non-multip lexed host
bus and the HI fun cti on is selected, this signal is line 1 of t he Host
Address bus.
Host Address 8
When the HI08 is programme d to interface wit h a multiplex ed host bus
and the HI function is selected, this signal is line 8 of the Host Addr ess
bus.
Port B 9
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
Host Inte rface (HI08)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-11
HA2
HA9
PB10
Input
Input
Input or
Output
Ignored input Host Address Input 2
When the HI08 is programme d to in terface with a non-multip lexed host
bus and the HI fun cti on is selected, this signal is line 2 of t he Host
Address bus.
Host Address 9
When the HI08 is programme d to interface wit h a multiplex ed host bus
and the HI function is selected, this signal is line 9 of the Host Addr ess
bus.
Port B 10
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
HRW
HRD/HRD
PB11
Input
Input
Input or
Output
Ignored input Host Read/Write
When the HI08 is programmed to interface with a single-dat a-strobe host
bus and the HI fun cti on is selected, this signal is the Ho st Read/W ri te
input.
Host Read Data
When the HI08 is programm ed to interf ace with a double- dat a-strobe host
bus and the HI fun cti on is select ed, thi s signal is the Ho st Read Data
strobe (HRD) Schmitt-t ri gger input. The polarit y of the dat a str obe is
programmable, but is configured as active-low (HRD) af te r reset.
Port B 11
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
HDS/HDS
HWR/HWR
PB12
Input
Input
Input or
Output
Ignored input Host Data Stro be
When the HI08 is programmed to interface with a single-dat a-strobe host
bus and the HI fun cti on is select ed, thi s signal is the Host Data Str obe
(HDS) Schmitt-trigger input. The polarity of the data strobe is
programmable, but is configured as active-low (HDS) followi ng reset.
Host Write Data
When the HI08 is programm ed to interf ace with a double- dat a-strobe host
bus and the HI fun cti on is selected, this signal is the Ho st Write Data
Strobe (HWR) Schmitt-trigger input. The pol arity of the data strobe is
programmable, but is configured as active-low (HWR) follo wing re s et.
Port B 12
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
Table 2-11. Host Inter face (Continue d)
Signal Name Type State During
Reset1,2 Signal Description
DSP56303 User’s Manual, Rev. 2
2-12 Freescale Semiconductor
Signals/Connections
HCS
HA10
PB13
Input
Input
Input or
Output
Ignored input Host Chip Selec t
When the HI08 is programme d to in terface with a non-multip lexed host
bus and the HI fun cti on is selected, this signal is the Ho st Chip Select
(HCS) input. The polarity of the chip select is programmable, but is
configured active-low (HCS) after reset.
Host Address 10
When the HI08 is programme d to interface wit h a multiplex ed host bus
and the HI function is selected, this signal is line 10 of the Host Address
bus.
Port B 13
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
HREQ/HREQ
HTRQ/HTRQ
PB14
Output
Output
Input or
Output
Ignored input Host Reque st
When the HI08 is programme d to interface with a single host request host
bus and the HI fun cti on is selected, this signal is the Ho st Request
(HREQ) output . The polarity of the host req uest is pr ogramma ble, but is
confi gured as acti ve-low (HREQ) fol lowi ng r ese t. The host request can be
programmed as a driven or open-drain output.
Transmit Host Request
When the HI08 is programmed to interface with a double host r equest
host bus and the HI function is selected, this signal is the Transmit Host
Request ( HTRQ) out put. The polarity of the host request is
programmable, but is configured as active-low (HTRQ) following reset.
The host request may be programmed as a driven or open-drai n output.
Port B 14
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
HACK/HACK
HRRQ/HRRQ
PB15
Input
Output
Input or
Output
Ignored input Host Ackno wledge
When the HI08 is programme d to interface with a single host request host
bus and the HI fun cti on is selected, this signal is the Ho st Acknowledge
(HACK) Schmitt-trigger input. The polarity of the host acknowledge is
programmable, but is configured as active-low (HACK) after reset.
Receive Host Request
When the HI08 is programmed to interface with a double host r equest
host bus and the HI function is selected, this signal is the Receive Host
Request (HRRQ) output. The polarity of the host re quest is
programmable, but is configured as active-low (HRRQ ) after reset. The
host request may be programmed as a driven or open-drain outp ut.
Port B 15
When the HI08 is con fi gured as GPIO through the HPCR, this signal is
indiv idually programmed through t he HDDR. Thi s input is 5 V tol erant.
Notes: 1. In the Sto p stat e, the si gnal ma int ains the last state as follow s:
• If the last state is input, the signal is an ignor ed input.
• If the last state is output, these li nes are tr i-stated
2. The Wait processing state does not affect the signal state.
Table 2-11. Host Inter face (Continue d)
Signal Name Type State During
Reset1,2 Signal Description
Enhanced Synchronous Serial Interface 0 (ESSI0)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-13
2.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial
communication with a variety of serial devices, including one or more industry-standard
CODECs, other DSPs, microprocessors, and peripherals that implement the Freescale serial
peripheral interface (SPI).
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal
Name Type State Duri ng
Reset1, 2 Signal Description
SC00
PC0
Input or Output Ignored input Serial Control 0
Functi ons in eit her Synchronous or Asynchronous mode. For Asynchronous
mode, this signal is t he receive clock I/O (Schmitt- trigger input). For
Synchronous mode, this signal is either for Transmi tter 1 output or Serial I/ O
Flag 0.
Port C 0
The default configuration following reset is GPIO. For PC0, signal dir ection is
controlled thro ugh the Port C Direction Re gister (PRRC).
This signal is confi gured as SC00 or PC0 through the Port C Contr ol Register
(PCRC). This i nput is 5 V tolerant.
SC01
PC1
Input/Output
Input or Output
Ignored input Serial Control 1
Functi ons in eit her Synchronous or Asynchronous mode. For Asynchronous
mode, this signal is t he receiver frame sync I/O. For Syn chronous mode, this
signal is either Transmitter 2 output or Serial I/O Flag 1.
Port C 1
The default configuration following reset is GPIO. For PC1, signal dir ection is
controlled thr ough PRRC.
This si gnal is configured as SC01 or PC1 throug h PCRC. This input is 5 V
tolerant.
SC02
PC2
Input/Output
Input or Output
Ignored input Serial Contr ol Sig nal 2
The frame sync for bot h the transmitter and recei ver in Synchronous mode,
and for th e transmitt er only i n Asynchronous mode. When co nfi gured as an
output, this signal is the internally generated frame sync signal. When
configured as an input, this signal rec eives an external frame sync signal for
the transmitter (and t he receiver in synchronous operation).
Port C 2
The default configuration following reset is GPIO. For PC2, signal dir ection is
controlled thro ugh PRRC. Thi s signal is con fi gured as SC02 or PC2 through
PCRC. This input is 5 V toleran t.
DSP56303 User’s Manual, Rev. 2
2-14 Freescale Semiconductor
Signals/Connections
SCK0
PC3
Input/Output
Input or Output
Ignored input Serial Clock
Provi des the serial bit rate clock for the ESSI interface for both the trans mitter
and receiver in Sync hronous modes, or the transm itt er only in Asynchronous
modes.
Although an external seri al clock can be independent of and asynchronous to
the DSP system clock, i t must exceed the minimum clock cycle tim e of 6 T
(that is, the system clock frequency mu st be at l east three t imes the external
ESSI cloc k frequency). The ESSI needs at l east thr ee DSP phases inside
each half of t he serial clock.
Port C 3
The default configuration following reset is GPIO. For PC3, signal dir ection is
controlled thro ugh PRRC. Thi s signal is con fi gured as SCK0 or PC3 through
PCRC. This input is 5 V toleran t.
SRD0
PC4
Input
Input or Output
Ignored input Serial Receive Data
Receives serial data and transf ers the data to the ESSI receive shi ft regi ster.
SRD0 is an input when data is being received.
Port C 4
The default configuration following reset is GPIO. For PC4, signal dir ection is
controlled thro ugh PRRC. Thi s signal is con fi gured as SRD0 or PC4 through
PCRC. This input is 5 V toleran t.
STD0
PC5
Output
Input or Output
Ignored input Serial Transmit Data
Transmits data from th e serial tr ansmit shif t regi ster. STD0 is an output when
data i s being transmitted.
Port C 5
The default configuration following reset is GPIO. For PC5, signal dir ection is
controlled thro ugh PRRC. Thi s signal is con fi gured as STD0 or PC5 through
PCRC. This input is 5 V toleran t.
Notes: 1. In the Stop state, the signal maint ains the last state as follows:
• If th e last state is input, the signal i s an ignored input .
• If th e last state is output, these li nes are tr i-st ated.
2. The Wai t pro cessing stat e does not affect the si gnal state.
Table 2-12. Enhanced Synchronous S erial Interface 0 (ESSI0) (Continued)
Signal
Name Type State Duri ng
Reset1, 2 Signal Description
Enhanced Synchronous Serial Interface 1 (ESSI1)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-15
2.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal
Name Type State Duri ng1
Signal Description
Reset Stop
SC10
PD0
Input or Ou tput Inpu t Disconnected
internally Serial Control 0
Functi ons in eit her Synchronous or Asynchronous mode. For
Asynchronous mode, this si gnal is the receive clock I /O
(Schm it t-t rigger inp ut). For Synchronous mode, thi s signal i s either
for Tra nsm it ter 1 out put or Serial I/ O Flag 0.
Port D 0
The default configuration following reset is GPIO. For PD0, signal
direc ti on is controlled thr ough the Port D Direction Register
(PRRD).
This si gnal is configured as SC10 or PD0 th rough the Por t D
Control Register (PCRD). This input i s 5 V tol erant.
SC11
PD1
Input/Output
Input or Ou tput
Input Disconnected
internally Serial Control 1
Functi ons in eit her Synchronous or Asynchronous mode. For
Asynchronous mode, thi s signal is th e receiver fram e sync I/O. For
Synchronous mode, this signal is ei ther Transmitter 2 output or
Serial I/O Flag 1.
Port D 1
The default configuration following reset is GPIO. For PD1, signal
direc ti on is controlled through PRRD.
This si gnal is configured as SC11 or PD1 throug h PCRD. This
input is 5 V tolerant.
SC12
PD2
Input/Output
Input or Ou tput
Input Disconnected
internally Serial Control Signal 2
The frame sync for bot h the transmitter and receiver in
Synchronous mode, and for the transmitter onl y in Asynchronous
mode. When confi gured as an output, this signal is the int ernall y
generated frame sync si gnal. W hen configured as an input, this
signal receives an external frame sync signal for the tr ansmitter
(and the receiver in synchronous operation).
Port D 2
The default configuration following reset is GPIO. For PD2, signal
direc ti on is controlled through PRRD.
This si gnal is configured as SC12 or PD2 throug h PCRD. This
input is 5 V tolerant.
DSP56303 User’s Manual, Rev. 2
2-16 Freescale Semiconductor
Signals/Connections
2.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial communication
with other DSPs, microprocessors, or peripherals such as modems.
SCK1
PD3
Input/Output
Input or Ou tput
Input Disconnected
internally Serial Clock
Provides the serial bit rate clock f or the ESSI interf ace for both the
transmitter and receiver i n Synchronous modes, or the transmit ter
only in Asynchronous mod es.
Although an external serial cl ock can be independent of and
asynchronous to the DSP system cl ock, it mus t exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times t he ext ernal ESSI clock
freque ncy). The ES SI needs at least three DSP phases i nside each
half of the serial clock.
Port D 3
The default configuration following reset is GPIO. For PD3, signal
direc ti on is controlled through PRRD.
This si gnal is configured as SCK1 or PD3 through PCRD. This
input is 5 V tolerant.
SRD1
PD4
Input
Input or Ou tput
Input Disconnected
internally Serial Receive Data
Receives serial data and transfers the data t o the ESSI receive
shift register . SRD0 is an input when data is being received.
Port D 4
The default configuration following reset is GPIO. For PD4, signal
direction is controlled through PRRD. This signal is configured as
SRD1 or PD4 through PCRD. This input is 5 V tolerant.
STD1
PD5
Output
Input or Ou tput
Input Disconnected
internally Serial Transmit Data
Transmits dat a from the serial transm it shift register. STD1 is an
output when data is being transmitted.
Port C 5
The default configuration following reset is GPIO. For PD5, signal
direction is controlled through PRRD. This signal is configured as
STD1 or PD5 through PCRD. This input is 5 V tolerant.
Notes: 1. The Wait processing stat e does not affect the signal state.
Table 2-13. Enhanced Synchronous S erial Interface 1 (ESSI1) (Continued)
Signal
Name Type State Duri ng1
Signal Description
Reset Stop
Timers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-17
2.11 Timers
The DSP56303 has three identical and independent timers. Each can use internal or external
clocking, interrupt the DSP56303 after a specified number of events (clocks), or signal an
external device after counting a specific number of internal events.
Table 2-14. Serial Communication Interface (SCI)
Signal
Name Type State During 1
Signal Descr iption
Reset Stop
RXD
PE0
Input
Input or
Output
Input Disconnected
internally Serial Receive Data
Receives byte-oriented serial data and tr ansfers it to the SCI
receive shif t register .
Port E 0
The default configur ation fol lowing reset i s GPIO. When configur ed
as PE0, signal direction is controlled through t he Port E Directions
Regist er (PRRE). This signal is configured as RXD or PE0 thr ough
the Port E Contr ol Regi ster (PCRE). This i nput is 5 V tolerant.
TXD
PE1
Output
Input or
Output
Input Disconnected
internally Serial Transmit Data
Transmits data f rom SCI tr ansmit data regi ster.
Port E 1
The default configur ation fol lowing reset i s GPIO. When configur ed
as PE1, signal direction is controlled thr ough the SCI PRRE. This
signa l is c onfigu red as TXD or PE1 thr ough PCRE. Thi s inpu t is 5 V
tolerant.
SCLK
PE2
Input/Output
Input or
Output
Input Disconnected
internally Serial Clock
Provides the inp ut or output cl ock used by the tr ansmitter and/or
the receiver.
Port E 2
The default configuration following reset is GPIO. For PE2, signal
direction is controlled through the SCI PRRE. This signal is
confi gured as SCLK or PE2 through PCRE. This input is 5 V
tolerant.
Notes: 1. The Wait processing state does not affect t he signal state.
Table 2-15. Trip le Timer Signals
Signal
Name Type State Dur ing1
Reset Stop Signal Description
TIO0 I nput or
Output Input Disconnected
internally Timer 0 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO0 is
input . In Watchdog, Timer , or Pulse Mod ulation mode, TIO0 is
output. The default mode after reset i s GPIO input. This can be
changed to output or conf igured as a Timer Input/ Ou tput thr ough
the Timer 0 Control/Status Register (TCSR0). This input is 5 V
tolerant.
DSP56303 User’s Manual, Rev. 2
2-18 Freescale Semiconductor
Signals/Connections
2.12 JTAG/OnCE Interface
TIO1 I nput or
Output Input Disconnected
internally Timer 1 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO1 is
input . In Watchdog, Timer , or Pulse Mod ulation mode, TIO1 is
output. The default mode after reset i s GPIO input. This can be
changed to output or conf igured as a Timer Input/ Ou tput thr ough
the Timer 1 Control/Status Register (TCSR1). This input is 5 V
tolerant.
TIO2 I nput or
Output Input Disconnected
internally Timer 2 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO2 is
input . In Watchdog, Timer , or Pulse Mod ulation mode, TIO2 is
output. The default mode after reset i s GPIO input. This can be
changed to output or conf igured as a Timer Input/ Ou tput thr ough
the Timer 2 Control/Status Register (TCSR2). This input is 5 V
tolerant.
Notes: 1. The Wai t pr ocessing state does not af fect th e signal st ate.
Table 2-16. JT AG/OnC E Interface
Signal Name Type State During
Reset Signal Descri ption
TCK Input Input Test Clock
A test clock s ignal for synchroni zing JTAG test logic. This input is 5
V tolerant.
TDI Input Input Test Data I nput
A test data serial signal for test instructions and data. TDI is
sampled on the ri sing edge of TCK and has an internal pul l-up
resis tor . This i nput is 5 V t olerant.
TDO Output Tri-stated Test Data Output
A test data serial signal for test instructions and data. TDO can be
tri -st ated. The sign al i s actively driven in the shif t-IR and shif t- DR
contro ller s tates and chang es on the fal ling e dge of TCK. Thi s pin is
5 V tolerant.
TMS Input Input Test Mode Select
Sequences the test cont roll er’s stat e ma chine, is sampl ed on the
risi ng edge of TCK, and ha s an i ntern al pul l-up r esist or. Thi s input is
5 V tolerant.
TRST Input Input Test Reset
Asynchronously initializes the test control ler, has an internal pull -up
resistor, and must be asser ted after power up. Thi s input is 5 V
tolerant.
Table 2-15. Triple Timer Signals (Continued)
Signal
Name Type State Dur ing1
Reset Stop Signal Description
JTAG/OnCE Interface
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 2-19
DE Input/Output Input Debug Event
Provides a way to ente r Debug mode from an external command
controller (as input) or to acknowledge that the chi p has entered
Debug mode (as output). When asserted as an input , DE causes
the DSP56300 core to finish the current instr uction, save the
instruction pipeline information, enter Debug mode, and wait for
commands from the debug serial input line. When a debug request
or a br eakpoint cond ition cause the chip to enter Debug mode DE is
asse rted as an output for t hree c lock cycles. DE has an in ternal
pull- up resistor.
DE i s not a standard part of the JTAG Test Access Port (TAP)
Controller . It connect s to the OnCE m odule to initiate Debug mode
directly or to provide a dire ct ext ernal i ndication th at the chip has
entered the Debug mode. Al l other interf ace with the OnCE module
must occur through the JTAG port. This input is 5 V tolerant.
Table 2-16. JTAG/OnCE Interface (Continued)
Signal Name Type State During
Reset Signal Descri ption
DSP56303 User’s Manual, Rev. 2
2-20 Freescale Semiconductor
Signals/Connections
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-1
Memory Configuration 3
Like all members of the DSP56300 core family, the DSP56303 addresses three sets of
16 M × 24-bit memory internally: program, X data, and Y data. Each of these memory spa ces
includes both internal and external memory (accessed through the external memory interface).
The DSP56303 is extremely flexible because it has several modes to allocate internal memory
between the program memory and the two data memory spaces. You can also configure it to
operate in a special sixteen-bit compatibility mode that allows the chip to use DSP56000 object
code without any change; this can result in higher performance of existing code for applications
that do not require a larger address space. This section provides detailed information on each of
these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
Internal program RAM (4 K by default)
Instruction cache (optional, 1 K) formed from program RAM. When enabled, the memory
addresses used by the internal cache memory are switched to external memory. The
internal memory in this address range switches to cache-only mode and is not available via
direct addressing when cache is enabled. In systems using Instruction Cache, always
enable the cache (CE = 1) before loading code into internal program memory; this
prevents the condition in which code loaded into program memory before cache is enabled
“disappears” after cache is enabled.
Off-chip memory expansion (optional, as much as 64 K in 16-bit mode or 256 K in 24-bit
mode using the 18 external address lines or 4 M using the external address lines and the
four address attribute lines). Refer to the DSP56300 Family Manual, especially Chapter
9, External Memory Interface (Port A) , for details on using the external memory interface
to access external program memory.
Bootstrap program ROM (192 × 24-bit)
Note: Program memory space at locations $FF00C0–$FFFFFF is reserved and should not be
accessed.
DSP56303 User’s Manual, Rev. 2
3-2 Freescale Semiconductor
Memory Configuration
3.1.1 Internal Program Memory
The default internal program memory consists of a 24-bit-wide, high-speed, SRAM occupying
the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space, depending on the
settings of the OMR[MS] and (SR[CE]) bits. Section 4.3.2, Operating Mode Register (OMR), on
page 1-15 provides details on the MS bit. Section 4.3.1, Status Register (SR), on page 1-9
provides details on the CE bit. The default internal program RAM is organized in 16 banks with
256 locations each (4 K). Setting the MS bit switches four banks of program memory to the X
data memory and an additional four banks of program memory to the Y data memory. Setting the
CE bit switches four banks of internal program memory to the Instruction Cache and reassigns its
address to external program memory. The memory addresses for the Instruction Cache vary
depending on the setting of the MS and CE bits. Section 3.6 provides a summary of the internal
RAM configurations. Refer to the memory maps for detailed information.
3.1.2 Memory Switch Modes—Program Memory
Memory switch mode allows reallocation of portions of program RAM to X and Y data RAM.
OMR[7] is the memory switch (MS) bit that controls this function, as follows:
When the MS bit is cleared, program memory consists of the default 4 K × 24-bit memory
space described in the previous section. In this default mode, the lowest external program
memory location is $1000. If the CE bit is set, the program memory consists of the lowest
3 K × 24-bits of memory space and the lowest external program memory location is
$0C00.
When the MS bit is set, the highest 2 K × 24-bit portion of the internal program memory is
switched to internal X and Y data memory. In this mode, the lowest external program
memory location is $800. If the CE bit is set and the MS bit is set, the program memory
consists of the lowest 1 K × 24-bits of memory space and the lowest external program
memory location is $400.
3.1.3 Instruction Cache
In program memory space, the location of the internal Instruction Cache (when enabled by the
CE bit) varies depending on the setting of the MS bit, as noted above. Refer to the memory maps
for detailed address information. When the instruction cache is enabled (that is, the SR[CE] bit is
set), 1 K program words switch to instruction cache and are not accessible via addressing; the
address range switches to external program memory.
3.1.4 Program Bootstrap ROM
The program memory space occupying locations $FF0000–$FF00BF includes the internal
bootstrap ROM. This ROM contains the 192-word DSP56303 bootstrap program.
X Data Memory Space
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-3
3.2 X Data Memory Space
The X data memory space consists of the following:
Internal X data memory (2 K by default up to 3 K)
Internal I/O space (upper 128 locations)
Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit mode
using the 18 external address lines, or 4 M using the external address lines and the four
address attribute lines). Refer to the DSP56300 Family Manual, especially Chapter 9,
External Memory Interface (Port A), for details on using the external memory interface to
access external X data memory.
Note: The X memory space at $FF0000–$FFEFFF is reserv ed and should not be accessed.
3.2.1 Internal X Data Memory
The default internal X data RAM is a 24-bit-wide, internal, static memory occupying the lowest
2 K locations ($000–$7FF) in X memory space. The internal X data RAM is organized into 8
banks with 256 locations each. Available X data memory space is increased by 1 K through
reallocation of program memory using the memory switch mode described in the next section.
3.2.2 Memory Switch Modes—X Data Memory
Memory switch mode reallocates portions of program RAM to X and Y data memory. Bit 7 in the
OMR is the MS bit that controls this function, as follows:
When the MS bit is cleared, the X data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest external
X data memory location is $800.
When the MS bit is set, a portion of the higher locations of the internal program memory is
switched to X and Y data memory. The X da ta memory in this mod e consists of a
3 K × 24-bit memory space. In this mode, the lowest external X data memory location is
$C00.
3.2.3 Internal I/O Space—X Data Mem ory
One part of the internal peripheral registers and some of the DSP56303 core registers occupy the
top 128 locations of the X data memory ($FFFF80–$FFFFFF ). This area is referred to as the
internal X I/O space and it can be accessed by move, movep instructions and by bit-oriented
instructions (bchg, bclr, bset, btst, brclr, brset, bsclr, bsset, jclr, jset, jsclr, and jsset). The
contents of the internal X I/O memory space are listed in Appendix A, Bootstrap Program.
DSP56303 User’s Manual, Rev. 2
3-4 Freescale Semiconductor
Memory Configuration
3.3 Y Data Memory Space
The Y data memory space consists of the following:
Internal Y data memory (2 K by default up to 3 K)
External I/O space (upper 128 locations)
Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit mode
using the 18 external address lines, or 4 M using the external address lines and the four
address attribute lines). Refer to the DSP56300 Family Manual, especially Chapter 9,
External Memory Interface (Port A), for details on using the external memory interface to
access external Y data memory.
Note: The Y memory space at $FF0000–$FFEFFF is reserv ed and should not be accessed.
3.3.1 Internal Y Data Memory
The default internal Y data RAM is a 24-bit-wide, internal, static memory occupying the lowest
2 K ($000–$7FF) of Y memory space. The internal Y data RAM is organized into 8 banks with
256 locations each. Available Y data memory space is increased by 1 K through reallocation of
program memory using the memory switch mode described in the next section.
3.3.2 Memory Switch Modes—Y Data Memory
Memory switch mode reallocates of portions of program RAM to X and Y data memory. Bit 7 in
the OMR is the MS bit that controls this function, as follows:
When the MS bit is cleared, the Y data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest external
Y data memory location is $800.
When the MS bit is set, a portion of the higher locations of the internal program memory is
switched to X and Y data memory. The Y da ta memory in this mod e consists of a
3 K × 24-bit memory space. In this mode, the lowest external Y data memory location is
$C00.
3.3.3 External I/O Space—Y Data Memory
The off-chip peripheral registers should be mapped into the top 128 locations of Y data memory
($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit Address mode)
to take advantage of the Move Peripheral Data (MOVEP) instruction and the bit-oriented
instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET,
JSCLR, and JSSET).
Dynam ic Memory Configurat ion Swi tchi ng
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-5
3.4 Dynamic Memory Configuration Switching
Do not change the OMR[MS] bit when the SR[CE] bit is set. The Instruction Cache occupies the
top 1 K of what is otherwise Program RAM, and to switch memory into or out of Program RAM
when the cache is enabled can cause conflicts. To change the MS bit when CE is set:
1. Clear CE.
2. Change MS.
3. Set CE.
Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate
the switch condition, special care should be taken in relation to the interrupt vector routines.
3.5 Sixteen-Bit Compatibility Mode Configuratio n
The sixteen-bit compatibility (SC) mode allows the DSP56303 to use DSP56000 object code
without change. The SC bit (Bit 13 in the SR) is used to switch from the defa ult 24-bit mode to
this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode. The
address ranges described in the previous sections apply in the SC mode with regard to the
reallocation of X and Y data memory to program memory in MS mo de, but the maximum
addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide.
3.6 RAM Configuration Sum mary
The RAM configurations for the DSP56303 are listed in Table 3-1.
CAUTION
To ensure that dynamic switching is tr ouble-free, do not allow any
accesses (including instruction fetches) to or from the affected address
ranges in program and data memories during the switch cycle.
CAUTION
Pay special attention when executing a memory switch routine using the
OnCE port. Running the switch routine in trace mode, for example, can
cause the s witch t o com plete after th e MS/M SW bit s change while th e DSP
is in Debug mode. As a result, subsequent instructions may be fetched
according to the new memory configuration (after the switch) and thus
may execute improperly.
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3-6 Freescale Semiconductor
Memory Configuration
The actual memory locations for Program RAM and the Instruction Cache in the Program
memory space are determined by the MS and CE bits, and their addresses are given in Table 3-2.
3.7 Memory Maps
The following figu res describe each of the memory space and RAM configurations defined by
the settings of the SC, MS, and CE bits. The figures show the configuration and the table
describes the bit settings, memory sizes, and memory locations.
Table 3-1. DSP56303 RAM Configurations
Bit Settings Memory Sizes ( in K)
MS CE Program RAM X data RAM Y dat a RAM Cache
004220
013221
102330
111331
Tabl e 3-2. DSP56303 RAM Address Ranges by Configuration
MS CE Program RAM Location Cache Location
0 0 $000–$FFF N/A
0 1 $000–$BFF $C00–$FFF (internal location not accessible; address range
assigned to ext ernal Pr ogram Memor y)
1 0 $000–$7FF N/A
1 1 $000–$3FF $400–$7FF (i nternal loca ti on not accessible; address ed
assigned to ext ernal Pr ogram Memor y)
Memory Maps
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-7
Figure 3-1. Default Settings (0, 0, 0)
Internal
Reserved
Bootstrap ROM
External
Internal
Pro gra m R A M
4 K
$FFFFFF
$FFF0C0
$FF0000
$001000
$000000
Internal
Reserved
Internal I/O
External
Internal
X data RAM
2 K
External
$000800
Internal
Reserved
External I/O
External
Internal
Y data RAM
2 K
External
$FF0000
$000000
$FFF000
$FFFF80
Program X Data Y Dat a
DEFAULT
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressabl e
Memory Size
000 4 K
$000–$FFF 2 K
$000–$7FF 2 K
$000–$7FF None 16 M
$FFFFFF
$000800
$FF0000
$000000
$FFF000
$FFFF80
$FFFFFF
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3-8 Freescale Semiconductor
Memory Configuration
Figure 3-2. Instruction Cache Enabled (0, 0, 1)
Internal
Reserved
Bootstrap ROM
External
Internal
Program RAM
3 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
In te r n a l I/O
External
Internal
X data RAM
2 K
External
$000800
Internal
Reserved
External I/O
External
Internal
Y data RAM
2 K
External
$FFF000
$FFFF80
Program X Data Y Data
$000C00
Bit Settin gs Memor y Configurati on
SC MS CE Progra m RAM X Da ta RAM Y Data RAM Cache Addressable
Memory Size
001 3 K
$000–$BFF 2 K
$000–$7FF 2 K
$000–$7FF 1 K
internal not
accessible
16 M
$FFFFFF
$FF0000
$000000
$000800
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
Memory Maps
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-9
Figure 3-3. Switched Program RAM (0, 1, 0)
Internal
Reserved
Bootstrap ROM
Internal
Program RAM
2 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
In te r n a l I/O
External
Internal
X data RAM
3 K
External
$000C00
Internal
Reserved
External I/O
External
Internal
Y data RAM
3 K
External
$FFF000
$FFFF80
Program X Data Y Data
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
010 2 K
$000–$7FF 3 K
$000–$BFF 3 K
$000–$BFF None 16 M
External
$FFFFFF
$FF0000
$000000
$000C00
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
$000800
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3-10 Freescale Semiconductor
Memory Configuration
Figure 3-4. Switched Program RAM and Instruction Cache Enabled (0, 1, 1)
Internal
Reserved
Bootstrap ROM
External
Internal
RAM 1 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
In te r n a l I/O
External
Internal
X data RAM
3 K
External
$000C00
Internal
Reserved
External I/O
External
Internal
Y data RAM
3 K
External
$FFF000
$FFFF80
Program X Data Y Data
$000400
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
011 1 K
$000–$3FF 3 K
$000–$BFF 3 K
$000–$BFF 1 K
internal not
accessible
16 M
Program
$FFFFFF
$FF0000
$000000
$000C00
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
Memory Maps
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-11
Figure 3-5. 16-bit Space with Default RAM (1, 0, 0)
External
Internal
Program RAM
4 K
$FFFF
$1000
$0000
In te r n a l I/O
Internal
X data RAM
2 K
External
External I/O
Internal
Y data RAM
2 K
External
Program X Data Y Data
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
100 4 K
$000–$FFF 2 K
$000–$7FF 2 K
$000–$7FF None 64 K
$FFFF
$0000
$FF80
$0800
$FFFF
$0000
$FF80
$0800
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3-12 Freescale Semiconductor
Memory Configuration
Figu re 3-6. 16-bit Space with Instruction Cache Enabled (1, 0, 1)
External
Internal
Program RAM
3 K
$FFFF
$0000
In te r n a l I/O
External
Internal
X data RAM
2 K
External I/O
External
Internal
Y data RAM
2 K
Program X Data Y Data
$0C00
$0800
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
101 3 K
$000–$BFF 2 K
$000–$7FF 2 K
$000–$7FF 1 K
internal not
accessible
64 K
$FFFF
$0000
$FF80
$0800
$FFFF
$0000
$FF80
Memory Maps
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 3-13
Figure 3-7. 16-bit Space with Swi tched Program RAM (1, 1, 0)
Internal
Program RAM
2 K
$FFFF
$0000
In te r n a l I/O
Internal
X data RAM
3 K
External
External I/O
Internal
Y data RAM
3 K
External
$FFFF
$0000
Program X Data Y Data
$FF80
$0C00
$0800
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
110 2 K
$000–$7FF 3 K
$000–$BFF 3 K
$000–$BFF None 64 K
External
$FFFF
$0000
$FF80
$0C00
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3-14 Freescale Semiconductor
Memory Configuration
Figu re 3-8. 16-bit Space, Switched Program RAM, Instruction Cache Enabled
(1, 1, 1)
External
$FFFF
$0000
In te r n a l I/O
Internal
X data RAM
3 K
External
$0C00
External I/O
Internal
Y data RAM
3 K
External
Program X Data Y Data
$0400
Bit Settings Memory Conf iguration
SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable
Memory Size
111 1 K
$000–$3FF 3 K
$000–$BFF 3 K
$000–$BFF 1 K
internal not
accessible
64 K
Internal
RAM 1 K
Program
$FFFF
$0000
$FF80
$0C00
$FFFF
$0000
$FF80
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-1
Core Configuration 4
This chapter presents DSP56300 core configuration details specific to the DSP56303, including:
Operating modes
Bootstrap program
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
Interrupt Priority Registers (IPRC and IPRP)
PLL control (PCTL) register
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
DMA Control Registers 5–0 (DCR[5–0])
Device identification register (IDR)
JTAG identification register
JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the DSP56300
Family Manual.
4.1 Operating Modes
The DSP56303 begins operation by leaving the Reset state and going into one of eight operating
modes. As the DSP56303 exits the Reset state, it loads the values of MODA, MODB, MODC, and
MODD into bits MA, MB, M C, and MD of the OMR. These bit settings determine the DSP
operating mode, which in turn determines the bootstrap program option the DSP uses to start up.
Software can also set the OMR[MA–MD] bits directly. A jump directly to the bootstrap program
entry point ($FF0000) after the OMR bits are set causes the DSP56303 to execute the specified
bootstrap program option (except modes $0 and $8). Table 4-1 shows the DSP 56303 bootstrap
operation modes, the corresponding settings of the external operational mode signal lines (the
OMR[MA–MD] bits), and the reset vector address to which the DSP56303 jumps once it leaves
the Reset state.
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4-2 Freescale Semiconductor
Core Confi gurati on
Table 4-1. DSP56303 Operating Modes
Mode MODD MODC MODB MODA Reset
Vector Description
00000$C00000Expanded mode
Bypasses t he b ootstr ap ROM, and the DSP56303 start s fet ching
instr uctions beginning at address $C00000. Memory accesses
are perf ormed using SRAM memory acc ess type with 31 wait
states and no address attributes selected (default). Address
$C00000 is reflected as address $00000 on Port A signals
A[0–17].
10001$FF0000Bootstra p from byte-wide memory
The bootstrap program loads a program RAM segment from
consecuti ve byte-wide P memory locations, starting at
P:$D00000 (bits 7–0) . The mem ory is select ed by the Address
Attribute AA1 and is access ed wit h 31 wait states. The EPROM
bootstrap code reads 3 bytes specifying the number of program
words, 3 byt es specifying the address to start loading the
program words, and then 3 byt es for each pr ogram word to be
loaded. The number of words, the starting address and the
program words are re ad LSB first foll owed by the mid and then
the MSB. The program words are condensed int o 24-bit words
and stored in conti guous PRAM memory l ocations fr om the
specified starting address. Program execution starts from the
same address where loading start ed.
20010$FF0000Bootstrap through SCI
The DSP is configured to load the progr am RAM from the SCI
interface. The number of program wor ds to be loaded and the
start ing address must be specifi ed. The SCI boot strap code
expects to receive 3 bytes specifying the number of program
words, 3 byt es specifying the address to start loading the
program words and then 3 bytes for each program word to be
loaded. The number of words, the starting address and the
program words are re ceived least signifi cant byte f irst fol lowed
by the mid and then by the most significant by te. After receiving
the progr am words, program executi on starts in the same
address where loading started. The SCI is programmed to work
in asynchronous mod e wit h 8 data bits, 1 stop bit and no pari ty.
The clock source is ext ernal and the cl ock frequency must be
16x the baud rat e. After each byte is received, it is echoed back
through the SCI transmitter.
3 0 0 1 1 $FF0000 Reserved
40100$FF0000HI08 bootst rap i n ISA/DSP5 63xx m ode
The HI08 is configured to load the program RAM from the Host
Inter face programmed to operat e in the ISA mode. The HOST
ISA bootst rap code expects to read a 24-bi t wor d specifying the
number of program words, a 24- bit word specifying the addr ess
to star t lo ading the pr ogram words and then a 24-bit word for
each program word to be loaded. The prog ram words are stor ed
in conti guous P RAM memory l ocations starting a t th e specified
start ing address. Af ter re ading the program words, program
execution start s from the same address where loadi ng started.
The Host Interface boot strap l oad pr ogram may be stopped by
setti ng the Host Flag 0 ( HF0). Thi s star ts execu tion of th e loaded
program fr om the specified starting addr ess.
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-3
50101$FF0000HI08 bootst rap i n HC11 nonmulti plexed mode
The bootstrap progr am sets the host interface to interface wit h
the Freescale HC11 microcontr oller through the HI08. The
HOST HC11 bootstrap code expects to read a 24-bit word
specifying the num ber of program words, a 24-bit word
specifying the address to start lo ading the progr am words and
then a 24-bi t wor d for each program word to be loa ded. The
program words are stor ed in contiguous P RAM memor y
locations s tarting at the specified starting addr ess. Aft er reading
the progr am words, program executi on starts from the sam e
address where loadin g started. The Host Interfa ce bootstrap
load progr am ma y be stopped by setti ng the Host Flag 0 (HF0).
This starts execution of the loaded program from the specified
s t arting ad dr es s.
60110$FF0000HI08 bootst rap i n 8051 multipl exed bus m ode
The bootstrap progr am sets the host interface to interface wit h
the Inte l 8051 bus thr ough the HI08. The HI08 pin configuration
is optim ized for connection to the Intel 8051 mul ti plexed bus, in
double- strobe pin conf igurat ion. Th e HOST 8051 boot stra p code
expects accesses that are byt e wide. The HOST 8 051 bootstrap
code expects to read 3 bytes for ming a 24-bit word speci fying
the number of program words, 3 bytes forming a 24-bit word
specifying the address to start lo ading the progr am words and
then 3 bytes formi ng 24-bit words for each program word to be
loaded. The pr ogram wor ds are stored in contiguous PRAM
memory locat ions st arti ng at the spec ifi ed start ing addr ess. Aft er
reading the program words, progr am executi on starts from the
same address where loading s tarted. The Host Interface
bootst rap load pr ogram may be stopp ed by setting t he Host F lag
0 (HF0). This start s execution of the loaded program from the
specified starting address. The base address of the HI 08 in
multi plexed mode is $80 and is not mo dif ied by the bootstr ap
code. Al l th e add ress l ines a re e nabled a nd s hould be conn ected
accordingly.
7 0 1 1 1 $FF0000 HI08 bootst rap i n MC683 02 bus mode
The bootstrap program loads the program RAM from the Host
Inter face programm ed to operate in the MC68302 bus mode , in
single-strobe pin confi guration. The HOST MC68302 bootstrap
code expect s acces ses that ar e byte wide. The HOST MC68302
bootstrap code expects t o read 3 bytes formi ng a 2 4-bi t word
specifying the num ber of program words, 3 byt es forming a
24-bit word specifying the address to star t l oading the program
words and then 3 bytes for ming 24-bit words for each pr ogram
word to be load ed. The progr am words are stored in contiguous
PRAM memory loca ti ons starting at the specif ied starting
address. After reading the progr am words, progra m exe cution
start s fr om the same address where loadi ng start ed. The Host
Inter face bootstr ap load program may be stopped by se tting the
Host Flag 0 (HF0). This st arts executio n of the l oaded p rogram
from the specified starting addre ss.
Tabl e 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA Reset
Vector Description
DSP56303 User’s Manual, Rev. 2
4-4 Freescale Semiconductor
Core Confi gurati on
8 1 0 0 0 $008000 Expanded mode
Bypasses t he b ootstr ap ROM, and the DSP56303 start s fet ching
instr uctions beginning at address $008000. Memor y accesses
are perf ormed using SRAM memory acc ess type with 31 wait
states and no address attributes selected.
91001$FF0000Bootstra p from byte-wide memory
The bootstrap program it loads a program RAM segment from
consecuti ve byte-wide P memory locations, starting at
P:$D00000 ( bits 7-0). The memory is selected by the Address
Attribute AA1 and is access ed wit h 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying the number of
program words, 3 byt es specifying t he address to start loading
the progr am words and then 3 byt es for each program word to
be loaded. The number of words, the starting address and the
program wor ds ar e read least significant byt e first followed by
the mid and then by the most si gnific ant byte. The program
words are condensed into 24-bit wor ds and stored in conti guous
PRAM memory loca ti ons starting at the specif ied start ing
address. After reading the progr am words, progra m exe cution
start s from the same address where loading st arted.
A1010$FF0000Bootstrap through SCI
The DSP is configured to load the progr am RAM from the SCI
interface. The number of program wor ds to be loaded and the
start ing address must be specifi ed. The SCI boot strap code
expects to receive 3 bytes specifying the number of program
words, 3 byt es specifying the address to start loading the
program words and then 3 bytes for each program word to be
loaded. The number of words, the starting address and the
program words are re ceived least signifi cant byte f irst fol lowed
by the mid and then by the most significant by te. After receiving
the progr am words, program executi on starts in the same
address where loading started. The SCI is programmed to work
in asynchronous mod e wit h 8 data bits, 1 stop bit and no pari ty.
The clock source is ext ernal and the cl ock frequency must be
16x the baud rat e. After each byte is received, it is echoed back
through the SCI transmitter.
B 1 0 1 1 $FF0000 Reserved
C1100$FF0000HI08 bootstrap i n ISA/DSP5 63xx m ode
The HI08 is configured to load the program RAM from the Host
Inter face programmed to operat e in the ISA mode. The HOST
ISA bootst rap code expects to read a 24-bi t wor d specifying the
number of program words, a 24- bit word specifying the addr ess
to star t lo ading the pr ogram words and then a 24-bit word for
each program word to be loaded. The prog ram words are stor ed
in conti guous P RAM memory l ocations starting a t th e specified
start ing address. Af ter re ading the program words, program
execution start s from the same address where loadi ng started.
The Host Interface boot strap l oad pr ogram may be stopped by
setti ng the Host Flag 0 ( HF0). Thi s star ts execu tion of th e loaded
program fr om the specified starting addr ess.
Tabl e 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA Reset
Vector Description
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-5
D1101$FF0000HI08 bootstrap i n HC11 nonmulti plexed mode
The bootstrap progr am sets the host interface to interface wit h
the Freescale HC11 microcontr oller through the HI08. The
HOST HC11 bootstrap code expects to read a 24-bit word
specifying the num ber of program words, a 24-bit word
specifying the address to start lo ading the progr am words and
then a 24-bi t wor d for each program word to be loa ded. The
program words are stor ed in contiguous PRAM m em ory
locations s tarting at the specified starting addr ess. Aft er reading
the progr am words, program executi on starts from the sam e
address where loadin g started. The Host Interfa ce bootstrap
load progr am ma y be stopped by setti ng the Host Flag 0 (HF0).
This starts execution of the loaded program from the specified
s t arting ad dr es s.
E1110$FF0000HI08 bootst rap i n 8051 multipl exed bus m ode
The bootstrap progr am sets the host interface to interface wit h
the Inte l 8051 bus thr ough the HI08. The HI08 pin configuration
is optim ized for connection to the Intel 8051 mul ti plexed bus, in
double- strobe pin conf igurat ion. Th e HOST 8051 boot stra p code
expects accesses that are byt e wide. The HOST 8 051 bootstrap
code expects to read 3 bytes for ming a 24-bit word speci fying
the number of program words, 3 bytes forming a 24-bit word
specifying the address to start lo ading the progr am words and
then 3 bytes formi ng 24-bit words for each program word to be
loaded. The pr ogram wor ds are stored in contiguous PRAM
memory locat ions st arti ng at the spec ifi ed start ing addr ess. Aft er
reading the program words, progr am executi on starts from the
same address where loading s tarted. The Host Interface
bootst rap load pr ogram may be stopp ed by setting t he Host F lag
0 (HF0). This start s execution of the loaded program from the
specified starting address. The base address of the HI 08 in
multi plexed mode is 0x80 and is not modified by t he bootstrap
code. Al l th e add ress l ines a re e nabled a nd s hould be conn ected
accordingly.
F1111$FF0000HI08 bootstrap in MC683 02 bus mode
The bootstrap program loads the program RAM from the Host
Inter face programm ed to operate in the MC68302 bus mode , in
single-strobe pin confi guration. The HOST MC68302 bootstrap
code expect s acces ses that ar e byte wide. The HOST MC68302
bootstrap code expects t o read 3 bytes formi ng a 2 4-bi t word
specifying the num ber of program words, 3 byt es forming a
24-bit word specifying the address to star t l oading the program
words and then 3 bytes for ming 24-bit words for each pr ogram
word to be load ed. The progr am words are stored in contiguous
PRAM memory loca ti ons starting at the specif ied starting
address. After reading the progr am words, progra m exe cution
start s fr om the same address where loadi ng start ed. The Host
Inter face bootstr ap load program may be stopped by se tting the
Host Flag 0 (HF0). This st arts executio n of the l oaded p rogram
from the specified starting addre ss.
Tabl e 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA Reset
Vector Description
DSP56303 User’s Manual, Rev. 2
4-6 Freescale Semiconductor
Core Confi gurati on
4.2 Boots trap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap ROM
located in program memory space at locations $FF0000 –$FF00BF. The bootstrap program can
load any program RAM segment from an external byte-wide EPROM, the SCI, or the host port.
The bootstrap program code is listed in Appendix 4, Core Configuration .
Upon exit from the Reset state, the DSP56303 samples the MODA–MODD signal lines and loads
their values into OMR[MA–MD]. The mode input signals (MODA–MODD) and the resulting MA,
MB, MC, and MD bits determine which bootstrap mode the DSP56303 enters (see Table 4-1).
Note: To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0). The
loaded user program begins executing from t he specified starting address.
You can invoke the bootstrap program options (except modes $0 and $8) at any time by writing
the appropriate values to the MA, MB, MC, and MD bits in the OMR and jumping to the
bootstrap program entry point, $FF0000. Software can set the mode selection bits directly in the
OMR. Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes. The other
bootstrap modes select different specific bootstrap loading source devices. Refer to Appendix A ,
Bootstrap Program for details on the bootstrap program.
In these modes, the bootstrap program expects the following data sequence when downloading
the user program through an external port:
1. Three bytes that specify the number of (24-bit) program words to load .
2. Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56303 program memory.
3. The user program (three bytes for each 24-bit program word).
Note: The three bytes for each data sequence are loaded LSB first.
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
Two CPU registers must be configured to initialize operation. The Status Register (SR) selects
various arithmetic processing protocols and contains several status reporting flag bits. The
Operating Mode Register (OMR) configures several system operating modes and characteristics.
Central Processor Uni t (CPU) Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-7
4.3.1 Status Register (SR)
The Status Register (SR) (Figure 4-1) is a 24-bit register that indicates the current system state of
the processor and the results of previous arithmetic computations. The SR is pushed onto the
system stack when program looping is initialized or a jsr is performed, including long interrupts.
The SR consists of the following three special-purpose 8-bit control registers:
Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8]) .
These special-purpose registers define the current system state of the processor. The bi ts
in both registers are affected by hardware reset, exception processing, enddo (end current
do loop) instructions, rti (return from interrupt) instructions, and trap instructions. In
addition, the EMR bits are affected by instructions that specify SR as their destination (for
example, do forever instructions, brkcc instructions, and movec). During hardware reset,
all EMR bits are cleared. The MR register bits are affected by do instructions, and
instructions that directly reference the MR (for example, andi, ori, or instructions, such as
movec, that specify SR as the destination). During processor reset, the interrupt mask bits
are set and all other bits are cleared.
Condition Code Register (CCR) (SR[7–0]). Defines the results of previous arithmetic
computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU)
operations, parallel move operations, instructions that directly reference the CCR (for
example, ori and andi), and instructions that specify SR as a destination (for example,
movec). Parallel move operations affect only the S and L bits of the CCR. During
processor reset, all CCR bits are cleared.
The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Freescale DSPs. Bit definitions in the following paragraphs
identify the bits within the SR and not within the subregister.
Extended Mode Regi ster (EMR) Mode Register (MR) Condition Code Register (CCR)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP[1–0] RM SM CE SA FV LF DM SC S[1–0] I[1–0] S L E U N Z V C
Reset:
110000000000001100000000
Reser v ed bi t. Re a d as z er o ; w rit e to zer o fo r fut ur e co mp a tib ility
Figure 4-1. Status Register (SR)
DSP56303 User’s Manual, Rev. 2
4-8 Freescale Semiconductor
Core Confi gurati on
Table 4-2. Status Register Bit Definitions
Bit Number Bit Name Reset Value Description
23–22 CP[1–0] 11 Core Priority
Under control of the CDP[1–0] bits in the OMR, the CP bit s specify th e prior ity
of core accesses to external memory. These bits are comp ared against the
prior it y bits of the active DMA channel. If the core pri ori ty is gr eater t han the
DMA priority, the DMA waits for a free time slot on the external bus. If t he core
prior it y is l ess than the DMA priority, the core waits for a free time slot on the
external bus. If the core pri ority equals the DMA pri ori ty, the core and DMA
access t he exter nal bus in a round r obin pat tern ( for ex ample, . .. P, X, Y, DMA,
P, X, Y, . .. ).
Priority
Mode Core
Priority DMA
Priority OMR
(CDP[1-0]) SR (CP[1–0])
Dynamic 0
(Lowest) Determine
d by DCRn
(DPR[1–0])
for active
DMA
channel
00 00
10001
20010
3
(Highest) 00 11
Static core < DMA 01 xx
core = DMA 10 xx
core > DMA 11 xx
21 RM 0 Rounding Mode
Selects the ty pe of rounding per formed by the Data ALU dur ing arithmetic
operati ons. If RM is cle ared, convergent rounding is selected. If RM is set ,
two’s-complement rounding is selected.
20 SM 0 Arithme tic Sat u ra tion Mode
Selects automatic saturati on on 48 bit s for the results going to the
accumulator. This saturati on is performed by a special circuit inside the MAC
unit. The purpose of this bit is t o provi de an Arit hm etic Saturation m ode for
algorithms that do not recognize or cannot take advantage of the extension
accumulator.
19 CE 0 Cache Enable
Enables/disables the instruction cache cont roller . If CE is set , the cache is
enabled, and i nstructions are cached into and fetched fr om the internal
Program RAM. If CE is cleared, the cache is di sabled and t he DSP5 6300 cor e
fetches i nstructions from exter nal or inte rnal program mem ory, accordi ng to
the memory space table of th e specific DSP56300 core-based device.
Note: To ensure proper operation, do not clear Cache Enable mode while
B urst mode is enabled (OMR[BE] is set) .
18 0 Reserved. Write to zer o for futur e compatibil ity.
17 SA 0 Sixteen-Bit Arithmetic Mode
Affect s data width functi onality, enabli ng the Sixteen-bit Arithmetic mode of
operati on. When SA is set, the core uses 16-bit operations instead of 24-bit
operati ons. In this mode, 16- bit data is right-aligned in the 24-bit me mo ry
locations, registers, and 24-bit register port ions. Shi fti ng, li m it ing, roundi ng,
arith me ti c instructions, and moves are performed accor dingly. For det ails on
Sixteen-Bit Arit hmetic mode, consult the DSP56300 Family Manual.
Central Processor Uni t (CPU) Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-9
16 FV 0 DO FOREVER Flag
Set when a DO FOREVER loop executes. The FV flag, li ke the LF fl ag, i s
restored from the stack when a DO FO REVER loop terminates. Stacking and
restor ing the FV flag when initiating and exiting a DO FOREVER loop,
respectivel y, al low progr am loops to be nest ed. Whe n returning from the long
inter rupt with an RTI i nstructi on, the system stack is pulled and the value of
the FV bit is rest ored.
15 LF 0 Do Loop Flag
When a program loop i s in pr ogress, enables t he detecti on of the end of t he
loop. The LF is resto red from stack when a progra m loop termin ates. Sta cking
and restor ing the LF when initiatin g and exiting a prog ram loop, respectively,
allow program loops to be nested. When returning f rom the l ong interrupt wit h
an RTI instruction, the System Stack is pulled and the LF bit val ue is restored.
14 DM 0 Double-Precision Multiply Mode
Enables four multiply/MAC operat ions to i mp lement a double- precision
algorithm that mult iplies two 48-bit operands with a 96- bit result. Clearing the
DM bit disabl es the mode.
The Double-Pr ecision Multiply m ode is supported to maintain object code
compatibility wi th devices in the DSP56000 family. For a m ore effi cient way of
executi ng d ouble pr ecisi on mult iply , ref er to the chap ter on the Data Ari thmeti c
Logic Unit in the DSP56300 Famil y Man ual.
In Double -Preci sion Mul tipl y mode, the beha vior of the fo ur speci fic o per ations
listed in the double-precision algorithm is modified. Therefore, do not use
these operations (with those specific register combinations) in
Double-Pr ecision Multiply mode for any purpose other than the doubl e
precision multiply algorithm. All other Data ALU operat ions (or the four listed
operati ons, but wi th other register combinati ons) can be used.
The double-preci sion multiply algor ithm uses the Y0 Register at all stages.
Therefore, do not change Y0 when running the double-precision multiply
algorithm. If the Data ALU must be used in an int errupt service routine, Y0
should be sav ed with oth er Data ALU regist ers to be use d and res tored befor e
the interrupt routi ne terminates.
13 SC 0 Sixteen-Bit Com patibility Mode
Affect s addressing funct ionality, enabling full compati bility with obj ect code
written for the DSP56000 family. When SC i s set, MOVE operati ons to/ from
any of the foll owing PCU register s clear the eight MSBs of the destina ti on: LA,
LC, SP, SSL, SSH, EP, SZ, VBA and SC. I f th e source is either the SR or
OMR, then the eig ht MSBs of t he destination are also cle ared. If the
destin ation is either the SR or OMR, then the eight MSBs of the destination
are lef t unchange d. To change the v alue of on e of the eight MSBs of the SR or
OMR, clear SC.
SC also affe cts the content s of the Loop Counter Register. If SC is cleared
(normal operati on), t hen a loop coun t value of zero caus es the loop body t o be
skipped, and a loop count value of $FFFFFF causes the lo op to execute the
maximum number of 224 – 1 times. If the SC bit is set, a loop cou nt val ue of
zero cause s th e loop to execu te 216 times, and a loop count value of $FFFFFF
causes the loop to execut e 216 – 1 times.
Note: Due to pi pelining, a change in the SC bit takes effect only aft er three
instr uction cycles. Ins ert three NOP inst ructions aft er the instr uction
that changes the value of this bit to ensur e proper operatio n.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
4-10 Freescale Semiconductor
Core Confi gurati on
12 0 Reserved. W rit e to 0 for future com patibility.
11–10 S[1–0] 0 Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter /limiter Scali ng mode
affect s data read from the A or B accumula tor registers out to the X-data bus
(XDB) and Y-data bus (YDB). Different scaling modes can be used with the
same program code to allow dynami c scali ng. On e application of dynam ic
scaling is to facilitate block floating-point arithmetic. The scaling mode also
affect s the MAC rounding position to maintain proper rounding when diff erent
porti ons of the accumulator registers are re ad out to the XDB and YDB.
Scalin g mode bits are cleared at the st art of a lon g Interrupt Service Routine
and during a hardware reset.
S1 S0 Scaling
Mode Rounding Bit SEquation
0 0 No scali ng 23 S = (A46 XOR A45)
OR (B46 XOR B45)
OR S (previous)
0 1 Scale down 24 S = (A47 XOR A46)
OR (B47 XOR B46)
OR S (previous)
1 0 Scale up 22 S = (A45 XOR A44)
OR (B45 XOR B44)
OR S (previous)
1 1 Re served — S undefi ned
9–8 I[1–0] 11 Interrupt Mask
Reflect the current Interrupt Prio ri ty Level (IPL) of the processor and i ndicate
the IPL needed f or an interr upt source to interrupt t he processor. The curr ent
IPL of the pro cessor can be changed under software control . The i nterrupt
mask bits ar e set dur ing hardware reset, but not during softwar e reset.
Priority I1 I0 Exceptions
Permitted Exceptions M asked
Lowest 0 0 IPL 0, 1, 2, 3 None
0 1 IPL 1, 2, 3 IPL 0
1 0 IPL 2, 3 IPL 0, 1
Highest 1 1 IPL 3 I PL 0, 1, 2
7S0Scaling
Set when a result moves from accumu lator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulat or to register move) and
remains set until explicitly cleared; that i s, the S bit is a sticky bit. The logical
equations of t his bit are de pendent on the Scaling mode. The scaling bi t i s set
if the abs olute value in the accumulator, before scali ng, is > 0.25 or < 0.75.
6L0Limit
Set if the overf low bit is set or i f th e data shif ter/ li m iter cir cuits perform a
limiting operati on. In Ar it hm etic Saturation mode, the L bit is also set when an
arithme ti c saturation occurs in the Data ALU result ; ot herwise, it is not
affect ed. The L bi t is cl eared onl y by a proce ssor reset or by an inst ructi on that
specifical ly cl ears it (that is, a sticky bit); this allows the L bit to be used as a
latching overflow bit . The L bi t is affected by dat a mov em ent operat ions that
read the A or B accumulator r egisters.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
Central Processor Uni t (CPU) Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-11
5E1Extension
Cleared i f all the bi ts of the i nteger porti on of the 56- bit result are all o nes or all
zeros; otherwise, this bit is set. The Scal ing mode defines t he integer portion.
If the E bi t is cleared, then the l ow-order fract ion portion contains all the
significant bit s; the hi gh-order i nteger portion i s sign extension. In this case,
the accumulator extensi on register can be ignored. I f the E bi t is set , i t
indic ates that the accumulator ext ension register is in use.
S1 S0 Scaling Mode Integer Porti on
0 0 No scaling Bits 55–47
0 1 Scale down Bits 55–48
1 0 Scale up Bit s 5–46
1 1 Reserved Undefined
4U0Unnormalized
Set if the two MSBs of the Most Significant Port ion (MSP) of the result are
identical; other wise, this bit is cleared. The MSP portion of the A or B
accumulators i s defined by th e Scali ng mode.
S1 S0 Scaling Mode Integer Porti on
0 0 No scaling U = ( Bit 47 XOR Bit
46)
0 1 Scale down U = (Bit 48 XOR Bit
47)
1 0 Scale up U = (Bit 46 XOR Bit
45)
1 1 Reserved U undefined
3N0Negative
Set if the MSB of the result is set; otherwise, thi s bit is cleared.
2Z0Zero
Set if the resul t equals zero; ot herwise, this bit i s cleared.
1V0Overflow
Set if an arit hm eti c overflow occur s in th e 56-bi t result ; ot herwise, this bit is
cleared. V indicates that the result cannot be represented in the accumulator
register (that is , the register overflowed). In Arithmetic Saturation mode, an
arith meti c overflow occurs if the Data ALU result is not r epresentable in the
accumulator wi thout t he extension part (that is, 48- bit accumulat or or the
32-bit accumulator in Arith metic Sixteen-bit mode).
0C0Carry
Set if a car ry is generated by the MSB resulting from an addition operation.
This bi t is also set if a borrow is generated in a subt raction operation;
otherwi se, thi s bit is cleared. The carry or borr ow is generated from Bit 55 of
the resul t. The C bit is al so affected by bit manipulati on, rotate, and shift
instructions.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
4-12 Freescale Semiconductor
Core Confi gurati on
4.3.2 Op erating Mode Reg ister (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes (EOM
and COM) control the chip’s operating mode. The high byte (SCS) controls and monitors the
stack extension. The OMR control bits are shown in Figure 4-2.
The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected only
by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI, and
other instructions, such as MOVEC, that specify OMR as a destination). The Stack
Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits
(MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,
MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits.
Stack Contr ol/St atus (SCS) Extended Operating Mode (EOM) Chip Operating Mode (COM )
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SENWRPEOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] MS SD EBD MD MC MB MA
Reset:
0000000000000011 0 000****
* After reset , these bits refl ect the correspondi ng value of the mode i nput (th at i s, MODD, MO DC, MODB, or MODA,
respectively).
Reser ve d bit . R e ad as ze r o; wr ite to zero fo r fu tu re compat ib ili ty
Figure 4-2. Operating Mode Register (OMR)
Table 4-3. Operating Mode Register (OMR) Bit Definitions
Bit Number Bit Name Reset Value Descript ion
23–21 0 Reserved . Write to 0 for future compatibility.
20 SEN 0 Stack Extension Enable
Enables/di sables the stack extensio n in dat a me mo ry. If the SEN bit is set ,
the extension is enabled. Hardwar e reset clear s this bit, so the defaul t out of
reset is a disabled stack extension.
19 WRP 0 Stack Extens ion Wrap Flag
Set when copyi ng from the int ernal har dware stack (System Stack Register
file) to the stack ext ension memory begins. You can use this flag during the
debugging phase of t he software development to eval uate and increase the
speed of softwar e-impl ement ed algor ithms. The WRP flag i s a sti cky b it (t hat
is, cleared only by hardware reset or by an explicit MOVEC operati on to the
OMR ).
18 EOV 0 Stack Extension Overflow Flag
Set when a stack overflow occurs in Stack Extended mode. Extended stack
overflow is recognized when a push operat ion is requested while SP = SZ
(Stack Size re giste r), an d the Ext ended mode is enab led by t he SEN bit . The
EOV flag is a sticky bit (that is, cleared only by hardware reset or by an
expli cit MOVEC operation to the OMR). The transit ion of t he EOV fla g from
zero to one causes a Prior ity Level 3 (Non -m askable) stack error excepti on.
Central Processor Uni t (CPU) Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-13
17 EUN 0 Stack Extension Underflow Flag
Set when a st ack unde rflo w occ urs i n Extende d St ack mo de. Ext ended st ack
underflow is recognized when a pull operati on is request ed, SP = 0, and t he
SEN bit enables Extended mode. The EUN flag is a sti cky bit (th at is, c lea red
only by hardware reset or by an explicit MOVEC operati on to the OMR).
Transition of the EUN flag from zero to one causes a Priority Level 3
(Non-maskable) stack error except ion.
NOTE: While the chip is in Extended Stack mode, the UF bi t in the SP act s
like a normal counter bit.
16 XYS 0 Stack Extension XY Select
Determi nes whether the stack extension is mapped onto X or Y memory
space. If the bit is clear, then the stack extension is mapped onto the X
memory space. If the XYS bit is set, the stack extension is mapped to the Y
memory space.
15 ATE 0 Address Trac e Enable
When set, the Address Tr ace Enable (ATE) bit enables Address Trace
mode. The Address Trace mode is a debugging t ool that re fl ects internal
memory accesses at the extern al bus address.
14 APD 0 Address Attribute Priority Disa ble
Disabl es the pri ority assi gned to the Address Att ri bute signals (AA[0–3]).
When APD = 0 (def ault set ting), the fou r Ad dress At tri bute si gnals each have
a certai n prior ity: AA3 has the highest pr iori ty, AA0 has t he lowest priority.
Therefore, onl y one AA signal can be active at one ti m e. Thi s allows
conti nuous part iti oning of external memory ; however, cert ain fu nction s, such
as using the AA si gnals as addit ional address l ines, requi re the use of
additional interface hardware. When APD is set, the priority mechanism is
disabl ed, all owing more than one AA signal to be active simult aneously.
Therefore, the AA signal s can be used as additional address li nes wit hout
the need for additional interf ace hardware. For details on the Addres s
Attr ibute Regist ers, see Se ct i o n 4. 6.3, Address Attribute Regi sters
(AAR[0–3]), on page 4-26.
13 ABE 0 Asynchronous Bus Arbitration Enable
Eliminates the setup and hold time requirements for BB and BG, and
substitutes a required non-overlap interval between the deassertion of one
BG input to a DSP5630 0 family devic e and the assertion of a second BG
input to a second DSP56300 family device on t he sam e bus. When the ABE
bi t is set, th e BG and BB inputs are synchr onized. This synchronization
causes a delay between a change in BG or BB unti l this change i s actually
accepted by the r eceiving device .
12 BRT 0 Bus Release Timing
Selects between fas t or sl ow bus release. If BRT is cleared, a Fast Bus
Release mode is sel e cted (that is, no additi onal cycles are added to the
access and BB is not guaranteed to be the la st Port A pin that is tri-st ated at
the end of th e access). If BRT i s set, a Slow Bus Release mode is sel ected
(that is, an additi onal cycle is added to the access, and BB is the last Port A
pin that is tri-stated at the end of the acc ess).
11 TAS 0 TA Synchronize Selec t
Selects the synchr onization method f or the in put Port A pin—TA (Transfer
Acknowledge). If TAS is clear ed, you are r esponsible for asserting the TA
pin i n synchr ony with t he chip clock, as desc ribed in the techni cal da ta sheet.
If TA S is set, th e T A i nput pin i s synchronized inside th e chip, thus
eliminating the need for an off-chip synchronizer. Note that the TAS bit has
no effec t when the TA pin is deassert ed: you are respons ib le for deas serting
the TA pin in synchrony with the chip clock, regardless of the value of TAS.
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Descript ion
DSP56303 User’s Manual, Rev. 2
4-14 Freescale Semiconductor
Core Confi gurati on
10 BE 0 Cache Burst Mode Enable
Enables/di sables Burst mo de in t he memor y expansion port dur ing an
instruction cache miss. If the bit is cleared, Bur st mode is dis abled and only
one program word is fetched from the exter nal memory when an instructi on
cache miss condi tion is det ected. If the bi t is set, Burs t mode is enabl ed, and
up to four program wor ds are fetched from the exter nal memory when an
instruction cache miss is detected.
9–8 CDP[1–0] 11 Core-DMA Priority
Specif y the pri ority of cor e and DMA accesses to the external bus.
00 De termine d by comparing sta tus regi ster CP[1– 0] to the active
DMA chan nel priorit y
01 DMA accesses have higher priority than core accesses
10 DMA accesses have the same priority as the core accesses
11 DMA accesses have lower priority t han the core accesses
7MS0Memory Switch Mode
Allows som e intern al data memory (X, Y, or both) t o become part of t he chip
internal Program RAM.
Notes: 1. Program data placed in the Program RAM/Inst ructi on Cache
area changes it s placement after the OMR[M S] bi t is set (that
is, the Instr uction Cache always uses the hi ghest in ternal
program RAM a ddresses).
2. To ensure proper operation, place six NOP instructions after
the instruction that changes the MS bit.
3. To ensure proper operation, do not set the MS bit while the
Instr uction Cache is enabled (SR[CE] bit is set ).
6SD0Stop Delay Mode
Determines the len gth of the delay invoked when the core exits the Stop
state. The STOP instr uction suspends core processing indefinit ely until a
defin ed ev ent occu rs to r estar t it . If S D is cleare d, a 128K c lock c ycl e delay is
invoked before a STOP instruction cycle conti nues. However, if SD is set,
the delay before the instructio n cycle continues i s 16 clock cycles. The long
delay al lows a clock stabilization period for the internal clock to begin
oscil lati ng and to stabilize . When a stable external cl ock is used, the shorter
delay allows faster start-up of the DSP56300 core.
50 Reser ved. Wr ite to zero for f uture compatibility.
4 EBD 0 External Bus Disab le
Disabl es the external bus controller to reduce powe r consumption when
external memories are not used. When EBD is set, the external bus
controller is disabled and external memory cannot be accessed. W hen EBD
is cl eared, the exter nal bus controller is enabled and external access can be
performed. Hardware reset clear s the EBD bi t.
3–0 MD–MA * Chip Operating Mode
Indic ate the oper ating mode of the DSP56300 core. On hardware r eset,
these bits are loaded from the external mode select pins, MODD, MODC,
MODB, and MODA, re specti vely. Af ter th e DSP5 6300 cor e leaves the Reset
state, MD–MA can be changed under program control.
* The MD–MA bits reflect the correspondi ng value of the mode input (that is, MODD–MODA), respecti vely.
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Descript ion
Configur ing Interrupts
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-15
4.4 Configuring Interrupts
DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for DSP
applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture
Overview, in the DSP56300 Family Manual. Two registers are programmed to configure the
interrupt characteristics:
Interrupt Priority Register-Core (IPRC). Configure the priority levels for the core DMA
interrupts and the external interrupt lines as well as the interrupt line trigger mode s.
Interrupt Priority Register-Peripherals (IPRP). Configure the priority levels for the
interrupts used with the internal peripheral devices
The interrupt table resides in the 256 locations of program memory to which the PCU vector base
address (VBA) register points. These locations store the starting instructions of the interrupt
handler for each specified interrupt. The memory is programmed by the bootstrap program at
start-up.
4.4.1 Interrupt Priority Registers (IPRC and IPRP)
There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is dedicated to
DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56303 peripheral
interrupt sources.
Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
IAL0IAL1IAL2IBL0IBL1IBL2ICL0ICL1ICL2 01234567
8
91011
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
D0L0D0L1D1L0D1L1
23 22 21 20 19 18 17 16 15 14 13 12
DMA0 IPL
DMA1 IPL
D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
IDL2 IDL1 IDL0
IRQD mode
DSP56303 User’s Manual, Rev. 2
4-16 Freescale Semiconductor
Core Confi gurati on
Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL bits.
The IPRC also selects the trigger mode of the external interrupts (IRQA–IRQD). If the value of the
IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2 Interrupt Table Memory Map
Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries for
interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56303 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are used
for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for
host NMI (IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector locations can
be used for program or data storage.
Table 4-4. Interrupt Priori ty Level Bits
IPL bits Interrupts Enabled Inter rupts Masked Interrupt Prior it y Level
xxL1 xxL0
00 No — 0
01 Yes 0 1
10 Yes 0, 1 2
1 1 Ye s 0 , 1 , 2 3
HPL0HPL1S0L0S0L1S1L0S1L1
23 22 21 20 19 18 17 16 15 14 13 12
01234567
8
91011
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IP L
TRIPLE TIMER IPL
T0L0
T0L1 SCL0SCL1
reserved
reserved
Reserved bit ; re ad as zero; should be written wit h zero for future compatibility
Configur ing Interrupts
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-17
Ta ble 4-5. Interrupt Sources
Interrupt
Starting Address
Interrupt
Priority Level
Range Interrupt Source
VBA:$00 3 Hardware RESET
VBA:$02 3 Stack error
VBA:$04 3 Illegal instruction
VBA:$06 3 Debug request interrupt
VBA:$08 3 Trap
VBA:$0A 3 Nonmaskable interrupt (NMI )
VBA:$0C 3 Reserved
VBA:$0E 3 Reserved
VBA:$10 0–2 IRQA
VBA:$12 0–2 IRQB
VBA:$14 0–2 IRQC
VBA:$16 0–2 IRQD
VBA:$18 0–2 DMA channel 0
VBA:$1A 0–2 DMA ch annel 1
VBA:$1C 0–2 DMA channel 2
VBA:$1E 0–2 DMA ch annel 3
VBA:$20 0–2 DMA channel 4
VBA:$22 0–2 DMA channel 5
VBA:$24 0–2 TIMER 0 compare
VBA:$26 0–2 TIMER 0 overflow
VBA:$28 0–2 TIMER 1 compare
VBA:$2A 0–2 TIMER 1 over fl ow
VBA:$2C 0–2 TIMER 2 compare
VBA:$2E 0–2 TIMER 2 over fl ow
VBA:$30 0–2 ESSI0 receive data
VBA:$32 0–2 ESSI0 recei ve data with exce pti on status
VBA:$34 0–2 ESSI0 receive last slot
VBA:$36 0–2 ESSI0 transmit dat a
VBA:$38 0–2 ESSI0 transmit dat a with exception status
VBA:$3A 0–2 ESSI0 tran smit las t sl ot
VBA:$3C 0–2 Reserved
VBA:$3E 0–2 Reserved
VBA:$40 0–2 ESSI1 receive data
VBA:$42 0–2 ESSI1 recei ve data with exce pti on status
DSP56303 User’s Manual, Rev. 2
4-18 Freescale Semiconductor
Core Confi gurati on
4.4.3 Processing Interrupt Source Priorities Within an IPL
If more than one interrupt request is pending when an instruction executes, the interrupt source
with the highest IPL is serviced first. When several interrupt requests with the same IPL are
pending, another fixed-priority structure within that IPL determines which interrupt source is
serviced first. Table 4-6 shows this fixed-priority list of interrupt sources within an IPL, from
highest to lowest at each level The interrupt mask bits in t he Status Register (I[1–0]) can be
programmed to ignore low priority-level interrupt requests.
VBA:$44 0–2 ESSI1 receive last slot
VBA:$46 0–2 ESSI1 transmit dat a
VBA:$48 0–2 ESSI1 transmit dat a with exception status
VBA:$4A 0–2 ESSI1 tran smit las t sl ot
VBA:$4C 0–2 Reserved
VBA:$4E 0–2 Reserved
VBA:$50 0–2 SCI receive data
VBA:$52 0–2 SCI recei ve data wi th excepti on status
VBA:$54 0–2 SCI transmit data
VBA:$56 0–2 SCI idle line
VBA:$58 0–2 SCI timer
VBA:$5A 0–2 Reserved
VBA:$5C 0–2 Reserved
VBA:$5E 0–2 Reserved
VBA:$60 0–2 Host receive data f ull
VBA:$62 0–2 Host transmit data em pty
VBA:$64 0–2 Host co mm and (default)
VBA:$66 0–2 Reserved
:::
VBA:$FE 0–2 Reserved
Tabl e 4-6. Interrupt Source Priorities Within an IPL
Priority Interrupt Source
Level 3 (nonmaskable)
Highest Hardware RESET
Stack error
Table 4-5. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority Level
Range Interrupt Source
Configur ing Interrupts
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-19
Illegal instruct ion
Debug request i nterrupt
Trap
Lowest No nm askable interrupt
Levels 0, 1, 2 (m askable)
Highest IRQA (external interrupt)
IRQB (external interrupt)
IRQC (external interrupt)
IRQD (external interrupt)
DMA chan nel 0 interrupt
DMA chan nel 1 interrupt
DMA chan nel 2 interrupt
DMA chan nel 3 interrupt
DMA chan nel 4 interrupt
DMA chan nel 5 interrupt
Host comm and interrupt
Host transmit data empty
Host receive dat a ful l
ESSI0 RX data with exception interrupt
ESSI0 RX data interrupt
ESSI0 receive la st sl ot int errupt
ESSI0 TX data wi th exception interrupt
ESSI0 tr ansmit last slot interrupt
ESSI0 TX data i nterr upt
ESSI1 RX data with exception interrupt
ESSI1 RX data interrupt
ESSI1 receive la st sl ot int errupt
ESSI1 TX data wi th exception interrupt
ESSI1 tr ansmit last slot interrupt
ESSI1 TX data i nterr upt
SCI r eceive dat a with exception interr upt
SCI rec eiv e data
SCI tr ansm it data
SCI idle line
SCI timer
TIMER0 overfl ow inter rupt
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority Interrupt Source
DSP56303 User’s Manual, Rev. 2
4-20 Freescale Semiconductor
Core Confi gurati on
4.5 PLL Control Register (PCTL)
The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring
the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs
the internal PLL operation. (See Figure 4-5.)
Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL to
lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.
TIME R0 compare int errupt
TIMER1 overfl ow inter rupt
TIME R1 compare int errupt
TIMER2 overfl ow inter rupt
Lowest T IMER2 compare int errupt
23 22 21 20 19 18 17 16 15 14 13 12
PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 DF0
11109876543210
MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0
Figure 4-5. PLL Co ntro l Register (PC TL)
Table 4-7. PLL Control Register (PCTL) Bit Definitions
Bit Number Bi t Name Reset Value Description
23–20 PD[3–0] 0 Pr e d iv id e r F a ct o r
Define t he predivis ion factor (PDF) to be appli ed to the PLL i nput fre quency.
The PD[3–0] bits are cl eared during DSP56303 har dware reset, which
corresponds to a PDF of one.
19 COD 0 Clock Output Disable
Controls the output buffer of t he clock at the CLKOUT pin . When COD is set,
the CLKOUT output is pulled high. When COD i s cleared, t he CLKO UT pin
provides a 50 percent duty cycl e clock.
18 PEN Set to PINIT
input value PLL Enable
Enables PLL operatio n.
17 PSTP 0 PLL Stop State
Control s PLL and in ternal crys tal os cill ator behav ior du ring t he sto p pr ocessi ng
state.
16 XTLD 0 XTAL Disable
Controls the internal crystal oscillator XTAL output. The XTLD bit is cleared
during DSP56303 hardware reset, so the XTAL output signal is active,
permitting norm al operat ion of th e crystal osc illato r.
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority Interrupt Source
Bus Interface Unit (BIU ) Regi sters
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-21
4.6 Bus Interface Unit (BIU) Registers
The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port
A). They include the following:
Bus Control Register (BCR)
DRAM Control Register (DCR)
Address Attribute Registers (AAR[3–0])
To use Port A correctly, configure these registers as part of the bootstrap process. The following
subsections describe these registers.
4.6.1 Bus Control Register (BCR)
The Bus Control Register (BCR), depicted in Figure 4-6, is a read/write register that controls the
external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21, BBS,
are read/write bits. The BCR bits are defined in Table 4-8.
Figur e 4-6. Bus Control Register (BCR)
15 XTLR 0 Crystal Range
Control s the inter nal crystal oscilla tor transconductance. The XTLR bit is
cleared (0) during hardware r eset.
14–12 DF[2–0] 0 Division Factor
Define the DF of the l ow-power di vider. These bits specify the DF as a power
of two in t he range from 20 to 27.
11–0 MF[11–0] 0 PLL Multipl icati on Factor
Define t he mu lt iplica tion facto r that is applied to the PLL input f requency. The
MF bits are cleared during hardware reset and thus correspond to an M F of
one.
23 22 21 20 19 18 17 16 15 14 13 12
BRH BBS BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2
11109876543210
BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0
Reserved bi t. Read as zero; write to zero for futur e com patibility
Table 4-7. PLL Control Register (PCTL) Bit Definitions (Continued)
Bit Number Bi t Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
4-22 Freescale Semiconductor
Core Confi gurati on
Table 4-8. Bus Control Register (BCR) Bit Definitions
Bit
Number Bit Name Reset Value De scri ption
23 BRH 0 Bus Request Hold
Asserts the BR signal, even if no external acc ess is needed. When BRH is set , the
BR signal is al ways asserted. If BRH is cleared, the BR is asserted only i f an
external access is attempted or pending.
22 0 Re s er v ed . Wr it e to zero fo r fu tu re co mp at ib ility.
21 BBS 0 Bus State
This re ad-only bit is set when the DSP is the bus master and is cleared otherwi se.
20–16 BDFW 11111
(31 wait
states)
Bus Default Area W ait Stat e Control
Defines the number of wai t stat es (one through 31) ins erted into each external
access to an area that is not defined by any of t he AAR r egisters. The access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory acc ess requires at least one wai t stat e.
When four through seven wait states are sel ected, one additional wai t state is
inserted at th e end of the access. When selecting eig ht or more wa it states, two
additional wait stat es are insert ed at the end of the access. These trailing wai t
states increase the data hol d ti m e and the memor y rel ease time and do not
increase the me mo ry access time.
15–13 BA3W 1
(7 wait
states)
Bus Area 3 Wait Stat e Control
Defines the number of wait states (one through seven) inserted i n each ex ternal
SRAM acce ss to Area 3 (DRAM accesses are not affecte d by these bits). Area 3 is
the area defi ned by AAR3.
Note: Do not program the value of thes e bit s as zero since SRAM mem ory
access requires at l east one wai t state.
When four through seven wait states are sel ected, one additional wai t state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release ti m e and does not increase the memory access ti m e.
12–10 BA2W 111
(7 wait
states)
Bus Area 2 Wait Stat e Control
Defines the number of wait states (one through seven) inserted i nto each external
SRAM acce ss to Area 2 (DRAM accesses are not affecte d by these bits). Area 2 is
the area defi ned by AAR2.
Note: Do not program the value of these bits as zero, since SRAM memory
access requires at l east one wai t state.
When four through seven wait states are sel ected, one additional wai t state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release ti m e and does not increase the memory access ti m e.
Bus Interface Unit (BIU ) Regi sters
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-23
4.6.2 DRAM Control Register (DCR)
The DRAM controller is an efficient interface to dynamic RAM devices in both random
read/write cycles and Fast Access mode (Page mode). An internal DRAM controller controls the
page hit circuit, the address multiplexing (row address and column address), the control signal
generation (CAS and RAS) and the refresh access generation ( CAS before RAS) for a variety of
DRAM module sizes and access times. The internal DRAM controller configuration is
determined by the DRAM Control Register (DCR). The DRAM Control Register (DCR) is a
24-bit read/write register that controls and co nfigures the external DRAM accesses. The DCR
bits are shown in Figure 4-7.
Note: To prevent improper device operation, you must guarantee that all the DCR bits except
BSTR are not changed during a DRAM access.
9–5 BA1W[4–0] 11111
(31 wait
states)
Bus Area 1 Wait Stat e Control
Defines the number of wai t states (one thro ugh 31) inserted into each external
SRAM acce ss to Area 1 (DRAM accesses are not affecte d by these bits). Area 1 is
the area defi ned by AAR1.
Note: Do not program the value of these bits as zero, since SRAM memory
access requires at l east one wai t state.
When four through seven wait states are sel ected, one additional wai t state is
inserted at th e end of the access. When selecting eig ht or more wa it states, two
additional wait stat es are insert ed at the end of the access. These trailing wai t
states increase the data hol d ti m e and the memor y rel ease time and do not
increase the me mo ry access time.
4–0 BA0W 11111
(31 wait
states)
Bus Area 0 Wait Stat e Control
Defin es the n umber of wait stat es (one thr ough 31) inser te d in eac h exter nal SRAM
access to Area 0 (DRAM accesses are not affected by these bits). Area 0 is the
area defined by AAR0.
Note: Do not program the value of these bits as zero, since SRAM memory
access requires at l east one wai t state.
When selecting four through seven wait states, one additional wait state is inserted
at the end of the access. W hen selecting eight or more wait states, two additional
wait st ates are insert ed at the end of th e access . These traili ng wait states increase
the data hold time and the memory r elease ti m e and do not incr ease the mem ory
access time.
Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset Value De scri ption
DSP56303 User’s Manual, Rev. 2
4-24 Freescale Semiconductor
Core Confi gurati on
Figu re 4-7. DRAM Control Register (DCR)
Table 4-9. DRAM Control Register (DCR) Bit Definitions
Bit
Number Bit Name Reset
Value Description
23 BRP 0 Bus Refresh Prescaler
Controls a prescaler in series wi th the refresh clock divider. If BPR i s set, a divide-by-64
prescaler is connect ed in seri es with the refresh clock divider. If BPR is cl eared, t he
prescaler is bypassed. The refresh request rate (in clock cycles) i s the value writt en to
BRF[7–0] bits + 1, multiplied by 64 (if BRP is set) or by one (if BRP is cleared). When
programming the periodic re fresh rate, you m ust consi der the RAS time-out period.
Hardware support for the RAS time- out rest riction does not exi st.
Note: Refresh requests are not accumulated and, therefore, in a fast refresh request
rate not al l the refresh requests are served (for example, the combination
BRF[7–0] = $00 and BRP = 0 generates a refresh r equest every clock cycle, but
a refresh access takes at least five clock cycles).
22–15 BRF[7–0] 0 Bus Refresh Rate
Controls the refresh request rate. The BRF[7–0] bits specify a divide rate of 1–25 6
(BRF[7–0] = $00–$FF). A refresh request is generated each ti m e the r efresh counter
reaches zero if the refresh counter is enabled (BRE = 1).
14 BSTR 0 Bus Softw are Triggered Reset
Generates a soft ware-t riggered refres h request. Whe n BSTR is set, a refresh request is
generated and a refr esh access is executed to all DRAM banks (the exact ti m ing of the
refr esh access depends on the pending external accesses and the status of the BM E bit) .
After the refresh acc ess (CAS before RAS) is executed, the DRAM contr oller hardware
clears the BSTR bit. The ref resh cycle length depends o n the BRW[1–0] bi ts (a refresh
access is as long as the out-o f-page access).
13 BREN 0 Bus Refresh Enable
Enables/di sables the inte rnal refresh counter . When BREN is set , the ref resh counter is
enabled and a ref resh request (CAS before RAS) i s generated each time the ref resh
counter reaches zer o. A refre sh cycle occu rs fo r all DRAM banks togethe r (that i s, all pins
that ar e defi ned as RAS are asserted toget her). When this bi t is cleared, the refresh
counter is disab led and a refresh request may be software triggered by using the BSTR
bit. In a system in which DSPs share the same DRAM, th e DRAM controller of more than
one DSP may be active, but it is recomme nded that onl y one DSP have its BREN bit set
and that bus mastership is requested for a refresh access. If BREN is set and a WAIT
instruction is executed, peri odic refresh is still generated each ti m e the refresh counter
reaches zero. If BREN i s set and a STOP instr uction is executed, peri odic refresh i s not
generated and the ref resh counter is disabled. The cont ents of t he DRAM ar e lost.
23 22 21 20 19 18 17 16 15 14 13 12
BRP BRF7 BRF6 BRF5 BRF4 BRF3 BRF2 BRF1 BRF0 BSTR BREN BME
11109876543210
BPLE BPS1 BPS0 BRW1 BRW0 BCW1 BCW0
Reserved bit . Read as zero; wri te to zero f or future compat ibility
Bus Interface Unit (BIU ) Regi sters
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-25
12 BME 0 Bus Mastershi p Enable
Enables/disables interface to a local DRAM for the DSP. When BME is cleared, the RAS
and CAS pins are t ri -stated when mastership i s lost. Ther efore, you must connect an
external pul l-up resistor to these pins. In this case (BME = 0), the DSP DRAM controller
assum es a page fault each time the mastership is lost. A DRAM refresh requires a bus
mastership. If t he BM E bit is s et, the RAS and CAS pins are always driven from the DSP.
Therefore, DRAM refresh can be performed, even if the DSP is not the bus master.
11 BPLE 0 Bus Page Logic Enable
Enables/di sables the in-p age identifying logic. When BPLE is set, it ena bles the page
logic (the page size is defined by BPS[1–0] bits). Each in-page identification causes the
DRAM contro ller to dri ve onl y the col umn ad dress ( and t he associ ated CAS s ign al). Wh en
BPLE is cleare d, the page logic is di sa bled, and the DRAM cont roll er al ways accesses th e
external DRAM in out-of- page accesses (for example , row add ress with RAS assertion
and then column address with CAS asser tion). This mode is useful for low power
dissi pation. Only one in-page identi fying logi c exists. Therefore, during swit ches from one
DRAM external bank to another DRAM bank (t he DRAM exter nal banks are def ined by
the access type bits in the AARs, different exte rnal banks are accessed through di ff erent
AA/RAS pins), a page fault occurs.
10 0 R eserved. Write t o zero for f uture compatibility.
9–8 BPS 0 Bus DRAM Page Size
Defines the size of the external DRAM page and thus the number of t he column address
bits . The internal page m echanism works according to these bits only if the page logic is
enabled (by the BPLE bit). The four combinations of BPS[1–0] enable the use of many
DRAM sizes (1 M bit , 4 M bit, 16 M bit, and 64 M bit). The encoding of BPS[1–0] is:
00 = 9-bit column width, 512 words
01 = 10-bit column width, 1 K words
10 = 11-bit column width, 2 K words
11 = 12-bit column width, 4 K words
When the row address is driven, all 24 bits of the external address bus are driven [for
examp le, if BPS[1–0] = 01, when driving the row address, the 14 MSBs of the internal
address (XAB, YAB, PAB, or DAB) are driven on address l ines A[0–13], and the address
lines A[14–23] are driven with the 10 MSBs of the internal addr ess. This method enables
the use of diff erent DRAMs with the same page si ze.
7–4 0 R eserved. Write t o zero for future compatibility.
3–2 BRW 0 Bus Row Out-of-page Wa it State s
Defines the number of wait st ates that should be inserted int o each DRAM out-of-page
access. The encoding of BRW[1–0] is:
00 = 4 wait states for each out- of-page access
01 = 8 wait states for each out- of-page access
10 = 11 wait sta tes for eac h out-of-page access
11 = 15 wait sta tes for eac h out-of-page access
1–0 BCW 0 Bus Colu mn In-Page Wait State
Defines the number of wai t states t o insert for each DRAM in-page access. The encoding
of BCW[1–0] is:
00 = 1 wait state for each in-p age access
01 = 2 wait states for each in-page access
10 = 3 wait states for each in-page access
11 = 4 wait states for each in-page access
Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
DSP56303 User’s Manual, Rev. 2
4-26 Freescale Semiconductor
Core Confi gurati on
4.6.3 Address Attrib ute Registers (AAR[0–3])
The Address Attribute Registers (AAR[0–3]) are read/write registers that control the activity of
the AA0/RAS0–AA3/RAS3 pins. The associated AAn/RASn pin is asserted if the address defined by
the BAC bits in the associated AAR matches the exact number of external address bits defined by
the BNC bits, and the external address space (X data, Y data, or program) is enabled by the AAR.
Figure 4-8 shows an AAR register; Table 4-10 lists the bit definitions.
Note: The DSP56303 does not support address multiplexing.
Figure 4-8. Address A ttribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6)
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number Bit Name Reset
Value Description
23–12 BAC 0 Bus Address to Compare
Read/write control bits t hat define the upper 12 bi ts of the 24-bit add ress with which to
compare the exter nal address to determ ine whether to assert th e corr esponding AA/RAS
signal . Thi s is a lso tr ue o f 16-b it compa tibi lity m ode. Th e BNC[3–0] bi ts def ine th e number of
address bits to compare.
11–8 BNC 0 Bus Number of Address Bits to Compare
Specify the number of bits ( from the BAC bits ) tha t are comp ared to the external address.
The BAC bits are alway s compared wi th the Mos t Signi fican t Portion o f the ext er nal addr ess
(for example, i f BNC[3– 0] = 0011, then the BAC[11–9] bit s are compared to the 3 MSBs of
the exte rnal address). If no bits are specified (that is, BNC[3–0] = 0000), the AA signal is
activated for the entire 16 M-word space identified by the space enable bit s (BPEN, BXEN,
BYEN), but only when the address is externa l to the in ternal memo ry map. The
combinations BNC[3–0] = 1111, 1110, 1101 are reser ved.
BAC0
BPEN 0
1
BYEN 2BAT1
3BAAP
4
567891011 BXEN
121314
BAC8 15
1617181920212223
BAT0
BAC3 BAC2BAC11 BAC5BAC7 BAC6BAC9BAC10 BAC1
BNC3 BNC1BNC2 BNC0
BAC4
BPAC
Re s e rv e d Bit . Write to ze ro fo r fu tu r e c ompat ib ility.
External Access Type
AA pin pola ri ty
Program space Enable
X data space Enable
Y data space Enable
Reserved
Packing Enable
Number of Address bit to
compare
Address to Compare
Bus Interface Unit (BIU ) Regi sters
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-27
7 BPAC 0 Bus Packing Enable
Enables/disables the internal packing/un packing logic. When BPAC is set, packing is
enabled. In this mode each DMA external access initi ates three external accesses to an
8-bit wide exter nal memory (the addresses for the se accesses are DAB, then DAB + 1 and
then DAB + 2). Packing to a 24-bi t word (or unpacking fro m a 24-bit word to thr ee 8-bit
words) i s done a utomatical ly by the expansion port control hardware. The external memo ry
should reside in the ei ght Least Si gnifi cant Bits (LSBs) of the external data bus, and the
packing (or unpacking for external write accesses) occurs in “Littl e Endian” order (that is,
the low byt e i s store d in the lowest of t he three memory l ocati ons and is transf erred fi rst ; the
middle byte i s stor ed/transferred next; and t he high byte is stored /t ransferred la st). When
this bit i s cleared, the expan sion port control lo gic assumes a 24-bit wide external memory.
Notes: 1. BPAC is used only for DMA accesses and not core accesses.
2. To ensure sequential external accesses, the DMA address should advance
three st eps at a tim e in two-dimens io nal mode with a row len gth of one and an
offset size of three. For detail s, refer to the Freescale applicat ion note,
APR23/D, Using the DSP56300 Direct Memory Acce ss Controller.
3. To prevent improper operati on, DMA address + 1 and DMA
address + 2 should not cross the AAR bank border s.
4. Arbit ration is not al lowed during the packing access (that is, the three
accesses are tr eated as one access with r espect to arbi tration , and the bus
mastershi p is not released during these accesses).
60 Reserved. Write to 0 for futur e com patibility.
5 BYEN 0 Bus Y Data Memory Enabl e
A read/wr it e control bit that enable s/disables the AA pin and log ic duri ng external Y data
space accesses. W hen set, BYEN enables the comparison of the external address to the
BAC bits during exter nal Y data space accesses. If BYEN is cleare d, no address
comparison is perfor me d.
4 BXEN 0 Bus X Data Memory Enabl e
A read/wr it e control bit that enable s/disables the AA pin and log ic duri ng external X data
space accesses. W hen set, BXEN enables the comparison of the external address to the
BAC bits during exter nal X data space accesses. If BXEN is cleare d, no address
comparison is perfor me d.
3 BPEN 0 Bus Program Memory Enable
A read/wr it e control bit that enab les/disabl es the AA/RAS pin and logic duri ng external
progra m space acc esse s. When set, BPEN enables t he compar ison of the exter nal addr ess
to the BAC bits dur ing external program space accesses. If BPEN is clear ed, no address
comparison is perfor me d.
2 BAAP 0 Bus Address Attr ibute Pol arity
A read/wr it e Bus Address Att ribute Polarit y (BAAP) control bit tha t defines whet her t he
AA/RAS signa l is active low or act ive high. When BAAP i s cleared, the AA/RAS signal is
acti ve low (useful for ena bli ng memor y modules or fo r DRAM Row Address St robe). If
BAAP is set, the appr opria te AA/RAS signal is active high (useful as an additional address
bit).
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number Bit Name Reset
Value Description
DSP56303 User’s Manual, Rev. 2
4-28 Freescale Semiconductor
Core Confi gurati on
4.7 D MA Con trol Registers 5–0 (DCR[5–0])
The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA operation
for each of their respective channels. All DCR bits are cleared during processor reset.
Figu re 4-9. DMA Control Register (DCR)
1–0 BAT 0 Bus Access Type
Read/write bit s that define the t ype of exter nal memory (DRAM or SRAM) to acces s for the
area def ined by the BAC[11–0] ,BYEN, BXEN, and BPEN bi ts. Th e encoding of BAT[1–0] is:
00 = Reserved
01 = SRAM access
10 = DRAM access
11 = Reserved
When the ext er nal acce ss type i s de fined a s a DRAM access ( BAT[ 1–0] = 10) , AA/RAS act s
as a Row Address Strobe (RAS) signal. Otherwise, it acts as an Address Attribute signal.
External accesses to the defa ult area alway s execute as if BAT[1–0] = 01 (that is, SRAM
access). I f Port A is used for external accesses, the BAT bits in the AAR3–0 regi sters must
be ini ti alized to the SRAM access type (that is, BAT = 01) or t o the DRAM access type (t hat
is BAT = 10). To ensure proper operati on of Port A, this initi alizat ion mu st occur even for an
AAR register that is not used duri ng any Port A access. Note that at reset, the BAT bits are
initialized to 00.
Table 4-11. DMA Control Register (DCR) Bit Definitions
Bit
Number Bit Name Reset
Value Description
23 DE 0 DMA Channel Enable
Enabl es the chan nel operati on. Set ting DE eit her tr iggers a singl e block DM A trans fer i n the
DMA transfer mode that uses DE as a trigger or enabl es a single-block, single-line, or
singl e-word DMA transfer in the transfer modes that us e a requesting devi ce as a trigger.
DE is c leared by the en d of DMA transf er in some of the t ransfer m odes def ined by the DTM
bits. If software explicitly clears DE duri ng a DMA ope rat ion, t he channel operati on stops
only after the current DMA t ransfer completes (t hat is, the curr ent word is stored into the
destination).
22 DIE 0 DMA Interrup t Enable
Gene rates a DMA interrupt at the end of a DMA block transfer after the counter is loaded
with its prel oaded value. A DMA interrupt is also generated when software explicitl y clears
DE duri ng a DMA operation. Once asser ted, a DMA interrupt request can be cleared only
by the service of a DMA interrupt r outine. To ensure that a new interrupt request is not
generated, clear DIE while the DMA inte rrupt is serviced and before a new DMA request i s
generated at the end of a DMA block transfer—that is, at the beginning of the DM A channel
int errupt serv ice routine. When DIE is cleared, t he DMA interrupt is disabled.
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number Bit Name Reset
Value Description
23 22 21 20 19 18 17 16 15 14 13 12
DE DIE DTM2 DTM1 DTM0 DPR1 DPR0 DCON DRS4 DRS3 DRS2 DRS1
11109876543210
DRS0 D3D DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DDS1 DDS0 DSS1 DSS0
DMA Control Registers 5–0 (DCR[5–0])
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-29
21–19 DTM 0 DMA Transfer Mode
Specify the oper ati ng m odes of the DMA channel, as follows:
DTM[2–0
]Trigger DE
Cleared
After Transfer Mode
000 request Yes Block Transfer—DE enabled and DM A request
initiated. The trans fer is comp let e when the counter
decrement s to z ero and the DMA cont roll er relo ads the
counter with the original value.
001 request Yes Word Tr ansfer— A word- by-word block transf er (lengt h
set by the count er) that is DE enabled. The transfer is
complet e whe n the c ount er decr ement s to zero an d t he
DMA control ler reloads the counter with the origi nal
value.
010 request Yes Line Tran sfer—A line by line block transf er (l ength set
by the counter) that is DE enabled. The transfer i s
complet e whe n the c ount er decr ement s to zero an d t he
DMA control ler reloads the counter with the origi nal
value.
011 DE Yes Block Tra nsfer—The DE-ini tiat ed transfer is comp lete
when the counter decrement s to zero and the DMA
controller reloads the counter with the original value.
100 request No Block Transfer—The transfer is enabled by DE and
initiated by the fir st DMA request. The transfer i s
completed when the counter decrements to zero and
reloads itself with the original value. The DE bit is not
cleared at the end of the block, so the DMA channel
waits f or a new requ est.
NOTE: The DMA End-of-Block-Transfer Interrup t
cannot be used in this m ode.
101 request No Word Transfer—The transfer is enabled by DE and
initia ted by every DMA request. When t he counter
decrements to zero, it i s reloaded wit h it s origi nal
value. The DE bit is not automatically cl eared, so the
DMA channel wait s for a new reque st.
NOTE: The DMA End-of-Block-Transfer Interrup t
cannot be used in this m ode.
110 Reserved
111 Reserved
Note: When DTM = 001 or 101, some per ipherals can gener ate a second DMA request whi le the DMA contr oller is sti ll
processing the first request (s ee the descript ion of the DRS bits).
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
DSP56303 User’s Manual, Rev. 2
4-30 Freescale Semiconductor
Core Confi gurati on
18–17 DPR 0 DMA Channel Prio ri ty
Defi ne the DMA channel pri ori ty relative to the other DMA channels and to the core priority
if an external bus access is requi red. For pending DMA transfers, the DMA controll er
com pares channel pr ior ity levels to determine whic h channel can activate the next wor d
transfer. This decision is required because all channel s use common resources, such as
the DMA address generation logi c, buses, and so fort h.
DPR Chann el Priori ty
00 Prio r ity l ev el 0 (lowes t)
01 Priority level 1
10 Priority level 2
11 Prior ity level 3 (hi ghest)
• If all or some channels have the same priorit y, then channels are acti vated in a
round-robin fa shion—tha t is , channel 0 is activated to transfer one word, followed by
channel 1, then channel 2, and so on.
• If channels have di ff erent prioriti es, the highest priority channel executes DMA transfers
and conti nues for i ts pending DMA transfers.
• If a lower-priority channel i s executi ng DM A transfers when a higher priorit y channel
receives a transfer request, the lower-priority channel finishes the curr ent word tr ansfer
and arbit rati on starts again.
• If some channels wi th the same priority are activ e in a roun d-robin fas hion and a new
higher-pri ori ty channel receives a transfer request, th e higher- priority channel is gr anted
transfer acces s after the cur rent word transfer is com plete. After t he higher-priori ty
channel trans fers a re comple te, the rou nd-robi n tr ansfer s co ntinue. The or der of t ransfer s
in the rou nd-robi n m ode m ay change, but the algorit hm rema ins the same.
• The DPR bit s also determine the DMA priority relative to the core pri ority for external bus
access. Arbi tratio n uses the curr ent acti ve DMA priority, the core prior it y defined by the
SR bits CP[1–0] , and t he cor e-DMA pri ority def ined by t he OMR bits CDP[ 1–0]. Priorit y of
core accesses to external memory is as follows:
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
DMA Control Registers 5–0 (DCR[5–0])
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-31
18–17
cont. DPR OMR - CDP[1–0] CP[1–0] Core Prio rity
00 00 0 (lowest )
00 01 1
00 10 2
00 11 3 (highest )
01 xx DMA accesses have higher priorit y than
core accesses
10 xx DMA accesses have the same priori ty as
core accesses
11 xx DMA accesses have lower priority than core
accesses
• If DMA priori ty > core priority (for exam ple, if CDP = 01, or CDP = 00 and
DPR > CP), the DMA performs the ext ernal bus access fi rst and t he core wait s for the
DMA channel to complete the current transfer.
• If DMA priori ty = core priority (for exam ple, if CDP = 10, or CDP = 00 and
DPR = CP), the core perfo rms all its external accesses first and then the DMA channel
performs its access.
• If DMA priori ty < core priority (for exam ple, if CDP=11, or CDP = 00 and
DPR < CP), the core perfo rms its exter nal accesses and the DMA waits for a free sl ot in
which the core does not require the external bus.
• In Dynami c Priority mode (CDP = 00), the DMA channel can be halted before executing
both the source and destination accesses if the core has higher priority . If another
higher-priority DMA channel requests access, the halted channel finishes its previous
access with a new higher priority before the new requesting DM A channel is servi ced.
16 DCON 0 DMA Conti nuous Mode Enable
Enables/disables DM A Conti nuous mode . When DCON is set , the channel enters the
Continuous Transfer mode and cannot be in terrupted duri ng a transfer by any other DMA
channel of equal priority. DMA transfers in the continuous mo de of operation can be
int errupt ed if a DMA channel of higher prior ity i s enable d after the cont inuous mode tr ansfer
starts. If the pri ority of the DMA transf er in cont inuous mode (that is, DCON = 1) is higher
than the core priority (CDP = 01, or CDP = 00 and DPR > CP), and if the DMA requires an
external access, t he DM A gets the exter nal bus and the core is not able t o use the external
bus in the next cycle after the DMA access even if the DMA does not need the bus in thi s
cycle. However, if a refresh cycle f rom the DRAM controller is requested, the refresh cycle
int errupts the DMA tr ansfer. When DCON is cleared, t he priority algorithm operates as for
the DPR bits.
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
DSP56303 User’s Manual, Rev. 2
4-32 Freescale Semiconductor
Core Confi gurati on
15–11 DRS 0 DMA Request Source
Encodes the source of DMA request s that trigger the DMA transfe rs. The DMA request
sources may be external devices requestin g service through the IRQA, IRQB, IR Q C and
IRQD pins, triggeri ng by transfers done from a DMA channel, or transfers from the i nternal
peripherals. All the request sources behave as edge-triggered synchronous inputs.
DRS[4–0] Requ esti ng Device
00000 External (IRQA pin)
00001 External (IRQB pin)
00010 External (IRQC pin)
00011 External (IRQD pin)
00100 Transf er done from channel 0
00101 Transf er done from channel 1
00110 Transf er done from channel 2
00111 Transf er done from channel 3
01000 Transf er done from channel 4
01001 Transf er done from channel 5
01010 ESSI0 rec eive data (RDF0 = 1)
01011 ESSI0 transmit data (TDE0 = 1)
01100 ESSI1 rec eive data (RDF1 = 1)
01101 ESSI1 transmit data (TDE1 = 1)
01110 SCI rec eive data (RDRF = 1)
01111 SCI transmit data ( TDRE = 1)
10000 Timer0 (TCF0 = 1)
10001 Timer1 (TCF1 = 1)
10010 Timer2 (TCF2 = 1)
10011 Host receive data full (HRDF = 1)
10100 Host transmit data empty (HTDE = 1)
10101–11111 Reserved
Peripheral requests 18–21 (DRS[4–0] = 111xx) can serve as fast request sources. Unlike a
regular per ipheral request in whi ch the peripheral can not generate a second request until
the fi rst one is serv ed, a fas t periphera l has a ful l duplex ha ndsha ke to the DMA, enabling a
max imum throughput of a trigger every two clock cycles. This mode is functi onal only i n the
Wor d Transfer mode (that is, DTM = 001 or 101). In the Fast Request mode, the DMA sets
an enable li ne to t he peripheral . If required, the peripheral c an send the DMA a one cyc le
tri ggering pulse. This pulse resets t he enable line. If t he DM A decides by the priority
algorithm th at this trigger will be served in the next cycle, the enable line is set agai n, even
before the corresponding register in the peripheral is accessed.
10 D3D 0 Three-Dimensional Mode
Indicates whet her a DMA channe l i s curr ently using three-dimensional (D3D = 1) or
non-three-dimensional (D3D = 0) addressing modes. The addressing modes are specifi ed
by the DAM bits.
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
Device Identification Register (IDR)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 4-33
4.8 Devi ce Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family members.
It specifies the derivative number and revision number of the device. This information is used in
testing or by software. Figure 4-10 shows the contents of the IDR. Revision numbers are
assigned as follows: $0 is revision 0, $1 is revision A, and so on.
.
Figu re 4-10 . Identification Register Configuration (Revision E)
9–4 DAM 0 DMA Address Mode
Defines the address generation mode for the DMA transfer. These bit s are encoded in two
different ways according to the D3D bit.
3–2 DDS[1–0] 0 DMA Destination Space
Specify t he me mo ry space referenced as a desti nation by the DMA.
Note: I n Cache m ode, a DMA to Progra m memory space has some li mitation s (as
descri bed in Chapter 3, Memory Configuration.
DDS1 DDS0 DMA Destination M emory Space
0 0 X Memory Space
0 1 Y Memory Space
1 0 P Memory Space
11Reserved
1–0 DSS 0 DMA Source Space
Specify t he me mo ry space refer enced as a source by the DMA.
Note: I n Cache m ode, a DMA to Progra m memory space has some li mitation s (as
descri bed in Chapter 3, Memory Configuration.
DSS1 DSS0 DMA Sour ce Memory Space
0 0 X Memory Space
0 1 Y Memory Space
1 0 P Memory Space
11Reserved
23 16 15 12 11 0
Reserved Revision Number Derivative Number
$00 $5 $303
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number Bit Name Reset
Value Description
DSP56303 User’s Manual, Rev. 2
4-34 Freescale Semiconductor
Core Confi gurati on
4.9 JTAG Identi fica tion (ID) Register
The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes the
component on a board according to the IEEE 1149.1 standard. Figure 4-11 shows the JTAG ID
register configuration. Version information corresponds to the revision number ($0 for revision 0,
$1 for revision A, and so forth).
I)
4.10 JTAG Boundary Scan Register (BSR)
The BSR in the DSP56303 JTAG implementation contains bits for all device signals, clock pins,
and their associated control signals. All bidirectional pins have a corresponding register bit in the
BSR for pin data and are controlled by an associated control bit in the BSR. For details on the
BSR, consult the DSP56300 Family Manual. For the latest description of the BSR contents by
available package type in boundary scan description language (BSDL), call your local Freescale
Semiconductor Sales Office or authorized distributor or visit the Freescale Semiconductor web
site listed on the back cover of this manual.
31 28 27 22 21 12 11 1 0
Version In formation Design Center
Number Sequence
Number Manufactur er
Identity 1
0101 000110 0000000011 00000001110 1
Figure 4-11. JTAG Identification Register Configuration (Revision E)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 5-1
Programming the Peripherals 5
When peripherals are programmed in a given application, a number of possible modes and
options are available for use. Chapters 6 through 9 describe in detail the possible modes and
configurations for peripheral registers and ports. This chapter presents general guidelines for
initializing the peripherals. These guidelines include a description of how the control registers are
mapped in the DSP56303, data transfer methods that are available when the various peripherals
are used, and information on General-Purpose Input/Output (GPIO) configuration.
5. 1 Peripheral Initial ization St e ps
Each peripheral has its own initialization process. However, all four peripherals share some
common steps, which follow:
1. Determine the Register values to be program med, using the following steps:
a. Find the peripheral register descriptions in the manual.
b. Choose the appropriate modes to configure for a given application.
c. Determine the bit settings for programming those modes.
2. Make sure the peripheral is in individual reset state or disabled.
Note: Peripheral registers should not be modified while the peripheral is active.
1. Configure the registers by writing the predetermined values from step 1 into the
appropriate register locations.
2. Enable the peripheral. Once the peripheral is enabled, it operates according the
programmed modes determined in step 1.
For detailed initialization procedures unique to each peripheral device, consult the initialization
section in the specific peripheral device chapter.
5.2 Mapping the Control Registers
The I/O peripherals are controlled through registers mapped to the top 128 words of X-data
memory ($FFFF80–$FFFFFF). Referred to as the internal I/O space, the control registers are
accessed by move (MOVE, MOVEP) instructions and bit-oriented instructions (BCHG, BCLR,
BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). The
DSP56303 User’s Manual, Rev. 2
5-2 Freescale Semiconductor
Programming the Peripherals
contents of the internal X I/O memory space are listed in Appendix B, Programming Reference,
Table B-2.
5.3 Reading Status Registers
Each peripheral has a read-only status register that indicate the state of the peripheral at a given
time. The HI08, ESSI, and SCI have dedicated status registers. The triple timer ha s status bits
embedded within a control/status register. Changes in the status bits can generate interrupt
conditions. For example, the HI08 has a host status register with two host flag bits that can be
encoded by the host to generate an interrupt in the DSP.
5.4 D ata Transfer Met hods
Peripheral I/O on the DSP56303 can be accomplished in three ways:
Polling
Interrupts
DMA
Figure 5-1. Memory Mapping of Peripherals Control Registers
X-Data Memory
Internal I/O
External
Internal
Reserved
External
Internal
X-Data RAM
2 K ( default)
$FFFFFF
$FFFF80
$FFF000
$FF0000
$000800
$000000
Peripherals Control Registers
Memory Space
Data Transfer Methods
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 5-3
5.4.1 Polling
Polling is the easiest method for data transfers. When polling is cho sen, the DSP56303 core
continuously checks a specified register flag waiting for an event to happen. One example would
be setting an overflow flag in one of the Timers. Once the event occurs, the DSP56303 is free to
continue with its next task. However, while it is waiting for the event to occur, the DSP56303
core is not executing any other code. Polling is the easiest transfer method since it does not
require register initialization, but it is also the least efficient use of the DSP core.
Each peripheral has its own set of flags which can be polled to determine when data is ready to be
transferred. For example, the ESSI control registers provide bits that tell the core when data is
ready to be transferred to or from the peripheral. The core polls these bits to determine when to
interact with the peripheral. Similar flags exist for each peripheral.
Example 5-1 shows software polling programmed in an application using the HI08.
Example 5-1. Software Polling
jclr#1,x:M_HSR,* ; loop if HSR[1]:HTDE=0
movey:(TBUFF_PTR)+,x1 ; move data to x1
In this example, the core waits until the Host Status Register (HSR) Host Transmit Data Empty
(HTDE) flag is set. When the flag is set, the core moves data from Y memory to the X1 register.
5.4.2 Interrupts
Interrupts are more efficient than polling, but interrupts also require additional register
initialization. Polling requires the core to remain busy checking a flag in a specified control
register and therefore does not allow the core to execute other code at the same time. For
interrupts, you can initialize the interrupt so it is triggered off one of the same flags that can also
be polled. Then the core does not have to continuously check a flag. Once the interrupt is
initialized and the flag is set, the core is notified to execute a data transfer. Until the flag is set, the
core can remain busy executing other sections of code.
When an interrupt occurs, the core execution flow jumps to the interrupt start address defined in
Table B-3 in Appendix B, Programming Reference. It executes code starting at the interrupt
address. If it is a short interrupt (that is, the service routine is two opcodes long), the code
automatically returns to the original program flow after executing two opcodes with no impact to
the pipeline. Otherwise, if a longer service routine is required the programmer can place a
jump-to-subroutine (JSR) instruction at the interrupt service address. In this case , the program
executes that service routine and continues un til a return-from-interrupt (RTI) instruction
executes. The execution flow then resumes from the position the program counter was in before
the interrupt was triggered.
DSP56303 User’s Manual, Rev. 2
5-4 Freescale Semiconductor
Programming the Peripherals
Configuring interrupts requires two steps:
1. Setting up the interrupt routine
a. The interrupt handler is located at the interrupt starting address.
b. The interrupt routines can be short (only two opcodes long) or long (more than two
opcodes and requiring a JSR instruction).
2. Enabling the interrupts
a. Set the corresponding bits in the applicable peripheral control register.
b. Enable peripheral interrupts in the Interrupt Priority Register (IPRP).
c. Enable global interrupts in the Mode Register (MR) portion of the Status Register
(SR).
Events that change bits in the peripheral control registers can then trigger the interru pt.
Depending on the peripheral, from two to six peripheral interrupt sources are available to the
programmer.
Example 5-2 shows a short interrupt programmed for the HI08. The main program enables the
Host Receive Interrupt in the Host Control Register (HCR). When the interrupt is triggered
during code execution, the core processing jumps to the Host Receive Interrupt routine location
at p:$60 and executes the code there. Since this is a short interrupt, the core returns to normal
code execution after executing the two move instructions, and an RTI instruction is not
necessary.
Example 5-2. Interrupts
bset#M_HRIE,x:M_HCR ; enable host receive interrupt
; Short Interrupt Routine
orgP:$60
movepx:M_HRX,x1 ; HI08 Receive Data Full interrupt
movex1,y:(r0)+
5.4.3 DMA
The Direct Memory Access (DMA) controller permits data transfers between internal/external
memory and/or internal/external I/O in any combination without the intervention of the
DSP56303 core. Dedicated DMA address and data buses and internal memory partitioning
ensure that a high level of isolation is achieved so the DMA operation does not interfere with the
core operation or slow it down. The DMA moves data to /from the peripheral transmit/receive
registers. The programmer can use the DMA control registers to configure sources and
destinations of data transfers. Depending on the peripheral, one to four peripheral request sources
are available. This is the most efficient method of data transfer available. Core intervention is not
required after the DMA channel is initialized.
Data Transfer Methods
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 5-5
Example 5-3 shows a DMA configuration for transferring data to the Host Transmit register of
the HI08.
Example 5-3. DMA Transfers
bclr#M_D1L0,x:M_IPRC ; disable DMA1 interrupts
bclr#M_D1L1,x:M_IPRC
movep#TBUFF_START,x:M_DSR1 ; DMA1 source is transmit buffer
movep#M_HTX,x:M_DDR1 ; DMA1 destination is HTX
movep#TBUFF_SIZE-1,x:M_DCO1; DMA1 count is the full buffer
movep#INIT_DCR1,x:M_DCR1 ; init. DMA1 control register
DMA requires more initialization code and consideration of DMA modes. However, it is the
most efficient use of core resources. Once these registers are programmed, you must enable the
DMA by triggering a DMA request off one of the peripheral control flags or enabling it in normal
program flow or an interrupt service routine.
5.4.4 Advantages and Disadvantages
Polling is the easiest method to implement, but it requires a large amount of D SP56303 core
processing power. The core cannot be involved in other processing activities while it is polling
receive and transmit ready bits. Interrupts require more code, but the core can process other
routines while waiting for data I/O. An interrupt is generated when data is ready to be transferred
to or from the peripheral device. DMA requires even less core intervention, and the setup code is
minimal, but the DMA channels must be available.
Note: Do not use interrupt requests and DMA requests simultaneously.
Table 5-1. DMA-Accessible Registers
Block Register DMA
Read Write
ESSI TX0 No Yes
TX1 No Yes
TX2 No Yes
RX Yes No
SCI SRX Yes No
STX No Yes
EFCOP FDIR No Yes
FDOR Yes No
HI08 HTX No Yes
HRX Yes No
Timer
DSP56303 User’s Manual, Rev. 2
5-6 Freescale Semiconductor
Programming the Peripherals
5.5 General-Purpose Input/O utput (GPIO)
The DSP56303 provides 34 bidirectional signals that can be configured as GPIO signals or as
peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are
GPIO by default after reset. The control register settings of the DSP56303 peripherals determine
whether these signals function as GPIO or as peripheral dedicated signals. This section describes
how signals can be used as GPIO.
Chapter 2, Signals/Connections details the special uses of the 34 bidirectional signals. These
signals fall into five groups and are controlled separately or as a group:
Port B: 16 GPIO signals (shared with the HI08 signals)
Port C: six GPIO signals (shared with the ESSI0 signals)
Port D: six GPIO signals (shared with the ESSI1 signals)
Port E: three GPIO signals (shared with the SCI signals)
Timers: three GPIO signals (shared with the triple timer signals)
5.5.1 Port B Signals and Registers
Each of the 16 Port B signals not used as an HI08 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port B: host control register (HCR), host port
GPIO data register (HDR), and host port GPIO direction register (HDDR). Chapter 6, Host
Interface (HI08), discusses these registers.
Figure 5-2. Port B Signals
DSP56303
Host Interface
(HI08) Port
Non-Multiplexed
Bus Multiplexed
Bus Port B GPIO
H[0–7] HAD[0–7] PB[0–7]
HA0 HAS/HAS PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
HA1
HA2
HCS/HCS
Singl e DS
HRW
HDS/HDS
Singl e HR
HREQ/HREQ
HACK/HACK
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
General-Purpose Input/ O utput (GPIO)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 5-7
5.5.2 Port C Signals and Registers
Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port C: Port C control register (PCRC), Port C
direction register (PRRC), and Port C data register (PDRC). Chapter 7, Enhanced Synchronous
Serial Interface (ESSI), discusses these registers.
Figu re 5-3. Port C Signals
5.5.3 Port D Signals and Registers
Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port D: Port D control register (PCRD), Port D
direction register (PRRD), and Port D data register (PDRD). Chapter 7, Enhanced Synchronous
Serial Interface (ESSI), discusses these registers.
5.5.4 Port E Signals and Registers
Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port E: Port E control register (P CRE), Port E
Figu re 5-4. Port D Signals
DSP56303
Enhanced Synchronous
Ser ia l In te r face P o rt 0
(ESSI0)
SC0[0–2]
SCK0
SRD0
STD0
Port C GPIO
PC[0–2]
PC3
PC4
PC5
DSP56303
Enhanced Synchronous
Serial Interface Port 1
(ESSI1)
SC1[0–2]
SCK1
SRD1
STD1
Port D GPIO
PD[0–2]
PD3
PD4
PD5
DSP56303 User’s Manual, Rev. 2
5-8 Freescale Semiconductor
Programming the Peripherals
direction register (PRRE), and Port E data register (PDRE). Chapter 8, Serial Communication
Interface (SCI), discusses these re gisters.
5.5.5 Triple Timer Signals and Registers
Each of the three triple timer interface signals (TIO[0–2]) not used as a timer signal can be
configured as a GPIO signal. Each signal is controlled by the appropriate timer control status
register (TCSR[0–2]). Chapter 9, Triple Timer Module, discusses these registers.
Figure 5-5. Port E Signals
Figure 5-6. Triple Timer Signals
DSP56303
Serial
Communications
Interface (S C I ) Po r t
RXD
TXD
SCLK
Port E GPIO
PE0
PE1
PE2
DSP56303
Timers TIO0
TIO1
TIO2
Timer GPIO
TIO0
TIO1
TIO2
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-1
Host Interface (HI08) 6
The host interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that can
connect directly to the data bus of a host processor. The HI08 supports a variety of buses and
provides glueless connection with a number of industry-standard microcomputers,
microprocessors, and DSPs. The HI08 signals not used to interface to the host can be configured
as GPIO signals, up to a total of 16.
6.1 Features
The HI08 host is a slave device that operates asynchronously to the DSP core and host clocks.
Thus, the HI08 peripheral has a host processor interface and a DSP core interface. This section
lists the features of the host processor and DSP core interfaces.
6.1.1 DSP Core Interface
Mapping: Registers are directly mapped into eight internal X data memory locations.
Data word: DSP56303 24-bit (native) data words are supported, as are 8-bit and 16-bit
words.
Handshaking protocols:
— Software polled
— Interrupt driven
— Core DMA accesses
Instructions:
— Memory-mapped registers allow the standard MOVE instruction to t r ansfer data
between the DSP56303 and external hosts.
— A special MOVEP instruction for I/O service capability using fast interrupts.
— Bit addressing instructions (for example, BCHG, BCLR, BSET, BTST, JCLR, JSCLR,
JSET, JSSET) simplify I/O service routines.
6.1.2 Host Processor Interface
Sixteen signals support non-multiplexed or multiplexed buses:
—H[0–7]/HAD[0–7] host data bus (H[0–7]) or host multiplexed address/data bus (HAD[0–7])
—HAS/HA0 address strobe (HAS) or host address line (HA0)
—HA8/HA1 host address line (HA8) or host address line (HA1)
—HA9/HA2 host address line (HA9) or host address line (HA2)
DSP56303 User’s Manual, Rev. 2
6-2 Freescale Semiconductor
Host Interface (H I0 8)
—HRW/HRD read/write select (HRW) or read strobe (HRD)
—HDS/HWR data strobe (HDS) or write strobe (HWR)
—HCS/HA10 host chip select ( HCS) or host address line (HA10)
—HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ)
—HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ)
Note: The signals in the above list that are shown as asserted low (for example, HRD) all have
programmable polarity. The default value following reset is shown in the above list.
Mapping:
— HI08 registers are mapped into eight consecutive locations in the host’s external bus
address space.
— The HI08 acts as a memory or I/O-mapped peripheral for microprocessors,
microcontrollers, and so forth.
Transfer modes:
— Mixed 8-bit, 16-bit, and 24-bit data transfers, DSP-to-host and host-to-DSP
— Host command
Handshaking protocols:
— Software polled
— Interrupt-driven (Interrupts are compatible with most processors, including the
MC68000, 8051, HC11, and Hitachi H8.)
Data word: 8 bits
Dedicated interrupts:
— Separate request lines for each interrupt source
— Special host commands force DSP core interrupts under host processor control. These
commands are useful for
• Real-time production diagnostics
• Creation of a debugging window for program development
• Host control proto cols
Interface capabilities:
— Glueless interface (no external logic required) to
•HC11
• Hitachi H8
• 8051 family
• Thomson P6 fam ily
— Minimal glue logic (pull-ups, pull-downs) required to interface to
•ISA bus
• Freescale 68K family
• Intel X86 family
Host Port Signal s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-3
6.2 Host Port Signa ls
The host port signals are discussed in Chapter 2, Signals/Connections. Each host port signal can
be programmed as a host port signal or as a GPIO signal, PB[0–15]. See Table 6-1 through
Table 6-3.
The HI08 port can operate in multiplexed or non-multiplexed mode. In multiplexed mode
(HPCR[11]:HMUX = 1), the lower eight address signals multiplex with the eight data lines. In
non-multiplexed mode (HPCR[11]:HMUX = 0), the HI08 requires a chip select signal and three
address lines to select one of the eight registers accessible to the host. Eight lines are used for
data. The HI08 port can also be programmed to use a single or dual read/write data strobe and
single or double host request.
Software and hardware resets clear all DSP-side control registers and configure the HI08 as
GPIO. To select GPIO functions, clear HPCR bits 6 through 1; to select other HI08 functions, set
those same bits. If the HI08 is in GPIO mode, the HDDR configures each corresponding signal in
the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is
set. For details, see Section 6.6. 3, Host Data Direction Register (HDDR), on page 6-14 and
Section 6.6.4, Host Data Register (HDR), on page 6-15.
Table 6-1. HI08 Signal Definitions for Operational Modes
HI08 Port Signal Multiplexed Address/Data Bus Mode Non-multiplexed Bus Mode GPIO Mode
HAD[0–7] HAD[0–7] H[0–7] PB[0–7]
HAS/HA0 HAS/HAS HA0 PB8
HA8/HA1 HA8 HA1 PB9
HA9/HA2 HA9 HA2 PB10
HCS/HA10 HA10 HCS/HCS PB13
Table 6-2. HI08 Data Strobe Signals
HI08 Port Signal Single Strobe Mode Dual Strobe Mode GPIO Mode
HRW/HRD HRW HRD/HRD PB11
HDS/HWR HDS/HDS HWR/HWR PB12
Table 6-3. HI08 Host Request Signals
HI08 Port Signal Si ngle Host Request Mode Double Host Request Mode GPI O Mode
HREQ/
HTRQ HREQ/HREQ HTRQ/HTRQ PB14
HACK/
HRRQ HACK/HACK HRRQ/HRRQ PB15
DSP56303 User’s Manual, Rev. 2
6-4 Freescale Semiconductor
Host Interface (H I0 8)
6.3 Overview
The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side register bank
is accessible only to the host, and the DSP-side register bank is accessible only to the DSP core.
For the host, the HI08 appears as eight byte-wide locations mapped in its external address space.
The DSP-side registers appear to the DSP core as six 24-bit registers mapped into internal I/O X
memory space and therefore accessible via standard DSP56300 instructions and addressing
modes.
Figure 6-1. HI08 Block Diagram
TXLTXMTXH
HPCR
Latch RXLIVRCVRICR
24
HDDRHCR HSR HDR
DSP Peripheral Data Bus
HOST Bus
RXM
HBAR
ISR
8
HRXHTX
Core DMA Data Bus
RXH
HCR = Host Control Register
HSR = Host Status Registe r
HPCR = Host Port Control Regi ster
HBAR = Host Base Addres s Register
HTX = Host Transmit Register
HRX = Host Receive Register
HDDR = Host Data Direction Register
HDR = Host Data Register
ICR = Interface Control Register
CVR = Command Vector Register
IVR = Interrupt Vector Register
RXH = Receive Regist er Hi gh
RXM = Receive Regi ster Midd le
RXL = Receive Regi ster Low
TXH = Transmit Register Hi gh
TXM = T ransmit Regist er Middle
TXL = Transmit Regist er Low
Address
Comparator 24
24242424242424242424
8 8 8 8 3 8 8 8 8 8 8
35
ISR = Inte rfac e S ta t us R egis ter
Host-Side Registers
DSP-Side Registers
Control Registe rs Data Registers
Control Register s Data Registers
DSP
Side
Hos
t
Side
Operation
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-5
In GPIO mode, two additional registers (HDDR and HDR) are related to the HI08 peripheral. The
separate receive and transmit data paths are double buffered for efficient, high speed
asynchronous transfers. The host-side transmit data path (host writes) is also the DSP-side
receive path; the host-side receive data path (host reads) is also the DSP-side transmit path. The
Receive (RXH:RXM:RXL) and Transmit Data Registers (TXH:TXM:TXL) use the same host
address. During host writes to these addresses, the data is transferred to the Transmit Data
Registers while reads are performed from the Receive Data Registers.
6.4 Operation
The HI08 is a slave-only device, so the host is the master of all bus transfers. In host-to-DSP
transfers, the host writes data to the Transmit Data Registers (TXH:TXM:TXL). In DSP-to-host
transfers the host reads data from the Receive Data Registers (RXH:RXM:RXL). The DSP side
has access only to the Host Receive Data Register (HRX) and the Host Transmit Data Register
(HTX). Data automatically moves between the host-side data registers and the DSP-side data
registers when it is available. This double-buffered mechanism allows for fast data transfers but
creates a “pipeline” that can either stall communication (if the pipeline is either full or empty) or
cause erroneous data transfers (new data to be overwritten or old data to be read twice). The HI08
port has several handshaking mechanisms to counter these buffering effects.
Suppose the host is writing several pieces of data to the HI08 port. The host first uses one of the
handshaking protocols to determine whether any data previously written to the Transmit Data
Registers (TXH:TXM:TXL) has successfully transferred to the DSP side. If the host-side
Transmit Data Registers (TXH:TXM:TXL) are empty, the host writes the data to these registers.
The transfer to the DSP-side Host Receive Data Register (HRX) occurs only if HRX is empty
(that is, the DSP has read it). The DSP core then uses an appropriate handshaking protocol to
move data from the HRX to the receiving buffer or register. Without handshaking, the host might
overwrite data not transferred to the DSP side or the DSP might receive stale data.
Similarly, when the host performs multiple reads from the HI08 port Receive Data Registers
(RXH:RXM:RXL), the DSP side uses an appropriate handshaking protocol to determine whether
any data previously written to the Host Transmit Register (HTX) has successfully transferred to
the host-side registers. If HTX is empty, the DSP writes the data to this register. Data transfers to
the host-side Receive Data Registers (RXH:RXM:RXL) occur only if they are empty (that is, the
host has read them). The host can then use any of the available handshaking protocols to
determine whether more data is ready to be read. The DSP56303 HI08 port offers the following
handshaking protocols for data transfers with the host:
Software polling
Interrupts
Core DMA access
Host requests
DSP56303 User’s Manual, Rev. 2
6-6 Freescale Semiconductor
Host Interface (H I0 8)
The choice of which protocol to use is based on such system constraints as the amount of data to
be transferred, the timing requirements for the transfer, and the availability of such resources as
processing bandwidth and DMA channels. All of these constraints are discussed in the following
sections. The transfers described here occur asynchronously between the host and the DSP; each
transferring data at its own pace. However, use of the appropriate handshaking protocol allows
data transfers to occur at optimum rates.
6.4.1 Software Polling
Software polling is the simplest data transfer method to use, but it demands the greatest amo unt
of the core’s processing power. Status bits are provided for the host or the DSP core to test and
determine if the data registers are empty or full. However, the DSP core cannot be involved in
other processing activities while it is polling these status bits.
On the DSP side, for transfers from the DSP to the host (host reads), the DSP core must
determine the state of Host Transmit Data register (HTX). In transfers fro m the host to the DSP
(host writes), the DSP side should determine the state of the Host Receive Data Register (HRX).
Thus, two bits are provided to the core for polling:
the Host Transmit Data Empty (HTDE) bit in the Host Status register (HSR[1]:HTDE)
the Host Receive Data Full (HRDF) bit in the Host Status register (HSR[0]:HRDF)
A similar mechanism is available on the host-side to determine the state of the Transmit Registers
(TXH:TXM:TXL) and Receive Registers (RXH:RHM:RHL). Two bits are provided to the host
for polling:
the Transmit Data Empty (TXDE) bit in the Interface Status Register (ISR[1]:TXDE)
the Receive Data Full (RXDF) bit in the Interface Status Register (ISR[0]:RXDF)
The HI08 also offers four general-purpose flags for communication between the host and the
DSP. The DSP-side uses the HSR Host Flag bits (HCR[4–3] = HF[3–2]) to pass
application-specific information to the host. The status of HF3–HF2 is reflected in the host-side
ISR Host Flag bits (ISR[4–3] = HF[3–2]). Similarly, the host side can use the ICR Host Flag bits
(ICR[4–3] = HF[1–0]) to pass application-specific information to the DSP. The status of HF[1–0]
is reflected in the DSP-side HSR Host Flag bits (HSR[4–3] = HF[1–0]).
6.4.2 Core Interrupts and Host Commands
The HI08 can request interrupt service from the DSP56303 core. The DSP56303 core interrupts
are internal and do not require the use of an external interrupt signal. When the appropriate
interrupt enable bit in the HCR is set, an interrupt condition caused by the host interface sets the
appropriate bit in the HSR, generating an interrupt request to the DSP56303 interrupt controller
(see Figure 6-2). The DSP56303 acknowledges interrupts by jumping to the appropriate interrupt
service routine. The following DSP core interrupts are possible from the HI08 peripheral:
Operation
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-7
Host command
Transmit data register empty
Receive data register full
These interrupts are maskable via the Host Receive Interrupt Enable bit (HCR[0] = HRIE), the
Host Transmit Interrupt Enable bit (HCR[1] = HTIE), and the Host Command Interrupt Enable
bit (HCR[2] = HCIE), respectively. Receive Data Full and Transmit Data Empty interrupts move
data to/from the HTX and HRX data registers. The DSP interrupt service routine must read or
write the appropriate HI08 data register (HRX or HTX) to clear the interrupt condition.
Host commands allow the host to issue command requests to the DSP by sele cting any of 128
DSP interrupt routines for execution. For example, the host may issue a command via the HI08
that sets up and enables a DMA transfer. The DSP56303 processor has reserved interrupt vector
addresses for application-specific service routines. However, this flexibility is independent of the
data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt
handler (for example, SSI, SCI, IRQx, and so on).
To enable Host Command interrupts, the HCR[2] = HCIE bit is set on the DSP side. The host
then uses the Command Vector Register (C VR) to start an interrupt routine. The host sets the
Host Command bit (CVR[7] = HC) to request the command interrupt and the seven Host Vector
bits CVR[6–0] = HV[6–0] to select the interrupt address to be used. When the DSP core
recognizes the host command interrupt, the address of the interrupt taken is 2xHV. For host
command interrupts, the interrupt acknowledge from the DSP56303 program controller clears the
pending interrupt condition.
Figure 6-2. HI08 Core Interrupt Operation
15
X:HCR
X:HSR
0
Enable
HF3 HF2 HCIE HTIE HRIE HCR
HF1 HF0 HCP HTDE HRDF HSR
Status
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
15 0
DSP56303 User’s Manual, Rev. 2
6-8 Freescale Semiconductor
Host Interface (H I0 8)
Note: When the DSP enters Stop mode, the HI08 pins are electrically disconnected
internally, thus disabling the HI08 until the core leaves Stop mode. Do not issue a
STOP command via the HI08 unless some other mechanism for exiting this mode is
provided.
6.4.3 Cor e DMA Access
The DSP56300 family Direct Memory Access (DMA) controller permits transfers between
internal or external memory and I/O without any core intervention. A DMA channel can be set up
to transfer data to/from the HTX and HRX data registers, freeing the core to use its processing
power on functions other than polling or interrupt routines for the HI08. DMA may well be the
best method to use for data transfers, but it requires that one of the six DMA channels be
available for use. Two HI08 DMA sources are possible, as Table 6-4 shows. Refer to the
DSP56300 Family Manual to learn about DMA accesses.
Note: DMA transfers do not access the host bus. The host must determine when data is
available in the host-side data registers usin g an appropriate polling m echanism.
6.4.4 Host Requests
A set of signal lines allow the HI08 to request service from the host. The request signal lines
normally connect to the host interrupt request pins (IRQx) and indicate to the host when the DSP
HI08 port requires service. The HI08 can be configured to use either a single Host Request
(HREQ) line for both receive and transmit requests or two signal lines, a Host Transmit Request
(HTRQ) and a Host Receive Request (HRRQ ), for each type of transfer.
Host requests are enabled on both the DSP-side and host-side. On the DSP side, the HPCR Host
Request Enable bit (HPCR[4] = HREN) is set to enable host requests. On the host side, clearing
the ICR Double Host Request bit (ICR[2] = HDRQ) configures the HI08 to use a single request
line (HREQ). Setting the ICR[2] = HDRQ bit enables both transmit and request lines to be used.
Further, the host uses the ICR Receive Request Enable bit (ICR[0] = RREQ) and the ICR
Transmit Request Enable bit (ICR[1] = TREQ) to enable receive and transmit reques ts,
Table 6-4. DMA Request Sources
Requesting Devi ce DCRx[15–11] = DRS[4– 0]
Host Rece ive Data Full (HRDF = 1) 10011
Host Tr ansmit Data Empty (HTDE = 1) 10100
Operation
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-9
respectively. When host requests are enabled, the host request pins operate as shown in Figure
6-3.
Table 6-5 shows the operation of the HREQ pin when a single request line is used. The host can
test these ICR bits to determine the interrupt source.
Table 6-6 shows the operation of the transmit request (HTRQ) and receive request (HRRQ) lines
with dual host requests enabled.
6.4.5 Endian Modes
The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows
the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian
mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4.
Figure 6-3. HI08 Host Request Str ucture
Tabl e 6-5. HREQ Pin Operation In Single Request Mode (ICR[2] = HDRQ = 0)
ICR[1 ] = TREQ ICR[0] = RREQ HREQ Pin
0 0 No interrupts
0 1 RXDF request enabled
1 0 TXDE request enabl ed
1 1 RXDF and TXDE request enabled
Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2] = HDRQ = 1)
ICR[1] = TREQ ICR[0] = RREQ HTRQ Pin HRRQ Pin
0 0 No interrupts No interrupt s
0 1 No interrupts RXDF request enabled
1 0 TXDE Reque st enabled No interrupts
1 1 TXDE Reque st enabled RXDF request enabled
$0 HF1 HF0 HLEND TREQ RREQ ICR
Enable
70
INIT 0 0
Status
70
$2 HF3 HF2 TRDY TXDE RXDF ISRHREQ 0 0
Host Request
Asserted HRRQ
HREQ
HTRQ
Host Reques
t
Signals
DSP56303 User’s Manual, Rev. 2
6-10 Freescale Semiconductor
Host Interface (H I0 8)
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three store
(or load) byte operations, ensuring that the data byte at host bus address $7 is written last since
this causes the transfer of the data to the DSP-side HRX. However, the host bus controller may be
sophisticated enough that the host can transfer all bytes in a single operation (instruction). For
example, in the PowerPC MPC860 processor, the General-Purpose Controller Module (GPCM)
in the memory controller can be programmed so that the host can execute a single read (load
word, LDW) or write (store word, STW) instruction to the HI08 port a nd cause four byte
transfers to occur on the host bus. The 32-bit datum transfer shown in Figure 6-4 has byte data xx
written to HI08 address $4, byte aa to address $5, byte bb to address $6 and byte cc to address $7
(this assumes the 24-bit datum is contained in the lower 24 bits of the host’s 32-bit data register
as shown).
A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing the Host
Little Endian bit (ICR[5] = HLEND). Big Endian mode is depicted in Figure 6-5.
Figu re 6-4. HI08 Read and Write Operations in Little Endian Mode
Figure 6-5. HI08 Read and Write Operations in Big Endian Mode
cc bb aa High Byte
Low Byte
Host bus address: $5 $6 $7
aa bb cc
HTX/HRX Bit Number: 23 0
DSP side
Host side
cc bb aa
(read/write last!)
xx
Host 32-bit
internal register
aa bb cc Low Byte
High Byte
Host bus address: $5 $6 $7
aa bb cc
HTX/HRX Register: 23 0
DSP side
Host side
aa bb cc
(read/write last!)
xx
Host 32-bit
internal register
Boot-up Usi ng the HI08 Host Port
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-11
6.5 B oot- up Using the HI08 Host Port
The DSP56300 core has eight bootstrap operating modes to start up after reset. As the processor
exits the Reset state the value at the external mode pins MODA/IRQA, MODB/IRQB, MODC/IRQC and
MODD/IRQD are loaded into the Chip Operating Mode bits (MA, MB, MC and MD) of the
Operating Mode Register (OMR). These bits determine the bootstrap operating mode. Modes C,
D, E and F use the HI08 host port to bootstrap the application code to the DSP. Table 6-7
describes these modes.
The bootstrap program is factory-programmed into an internal 192-word by 24-bit bootstrap
ROM at locations $FF0000–$FF00BF of P memory. This program can load program RAM
segment from the HI08 host port. When any of the modes in the preceding table are used, the core
begins executing the bootstrap program and configures the HI08 based on the OMR mode bits.
The bootstrap program then expects the following data sequence when the user program is
downloaded from the HI08:
1. Three bytes (least significant byte first) indicating the number of 24-bit program words
to be loaded.
2. Three bytes (least significant byte first) indicating the 24-bit starting address in
P-memory to load the user's program.
3. The user program (three bytes, least significant byte first, for each program word).
Once the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
6.6 DSP Core Programming Model
The DSP56300 core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in X data memory space. The DSP can use the HI08 as a normal memory-mapped
peripheral, employing either standard polled or interrupt-driven programming techniques.
Separate transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Direct memory mapping allows t he
DSP56303 core to communicate with the HI08 registers using standard instructions and
Table 6-7. HI08 Boot Modes
Mode MODD MODC MODB MODA HI 08 Bootstr ap Description
C1100ISA/DSP5630x mode
D1101HC11 non-multiplexed bus mode
E11108051 multiplexed bus mode
F1111MC68302 bus mode
DSP56303 User’s Manual, Rev. 2
6-12 Freescale Semiconductor
Host Interface (H I0 8)
addressing modes. In addition, the MOVEP instruction allows direct data transfers between
DSP56303 internal memory and the HI08 registers or vice versa.
There are two types of host processor registers, data and control, with eight registers in all. The
DSP core can access all eight registers, but the external host cannot. The following data registers
are 24-bit registers used for high-speed data transfers by the DSP core.
Host data receive register (HRX), on page 6-1 9
Host data transmit register (HTX), on page 6-19
The DSP-side control registers are 16-bit registers that control HI08 functionality:
Host control register (HCR), on page 6-12
Host status register (HSR), on page 6-13
Host GPIO data direction register (HDDR), on page 6-14
Host GPIO data register (HDR), on page 6-15
Host base address register (HBAR), on page 6-15
Host port control register (HPCR), on page 6-16
Both hardware and software resets disable the HI08. After a r eset, the HI08 signals are
configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left
floating).
6.6.1 Host Control Register (HCR)
This read/write register controls the HI08 interrupt operation. Initialization values for HCR bits
are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.
1514131211109876543210
HF3 HF2 HCIE HTIE HRIE
—Reserved bit; read as 0; write to 0 for future compatibilit y.
Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)
Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number Bit Name Rese t Valu e Descri pti on
15–5 0 Reserved. Write to 0 for future com patibility.
4–3 HF[3 –2] 0 Host Fl ags 2, 3
General- purpose flags for DSP-t o-host communicati on. The DSP core can
set or cle ar HF[ 3–2]. The val ues o f HF[3 –2] are ref lected in the interfac e
status register (ISR); that is, if they are modified by the DSP software, the
host pr ocessor can r ead the modified values by reading the I SR. These two
general-purpose flags can be used individuall y or as encoded pairs in a
simple DSP- to-host comm unicatio n protocol, implemented in bot h the DSP
and the host pr ocessor softwar e. The bi t val ue is indetermi nate after an
individual reset.
DSP Core Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-13
6.6.2 Host Status Register (HSR)
The HSR is a 16-bit read-only status register by which the DSP reads the HI08 status and flags.
The host processor cannot access it directly. The initialization values for the HSR bits are
discussed in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.
2 HCIE 0 Host Command Interrupt Enable
Generates a host command interrupt request if t he host comm and pending
(HCP) status bit in the HSR i s set. If HCIE is cleared, HCP interrupts are
disabl ed. The int errupt address i s determined by the host command vector
register (CVR).
NOTE: If more th an one inter rupt request sour ce is asserted and enabl ed
(for example , HRDF is set, HCP is set, HRIE is set, and HCIE is set), the
HI08 gener ates int errup t request s accord ing to pr iori ties sh own here. The bit
value is indeterminate afte r an ind ividual reset .
Priority Interrupt Source
Highest Host Co mman d (HCP = 1)
Transmit Data (HTDE = 1)
Lowest Receive Dat a (HRDF = 1)
1HTIE0Host Transmit I n terrupt Enabl e
Generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit i n the HSR is set. The HTDE bit is set when data is
transf erred from the HTX to the RXH, RXM, or RXL registers. If HTIE is
cleared, HTDE interrupts are disabled. The bit value is indeterminate after
an indiv idual r eset.
0 HRIE 0 Host Receive Inter rupt Enabl e
Generates a host re ceive data interrupt req uest if the host recei ve data ful l
(HRDF) bit in the host status regi ster (HSR, Bit 0) is set. The HRDF bit i s set
when data i s transferr ed to the HRX from the TXH, TXM , or TXL registers . I f
HRIE is cleared, HRDF int errupts are disa bled. The bit value is
indeterminate aft er an indivi dual reset.
1514131211109876543210
HF1 HF0 HCP HTDE HRDF
—Reserved bit; read as 0; write to 0 for future compatibilit y.
Figure 6-7. Host Status Register (HSR) (X:$FFFFC3)
Table 6-9. Host Status Register (HSR) Bit Definitions
Bit Number Bit Name Reset Value Descri pti on
15–5 0 Reserved. Write to 0 for future com patibility.
Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number Bit Name Rese t Valu e Descri pti on
DSP56303 User’s Manual, Rev. 2
6-14 Freescale Semiconductor
Host Interface (H I0 8)
6.6.3 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured as
GPIO. Even when the HI08 functions as the host interface, its unused signals can be configured
as GPIO signals. For information on the HI08 GPIO configuration options, see Section 6.2, Host
Port Signals, on page 6-3. If Bit DRxx is set, the corresponding HI08 signal is configured as an
output signal. If Bit DRxx is cleared, the corresponding HI08 signal is configured as an input
signal. Hardware and software reset clear the HDDR bits.
4–3 HF[1–0] 0 Host Flags 0, 1
General-purpose flags for host-to-DSP communication. These bits reflect
the stat us of host f lags HF[1–0] i n the ICR on the host side. These two
general-purpose flags can be used individuall y or as encoded pairs in a
simple host-to -DSP comm unication protocol, i m plemented in both th e
DSP and the host pro cessor sof tware.
2 HCP 0 Host Command Pending
Reflects the stat us of the CVR[HC] bit. When set , it indicates that a host
command in ter rupt is pending. HI08 har dware clears HC and HCP wh en
the DSP core ser vices the interrupt request. I f the host cl ears HC, HCP i s
also cleared.
1HTDE0Host Transmit Data Empty
Indic ates that the host transmit data registe r (HTX) i s em pty and can be
written by th e DSP core. HTDE is s et when the HTX regist er is transf erred
to the RXH:RXM:RXL regi sters. The host pro cessor can al so set HTDE
using th e ini tialize functio n. HTDE is cleared when the DSP cor e wri tes to
HTX.
0 HRDF 0 Host Receive Dat a Full
Indic ates that the host rec eive data register (HRX) contains data fr om the
host processor. HRDF is set when data is t ransferred from the
TXH:TXM:TXL regist ers to the HRX regi ster. The host processor can also
clear HRDF using the i nitialize function.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
Ta ble 6-9. Host Status Register (HSR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Descri pti on
DSP Core Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-15
6.6.4 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals configured as
GPIO signals. The functionality of Dxx depends on the corresponding HDDR bit (that is,
DRxx).The host processor can not access the Host Data Register (HDR)
6.6.5 Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the base
address as programmed in the Base Address Register. An internal chip select is generated if a
match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figur e 6-9. Host Data Register (HDR) (X:$FFFFC8)
Table 6-10. HDR and HDDR Functionality
HDDR HDR
DRxx Dxx
GPIO Signal1Non- GPIO Sig nal1
0 Read -onl y bit—The value read is the binary value of
the signal. The corresponding signal is configure d as
an input.
Read-only bit—Does not contain significant data.
1 Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven wit h the dat a wri tten to Dxx.
Read/write b it — Th e value written is the value read.
1. Defined by the sel ected configuration.
1514131211109876543210
BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3
—Reserved bit, read as 0, write to 0 for future compatibilit y.
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
Bit Number Bit Name Reset Value Descri pti on
15–8 0 Reserved. Write to 0 for future com patibility.
7–0 BA[10–3] $80 Base Address
Reflect the base address where the host-si de register s are mapped into
the bus address space.
DSP56303 User’s Manual, Rev. 2
6-16 Freescale Semiconductor
Host Interface (H I0 8)
6.6.6 Host Port Control Register (HPCR)
The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit
initialization values are discussed in Section 6.6.9, DSP-Side Registers After Re set, on page
6-20. Hardware and software reset clear the HPCR bits.
To assure proper operation of the DSP56303, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX,
HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. Similarly,
the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN,
HCSEN, HA9EN, and HA8EN should not be set when HEN is set nor at the time HEN is set.
Figu re 6-11 . Self Chip-Select Logic
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAP HRP HCSP HDDS HMUX HASP HDSP HROD HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
—Reserv ed bit , read as 0; writ e to 0 fo r future compatibility.
Figure 6-12. Host Port Cont rol Register (HPCR) (X :$FFFFC4)
Table 6-12. Host Port Control Register (HPCR) Bit Definitions
Bit Number Bit Name Reset Val ue Description
15 HAP 0 Host Acknowl edge Polarity
If HAP is clear ed, the host acknowle dge (HACK) signal is configured as an
active low input. The HI08 dr ives the contents of the IVR onto the host bus
when the HACK signal is l ow. If the HAP bit is set, the HACK si gnal is
configured as an activ e high input. The HI08 o utputs the contents of the IVR
when the HACK sign al i s high.
14 HRP 0 Host Request Polarity
Controls the polar ity of the host request signals. In single host request mode
(that is, when HDRQ i s cleared in the ICR) , i f HRP is cleared and host
reques ts are e nabled ( that i s, if HREN i s set and HEN is set ), the n the HREQ
signal i s an active low output. If HRP is set and host requests ar e enabled,
the HREQ signal is an active high output. In the double host request mode
(that is, when HDRQ i s set in the ICR), if HRP is cleared and host requests
are enabled (that is, if HREN is set and HEN is set), then the HTRQ and
HRRQ signal s are act ive low outputs. If HRP is set and host requests are
enabled, t he HTRQ and HRRQ signal s are act ive high out puts.
HAD[0–7]
Ch ip se le c t
Comparator
A[3–7]
8 bits
HAS
HA[8–10]
DSP Peripheral
Data Bus
Latch
Base
Address
Register
DSP Core Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-17
13 HCSP 0 Host Chip Select Polarity
If t he HCSP bit is cl eared, the host chip sele ct (HCS) signal is config ured as
an acti ve low input and the HI08 is selected when the HCS signal is low. If
the HCSP signa l i s set, HCS i s configur ed as an active hi gh input and the
HI08 i s selected when the HCS si gnal is high.
12 HDDS 0 Host Dual Data Strobe
If th e HDDS bit is cle ared, th e HI08 operates in singl e-strobe bus mode. In
this mod e, the bus has a single data str obe signal for both reads and writes.
If th e HDDS bit is set, the HI08 oper ates in dual strobe bus mo de. I n thi s
mode, the bus has two separate data strobes: one for data read s, t he other
for data writes. See Figure 6-13 on page -19 and Figure 6-14 on page -19
for details on dual and single str obe modes.
11 HMUX 0 Host Multiplexed Bus
If HMUX is set, t he HI08 oper ates in mul tipl ex mode, latching the lo wer
portion of a multiplexed address/data bus. In this mode the internal address
lin e values of t he host regi sters are taken from the int ernal l atch. If HMUX is
cleared, it indi cates that the HI08 is connected to a non- m ult iplexed type of
bus. The values of the address lines are then taken fr om the HI08-dedi cated
address signals.
10 HASP 0 Host Address Strobe Polarity
If HASP is clear ed, the host address strobe (HAS) signal i s an activ e low
input, and the addr ess on the host address/data bus is sampled when the
HAS signal is l ow. I f HASP is set, HAS is an acti ve-high addr ess strobe
input, and t he address on the host address or data bus is sampled when the
HAS signal is hi gh.
9 HDSP 0 Host Data Strobe Pol ari ty
If HDSP is cleared, the data strobe signals are conf igured as active low
inputs, and data is transferred when the data str obe is low. If HDSP i s set,
the data str obe signals are conf igured as active high inputs, and dat a is
transferr ed when the data strobe is high. The data str obe signals are either
HDS by itself or both HRD and HWR t ogether.
8 HROD 0 Host Request Open Drai n
Controls the output drive of the host request si gnals. In the single host
request mode (that is, when HDRQ is cleared in ICR), if HROD is cleared
and host requests are enabled ( that is, if HREN is set and HEN is set in the
host por t contr ol registe r (HPCR)), t hen the HREQ signal i s always driven by
the HI08. If HROD is set and hos t requests ar e enabled, th e HREQ signal i s
an open drain output . In th e double host request mode (t hat is, when HDRQ
is set in the ICR), if HRO D is c leared and host request s are enabled (th at i s,
if HREN is set and HEN is set in the HPCR), then the HTRQ and HRRQ
signa ls are al ways driv en. If HROD is set and host request s are ena bled, the
HTRQ and HRRQ signals ar e open drain outputs.
70 Reserved. Write to 0 for fu ture compatibil ity.
6HEN0Host Enabl e
If HEN is set, the HI08 operat es as the host i nterface. If HEN is cleared, the
HI08 is not active, and all the HI0 8 signals are conf igured as GPIO signals
according to the value of the HDDR and HDR.
Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued)
Bit Number Bit Name Reset Val ue Description
DSP56303 User’s Manual, Rev. 2
6-18 Freescale Semiconductor
Host Interface (H I0 8)
5 HAEN 0 Host Acknowl edge Enable
Contro ls the HACK signal . In the si ngle h ost request mode (HDRQ is c leared
in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as
the host acknowledge (HACK) input. If HAEN or HREN is cleared,
HACK/HRRQ is conf igured as a GPIO signal according to the value of the
HDDR and HDR. I n the double host reque st mode (HDRQ is set in the ICR),
HAEN is ignored.
4 HREN 0 Host Request Enable
Contro ls the h ost requ est sig nals. If HREN is se t and the HI08 i s in the singl e
host request mode (t hat is, if HDRQ i s cleared in the host int erface control
register (I CR)), then HREQ /HTRQ is confi gured as the host request (HREQ)
output. If HREN is c leared, HREQ/HTRQ and HACK/HRRQ are configured
as GPIO signals according to the value of the HDDR and HDR.
If HREN is set in th e double host request mode (that is, if HDRQ is set in the
ICR), HREQ/HTRQ i s conf igured as the ho st trans mit r equest (HTRQ) ou tpu t
and HACK/HRRQ as the host receive request (HR RQ) output. I f HREN is
cleared, HREQ/HTRQ and HACK/HRRQ are c onfigured as G PIO signals
according to the value of the HDDR and HDR.
3 HCSEN 0 Host Chip Select Enable
If the HCSEN bit is set, HCS/HA10 is a host chip select (HCS) in the
non-mul tipl exe d bus mode (t hat i s, when HMUX is cl ear ed) and hos t addr ess
line 10 (HA10) in the multi plexed bus mode (that is, when HMUX is set). If
this bit is cl eared, HCS/HA10 i s co nfigur ed as a GPIO si gna l accor ding t o the
value of the HDDR and HDR .
2 HA9EN 0 Host Address Line 9 Enable
If HA9EN is set and th e HI08 i s in mul ti plexed bus mode, th en HA9/HA2 i s
host address l ine 9 (HA9). If t his bit is cleare d and the HI08 i s in multiplexed
bus mode , th en HA9/HA2 is config ured as a GPIO signal according to the
value of the HDDR and HDR .
NOTE: HA9EN is ignored when the HI08 is not in the multiplexed bus mode
(that is, when HMUX is cleared).
1 HA8EN 0 Host Address Line 8 Enable
If HA8EN is set and th e HI08 i s in mul ti plexed bus mode, th en HA8/A1 is
host address l ine 8 (HA8). If t his bit is cleare d and the HI08 i s in multiplexed
bus mode, then HA8/HA1 is a GPIO signal according to the value of the
HDDR and HDR .
NOTE: HA8EN is ignored when the HI08 is not in the multiplexed bus mode
(that is, when HMUX is cleared).
0HGEN0Hos t G P IO P o rt En a b le
Enables/disables si gnals configure d a s GPIO . If this bit is cleared, si gnals
configured as GPIO are disconnected: out puts are high impedance, i nputs
are electrically disconnected. Signal s configured as HI08 are not affecte d by
the val ue of HGEN.
Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued)
Bit Number Bit Name Reset Val ue Description
DSP Core Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-19
6.6.7 Host Transmit (HTX) Register
The HTX register is used in DSP-to-host data transfers. The DSP56303 views it as a 24-bit
write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host transfer
data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register are transferred
as 24-bit data to the Receive Data Registers (RXH:RXM:RXL) when both HSR[HTDE] and
receive data full (ISR[RXDF]) on the host-side bits are cleared. This transfer operation sets the
ISR[RXDF] and HSR[HTDE] bits. The DSP56303 can set the HCR[HTIE] bit to cause a host
transmit data interrupt when HSR[HTDE] is set. To prevent the previous data from being
overwritten, the DSP56303 should never write to the HTX when HSR[HTDE] is cleared.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of the status bits
within the next two cycles, the bit does not reflect its current status. For details, see
Section 5.4.1, Polling, on page 1-3.
6.6.8 Host Receive (HRX) Register
The HRX register is used in host-to-DSP data transfers. The DSP56303 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit data
Figu re 6-13 . Si ngle-Strobe Mode
Figure 6-14. Dual-Strobe Mode
HRW
HDS
In a single -strobe mode, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write)
signal specifies the direction of the access .
Data
HWR
Data
HRD
In dual-strobe mode, separate HRD a nd HWR signals specify the access as a read or wri te
access, respectively.
Read Dat a Out
Read Cycle
Write Cycl e
Wr i t e Data In
DSP56303 User’s Manual, Rev. 2
6-20 Freescale Semiconductor
Host Interface (H I0 8)
registers (TXH:TXM:TXL on the host side) when both the transmit data register empty
(ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on the DSP side are
cleared. The transfer operation sets both ISR[TXDE] and HSR[HRDF]. When the HSR[HRDF]
is set, the HRX register contains valid data. The DSP56303 can set the HCR[HRIE] to cause a
host receive data interrupt when HSR[HRDF] is set. When the DSP56303 reads the HRX
register, the HSR[HRDF] bit is cleared.
Note: The DSP56303 should never try to read the HRX register if the HSR[HRDF] bit is
already cleared.
6.6. 9 D SP -Sid e R eg ist ers A ft er Res et
Table 6-13 shows the results of the four reset types on the bits in each of the HI08 registers
accessible to the DSP56303. The hardware reset (HW) is caused by the RESET signal. The
software reset (SW) is caused by execution of the RESET instruction. The individual reset (IR)
occurs when HPCR[HEN] is cleared. The stop reset (ST) occurs when th e STOP instruction
executes.
6.7 Host Programmer Model
The HI08 provides a simple, high-speed interface to a host processor. To the host bus, the HI08
appears to be eight byte-wide regi sters. Separate transmit and receive data paths are
double-buffered to allow the DSP core and host processor to transfer data efficiently a t high
speed. The host can access the HI08 asynchronously using polling techniques or interrupt-based
Table 6-13. DSP-Side Registers After Reset
Register
Name Register
Data
Reset Type
HW
Reset SW
Reset IR
Reset ST
Reset
HCR All bit s 0 0 — —
HPCR All bits 0 0 — —
HSR HF[1–0] 0 0 — —
HCP0000
HTDE1111
HRDF 0 0 0 0
HBAR BA[10–3] $80 $80 — —
HDDR DR[15–0] 0 0 — —
HDR D[15–0] — — — —
HRX HRX [23–0] empty empty empty empty
HTX HTX [23–0] empty e mp ty empty empty
Note: A l ong dash (—) denotes that th e bit value is not aff ected by the specif ied reset .
Host Programmer Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-21
techniques. The HI08 appears to the host processor as a memory-mapped peripheral o ccupying
eight bytes in the host processor address space. (See Table 6-14.)
The eight HI08 registers include the following:
A control register (ICR), on page 6-22
A status register (ISR), on page 6-24
Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), on page 6-26
Two vector registers (CVR and IVR), on page 6-24 and page 6-26
To transfer data between itself and the HI08, the host processor bus performs the following steps:
1. Asserts the HI08 address and strobes to select the register to be read or written. (Chip
select in non-multiplexed mode, the address strobe in multiplexed mode.)
2. Selects the direction of the data transfer. If it is writing, the host processor places the
data on the bus. Otherwise, the HI08 places the data on the bus.
3. Strobes the data transfer.
Host processors can use standard host processor instructions (for example, byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are aligned so that
8-bit host processors can use 8-, 16-, or 24-bit load and store instructions for data transfers. The
HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or interrupt-driven
data transfers with the host processor. Because of the speed of the DSP56303 interrupt response,
most host microprocessors can load or store data at their maximum programmed I/O instruction
rate without testing the handshake flags for each transfer. If full handshake is not needed, the host
processor can treat the DSP56303 as a fast device, and data can be transferred between the host
processor and the DSP56303 at the fastest data rate of the host process or.
One of the most innovative features of the host interface is the host command feature. With this
feature, the host processor can issue vectored interrupt requests to the DSP56303. The host can
select any of 128 DSP interrupt routines for execution by writing a vector address register in the
HI08. This flexibility allows the host processor to execute up to 128 pre-program med functions
inside the DSP56303. For example, the DSP56303 host interrupts allow the host processor to
read or write DSP registers (X, Y, or program memory locations), force interrupt handlers (for
example, ESSI, SCI, IRQA, IRQB interrupt routines), and perform control or debugging
operations.
Note: When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the HI08
configuration remains unchanged in Stop mode, the core cannot be restarted via the
HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you
provide some other mechanism to exit stop mode.
DSP56303 User’s Manual, Rev. 2
6-22 Freescale Semiconductor
Host Interface (H I0 8)
6.7.1 Interface Control Register (ICR)
The ICR is an 8-bit read/write control register by which the host processor controls the HI08
interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register, which
allows the use of bit manipula tion instructions on control register bits. Hardware and software
reset clear the ICR bits.
Table 6-14. Host-Side Register Map
Host Address Big Endian HLEND = 0 Little Endian HLEND = 1 Register Name
0 ICR ICR I nterface Control
1 CVR CVR Command Vect or
2 I SR ISR Interface Status
3 I VR IVR Interrupt Vect or
4 00000000 00000000 Unused
5RXH/TXHRXL/TXLReceive/ Transmit
Data
6RXM/TXMRXM/TXM
7 RXL/TXL RXH/TXH
76543210
INIT HLEND HF1 HF0 HDRQ TREQ RREQ
—Reserv ed bit ; read as 0; writ e to 0 for future compatibility .
Figure 6-15. Interface Control Register (ICR)
Tabl e 6-15. Interface Control Register (ICR) Bit Definitions
Bit Number Bit Name Reset Value Descri ption
7INIT0Initialize
The host processor uses INIT to force initialization of the HI08 hardware.
During ini tialization, the HI08 t ransmit and receive control bits are configured.
Use of the INIT bit to initialize t he HI08 hardware depends on the software
design of t he int erface. The type of initialization when the INIT bit is set
depends on the state of TREQ and RREQ The INIT command, wh ich is local
to t he HI08, configures the HI08 into the desired data transfer mode. W hen
the host set s the INIT bit, the HI08 hardware executes the INI T command.
The interfac e hardware clears the INIT bi t after the command executes.
TREQ RREQ After INIT Execution Transfer Di rection
0 0 INIT = 0 None
0 1 INIT = 0;
RXDF = 0; HTDE = 1 DSP to host
1 0 INIT = 0;
TXDE = 1; HRDF = 0 Host to DSP
1 1 INIT = 0;
RXDF = 0; HTDE = 1;
TXDE = 1; HRDF = 0
Ho s t to /f ro m D S P
Host Programmer Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-23
60 Reserved. Write to 0 for future compatibility.
5HLEND0Host Little Endian
If the HLEND bi t is cleared, the host can access the HI08 in Big-Endian byt e
order. If set, the host can access the HI08 in Little-Endian byte order. If the
HLEND bit is cleared the RXH/TX H regi ster i s loc ated at addr ess $5, the
RXM/TXM regi ster at $6, and the RXL/TXL r egister at $7. I f t he HLEND bit is
set, the RXH/TXH register is located at address $7, t he RXM /TXM regist er at
$6, and the RXL/TXL regi ster at $5.
4HF10Host Flag 1
A general-purpose flag for hos t-to-DSP communication. The host processor
can set or cl ear HF1, and the DSP56303 can not change it. HF1 is reflected
in th e HSR on the DSP side of the HI08 .
3HF00Host Flag 0
A general-purpose flag for hos t-to-DSP communication. The host processor
can set or clear HF0, and the DSP5630 3 cannot chan ge it. HF0 i s reflect ed i n
the HSR on the DSP side of the HI08.
2 HDRQ 0 Double Host Request
If cleared, the HDRQ bit confi gures HREQ/HTRQ and HACK/HRRQ as
HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is configured
as HTRQ, and HACK/HRRQ i s configured as HRRQ.
1TREQ0Transmit Request Enable
Enabl es hos t reques ts via the hos t reques t (HREQ o r HTRQ) signal whe n the
transmit data register empty (TXDE) stat us bit in the ISR is set. If TREQ i s
cleared, TXDE interrupts are disabled. I f TREQ and TXDE are set , the host
request signal is asserted.
TREQ and RREQ modes ( HDRQ = 0)
TREQ RREQ HREQ Signal
0 0 No interrupts (polling)
0 1 RXDF request (interrupt)
1 0 TXDE request (interr upt)
1 1 RXDF and TXDE request (inter rupts)
TREQ and RREQ modes ( HDRQ = 1)
TREQ RREQ HTRQ Signal HRRQ Signal
0 0 No interrupts (poll ing) No inte rrupts
(polling)
0 1 No interrupts (polling) RXDF request
(interrupt)
1 0 TXDE request
(interrupt) No interr upts
(polling)
1 1 TXDE request
(interrupt) RXDF request
(interrupt)
0 RREQ 0 Receive Request Enable
Contr ols t he HREQ signal for host r eceive dat a tra nsfers . RREQ enables host
requests via t he host request (HREQ or HRRQ) sign al when the receive dat a
register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF
interrupts are disabled. If RREQ and RXDF are set, the host r equest signal
(HREQ or HRRQ) is asserted.
Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Descri ption
DSP56303 User’s Manual, Rev. 2
6-24 Freescale Semiconductor
Host Interface (H I0 8)
6.7.2 Command Vector Register (CVR)
The host processor uses the CVR, an 8-bit read/write reg ister, to cause the DSP56303 to execute
an interrupt. The host command feature is independent of any of the data transfer mechanisms in
the HI08. It causes execution of any of the 128 possible interrupt routines in the DSP core.
Hardware, software, individual, and stop resets clear the CVR bits.
6.7.3 Interface Status Register (ISR)
The host processor uses the ISR, an 8-bit read-only status register, to interrogate the HI08 status
and flags. The DSP core cannot address the ISR.
76543210
HC HV6 HV5 HV4 HV3 HV2 HV1 HV0
Figure 6-16. Command Vector Register (CVR)
Table 6-16. Command Vector Register (CVR) Bit Definitions
Bit Number Bi t Name Reset Value Description
7HC0Host Command
The host processor uses the HC bit to handshake the execution of host
com ma nd int errupts. Normally, the host processor sets HC t o request a
host command i nterr upt fr om the DSP56303. When the DSP56303
acknowledges the host command int errupt, HI0 8 hardware clear s the
HC bit . The host processor can r ead the state of HC to deter mine when
the host command has been accepted. After settin g HC, the hos t must
not wr ite t o the CVR again un til the HI08 har dware cl ears t he HC. Set ting
the HC bit causes host command pending (HCP) to be set in the HSR.
The host can write to the HC and HV bits in the same write cycle.
6–0 HV[6–0] $32 Host Vector
Selec t the host comman d inte rrupt address fo r use by t he host command
interrupt logic. When the DSP interrupt contr ol l ogic recogni zes the host
comm and interrupt, the address of the interrupt routine taken is 2 × HV.
The host can write HC and HV in the same write cycle.
The h ost processor can select any of th e 128 possible interrupt routine
starting add resses in the DSP by writing the int errupt rou ti ne address
divided by 2 into the HV bits. This means that the host processor can
force any interrupt handle r (ESSI, SCI, IRQA, IRQB , and so forth) and
can use any reserved or otherwise unused addresses (if have been
pre-programmed in the DSP). HV is set to $32 (vector location $064) by
hardware, sof tware, individual, and st op resets.
76543210
HREQ HF3 HF2 TRDY TXDE RXDF
—Reserv ed bit ; read as 0; writ e to 0 for future compatibility .
Figure 6-17. Interface Status Register (ISR)
Host Programmer Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-25
Tabl e 6-17. Interface Status Register (ISR) Bit Definitions
Bit Number Bi t Name Reset Value Description
7 HREQ 0 (Hardware
and Software
reset)
1 (Indi vidual
reset and
TRE Q is s e t)
1 (St op r eset
and TREQ is
set)
Host Request
If HDRQ is set, the HREQ bi t indicat es the status o f the externa l transmit
and receiv e request out put sig nals (HTRQ and HRRQ). If HDRQ is
cleared, HREQ indicates the stat us of the ext ernal host request output
signal (HREQ). The HREQ bit i s set from either or both of t wo
conditi ons— th e receive byte r egisters are full or the transmit byte
registers are em pty. These condi tions are indi cated by status bit s: ISR
RXDF indi cates that the rece ive byte regi sters are full , and ISR TXDE
indi cates that the transm it byte regi sters ar e emp ty. If the interr upt
sourc e is e nabl ed by t he a ssociat ed req uest ena ble bit in th e ICR, HREQ
is set if one or more of the two enabled inter rupt sour ces is set.
HDRQ HREQ Effect
00
HREQ is clear ed; no host processor
interrupts are requested.
01
HREQ is set; an inter rupt i s requested.
10
HTRQ and HRRQ are cleared, no host
processor i nterrupts are re quested.
11
HTRQ or HRRQ are set; an int errupt is
requested.
6–5 0 Reserv ed. Write to 0 for f uture compatibility.
4HF30Host Flag 3
Indi cates the sta te of HF3 in the HCR on the DSP side. HF3 can be
changed only by the DSP56303. Hardware and software reset clear
HF3.
3HF20Host Flag 2
Indi cates the sta te of HF2 in the HCR on the DSP side. HF2 can be
changed only by the DSP56303. Hardware and software reset clear
HF2.
2 TRDY 1 Tr ansm itt er Ready
Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY
is set , the data that the host process or writes to TXH:TXM:TXL is
imm ediately transferr ed to t he DS P side of the HI08. This feature has
many applications . For example, i f the host processor issues a host
com ma nd that causes the DSP56303 to re ad the HRX, the host
processor can be guaranteed that t he data it just transferr ed to the HI08
is t hat being recei ved by the DSP 56303. Hardware, soft ware, i ndividual ,
and stop reset s all set TRDY.
CAUTION:
TRDY = TXDE and HRDF
1TXDE1Transmi t Data Register Empty
Indicates that the transmit byte regist ers (TXH:TXM:TXL) are empty and
can be written by t he host processor. TXDE is set when t he contents of
the tr ansmit byte r egisters ar e tr ansferred to the HRX regist er. TXDE is
clea red when the transm it regis ter (TXL or TXH accordi ng to HLEND bit)
is writt en by the host pr ocessor . The host proce ssor can set TXDE usi ng
the initiali ze function. TXDE can assert the external HTRQ signal if the
TREQ bit i s set. Regardless of whether the TXDE interrupt i s enabl ed,
TXDE in dicate s whether t he TX re giste rs are fu ll an d data c an be latc hed
in (so that polling techniques may be used by the host pr ocessor).
Hardware, soft ware, individual, and stop resets all set TXDE.
DSP56303 User’s Manual, Rev. 2
6-26 Freescale Semiconductor
Host Interface (H I0 8)
6.7.4 Interrupt Vector Register (IVR)
The IVR is an 8-bit read/write register that typically contains the interrupt vector number used
with MC68000 family processor vectored interrupts. Only the host processor can read and write
this register. The contents of the IVR are placed on the host data bus, H[7–0], when both the
HREQ and HACK signals are asserted. The contents of this register are initialized to $0F by a
hardware or software reset. This value corresponds to the uninitialized interrupt vector in the
MC68000 family.
6.7.5 Receive Data Registers (RXH:RXM:RXL)
The host processor views the receive byte registers as three 8-bit read-only registers: the receive
high register (RXH), the receive middle register (RXM), and the receive low register (RXL).
They receive data from the high, middle, and low bytes, respectively, of the HTX register and are
selected by the external host address inputs (HA[2–0]) during a host processor read operation.
The memory address of the receive byte registers are set by ICR[HLEND]. If ICR[HLEND] is
set, the RXH is located at address $7, RXM at $6, and RXL at $5. If ICR[HLEND] is cleared, the
RXH is located at address $5, RXM at $6, and RXL at $7.
When data is transferred from the HTX register to the receive byte register at host address $7, the
ISR Receive Data Register Full (RXDF) bit is set. The host processor can program the RREQ bit
to assert the external HREQ signal when ISR[RXDF] is set. This indicates that the HI08 has a full
word (either 8, 16, or 24 bits) for the host processor. The host processor can program the RREQ
bit to assert the external HREQ signal when ISR[RXDF] is set. Assertion of the HREQ signal
informs the host processor that the receive byte registers have data to be read. When the host
reads the receive byte register at host address $7, the ISR[RXDF] bit is cleared.
0RXDF0Receive Data Register Full
Indicates t hat the rec eive byte r egisters (RXH:RXM: RXL) contai n data
from the DSP56303 to be read by the host proc essor. RXDF is s et when
the HTX is transferr ed to the receive byte regist ers. RXDF is cleared
when the host pro cessor reads the rece ive data re gister (RXL or RXH
according to HLEND bit). The host processor can clear RXDF using the
ini ti alize function. RXDF can assert t he external HREQ sig nal if the
RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indi cates whether the RX regist ers are full and data can be
latched out (so that the host processor can use polling techniques).
76543210
IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0
Figure 6-18. Interrupt Vector Register (IVR)
Table 6-17. Interface Status Register (ISR) Bit Definitions (Continued)
Bit Number Bi t Name Reset Value Description
Host Programmer Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-27
Note: The external host should never read the RXH:RXM:RXL registers if the ISR[RXDF]
bit is cleared.
6.7.6 Transmit Data Reg isters (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit write-only registers. These
registers are the transmit high register (TXH), the transmit middle register (TXM), and the
transmit low register (TXL). These registers send data to the high, middle, and low bytes,
respectively, of the HRX register and are selected by the external host address inputs, HA[2–0],
during a host processor write operation.
If ICR[HLEND] is set, the TXH register is located at address $7, the TXM register at $6, and the
TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is located at address
$5, the TXM register at $6, and the TXL register at $7.
Data can be written into the transmit byte registers when the ISR transmit data register empty
(TXDE) bit is set. The host processor can program the ICR[TREQ] bit to assert the external
HREQ/HTRQ signal when ISR[TXDE] is set. This informs the host processor that the trans mit
byte registers are empty. Writing to the data register at host address $7 clears the ISR[TXDE] bit.
The contents of the transmit byte registers are transferred as 24-bit data to the HRX register when
both ISR[TXDE] and HSR[HRDF] are cleared. This transfer operation sets HSR[TXDE] and
HSR[HRDF]. The external host should never write to the TXH:TXM:TXL registers if the
ISR[TXDE] bit is cleared.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit will not reflect its current status. For details, see
Section 5.4.1, Polling, on page 1-3.
6.7.7 Host-Side Registers After Reset
Table 6-18 shows the result of the four kinds of reset on bits in each of the HI08 registers seen by
the host processor. To cause a hardware reset, assert the RESET signal. To cause a software reset,
execute the RESET instruction. To reset the HEN bit individually, clear the HPCR[HEN] bit. To
cause a stop reset, execute the STOP instruction.
Table 6-18. Host-Side Registers After Reset
Register
Name Register
Data
Reset Type
HW
Reset SW
Reset Indivi dual Reset STOP
ICR Al l bi ts 0 0 — —
CVR HC 0 0 0 0
HV[0–6] $32 $32 — —
DSP56303 User’s Manual, Rev. 2
6-28 Freescale Semiconductor
Host Interface (H I0 8)
6.8 Programming Model Quick Reference
Table 6-19 summarizes the HI08 programming model.
ISR HREQ 0 0 1 if TREQ is set;
0 otherwi se 1 if TREQ is set;
0 otherwi se
HF3 -HF2 0 0 — —
TRDY 1 1 1 1
TXDE 1 1 1 1
RXDF 0 0 0 0
IVR IV[0–7] $0F $0F — —
RX RXH:RXM:RXL empty empty empty empty
TX TXH:TXM:TXL empty empty empty empty
Note: A lon g dash (— ) denotes that the bit val ue is not affe cted by the specified reset.
Table 6-19. HI08 Programming Model, DSP Side
Register
Bit Reset Type
Bit
No. Bit Name Value Function HW/
SW Indivi-
dual STOP
HCR 0 HRIE Receive Interrupt
Enable 0
1HRRQ interrupt disabled
HRRQ interrupt enabled 0——
1 HTIE Transm it
Interrupt Enable 0
1HTRQ inter rupt disabled
HTRQ interrupt enabled 0——
2 HCIE Ho st Command
Interrupt Enable 0
1HCP interrupt di sabled
HCP interrupt enabled 0——
3 HF2 Host Flag 2 0
4 HF3 Host Flag 3 0 — —
HPCR 0 HGEN Host GPIO
Enable 0
1GPI O signal di sconnected
GPI O signals acti ve 0——
1 HA8EN Host Address
Line 8 Enable 0
1HA8/A1 = GPIO
HA8/A1 = HA8 0——
2 HA9EN Host Address
Line 9 Enable 0
1HA9/A2 = GPIO
HA9/A2 = HA9 0——
3 HCSEN Ho st Chip Select
Enable 0
1HCS/A10 = GPIO
HCS/A10 = HCS 0——
Table 6-18. Host-Side Registers After Reset (Continued)
Register
Name Register
Data
Reset Type
HW
Reset SW
Reset Indivi dual Reset STOP
Programming Model Quick Reference
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-29
HPCR
cont. 4 HREN Host Request
Enable 0
1
HDRQ = 0
HDRQ = 1
HREQ/HTRQ = GPIO
HREQ/HTRQ
HACK/HRRQ = GPIO
HREQ/HTRQ =
HREQ,HREQ/HTRQ
HACK/HRRQ = HTRQ, HRRQ
0——
5 HAEN Host
Acknowledge
Enable 0
1
HDRQ = 0
HDRQ=1
HACK/HRRQ = GPIO
HREQ/HTRQ
HACK/HRRQ = GPIO
HACK/HRRQ = HACK
HREQ/HTRQ
HACK/HRRQ = HTRQ, HRRQ
0——
6 HEN Host Enable 0
1Host Port = GPIO
Host Port Acti ve 0——
7 — Reserved 0 Reserved 0 — —
8 HROD Host Request
Open Drain 0
1HREQ/HTRQ/HRRQ = driven
HREQ/HTRQ/HRRQ = open dr ain 0
9 HDSP Host Data Strobe
Polarity 0
1HDS/HRD/HWR active low
HDS/HRD/HWR act ive high 0——
10 HASP Host Address
Strobe Polarity 0
1HAS activ e low
HAS activ e high 0——
11 HMUX Host Mu ltiple xed
Bus 0
1Separate address and data l ines
Multiplexed address/data 0——
12 HDDS Host Dual Data
Strobe 0
1Single Data Strobe (HDS)
Double Dat a Str obe (HWR, HRD) 0——
13 HCSP Host Chip Select
Polarity 0
1HCS active low
HCS activ e high 0——
14 HRP Ho st Request
Polarity 0
1HREQ/HTRQ/HRRQ active low
HREQ/HTRQ/HRRQ active high 0——
15 HAP Host
Acknowledge
Polarity
0
1HACK active low
HACK active high 0——
Table 6-19. HI08 Programming Model, DSP Side (Continued)
Register
Bit Reset Type
Bit
No. Bit Name Value Function HW/
SW Indivi-
dual STOP
DSP56303 User’s Manual, Rev. 2
6-30 Freescale Semiconductor
Host Interface (H I0 8)
HSR 0 HRDF Host Receive
Data Full 0
1no receive data to be read
Receive Data Register is full 000
1 HTDE Host Transmi t
Data Empty 1
0The Transmit Data Register is
empty.
The Transmit Data Register is not
empty.
111
2 HCP Host Command
Pending 0
1no host comm and pending
host comm and pending 000
3 HF0 Host Flag 0 0 — —
4 HF1 Host Flag 1 0 — —
HBAR 7–0 BA[10–3
]Ho st Base
Address
Register
$80
HRX 23–
0DSP Receive
Data Regi ster empt
y
HTX 23–
0DSP Transmi t
Data Regi ster empt
y
HDR 16–
0D[16–0] GPIO signal
Data $000
0——
HDRR 16–
0DR[16–
0] GPIO signal
Direction 0
1Input
Output $000
0——
Table 6-20. HI08 Programming Model: Host Side
Reg
Bit Reset Type
# Name Value Function HW/
SW
Indi
vi-d
ual STOP
ICR 0 RREQ Receive Request Enable 0
1HRRQ interrupt di sabled
HRRQ interrupt enabled 0——
1 TREQ Transmit Request Enable 0
1HTRQ interrupt di sabled
HTRQ interrupt enabled 0——
2 HDRQ Double Host Request 0
1
HREQ/HTRQ = HREQ,
HACK/HRRQ = HACK
HREQ/HTRQ = HTRQ,
HACK/HRRQ = HRRQ
0——
3 HF0 Host Flag 0 0 — —
4 HF1 Host Flag 1 0 — —
5 HLEND Host Little Endian 0
1Big Endi an order
Little Endian order 0——
7 INIT Initialize 1 Reset dat a pat hs according to
TREQ and RREQ 0——
Table 6-19. HI08 Programming Model, DSP Side (Continued)
Register
Bit Reset Type
Bit
No. Bit Name Value Function HW/
SW Indivi-
dual STOP
Programming Model Quick Reference
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 6-31
ISR 0 RXDF Recei ve Data Register Full 0
1Host Receive Regist er is empty
Host Receive Register is full 00 0
1 TXDE Transm it Data Register
Empty 1
0Host Transmit Register is
empty
Host Transmit Register is full
11 1
2 TRDY Tra nsm it ter Ready 1
0transmit FIFO (6 deep) is
empty
transmit FIFO is not empty
11 1
3 HF2 Host Flag 2 0 — —
4 HF3 Host Flag 3 0 — —
7 HREQ Host Request 0
1HREQ signal i s deasserted
HREQ signal is asserted (i f
enabled)
00 0
CVR 6–0 HV[ 6–0] Host Command Vector $32 — —
CVR 7 HC Hos t Command 0
1no host comma nd pending
host command pending 00 0
RXH/M/
L7–0 Host Receive Data Register empt
y
TXH/M/
L7–0 Host Transmit Data
Register empt
y
IVR 7–0 IV[7–0] Inter rupt Regi ster 68000 family vec tor regist er $0F — —
Table 6-20. HI08 Programming Model: Host Side (Continued)
Reg
Bit Reset Type
# Name Value Function HW/
SW
Indi
vi-d
ual STOP
DSP56303 User’s Manual, Rev. 2
6-32 Freescale Semiconductor
Host Interface (H I0 8)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-1
Enhanced Synchronous Serial Interf ace
(ESSI) 7
The ESSI provides a full-duplex serial port for serial communication with a variety of serial
devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals. The ESSI consists of independent transmitter and receiver sections and a common
ESSI clock generator. There are two independent and identical ESSIs in the DSP5 6303: ESSI0
and ESSI1. For simplicity, a single generic ESSI is described here. The ESSI block diagram is
shown in Figure 7-1. This interface is synchronous because all serial transfers are synchronized
to one clock.
This synchronous interface should not be confused with the asynchronous channels mode of the
ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is
still a synchronous device because all transfers are synchronized to these clocks. Pin notations for
the generic ESSI refer to the analogous pin of ESSI0 (PCx) and ESSI1 (PDx).
Figure 7-1. ESSI Block Diagram
RSMA
RSMB
TSMA
TSMB
SSISR
RX
RX SHIFT REG
TX0 SHIFT REG
TSR
RCLK
TX0
CRB
CRA
SRD
STD
TCLK
SC2
SCK
Clock/Frame Sync Generators and Control Logic
Interrupts
TX1 SHIFT REG
TX1
SC0
TX2 SHIFT
TX2
SC1
GDB
DDB
DSP56303 User’s Manual, Rev. 2
7-2 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
Additional synchronization signals delineate the word frames. The Normal mode of operation
transfers data at a periodic rate, one word per period. The Network mode is similar in that it is
also for periodic transfers; however, it supports up to 32 words (time slots) per period. The
Network mode can be used to build time division multiplexed (TDM) networks. In contrast, the
On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of the
Freescale Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed when
the data become available. Since each ESSI unit can be configured with one receiver and three
transmitters, the two units can be used together for surround sound applications (which need two
digital input channels and six digital output channels).
7.1 ESSI Enhancements
The DSP56000 SSI is enhanced in the following ways to make the ESSI:
Network enhancements
— Time slot mask registers (receive and transmit)
— End-of-frame interrupt
— Drive enable signal (used with transmitter 0)
Audio enhancements
— Three transmitters per ESSI (for six-channel surround-sound)
General enhancements
— Can trigger DMA interrupts (receive or transm it)
— Separate exception enable bits
Other changes
— One divide-by-2 step is removed from the internal clock source chain
— The CRA[PSR] bit definition is reversed
— Gated-Clock mode is not available
7.2 ESS I Da ta and Cont r ol Signals
Three to six signals are required for ESSI operation, depending on the operating mode selected.
The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are fully
synchronized to the clock if they are programmed as transmit-data signals.
7.2.1 Serial Transmit Data Signal (STD)
The STD signal transmits data from the serial transmit shift register. STD is an output when data is
transmitted from the TX0 shift register. With an internally-generated bit clock, the STD signal
becomes a high impedance output signal for a full clock period after the last data bit is
transmitted if another data word does not follow immediately. If sequential data w ords are
ESSI Data and Control Signal s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-3
transmitted, the STD signal does not assume a high-impedance state. The STD signal can be
programmed as a GPIO signal (P5) when the ESSI STD function is not in use.
7.2.2 Serial Receive Data Signal (SRD)
SRD receives serial data and transfers the data to the receive shift register. SRD can be
programmed as a GPIO signal (P4) when the SRD function is not in use.
7.2.3 Serial Clock (SCK)
SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The signal is
a clock input or output used by all the enabled transmitters and receivers in Synchronous modes
or by all the enabled transmitters in Asynchronous modes. See Table 7-1 for details. SCK can be
programmed as a GPIO signal (P3) when not used as the ESSI clock.
Note: Although an external serial clock can be independent of and asynchronous to the DSP
system clock, the external ESSI clock frequency must not exceed Fcore/3, and each
ESSI phase must exceed the minimum of 1.5 CLKOUT cycles. The internally sourced
ESSI clock frequency must not exceed Fcore/4.
7.2.4 Serial Control Signal (SC0)
ESSI0: SC00; ESSI1: SC10
To determine the function of the SC0 signal, select either Synchronous or Asynchronous mode,
according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In
Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or
for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for
addressing in codec systems.
If SC0 is co nfigured as a serial flag signal or receive clock signal, its direction is determined by
the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as
an output, SC0 functions as the serial Output Flag 0 (OF0) or as a receive shift register clock
Table 7-1. ESSI Clock Sources
SYN SCKD SCD0 RX Clock Source RX Clock
Out TX Clock Source TX Clock Out
Asynchronous
0 0 0 EXT, SC0 — EXT, SCK —
0 0 1 INT SC0 EXT, SCK —
0 1 0 EXT, SC0 — INT SCK
0 1 1 INT SC0 INT SCK
Synchronous
1 0 0/1 EXT, SCK — EXT, SCK —
1 1 0/1 INT SCK INT SCK
DSP56303 User’s Manual, Rev. 2
7-4 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
output. If SC0 is used as the serial Output Flag 0, its value is determined by the value of the serial
Output Flag 0 (OF0) bit in the CRB. If SC0 is an input, it functions as either serial Input Flag 0 or
a receive shift register clock input. As serial Input Flag 0, SC0 controls the state of the serial Input
Flag 0 (IF0) bit in the ESSI Status Register (SSISR).
When SC0 is configured as a transmit data signal, it is always an output signal, regard less of the
SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD and SC1). SC0
can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not in use.
Note: The ESSI can operate with more than one active transmitter only in Synchronous
mode.
7.2.5 Serial Control Signal (SC1)
ESSI0:SC01; ESSI1: SCI11
To determine the function of SC1, select either Synchronous or Asynchronous mode, according to
Table 7-2. In Asynchronous mode (as for a single codec with asynchronous transmit and
receive), SC1 is the receiver frame sync I/O. In Synchronous mode, SC1 is the transmitter data out
signal of transmit shift register TX2, for the transmitter 0 drive-enabled signal, or for serial flag
I/O. As serial flag I/O, SC1 operates like SC0. SC0 and SC1are independent flags but can be used
together for multiple serial device selection; they can be unencoded to select up to two CODECs
or decoded externally to select up to four CODECs. If SC1 is configured as a serial flag or receive
frame sync signal, the Serial Control Direction 1 CRB[SCD1] bit determines its direction.
Table 7-2. Mode and Signal Definitions
Control Bit s ESSI Signals
SYN TE0 TE1 TE2 RE SC0 SC1 SC2 SCK STD SRD
00XX0U U UUUU
00XX1RXC FSR UUURD
01XX0U U FSTTXCTD0U
0 1 X X 1 RXC FSR FST TXC TD0 RD
10000U U UUUU
1 0 0 0 1 F0/U F1/T0D/U FS XC U RD
10010F0/U TD2 FSXCUU
10011F0/U TD2 FSXCURD
1 0 1 0 0 TD1 F1/T0D/U FS XC U U
1 0 1 0 1 TD1 F1/T0D/U FS XC U RD
10110TD1 TD2 FSXCUU
1 0 1 1 1 TD1 TD2 FS XC U RD
1 1 0 0 0 F0/U F1/T0D/U FS XC TD0 U
ESSI Data and Control Signal s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-5
When configured as an output, SC1 functions as a serial Output Flag, as the transmitter 0
drive-enabled signal, or as the receive frame sync signal output. If SC1 is used as serial Output
Flag 1, its value is determined by the value of the serial Output Flag 1 (OF1) bit in the CRB.
When configured as an input, this signal can receive frame sync signals from an external source,
or it acts as a serial input flag. As a serial input flag, SC1controls status bit IF1 in the SSISR.
When SC1 is configured as a transmit data signal, it is always an output signal, regard less of the
SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data signals
(STD and SC0). SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not
in use.
7.2.6 Serial Control Signal (SC2)
ESSI0:SC02; ESSI1:SC12
SC2 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode and for
the transmitter only in Asynchronous mode. The direction of this signal is determined by the
SCD2 bit in the CRB. When configured as an output, this signal outputs the internally generated
frame sync signal. When configured as an input, this signal receives an external frame sync signal
for the transmitter in Asynchronous mode and for both the transmitter and receiver when in
Synchronous mode. SC2 can be programmed as a GPIO signal (P2) when the ESSI SC2 function is
not in use.
1 1 0 0 1 F0/U F1/T0D/U FS XC TD0 RD
1 1 0 1 0 F0/U TD2 FS XC TD0 U
1 1 0 1 1 F0/U TD2 FS XC TD0 RD
1 1 1 0 0 TD1 F1/T0D/U FS XC TD0 U
1 1 1 0 1 TD1 F1/T0D/U FS XC TD0 RD
1 1 1 1 0 TD1 TD2 FS XC TD0 U
1 1 1 1 1 TD1 TD2 FS XC TD0 RD
TXC = Transmitter clock
RXC = Receiver clock
XC = Transmitter/receiver clock (synchronous operation)
FST = Transmitter frame syn c
FSR = R eceiver fram e sync
FS = Transmitter/receiver frame sync (synchronous operation)
TD0 = Transmit data signal 0
TD1 = Transmit data signal 1
TD2 = Transmit data signal 2
T 0D = Tr ansm itt er 0 drive enable if SSC1 = 1 & SC D1 = 1
RD = Receive data
F0 = Flag 0
F1 = Flag 1 if SSC1 = 0
U = Unused (can be used as GPIO signal)
X = Indeterminate
Table 7-2. Mode and Signal Definitions (Continued)
Control Bit s ESSI Signals
SYN TE0 TE1 TE2 RE SC0 SC1 SC2 SCK STD SRD
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7-6 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
7.3 Operation
This section discusses ESSI basics: reset state, initialization, and exceptions.
7.3.1 ESSI Aft er Reset
A hardware RESET signal or software reset instruction clears the port control register and the port
direction control register, thus configuring all the ESSI signals as GPIO. The ESSI is in the reset
state while all ESSI signals are programmed as GPIO; it is active only if at least one of the ESSI
I/O signals is programmed as an ESSI signal.
7.3.2 Initialization
To initialize the ESSI, do the following:
1. Send a reset: hardware RESET signal, software reset instruction, ESSI individual reset,
or stop instruction reset.
2. Program the ESSI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one signal as ESSI signal.
5. If an external frame sync is used, from the moment the ESSI is activated, at least five (5)
serial clocks are needed before the first external frame sync is supplied. Otherwise,
improper operation may result.
When the PC[5–0] bits in the GPIO Port Control Register (PCR) are cleared during program
execution, the ESSI stops serial activity and enters the individual reset state. All status bits of the
interface are set to their reset state. The contents of CRA and CRB are not affected. The ESSI
individual reset allows a program to reset each interface separately from the other inter nal
peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the
ESSI are not valid, and data read there are undefined. To ensure proper operation of the ESSI, use
an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE,
TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).
Here is an example of how to initialize the ESSI.
1. Put the ESSI in its individual reset state by clearing the PCR bits.
2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable
bits for the operating mode chosen.
3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.
4. Write initial data to the transmitters that are in use during operation. This step is needed
even if DMA services the transmitters.
5. Enable the transmitters and receiver to be used.
Operation
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-7
Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI is enabled (Step 3),
operation starts as follows:
1. For internally generated clock and frame sync, these signals start activity immediately
after the ESSI is enabled.
2. The ESSI receives data after a frame sync signal (either internally or externally
generated) only when the receive enable (RE) bit is set.
3. Data is transmitted after a frame sync signal (either internally or externally generated)
only when the transmitter enable (TE[2–0]) bit is set.
7.3.3 Exceptions
The ESSI can generate six different exceptions. They are discussed in the following paragraphs
(ordered from the highest to the lowest exception priority):
ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data regi ster is full,
and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE bit is
cleared when you first read the SSISR and then read the Receive Data Register (RX).
ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This error-free
interrupt can use a fast interrupt service routine for minimum overhead.
ESSI receive last slot interrupt:
Occurs when the ESSI is in Network mode and the last s lot of the fra me has ended. This
interrupt is generated regardless of the receive mask register setting. The receive last slot
interrupt can signal that the receive mask slot register can be reset, the DMA channels can
be reconfigured, and data memory pointers can be reassigned. Using the receive last slot
interrupt guarantees that the previous frame is serviced with the previous setting and the
new frame is serviced with the new setting without synchronization problems.
Note: The maximum time it takes to service a receive last slot interrupt should not exceed N
– 1 ESSI bits service time (where N is the number of bits the ESSI can transmit per
time slot).
ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit data register
of the enabled transmitters is empty, and a transmitter underrun error has occurred. This
exception sets the SSISR[TUE] bit. The TUE bit is cleared when you first read the SSISR
and then write to all the transmit data registers of the enabled transmitters, or when you
write to TSR to clear the pending interrupt.
ESSI transmit last slot interrupt:
Occurs when the ESSI is in Network mode at the start of the last slo t of the frame . This
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7-8 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
exception occurs regardless of the transmit mask register setting. The transmit last slot
interrupt can signal that the transmit mask slot register can be reset, the DMA channels
can be reconfigured, and data memory pointers can be reassigned. Using the Transmit Last
Slot interrupt guarantees that the previous frame is serviced with the previous frame
settings and the new frame is serviced with the new frame settings without
synchronization problems.
Note: The maximum transmit last slot interrupt service time should not exceed
N – 1 ESSI bits service time (where N is the number of bits in a slot).
ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit d ata
registers is empty, and no transmitter error conditions exist. Write to all the enabled TX
registers or to the TSR to clear this interrupt. This error- free interrupt uses a fast interrupt
service routine for minimum overhead (if no more than two transmitters are used).
To configure an ESSI exception, perform the following steps:
1. Configure the interrupt service routine (ISR):
a. Load vector base address register VBA (b23:8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it i s defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt). p:I_SI0TD
2. Configure interrupt trigger; preload transmit data
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (S0L1:0)
b. Write data to all enabled transmit registers. TX00
c. Enable a peripheral interrupt-generating function.CRB (TE0)
d. Enable a specific peripheral interrupt. CRB0 (TIE)
e. Enable peripheral and associated signals. PCRC (PC[5–0])
f. Unmask interrupts at the global level. SR (I1–0)
The example material to the right of the steps shows register settings for configuring an
ESSI0 transmit interrupt using transmitter 0. The order of the steps is optional except
that the interrupt trigger configuration must not be completed until the ISR
configuration is complete. Since step 2c may cause an immediate transmit without
generating an interrupt, perform the transmit data preload in step 2b before step 2c to
ensure that valid data is sent in the first transmission.
Operating Modes: Normal, Network, and On-Demand
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-9
After the first transmit, subsequent transmit values are typically loaded into TXnn by the
ISR (one value per register per interrupt). Therefore, if N items are to be sent from a
particular TXnn, the ISR needs to load the transmit register (N – 1) times. Steps 2c and
2d can be performed in step 2a as a single in struction. If an interrupt trigger event
occurs before all interrupt trigger configuration steps are performed, the event is ignored
and not queued. If interrupts derived from the core or other peripherals need to be
enabled at the same time as ESSI interrupts, step 2f should be performed last.
7.4 Op erating Modes: Normal, Netwo rk, and On-Demand
The ESSI has three basic operati ng modes and several data and operation formats. These modes
are programmed via the ESSI control registers. The data and operation formats available to the
ESSI are selected when you set or clear control bits in the CRA and C RB. These control bits are
WL[2–1], MOD, SYN, FSL[1–0], FSR, FSP, CKP, and SHFD.
7.4.1 Normal/Network/On-Demand Mode Selection
To select either Normal mode or Network mode, clear or set CRB[MOD]. In Normal mode, the
ESSI sends or receives one data word per frame (per enabled receiver or transmitter). In Network
mode, 2 to 32 time slots per frame can be selected. During each frame, 0 to 32 data words are
received or transmitted (from each enabled receiver or transmitter). In either case, the transfers
are periodic.
The Normal mode typically transfers data to or from a single device. Network mode is typically
used in time division multiplexed networks of CODECs or DSPs with multiple words per frame.
Network mode has a submode called On-Demand mode. Set the CRB[MOD] for Network mode,
and set the frame rate divider to 0 (DC = $00000) to select On-Demand mode. This submode
does not generate a periodic frame sync. A frame sync pulse is generated only when data is
available to transmit. The frame sync signal indicates the first time slot in the frame. On-Demand
mode requires that the transmit frame sync be internal (output) and the receive frame sync be
external (input). For simplex operation, Synchronous mode could be used; however, for
full-duplex operation, Asynchronous mode must be used. You can enable data transmission that
is data-driven by writing data into each TX. Although the ESSI is double-buffered , only one
word can be written to each TX, even if the transmit shift register is empty. The receive and
transmit interrupts function normally, using TDE and RDF; however, transmit underruns are
impossible for On-Demand transmission and are disabled. This mode is useful for interfacing
with codecs requiring a continuous clock.
Note: When the ESSI transmits data in On-Demand mode (that is, MOD = 1 in the CRB and
DC[4–0] = $00000 in the CRA) with WL[2–0] = 100, the transmission does not work
properly. To ensure correct operation, do not use On-Demand mode with the WL[2–0]
= 100 3 2-bit word length mode.
DSP56303 User’s Manual, Rev. 2
7-10 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
7.4.2 Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESSI interface are synchronous or asynchronous. The
transmitter and receiver use common clock and synchronization signals in Synchronous mode;
they use separate clock and sync signals in Asynchronous mode. The CRB[SYN] bit selects
synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX and RX
clocks and frame sync sources are independent. If the SYN bit is set, the ESSI TX and RX clocks
and frame sync are driven by the same source (either external or internal). Since the ESSI
operates either synchronously or asynchronously, separate receive and transmit interrupts are
provided.
Transmitter 1 and transmitter 2 operate only in Synchronous mode. Data clock and frame sync
signals are generated internally by the DSP or obtained from external sources. If clocks are
internally generated, the ESSI clock generator derives bit clock and frame sync signals from the
DSP internal system clock. The ESSI clock generator consists of a selectable fixed prescaler with
a programmable prescaler for bit rate clock generation and a programmable frame-rate divider
with a word-length divider for frame-rate sync-signal generation.
7.4.3 Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either a bit-long
or word-long frame-sync signal format, and the receiver can have the same or another format.
The selection is made by programming the CRB FSL[1–0], FSR, and FSP bits.
7.4.4 Frame Sync Signal Format
CRB[FSL1] controls the frame sync signal format.
If CRB[FSL1] is cleared, the receive frame sync is asserted during the entire data transfer
period. This frame sync length is compatible with Freescale codecs, serial peripherals that
conform to the Freescale SPI, serial A/D and D/A converters, shift registers, and
telecommunication pulse code modulation serial I/O.
If CRB[FSL1] is set, the receive frame sync pulses active for one bit clock immediately
before the data transfer period. This frame sync length is com patible with Intel and
National Semiconductor Corporation components, codecs, and telecommunication pulse
code modulation serial I/O.
7.4.5 Frame Sync Length for Multiple Devices
Mixing frame sync lengths is useful in configuring systems in which data is rec eived from one
type of device (for example, codec) and transmitted to a different type of device. CRB[FSL0]
controls whether RX and TX have the same frame sync length.
If CRB[FSL0] is cleared, both RX and TX have the same frame sync length.
Operating Modes: Normal, Network, and On-Demand
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-11
If CRB[FSL0] is set, RX and TX have different frame sync lengths. CRB[FSL0] is
ignored when CRB[SYN] is set.
7.4.6 Word Length Frame Sync and Data Word Timi ng
The CRB[FSR] bit controls the relative timing of the word length frame sync relative to the data
word timing.
When CRB[FSR] is cleared, the word length frame sync is generated (or expected) with
the first bit of the data word.
When CRB[FSR] is set, the word length frame sync is generated (or expected) with the
last bit of the previous word.
CRB[FSR] is ignored when a bit length frame sync is selected.
7.4.7 Frame Sync Polarity
The CRB[FSP] bit controls the polarity of the frame sync.
When CRB[FSP] is cleared, the polarity of the frame sync is positi ve; that is, the frame
sync signal is asserted high. The ESSI synchronizes on the leading edge of the frame sync
signal.
When CRB[FSP] is set, the polarity of the frame sync is negative; that is, the frame sync is
asserted low. The ESSI synchronizes on the trailing edge of the frame sync signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if CRB[FSP] is cleared,
trailing edge if FSP is set) only when the previous frame is comple ted. If the frame sync is
asserted before the frame is completed (or before the last bit of the frame is received in t he case
of a bit frame sync or a word-length frame sync with CRB[FSR] set), the current frame sync is
not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent; that is, a new frame sync does not have to follow the previous
frame immediately. Gaps of arbitrary periods can occur between frames. All the enabled
transmitters are tri-stated during these gaps.
7.4.8 Byte Format (LSB/MSB) for the Transmitter
Some devices, such as CODECs, require a MSB-first data format. Other devices, such as those
that use the AES–EBU digital audio format, require the LSB first. To be compatible with all
formats, the shift re gisters in the ESSI are bidirectional. You select either MSB o r LSB by
programming CRB[SHFD].
If CRB[SHFD] is cleared, data is shifted into the receive shift register MSB first and
shifted out of the transmit shift register MSB first.
If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and shifted out
of the transmit shift register LSB first.
DSP56303 User’s Manual, Rev. 2
7-12 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
7.4.9 Flags
Two ESSI signals (SC[1–0]) are available for use as serial I/O flags. Their operation is controlled
by the SYN, SCD[1–0], SSC1, and TE[2–1] bits in the CRB/CRA.The control bits OF[1–0] and
status bits IF[1–0] are double-buffered to and from SC[1–0]. Double-buffering the flags keeps
the flags in sync with TX and RX.
The SC[1–0] flags are available in Synchronous mode only. Each flag can be separately
programmed. The SC0 flag is enabled when transmitter 1 is disabled (TE1 = 0). The flag’s
direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When
SCD0 is cleared, SC0 is configured as input. Similarly, the SC1 flag is enabled when transmitter 2
is disabled (TE2 = 0), and the SC1 signal is not configured as the transmitter 0 drive-enabled
signal (Bit SSC1 = 0). The direction of SC1 is determined by the SCD1 bit. When SCD1 is set,
SC1 is an output flag. When SCD1 is cleared, SC1 is an input flag.
When programmed as input flags, the value of the SC[1–0] bits is latched at the same time as the
first bit of the received data word is sampled. Once the input is latched, the signal on the input
flag signal (SC0 and SC1) can change without affecting the input flag. The value of SC[1–0] does
not change until the first bit of the next data word is received. When the received dat a word is
latched by RX, the latched values of SC[1–0] are latched by the SSISR IF[1–0] bits, respectively,
and can be read by software.
When they are programmed as output flags, the value of the SC[1–0] bits is taken from the value
of the OF[1–0] bits. The value of OF[1–0] is latched when the contents of TX transfer to the
transmit shift register. The value on SC[1–0] is stable from the time the first bit of the transmit
data word transmits until the first bit of the next transmit data word transmits. Software can
directly set the OF[1–0] values, allowing the DSP56303 to control data transmission by indirectly
controlling the value of the SC[1–0] flags.
7.5 ESSI Programming Model
The ESSI is composed of the following registers:
Two control registers (CRA, CRB), page 7-13 and page 7-17
One status register (SSISR), page 7-26
One Receive Shift Register, page 7-28
One Receive Data Register (RX), page 7-28
Three Transmit Shift Registers, page 7-28
Three Transmit Data Registers (TX0, TX1, TX2), page 7 -28
One special-purpose Time Slot Register (TSR), page 7-31
Two Transmit Slot Mask Registers (TSMA, TSMB), page 7-31
Two Receive Slot Mask Registers (RSMA, RSMB), page 7-32
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-13
This section discusses the ESSI registers and describes their bits. Section 7.6 , GPIO Signals and
Registers, on page 7-33 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct
the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word
length, and number of words per frame for serial data.
Figure 7-2. ES SI Contro l Register A(CRA)
23 22 21 20 19 18 17 16 15 14 13 12
SSC1 WL2 WL1 WL0 ALC DC4 DC3 DC2 DC1 DC0
11109876543210
PSR PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
—Reserv ed bit; read as 0; wri te to 0 for future compatibility.
(ESSI0 X:$FFFFB5, ESSI1 X:$FF FFA5)
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
Bit Number B it Name Reset Value Description
23 0 Reserved. Write to 0 for future com patibility.
22 SSC1 0 Select SC1
Controls the functional ity of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/ asynchronous bit
(SYN) is set), and transmitter 2 is disabl ed (transmit enable ( TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal i s configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the seri al I/O flag while the SC1 si gnal is
configured as output (SCD1 = 1).
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7-14 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
21–19 WL[2–0] 0 Word Length Control
Select the length of the data words transferr ed via the ESSI. Word lengths of
8-, 12-, 16-, 24-, or 32- bits can be selecte d. The ESSI data pa th programming
mode l i n Figure 7-12 and Figure 7-13 shows additi onal i nformation on how to
select di ff erent l engths for data words. The ESSI data registe rs are 24 bit s
long. The ESSI tr ansmits 32-bit words i n one of two ways:
• By duplicating the la st bit 8 times when WL[2–0] = 100
• By duplicating the first bi t 8 tim es when W L[2–0] = 101.
Note: When W L[2–0] = 100, t he ESSI is designe d to dupli cate the l ast bit of
the 24-bit transm ission ei ght times to fill the 32- bit shifter. In stead,
after the 24-bit word is shif ted correctl y, eight zer os (0s) are shif ted.
ESSI Word Length Selection
WL2 WL1 WL0 Number of Bits/Word
00 0 8
00 1 12
01 0 16
01 1 24
10 0 32
(valid data in the first 24
bits)
10 1 32
(valid data in the l a st 24
bits)
1 1 0 Reserved
1 1 1 Reserved
Note: When the ESSI transmit s data in On-Demand mode (that is, MOD = 1
in t he CRB and DC[4–0]=00000 in the CRA) with WL[ 2–0] = 100, the
tran smissi on does not work properl y. To ensure correct oper ation, do
not use On-De mand mode wit h t he WL[2– 0] = 100 32-bit word lengt h
mode.
18 ALC 0 Alignment Control
The ESSI handles 24-bit fractional data. Shorte r data words are left-aligned to
the MSB, bi t 23. For appl ications tha t use 16-bit fractional data, shor ter data
words are left-aligned to bit 15. The ALC bit supports shorter data words. If
ALC is s et, re ceived wor ds a re left- alig ned to bi t 15 in t he recei ve shi ft re gister .
Transmitted words m ust be left -al igned to bit 15 in the tr ansmit shift register. If
the ALC bit is cleared, received words are left-aligned to bit 23 in the receive
shift register. Transmitted words must be left-aligned to bit 23 in the transmit
shift regi ster.
Note: I f the ALC bit is set, onl y 8-, 12-, or 16-bit words are use d. The use of
24- or 32-bit words leads to unpredictable results.
17 Re served . Write to 0 fo r fu tu r e c om pa t ib ility.
Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number B it Name Reset Value Description
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-15
16–12 DC[4–0] 0 Frame Rat e Divider Control
Contr ol the di vide rat io for the pro grammabl e frame ra te divi ders tha t generat e
the fr ame clocks . In Networ k mode, t his ra tio is t he numbe r of words per fr ame
minus one. In Nor ma l mode, this ratio determines the word transfer rate. The
divi de rati o ranges from 1 to 32 (DC = 00000 t o 1111 1) for Normal mode and 2
to 32 (DC = 00001 to 11111) for Network mode . A divide ratio of one (DC =
00000) in Networ k m ode is a special case known as On-Demand mode. In
Normal mode, a divide rat io of one (DC = 00000) provi des conti nuous periodic
data word transf ers. A bit-length frame sync mus t be used in this case; you
select it by setti ng the FSL[1–0] bits in t he CRA to (01) . Figure 7-4 shows the
ESSI frame sync generator functional block diagr am.
11 PSR 0 Prescaler Range
Controls a fixed divide-by- eight prescaler in series with th e variable pr escaler.
This bi t extends the range of the prescaler when a slower bit clock is needed.
When PSR is set, the fi xed prescaler is bypassed. When PSR is cleared, the
fixed divid e-by-eight prescal er is oper ational, as in Figure 7-3. Th is definitio n
is rev ersed from that of the SSI in other DSP56000 family members. The
maximum allowed internally generated bit clock frequency is the internal
DSP56303 clock frequency di vided by 4; t he m inimum possible internally
generat ed bit clock frequency is the DSP56303 internal clock frequency
divided by 4096.
Note: The combination PSR = 1 and PM[7–0] = $00 (dividing Fcore by 2)
can cause synchronization problems and thus should not be used.
10–8 0 Reserved. Write to 0 for future com patibility.
7–0 PM[7–0] 0 Prescale Modulus Select
Specify t he divide rat io of the prescale di vider i n the ESSI clo ck generator. A
divide rat io from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is avai lable at the transmit cloc k signal (SCK) and /or the recei ve clock
(SC0) s ignal of the DSP. The bit clock ou tpu t is also a vai lable internal ly for use
as the bit clock to shift the transmit and receive shift registers. Figure 7-3
shows the ESSI cl ock generator functional block diagr am. Fcore is the
DSP56303 core clock fr equency (the same frequency as the enabled
CLKOUT signal). Care ful choice of t he crystal osci ll ator f requency and the
prescaler modulus can generat e the industry- standard CODEC master clock
frequencies of 2.04 8 MHz, 1.544 MHz, and 1.536 MHz.
Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number B it Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
7-16 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
Figure 7-3. ESSI Clock Generator Functional Block Diagr am
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
SCn0
SCKn
CRB(SCD0)
CRB(SCKD)
CRB(SYN) = 1 SCD0 = 0
RCLOCK
TCLOCK
Internal Bit Clock
SYN = 1
CRA(WL2–0)
RX Shift Regist er
TX Shift Register
/1 or /8 /1 to /256
FCORE
RX
Word
Clock
SYN = 0 SCD0 = 1
•F
CORE is the DSP56300 core internal
clock fr equency.
• ESSI internal clock ran ge:
min = FOSC/4096
max = FOSC/4
• ‘n’ in si gnal name is ESSI # (0 or 1)
Sync:
TX 1, or
Async:
RX clk
Sync:
TX/RX clk
Async:
TX clk
0
0 0 255
CRA(PSR) CRA(PM7:0)
/8 , /12, /1 6 , /24,
1234,5
Flag0 Out
(Sync Mo de)
CRB(OF0)CRB(TE1)
TX 1 Flag0 In
(Sync Mo de)
SSISR(IF0)
1
SYN = 0 0
/8 , /1 2, /16 , /24,
1234,5
/2
CRA(WL2–0) TX
Word
Clock
Flag0
(Opposite
from SSI)
or
Frame Sync
Transmit
Frame Sync
Receive
RX
Word
TX Wo rd
Clock
CRA(DC4:0)
Receive
Control
Logic
Transmit
Control
Logic
Sync-
Type
Sync
Type
CRB(SYN) = 0
SYN =
Internal Rx Frame Sync
CRB(SCD1) = 1
SYN = 1
SCD1 =
SYN = 0 CRB(SCD1)
Internal TX Frame Sync
SCn1
/1 to /32
310
CRB(FSL1)
CRB(FSL[1–0])
CRA(DC4–0)
/1 to /32
310
SCn2
CRB(SCD2)
Flag1 Out,
(Syn c Mo de) CRB(OF1)CRB(TE2)
TX 2, or drive enb.
CRA(SSC1)
Flag1 In
SSISR(IF1)
(Sync Mode)
CRB(FSR)
Sync:
TX 2 Flag1
,
Async:
RX F.S.
or drive en
b.
Sync:
TX/RX F.S.
Async:
TX F.S.
CRB(FSR)
These signals are
identi cal in sync mode.
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-17
7.5.2 ESSI Control Register B (CRB)
CRB is one of two read/write control registers that direct the operation of the ESSI (see Figure
7-5). The CRB bit definitions are presented in Table 7-4. CRB controls the ESSI multifunction
signals, SC[2–0], which can be used as clock inputs or outputs, frame synchronization signals,
transmit data signals, or serial I/O flag signals.
Figure 7-5. E S SI Cont rol Re g i s t er B (C R B )
The CRB contains the serial output flag control bits and the direction control bits for the serial
control signals. Also in the CRB are interrupt enable bits for the receiver and the transmitter. Bit
settings of the CRB determines how many transmitte rs are enabled: 0, 1, 2, or 3 . The CRB
settings also determine the ESSI operating mode. Either a hardware RESET signal or a software
RESET instruction clears all the bits in the CRB. Table 7-2, Mode and Signal Definitions, on
page 7-4 summarizes the relationship between the ESSI signals SC[2–0], SCK, and the CR B bits.
The ESSI has two serial outpu t flag bits, OF1 and OF0. The normal sequence follows for setting
output flags when transmitting data (by transmitter 0 through the STD signal only).
1. Wait for TDE (TX0 empty) to be set.
2. Write the flags.
3. Write the transmit data to the TX register
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when the TX
data is transferred to the transmit shift register. The flag bit values are synchronized with the data
transfer. The timing of the optional serial output signals SC[2–0] is controlled by the frame timing
and is not affected by the settings of TE2, TE1, TE0, or the receive enable (RE) bit of the CRB.
The ESSI has three transmit enable bits (TE[2–0]), one for each data transmitter. The process of
transmitting data from TX1 and TX2 is the same. TX0 differs from these two bits in that it can
also operate in Asynchronous mode. The normal transmit enable sequence is to write data to one
or more transmit data registers (or the Time Slot Register (TSR)) before you set the TE bit. The
normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit and then to clear
the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt Enable (TEIE) bits. In
Network mode, if you clear the appropriate TE bit and set it again, then you disable the
corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter
remains disabled until the beginning of the next frame. During that t ime period, the
23 22 21 20 19 18 17 16 15 14 13 12
REIE TEIE RLIE TLIE RIE TIE RE TE0 TE1 TE2 MOD SYN
11109876543210
CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0
(ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)
DSP56303 User’s Manual, Rev. 2
7-18 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
corresponding SC (or STD in the case of TX0) signal remains in a high-impedance state. The
CRB bits are cleared by either a hardware RESET signal or a software RESET instruction.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions
Bit Number Bit Name Reset Value Description
23 REIE 0 Receive Exception Inter rupt Enable
When the REIE bit is set, the DSP is interr upted when both RDF and ROE
in the ESSI status register are set. When REIE is cleared, this interrupt is
disabled. The recei ve interru pt i s docum ented in
Section 7.3.3, Exceptions, on page 7-7. A read of the status regi ster
followed by a read of the receive data regist er cl ears both ROE and the
pending interrupt.
22 TEIE 0 Transmit Except ion Interrupt Enabl e
When the TEI E bit is s et, t he DSP is inter rupted whe n both TDE and TUE in
the ESSI st atus regi ster are set . When TEIE is cleare d, this interr upt is
disabled. The use of the transmit interrupt is documented
in Section 7.3.3, Exceptions, on page 7- 7. A read of the status register,
followed by a write to all the data registers of the enabled transmitters,
clears both TUE and the pending interrupt.
21 RLIE 0 Rece ive Last Slot Interrupt Enable
Enables/di sables an int errupt after the l ast slot of a fr am e ends when the
ESSI i s in Net work mode. When RL IE is set, t he DSP is inter rupte d afte r the
last slot in a frame ends regardless of the re ceive mask register setti ng.
When RLI E is cl eared, t he receive last slot interrupt i s disabled. The use of
the receive las t sl ot interr upt is documented in
Section 7.3. 3, Exceptions, on page 7-7. RLI E is di sabled when the ES SI is
in On- Demand mode (DC = $0).
20 TLIE 0 Transm it Last Sl ot Interrupt Enable
Enables/di sables an int errupt at the beginning of the last sl ot of a fram e
when the ESSI is in Netw ork mode. When TLIE is set, the DSP is
interrupt ed at t he start of the last slot in a frame regardless of the transmit
mask register set ting. When TLIE is cl eared, the transmit l ast slot interrupt
is di sabled. The transmit last slot interrupt is documented
in S ection 7.3.3, Exceptions, on page 7-7. TLIE is disabled when th e ESSI
is in On-Dem and mo de (DC = $0).
19 RIE 0 Receive Interrup t Enabl e
Enables/disables a DSP receive data interrupt; the interr upt i s generated
when both th e RIE and rec eive data register f ull (RDF) bit (i n the SSISR)
are set . Wh en RIE is clear ed, th is inter rup t is d isabl ed. The r eceive inter rupt
is documented in Section 7.3.3, Exceptions, on page 7-7. When the
receive data reg ister is read, it clears RDF and the pending int errupt.
Receive int errupt s wit h exception have higher priority than norm al recei ve
data interru pts. If the receiver over run error (ROE) bit is set (si gnaling that
an exception has occurred) and the REIE bit i s set, the ESSI requests an
SSI recei ve data with exception interrupt from the int errupt cont roll er.
18 TIE 0 Transmit Interrupt Enable
Enables/disables a DSP transmit interrupt; the interrupt is generated when
both the TIE and the TDE bits i n the ESSI stat us register are set. When TIE
is cl eared, the transmit inte rrupt is disabled. The tr ansm it i nterrupt is
docum ented in Section 7.3.3. When data is written t o the data registers of
the enabled trans mitters or to the TSR, it clears TDE and also clears t he
interrupt . Tra nsm it in terrupts with exception condit ions have higher priorit y
than normal transmit data inter rupts. If the transmit ter underrun er ror (TUE)
bit is set (si gnaling that an exception has occurred) and the TEIE bit is set,
the ESSI re quests an SSI transmit data wi th exceptio n int errupt from the
interrupt controller.
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-19
17 RE 0 Receive Enable
Enables/disables the receive portion of the ESSI . Wh en RE is cleared, t he
receiver is disabled: data t ransfer into RX is inhibited. If data is being
received while this bit is c leared, t he remainder of the word is shifted in and
transferr ed to th e ESS I rec eive data regi ster. RE must be set in bot h
Normal and On- D em and modes for th e ESSI to re ceive data. In Networ k
mode, cleari ng RE and se tt ing it again disabl es the receiver afte r rec eption
of the cur rent dat a word. The rec eiver r em ains dis abled until the beginning
of the next data frame.
Note: The sett ing of the RE bit does not affect the generation of a fr am e
sync.
16 TE0 0 Transmit 0 Enable
Enables the t ransfer of data from TX0 to Transmit Shift Register 0. TE0 is
functional when the ESSI is in either synchronous or Asynchronous mode.
When TE0 is set and a fra me sync is detected, the transmitter 0 is enabled
for t hat f rame.
When T E0 is c lea red, t ransmi tter 0 is d isabl ed af ter the tr ansmiss io n of dat a
currently in the ESSI transmit shift regi ster. The STD output is tri-stat ed,
and any data present i n TX0 is not tran sm it ted. I n other words, data can be
writ ten to TX0 with TE0 cleared; the TDE bit is cleared, but data is not
transferr ed to the transmit shift register 0. The transmit enabl e sequence in
On-D em and mode can be the same as in Normal mode, or TE0 can be left
enabled.
Note: Transmitt er 0 is the only t ransmitter th at can operate in
Asynchronous mode (SYN = 0). The setting of the TE0 bit does
not aff ect the generat ion of f rame sync or output flags.
15 TE1 0 Transmit 1 Enable
Enables the t ransfer of data from TX1 to Transmit Shift Register 1. TE1 is
funct ional only when t he ESSI i s in Synch ron ous mode a nd is i gnored when
the ESSI is in Asynchronous mode. When TE1 is set and a frame sync is
detected, tr ansm itter 1 is enabl ed for that frame.
When TE1 is cleared, transm itter 1 is di sabled after com pleting
transmissi on of dat a currently in the ESSI transmit shif t regist er. Any data
present in TX1 is not transmitt ed. If TE1 is clea red, data can be written to
TX1; the TDE bit is cleared, but data is not transferr ed to transmit shift
register 1. If th e TE1 bit i s kept cleared until the st art of t he next frame, i t
causes the SC0 signal to act as serial I/ O flag from the start of the frame i n
both Normal and Network mode. The transmi t enable sequence in
On-D em and mode can be the same as in Normal mode, or t he TE1 bit can
be left enabled.
Note: The setting of the TE1 bit does not affect the generation of frame
sync or output fl ags.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
7-20 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
14 TE2 0 Transmit 2 Enable
Enables the t ransfer of data from TX2 to Transmit Shift Register 2. TE2 is
funct ional only when t he ESSI i s in Synch ron ous mode a nd is i gnored when
the ESSI is in Asynchronous mode. When TE2 is set and a frame sync is
detected, tr ansm itter 2 is enabl ed for that frame.
When TE2 is cleared, transm itter 2 is di sabled after com pleting
transmissi on of dat a currently in the ESSI transmit shif t regist er. Any data
present in TX2 is not transmitt ed. If TE2 is clea red, data can be written to
TX2; the TDE bit is cleared, but data is not transferr ed to transmit shift
register 2. If th e TE2 bit i s kept cleared until the st art of t he next frame, i t
causes the SC1 signal t o act as a ser ial I /O fl ag from the star t of the frame
in both Normal mode a nd Network mode. The transmit enabl e sequence in
On-D em and mode can be the same as in Normal mode, or t he TE2 bit can
be left enabled.
Note: The setting of the TE2 bit does not affect the generation of frame
sync or output fl ags.
13 MOD 0 Mode Sel ect
Select s the operati onal mode of the ESSI, as in Figure 7-8 on page -25,
Figure 7-9 on page -26, and Figure 7-10 on page -26. When M O D is
clear ed, the Nor mal mode is sel ected; when MOD is set, the Net work mod e
is sel ected. I n Normal mode, the fram e rate divid er det ermines the word
transfer rate: one wor d is transferred per frame sync during the frame sync
time slot. In Network mod e, a word can be transferr ed every ti m e slot. For
details, see Section 7.3.
12 SYN 0 Synchronous/Asynchronous
Controls whether the receive and transmit functions of the ESSI occur
synchronously or async h ronously wi th respect to each other. (See Figure
7-7 on page -24.) When SYN is cleared, the ESSI is in Asynchr onous
mode, and separate clock and frame sync signals are used for t he transmit
and receive sections. When SYN is set, the ESSI is in Sync hronous mode,
and the tr ansm it and recei ve se cti ons u se com m on clock and frame sync
signals. O nly i n Synchronous mode can more than one trans m it ter be
enabled.
11 CKP 0 Clock Polarity
Controls which bit clock edge data and frame sync are cl ocked out and
latc hed in. I f CKP is cleared, t he data and the frame sync are clock ed out
on the risi ng edge of the transmit bit clock and latched i n on th e falling edge
of the re ceive bit clock. If CKP is set , the data and the frame sync are
clock ed out on t he f alling e dge of the tr ansmit bit cl ock and l at ched in on the
rising edge of the recei ve bit clock.
10 FSP 0 Frame Sync Polarity
Determines the pol arity of t he receive and tr ansm it f rame sync s ignals.
When FSP is cleared, the frame sync s ignal polarity is positive; that is, the
frame start is indi cated by the f rame s ync signal goi ng high. When FSP is
set, the frame sync signal polarity is negat ive; that is, the fr am e start is
indi cated by the fra me sync signal going low.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-21
9FSR0Frame Sync Relative Timing
Determi nes t he rela tive t iming of the recei ve and tra nsmit fr ame syn c signal
in ref erence to the ser ial dat a li nes for word len gth frame sync only. When
FSR is cleared, the word l ength frame sync occurs together with the fi rst bit
of the dat a word of the first slot . When FSR is set, the wor d length fram e
sync occurs one serial clock cycle earlier (that is, simu ltaneously with the
last bit of the previous data word).
8–7 FSL[1–0] 0 Frame Sync Length
Selects the length of frame sync to be generated or recognized, as in
Figure 7-6 on pag e -23, Figure 7-9 on page -2 6, and Figur e 7-10, Network
Mode, External Frame Sync (8 Bi t, 2 Words in Fr am e), on page 7-26.
FSL1 FSL0 Frame Sync Length
RX TX
0 0 word word
01word bit
10 bit bit
1 1 bit word
6SHFD0Sh if t D ir ec t io n
Determines the shi ft direction of t he transmit or receive shif t regi ster. If
SHFD is set, dat a is shifted in and out with the LSB first. If SHFD is cl eared,
data is shif ted in and out with the MSB first, as in Figure 7-12, ESSI Data
Path Program m ing Model ( SHFD = 0), on page 7-29 and Figure 7-13 on
page -30.
5SCKD0Clock Source Direc ti on
Selects the source of the clo ck signal that clocks the tr ansm it shift register
in Asynchronous mode and both the transmit and receive shi ft registers in
Synchronous mode. If SCKD is set and the ESSI is in Sync hronous mode,
the i nternal clock i s the source of the clock signal used for all the transmit
shift registers and t he receive shift regist er. If SCKD is set and the ESSI is
in Asynchronous mode, the internal clock sou rce becomes the bit clock for
the tr ansm it shi ft re gister and word length divi der. The inter nal clock is
output on the SCK si gna l. When SCKD i s clear ed, the e xterna l cloc k source
is selected. The internal clock generator is disconnected from the SCK
signal , and an ext ernal clock sour ce may drive t his signal.
4 SCD2 0 Serial Control Di rect ion 2
Controls the direction of the SC2 I/O signal . When SCD2 is set, SC2 is an
output; when SCD2 is cleared, SC2 i s an input.
Note: Pr ogramming the ESSI to use an int ernal frame sync (that is,
SCD2 = 1 in CRB) causes the SC2 and SC1 signal s to be
programmed as output s. However, if the corresponding
multi plexed pins are prog ramm ed by the Port Control Register
(PCR) to be GPIOs , the GPIO Port Direction Register (PRR)
chooses their directi on. The ESSI uses an external frame sync if
GPIO is selected. To assure corre ct operation, either program the
GPIO pins as out puts or configur e the pi ns in the PCR as ESSI
signa ls. The def ault se lecti on for t hese signal s afte r reset is GPIO.
This not e applies to both ESSI0 and ESSI1.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
7-22 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
3 SCD1 0 Serial Control Di rect ion 1
In Synchronous mode (SYN = 1) when transmitter 2 is di sabled (TE2 = 0),
or in Asynchronous mode (SYN = 0), SCD1 control s the direct ion of the
SC1 I/O signal. W hen SCD1 is set, SC1 i s an output; when SCD1 is
cleared, SC1 is an input. Whe n TE 2 is set , the value of SCD1 is igno red
and the SC1 sig nal is always an output.
2 SCD0 0 Serial Control Di rect ion 0
In Synchronous mode (SYN = 1) when transmitter 1 is di sabled (TE1 = 0),
or in Asynchronous mode (SYN = 0), SCD0 control s the direct ion of the
SC0 I/O signal. W hen SCD0 is set, SC0 i s an output; when SCD0 is
cleared, SC0 is an input. Whe n TE 1 is set , the value of SCD0 is igno red
and the SC0 sig nal is always an output.
1 OF1 0 Serial Ou tput Flag 1
In Synchronous mode (SYN = 1), when transmitter 2 is disabl ed (TE2 = 0) ,
the SC1 sign al i s configure d as ESSI flag 1. When SCD1 is set, SC1 is an
output. Data present in bi t OF1 is writ ten to SC1 at the beginning of the
frame in Normal mode or at the beginning of the next tim e slot in Network
mode.
0OF00Serial Ou tput Flag 0
In Synchronous mode (SYN = 1), when transmitter 1 is disabl ed (TE1 = 0) ,
the SC0 sign al i s configure d as ESSI flag 0. When SCD0 is set, the SC0
signal is an output. Data present in Bit OF0 is writt en to SC0 at the
beginning of the frame in Normal mode or at the beginning of t he next ti me
slot i n Netwo rk mode.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-23
Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0)
Serial Clock
RX, TX Frame SYNC
Wor d Length: FSL1 = 0, FSL0 = 0
RX, TX Serial Data
NOTE: Frame sync occurs while data i s valid.
Data Data
Serial Clock
RX, TX Frame SYNC
One Bit Length: FSL1 = 1, FSL0 = 0
RX, TX Serial Data
NOTE: Frame sync occurs for one bit ti m e preceding th e data.
Serial Clock
TX Frame SYNC
Mixed Frame Length: FSL1 = 0, FSL0 = 1
RX Frame Sync
Serial Clock
TX Frame SYNC
Mixed Frame Length: FSL1 = 1, FSL0 = 1
TX Serial Data
RX Frame SYNC
Data Data
Data Data
Data Data
Data Data
Data Data
RXSerial Data
TX Serial Data
RX Serial Data
DSP56303 User’s Manual, Rev. 2
7-24 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
Figur e 7-7. CRB SYN Bit Operat ion
External Frame SYNC
SC1
Asynchronous (SYN = 0)
Transmitter
Clock Frame
SYNC
Receiver
Clock Frame
SYNC SR
STD
SC2
Exte rna l Tr an smi t Frame
External Receive Frame
Internal Frame SYNC
SC0
SCK External Transmit Cl ock
External Receive Clock
Internal Cloc k
ESSI Bit
Clock
NOTE: Transmitter and r eceiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN = 1 )
Transmitter
Clock Frame
SYNC
Receiver
Clock Frame
SYNC SRD
ST
SC2
Internal Frame SYNC
SCK External Clock
Internal Clock
ESSI Bit
Clock
NOTE: Tra nsm itter and receiver ma y have the sam e clock frame sync s.
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-25
Figu re 7-8. CRB MOD Bit Ope ration
SSI Control Regi ster B ( CRB)
(READ/WRITE)
Normal Mode (MOD = 0)
Serial Clock
Frame SYNC
Serial Data Data Data
Transmitter Interrupt (or DMA Request) and
Receiver Interrupt (or DMA Request) and Flags
NOTE: Inter rupts occur and data i s tr ansferred once per frame sync.
Network Mode (MOD = 1)
Serial Clock
Frame SYNC
Transmitter Interrupts (or DMA Request) and
Slot 1 Slot 2 Slot 3 Slot 1 Slot 2
Serial Data
Receiver Interrupt (or DMA Request) and Flags Set
NOTE: Interrupt s occur every t ime slot and a word may be tra nsferred.
DSP56303 User’s Manual, Rev. 2
7-26 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
Figure 7-10. Netw ork Mode, External Frame Sync (8 Bit, 2 Words in Frame)
7. 5.3 ESSI Stat us Register (SSI SR)
The SSISR is a read-only status register by which the DSP reads the ESSI status and serial input
flags.
Figure 7-11. ESSI Status Register (SSISR)
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
RDF TDE ROE TUE RFS TFS IF1 IF0
—Reser ved bit; read as 0; write to 0 0 for fu tur e com patibility.
(ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data Out
Flags
Slot 0 Slot 0Wait
SLOT 0 SLOT 1SLOT 1 SLOT 0
Frame S Y N C
(FSL0 = 0, FSL1 = 0)
Frame S Y N C
(FSL0 = 0, FSL1 = 1)
Flags
Data
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-27
Table 7-5. ESSI Status Register (SSISR) Bit Definitions
Bit Number Bit Name Reset Val ue Description
23–8 0 Reserved. Write to 0 for futur e com patibility.
7 RDF 0 Receive Data Regist er Full
Set when the cont ents of t he receive shift regist er transfer to the rec eive
data re giste r. RDF i s clear ed when th e DSP reads t he receiv e data r egist er.
If RIE and RDF are set, a DSP receiv e data i nterr upt request is issued.
6TDE0Transmit Data Register Empty
Set when the cont ents of t he transmit dat a register of every enabled
transmitter are tr ansferred to th e transmit shi ft regist er. I t is al so se t for a
TSR disabled time sl ot period in Network mode (as if data were being
transmi tted af ter th e TSR has been wri tten). When TDE is set, TDE dat a is
written to all the TX registers of the enab led transmitte rs or to the TSR. The
TDE bit is clear ed when the DSP writes to all the trans mit data re gisters of
the enabl ed transmitters, or when the DSP writes t o the TSR to disable
transmission of t he next tim e slot. If the TIE bit is set , a DSP tra nsmit dat a
inter rupt re quest is i ssued wh en TDE is set .
5ROE0Receiver Overrun Error Flag
Set when the ser ial recei ve shif t regis ter is f illed and r eady t o t ransf er to the
recei ve data regi ster ( R X) but RX is al ready ful l (that is, the RDF bit is set).
If the REIE bit is set , a DSP receiver overrun error i nterr upt request is
issued when the ROE bit is set . The programme r cl ears ROE by reading
the SSISR with the ROE bit set and then reading t he RX.
4TUE0Transmitter Underrun Error Flag
TUE is set when at least one of the enabl ed serial transm it shi ft registers i s
empty (that is, ther e is no new data t o be transmitted) and a transmi t t ime
slot occ u rs. When a transmit underr un error occurs, the previous data
(which is still present in the TX registers not written) is retransmitted. In
Normal mode, ther e is onl y one transmit time slot per frame. In Network
mode, there can be up to 32 transmit time slots per frame. If the TEIE bit is
set, a DSP transm it underrun error interrupt request is issued when the
TUE bit is set. The programmer can also clear TUE by fi rst reading the
SSISR with the TUE bit set, then writing to al l t he enabled trans mit data
regis ters or to the TSR.
3RFS0Receive Frame Sync Flag
When set, the RFS bit indicates that a rec eive frame sync occurred dur ing
the reception of a word in the serial receive data register. In other words,
the data wor d is from the first time slot in t he frame. When the RFS bit is
cleared and a word is received, i t indicates (only in Network mode) that t he
frame sync did not occur duri ng reception of that wor d. RFS is vali d only if
the receiver is enabled (that is, if the RE bit is set). In Normal mode, RFS is
always read as 1 when data is read bec ause there is onl y one time slot per
frame, the frame sync time slot .
2 TFS 0 Transmit Frame Sync Flag
When set , TFS in dicates that a transmit f rame sync occurred in the cur rent
time sl ot. TFS i s set at the st art of the fir st tim e slot in th e fram e and clear ed
during all other time slots. If the t ransmitter is enabled, data written to a
transmit dat a register during the ti m e slot when TFS is set is tra nsm itt ed (in
Network mode) during the second time slot in the frame. TFS is useful in
Network mode to ident ify the st art of a fr am e. TFS i s valid only if at l east
one transmitter i s enabled that i s, when TE0, TE1, or TE2 is set) . In Normal
mode, TFS is alwa ys read as 1 when data is being transmitted bec ause
there i s only one ti m e slot per frame, the frame sync time slo t.
DSP56303 User’s Manual, Rev. 2
7-28 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
7.5. 4 ESSI Receive Shift Register
The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives incoming data
from the serial receive data signal. The selected (internal/external) bit clock shifts data in when
the associated frame sync I/O is asserted. Data is received MSB first if SHFD is cleared and LSB
first if SHFD is set. Data transfers to the ESSI Receive Data Register (RX) after 8, 12, 16, 24, or
32 serial clock cycles are counted, depending on the word length control bits in the CRA.
7.5.5 ESSI Receive Data Register (RX)
The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the receive
shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data read is
aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23,
and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15, and the most
significant byte is unused. Unused bits are read as 0. If the associated interrupt is enabled, the
DSP is interrupted whenever the RX register becomes full.
7.5. 6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted, as in Figure 7-12 and
Figure 7-13. Data is shifted out to the serial transmit data signals by the selected (whether
internal or external) bit clock when the associated frame sync I/O is asserted. The word -length
control bits in CRA determine the number of bits that must be shifted out before the shift
registers are considered empty and can be written again. Depending on the setting of the CRA,
the number of bits to be shifted out can be 8 , 12, 16, 24, or 32. Transmitted data is aligned
according to the value of the ALC bit. When ALC is cleared, the MSB is Bit 23 and the least
significant byte is unused. When ALC is set, the MSB is Bit 15 and the most significant byte is
1 IF1 0 Serial Input Flag 1
The ESSI latches any da ta on th e SC1 signal during recepti on of the first
received bit after the frame sync is det ected. IF1 is updated wit h this data
when the data i n the r eceive shift register transfers i nto the recei ve data
register. IF1 is enabl ed only when SC1 is an i nput flag and Synchronous
mode is selec ted; that is, when SC1 is prog rammed as ESSI in the port
control register (PCR), the SYN bit is set, and the TE 2 and SCD1 bit s are
cleared. If it is not enabl ed, IF1 is cleared.
0IF00Serial Input Flag 0
The ESSI latches any da ta on th e SC0 signal during recepti on of the first
recei ved bit after the f rame s ync is de tec ted. The IF0 bit is updated wi th thi s
data when the data in the receive shift register transfers into the receive
data regi ster. IF0 is enabl ed only when SC0 is an inpu t flag and the
Synchronous mode is selected; th at i s, when SC0 is programmed as ESSI
in the p ort cont rol regi ster (PCR), t he SYN bit is se t, and t he TE1 a nd SCD0
bits ar e cleared. If it is not enabled, the I F0 bit is clear ed.
Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
Bit Number Bit Name Reset Val ue Description
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-29
unused. Unused bits are read as 0. Data shifts out of these registers MSB first if the SHFD bit is
cleared and LSB first if SHFD is set.
Figu re 7-12 . ESSI Data Path Programming Model (SHFD = 0)
SRD
ESSI Receive Data
Register
Serial
Receive
Shift
Register 24 Bit
WL1, WL0
24-bit Data
000
16-bit Data
12-b i t D ata
8-bit Data
LSB
LSB
LSB
LSBMSB Least Significant
Zero Fill
NOTES:
Data is re ce ived MSB first if SH FD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
16 Bit
12 Bit
8 Bit
(a) Receive Regist ers
STD
ESSI Tran smit Data
Register
ESSI Transmit
Shift Register
24-bit Data
000
16-bit Data
12-bit Data
8-b it D a ta
LSB
LSB
LSB
LSB Least Sig nificant
Zero Fill
(b) Tr ansm it Regist ers
Transmit High Byte Transm it Middle Byte Transmit Low Byte
Transmit High Byte Transm it Middle Byte Transmit Low Byte
23 16 15 8 7 0
23 16 15
8
70
707
0
70
7070
70
MSB
MSB
MSB
NOTES:
Data is transmitted MSB first if
SHFD = 0. 4-bi t fractional format (AL C = 0).
32-bit mode is not shown.
Receive High Byte Receive Middl e Byte Receive Low Byte
Receive High Byte Receive Middl e Byte Receive Low Byte
23 16 15 87 0
23 16 15 70
707 7 0
7070
70
MSB
MSB
MSB
MSB
0
0
DSP56303 User’s Manual, Rev. 2
7-30 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
Figu re 7-13 . ESSI Data Path Programming Model (SHFD = 1)
SR
ES SI Receive Data
Register (Read Only)
ESSI Receive
Shift Register
24-bit Data
000
16-bit Dat a
12-bit Data
8-b it D a ta
LSB
LSB
LSB
LSBMSB
MSB
MSB
MSB
Least Sig nificant
Zero Fill
(a) Receive Registers
ST
ESSI Transmit Data
Register
(Write Only)
ESSI Transmit Shift
Register
24 Bit
WL1, WL0
24-bit Data
000
16-bit Dat a
12-bit Data
8-b it D a ta
LSB
LSB
LSB
LSBMSB
MSB
MSB
MSB
Least Sig nif icant
Zero Fill
16 Bit
12 Bit
8 Bit
(b) Transmit Registers
Receive High Byte Receive Mi ddle Byte Receive Low Byte
Receive High Byte Receive Mi ddle Byte Receive Low Byte
23 16 15 87 0
23 16 15 7 0
707 7 0
70707 0
NOTES:
Data is received MSB first if SHFD = 0
.
24-bi t fractional format (ALC = 0).
32-bi t mode is not shown.
Transmit High Byte Transmit Middle Byt e Transmit Low Byte
Transmit High Byte Transmit Middle Byt e Transmit Low Byte
23 16 15 8 7 0
23 16 15 7 0
707 7 0
70707 0
NOTES:
Da t a is re ceiv e d MSB first if S H F D = 0.
4-bit fr actional for mat (ALC = 0) .
32-bit mo de is not shown.
0
0
0
0
ESSI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-31
7.5.7 ESSI Transmit Data Register s (TX[2–0])
ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01
TX2, TX1, and TX0 are 24-bit write-only registers. Data written into t hese registers
automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) T h e
data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When the
ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data
register empty interrupt has been enabled, the DSP is interrupted whenever a transmit data
register becomes empty.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay while
any status bits affected by this operation are updated. If any of those status bits are read
during the two-cycle delay, the status bit may not reflect the current status.
7. 5. 8 ESSI Time Slot Re gister (TSR)
TSR is effectively a write-only null data register that prevents data transmission in the current
transmit time slot. For timing purposes, TSR is a write-only register that behaves as an alternative
transmit data register, except that, rather than transmitting data, the transmit data signals of all the
enabled transmitters are in the high-impedance state for the current time slot.
7.5.9 Transm it Slot Mask Registers (TSMA, TS MB)
Both transmit slot mask registers are read/write registers. When the TSMA or TSMB is read to
the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the
high-order byte is filled by 0. In Network mode the transmitter(s) use these registers to determine
which action to take in the current transmission slot. Depending on the bit settings, the
transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data word and generate
a transmitter empty condition.
23 22 21 20 19 18 17 16 15 14 13 12
TS15 TS14 TS13 TS12
11109876543210
TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0
—Reserved bit; read as 0; write to 0 0 for fut ure compatibil it y.
(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)
Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA)
DSP56303 User’s Manual, Rev. 2
7-32 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
TSMA and TSMB (as in Figure 7-12 and Figure 7-13) can be seen as a single 32-bit register,
TSM. Bit n in TSM (TSn) is an enable/disable control bit for transmission in slot number N.
When TSn is cleared, all the data signals of the enabled transmitters are tri-stated during transmit
time slot number N. The data still transfers from the enabled transmit data register(s) to the
transmit shift register. However, the TDE and the TUE flags are not set. Consequently, during a
disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled
slots. Data written to the transmit data register when the transmitter empty interrupt request is
serviced transmits in the next enabled transmit time slot. When TSn is set, the transmit sequence
proceeds normally. Data transfers from the TX register to the shift register during slot number N,
and the TDE flag is set. The TSM slot mask does not conflict with the TSR. Even if a slot is
enabled in the TSM, you can chose to write to the TSR to tri-state the signals o f the enabled
transmitters during the next transmission slot. Setting the bits in the TSM affects the next frame
transmission. The frame being transmitted is not affected by the new TSM setting. If the TSM is
read, it shows the current setting.
After a hardware RESET signal or software RESET instruction, the TSM register is reset to
$FFFFFFFF, enabling all 32 slots for data transmission.
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use
these registers to determine which action to take in the current time slot. Depending on the setting
of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and
generate a receiver full condition.
23 22 21 20 19 18 17 16 15 14 13 12
TS31 TS30 TS29 TS28
11109876543210
TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
—Reserved bit; read as 0; write to 0 0 for fut ure comp ati bility.
(ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)
Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB)
23 22 21 20 19 18 17 16 15 14 13 12
RS15 RS14 RS13 RS12
11109876543210
RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
—Reserved bit ; read as 0; write to 0 0 for future compati bili ty.
(ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)
Figure 7-16. ESSI Receive Slot Mask Register A (RSMA)
GPIO Signal s and Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-33
RSMA and RSMB (as in Figure 7-12 and Figure 7-13) can be seen as one 32-bit register, RSM.
Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn is cleared,
all the data signals of the enabled receivers are tri-stated during time slo t number N. Data
transfers from the receive data register(s) to the receive shift register(s), but the RDF and ROE
flags are not set. Consequently, during a disabled slot, no receiver full interrupt is generated. The
DSP is interrupted only for enabled slots. When RSn is set, the receive sequence proceeds
normally. Data is received during slot number N, and the RDF flag is set.
When the bits in t he RSMx are set, the frame being transmitted is unaffected, but the next frame
transmission is affected. If the RSMx is read, it shows the current setting. When the internal data
bus reads RSMA or RSMB, the register contents occupy the two low-order bytes of the data bus,
and the high-order byte is filled by 0.
After a hardware RESET signal or a software RESET instruction, the RSM register is reset to
$FFFFFFFF, enabling all 32 time slots for data transmission.
7.6 GPIO Signals and Reg isters
The functionality of each ESSI port is controlled by three registers: port control register (PCRC,
PCRD), port direction register (PRRC, PRRD), and port data register (PDRC, PDRD).
7.6.1 Port Control Registers (PCRC and PCRD)
The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1.
Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a
PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a PC R[i]
bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware
RESET signal or a software RESET instruction clears all PCR bits.
23 22 21 20 19 18 17 16 15 14 13 12
RS31 RS30 RS29 RS28
11109876543210
RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
–Reserved. Read as zero. Write with zer o for future com patibility.
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)
DSP56303 User’s Manual, Rev. 2
7-34 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
7.6.2 Port Direction Registers (PRRC and PRRD)
The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals
when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively).
When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO) signal. When
PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI) signal. Either a
hardware RESET signal or a software RESET instruction clears all PRRC and PRRD bits.
Table 7-6 summarizes the ESSI port signal configurations.
7.6.3 Port Data Registers (PDRC an d PDRD)
Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal
lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an
input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PCx5 PCx4 PCx3 PCx2 PCx1 PCx0
Note: For Px[5–0], a 0 selects Pxn as th e signal and a 1 selects t he specified ESSI signa l. For ESSI0, the GPIO signals are
PC[5–0] and the ESSI si gnals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO signals are PD[5–0] and
the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0].
= Res er v ed . Re a d as z er o . W ri te wi th zero fo r fu tu re compat ib ility.
Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$F FFAF)
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PRx5 PRx4 PRx3 PRx2 PRx1 PRx0
Note: For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals are
PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding dir ection bits for Port C GPIOs are PRC[5 –0].
The corresponding direct ion bit s for Port D GPIOs are PRD[5– 0].
= Reserved. Read as zer o. Writ e with zero for future compatibi li ty.
Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
Table 7-6. ESSI Port Signal Configurations
PCRC/PCRD[i] PRRC/PRRD[ i] Port Signal[i ] Function
1 X ESSI0/ESSI1
0 0 Port C/Port D GPI
0 1 Port C/Port D GPO
X: The signal setting is irrelevant to t he Port Signal[i] function.
GPIO Signal s and Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 7-35
signal line. If a port signal PC[i] or PD[i] is configured as an output (GPO), a value written to the
corresponding PDRC[i] pr PDRD[i] bit is reflected as a value on the output signal line. Either a
hardware RESET signal or a software RESET instruction clears all PDRC and PDRD bits.
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PDRx5 PDRx4 PDRx3 PDRx2 PDRx1 PDRx0
Note: For bit s 5–0, the value represents the leve l that is written to or read from the associated signal line if i t is
enabled as a GPIO signal by the respective port control register (PCRC or PCRD) bits. For ESSI0, the GPIO
signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The cor responding data bi ts for Port C
GPIOs are PDRC[5– 0]. The corresponding dat a bit s for Port D GPIOs are PDRD[5–0].
= Reserved. Read as zer o. Writ e with zero for futu re compatibility.
Figure 7-20. Port Data Registers (P DRC X:$FFFFBD) (PDRD X: $FFFFAD)
DSP56303 User’s Manual, Rev. 2
7-36 Freescale Semiconductor
Enhanced Synchronous Serial Inter face (ESSI)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-1
Ser ial Communicati on Interf ace (SCI ) 8
The SCI provides a full-duplex port for serial communication with other DSPs, microprocessors,
or peripherals such as modems. The SCI interfaces without additional logic to peripherals that
use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral
interfaces that have non-TTL level signals, such as RS-232, RS-422, and so on. This interface
uses three dedicated signals: transmit data, receive data, and SCI serial clock. It supports
industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data
transmission. SCI asynchronous protocols include a multidrop mode for master/slave operation
with wake-up on idle line and wake-up on address bit capability. This mode allows the
DSP56303 to share a single serial line efficiently with other peripherals.
The SCI consists of separate transmit and receive sections that can operate asynchronously with
respect to each other. A programmable baud rate generator supplies the transmit and receive
clocks. An enable vector and an interrupt vector are included so that the baud-rate generator can
function as a general-purpose timer when the SCI is not using it, or when the interrupt timing is
the same as that used by the SCI.
8.1 Operating Modes
The operating modes for the DSP56303 SCI are as follows:
8-bit synchronous (shift register mode)
10-bit asynchronous (1 start, 8 data, 1 stop)
11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)
11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)
11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)
This mode is used for master/slave operation with wake-up on idle line and wake-up on
address bit capability. It allows the DSP56303 to share a single serial line efficiently with
other peripherals.
These modes are selected by the SCR WD[2–0] bits. Synchronous data mode is essentially a
high-speed shift register for I/O expansion and stream-mode channel interfaces. A gated transmit
and receive clock compatible with the Intel 8051 serial interface mode 0 synchronizes data.
Asynchronous modes are compatible with most UART-type serial devices. Standard RS-232
communication links are supported by these modes. Multidrop Asynchronous mode is
DSP56303 User’s Manual, Rev. 2
8-2 Freescale Semiconductor
Serial Communication I nterface (SCI)
compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial
interface.
8.1.1 Synchronous Mode
Synchronous mode (SCR[WD2–0]=000, Shift Register mode) handles serial-to-parallel and
parallel-to-serial conversions. In Synchronous mode, the clock is always common to the transmit
and receive shift registers. As a controller (synchronous master), the DSP puts out a clock on the
SCLK pin. To select master mode, choose the internal transmit and receive clocks (set TCM and
RCM=0).
As a peripheral (synchronous slave), the DSP accepts an input clock from the SCLK pin. To select
the slave mode, choose the external transmit and receive clocks (TCM and RCM=1). Since there
is no frame signal, if a clock is missed because of noise or any other reason, the receiver loses
synchronization with the data without any error signal being generated. You can det ect an error
of this type with an error detecting protocol or with external circuitry such as a watchdog timer.
The simplest way to recover synchronization is to reset the SCI.
8.1.2 Asynchronous Mode
Asynchronous data uses a data format with embedded word sync, which allows an
unsynchronized data clock to be synchronized with the word if the clock rate and number of bits
per word is known. Thus, the clock can be generated by the receiver rather than requiring a
separate clock signal. The transmitter and receiver both use an internal clock that is 16 times the
data rate to allow the SCI to synchronize the data. The data format requires that each data byte
have an additional start bit and stop bit. Also, two of the word formats have a parity bit. The
Multidrop mode used when SCIs are on a common bus has an additional data type bit. The SCI
can operate in full-duplex or half-duplex modes since the transmitter and receiver are
independent.
8.1.3 Multidrop Mode
Multidrop is a special case of asynchronous data transfer. The key difference is that a protocol
allows networking transmitters and receivers on a single data-transmission line. Inter-processor
messages in a multidrop network typically begin with a destination address. All receivers check
for an address match at the start of each message. Receivers with no address match can ignore the
remainder of the message and use a wakeup mode to enable the receiver at the start of the next
message. Receivers with an address match can receive the message and optionally transmit an
acknowledgment to the sender. The particular message format and protocol used are determined
by the user’s software.
I/O Signals
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-3
8.1.3.1 Transmitting Data and Address Characters
To send data, the 8-bit data character must be written to the STX register. Writing the data
character to the STX register sets the ninth bit in the frame to zero, which indicates that this frame
contains data. To send an 8-bit address, the address data is written to the STXA register, and the
ninth bit in the frame is set to one, indicating that this frame contains an address.
8.1.3.2 Wired-OR Mode
Building a multidrop bus network requires connecting multiple transmitters t o a common wire.
The Wired-OR mode allows this to be done without damaging the transmitters when the
transmitters are not in use. A protocol is still needed to prevent two transmitters from
simultaneously driving the bus. The SCI multidrop word format provides an address field to
support this protocol.
8.1.3.3 Idle Line Wakeup
A wakeup mode frees a DSP from reading messages intended for other processors. The usual
operational procedure is for each DSP to suspend SCI reception (the DSP can continue
processing) until the beginning of a message. Each DSP compares the address in the message
header with the DSP’s address. If the addresses do not match, the SCI again suspends reception
until the next address. If the address matches, the DSP reads and processes the message and then
suspends reception until the next address. The Idle Line Wakeup mode wakes up the SCI to read
a message before the first character arrives.
8.1.3.4 Address Mode Wakeup
The purpose and basic operational procedure for Address Mode Wakeup is the same as for Idle
Line Wakeup. The difference is that Address Mode Wakeup re-enables the SCI when the ninth
bit in a character is set to one (if cleared, this bit marks a character as data; if set, an address). As
a result, an idle line is not needed, which eliminates the dead time between messages.
8.2 I/O Signals
Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO signal or
as a specific SCI signal. Each signal is independent of the others. For example, if only the TXD
signal is needed, the RXD and SCLK signals can be programmed for GPIO. However, at least one
of the three signals must be selected as an SCI signal to release the SC I from reset.
To enable SCI interrupts, program the SCI control registers before any of the SCI signals are
programmed as SCI functions. In this case, only one transmit interrupt can be generated because
the Transmit Data Register is empty. The timer and timer interrupt operate regardless of how the
SCI pins are configured, either as SCI or GPIO.
DSP56303 User’s Manual, Rev. 2
8-4 Freescale Semiconductor
Serial Communication I nterface (SCI)
8.2.1 Receive Data (RXD)
This input signal receives byte-oriented serial data and transfers the data to the SCI receive shift
register. Asynchronous input data is sampled on the positive edge of the receive clock (1 × SCLK)
if the SCI Clock Polarity (SCKP) bit is cleared. RXD can be configured as a GPIO signal (PE0)
when the SCI RXD function is not in use.
8.2.2 Transm it Data (TXD)
This output signal transmits serial data from the SCI transmit shift register. Data changes on the
negative edge of the asynchronous transmit clock (SCLK) if SCKP is cleared. This output is stable
on the positive edge of the transmit clock. TXD can be programmed as a GPIO signal (PE1) when
the SCI TXD function is not in use.
8.2.3 SCI Serial Clock (SCLK)
This bidirectional signal provides an input or output clock from which the transmit and/or receive
baud rate is derived in Asynchronous mode and from which data is transferred in Synchronous
mode. SCLK can be programmed as a GPIO signal (PE2) when the SCI SCLK function is not in use.
This signal can be programmed as PE2 when data is being transmitted on TXD, since the clock
does not need to be transmitted in Asynchronous mode. Because SCLK is independent of SCI data
I/O, there is no connection between programming the PE2 signal as SCLK and data coming out the
TXD signal.
8.3 SCI After Reset
There are several different ways to reset the SCI:
Hardware RESET signal
Software RESET instruction:
Both hardware and software resets clear the port control register bits, which configure all
I/O as GPIO input. The SCI remains in the Reset state as long as all SCI signa ls are
programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI becomes active only
when at least one of the SCI I/O signals is not programmed as GPIO.
Individual reset:
During program execution, the PC2, PC1, and PC0 bits can all be cleared (that is,
individually reset), causing the SCI to stop serial activity and enter the Reset state. All SCI
status bits are set to their reset state. However, the contents of the SCR remain unaffected
so the DSP program can reset the SCI separately from the other internal peripherals.
During individual reset, internal DMA accesses to the data registers of the SCI are not
valid, and the data is unknown.
Stop processing state reset (that is, the STOP instruction)
Executing the STOP instruction halts operation of the SCI until the DSP is restarted,
SCI After Reset
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-5
causing the SCI Status Register (SSR) to be reset. No other SCI registers are affected by
the STOP instruction.
Table 8-1 illustrates how each type of reset affects each register in the SCI.
Table 8-1. SCI Registers After Reset
Register Bit Mnemonic Bit Number Reset Type
HW Reset SW Reset IR Reset ST Reset
SCR REIE 16 0 0 — —
SCKP 15 0 0 — —
STIR 14 0 0 — —
TMIE 13 0 0 — —
TIE 12 0 0 — —
RIE 11 0 0 — —
ILIE 10 0 0 — —
TE 9 0 0 — —
RE 8 0 0 — —
WOMS 7 0 0 — —
RWU 6 0 0 — —
WAKE 5 0 0 — —
SBK 4 0 0 — —
SSFTD 3 0 0 — —
WDS[2–0] 2–0 0 0 — —
SSR R8
FE
PE
OR
IDLE
RDRF
TDRE
TRNE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
TCM 15 0 0 — —
RCM 14 0 0 — —
SCCR SCP 13 0 0 — —
COD 12 0 0 — —
CD[11–0] 11–0 0 0 — —
SRX SRX[23–0] 23–16, 15–8, 7–0 — — — —
STX STX[23–0] 23–0 — — — —
SRSH SRS[8–0] 8–0 — — — —
STSH STS[8–0] 8–0 — — — –
SRSH SCI receiv e shift regist er, STSH—SCI tr ansmit shi ft register
HW Hardware reset is caused by asserting the external RESET signal.
SW Software reset is caused by executing t he RESET instruct ion.
IR Individual reset is caus ed by clearing PCRE (bits 0–2) (conf igured for GPIO ).
ST Stop reset is caus ed by executing the STOP inst ruction.
1 The bit is se t dur ing thi s reset.
0 T he bit is cleared during this res et.
— The bit is not changed during this reset.
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8-6 Freescale Semiconductor
Serial Communication I nterface (SCI)
8.4 SCI Initialization
The SCI is initialized as follows:
1. Ensure that the SCI is in its individual reset state (PCRE = $0). Use a hardware RESET
signal or software RESET instruction.
2. Program the SCI control registers.
3. Configure at least one SCI signal as an SCI signal.
If interrupts are to be used, the signals must be selected, and global interrupts must be enabled
and unmasked before the SCI can operate. The order does not matter; any one of these three
requirements for interrupts can enable the SCI, but the interrupts should be unmasked last (that is,
I[1–0] bits in the Status Register (SR) should be changed last). Synchronous applications usually
require exact frequencies, so the crystal frequency must be chosen carefully. An alternative to
selecting the system clock to accommodate the SCI requirements is to provide an external clock
to the SCI. When the SCI is configured in Synchronous mode, internal clock, and all the SCI pins
are simultaneously enabled, an extra pulse of one DSP clock length is provided on the SCLK pin.
There are two workarounds for this issue:
Enable an SCI pin other than SCLK.
In the next instruction, enable the remaining SCI pins, including the SCLK pin.
Following is an example of one way to initialize the SCI:
1. Ensure that the SCI is in its individual reset state (PCRE = $0).
2. Configure the control registers (SCR, SCCR) according to the operating mode, but do
not enable transmitter (TE = 0) or receiver (RE = 0).
Note: It is now possible to set the interrupts enable bits that are used during the operation. No
interrupt occurs yet.
3. Enable the SCI by setting the PCRE bits according to which signals are used during
operation.
4. If transmit interrupt is not used, write data to the transmitter.
Note: If transmitter interrupt enable is set, an interrupt is issued and the interrupt handler
should write data into the transmitter. The DMA channel services the SCI transmit
request if it is programmed to service the SCI transmitter.
5. Enable transmitters (TE = 1) and receiver (RE = 1) according to use.
SCI Initialization
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Freescale Semiconductor 8-7
Operation starts as follows:
For an internally-generated clock, the SCLK signal starts operation immediately after the
SCI is enabled (Step 3 above) for Asynchronous modes. In Synchronous mode, the SCLK
signal is active only while transmitting (that is, a gated clock).
Data is received only when the receiver is enabled (RE = 1) and after the occurrence of the
SCI receive sequence on the RXD signal, as defined by the operating mode (that is, idle line
sequence).
Data is transmitted only after the transmitter is enabled (TE = 1), and after the
initialization sequence has been transmitted (depending on the operating mode).
8.4.1 Preamble, Break, and Data Transmission Priority
Two or three transmission commands can be set simultaneously:
A preamble (TE is set. )
A break (SBK is set or is cleared.)
An indication that there is data for transmission (TDRE is cleared.)
After the current character transmission, if two or more of these commands are set, the
transmitter executes them in the following order: preamble, break, data.
8.4.2 Bootstrap Loading Through the SCI (Boot Mode $2 or RA)
When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins and
sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits are
write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI.
Appendix A‚ Bootstrap Program shows the complete bootstrap code. This program performs
the following steps:
1. Configures the SCI.
2. Loads the program size.
3. Loads the location where the program begins loading in program memory.
4. Loads the program.
First, the SCI Control Register is set to $000302, which enables the transmitter and receiver and
configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit, and no
parity. Next, the SCI Clock Control Register is set to $00C000, which configures the SCI to use
external receive and transmit clocks from the SCLK pin input. This external clock must be 16
times the desired serial data rate.
The next step is to receive the program size and then the starting address to load the program.
These two numbers are three bytes each loaded least significant byte first. Each byte is echoed
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8-8 Freescale Semiconductor
Serial Communication I nterface (SCI)
back as it is received. After both numbers are loaded, the program size is in A0 and the starting
address is in A1.
The program is then loaded one byte at a time, least significant byte first. After the program is
loaded, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution with
the first instruction loaded.
8.5 Exceptions
The SCI can cause five different exceptions in the DSP, discussed here from the highest to the
lowest priority:
1. SCI receive data with exception status occurs when the receive data register is full with
a receiver error (parity, framing, or overrun error). To clear the pending interrupt, read
the SCI status register; then read SRX. Use a long interrupt service routine to handle the
error condition. This interrupt is enabled by SCR[16] (R EIE).
2. SCI receive data occurs when the receive data register is full. Read SRX to clear the
pending interrupt. This error-free interrupt can use a fast interrupt service routine for
minimum overhead. This interrupt is enabled by SCR[11] (RIE).
3. SCI transmit data occurs when the transmit data register is empty. Write STX to clear
the pending interrupt. This error-free interrupt can use a fast interrupt service routine for
minimum overhead. This interrupt is enabled by SCR[12] (TIE).
4. SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones).
This interrupt is latched and then automatically reset when the interrupt is accepted.
This interrupt is enabled by SCR[10] (ILIE).
5. SCI timer occurs when the baud rate counter reaches zero. This interrupt is
automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[13]
(TMIE).
8.6 SCI Programming Model
The SCI programming model can be viewed as three types of registers:
Control
— SCI Control Register (SCR) in Figure 8-3
— SCI Clock Control Register (SCCR) in Figure 8-4
Status
— SCI Status Register (SSR) in Figure 8-3
Data transfer
— SCI Receive Data Registers (SRX) in Figure 8-7
— SCI Transmit Data Registers (STX) in Figure 8-7
SCI Programming Model
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Freescale Semiconductor 8-9
— SCI Transmit Data Address Register (STXA) in Figure 8-7
The SCI includes the GPIO functions described in Section 8.7, GPI O Signals and Registers, on
page 8-22. The next subsections describe the registers and their bits.
Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1
Mode 0
8-bit Synchron ous Data (Shift Regi ster Mode)
TX
(SSFTD = 1)
One Byte From Shift Register
Mode 2
10-bit A synchronous (1 St art, 8 Data, 1 Stop)
TX
(SSFTD = 1) Start Stop
Bit
Mode 4
11-bi t Asynchronous (1 Start, 8 Data, 1 Even Parit y, 1 Stop)
TX
(SSFTD = 1) Start Stop
Bit
Even
Parity
Mode 5
11-bit Asynchr onous (1 Start, 8 Data, 1 Odd Pari ty, 1 Stop)
TX
(SSFTD = 1) Start D0 or
Data
Type
Stop
Bit
Odd
Parity
Mode 6
11-bit Asynchr onous Multi drop (1 St art, 8 Data, 1 Data Type, 1 Stop)
TX
(SSFTD = 1) Start Stop
Bit
Data
Type
D7 D6 D5 D4 D3 D2 D1 D0
WDS2 WDS1 WDS0
000
• Modes 1, 3, and 7 are reserved.
• D0 = LSB; D7 = MSB
• Data is tr ansm itted and received LSB first if SSFTD = 0, or MSB fir st if SSFTD
= 1
0 = Data Byte
Data Type: 1 = Addres s Byte
D0 or
Data
Type
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1 D0 or
Data
Type
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1 D0
WDS2 WDS1 WDS0
010
WDS2 WDS1 WDS0
100
WDS2 WDS1 WDS0
101
WDS2 WDS1 WDS0
110
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Serial Communication I nterface (SCI)
8.6.1 SCI Control Register (SCR)
The SCR is a read/write register that controls the serial interface operation.
Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2
Mode 0
8-bit Synchro nous Data (Shift Register Mode)
TX
(SSFTD = 0)
One Byte From Shift Register
Mode 2
10-bit Asynchronous (1 St art, 8 Data, 1 Stop)
TX
(SSFTD = 0)
D7 or
Data
Type
Stop
Bit
Mode 4
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
TX
(SSFTD = 0)
D7 or
Data
Type
Stop
Bit
Even
Parity
Mode 5
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
TX
(SSFTD = 0) Start
Bit
D7 or
Data
Type
Stop
Bit
Odd
Parity
Mode 6
11-bit Asynchr onous Multi drop (1 St art, 8 Data, 1 Data Type, 1 Stop)
TX
(SSFTD = 0) Start
Bit Stop
Bit
Data
Type
• Modes 1, 3, and 7 are re served.
• D0 = LSB; D7 = MSB.
• Dat a is transmitted and received LSB first if SSFTD = 0,
or MSB first if SSFTD = 1.
D0 D1 D2 D3 D4 D5 D6 D7
010
D0 D1 D2 D3 D4 D5 D6
WDS2 WDS1 WDS0
000
100
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
Start
Bit
WDS2 WDS1 WDS0
Start
Bit
WDS2 WDS1 WDS0
101
WDS2 WDS1 WDS0
D0 D1 D2 D3 D4 D5 D6 D7
110
WDS2 WDS1 WDS0
0 = Data Byte
Data Type: 1 = Addres s Byte
SCI Programming Model
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Freescale Semiconductor 8-11
.
23 22 21 20 19 18 17 16
REIE
15 14 13 12 11 10 9 8
SCKP STIR TMIE TIE RIE ILIE TE RE
76543210
WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0
—Reserv ed bit ; read as 0; writ e to 0 for future compatibility .
Figure 8-3. SCI Control Register (SCR)
Table 8-2. SCI Control Register (SCR) Bit Definitions
Bit
Number Bit
Name Reset
Value Description
23–17 0 Reserved. Writ e to 0 for future compatibil ity.
16 REIE 0 Receive with Except ion I nterrupt Enabl e
Enables/disables the SCI re ceive data wi th exception interrupt. If REIE is cl eared, t he
recei ve data wi th excepti on inte rrupt is dis abled. I f both REIE and RDRF are s et, and PE,
FE, and OR are not all cleared, the SCI requests an SCI receive data wi th exception
interrupt from the i nterr upt controller. Either a hardware RESET si gnal or a software
RESET instruction clears REIE.
15 SCKP 0 SCI Clock Polar it y
Control s the clock pol arity sourced or received on the cl ock signal (SCLK), eli m inating
the need for an external inverter. When SCKP is cleared, the cl ock polarity is positive ;
when SCKP is set, the clock polar it y is negative. In Synchronous mode, positive pol ari ty
means that the clock is normally positive and transitions negative dur ing valid data.
Negative polarity means that the clock is normally negative and transitions positive
during vali d data. I n Asynchronous mode, positi ve polarit y m eans that t he rising edge of
the cl ock o ccurs i n the c ent er of the pe ri od that data i s va lid. Negat ive pol ari ty means that
the fal li ng edge of the clock occurs durin g the cent er of the peri od that data is valid.
Either a hardware RESET signal or a sof tware RESET instruction clears SCKP.
14 STIR 0 Timer Interrupt Rate
Controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is cleared, the
divi de-by-32 is i nserted in the chai n. When STIR is set, th e divi de-by-32 is bypas sed,
thereby i ncreasing time r res olution by a factor of 32. Either a hardware RESET signal or
a softwar e RES E T inst ruction clears this bi t. To ensure pr oper operation of the timer,
STIR must not be changed during timer oper ation (that is, i f TMIE = 1).
13 TMIE 0 Ti mer Interrupt Enable
Enables/disabl es the SCI timer int errupt. If TMIE is set, timer int err upt requests are sent
to the interrupt contr oll er at the rate set by the SCI clock regi ster. The ti me r in terrupt i s
automaticall y cleared by the timer interrupt acknowledge from the i nterr upt controll er.
This feature all ows DSP programmers to use the SCI baud rat e generator as a simpl e
period ic int errup t generat or if the SC I is not in use, if exter nal clo cks ar e used fo r the SC I,
or if period ic inte rrupt s a re needed at the SCI bau d rate. The SCI inter nal clo ck is divided
by 16 (to match the 1 × SCI baud rate) f or t imer inter rupt generation. This tim er does not
require that any SCI signals be configured for SCI use to oper ate. Either a hardware
RESET si gnal or a software RESET instruction clears TMIE.
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Serial Communication I nterface (SCI)
12 TIE 0 SCI Transmit In terrup t Enable
Enables/ disables the SCI trans mit data interrupt. If TIE is cleared, transmit data
inter rupts are disabl ed, and the transmit data register empty (TDRE) bit in th e SCI status
register must be polled to determi ne whether the transmit data registe r is empty. If both
TIE and TDRE are set, the SCI requests an SCI tr ansmit data interrupt from the interrupt
contro ll er. Either a hardware RESET signal or a so ftware RESET instruction clears TIE.
11 RIE 0 SCI Receive Interrupt Enable
Enables/disables the SCI re ceive data i nterrupt. If RI E is cleared, t he receive data
interrupt is disabled, and the RDRF bi t in the SCI s tatus register must be polled to
determine whet her t he recei ve data re gister is f ull . If both RIE and RDRF ar e set, the SCI
requests an SCI receive data interrupt from the interrupt controller. Receive interrupts
with exception hav e higher priority than nor m al r eceive data interrupts. Ther efore, if an
exception occurs (that is, i f PE, FE, or OR are set ) and REIE is set, the SCI requ ests an
SCI receive data wit h excepti on inter rupt f rom the interrupt controller. Either a hardware
RESET si gnal or a software RESET instruction clears RIE.
10 ILIE 0 Idle Line Interrupt Enable
When ILIE is set, the SCI interrupt occurs when IDLE ( SCI status register bit 3) is set.
When ILIE is cleared, the IDLE interrupt is disabled. Either a hardware RESET signal or
a software RESET instruction clears ILIE. An internal flag, t he shift register idle interrupt
(SRIINT) fl ag, is the int errupt req uest to th e int errupt cont rol ler. SRIINT is not direct ly
accessible t o the user. When a vali d start bit is received, an idle int errupt is gene rated if
both IDLE and IL IE are set. The idl e interr upt acknowledge from th e int errupt contro ll er
clears this in terrupt re quest. The idle interrupt i s not asserted agai n until at least one
character has been received. The resul ts are as follows:
• The IDLE bit shows the real st atus of th e receive line at all t imes.
• An idl e inter rupt i s genera ted once f or ea ch idle s tate, no matter how long th e idle st ate
lasts.
9TE0Transm itter Enable
When TE is set, the transmitter is enabled. W hen TE is cleared, the transmitter
completes transmission of data in the SCI transmit data shift register , and then the serial
output is f orced high (t hat is, idle). Data present in the SCI transmit data register (STX) i s
not tra nsm it ted. STX can be written and TDRE clear ed, but t he data is not tr ansferred
into the shift register. TE does not inhibit TDRE or transmit interr upts. Either a hardware
RESET si gnal or a software RESET instruction clears TE.
Setti ng TE causes the transmi tter to sen d a preamble of 10 or 11 consecutive ones
(depending on WDS), givi ng you a convenient way to ensure th at t he line goes idle
before a new messag e starts. To force this se paration of messages by the minimum idle
line time, we recommend the fol lowing sequence:
1. Write th e last byte of the fi rst message to STX.
2. Wait for TDRE to go high, indic ating the las t byt e has been transferred to the
transmit shi ft register.
3. Clear TE and set TE to queue an id le l ine preamble to follow immediatel y the
transmission of the last charac ter of the message (including the st op bit).
4. Write the first byte of the second message t o STX.
If the fir st byte of the second messa ge is not transferred to STX prior to the fi nish of the
preamble tran sm ission, the transmi t data l ine remains idle until STX is finally written.
Ta ble 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number Bit
Name Reset
Value Description
SCI Programming Model
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Freescale Semiconductor 8-13
8RE0Receiver Enabl e
When RE is set, th e recei ver is enabled. When RE is cleared, the receiver is di sabled,
and data transfer from the receive shift register t o the receive data register (SRX) is
inhibited. If RE is cleared while a character is bei ng received, the reception of the
charact er compl etes befo re the recei ver is disabl ed. RE does not i nhibi t RDRF or recei ve
interrupts. Either a hardware RESET signal or a software RESET instruction clears RE.
7WOMS0Wire d-OR Mode Select
When WOMS is set, the SCI TXD driver is program me d to fu nction as an open-drai n
output and can be wir ed together with other TXD signals in an appropriate bus
configurati on, such as a master-slave multidrop config uration. An external pullu p resistor
is required on the bus. When WOMS is cleared, the TXD si gnal uses an active internal
pullu p. Ei the r a hard ware RESET signal or a softwar e RESET inst ruction clears W OMS.
6RWU0Receiver Wakeup Enable
When RWU is set and t he SCI i s in Asyn chr onous mo de, the wakeup func tion i s enabl ed;
that is, the SCI is asleep and can be awakened by the event defined by the WAKE bit. In
Sleep st ate, all interrupts and all recei ve flags except IDLE ar e disabled. When the
recei ver wakes up, RW U is cleared by the wakeup hardware. You can also clear t he
RWU bit t o wake up the receiver. You can use RWU to ignore messages that ar e for
other dev ices on a multidrop serial network. Wakeu p on idl e line (i. e., WAKE is cleared)
or wakeup on address bit (i. e., WAKE is set) must be chosen. When WAKE is cleared
and RWU is s et, the receiver d oes not resp ond to data on the dat a line unti l an idle l ine is
detected. When WAKE is set and RWU is set, the r eceiver does not respond to dat a on
the data l ine unti l a data frame with Bit 9 set is detected.
When the receiver wakes up, the RW U bit is cleared, and the first f rame of data is
recei ved. If interru pts are enabled, the CPU is i nterrupt ed and the inter rupt rout ine reads
the message header to determine whether the message is intended for this DSP. If the
messag e is fo r th is DSP, the message is r eceived, and RWU is set to wait for the next
message. If t he message is not for this DSP, the DSP immediatel y sets RWU. Setting
RWU causes the DSP to ignore the remai nder of the mes sage and wait for the next
messag e. Either a hardwa re RESET si gnal or a software RESET ins truct ion clear s RWU.
RWU is i gnored in Synchronous mode.
5 WAKE 0 Wakeup Mode S elect
When WAKE is cleared , th e wakeup on Idle Li ne mode is sel ected. In the wake up on idle
line mode, t he SCI receiv er is re-enabl ed by an i dle str ing of at least 10 or 11 (d epending
on WDS mode) c onsec utive o nes. The t ransm itter’ s soft ware mus t provide t hi s idle string
between consecutive messages. The idl e str ing cannot occur within a vali d m essage
because each word frame there contains a sta rt bit that is 0.
When WAKE is set, the wakeup on address bi t mode is selected. In the wake up on
address bit mode, the SCI recei ver is re-enabled when t he last (eigh th or ninth) data bit
recei ved in a charact er (fram e) is 1. The ninth data bit is the addre ss bit (R8) in the 11-bit
multidrop mode; the ei ghth data bit is the address bit in the 10-bit asynchronous and
11-bit asynchronous with par ity modes. Thus, the rece ived character is an addre ss that
has to be processed by all sleeping processors—that is, each processor has to com pare
the recei ved character with its own addr ess and decide whether to receive or ignore all
following character s.
Ta ble 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number Bit
Name Reset
Value Description
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Serial Communication I nterface (SCI)
4 SBK 0 Send Break
A break is an all-zero word f rame— a start bit 0, characters of all zeros (inclu ding any
parit y), and a stop bit 0 (t hat is, ten or eleven zeros, depend ing on the mode selected). If
SBK is set and the n cleared, th e tra nsm itt er finish es transmitt ing the curr ent frame,
sends 10 or 11 0s, and r evert s to idl e or sendi ng data. If SBK remai ns set, t he trans mitte r
continually sends whole frames of 0s (10 or 11 bits with no stop bit). At the end of the
break code, the tran sm itter sends at least one high (set) bit before transmitting any data
to guarant ee recognitio n of a val id star t bit. Break can signal an unusual condit ion,
messag e, and so on, by for cing a frame err or; the frame er ror is caused by a missing
stop bi t.
3 SSFTD 0 SCI Shift Direction
Determi nes the order in which the SCI dat a shif t regi sters shif t data i n or out : MSB fir st
when set, LSB first when cleared. The pari ty and data t ype bits do not change th eir
position in the frame, and they remain adjacent to the stop bit.
2–0 WDS 0 Wor d Select
Select the for m at of transmitt ed and rece ived data. Asynchronous modes ar e compatible
with most UART-type serial devices, and t hey support standar d RS-232 comm unication
link s. Multidrop Asynchronous mode is compatible with th e MC68 681 DUART, the
M68HC11 SCI inte rface, and the I ntel 8051 serial interfac e. Synchronous data mode is
essentiall y a high-speed shift register f or I/O expansion and stream-mode channel
interfaces. You can synchroni ze data by using a gated transmit and r eceive clock
compatible with the Intel 8051 seri al i nterface mode 0. When odd parity is selected, the
transmitter counts the num ber of ones in the data word. I f the total is not an odd num ber,
the par ity bi t is set, thus pr oducing an odd number . If the rec eiver counts a n even number
of ones, an er ror in trans m ission has occurred. When even pari ty is sel ected, an even
number m ust result from the calculat ion performed at both ends of the line, or an error i n
transmission has occurred.
WDS2 WDS1 WDS0 Mode Word Formats
0000
8-Bit Synchro nous Data (shift registe r mode)
0011
Reserved
0102
10-Bit Asynchronous (1 start, 8 data, 1 stop)
1113
Reserved
1004
11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 sto p)
1015
11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
1106
11-Bit Mult idrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
0117
Reserved
Ta ble 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number Bit
Name Reset
Value Description
SCI Programming Model
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Freescale Semiconductor 8-15
8.6.2 SCI Status Register (SSR)
The SSR is a read-only register that indicates the status of the SCI.
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
76543210
R8 FE PE OR IDLE RDRF TDRE TRNE
—Reserved bit; read as 0; write to 0 for future compatibilit y.
Table 8-3. SCI Status Register
Table 8-4. SCI Status Register (SSR) Bit Definitions
Bit
Number Bit
Name Reset
Value Description
23–8 0 Reserved. Write to 0 for future compatibility.
7R80Rece ived B it 8
In 11- bit Asynchronous Multidrop mode, t he R8 bit indicates whether the r eceived byte
is an address or data. R8 is s et f or addresses and is cleared for d ata. R8 i s not affected
by reads of the SRX or SCI st atus register. A hardware RESET signal, a software
RESET inst ructi on, an SCI individual reset, or a STOP in structi on clears R8.
6FE0Framing Er ror Fl ag
In Asynchronous mode, FE is set when no stop bit is detected in the data string
recei ved. FE an d RDRE are set s imult aneously when the re ceived wor d is t ransfe rred to
the SRX. However, the FE flag inhibits further transfer of data i nto the SRX until i t i s
cleared. FE is cl eared when the SCI status register is read followe d by a read of the
SRX. A hardware RESET signal, a soft ware RESET instr uction, an SCI indi vidual reset,
or a STOP inst ruction cl ears FE. I n 8-bi t Synchr onou s mode, FE i s always cl eared. If the
byte received causes both framing and overrun err ors, the SCI receiver re cognizes only
the overrun err or.
5PE0Parit y Err or
In 11- bit Asynchronous modes, PE is set when an incor rect parity bit is detected in the
received char acter. PE and RDRF are set simultaneously when the received word is
tran sferr ed to the SRX. If PE i s set, fur ther dat a trans fer into t he SRX is not inhib ited. PE
is cl eared when the SCI status r egister is read, fol lowed by a read of SRX. A h ardware
RESET signal, a software RESET instruction, an SCI individual reset, or a STOP
instruction also clears PE. I n 10-bit Asynchr onous mode, 11-bi t multidr op mode, and
8-bi t Synchr onous mod e, the PE bi t is al ways clea red sinc e there i s no pari ty bit in these
mode s. If the byte recei ved causes both parit y and overrun error s, t he SCI receiver
recognizes only the overrun error.
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Serial Communication I nterface (SCI)
4OR0Overrun Error Flag
Set when a byte i s ready to be t ransferr ed from the recei ve shift regi ster to the receive
data registe r (SRX) that i s already fu ll (RDRF = 1). The receive shif t regist er dat a is not
transferred to the SRX. The OR flag indicates that character(s) in the received data
stream may have been l ost. The only valid data i s located in the SRX. OR is cleared
when the SCI status r egister is r ead, followed by a read of SRX. The OR bit clears the
FE and PE bits; that is, overrun error has higher priority than FE or PE. A hardware
RESET signal, a software RESET instruction, an SCI individual reset, or a STOP
instruction clears OR.
3IDLE0Idle Line Flag
Set when 10 (or 11) consecutive ones are received. IDLE is cl eared by a start-b it
detecti on. The IDLE status bit represents the st atus of t he receive line. The transition of
IDLE from 0 to 1 can cause an IDLE interrupt (ILIE).
2 RDRF 0 Receive Data Register Full
Set when a val id character is transferr ed to t he S CI rec eive data regist er f rom the SCI
receive shif t registe r (r egardless of the error bits cond ition). RDRF is cl eared when the
SCI receive data register is read.
1 TDRE 1 Transmit Data Register Empty
Set when the SCI transmit data register is empt y. When TDRE is set , new data can be
written to one of the SCI transmit data registers (STX) or the transmit data address
regi ster ( STXA). TDRE is clear ed when the SCI trans mit data regist er is writ ten. Either a
hardwar e RESET signal, a software RESET i nstructio n, an SCI individual rese t, or a
STOP in struction sets TDRE.
In Synchr ono us mode, when the in ternal SCI clock is in use , there i s a de lay of up to 5. 5
serial clock cycl es be tween the tim e that STX is written unti l TDRE is set, ind icati ng the
data has been transferred from the STX to the transmit shi ft register. There is a delay of
2 to 4 serial clock cycles between wri ting STX and loading the t ransmit shift register; in
addition, TDRE is set in the middle of transmitti ng the second bit . Wh en using an
external serial transmit cl ock, if the clock stops, t he SCI transmitter st ops. TD RE is not
set until the middle of t he second bit transmitted after the ext ernal clock start s. Gating
the external cl ock o ff after the first bi t has been tra nsm itt ed delays TDRE indefinitely.
In Asynchronous mode, the TDRE flag is not set i m m ediately aft er a word is transferred
from t he STX or STXA to the transmit shift register nor when the word f irst begins to be
shi fte d ou t . TDR E is se t 2 cyc le s (o f th e 1 6 × cl ock) after the start bit; that is, 2 (16 ×
clock) cycles int o the transmission ti m e of the firs t data bit.
0 TRNE 1 Transmitter Empty
This flag bit is set when both the t ransmit shift register and transmit data register (STX)
are empty, indicating that there is no data in the t ransm itter. When TRNE is set, data
writ ten to one of the three STX locations or to the transmi t data address regi ster (STXA)
is t ransferr ed to the transmit shift register and is the first data transmitted. TRNE is
cleared when a write into STX or STXA clears TDRE or when an idle, pr eam ble, or
break is transmitted. W hen set , TRNE indicates that the t ransm itter is empty; therefore,
the data written to STX or STXA i s tr ansm itted next. That i s, t here is no word in the
transmit shi ft regist er being transmitted. This procedure i s useful when initiating the
transfer of a message (that is, a string of characters).
Table 8-4. SCI Status Register (SSR) Bit Definitions (Continued)
Bit
Number Bit
Name Reset
Value Description
SCI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-17
8.6.3 SCI Clock Control Register (SCCR)
The SCCR is a read/write register that controls the selection of clock modes and baud rates for
the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware RESET
signal.
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
TCM RCM SCP COD CD11 CD10 CD9 CD8
7 6 543210
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
R e ser ved. R e ad as 0. Wri te to 0 for futur e co m p a t ibility .
Figure 8-4. SCI Clock Control Register (SCCR)
Ta ble 8-5. SCI Clock Control Register (SCCR) Bit Definitions
Bit
Number Bit Name Reset
Value Description
23–16 0 Reserved. Wr ite to 0 for futur e com patibility.
15 TCM 0 Transmit Clock Source
Selects whether an internal or exter nal clock is used for the transmit ter. I f TCM is clear ed,
the int ernal cl ock is used. If TCM is set, t he external clock (fr om the SCLK si gnal) i s used.
14 RCM 0 Receive Cl ock Mode Source
Selects whether an internal or external clock is used for the receiver. If RCM is clear ed, the
internal clock is used. If RCM is set, the external clock (from t he SCLK signal) is used.
TCM RCM TX Clock RX Clock SCLK Mode
0 0 Internal Internal Output Synchronous/asynchronous
0 1 Internal External Input Asynchronous onl y
1 0 External Internal Input Asynchronous only
1 1 External External Input Synchronous/asynchronous
13 SCP 0 Cl ock Prescaler
Selects a divi de by 1 (SCP is cl eared) or divide by 8 (SCP is set) prescaler for the cl ock
divi der. The output of the prescaler is further divided by 2 to form the SCI cl ock.
12 COD 0 Clock O ut Di vider
The clock output divider i s cont rolled by COD and the SCI mode. If t he SCI mode is
synchronous, the output divider i s fi xed at divide by 2. If the SCI mode is asynchronous,
either:
• If COD is cleared and SCLK is an output (that is, TCM and RCM are both cleared), then
the SCI clock is di vided by 16 before being output to the SCLK signal. Thus, the SCLK
output is a 1 × clock.
• If COD is set and SCLK is an output, t he SCI cl ock is fed di rectly out to the SCLK signal.
Thus, the SCLK outp ut i s a 16 × baud clock.
11–0 CD[11–0] 0 Clock Divider
Specifies the divide rati o of th e prescale div ider in the SCI cl ock generator . A divide ratio
from 1 to 4096 (CD[11–0] = $000 to $FFF) can be sel ected.
DSP56303 User’s Manual, Rev. 2
8-18 Freescale Semiconductor
Serial Communication I nterface (SCI)
The SCI clock determines the data transmission (baud) rate and can also establish a periodic
interrupt that can act as an event timer or be used in any other timing function. Bits CD11– CD0,
SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1 when the
periodic time-out occurs, the SCI timer interrupt is recog nized and pending. The SCI timer
interrupt is automatically cleared when the interrupt is serviced. This interrupt occurs every time
the periodic timer times out.
Figure 8-5 shows the block diagram of the internal clock generation circuitry with the formula to
compute the bit rate when the internal clock is used.
As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode or
one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the
same source, but that source may be the internal SCI clock if the SCI is configured as a master
device or an external clock if the SCI is configured as a slave device. Asynchronous modes may
use clocks from the same source (internal or external) or different sources for the TX clock and
the RX clock.
For synchronous operation, the SCI uses a clock that is equal to the two times the desired bit rate
(designated as the 2 × clock) for both internal and external clock sources. It must use the same
source for both the TX and RX clock. The internal clock is used if the SCI is the master device
Figure 8-5. SCI Baud Rate Generator
Fcore Divide
By 2 12- bit Counter Prescaler:
Divi de by
1 or 8
Internal Clock
SCI Core Logic
Uses Divi de by 16 for
Asynchronous
Uses Divi de by 2 for
Synchronous
COD
SCKP
If Asynchronous
Divi de by 1 or 16
If Synchr onous
Divide By 2
SCLK
Divide
By 2
Divide
by 16
Timer
Interrupt
(STMINT)
Fcore
bps = 64 × (7( S CP) + 1) × CD + 1)
where: SCP = 0 or 1
CD = $000 to $FFF
STIR
SCKP = 0 +
SCKP = 1 -
CD[11–0] SCP
SCI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-19
and the external clock is used if the SCI is the slave device, as noted above. The clock is gated
and limited to a maximum frequency equal to one eighth of the DSP core operating frequency
(that is, 12.5 MHz for a DSP core frequency of 100 MHz).
For asynchronous operation, the SCI can use the internal and external clocks in any combination
as the source clocks for the TX clock and RX c lock. If an external clock is used for the SCLK
input, it must be sixteen times the desired bit rate (designated as the 16 × clock), as indicated in
Figure 8-6. When the internal clock is used to supply a clock to an external device, the clock can
use the actual bit rate (designated as the 1 × clock) or the 16 × clock rate, as determined by the
COD bit. The output clock is continuous.
When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of
the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the
positive edge and is stable on the negative edge. The received data on the RXD signal is sampled
on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the serial clock.
8.6.4 SC I Data Register s
The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7.
There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive
Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX
or STXA) and a parallel-to-serial Transmit Shift Register.
Figure 8-6. 16 x Serial Clock
RX, T X Data
(SSFTD = 0)
Idle Li n e
Start
Select 8-or 9-bit Words
x1 Clock
x16 Clock
(SCKP = 0)
10 2345678
Stop Start
DSP56303 User’s Manual, Rev. 2
8-20 Freescale Semiconductor
Serial Communication I nterface (SCI)
8.6.4.1 SCI Receive Register (SRX)
Data bits received on the RXD signal are shifted into the SCI receive shift register. When a
complete word is received, the data portion of the word is transferred to the byte-wide SRX. This
process converts serial data to parallel data and provides double buffering. Double buffering
promotes flexibility and increased throughput since the programmer can save (and process) the
previous word while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the
contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the
data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed into the
middle byte of the bus, and when SRXH is read, the contents of SRX are placed into the high
byte with the remaining bits are read as 0s. This way of mapping SRX efficiently packs three
bytes into one 24-bit word by ORing three data bytes read from the three addresses.
The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial word.
The SCR receive clock mode (RCM) defines the clock source.
Figu re 8-7. SCI Programming Model—Data Registers
SRX
SRX
SRX
RXD SCI Receive Data Shift Register
Note: SRX is the same regist er decoded at thr ee differen t addresses.
STX
STX
STX
TXDSCI Transmi t Dat a Shif t Regi ster
Note: Bytes are masked on the f ly.
STX is the same register dec oded at four different addresses.
STXA
(a) R e c ei v e D a ta Reg iste r
(b) Transmit Data Regi ster
SCI Rece ive Data Register High (Read Only)
SCI Recei ve Data Register Middle (Read Only
)
SCI Recei ve Data Register Low (Read Only)
078151623
078151623
078151623
SC I T ra n s mit D a ta Re g is t er Hi gh (Wr ite On ly )
SCI Transmit Data Register Middle (Write Only
)
SCI Transmit Data Register Low (Write Only)
SCI Transmi t Data Address Regist er (Writ e Onl
y)
SCI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-21
In Asynchronous mode, the start bit, the eight data bits, the address/data indicator bit or the parity
bit, and the stop bit are received, respectively. Data bits are sent LSB first if SSFTD is cleared,
and MSB first if SSFTD is set. In Synchronous mode, a gated clock provides synchronization. In
either Synchronous or Asynchronous mode, when a complete word is clocked in, the contents of
the shift register can be transferred to the SRX and the flags; RDRF, FE, PE, and OR are changed
appropriately. Because the operation of the receive shift register is transparent to the DSP, the
contents of this register are not directly accessible to the programmer.
8.6.4.2 SCI Transmit Register (STX)
The transmit data register is a one-byte-wide register mapped into four addresses as S TXL,
STXM, STXH, and STXA. In Asynchronous mode, when data is to be transmitted, STXL,
STXM, and STXH are used. When STXL is written, the low byte on the data bus is transferred to
the STX. When STXM is written, the middle byte is transferred to the STX. When STXH is
written, the high byte is transferred to the STX. This structure makes it easy for the programme r
to unpack the bytes in a 24-bit word for transmission. TDXA should be written in 11-bit
asynchronous multidrop mode when the data is an address and the programmer wants to set the
ninth bit (the address bit). When STXA is written, the data from the low byte on the data bus is
stored in it. The address data bit is cleared in 11-bit asynchronous multidrop mode when any of
STXL, STXM, or STXH is written. When either STX (STXL, STXM, or STXH) or STXA is
written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically, but not
immediately, after the last bit from the previous word is shifted out; that is, the transmit sh ift
register is empty. Like the receiver, the transmitter is double-buffered. However, a delay of two
to four serial clock cycles occurs between when the data is transferred from either STX or STXA
to the transmit shift register and when the first bit appears on the TXD signal. (A serial clock cycle
is the time required to transmit one data bit.)
The transmit shift register is not directly addressable, and there is no dedicated flag for this
register. Because of this fact and the two- to four-cycle delay, two bytes cannot be written
consecutively to STX or STXA without polling, because the second byte might overwrite the first
byte. Thus, you should always poll the TDRE flag prior to writing STX or STXA to prevent
overruns unless transmit interrupts are enabled. Either STX or STXA is usually written as part of
the interrupt service routine. An interrupt is generated only if TDRE is set. The transmit shift
register is indirectly visible via the SSR[TRNE] bit.
In Synchronous mode, data is synchronized with the transmit clock. That clock can have either an
internal or external source, as defined by the TCM bit in the SCCR. The length and format of the
serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR. In
Asynchronous mode, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and the
MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are
transmitted in that order. The data to be transmitted can be written to any one of the three STX
DSP56303 User’s Manual, Rev. 2
8-22 Freescale Semiconductor
Serial Communication I nterface (SCI)
addresses. If SCKP is set and SSHTD is set, SCI Synchronous mode is equiv alent to the SSI
operation in 8-bit data on-demand mode.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit does not reflect its current status. For details see
the DSP56300 Family Manual.
8.7 GPIO Signals and Reg isters
Three registers control the GPIO functionality of the SCI pins: Port E control register (PCRE),
Port E direction register (PRRE) and Port E data register (PDRE).
8.7.1 Port E Control Register (PCRE)
The read/write PCRE controls the functionality of SCI GPIO signals. Each of the PCRE[2–0] bits
controls the functionality of the corresponding port signal. When a PCRE[i] bit is set, the
corresponding port signal is configured as an SCI signal. When a PC [i] bit is cle ared, the
corresponding port signal is configured as a GPIO signal. A hardware RESET signal or a software
RESET instruction clears all PCRE bits.
8.7.2 Port E Direction Register (PRRE)
The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is
configured as GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the GPIO
port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[i] is
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PE2/
SCLK PE1/
TXD PE0/
RXD
Note: For bits 2–0, a 0 selects PEn as the signal and a 1 select s the specified SCI signal.
= Reserved. Read as zero. Write to zero for future compatibility.
Figure 8-8. Port E Control Register (PCRE X:$FFFF9F)
GPIO Signal s and Registers
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 8-23
configured as input. A hardware RESET signal or a software RESET instruction clears all PRRE
bits.
8.7.3 Port E Data Register (PDRE)
Bits 2–0 of the read/write 24-bit PDRE writes data to or reads data from the associated SCI signal
lines when configured as GPIO signals. If a port signal PE[i] is configured as an input (GPI), the
corresponding PDRE[i] bit reflects the value present on the input signal line. If a port signal PE[i]
is configured as an output (GPO), a value written to the corresponding PDRE[i] bit is reflected as
a value on the output signal line. Either a hardware RESET signal or a software RESET
instruction clears all PDR bits.
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PRRE2 PRRE1 PRRE0
Note: For b it s 2–0, a 0 configur es PEn as a GPI and a 1 confi gures PEn as a GPO. For the SCI, the GPIO signals are
PE[2–0]. The corresponding direction bits for Port E GPIOs are PRRE[ 2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 8-9. Port E Direction Register (PRRE X:$FFFF9E)
23 22 21 20 19 18 17 16 15 14 13 12
11109876543210
PDRE2 PDRE1 PDRE0
Note: For bi ts 2–0, the value represents the le vel that is wr it ten to or r ead fr om the associated signal li ne if enabled as a
GPIO signal by the PCRE bits. For SCI, the GPIO signal s are PE[2–0]. Th e corresponding data bi ts are PDRE[2–0].
= Res er v ed . Re a d as z er o . W ri te wi th zero fo r fu tu re compat ib ility.
Figure 8-10. Port Data Registers (P DRE X:$F FFF9D )
DSP56303 User’s Manual, Rev. 2
8-24 Freescale Semiconductor
Serial Communication I nterface (SCI)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-1
Triple Timer Module 9
The timers in the DSP56303 internal triple timer module act as timed pulse generators or as
pulse-width modulators. Each timer has a single signal that can function as a GPIO signal or as a
timer signal. Each timer can also function as an event counter to capture an event or to measure
the width or period of a signal.
9.1 Overview
The timer module contains a common 21-bit prescaler and three independent and identical
general-purpose 24-bit timer/event counters, each with its own register set. Each timer has the
following capabilities:
Uses internal or external clocking
Interrupts the DSP56303 after a specified number of events (clocks) or signals an external
device after counting internal events
Triggers DMA transfers after a specified number of events (clocks) occurs
Connects to the external world through one bidirectional signal, designated
TIO[0– 2] for timers 0–2.
When TIO is configured as an input, the timer functions as an external event counter or measures
external pulse width/signal period. When TIO is configured as an output, the timer functions as a
timer, a watchdog timer, or a pulse-width modulator. When the timer does not use TIO, it can be
used as a GPIO signal (also called TIO[0–2]).
9.1.1 Triple Timer Module Block Diagr am
Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit
Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and
three timers. Each timer can use the prescaler clock as its clock source.
DSP56303 User’s Manual, Rev. 2
9-2 Freescale Semiconductor
Trip le T imer Module
9.1.2 Individual Timer Block Diagram
Figure 9-2 shows the structure of an individual timer block. The DSP56303 treats each timer as a
memory-mapped peripheral with four registers occupying four 24-bit words in the X data
memory space. The three timers are identical in structure and function. Either standard polled or
interrupt programming techniques can be used to service the timers. A single, generic timer is
discussed in this chapter. Each timer includes the following:
24-bit counter
24-bit read/write Timer Control and Status Register (TCSR)
24-bit read-only Timer Count Register (TCR)
24-bit write-only Timer Load Register (TLR)
24-bit read/write Timer Compare Register (TCPR)
Logic for clock selection and interrupt/DMA trigger genera tion.
The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer
modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5.
Figure 9-1. Triple Timer Module Block Diagram
Timer Prescaler
Count Register
GDB 24
24
TPLR 24
Timer 0
Timer 2
Timer 1
24-bit Counter
CLK/2 TIO0 TIO1 TIO2
TPCR
Timer Prescaler
Load Register
24
Operation
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-3
9.2 Operation
This section discusses the following timer basics:
Reset
Initialization
Exceptions
9.2.1 Time r Afte r Reset
A hardware RESET signal or software reset instruction clears the Timer Control and Status
Register for each timer, thus configuring each timer as a GPIO. A timer is active only if the timer
enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.
9.2.2 Timer Initialization
To initialize a timer, do the following:
1. Ensure that the timer is not active either by sending a res et or clearing the TCSR[T E]
bit.
2. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt
enable bits as needed for the application.
Figure 9-2. Timer Module Block Diagram
GDB
Control/Status
Register
TCSR
Counter
Timer interr upt/DMA request
Ti m e r C on t ro l
CLK/2TIO
Compare
Register
TCPR
=
24
24
Logic
Load
Register Count
Register
TLR
Prescaler CLK
TCR
24249
2
24242424
24
DSP56303 User’s Manual, Rev. 2
9-4 Freescale Semiconductor
Trip le T imer Module
3. Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register
(TLR), and Timer Compare Register (TCPR) as needed for the application.
4. Enable the timer by setting the TCSR[TE] bit.
9.2.3 Timer Exceptions
Each timer can generate two different exceptions:
Timer Overflow (highest priority) — Occurs when the timer counter reaches the overflow
value. This exception sets the TOF bit. TOF is cleared when a value of one is written to it
or when the timer overflow exception is serviced.
Timer Compare (lowest priority) — Occurs when the timer counter reaches the value
given in the Timer Compare Register (TCPR) for all modes except measurement modes.
In measurement modes 4–6, a compare exception occurs when the appropriate transition
occurs on the TIO signal. The Compare exception sets the TCF bit. TCF is cleared when a
value of one is written to it or when the timer compare interrupt is serviced.
To configure a timer exception, perform the following steps. The example at the right of each
step shows the register settings for configuring a Timer 0 compare interrupt. The order of the
steps is optional except that the timer should not be enabled (step 2e) until all other exception
configuration is complete:
1. Configure the interrupt service routine (ISR):
a. Load vector base address register VBA (b23–8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it i s defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt). p:TIM0C
2. Configure the interrupt trigger:
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (TOL[1–0])
b. Enable a specific peripheral interrupt.
TCSR0 (TCIE)
c. Unmask interrupts at the global level.
SR (I[1–0])
d. Configure a peripheral interrupt-generating function.
TCSR0 (TC[7–4])
e. Enable peripheral and associated signals. TCSR0 (TE)
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-5
9.3 Operating Modes
Each timer has operating modes that meet a variety of system requirements, as follows:
Timer
— GPIO, mode 0: Internal timer interrupt generated by the internal clock
— Pulse, mode 1: External timer pulse generated by the internal clock
— Toggle, mode 2: Output timing signal toggled by the internal clock
— Event counter, mode 3: Internal timer interrupt generated by an external clock
Measurement
— Input width, mode 4: Input pulse width measurement
— Input period, mode 5: Input signal period measurement
— Capture, mode 6: Capture external signal
PWM, mode 7: Pulse width modulation
Watchdog
— Pulse, mode 9: Output pulse, internal clock
— Toggle, mode 10: Output toggle, internal clock
Note: To ensure proper operation, the TCSR TC[3–0] bits should be changed only when the
timer is disabled (that is, when TCSR[TE] is cleared).
9.3.1 Triple Timer Modes
For all triple timer modes, the following points are true:
The TCSR[TE] bit is set to clear the counter and enable the timer. Clearing TCSR[TE]
disables the timer.
The value to which the timer is to count is loaded into the TCPR. (This is true for all
modes except the measurement modes (modes 4 through 6).
The counter is loaded with the TLR value on the first clock.
If the counter overflows, TCSR[TOF] is set, and if TCSR[TOIE] is set, an overflow
interrupt is generated.
You can read the counter contents at any time from the Timer Count Register (TCR).
9.3.1.1 Timer GPIO (Mode 0)
In Mode 0, the timer generates an internal interrupt when a counter value is reached, if the timer
compare interrupt is enabled (see Figure 9-3 and Figure 9-4). When the counter equals the
TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is
Bit Settings Mode Charac teristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0000 0 GPIO Timer GPIOInternal
DSP56303 User’s Manual, Rev. 2
9-6 Freescale Semiconductor
Trip le T imer Module
set. If the TCSR[TRM] bit is set, the counter is reloaded with the TLR value at the next tim er
clock and the count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on
each timer clock signal. This process repeats until the timer is disabled.
Figure 9-3. Timer Mode (TRM = 1)
Figure 9-4. Timer Mode (TRM = 0)
Mode 0 (internal clock, no timer output): TRM = 1
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first eve n t last event
M
0 N N + 1 M N N + 1
N
Mode 0 (internal clock, no timer output): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first eve n t last event
M
0N
N + 1
M01
N
M + 1
TOF (Overflow Interrupt if TCIE = 1)
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-7
9.3.1.2 Timer Pulse (Mode 1)
In Mode 1, the timer generates an external pulse on its TIO signal when the timer count reaches a
pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit. When the counter
matches the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The polarity of the TIO signal is inverted for one timer clock period. If
TCSR[TRM] is set, the counter is loaded with the TLR value on the next timer clock and the
count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on each timer
clock. This process repeats until TCSR[TE] is cleared (disabling the timer).
The TLR value in the TCPR sets the delay between starting the tim er and generating the output
pulse. To generate successive output pulses with a delay of X clock cycles between signals, set
the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until the timer is
disabled.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0001 1 Timer Pulse Timer OutputInternal
Figure 9-5. Pulse Mode (TRM = 1)
Mode 1 (internal clock): TRM = 1
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
fi rs t eve n t
M
0 N N + 1 M N N + 1
N
pulse width =
timer clock
period
TIO pin (INV = 0)
TIO pin (INV = 1)
DSP56303 User’s Manual, Rev. 2
9-8 Freescale Semiconductor
Trip le T imer Module
9.3.1.3 Timer Toggle (Mode 2)
In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is
enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter valu e
matches the value in the TCPR, the polarity of the TIO output signal is inverted. TCSR[TCF] is
set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If the TCS R[TRM] bit is
set, the counter is loaded with the value of the TLR when the next timer clock is received, and the
count resumes. If the TRM bit is cleared, the counter continues to increment on each timer clock.
This process repeats until the timer is cleared (disabling the timer). The TCPR[TLR] value sets
the delay between starting the timer and toggling the TIO signal. To generate output signals with
a delay of X clock cycles between toggles, set the TLR value to X/2, and set the TCSR[TRM] bit.
This process repeats until the timer is disabled (that is, TCSR[TE] is cleared).
Figure 9-6. Pulse Mode (TRM = 0)
Bit Set ti ngs Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 0 1 0 2 Toggle Timer Output Internal
Mode 1 (internal clock): TRM = 0
N = write preload
M = write compare
TE
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
fi rs t eve n t
M
1
N
pulse width =
timer clock
period
TIO pin (INV = 0)
TIO pin (INV = 1)
TOF (Over flow Interrupt if TCIE = 1)
Counter (TCR) 0N
N + 1
M0M + 1
Clock
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-9
Figure 9-7. Toggle Mode, TRM = 1
Figure 9-8. Toggle Mode, TRM = 0
Mode 2 (internal clock): TRM = 1
N = write prel oad
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first event
M
0 N N + 1 M N N + 1
N
pulse width =
M - N clock
periods
TIO pin (INV = 0)
TIO pin (INV = 1)
Mode 2 (internal clock): TRM = 0
N = wri te prel oad
M = write compar e
TE
TLR
TCPR
TCF (Compare Interrupt i f TCIE = 1)
first event
M
N
First toggle = M - N clock periods
Second and later toggles = 2 24 clock periods
TIO pin (INV = 0)
TIO pin (INV = 1)
1
Counter (TCR) 0N
N + 1
M0M + 1
TOF (Overf low I nter rupt if TCIE = 1)
(CLK/2 or prescale CLK)
Clock
DSP56303 User’s Manual, Rev. 2
9-10 Freescale Semiconductor
Trip le T imer Module
9.3.1.4 Timer Event Counter (Mode 3)
In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits are set)
when the timer counts a preset number of events. The timer clock signal can be taken from either
the TIO input signal or the prescaler clock output. If an external clock is used, it must be
internally synchronized to the internal clock, and its frequency must be less than the DSP56303
internal operating frequency divided by 4. The value of the TCSR[INV] bit determines whether
low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the
INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared,
low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, TCSR[TCF] is set and a compare
interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is
loaded with the value of the TLR when the next timer clock is received, and the count is resumed.
If the TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 0 1 1 3 Event Counter Timer Input External
Figure 9-9. Event Counter Mode, TRM = 1
Mode 3 (inte rn a l cl ock): TRM = 1
N = write prelo ad
M = write compare
TE
Clock
(TIO pin or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TC IE = 1)
Counter (TCR)
first event
M
0 N N + 1 M N N + 1
N
interrupt s every
M - N clo ck
periods
if clock source
is f rom TIO pin,
TIO < CPUCLK + 4
NOTE: If INV = 1, counter is clocked on 1 -to-0 cloc k transit ions, i nstead of 0-t o-1 transitions.
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-11
9.3.2 Signal Measurement Mode s
The following signal measurement and pulse width modulation modes are provided:
Measurement input width (Mode 4)
Measurement input period (Mode 5)
Measurement capture (Mode 6)
Pulse width modulation (PWM) mode (Mode 7)
The external signal synchronizes with the internal clock that increments the counter. This
synchronization process can cause the number of clocks measured for the selected signal value to
vary from the actual signal value by plus or minus one counter clock cycle.
Figure 9-10. Event Counter Mode, TRM = 0
Mode 3 (internal clock): TRM = 0
N = write prel oad
M = write compare
TE
(TIO pin or prescale CLK)
TLR
TCPR
TCF (Com pare Interrupt if TCIE = 1)
first event
M
N
if cl ock source is from TIO pin,
TIO < CPUCLK + 4
Clock
1
Counter (TCR) 0NN + 1 M0M + 1
TOF (Overflow Interrupt if TCI E = 1)
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, i nstead of 0-to-1 transitions.
DSP56303 User’s Manual, Rev. 2
9-12 Freescale Semiconductor
Trip le T imer Module
9.3.2.1 Measurement Input Width (Mode 4)
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an input
signal. After the first appropriate transition (as determined by the TCSR[INV] bit) occurs on the
TIO input signal, the counter is loaded with the TLR value. If TCSR[INV] is set, the timer starts
on the first high-to-low (1 to 0) signal transition on the TIO signal. If th e INV bit is cleared, the
timer starts on the first low-to-high (that is, 0 to 1) transition on the TIO signal. When the first
transition opposite in polarity to the INV bit setting occurs on the TIO signal, the counter stops.
TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is set. The value of
the counter (which measures the width of the TIO pulse) is loaded into the TCR, which can be
read to determine the external signal pulse width. If the TC SR[TRM] bit is set, the counter is
loaded with the TLR value on the first timer clock received following the next valid transition on
the TIO input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to
increment on each timer clock. This process repeats until the timer is disabled.
Bit Set ti ngs Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 0 0 4 Input width Measurement Input Internal
Figu re 9-11 . Pulse Width Measurement Mode, TRM = 1
Mod e 4 (internal cloc k): TRM = 1
N = write prel oad
M = write co mpare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCR
Counter
first event
M
0NN + 1 M
N + 1
N
In te rrup t S e rvice
reads TCR; width
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
TCF (Compare Interrupt if TCIE = 1)
TI O pin width being measured
stops the counter and loads TCR with the count.
= M - N clock
periods
Next 0-to-1 edge
on TIO loads
counter and
process repeats
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-13
9.3.2.2 Measurement Input Period (Mode 5)
In Mode 5, the timer counts the period between the reception of signal edges of the same polarity
across the TIO signal. The value of the INV bit determines whether the period is measured
between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low
(1 to 0) transitions of TIO. If INV is set, high-to-low signal transitions are selected. If INV is
cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on
the TIO input signal, the counter is loaded with the TLR value. On the next signal transition of the
same polarity that occurs on TIO, TCSR[TCF] is set, and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The contents of the counter load into the TCR. The TCR then contains the
value of the time that elapsed between the two signal transitions on the TIO signal. After the
second signal transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter
and enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows.
Figu re 9-12 . Pulse Width Measurement Mode, TRM = 0
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 0 1 5 Inp ut per iod Measurement Input Internal
M
ode 4 (internal clock) : TRM = 1
N = write preload
M = wri te compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCR
Counter
fi rs t eve n t
M
0NN + 1 M
N + 1
N
Int e rrup t S e rvice
reads TCR for
NOTE: If IN V = 1, a 1-to-0 edge on TIO loads the coun ter, and a 0-to-1 edge on TIO
TCF (Compare Interrupt if TCIE = 1)
TI O pin width being measured
stops the count er and loads TCR with the count.
accumu lat ed width
of M - N clock period
s.
Next 0-t o-1 edge
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1
).
DSP56303 User’s Manual, Rev. 2
9-14 Freescale Semiconductor
Trip le T imer Module
Figure 9-13. Period Measurement Mode, TRM = 1
Figure 9-14. Period Measurement Mode, TRM = 0
Mode 5 (inte rn a l cl ock): TRM = 1
N = write prel oad
M = write compar e
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCR
Counter
first event
M
0NN + 1MN
N + 1
N
NOTE: If INV = 1, a 1-to- 0 edge on TIO lo ads the counter, and a 0-to-1 edge on TIO
TCF (Compare Interrupt if TCIE = 1)
TIO pin period being measured
loads TCR with count and the counter with N.
Int e rrup t S e rvice
reads TCR; per iod
= M - N clock
periods
Counter cont inues
counting, does
not stop
M
ode 5 (int ernal cloc k): TRM = 0
N = write prel oad
M = write compar e
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCR
Counter
first event
M
0NN + 1MM + 1
N + 1
N
NOTE: If INV = 1, a 1-to- 0 edge on TIO lo ads the counter, and a 0-to-1 edge on TIO
TCF (Compare Interrupt if TCIE = 1)
TIO pin period being measured
loads TCR with count and the counter with N.
Interrupt Service
reads TCR; peri od
= M - N clock
periods
Counter continues
counting, does
not st op. Overflow
ma y o cc u r (T O F = 1
).
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-15
9.3.2.3 Measurement Capture (Mode 6)
In Mode 6, the timer counts the number of clocks that elapse between when the timer starts and
when an external signal is received. At the first appropriate transition of the external clock
detected on the TIO signal, TCSR[TCF] is set and, if the TCSR[TCIE] bit is set, a compare
interrupt is generated. The counter halts. The contents of the counter are loaded into the TCR.
The value of the TCR represents the delay between the setting of the TCSR[TE] bit and the
detection of the first clock edge signal on the TIO signal. The value of the INV bit determines
whether a high-to-low (1 to 0) or low-to-high (0 to 1) tran sition of the external clo ck signals the
end of the timing period. If the INV bit is set, a high-to-low transition signals t he end of the
timing period. If INV is cleared, a low-to-high transition signals the end of the timing period.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 1 0 6 Capture Measurement Input Internal
Figure 9-15. Capture Measurement Mode, TRM = 0
Mode 6 (internal clock): TRM = 1
N = write prel oad
M = write compare
TE
Clock
(CLK/2 or prescale C LK)
TLR
TCR
Counter
first event
M
0 N N + 1 M N N + 1
N
Inte r ru p t S er v ic e
reads TCR; delay
NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and st ops the counter.
TCF (Compare Interrupt if TCIE = 1)
TIO pin delay being measured
= M - N clock
periods
Counter stops
counting; over flow
may occ ur before
capture (TOF = 1)
DSP56303 User’s Manual, Rev. 2
9-16 Freescale Semiconductor
Trip le T imer Module
9.3.3 Puls e Width Modulation
In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the
value in the TCPR, the TIO output signal is toggled and T CSR[TCF] is set. The contents of the
counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare interrupt is generated.
The counter continues to increment on each timer clock.
If counter overflow occurs, the TIO output signal is toggled, TCSR[TOF] is set, and an overflow
interrupt is generated if the TCSR[TOIE] bit is set. If the TCSR[TRM] bit is set, the counter is
loaded with the TLR value on the next timer clock and the count resumes. If the TCSR[TRM] bit
is cleared, the counter continues to increment on each timer clock. This process repeats until the
timer is disabled.
When the TCSR[TE] bit is set and the counter starts, the TIO signal assumes the value of INV. On
each subsequent toggle of the TIO signal, the polarity of the TIO signal is reversed. For example, if
the INV bit is set, the TIO signal generates the following signal: 1010. If the INV bit is cleared, the
TIO signal generates the following signal: 0101.
The value of the TLR determines the output period ($FFFFFF − TLR + 1). The timer counter
increments the initial TLR value and toggles the TIO signal when the counter value exceeds
$FFFFFF. The duty cycle of the TIO signal is determined by the value in the TCPR. When the
value in the TLR increments to a value equal to the value in the TCPR, the TIO signal is toggled.
The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For a 50
percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2.
Note: The value in TCPR must be greater than the value in TLR.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 1 1 7 Pulse width modulation PWM Output Internal
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-17
Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1
Mode 7 (internal clock): TRM = 1
N = write prelo ad
M = write compare
TE
Clock
(CLK/2 or pr escale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first event
M
0
N
M
N
N + 1
N
Perio d = $FFFFFF - TLR + 1
Duty cycl e = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
0
M + 1
TC F (O ver flow In ter rup t if TD IE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1) Pulse widt h
Period
DSP56303 User’s Manual, Rev. 2
9-18 Freescale Semiconductor
Trip le T imer Module
Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0
9.3.4 Watchdog Modes
The following watchdog timer modes are provided:
Watchdog Pulse
Watchdog Toggle
Mode 7 (internal clock): TRM = 0
N = write prelo ad
M = write compare
TE
Clock
(CLK/2 or pr escale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first event
M
0
N
M
1
2
N
Perio d = $FFFFFF - TLR + 1
Duty cycl e = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
0
M + 1
TC F (O ver flow In ter rup t if TD IE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1) Pulse widt h
Period
NOTE: On overflow, TCR is loa ded with the value of T LR.
Operati ng M odes
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-19
9.3.4.1 Watchdog Pulse (Mode 9)
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to the
period of one timer clock. After the counter reaches the value in the TCPR, if the TCSR[TRM]
bit is set, the counter is loaded with the TLR value on the next timer clock and the count resumes.
Therefore TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the
counter continues to increment on each subsequent timer clock. This process repeats until the
timer is disabled (that is, TCSR[TE] is cleared). If the counter overflows, a pulse is output on the
TIO signal with a pulse width equal to the timer clock period. If the INV bit is set, the pulse
polarity is high (logical 1). If INV is cleared, the pulse polarity is low (logical 0). The counter
reloads when the TLR is written with a new value while the TCSR[TE] bit is set. In Mode 9,
internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after
the hardware RESET sig nal is asserted. This convention ensures that a valid RESET signal is
generated when the TIO signal resets the DSP56303.
Figure 9-18. Wat c hdog Pulse Mode
Bit Settings Mode Characteri sti cs
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
1 0 0 1 9 Pulse Watchdog Output Internal
Mode 9 (internal clock): TRM = 0
N = write prelo ad
M = write compare
TE
Clock
(CLK/2 or pr escale CLK)
TLR
TCF (Compare Interrupt i f TCIE = 1)
Counte r (TCR)
first event
M
0
N
M
1
N
TRM = 1 is not useful for watchdog function
0
M + 1
TOF (Overflow Interrupt if TOIE = 1 )
TIO pin (INV = 0)
TIO pin (INV = 1)
(Soft w are does not reset watc hdog ti m er; watchdog times ou t)
N + 1
pulse width
= time r
clock pe riod
float
float
low
high
TIO can connect to the RESET pin, in ternal hardw are preserves the TIO v alue and
direction for an additional 2.5 clocks to ensure a reset of valid length.
TCPR
DSP56303 User’s Manual, Rev. 2
9-20 Freescale Semiconductor
Trip le T imer Module
9.3.4.2 Watchdog Toggle (Mode 10)
In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set to the
value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is set, and a
compare interrupt is generated if the TCSR[TCIE] bit is also set. If the TCSR[TRM] bit is set, the
counter loads with the TLR value on the next timer clock and the count resumes. Therefore, TRM
= 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the counter continues
to increment on each subsequent timer clock. When a counter overflow occurs, the polarity of the
TIO output signal is inverted. The counter is reloaded whenever the TLR is written with a new
value while the TCSR[TE] bit is set. This process repeats until the timer is disabled. In Mode 10,
internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after
the hardware RESET sig nal is asserted. This convention ensures that a valid reset signal is
generated when the TIO signal resets the DSP56303.
9.3.4.3 Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
1010 10 Toggle Watchdog Output Internal
Figure 9-19. Watchdog Toggle Mode
Mode 10 (internal clock): TRM = 0
N = write preload
M = write co mpare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCF (Compare Interrupt if TCIE = 1)
Counter (T CR)
first event
M
0
N
M
1
N
TRM = 1 is not usefu l fo r watc hdog function
0
M + 1
TOF (Overflo w Interrupt if T OIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
N + 1
float
float
low
high
TIO can connect to the RESET pin, internal hardwar e preserves th e TIO val ue and
direction for an additional 2.5 clocks to ensure a reset of valid length.
TCPR
Triple Timer Module Progra mmi ng Mode l
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-21
9.3.5 Special Cases
The following special cases apply during wait and stop state.
Timer behavior during wait. Timer clocks are active during the execution of the wait
instruction and timer activity is undisturbed. If a timer interrupt is generated, the
DSP56303 leaves the wait state and services the interrupt.
Timer behavior during stop. During execution of the stop instruction, the timer clocks are
disabled, timer activity stops, and the TIO signals are disconnected. Any external changes
that happen to the TIO signals are ignored when the DSP56303 is in stop state. To ensure
correct operation, disable the timers before the DSP56303 is placed in stop state.
9.3.6 DMA Trigger
Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a
timer event. The timer issues a DMA trigger on every event in all modes of operation. To ensure
that all DMA triggers are serviced, provide for the preceding DMA trigger to be serviced before
the DMA channel receives the next trigger.
9.4 Triple Timer Module P ro gramming Model
The timer programming model in Figure 9-20 shows the structure of the timer registers.
9.4.1 Prescaler Counter
The prescaler counter is a 21-bit counter that decrements on the rising edge of the prescaler input
clock. The counter is enabled when at least one of the three timers is enabled (that is, one or more
of the timer enable bits are set) and is using the prescaler output as its source (that is, one or more
of the PCE bits are set).
DSP56303 User’s Manual, Rev. 2
9-22 Freescale Semiconductor
Trip le T imer Module
Figure 9-20. Timer Module Programming Model
9.4.2 Timer Prescaler Load Register (TPLR)
The TPLR is a read/write register that controls the prescaler divide factor (that is, the number that
the prescaler counter loads and begins counting from) and the source for the prescaler input
clock.
23 22 21 20 19 18 17 16 15 14 13 12
PS1 PS0 PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12
11109876543210
PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
— Reser ved bit. Read as 0. Write to 0 for future compati bility
Figure 9-21. Timer Prescaler Load Register (TPLR)
DO DI DIR
15 14 13 12 11 10 9 8
TC1 TC0
INV
TCIE TE
76543210
Timer Control/St atus
Register (TCSR)
Re s er v ed bi t. Rea d as 0 . Write w ith 0 for futur e co mp at ib ility
23 0 Timer Load
Register (TLR)
23 22 21 20 19 18 17 16
23 0 Time r C ompar e
Register (TCPR)
PCE TRM
TCF TOF
TOIETC2
23 0 Timer Count
Register (TCR)
TC3
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TCSR2 = $FFFF87
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
23 0 Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
23 0 Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
Triple Timer Module Progra mmi ng Mode l
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-23
9.4.3 Timer Prescaler Count Register (TPCR)
The TPCR is a read-only register that reflects the current value in the prescaler counter.
Table 9-1. Timer Prescaler Load Register (TPLR) Bit Definitions
Bit Number Bit Name Reset Value Description
23 0 Reserved . Write t o zero for f uture compatibility.
22–21 PS[1–0] 0 Prescaler Source
Control the source of the prescaler clock . The prescaler’s us e of a TIO signal
is not affected by the TCSR set ti ngs of the t imer of the corr esponding TIO
signal. If the prescaler source clock is ext ernal, the prescaler counter is
incremented by signal transitions on the TIO signal. The ext ernal clock is
internally synchronized to t he internal clock. The external clock frequency
must be lower than the DSP56303 internal operating fr equency divi ded by 4
(that is, CLK/4).
Note: To ensure pr oper operat ion, change the PS[1–0] bits only when the
prescaler counter is disabled. Disable the prescaler counter by
clearing TCSR[TE] of each of three timers.
PS1 PS0 Prescaler Clock Source
0 0 Internal CLK/2
01 TIO0
10 TIO1
11 TIO2
20–0 PL[20–0] 0 Pre scaler Preload Value
Contains the presc aler pr eload value, which is loa ded into t he prescaler
counter when the counter value reaches 0 or the counter switches state from
disabl ed to enabled. If PL[20–0] = N, the n the pr escaler counts N+1 source
clock cycles before generati ng a prescaler cloc k pulse. Theref ore, the
prescaler di vide factor = (preload val ue) + 1.
23 22 21 20 19 18 17 16 15 14 13 12
PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12
11109876543210
PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Reserved bit; read as 0; w rite to 0 for future compatibility
Figure 9-22. Timer Prescaler Count Register (TPCR)
Table 9-2. Timer Prescaler Count Register (TPCR) Bit Definitions
Bit Number Bit Name Reset Value Description
23–21 0 R e se r ve d . Write to ze ro fo r fu tu r e c ompat ib ili ty.
20–0 PC[20–0] 0 Prescaler Count er Value
Contain the current value of t he prescaler count er.
DSP56303 User’s Manual, Rev. 2
9-24 Freescale Semiconductor
Trip le T imer Module
9.4.4 Timer Control/Statu s Register (TCSR)
The TCSR is a read/write register controlling the timer and reflecting its status.
23 22 21 20 19 18 17 16 15 14 13 12
TCF TOF PCE DO DI
11109876543210
DIR TRM INV TC3 TC2 TC1 TC0 TCIE TOIE TE
Reserved. Read as 0. Write to 0 for future compatibilit y
Figure 9-23. Timer Control/Status Register (TCSR)
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions
Bit Number Bit Name Reset Value Description
23–22 0 R eserv ed . Write to ze ro fo r futu re co m p at ib il ity .
21 TCF 0 Time r Comp are Flag
Indicate that the event count is complete. In timer, PWM, and watchdog
modes , th e TCF bit is set aft er (M – N + 1) event s are counted. (M i s the
value in the comp are r egister and N is the TLR val ue.) In measurement
modes , the TCF bit is set when the m easurement compl etes. Writi ng a one to
the TCF bi t cle ars it. A ze ro writ ten to t he TCF b it has n o effect . The bi t is al so
cleared when the tim er compare interru pt i s serviced. The TCF bit is cl eared
by a hardware RESET signal, a soft ware RESET inst ruction, the STOP
instruction, or by cl earing the TCSR[TE] bit to di sable the timer .
Note: The TOF and TCF bits are cleared by a 1 written to the specific bit.
To ensure that only the tar get bit is cl eared, do not use the BSET
command. The proper way to cl ear these bits is to write 1, using a
MOVEP instruction, to the flag to be cl eared and 0 to the other flag.
20 TOF 0 Timer Overflow Flag
Indi cates th at a counter overfl ow has occurr ed. Thi s bit is cl eared by wr iti ng a
one to the TOF bit. Writing a zer o to TO F has no e ffect . T he bit is also cl ear ed
when the ti m er overflo w interrupt is ser viced. The TOF bit is cl eared by a
hardware RESET signal, a software RESET instruction, the STOP
instruction, or by cl earing the TCSR[TE] bit to di sable the timer.
19–16 0 R eserv ed . Write to ze ro fo r futu re co m p at ib il ity .
15 PCE 0 Prescaler Clock Enable
Selects the prescaler clock as the timer sour ce clock. When PCE is cleared,
the ti m er uses either an internal (CLK/2) signal or an external ( TIO) signal as
its source clock. When PCE is set, the prescaler output i s the timer sour ce
clock for the counter, regar dless of the tim er operat ing mo de. To ensure
proper operat ion, t he P CE bit i s changed onl y when the timer is dis abled. The
PS[1–0] bit s of t he TPLR determine which sour ce clock is used fo r the
presca le r. A time r can be clock ed by a presca le r cloc k that is der ived f rom t he
TIO of another timer.
14 0 Re s er v ed . Wr it e to zero fo r fu tu re co mp at ib ility.
Triple Timer Module Progra mmi ng Mode l
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-25
13 DO 0 D a ta O u tp u t
The source of the TI O value when it is a data output signal . The TIO signal i s
a data out put when th e GPIO mode is enabl ed and DIR is set. A val ue written
to th e DO bi t is wr itt e n to th e TIO si g na l . If th e INV b it is se t, the va lu e of the
DO b it is inverted when written to the TIO signal. When the INV bit is cleared,
the value of the DO bit is writ ten direct ly to the TIO signal. W hen G PIO mode
is dis abled, writi ng to the DO bit has no effect.
12 DI 0 Data Input
Reflects the value of the TIO signa l. If the INV bit is set, the value of the TIO
signal is invert ed before it is wri tt en to the DI bit. If the INV bit is cl eared, t he
value of the TIO signal is written directly to the DI bit.
11 DIR 0 Direction
Determi nes th e beh avior of the TI O signal when it func tions as a GPIO s ignal .
When DIR is set, the TIO sig nal is an output; when DIR is cle ared, the TIO
signal is an input. The TIO signal functions as a GPIO si gnal only when the
TC[3–0] bit s are cleared. If any of t he T C[3–0] bi ts are set , then the GPIO
function is disabled, and the DIR bit has no effect.
10 0 Re s er v ed . Wr it e to zero fo r fu tu re co mp at ib ility.
9TRM0Timer Reloa d Mode
Controls the count er preload operation. In timer (0–3) and watc hdog ( 9–10)
modes , t he counter is prel oaded with the TLR value aft er the TCSR[TE] bit is
set and the first internal or external clock signal i s received. If t he TRM bit is
set, the counter is reloaded each time after it reaches the value contained by
the TCR. In PWM mode (7), the counter is reloaded each time counter
overf low occu rs. I n meas uremen t (4–5) m odes, i f th e TRM and the TCSR[T E]
bits are set, the c ounter is preloaded with the TLR value on each appropriate
edge of the input si gnal. I f the TRM bit is cleared, th e counter operat es as a
free running counter and is incremented on each incoming event.
8INV0Inverter
Affects the polari ty definition of the incomi ng signal on the TIO signal when
TIO is pro g rammed as input. It also affects the pol ari ty of th e output pul se
generated on the TIO signal when TI O is programmed as output. See Table
9-4, Inver ter (INV) Bit Oper ati on, on page 9-27. The INV bit does not affect
the polarity of the prescaler source when the TIO i s input to the prescaler.
Note: The INV bi t affects both the timer and G PIO modes of o perati on. To
ensure correct operat ion, change this bit only when one or both of
the f ollowing conditions is true: t he timer is disabl ed (the TCSR[TE]
bit is cleared). The ti m er is in GPIO mode.
Tabl e 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
9-26 Freescale Semiconductor
Trip le T imer Module
7–4 TC[3–0] 0 Timer Control
Control the source of the timer clock, the behavior of the TIO sig nal, and the
Timer mode of operat ion. Section 9.3, O perati ng M odes, on page 9-5
describes the t imer operating modes i n detail . To ensure pr oper operati on,
the TC[3–0] bits should be changed only when the timer is disabled (that is,
when the TCSR[TE] bit is cleared).
Note: I f the clock i s external, the counter is inc remented by the transitions
on the TIO signal. The external clo ck is intern ally sy nchronized to
the int ernal clock, and it s frequency should be lower than the
internal operating frequency divi ded by 4 (that is, CLK/4).
Bit Set ti ngs Mode Character isti cs
TC3 TC2 TC1 TC0 Mode
Number Mode
Function TIO Clock
0 0 0 0 0 Timer and
GPIO GPIO
1Internal
0 0 0 1 1 Timer pul se Outpu
tInternal
0 0 1 0 2 Tim er t oggle Outpu
tInternal
0 0 1 1 3 Event counter Input Externa
l
0 1 0 0 4 Input width
measurement Input Internal
0 1 0 1 5 Input period
measurement Input Internal
0 1 1 0 6 Capture
event Input Internal
0 1 1 1 7 Pulse width
modulation Outpu
tInternal
1 0 0 0 8 Reserved — —
1 0 0 1 9 Watchdog
pulse Outpu
tInternal
1 0 1 0 10 Watchdog
Toggle Outpu
tInternal
1011 11 Reserved——
1100 12 Reserved——
1101 13 Reserved——
1110 14 Reserved——
1111 15 Reserved——
Note: The GPIO function is enabled only if all of the TC[3–0] bits are 0.
30 Re s er v ed . Wr it e to zero fo r fu tu re co mp at ib ility.
Tabl e 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
Triple Timer Module Progra mmi ng Mode l
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-27
2TCIE0Timer Compare Inter rupt Enable
Enables/ disables the timer compare interrupts. When set, TCIE enables the
compa re inte rrupts. I n the timer , pulse width modul ation (PWM), or watchdo g
modes , a compare interru pt is generated after the counter value matches the
value of the TCPR. The counter st arts counting up from the numb er l oaded
from t he TLR and if the TCPR val ue is M, an inte rrupt occurs af ter ( M – N + 1)
events, where N is the value of TLR. When cl eared, t he TCSR[TCIE] bit
disables the compare inter rupts.
1TOIE0Timer O verflow Interrupt Enabl e
Enables timer overflow interrupts. When set, TOIE enables overf low interrupt
generat ion. The timer coun ter can hol d a maximum value of $FFFFFF. When
the counter val ue is at the maximum val ue and a new event causes the
counter to be i ncremented to $000000, the timer generates an overf low
interrupt . When cleared, the TOIE bi t di sables overflo w int errupt generation.
0TE0Timer Enabl e
Enables/disabl es the timer. When set , TE enables the tim er and clears the
timer counter. The count er starts counting accordi ng to the mo de selected by
the t imer control (TC[3–0]) bi t values. When cl ear, TE bit disables the timer.
Note: When all three timers are disabled and the signals are not in G PIO
mode, all three TIO signals are tri-stated. To prevent undesir ed
spikes on the TIO signals when you switch from tri-state into active
state, these si gnals should be tied to the high or low signal state by
pull -up or pull-down re sistors.
Table 9-4. Inverter (INV) Bit Operation
Mode TIO Programmed as Input TIO Programm ed as Output
INV = 0 INV = 1 INV = 0 INV = 1
0 GPIO sign al on the TIO signal
read directly. GPIO signal on the TIO signa l
inverted. B it writte n to GPIO
put on TIO si gnal
directly.
Bit w ri tte n to GPIO
inve rted and put o n TIO
signal .
1 Counter is incremented on the
rising edge of the signal from
the TIO signal.
Counter is increm ented on
the falling edge of the signal
from t he TIO signal. ——
2 Counter is incremented on the
rising edge of the signal from
the TIO signal.
Counter is increm ented on
the falling edge of the signal
from t he TIO signal.
Initial output put on
TIO si gnal directly. In it ia l ou t pu t inv e rt ed
and put on TIO signal.
3 Counter is incremented on the
rising edge of the signal from
the TIO signal.
Counter is increm ented on
the falling edge of the signal
from t he TIO signal. ——
4 Width of the high input pulse is
measured. Wid th of th e low input pul se is
measured. ——
5 Period is measured between
the rising edges of the input
signal .
Period is measured between
the falling edges of the input
signal . ——
Tabl e 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
DSP56303 User’s Manual, Rev. 2
9-28 Freescale Semiconductor
Trip le T imer Module
9.4.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value
after the TCSR[TE] bit is set and a first event occurs.
In timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs.
In measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is reloaded
with the value in the TLR on each appropriate edge of the input signal.
In PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it overflows
and the new event occurs.
In watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs. In
this mode, the counter is also reloaded when ever the TLR is written with a new value
while TCSR[TE] is set.
In all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a free-running
counter.
9.4.6 Timer Compare Regist er (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter
value. These two values are compared every timer clock after TCSR[TE] is set. When the values
match, the timer compare flag bit is set and an interrupt is generated if interrupts are enabled (that
is, the timer compare interrupt enable bit in the TCSR is set). The TCPR is ig nored in
measurement modes.
6 Event is captur ed on the rising
edge of t he si gnal f rom the TI O
signal.
Event is captured on the
falling edge of the signal
from t he TIO signal. ——
7——
Pulse generat ed by
the t imer has positive
polarity.
Pulse generated by th e
timer has negative
polarity.
9——
Pulse generat ed by
the t imer has positive
polarity.
Pulse generated by th e
timer has negative
polarity.
10 ——
Pulse generat ed by
the t imer has positive
polarity.
Pulse generated by th e
timer has negative
polarity.
Table 9-4. Inverter (INV) Bit Operation (Continued)
Mode TIO Programmed as Input TIO Programm ed as Output
INV = 0 INV = 1 INV = 0 INV = 1
Triple Timer Module Progra mmi ng Mode l
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor 9-29
9.4.7 Timer Count Register (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the contents of the counter
can be read at any time from the TCR register. In measurement modes, the TCR is loaded with
the current value of the counter on the appropriate edge of the input signal, and its value can be
read to determine the width, period, or delay of the leading edge of the input signal . When the
timer is in measurement mode, the TIO signal is used for the input signal.
DSP56303 User’s Manual, Rev. 2
9-30 Freescale Semiconductor
Trip le T imer Module
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-1
Bootstrap Program A
This appendix lists the bootstrap program and equates for the DSP56303. Freescale posts updates
to the bootstrap program on the Worldwide Web at the web site listed on the back cover of this
manual.
A.1 Boots trap Code
; BOOTSTRAP CODE FOR DSP56303 - (C) Copyright 1995 Freescale Inc.
; Revised June, 29 1995.
;
; Bootstrap through the Host Interface, External EPROM or SCI.
;
; This is the Bootstrap program contained in the DSP56303 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM, from the Host Interface or from the SCI serial interface.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56303 will
; start fetching instructions beginning with the address $8000 assuming that
; an external memory of SRAM type is used. The accesses will be performed
; using 31 wait states with no address attributes selected (default area).
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=001, then it loads a program RAM segment from consecutive
; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
; The memory is selected by the Address Attribute AA1 and is accessed with
; 31 wait states.
; The EPROM bootstrap code expects to read 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are read least significant byte first followed by the
; mid and then by the most significant byte.
; The program words will be condensed into 24-bit words and stored in
; contiguous PRAM memory locations starting at the specified starting
: address.
; After reading the program words, program execution starts from the same
; address where loading started.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=010, then it loads the program RAM from the SCI interface.
; The number of program words to be loaded and the starting address must
DSP56303 User’s Manual, Rev. 2
A-2 Freescale Semiconductor
Bootstrap Program
; be specified. The SCI bootstrap code expects to receive 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are received least significant byte first followed by the
; mid and then by the most significant byte. After receiving the
; program words, program execution starts in the same address where
; loading started. The SCI is programmed to work in asynchronous mode
; with 8 data bits, 1 stop bit and no parity. The clock source is
; external and the clock frequency must be 16x the baud rate.
; After each byte is received, it is echoed back through the SCI
; transmitter.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=100, then it loads the program RAM from the Host
; Interface programmed to operate in the ISA mode.
; The HOST ISA bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=101, then it loads the program RAM from the Host
; Interface programmed to operate in the HC11 non multiplexed mode.
;
; The HOST HC11 bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=110, then it loads the program RAM from the Host
; Interface programmed to operate in the 8051 multiplexed bus mode,
; in double-strobe pin configuration.
; The HOST 8051 bootstrap code expects accesses that are byte wide.
; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
Bootstr ap Code
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-3
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
; The base address of the HI08 in multiplexed mode is 0x80 and is not modified
; by the bootstrap code. All the address lines are enabled and should be
; connected accordingly.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=111, then it loads the program RAM from the Host
; Interface programmed to operate in the MC68302 bus mode,
; in single-strobe pin configuration.
; The HOST MC68302 bootstrap code expects accesses that are byte wide.
; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
BOOT equ $D00000 ; this is the location in P memory
; on the external memory bus
; where the external byte-wide
; EPROM would be located
AARV equ $D00409; AAR1 selects the EPROM as CE~
; mapped as P from $D00000 to
; $DFFFFF, active low
M_SSR EQU $FFFF93 ; SCI Status Register
M_STXL EQU $FFFF95; SCI Transmit Data Register (low)
M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low)
M_SCCR EQU $FFFF9B; SCI Clock Control Register
M_SCR EQU $FFFF9C; SCI Control Register
M_PCRE EQU $FFFF9F ; Port E Control register
M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1
M_HPCR EQU $FFFFC4 ; Host Polarity Control Register
M_HSR EQU $FFFFC3; Host Status Register
M_HRX EQU $FFFFC6; Host Receive Register
HRDF EQU $0; Host Receive Data Full
HF0 EQU $3; Host Flag 0
HEN EQU $6; Host Enable
ORG PL: $ff0000,PL:$ff0000; bootstrap code starts at $ff0000
DSP56303 User’s Manual, Rev. 2
A-4 Freescale Semiconductor
Bootstrap Program
START
clr a #$0a,X0; clear a and load X0 with constant 0a0000
jclr #2,omr,EPRSCILD ; If MC:MB:MA=0xx, go load from EPROM/SCI
jclr #1,omr,OMR1IS0; IF MC:MB:MA=10x, go to look for ISA/HC11 options
jclr #0,omr,I8051HOSTLD; If MC:MB:MA=110, go load from 8051 Host
jmp MC68302HOSTLD; If MC:MB:MA=111, go load from MC68302 Host
OMR1IS0
jset #0,omr,HC11HOSTLD; If MC:MB:MA=101, go load from HC11 Host
; If MC:MB:MA=100, go load from ISA HOST
;=============================================================================
; This is the routine which loads a program through the HI08 host port
; The program is downloaded from the host MCU with the following scenario:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is any integer number)
; The program words will be stored in contiguous PRAM memory locations starting
; at the specified starting address.
; After reading the program words, program execution starts from the same address
; where loading started.
; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1.
; When the downloading is terminated, the program will start execution of the
; loaded program from the specified starting address.
; The HI08 boot ROM program enables the following busses to download programs
; through the HI08 port:
;
; 1 - ISA- Dual strobes non-multiplexed bus with negative strobe
; pulses dual positive request
; 2 - HC11- Single strobe non-multiplexed bus with positive strobe
; pulse single negative request.
; 4 - i8051 - Dual strobes multiplexed bus with negative strobe pulses
; dual negative request.
; 5 - MC68302 - Single strobe non-multiplexed bus with negative strobe
; pulse single negative request.
;=============================================================================
ISAHOSTLD
movep #%0101000000011000,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 1 Positive host request
; HCSP = 0 Negative chip select input
; HD/HS = 1 Dual strobes bus (RD and WR strobes)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
; meaning in non-multiplexed bus)
; HDSP = 0 Negative data strobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
; future compatibility
Bootstr ap Code
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-5
; HEN = 0 When the HPCR register is modified
; HEN should be cleared
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no meaning in
; non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no meaning in
; non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
bra<HI08CONT
HC11HOSTLD
movep#%0000001000011000,x:M_HPCR
; Configure the following conditions:
; HAP= 0 Negative host acknowledge
; HRP= 0 Negative host request
; HCSP= 0 Negative chip select input
; HD/HS= 0 Single strobe bus (R/W~ and DS strobes)
; HMUX= 0 Non multiplexed bus
; HASP= 0 (address strobe polarity has no meaning in
; non-multiplexed bus)
; HDSP= 1 Positive data strobes polarity
; HROD= 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for future
; compatibility
; HEN= 0 When the HPCR register is modified HEN should be
; cleared
; HAEN= 0 Host acknowledge is disabled
; HREN= 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN= 0 (address 9 enable bit has no meaning in
; non-multiplexed bus)
; HA8EN= 0 (address 8 enable bit has no meaning in
; non-multiplexed bus)
; HGEN= 0 Host GPIO pins are disabled
bra<HI08CONT
I8051HOSTLD
movep#%0001110000011110,x:M_HPCR
; Configure the following conditions:
; HAP= 0 Negative host acknowledge
; HRP= 0 Negative host request
; HCSP= 0 Negative chip select input
; HD/HS= 1 Dual strobes bus (RD and WR strobes)
; HMUX= 1 Multiplexed bus
; HASP= 1 Positive address strobe polarity
; HDSP= 0 Negative data strobes polarity
; HROD= 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for future
; compatibility
; HEN= 0 When the HPCR register is modified HEN
; should be cleared
DSP56303 User’s Manual, Rev. 2
A-6 Freescale Semiconductor
Bootstrap Program
; HAEN= 0 Host acknowledge is disabled
; HREN= 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN= 1 Enable address 9 input
; HA8EN= 1 Enable address 8 input
; HGEN= 0 Host GPIO pins are disabled
bra<HI08CONT
MC68302HOSTLD
movep#%0000000000111000,x:M_HPCR
; Configure the following conditions:
; HAP= 0 Negative host acknowledge
; HRP= 0 Negative host request
; HCSP= 0 Negative chip select input
; HD/HS= 0 Single strobe bus (R/W~ and DS strobes)
; HMUX= 0 Non multiplexed bus
; HASP= 0 (address strobe polarity has no meaning in
; non-multiplexed bus)
; HDSP= 0 Negative data strobes polarity
; HROD= 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for future
; compatibility
; HEN= 0 When the HPCR register is modified HEN should be
; cleared
; HAEN= 1 Host acknowledge is enabled
; HREN= 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN= 0 (address 9 enable bit has no meaning in
; non-multiplexed bus)
; HA8EN= 0 (address 8 enable bit has no meaning in
; non-multiplexed bus)
; HGEN= 0 Host GPIO pins are disabled
HI08CONT
bset#HEN,x:M_HPCR ; Enable the HI08 to operate as host
; interface (set HEN=1)
jclr#HRDF,x:M_HSR,* ; wait for the program length to be
; written
movepx:M_HRX,a0
jclr#HRDF,x:M_HSR,* ; wait for the program starting address
; to be written
movepx:M_HRX,r0
mover0,r1
do a0,HI08LOOP ; set a loop with the downloaded length
; counts
HI08LL
jset#HRDF,x:M_HSR,HI08NW ; If new word was loaded then jump
;to read that word
jclr#HF0,x:M_HSR,HI08LL ; If HF0=0 then continue with the
; downloading
enddo ; Must terminate the do loop
bra<HI08LOOP
HI08NW
Bootstr ap Code
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-7
movepx:M_HRX,p:(r0)+ ; Move the new word into its destination
; location in the program RAM
HI08LOOP
bra<FINISH
;========================================================================
EPRSCILD
jclr #1,omr,EPROMLD ; If MC:MB:MA=001, go load from EPROM
;========================================================================
; This is the routine that loads from the SCI.
; MC:MB:MA=010 - external SCI clock
SCILD
movep #$0302,X:M_SCR ; Configure SCI Control Reg
movep #$C000,X:M_SCCR ; Configure SCI Clock Control Reg
movep #7,X:M_PCRE ; Configure SCLK, TXD and RXD
do #6,_LOOP6 ; get 3 bytes for number of
; program words and 3 bytes
; for the starting address
jclr #2,X:M_SSR,* ; Wait for RDRF to go high
movep X:M_SRXL,A2 ; Put 8 bits in A2
jclr #1,X:M_SSR,* ; Wait for TDRE to go high
movep A2,X:M_STXL ; echo the received byte
asr #8,a,a
_LOOP6
move a1,r0 ; starting address for load
move a1,r1 ; save starting address
do a0,_LOOP7 ; Receive program words
do #3,_LOOP8
jclr #2,X:M_SSR,* ; Wait for RDRF to go high
movep X:M_SRXL,A2 ; Put 8 bits in A2
jclr #1,X:M_SSR,* ; Wait for TDRE to go high
movep a2,X:M_STXL ; echo the received byte
asr #8,a,a
_LOOP8
movem a1,p:(r0)+ ; Store 24-bit result in P mem.
_LOOP7
bra <FINISH ; Boot from SCI done
;========================================================================
; This is the routine that loads from external EPROM.
; MC:MB:MA=001
EPROMLD
move #BOOT,r2 ; r2 = address of external EPROM
movep #AARV,X:M_AAR1 ; aar1 configured for SRAM types of access
do #6,_LOOP9 ; read number of words and starting address
DSP56303 User’s Manual, Rev. 2
A-8 Freescale Semiconductor
Bootstrap Program
movem p:(r2)+,a2 ; Get the 8 LSB from ext. P mem.
asr #8,a,a ; Shift 8 bit data into A1
_LOOP9 ;
move a1,r0 ; starting address for load
move a1,r1 ; save it in r1
; a0 holds the number of words
do a0,_LOOP10 ; read program words
do #3,_LOOP11 ; Each instruction has 3 bytes
movem p:(r2)+,a2 ; Get the 8 LSB from ext. P mem.
asr #8,a,a ; Shift 8 bit data into A1
_LOOP11 ; Go get another byte.
movem a1,p:(r0)+ ; Store 24-bit result in P mem.
_LOOP10 ; and go get another 24-bit word.
; Boot from EPROM done
;========================================================================
FINISH
; This is the exit handler that returns execution to normal
; expanded mode and jumps to the RESET vector.
andi #$0,ccr ; Clear CCR as if RESET to 0.
jmp (r1) ; Then go to starting Prog addr.
; End of bootstrap code. Number of program words: 91
;*****************************************************************************
;
; EQUATES for 56303 I/O registers and ports
;
; Last update: June 11 1995
;
;*****************************************************************************
page132,55,0,0,0
optmex
ioequ ident 1,0
A.2 Equates for I/O Port Programming
;------------------------------------------------------------------------
; Register Addresses
M_HDR EQU $FFFFC9 ; Host port GPIO data Register
M_HDDR EQU $FFFFC8 ; Host port GPIO direction Register
M_PCRC EQU $FFFFBF ; Port C Control Register
M_PRRC EQU $FFFFBE ; Port C Direction Register
M_PDRC EQU $FFFFBD ; Port C GPIO Data Register
Host Int erface (HI08) Equat es
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-9
M_PCRD EQU $FFFFAF ; Port D Control register
M_PRRD EQU $FFFFAE ; Port D Direction Data Register
M_PDRD EQU $FFFFAD ; Port D GPIO Data Register
M_PCRE EQU $FFFF9F ; Port E Control register
M_PRRE EQU $FFFF9E ; Port E Direction Register
M_PDRE EQU $FFFF9D ; Port E Data Register
M_OGDB EQU $FFFFFC ; OnCE GDB Register
;------------------------------------------------------------------------
;
A.3 Host Interface (HI 08) Equates
;------------------------------------------------------------------------
; Register Addresses
M_HCR EQU $FFFFC2 ; Host Control Register
M_HSR EQU $FFFFC3 ; Host Status Register
M_HPCR EQU $FFFFC4 ; Host Polarity Control Register
M_HBAR EQU $FFFFC5 ; Host Base Address Register
M_HRX EQU $FFFFC6 ; Host Receive Register
M_HTX EQU $FFFFC7 ; Host Transmit Register
; HCR bits definition
M_HRIE EQU $0 ; Host Receive interrupts Enable
M_HTIE EQU $1 ; Host Transmit Interrupt Enable
M_HCIE EQU $2 ; Host Command Interrupt Enable
M_HF2 EQU $3 ; Host Flag 2
M_HF3 EQU $4 ; Host Flag 3
; HSR bits definition
M_HRDF EQU $0 ; Host Receive Data Full
M_HTDE EQU $1 ; Host Receive Data Empty
M_HCP EQU $2 ; Host Command Pending
M_HF0 EQU $3 ; Host Flag 0
M_HF1 EQU $4 ; Host Flag 1
; HPCR bits definition
M_HGEN EQU $0 ; Host Port GPIO Enable
M_HA8EN EQU $1 ; Host Address 8 Enable
M_HA9EN EQU $2 ; Host Address 9 Enable
M_HCSEN EQU $3 ; Host Chip Select Enable
M_HREN EQU $4 ; Host Request Enable
M_HAEN EQU $5 ; Host Acknowledge Enable
M_HEN EQU $6 ; Host Enable
M_HOD EQU $8 ; Host Request Open Drain mode
M_HDSP EQU $9 ; Host Data Strobe Polarity
M_HASP EQU $A ; Host Address Strobe Polarity
M_HMUX EQU $B ; Host Multiplexed bus select
DSP56303 User’s Manual, Rev. 2
A-10 Freescale Semiconductor
Bootstrap Program
M_HD_HS EQU $C ; Host Double/Single Strobe select
M_HCSP EQU $D ; Host Chip Select Polarity
M_HRP EQU $E ; Host Request Polarity
M_HAP EQU $F ; Host Acknowledge Polarity
;------------------------------------------------------------------------
A.4 Serial Communicatio ns Interface (SCI) Equates
;------------------------------------------------------------------------
; Register Addresses
M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high)
M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle)
M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low)
M_SRXH EQU $FFFF9A ; SCI Receive Data Register (high)
M_SRXM EQU $FFFF99 ; SCI Receive Data Register (middle)
M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low)
M_STXA EQU $FFFF94 ; SCI Transmit Address Register
M_SCR EQU $FFFF9C ; SCI Control Register
M_SSR EQU $FFFF93 ; SCI Status Register
M_SCCR EQU $FFFF9B ; SCI Clock Control Register
; SCI Control Register Bit Flags
M_WDS EQU $7 ; Word Select Mask (WDS0-WDS3)
M_WDS0 EQU 0 ; Word Select 0
M_WDS1 EQU 1 ; Word Select 1
M_WDS2 EQU 2 ; Word Select 2
M_SSFTD EQU 3 ; SCI Shift Direction
M_SBK EQU 4 ; Send Break
M_WAKE EQU 5 ; Wakeup Mode Select
M_RWU EQU 6 ; Receiver Wakeup Enable
M_WOMS EQU 7 ; Wired-OR Mode Select
M_SCRE EQU 8 ; SCI Receiver Enable
M_SCTE EQU 9 ; SCI Transmitter Enable
M_ILIE EQU 10 ; Idle Line Interrupt Enable
M_SCRIE EQU 11 ; SCI Receive Interrupt Enable
M_SCTIE EQU 12 ; SCI Transmit Interrupt Enable
M_TMIE EQU 13 ; Timer Interrupt Enable
M_TIR EQU 14 ; Timer Interrupt Rate
M_SCKP EQU 15 ; SCI Clock Polarity
M_REIE EQU 16 ; SCI Error Interrupt Enable (REIE)
; SCI Status Register Bit Flags
M_TRNE EQU 0 ; Transmitter Empty
M_TDRE EQU 1 ; Transmit Data Register Empty
M_RDRF EQU 2 ; Receive Data Register Full
M_IDLE EQU 3 ; Idle Line Flag
Enhanced Synchronous Serial Interfa ce (ESSI) Equates
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-11
M_OR EQU 4 ; Overrun Error Flag
M_PE EQU 5 ; Parity Error
M_FE EQU 6 ; Framing Error Flag
M_R8 EQU 7 ; Received Bit 8 (R8) Address
; SCI Clock Control Register
M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11)
M_COD EQU 12 ; Clock Out Divider
M_SCP EQU 13 ; Clock Prescaler
M_RCM EQU 14 ; Receive Clock Mode Source Bit
M_TCM EQU 15 ; Transmit Clock Source Bit
;------------------------------------------------------------------------
A.5 Enhan ced Synchronous Serial Interface (ESSI) Equates
;------------------------------------------------------------------------
;
; Register Addresses Of SSI0
M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0
M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1
M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2
M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register
M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register
M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register
M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B
M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A
M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A
M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B
M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A
M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B
; Register Addresses Of SSI1
M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0
M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1
M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2
M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register
M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register
M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register
M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B
M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A
M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A
M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B
M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A
M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B
; SSI Control Register A Bit Flags
M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7)
M_PSR EQU 11 ; Prescaler Range
DSP56303 User’s Manual, Rev. 2
A-12 Freescale Semiconductor
Bootstrap Program
M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7)
M_ALC EQU 18 ; Alignment Control (ALC)
M_WL EQU $380000 ; Word Length Control Mask (WL0-WL7)
M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1)
; SSI Control Register B Bit Flags
M_OF EQU $3 ; Serial Output Flag Mask
M_OF0 EQU 0 ; Serial Output Flag 0
M_OF1 EQU 1 ; Serial Output Flag 1
M_SCD EQU $1C ; Serial Control Direction Mask
M_SCD0 EQU 2 ; Serial Control 0 Direction
M_SCD1 EQU 3 ; Serial Control 1 Direction
M_SCD2 EQU 4 ; Serial Control 2 Direction
M_SCKD EQU 5 ; Clock Source Direction
M_SHFD EQU 6 ; Shift Direction
M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1)
M_FSL0 EQU 7 ; Frame Sync Length 0
M_FSL1 EQU 8 ; Frame Sync Length 1
M_FSR EQU 9 ; Frame Sync Relative Timing
M_FSP EQU 10 ; Frame Sync Polarity
M_CKP EQU 11 ; Clock Polarity
M_SYN EQU 12 ; Sync/Async Control
M_MOD EQU 13 ; SSI Mode Select
M_SSTE EQU $1C000 ; SSI Transmit enable Mask
M_SSTE2 EQU 14 ; SSI Transmit #2 Enable
M_SSTE1 EQU 15 ; SSI Transmit #1 Enable
M_SSTE0 EQU 16 ; SSI Transmit #0 Enable
M_SSRE EQU 17 ; SSI Receive Enable
M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable
M_SSRIE EQU 19 ; SSI Receive Interrupt Enable
M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable
M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable
M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable
M_SREIE EQU 23 ; SSI Receive Error Interrupt Enable
; SSI Status Register Bit Flags
M_IF EQU $3 ; Serial Input Flag Mask
M_IF0 EQU 0 ; Serial Input Flag 0
M_IF1 EQU 1 ; Serial Input Flag 1
M_TFS EQU 2 ; Transmit Frame Sync Flag
M_RFS EQU 3 ; Receive Frame Sync Flag
M_TUE EQU 4 ; Transmitter Underrun Error FLag
M_ROE EQU 5 ; Receiver Overrun Error Flag
M_TDE EQU 6 ; Transmit Data Register Empty
M_RDF EQU 7 ; Receive Data Register Full
; SSI Transmit Slot Mask Register A
M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15)
Exception Processing Equate s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-13
; SSI Transmit Slot Mask Register B
M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)
; SSI Receive Slot Mask Register A
M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15)
; SSI Receive Slot Mask Register B
M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31)
;------------------------------------------------------------------------
A.6 Exception Pro cessing Equat es
;------------------------------------------------------------------------
; Register Addresses
M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core
M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral
; Interrupt Priority Register Core (IPRC)
M_IAL EQU $7 ; IRQA Mode Mask
M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low)
M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high)
M_IAL2 EQU 2 ; IRQA Mode Trigger Mode
M_IBL EQU $38 ; IRQB Mode Mask
M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low)
M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high)
M_IBL2 EQU 5 ; IRQB Mode Trigger Mode
M_ICL EQU $1C0 ; IRQC Mode Mask
M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low)
M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high)
M_ICL2 EQU 8 ; IRQC Mode Trigger Mode
M_IDL EQU $E00 ; IRQD Mode Mask
M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level
;(low)
M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level
; (high)
M_IDL2 EQU 11 ; IRQD Mode Trigger Mode
M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask
M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low)
M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high)
M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask
M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low)
M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high)
M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask
M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low)
DSP56303 User’s Manual, Rev. 2
A-14 Freescale Semiconductor
Bootstrap Program
M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high)
M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask
M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low)
M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high)
M_D4L EQU $300000 ; DMA4 Interrupt priority Level Mask
M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low)
M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high)
M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask
M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low)
M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)
; Interrupt Priority Register Peripheral (IPRP)
M_HPL EQU $3 ; Host Interrupt Priority Level Mask
M_HPL0 EQU 0 ; Host Interrupt Priority Level (low)
M_HPL1 EQU 1 ; Host Interrupt Priority Level (high)
M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask
M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low)
M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high)
M_S1L EQU $30 ; SSI1 Interrupt Priority Level Mask
M_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low)
M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high)
M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask
M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low)
M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high)
M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask
M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low)
M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high)
;---------------------------------------------------------------
A.7 Timer Module Equates
;---------------------------------------------------------------
; Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F ; TIMER0 Control/Status Register
M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg
M_TCPR0 EQU $FFFF8D ; TIMER0 Compare Register
M_TCR0 EQU $FFFF8C ; TIMER0 Count Register
; Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B ; TIMER1 Control/Status Register
M_TLR1 EQU $FFFF8A ; TIMER1 Load Reg
M_TCPR1 EQU $FFFF89 ; TIMER1 Compare Register
M_TCR1 EQU $FFFF88 ; TIMER1 Count Register
; Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87 ; TIMER2 Control/Status Register
Direct Memory Access (DMA ) Equat es
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-15
M_TLR2 EQU $FFFF86 ; TIMER2 Load Reg
M_TCPR2 EQU $FFFF85 ; TIMER2 Compare Register
M_TCR2 EQU $FFFF84 ; TIMER2 Count Register
M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register
M_TPCR EQU $FFFF82 ; TIMER Prescaler Count Register
; Timer Control/Status Register Bit Flags
M_TE EQU 0 ; Timer Enable
M_TOIE EQU 1 ; Timer Overflow Interrupt Enable
M_TCIE EQU 2 ; Timer Compare Interrupt Enable
M_TC EQU $F0 ; Timer Control Mask TC(3:0)
M_INV EQU 8 ; Inverter Bit
M_TRM EQU 9 ; Timer Restart Mode
M_DIR EQU 11 ; Direction Bit
M_DI EQU 12 ; Data Input
M_DO EQU 13 ; Data Output
M_PCE EQU 15 ; Prescaled Clock Enable
M_TOF EQU 20 ; Timer Overflow Flag
M_TCF EQU 21 ; Timer Compare Flag
; Timer Prescaler Register Bit Flags
M_PS EQU $600000 ; Prescaler Source Mask
M_PS0 EQU 21
M_PS1 EQU 22
; Timer Control Bits
M_TC0 EQU 4 ; Timer Control 0
M_TC1 EQU 5 ; Timer Control 1
M_TC2 EQU 6 ; Timer Control 2
M_TC3 EQU 7 ; Timer Control 3
;------------------------------------------------------------------------
A.8 Direct Memory Access (DMA) Equates
;------------------------------------------------------------------------
; Register Addresses Of DMA
M_DSTR EQU $FFFFF4 ; DMA Status Register
M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0
M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1
M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2
M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3
; Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register
M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register
DSP56303 User’s Manual, Rev. 2
A-16 Freescale Semiconductor
Bootstrap Program
M_DCO0 EQU $FFFFED ; DMA0 Counter
M_DCR0 EQU $FFFFEC ; DMA0 Control Register
; Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register
M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register
M_DCO1 EQU $FFFFE9 ; DMA1 Counter
M_DCR1 EQU $FFFFE8 ; DMA1 Control Register
; Register Addresses Of DMA2
M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register
M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register
M_DCO2 EQU $FFFFE5 ; DMA2 Counter
M_DCR2 EQU $FFFFE4 ; DMA2 Control Register
; Register Addresses Of DMA4
M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register
M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register
M_DCO3 EQU $FFFFE1 ; DMA3 Counter
M_DCR3 EQU $FFFFE0 ; DMA3 Control Register
; Register Addresses Of DMA4
M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register
M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register
M_DCO4 EQU $FFFFDD ; DMA4 Counter
M_DCR4 EQU $FFFFDC ; DMA4 Control Register
; Register Addresses Of DMA5
M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register
M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register
M_DCO5 EQU $FFFFD9 ; DMA5 Counter
M_DCR5 EQU $FFFFD8 ; DMA5 Control Register
; DMA Control Register
M_DSS EQU$3 ; DMA Source Space Mask
; (DSS0-Dss1)
M_DSS0 EQU0 ; DMA Source Memory space 0
M_DSS1 EQU1 ; DMA Source Memory space 1
M_DDS EQU$C ; DMA Destination Space Mask
; (DDS-DDS1)
M_DDS0 EQU2 ; DMA Destination Memory Space 0
M_DDS1 EQU3 ; DMA Destination Memory Space 1
M_DAM EQU$3f0 ; DMA Address Mode Mask
;(DAM5-DAM0)
Phase Locked Loop (PLL) equates
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-17
M_DAM0 EQU4 ; DMA Address Mode 0
M_DAM1 EQU5 ; DMA Address Mode 1
M_DAM2 EQU6 ; DMA Address Mode 2
M_DAM3 EQU7 ; DMA Address Mode 3
M_DAM4 EQU8 ; DMA Address Mode 4
M_DAM5 EQU9 ; DMA Address Mode 5
M_D3D EQU 10 ; DMA Three Dimensional Mode
M_DRS EQU$F800 ; DMA Request Source Mask (DRS0-DRS4)
M_DCON EQU16 ; DMA Continuous Mode
M_DPR EQU$60000 ; DMA Channel Priority
M_DPR0 EQU17 ; DMA Channel Priority Level (low)
M_DPR1 EQU18 ; DMA Channel Priority Level (high)
M_DTM EQU$380000 ; DMA Transfer Mode Mask
;(DTM2-DTM0)
M_DTM0 EQU19 ; DMA Transfer Mode 0
M_DTM1 EQU20 ; DMA Transfer Mode 1
M_DTM2 EQU21 ; DMA Transfer Mode 2
M_DIE EQU22 ; DMA Interrupt Enable bit
M_DE EQU23 ; DMA Channel Enable bit
; DMA Status Register
M_DTD EQU $3F ;Channel Transfer Done Status MASK
M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0
M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1
M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2
M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3
M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4
M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5
M_DACT EQU 8 ; DMA Active State
M_DCH EQU $E00 ; DMA Active Channel Mask
: (DCH0DCH2)
M_DCH0 EQU 9 ; DMA Active Channel 0
M_DCH1 EQU 10 ; DMA Active Channel 1
M_DCH2 EQU 11 ; DMA Active Channel 2
;---------------------------------------------------------------
A.9 Phase Locked Loop (PLL ) equates
;---------------------------------------------------------------
; Register Addresses Of PLL
M_PCTL EQU $FFFFFD ; PLL Control Register
; PLL Control Register
M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11)
M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)
M_XTLR EQU 15 ; XTAL Range select bit
DSP56303 User’s Manual, Rev. 2
A-18 Freescale Semiconductor
Bootstrap Program
M_XTLD EQU 16 ; XTAL Disable Bit
M_PSTP EQU 17 ; STOP Processing State Bit
M_PEN EQU 18 ; PLL Enable Bit
M_PCOD EQU 19 ; PLL Clock Output Disable Bit
M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3)
;---------------------------------------------------------------
A.10Bus Interface Unit (BIU) Eq uates
;---------------------------------------------------------------
; Register Addresses Of BIU
M_BCR EQU $FFFFFB ; Bus Control Register
M_DCR EQU $FFFFFA ; DRAM Control Register
M_AAR0 EQU $FFFFF9 ; Address Attribute Register 0
M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1
M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2
M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3
M_IDR EQU $FFFFF5 ; ;ID Register
; Bus Control Register
M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)
M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14)
M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2)
M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3)
M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4)
M_BBS EQU 21 ; Bus State
M_BLH EQU 22 ; Bus Lock Hold
M_BRH EQU 23 ; Bus Request Hold
; DRAM Control Register
M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1)
M_BRW EQU $C; Out Of Page Wait States Bits Mask (BRW0-BRW1)
M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)
M_BPLE EQU 11 ; Page Logic Enable
M_BME EQU 12 ; Mastership Enable
M_BRE EQU 13 ; Refresh Enable
M_BSTR EQU 14 ; Software Triggered Refresh
M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7)
M_BRP EQU 23 ; Refresh prescaler
; Address Attribute Registers
M_BAT EQU $3 ; External Access Type and Pin Definition Bits
;Mask BAT(1:0)
M_BAAP EQU 2 ; Address Attribute Pin Polarity
M_BPEN EQU 3 ; Program Space Enable
Bus Interface Unit (BIU ) Equates
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-19
M_BXEN EQU 4 ; X Data Space Enable
M_BYEN EQU 5 ; Y Data Space Enable
M_BAM EQU 6 ; Address Muxing
M_BPAC EQU 7 ; Packing Enable
M_BNC EQU $F00 ; Number of Address Bits to Compare Mask
M_BAC EQU $FFF000 ; Address to Compare Bits Mask BAC(11:0)
; control and status bits in SR
M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR
M_CA EQU 0 ; Carry
M_V EQU 1 ; Overflow
M_Z EQU 2 ; Zero
M_N EQU 3 ; Negative
M_U EQU 4 ; Unnormalized
M_E EQU 5 ; Extension
M_L EQU 6 ; Limit
M_S EQU 7 ; Scaling Bit
M_I0 EQU 8 ; Interrupt Mask Bit 0
M_I1 EQU 9 ; Interrupt Mask Bit 1
M_S0 EQU 10 ; Scaling Mode Bit 0
M_S1 EQU 11 ; Scaling Mode Bit 1
M_SC EQU 13 ; Sixteen_Bit Compatibility
M_DM EQU 14 ; Double Precision Multiply
M_LF EQU 15 ; DO-Loop Flag
M_FV EQU 16 ; DO-Forever Flag
M_SA EQU 17 ; Sixteen-Bit Arithmetic
M_CE EQU 19 ; Instruction Cache Enable
M_SM EQU 20 ; Arithmetic Saturation
M_RM EQU 21 ; Rounding Mode
M_CP0 EQU 22 ; bit 0 of priority bits in SR
M_CP1 EQU 23 ; bit 1 of priority bits in SR
; control and status bits in OMR
M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR
M_MA EQU0 ; Operating Mode A
M_MB EQU1 ; Operating Mode B
M_MC EQU2 ; Operating Mode C
M_MD EQU3 ; Operating Mode D
M_EBD EQU 4 ; External Bus Disable bit in OMR
M_SD EQU 6 ; Stop Delay
M_MS EQU 7 ; Memory Switch bit in OMR
M_CDP0 EQU 8 ; bit 0 of priority bits in OMR
M_CDP1 EQU 9 ; bit 1 of priority bits in OMR
M_BEN EQU 10 ; Burst Enable
M_TAS EQU 11 ; TA Synchronize Select
M_BRT EQU 12 ; Bus Release Timing
M_ATE EQU 15 ; Address Tracing Enable bit in OMR.
M_XYS EQU 16 ; Stack Extension space select bit in OMR.
M_EUN EQU 17 ; Extended stack UNderflow flag in OMR.
DSP56303 User’s Manual, Rev. 2
A-20 Freescale Semiconductor
Bootstrap Program
M_EOV EQU 18 ; Extended stack OVerflow flag in OMR.
M_WRP EQU 19 ; Extended WRaP flag in OMR.
M_SEN EQU 20 ; Stack Extension Enable bit in OMR.
A.11Interrupt Equates
;***************************************************************
;
; EQUATES for 56303 interrupts
;
; Last update: June 11 1995
;
;**************************************************************
page132,55,0,0,0
optmex
intequ ident 1,0
if @DEF(I_VEC)
;leave user definition as is.
else
I_VEC EQU$0
endif
;---------------------------------------------------------------
; Non-Maskable interrupts
;---------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL EQU I_VEC+$04 ; Illegal Instruction
I_DBG EQU I_VEC+$06 ; Debug Request
I_TRAP EQU I_VEC+$08 ; Trap
I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt
;---------------------------------------------------------------
; Interrupt Request Pins
;---------------------------------------------------------------
I_IRQA EQU I_VEC+$10 ; IRQA
I_IRQB EQU I_VEC+$12 ; IRQB
I_IRQC EQU I_VEC+$14 ; IRQC
I_IRQD EQU I_VEC+$16 ; IRQD
;---------------------------------------------------------------
; DMA Interrupts
;---------------------------------------------------------------
I_DMA0 EQU I_VEC+$18 ; DMA Channel 0
I_DMA1 EQU I_VEC+$1A ; DMA Channel 1
I_DMA2 EQU I_VEC+$1C ; DMA Channel 2
I_DMA3 EQU I_VEC+$1E ; DMA Channel 3
I_DMA4 EQU I_VEC+$20 ; DMA Channel 4
I_DMA5 EQU I_VEC+$22 ; DMA Channel 5
Interrupt Equates
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor A-21
;---------------------------------------------------------------
; Timer Interrupts
;---------------------------------------------------------------
I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare
I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow
I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare
I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow
I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare
I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow
;---------------------------------------------------------------
; ESSI Interrupts
;---------------------------------------------------------------
I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data
I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception Status
I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot
I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data
I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception Status
I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot
I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data
I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception Status
I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot
I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data
I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception Status
I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot
;---------------------------------------------------------------
; SCI Interrupts
;---------------------------------------------------------------
I_SCIRD EQU I_VEC+$50 ; SCI Receive Data
I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status
I_SCITD EQU I_VEC+$54 ; SCI Transmit Data
I_SCIIL EQU I_VEC+$56 ; SCI Idle Line
I_SCITM EQU I_VEC+$58 ; SCI Timer
;---------------------------------------------------------------
; HOST Interrupts
;---------------------------------------------------------------
I_HRDF EQU I_VEC+$60 ; Host Receive Data Full
I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty
I_HC EQU I_VEC+$64 ; Default Host Command
;---------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;---------------------------------------------------------------
I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
DSP56303 User’s Manual, Rev. 2
A-22 Freescale Semiconductor
Bootstrap Program
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-1
Programming Reference B
This reference for programmers includes a table showing the addresses of all DSP
memory-mapped peripherals, an exception priority table, and programming sheets for the major
programmable DSP registers. The programming sheets are grouped in the following order:
central processor, Phase Lock Loop (PLL), Host Interface (HI08), Enhanced Synchronous Serial
Interface (ESSI), Serial Communication Interface (SCI), Timer, and GPIO. Each sheet provides
room to write in the value of each bit and the hexadecimal value for each register. You can
photocopy these sheets and reuse them for each application development project. For details on
the instruction set of the DSP56300 family of DSPs, see the DSP56300 Family Manual.
Table B-2, Internal I/O Memory Map (X Data Memory), on page B-2 lists the memory
addresses of all internal peripherals.
Table B-3, Interrupt Sources, on page B-6 lists the interrupt starting addresses and
sources.
Table B-4, Interrupt Source Priorities Within an IPL, on page B-8 lists the priorities of
specific interrupts within interrupt priority levels.
The programming sheets appear in this manual as figures (listed in Table B-1); they show
the major programmable registers on the DSP56303.
Table B-1. Guide to Programming Sheets
Module Program ming Sheet Page
Central
Processor Figure B-1, "Status Register (SR)" page B-10
Figure B- 2, " O perati ng M ode Register ( OMR) " page B-11
IPR Figure B-3, "Interrupt Priority Register-Peripherals (IPRP)" page B-12
Figure B- 3, " Interru pt Priority Register -Peripher als (IPRP)" page B- 12
PLL Figure B- 4, "Phase-Locked Loop Control Register (PCTL)" page B-13
BIU Figure B-5, "Bus Control Register (BCR)" page B-14
Figure B- 6, "DRAM Contr ol Register (DCR)" page B-15
Figure B- 7, " Address Attribute Regist ers (AAR[ 3–0])" page B-16
DMA Figure B- 8, " DMA Control Registers 5–0 (DCR[ 5–0])" page B-17
DSP56303 User’s Manual, Rev. 2
B-2 Freescale Semiconductor
Programming Reference
B.1 Internal I/O Memory Map
HI08 Fi gure B-9, "Host Transmit Data Register" page B-18
Figure B-10, "Host Base Address and Host Port Control Registers" page B-19
Figure B-11, "Host Control Register" page B-20
Figure B-12, "Inter rupt Cont rol and Command Vector Registers" page B-21
Figure B-13, "Interrupt Vect or and Host Transmit Data Regist ers" page B-22
ESSI Figure B-14, "ESSI Control Register A (CRA)" page B-23
Figure B-15, "ESSI Control Register B (CRB)" page B-24
Figure B-16, "ESSI Transmit and Receive Sl ot Mask Registers (TSM, RSM)" page B-25
SCI Figure B-17, "SCI Control Register (SCR)" page B-26
Figure B-18, "SCI Clock Contro l Registers (SCCR)" page B-27
Timers Fi gure B-19, "Tim er Prescaler Load Register (TPL R)" page B-28
Figure B-20, "Timer Control/Status Register (TCSR) " page B-29
Figure B-21, "Timer Load, Compare, and Count Registers (TLR, TCPR, TCR)" page B-30
GPIO Fi gure B-22, "Host Data Di rection and Host Data Registers (HDDR, HDR)" page B-31
Figure B-23, "Port C Registers (PCRC, PRRC, PDRC)" page B-32
Figure B-24, "Port D Registers (PCRD, PRRD, PDRD)" page B-33
Figure B-25, "Port E Registers (PCRE, PRRE, PDRE)" page B-34
Ta ble B-2. Internal I/O Memory Map (X Data Memory)
Peripher al 16-Bit Addre ss 24-Bit Addr ess Registe r Nam e
IPR $FFFF $FFFFFF Interrupt Priority Register Core ( IPRC)
$FFFE $FFFFFE Interrupt Priority Register Peripheral (IPRP)
PLL $ FFFD $ FFFFFD PLL Control Register (PCT L)
OnCE $FFFC $FFFFFC OnCE GDB Regi ster (OGDB)
BIU $FFFB $FFFFFB Bus Control Regi ster (BCR)
$FFFA $FFFFFA DRAM Control Register (DCR)
$FFF9 $FFFFF9 Address Attribute Register 0 (AAR0)
$FFF8 $FFFFF8 Address Attribute Register 1 (AAR1)
$FFF7 $FFFFF7 Address Attribute Register 2 (AAR2)
$FFF6 $FFFFF6 Address Attribute Register 3 (AAR3)
$FFF5 $FFFFF5 ID Register (IDR)
Ta ble B-1. Guide to Programming S heets (Continued)
Internal I/O Memory Map
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-3
DMA $F FF4 $FFFFF4 DMA St atus Register (DSTR)
$FFF3 $FFFFF3 DMA Offset Register 0 (DOR0)
$FFF2 $FFFFF2 DMA Offset Register 1 (DOR1)
$FFF1 $FFFFF1 DMA Offset Register 2 (DOR2)
$FFF0 $FFFFF0 DMA Offset Register 3 (DOR3)
DMA0 $FFEF $FFFFEF DMA Source Address Register (DSR0)
$FFEE $FFFFEE DMA Destination Address Register (DDR0 )
$FFED $FFFFED DMA Count er (DCO0)
$FFEC $FFFFEC DMA Control Regi ster (DCR0)
DMA1 $FFEB $FFFFEB DMA Source Address Register (DSR1)
$FFEA $FFFFEA DMA Destination Address Register (DDR1 )
$FFE9 $FFFFE9 DMA Counter (DCO1)
$FFE8 $FFFFE8 DMA Control Register (DCR1)
DMA2 $FFE7 $FFFFE7 DMA Source Address Register (DSR2)
$FFE6 $FFFFE6 DMA Destination Address Register (DDR2 )
$FFE5 $FFFFE5 DMA Counter (DCO2)
$FFE4 $FFFFE4 DMA Control Register (DCR2)
DMA3 $FFE3 $FFFFE3 DMA Source Address Register (DSR3)
$FFE2 $FFFFE2 DMA Destination Address Register (DDR3 )
$FFE1 $FFFFE1 DMA Counter (DCO3)
$FFE0 $FFFFE0 DMA Control Register (DCR3)
DMA4 $FFDF $FFFFDF DMA Source Address Register (DSR4)
$FFDE $FFFFDE DMA Destination Addre ss Register (DDR4 )
$FFDD $FFFFDD DMA Counter ( DCO4)
$FFDC $FFFFDC DMA Control Register (DCR4)
DMA5 $FFDB $FFFFDB DMA Source Address Register (DSR5)
$FFDA $FFFFDA DMA Destination Addre ss Register (DDR5 )
$FFD9 $FFFFD9 DMA Counter (DCO5)
$FFD8 $FFFFD8 DMA Control Register (DCR5)
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripher al 16-Bit Addre ss 24-Bit Addr ess Registe r Nam e
DSP56303 User’s Manual, Rev. 2
B-4 Freescale Semiconductor
Programming Reference
$FFD7 $FFFFD7 Reserved
$FFD6 $FFFFD6 Reserved
$FFD5 $FFFFD5 Reserved
$FFD4 $FFFFD4 Reserved
$FFD3 $FFFFD3 Reserved
$FFD2 $FFFFD2 Reserved
$FFD1 $FFFFD1 Reserved
$FFD0 $FFFFD0 Reserved
$FFCF $FFFFCF Reserved
$FFCE $FFFFCE Reserved
$FFCD $FFFFCD Reserved
$FFCC $FFFFCC Reserved
$FFCB $FFFFCB Reserved
$FFCA $FFFFCA Reserved
Port B $FFC9 $FFFFC9 Host Port GPIO Data Register (HDR)
$FFC8 $FFFFC8 Host Port GPIO Direction Regi ster (HDDR)
HI08 $FFC7 $FFFFC7 Host Transmit Regis ter (HTX)
$FFC6 $FFFFC6 Host Receive Regi ster (HRX)
$FFC5 $FFFFC5 Host Base Address Register (HBAR)
$FFC4 $FFFFC4 Host Port Control Register (HPCR)
$FFC3 $FFFFC3 Host Status Register (HSR)
$FFC2 $FFFFC2 Host Contr ol Register (HCR)
$FFC1 $FFFFC1 Reserved
$FFC0 $FFFFC0 Reserved
Port C $FFBF $FFFFBF Port C Cont rol Regi ster (PCRC)
$FFBE $FFFFBE Port C Dire ction Regi ster (PRRC)
$FFBD $FFFFBD Por t C GPIO Data Regist er (PDRC)
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripher al 16-Bit Addre ss 24-Bit Addr ess Registe r Nam e
Internal I/O Memory Map
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-5
ESSI 0 $FFBC $FFFFBC ESSI 0 Transmit Data Register 0 (TX00)
$FFBB $FFFFBB ESSI 0 Tr ansmit Data Register 1 (TX01)
$FFBA $FFFFBA ESSI 0 Tr ansmit Data Register 2 (TX02)
$FFB9 $FFFFB9 ESSI 0 Time Slot Regi ster ( TSR0)
$FFB8 $FFFFB8 ESSI 0 Receive Data Regist er (RX0)
$FFB7 $FFFFB7 ESSI 0 Status Register ( SSISR0)
$FFB6 $FFFFB6 ESSI 0 Contro l Register B (CRB0)
$FFB5 $FFFFB5 ESSI 0 Contro l Register A (CRA0)
$FFB4 $FFFFB4 ESSI 0 Transmi t Sl ot Mask Regi ster A (TSMA0)
$FFB3 $FFFFB3 ESSI 0 Transmi t Sl ot Mask Regi ster B (TSMB0)
$FFB2 $FFFFB2 ESSI 0 Receive Slot Mask Register A (RSMA0)
$FFB1 $FFFFB1 ESSI 0 Receive Slot Mask Register B (RSMB0)
$FFB0 $FFFFB0 Reserved
Port D $FFAF $FFFFAF Port D Cont rol Regi ster (PCRD)
$FFAE $FFFFAE Port D Dire ction Regi ster (PRRD)
$FFAD $FFFFAD Por t D GPIO Data Regist er (PDRD)
ESSI 1 $FFAC $FFFFAC ESSI 1 Transmit Data Register 0 (TX10)
$FFAB $FFFFAB ESSI 1 Tr ansmit Data Register 1 (TX11)
$FFAA $FFFFAA ESSI 1 Tr ansmit Data Register 2 (TX12)
$FFA9 $FFFFA9 ESSI 1 Time Slot Regi ster ( TSR1)
$FFA8 $FFFFA8 ESSI 1 Receive Data Regist er (RX1)
$FFA7 $FFFFA7 ESSI 1 Status Register ( SSISR1)
$FFA6 $FFFFA6 ESSI 1 Contro l Register B (CRB1)
$FFA5 $FFFFA5 ESSI 1 Contro l Register A (CRA1)
$FFA4 $FFFFA4 ESSI 1 Transmi t Sl ot Mask Regi ster A (TSMA1)
$FFA3 $FFFFA3 ESSI 1 Transmi t Sl ot Mask Regi ster B (TSMB1)
$FFA2 $FFFFA2 ESSI 1 Receive Slot Mask Register A (RSMA1)
$FFA1 $FFFFA1 ESSI 1 Receive Slot Mask Register B (RSMB1)
$FFA0 $FFFFA0 Reserved
Port E $FF9F $FFFF9F Port E Control Register (PCRE)
$FF9E $FFFF9E Port E Direction Register (PRRE)
$FF9D $FFFF9D Por t E GPIO Data Regist er (PDRE)
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripher al 16-Bit Addre ss 24-Bit Addr ess Registe r Nam e
DSP56303 User’s Manual, Rev. 2
B-6 Freescale Semiconductor
Programming Reference
B.2 Interrupt Sources and Priorities
SCI $FF9C $FFFF9C SCI Control Register ( S CR)
$FF9B $FFFF9B SCI Cl ock Control Register ( SCCR)
$FF9A $FFFF9A SCI Receive Data Register—H igh (SRXH)
$FF99 $FFFF99 SCI Receive Data Register—Middle (SRXM)
$FF98 $FFFF98 SCI Receive Data Register—Low (SRXL)
$FF97 $FFFF97 SCI Tr ansm it Data Register—H igh ( S TXH)
$FF96 $FFFF96 SCI Tr ansm it Dat a Register—Middle (STXM)
$FF95 $FFFF95 SCI Tr ansm it Dat a Register—Low (STXL)
$FF94 $FFFF94 SCI Tr ansm it Address Register (STXA)
$FF93 $FFFF93 SCI St atus Regi ster (SSR)
$FF92 $FFFF92 Reserved
$FF91 $FFFF91 Reserved
$FF90 $FFFF90 Reserved
Triple Timer $FF8F $FFFF8F Timer 0 Control/Stat us Register ( TCSR0)
$FF8E $FFFF8E Timer 0 Load Regist er (TLR0)
$FF8D $FFFF8D Ti m er 0 Compare Regist er (TCPR0)
$FF8C $FFFF8C Ti m er 0 Count Register (TCR0)
$FF8B $FFFF8B Timer 1 Control/Stat us Register (TCSR1)
$FF8A $FFFF8A Timer 1 Load Regist er (TLR1)
$FF89 $FFFF89 Timer 1 Compare Register (TCPR1)
$FF88 $FFFF88 Timer 1 Count Register (TCR1)
$FF87 $FFFF87 Timer 2 Control/Status Register (TCSR2)
$FF86 $FFFF86 Timer 2 Load Regist er ( TLR2)
$FF85 $FFFF85 Timer 2 Compare Register (TCPR2)
$FF84 $FFFF84 Timer 2 Count Register (TCR2)
$FF83 $FFFF83 Timer Prescaler Load Register (TPLR)
$FF82 $FFFF82 Timer Prescaler Count Register ( TPCR)
$FF81 $FFFF81 Reserved
$FF80 $FFFF80 Reserved
Table B-3. Interrupt Sources
Interrupt
Starting Addr ess
Interrupt
Priority L e v el
Range Inter rupt Source
VBA:$00 3 Hardware RESET
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripher al 16-Bit Addre ss 24-Bit Addr ess Registe r Nam e
Inter rupt Sourc es and Priorities
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-7
VBA:$02 3 Stack Error
VBA:$04 3 Illegal Instruction
VBA:$06 3 Debug Request Interrupt
VBA:$08 3 Trap
VBA:$0A 3 Non-Maskable Interrupt (NMI )
VBA:$0C 3 Reserved
VBA:$0E 3 Reserved
VBA:$10 0–2 IRQA
VBA:$12 0–2 IRQB
VBA:$14 0–2 IRQC
VBA:$16 0–2 IRQD
VBA:$18 0–2 DMA Channel 0
VBA:$1A 0–2 DMA Channel 1
VBA:$1C 0–2 DMA Channel 2
VBA:$1E 0–2 DMA Channel 3
VBA:$20 0–2 DMA Channel 4
VBA:$22 0–2 DMA Channel 5
VBA:$24 0–2 Timer 0 Compare
VBA:$26 0–2 Timer 0 Overfl ow
VBA:$28 0–2 Timer 1 Compare
VBA:$2A 0–2 Timer 1 Overf low
VBA:$2C 0–2 Timer 2 Compare
VBA:$2E 0–2 Timer 2 Overf low
VBA:$30 0–2 ESSI0 Receive Data
VBA:$32 0–2 ESSI0 Recei ve Data With Exception Status
VBA:$34 0–2 ESSI0 Recei ve Last Slot
VBA:$36 0–2 ESSI0 Transmit Data
VBA:$38 0–2 ESSI0 Trans mit Data With Except ion Status
VBA:$3A 0–2 ESSI0 Transm it Last Slot
VBA:$3C 0–2 Reserved
VBA:$3E 0–2 Reserved
VBA:$40 0–2 ESSI1 Receive Data
VBA:$42 0–2 ESSI1 Recei ve Data With Exception Status
VBA:$44 0–2 ESSI1 Recei ve Last Slot
Table B-3. Interrupt Sources (Continued)
Interrupt
Starting Addr ess
Interrupt
Priority L e v el
Range Inter rupt Source
DSP56303 User’s Manual, Rev. 2
B-8 Freescale Semiconductor
Programming Reference
VBA:$46 0–2 ESSI1 Transmit Data
VBA:$48 0–2 ESSI1 Trans mit Data With Except ion Status
VBA:$4A 0–2 ESSI1 Transm it Last Slot
VBA:$4C 0–2 Reserved
VBA:$4E 0–2 Reserved
VBA:$50 0–2 SCI Receive Data
VBA:$52 0–2 SCI Receive Data With Exception Status
VBA:$54 0–2 SCI Transmit Data
VBA:$56 0–2 SCI Idle Line
VBA:$58 0–2 SCI Timer
VBA:$5A 0–2 Reserved
VBA:$5C 0–2 Reserved
VBA:$5E 0–2 Reserved
VBA:$60 0–2 Host Recei ve Data Full
VBA:$62 0–2 Host Tran smit Data Empt y
VBA:$64 0–2 Host Comman d (Default)
VBA:$66 0–2 Reserved
:::
VBA:$FE 0–2 Reserved
Table B-4. Interrupt Source Priorities Within an IPL
Priority Interrupt Source
Level 3 (Nonmaskable)
Highest Hardware RESET
Stack Err or
Ill egal Instructi o n
Debug Request Interrupt
Trap
Lowest Non-Maskable Interrupt
Levels 0, 1, 2 (M askable)
Highest IRQA (Extern a l Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
Table B-3. Interrupt Sources (Continued)
Interrupt
Starting Addr ess
Interrupt
Priority L e v el
Range Inter rupt Source
Inter rupt Sourc es and Priorities
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-9
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
Host Comma nd Int errupt
Host Transmit Data Empty
Host Receive Data Full
ESSI0 RX Data with Exception I nterrupt
ESSI0 RX Data Interrupt
ESSI0 Recei ve Last Slot Inter rupt
ESSI0 TX Data With Exception Interrupt
ESSI0 Tr ansmit Last Slot Interrupt
ESSI0 TX Data Interr upt
ESSI1 RX Data With Exception Inter rupt
ESSI1 RX Data Interrupt
ESSI1 Recei ve Last Slot Inter rupt
ESSI1 TX Data With Exception Interrupt
ESSI1 Tr ansmit Last Slot Interrupt
ESSI1 TX Data Interr upt
SCI Receive Data With Exception Inter rupt
Lowest SCI Receive Data
Highest SCI Transmit Data
SC I Id le Li n e
SCI Timer
Timer0 Overflow Inter rupt
Timer0 Compare Inter rupt
Timer1 Overflow Inter rupt
Timer1 Compare Inter rupt
Timer2 Overflow Inter rupt
Lowest Timer2 Compare Int errupt
Table B-4. Interrupt Source Priorities Within an IPL (Continued)
Priority Interrupt Source
DSP56303 User’s Manual, Rev. 2
B-10 Freescale Semiconductor
Programming Reference
B.3 Programming Sheets
Figure B-1. Status Register (SR)
Application:
Date:
Programmer: Sheet 1 of 2
Centra l Processor
1514131211109876543210
UZVC
19 18 17 1623 22 21 20 LLF S1SM I1 I0CE SA FV S0 N
Scaling Mode
S(1:0) Scaling Mode
00
01
10
11
No scaling
Scale down
Scale up
Reserved
*
0*
0
Interrupt Mask
I( 1:0) Exceptions Masked
00
01
10
11
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Carry
Overflow
Zero
Negative
Unnormali zed ( U = Acc(47) xnor Acc(46) )
Extension
Li mit
FFT Scaling ( S = Acc(46) xor Acc(45) )
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteen-Bit Arithmetic
Instruction Cache Enable
Arithmetic Saturation
Rounding Mod e
Core Priority
CP(1:0) Core Priority
00
01
10
11
0 (lowest)
1
2
3 (highest)
*
= Reserved, Program as 0
Mode Register (MR) Condition Code Register (CCR)Extended Mode Register (EMR)
Status Register (SR) Read/Write
Reset = $C00300
CP1 CP0 RM DM SC S E
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-11
Figure B-2. Operating Mode Register (OMR)
Central Processor
Operat ing Mode Register
Reset = $00030X; X = latched from lev els on Mode pins
1514131211109876543210
MS EBD MC MB MA
19 18 17 1623 22 21 20 SDBRT TAS CPD0
*
0
* = Reserved, Program as 0
BEEUN APD ABE MD
Stack Extension Enable, Bit 20
0 = Stack extension disabled
1 = Stack extension enabled
Stack Extension Wrap Flag, B it 19
0 = No st ac k exte ns io n w rap
1 = Stack extens ion wrap ( sticky bit)
Stack Extension Ove rflow Flag, Bit 18
0 = No stack ov erflow
1 = Stack overflow
S tack Exte nsio n X Y Selec t, Bit 16
0 = Mapped to X memory
1 = Mapped to Y memory
Stack Extension Underflow Flag, Bit 17
0 = No stack underflow
1 = Stack underflow
0 = Enables external bus
1 = Disables external bus
External Bus Disable, Bit 4
0 = De lay is 128K clock c ycles
1 = De lay is 16 clock cycl es
Memory Switch Mode, Bit 7
0 = Memory switching disabled
*
0
CPD1XYSWRP EOVSEN
Chip Operating Mode, Bits 3–0
Re fer to th e operat in g mo des
Stop Delay Mode, Bit 6
1 = Memory s witching enabled
Core-DMA Priority, Bits 9–8
TA Synchronize Select, Bit 11
0 = Not synchron ized
1 = Synchronized
CPD[1:0] Description
00 Compare SR[CP] to
ac tive DMA c hannel
priority
01 DMA has higher
priority than core
10 DMA has same
priority as core
11 DMA has lower
priority than core
Cache Burst Mode Enable, Bit 10
0 = Burst Mode disabled
1 = Burst Mode enabled
Address Attribute Pr iority Disable, Bit 14
0 = Priority mechanism enabled
1 = Priority mechanism disabled
Bus Release Timing, Bit 12
0 = Fast Bus Release mode
1 = Slow B us Releas e mode
Asynchronous Bus Arbitration Enable, Bit 13
0 = Synchronization disabled
1 = Synchronizat ion enabled
table in Chapter 4.
*
0*
0ATE
Address Trace Enable, Bit 15
0 = Address Trace mode dis abled
1 = Address Trace mode ena bled
Application: Date:
Programmer: Sheet 2 of 2
DSP56303 User’s Manual, Rev. 2
B-12 Freescale Semiconductor
Programming Reference
Figure B-3. Interrupt Priority Register-Peripherals (IPRP)
Application: Date:
Programmer: Sheet 1 of 2
Interru pt Priority
* = Reserved, Program as 0
Interrupt Priority Register (IPRP) X:$FFFFFE Read/Write
Rese t = $00000 0
HPL1 HPL0 Enabled IPL
00 No —
01 Yes 0
10 Yes 1
11 Yes 2
Host IPL
S0L1 S0L0 Enabled IPL
00 No —
01 Yes 0
10 Yes 1
11 Yes 2
ESSI0 IPL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S1L1 S1L0 S0L1 S0L0 HPL1 HPL0
23 22 21 20 19 18 1617 SCL0SCL1TOL0TOL1
*
0*
0*
0*
0*
0*
0
$0 *
0*
0*
0*
0
$0 *
0*
0*
0*
0
$0
S1L1 S1L0 Enabled IPL
00 No —
01 Yes 0
10 Yes 1
11 Yes 2
ESSI1 IPL
SCL1 SCL0 Enabled IPL
00 No—
01Yes0
10Yes1
11Yes2
S C I IPL
TOL1 TOL0 Enabled IPL
00 No —
01 Yes 0
10 Yes 1
11 Yes 2
Triple Timer IPL
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-13
Figure B-4. Phase-Locked Loop Control Register (PCTL)
Application: Date:
Programmer: Sheet 1 of 1
PLL
1514131211109876543210
MF7 MF5 MF4 MF3 MF2 MF1 MF0
19 18 17 1623 22 21 20 PENCODPD1PD3 MF6PD2 XTLD XTLR DF2 DF1 DF0 MF11PD0 PSTP MF10 MF9 MF8
PLL Control Register (PCTL) X:$FFFFFD Read/Write
Reset = $000000
XTAL Disable Bit (XTLD)
0 = Enable Xtal Oscillator
1 = EXTAL Driven From
An Ext ernal Source
Clock Output Disable (COD)
0 = 50% Duty Cyc le Clock
1 = Pin Held In High State
Crystal Range Bit (XTLR)
0 = External Xtal Freq > 200KHz
1 = External Xtal Freq < 200KHz
Predivision Factor Bits (PD0–PD3)
PD3–PD0 Predivision Factor PDF
$0
$1
$2
•
•
•
$F
1
2
3
•
•
•
16
Multiplication Factor Bits MF0–MF11
MF11–MF0 Multip lication Factor MF
$000
$001
$002
•
•
•
$FFF
$FFF
1
2
3
•
•
•
4095
4096
PSTP and PEN Relationship
PSTP PEN Operation During STOP
PLL Oscillator
0 1 Disabled Disabled
1 0 Disabled Enabled
1 1 Enabled Enabled
Division Factor Bits (DF0–DF2)
DF2–DF0 Division Factor DF
$0
$1
$2
•
•
•
$7
20
21
22
•
•
•
27
DSP56303 User’s Manual, Rev. 2
B-14 Freescale Semiconductor
Programming Reference
Figure B-5. Bus Control Register (BCR)
Bus Interfac e Unit
Bus Contr ol Register (BCR)
Res et = $1 FF FFF
Bus State, Bit 21
0 = DSP is not bus master
Area 0 Wait Control, B its 4– 0
Default Area Wait Control, Bits 20–16
1 = DSP is bus master
Area 3 Wait Control, Bits 15–13
Area 2 Wait Control, Bits 12–10
Bus Request Hold , Bit 23
0 = BR pin is asserted only for attempted
1 = BR pin is always asserted
or pe nd in g ac ces s
NOTE: All BCR bits are read/write control bits.
These read/write control bits de fine
the number of wai t states inserted
into each external SRAM access to
the desi gnated area. The value of
these bits shoul d not be programmed
as zero.
Area 1 Wait Control, Bits 9–5
Application: Date:
Programmer: Sheet 1 of 2
Bits Bit Name # of Wait States
20–16 BDFW[4–0] 0–31
15–13 BA3W[2–0] 0–7
12–10 BA2W[2–0] 0–7
9–5 BA1W[4–0] 0–31
4–0 BA0W[4–0] 0–31
151413121110987654321019 18 17 1623 22 21 20
BRH BBS BDFW[4–0] BA3W[2–0] BA2W[2–0] BA1W[4–0] BA0W[4–0]
X:$FFFFFB Read/Write
*
0
* = Reserved, Program as 0
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-15
Figure B-6 . DRAM Control Register (DCR)
Bus Interfac e Unit
DRAM Cont rol Register (DCR)
Reset = $000000
Refresh Request Rate, Bits 22–15
Refr esh Prescaler, Bit 23
0 = Prescaler bypassed
1 = Divide-by-64 presc aler used
NOTE: All DCR bits are read/write control b its.
These read/write control bits define
th e refres h req uest rate. The bit s
specify a d ivide f rom 1–256
(BRF[7–0] = $00–$FF). A refresh
request is generated every time
th e ref r es h coun te r reac hes ze ro,
Application: Date:
Programmer: Sheet 2 of 3
151413121110987654321019 18 17 1623 22 21 20
BRP BRF[7–0] BPS[1–0] BCW[1–0]
X:$FFFF FA Read /Write
BRW[1–0]BSTR BREN BME BPLE
if the refresh counter is enabled
(i.e., BREN = 1).
Bus Soft war e Trig ge red
0 = Refresh c omplet e/reset
1 = Software triggered refresh request
Bus Refres h
0 = Dis ab le
1 = Ena bl e
Bus Mastership
0 = Dis ab le
1 = Ena bl e
Bus Page Logic
0 = Dis ab le
1 = Ena bl e
* = Reserved, Program as 0
*
0*
0*
0*
0*
0
Bus DRAM Page Si ze, Bits 9–8
00 = 9-bit column wid th, 512
01 = 10-bit column width, 1 K
10 = 11-bit column width, 2 K
11 = 12-bit column width, 4 K
B us Row Ou t-of-P age
00 = 4 wait states
01 = 8 wait states
10 = 11 wait states
11 = 15 wait states
Bus In- Page
00 = 1 wait state
01 = 2 wait states
10 = 3 wait states
11 = 4 wait states
Refresh, Bit 14
Enable, Bit 13
Enable, Bit 12
Enable, Bit 11
Wait States, Bits 1–0
Wait St ates, Bits 3–2
DSP56303 User’s Manual, Rev. 2
B-16 Freescale Semiconductor
Programming Reference
Figure B-7 . Address Attribute Registers (AAR[3–0])
Bus Interface Unit
Address Attribute Registers 3 (AAR3)
Reset = $000000
151413121110987654321019 18 17 1623 22 21 20
*
= Reserved, Program as 0
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
Bu s Packi ng Ena ble , Bit 7
0 = Disable internal packin g/unpacking lo gic
*
0
Bus Access Type, Bits 1–0
Bus Y Data Memory Enable, Bit 5
1 = Enable internal packing/unpacking logic
Bus Nu mber of Address Bits to Compare, Bits 11–8
BN C[3–0] = number of bits (fr om BAC bits) that are
Bus Address to Compare, Bits 23–12
BAC[11–0] = address to compare to the
BAC11
(Combinations BNC[3–0] = 1111, 1110, 1101 are
reserved.)
ex ternal Y data spac e accesses
ex ternal Y data spac e accesses
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
Bus X Data Memory Enable, Bit 4
ex ternal X data spac e accesses
ex ternal X data spac e accesses
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
Bus Program Memory Enable, Bit 3
external program space accesses
external program space accesses
Bus Address Attribute Polarity, Bit 2
0 = AA/RAS signal is active low
1 = AA/RAS signal is active high
BAT[1–0] Encoding
00 Reserved
01 SRAM access
10 DRAM access
11 Reserved
c ompared to the external address
external address in order to decide
whether to assert the AA pin
Application: Date:
Programmer:
She et 3 of 3
BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC BYEN BXEN BPEN BAAP BAT1 BAT0
X:$ FFF FF6 Re ad/ Write
Address Attribute Registers 2 (AAR2) X:$FFFFF7 Read/Write
Address Attribute Registers 1 (AAR1) X:$FFFFF8 Read/Write
Address Attribute Registers 0 (AAR0) X:$FFFFF9 Read/Write
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-17
Figure B-8. DMA Contro l Register s 5–0 (DCR[5–0] )
DMA Contr ol Registers (DCR5–DCR0)
Reset = $000000
151413121110987654321019 18 17 1623 22 21 20
DMA Channel En able, Bit 23
0 = Disables channel operation
1 = Enables channel operation
DMA Interrupt Enable , Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
Three-Dimensional Mode, Bit 10
0 = Three-Dimens ional mode disabled
DMA Transfer Mode, Bits 21–19
DTM[2:0] Triggered By DE Cleared Transfer Mode
000 request yes block transfer
001 request yes word transfer
010 request yes line transfer
011 DE yes block transfer
100 request no block transfer
101 request no word transfer
110 reserved
111 reserved
1 = Three-Dimensional mode enabled
DMA Channel Priority, Bits 18–17
DPR[1:0] Channel Priority
00 Priority level 0 (lowest)
01 Priority level 1
10 Priority level 2
11 Priority level 3 (highes t)
DMA Source Space, Bits 1–0
DSS[1:0] DMA Source Memory
00 X Memory Space
01 Y Memory Space
10 P Memory Space
11 Reserved
DMA Destination Space, Bits 3–2
DSS[1:0] DMA Destination Memory
00 X Memory Space
01 Y Memory Space
10 P Memory Space
11 Reserved
DMA Request Source, Bits 15–11
DRS[4:0] Requesting Device
00000–00011 External (IRQA, IRQB, IRQC, IRQD)
00100–01001 Transfer done from channel 0,1,2,3,4,5
01010–01011 ESSI0 Receive, Transmit Data
01100–01101 ESSI1 Receive, Transmit Data
01110–01111 SCI Receive, Transmit Data
10000–10010 Timer0, Timer1, Timer2
10011 Host Receive Data Full
10100 Host Transmit Data Empty
10101 - 11111 Reserved
DMA Address Mode , Bits 9–4
Non - Th re e -D im e ns io nal Add r es s in g Mo de s ( D3D = 0)
Three-Dimens ional Addressing Mode s (D3D=1)
DAM[5:3]
DAM[2:0] Addressing Mode Counter
Mode Offset Register
Selection
000 2D B DOR0
001 2D B DOR1
010 2D B DOR2
011 2D B DOR3
100 No update A None
101 Postincrement-by-1 A None
110 reserved
111 reserved
DAM[5:3] Addressing Mode Offset Selection
000 2D DOR0
001 2D DOR1
010 2D DOR2
011 2D DOR3
100 No update None
101 Postincrement-by-1 None
110 3D DOR0: DOR1
111 3D DOR2: DOR3
DA M[2–0] = sourc e DA M[5–3] = Destination
DMA
Application: Date:
Programmer: She et 1 of 1
DRS[4–0]DE DTM[2–0] DAM[5–0] DDS[1–0] DSS[1–0]DIE DPR[1–0] DCON D3D
X:$F FFFE4, X : $FFFFE8, X: $FFFFEC Read/W ri t e
X:$FFFF D8, X:$FF FFDC, X:$FF FFE0,
DSP56303 User’s Manual, Rev. 2
B-18 Freescale Semiconductor
Programming Reference
Figure B-9. Host Transmit Data Register
Application:
Date:
Programmer: Sheet 1 of 5
HOST
151413121110987654321019 18 17 1623 22 21 20
Transmit High Byte Transmit Middle Byte Transmit Low Byte
Host Transmit Data ( usually Loaded by pr ogram)
Host Transmit Data Register (HTX) X:$FFFFC7 Write Only
Reset = empty
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-19
Figure B-10. Host Base Address and Host Port Control Registers
Application:
Date:
Programmer: Sheet 2 of 5
HOST 7654321015 BA5 BA3BA7 BA4BA6
*
0
Host Base Address Register (HBAR) X:$FFFFC5 Read/ Write
Reset = $80
8BA8BA9BA10
*
0
1514131211109876543210
HAEN HREN HCSEN HA9EN HA8EN HGEN
*
= Reserved, Progr am as 0
HEN
*
0
HAP HRP HCSP HDDS HRODHMUX HDSPHASP
Host Port Control Register (HPCR) X:$FFFFC4 Read /W ri te
Reset = $00
Host Acknowledge Enable
0 → HACK = GPIO
Host Reque st Enable
0 → HREQ/HACK = GPIO,
1 → HREQ = HREQ, if HDRQ = 0
Host Chip Se lect Enable
0 → HCS/HAI0 = GPIO,
1 → HCS/HA10 = HC8, if HMUX = 0
1 → HCS/HA10 = HC10, if HMUX = 1
Host Address Line 9 Enable
0 → HA9 = GPIO, 1 → HA9 = HA 9
Host Address Line 8 Enable
0 → HA8 = GPIO, 1 → HA8 = HA 8
Host GPIO Port Enable
0 = GPIO Pins Disable, 1 = GPIO Pin Enable
Host Acknowledge Priority
0 = HACK Active Lo w, 1 = HACK Active High
Host Chip Select Polarity
0 = HCS Active Low
Host Dual Data Strobe
0 = Singles Stroke, 1 = Dual Stoke
Ho st Multiplexed Bu s
0 = Nonmultiplexed, 1 = Multiplexed
Host Address Strobe Pol arity
0 = Strobe Active Low, 1 = Str obe Active High
Host Data Stro be Polarity
0 = Strobe Active Low, 1 = Str obe Active High
Host Enable
0 → HI08 Disable
1 → HI 08 Enable
Pins = GPIO
If HDRQ & HREN = 1,
HACK = HACK
Host Request Open Drain
HDRQ HROD HREN/HEW
0
0
1
1
0
1
0
1
1
1
1
1
HTRQ & HRRQ Enable
1 = HCS Active High
Host Request Priority
HDRQ HRP
0
0
1
1
0
1
0
1
HREQ Active Low
HREQ Active High
HTRQ,HRRQ Active Low
HTRQ,HRRQ Active High
DSP56303 User’s Manual, Rev. 2
B-20 Freescale Semiconductor
Programming Reference
Figure B-11. Host Control Register
Application:
Date:
Programmer: Sheet 3 of 5
HOST
*
= Reserved, Program as 0
7654321015
*
0*
0*
0
Hos t Rece iv e Inte rrupt Ena ble
1 = Enable0 = Disable
HCIE HRIEHF3 HTIEHF2
Host Flag 2
Host Command Interrupt Enable
Host Transmit Interrupt Enable
1 = Enable0 = Disable
*
0
Host Control Register (HCR) X:$F FFFC2 Read /Write
Reset = $0
if HRDF = 1
if HTDE = 1
1 = Enable0 = Disable if HCP = 1
Host Flag 3
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-21
Figure B-12. Interrupt Control and Command Vector Registers
Application: Date:
Programmer: Sheet 4 of 5
HOST
76543210
Host Side
RREQHF1 TREQHF0INIT HLEND
Interrupt Control Register (ICR) Host Addr ess: $0 Read/Write
Transmit Request Enable
DMA Off 0 = Interrupts Disabled 1 = Interrupts Enabled
DMA On 0 = DSP → Host 1 = Host → DSP
Host Flags
Write O nly
Init ia lize ( Wri te On ly)
Host Li ttle Endian
Receive Request Enable
DMA Off 0 = Interrupts Disabled 1 = Interrupts Enabled
DMA On 0 = Host → DSP 1 = DSP → Host
0 = No Action 1 = Initial ize DMA
HDRQ
*
0
HDRQ HREQ/HTRQ HACK/HRRQ
0 HREQ HACK
1 HTRQ HRRQ
Reset = $00
*= Reserved, Program as 0
76543210
HC0HC4 HC1HC3HC7 HC5
Comm and Vector Register (CVR )
HC2
Reset = $32
Contains the host command interrupt address HC6
Host Vector
Contains Host Command I nterrup t Address ÷ 2
Host Command
Handshakes Ex ecuti ng Host Co mmand Interrup ts
Host Address: $1 Read/Write
DSP56303 User’s Manual, Rev. 2
B-22 Freescale Semiconductor
Programming Reference
Figure B-13. Interrupt Vector and Host Transmit Data Registers
Application:
Date:
Programmer: Sheet 5 of 5
HOST Host Side
Tran smit Byte Registers Host Add resses : $7, $6, $5, $ 4 Write Only
Reset = $00
707007
Host Transmit Data (usually loaded by program)
$6 $5 $4
00 000000
07
$7
Transmit Middle Byte Transmit High Byte Not UsedTransmit Lo w By te
76543210
IV0IV4 IV1IV3IV7 IV5
Inte rru pt Vector Regi s te r (IV R)
IV2
Reset = $0F
Con t a in s the inte r ru pt ve c tor or nu mber
IV6
Host Addr ess: $3 Read/Write
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-23
Figure B-14. ESSI Co ntrol Register A (CRA)
Application:
Date:
Programmer: S he et 1 of 3
ESSI
1514131211109876543210
PM7 PM5 PM4 PM3 PM2 PM1 PM0
19 18 17 1623 22 21 20 ALCWL0WL1SSC1
* = Reserved, Program as 0
PM6
*
0
*
0
*
0
*
0
Word Length Control
WL2 WL1 WL0 Number of bits/word
0008
00112
01016
01124
1 0 0 32 (data in first 24 bits)
1 0 1 32 (data in last 24 bits)
110Reserved
111Reserved
Select SC1 as Tx#0 drive
enable
0 = SC1 functions as
serial I/O flag
1 = functions as driver
enable of Tx#0
external buffer
Frame Rate Divider Control
DC4:0 = $00-$1F (1 to 32)
Divide ratio for Normal mode
# of time slots for Network
Prescaler Range
0 = divide by 8
1 = divide by 1
Prescale Modulus Select
PM[7–0] = $00-$FF (divide by 1 to 256)
The combination of PSR = 1 and PM[7:0] = $00 is forbidden
*
0WL2 DC4 DC3 DC2 DC1 DC0 PSR
Alignment Control
0 = 16-bit data left aligned to bit 23
1 = 16-bit data left aligned to bit 15
ESSI Control Regi ster A (CRAx ) ESSI0—X:$FFFFB5 Read/Write
ESSI1—X:$FFFFA5 Read/WriteReset = $000000
DSP56303 User’s Manual, Rev. 2
B-24 Freescale Semiconductor
Programming Reference
Figure B-15. ESSI Co ntrol Register B (CRB)
Application:
Date:
Programmer: Sheet 2 of 3
ESSI
1514131211109876543210
FSL0 SCKD SCD2 SCD1 SCD0 OF1 OF0
19 18 17 1623 22 21 20 TIERIERLIEREIE SHFDTEIE TE0 TE1 TE2 MOD SYN CKPTLIE RE FSP FSR FSL1
ESSI Control Register B (CRBx ) ESSI 0—X :$F FF FB6 Read /W rite
ESSI1—X:$FFF FA6 Rea d /W rite
Rese t = $00000 0
Receive Exception Interrupt Enable
0 = Disable 1 = Enable
Transmit 2 Enable (SYN=1 only)
0 = Disable 1 = Enable
Mode Select
0 = Normal 1 = Network
Transmit 1 Enable (SYN=1 only)
0 = Disable 1 = Enable
Transmit Interrupt Enable
0 = Disable 1 = Enable
Receive Interrupt Enable
0 = Disable 1 = Enable
Transmit Last Slot Interrupt Enable
0 = Disable 1 = Enable
Receive Last Slot Interrupt Enable
0 = Disable 1 = Enable
Tra nsmi t Excepti on Int e rrupt Ena ble
0 = Disable 1 = Enable
Transmit 0 Enable
0 = Disable 1 = Enable
Receiver Enable
0 = Disable 1 = Enable
Clock Polarity
0 = out on rising/in on falling
1 = in on rising/out on falling
Sync/Async Control
0 = Asynchronous
1 = Synchr onous
Frame Sync Polarity
0 = high level (positive)
1 = low level (n egative)
F rame Syn c R ela t iv e Ti m ing
0 = with first data bit
1 = 1 clock cycle earlier than first data bit
FSL1 FSL0 Frame Sync
Length
TX RX
0 0 Word Word
01BitWord
10BitBit
11WordBit
Shift Direction
0 = MSB First 1 = LSB First
Clock Source Dir ection
0 = External Clock 1 = Internal Clock
Serial Control Direction Bits (see Table 7-2)
Pin SCDx = 0 (I nput) SCDx = 1 (Output)
SC0 Rx Clk Flag 0
SC1 Rx Frame Sync Flag 1
SC2 Tx Frame Sync Tx, Rx Frame Sync
Outp ut Fla g x
If SYN = 1 and SCD 1 = 1
OFx → SCx Pin
(Tx & Rx transfer together or not)
(clk edge data & Fram e S ync clocked out /in)
( WL Fram e Sync only)
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-25
Figur e B-16. ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)
Application:
Date:
Programmer: Sheet 3 of 3
ESSI
1514131211109876543210
RS23 RS21 RS20 RS19 RS18 RS17 RS16
1623
*
= Reserved, Program as
0
RS22
*
0RS31 RS30 RS29 RS28 RS27
ESSI0—X :$F FF FB2 Read /W rite
ESSI1—X :$F FF FA2 Read /W rite
Reset = $FFFF
ESSI0—X :$F FF FB1 Read /W rite
ESSI1—X :$F FF FA1 Read /W riteReset = $FFFF
ESSI0—X :$F FF FB4 Read /W rite
ESSI1—X :$F FF FA4 Read /W riteReset = $FFFF
ESSI0—X :$F FF FB3 Read /W rite
ESSI1—X :$F FF FA3 Read /W riteReset = $FFFF
ESSI R ece ive Slot Mask A (RSMA [0 –1]
ESSI R ece ive Slot Mask B (RSMB [0 –1] )
ESSI Transmit Slot Mask A (TSMA[0–1])
ESSI Transmit Slot Mask B (TSMB[0–1])
1514131211109876543210
RS7 RS5 RS4 RS3 RS2 RS1 RS0
1623 RS6
*
0RS15 RS14 RS13 RS12 RS11
1514131211109876543210
TS23 TS21 TS20 TS19 TS18 TS17 TS16
1623 TS22
*
0TS31 TS30 TS29 TS28 TS27
1514131211109876543210
TS7 TS5 TS4 TS3 TS2 TS1 TS0
1623 TS6
*
0TS15 TS14 TS13 TS12 TS11
SSI Transmit Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
*
0TS10 TS9 TS8
SSI Transm it Slo t Mask
0 = Ignore Time Slot
1 = Active Time Slot
TS26 TS25 TS24
*
0
RS10 RS9 RS8
RS26 RS25 RS24
*
0
*
0
SSI Receive Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
SSI Receive Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
DSP56303 User’s Manual, Rev. 2
B-26 Freescale Semiconductor
Programming Reference
Figure B-17. SCI Control Re gister (SCR)
Application:
Date:
Programmer: Sheet 1 of 2
SCI
SCI Control Register (SCR)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WOMS WAKE SBK SSFTD WDS2 WDS1 WDS0
23
*
RWU
*
0SCKP STIR TMIE TIE RIE ILIE TE RE
SCI Shif t Directi on
0 = LSB First
1 = MSB First
Send Break
0 = Send break, then revert
1 = Continually send breaks
Receiver Wakeup Enable
0 = receiver has awak ened
1 = Wakeup function enabled
Receiver Enable
0 = Receiver Disabled
1 = Receiver Enabled
Wired-Or Mode Select
1 = M ultid rop
0 = Point to Point
Wa k eup Mode Select
0 = Idle Line Wakeup
1 = Address Bit Wakeup
Word Select Bits
0 0 0 = 8-bit Sync hronous Data (Sh ift Register Mode)
0 0 1 = Reserved
0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
0 1 1 = Reserved
1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)
1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)
1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)
1 1 1 = Reserved
Transmitter Enable
0 = Transmitter Disable
1 = Transmitter Enable
Tran smit Inte rrupt Enabl e
0 = Transmit Interrupts Disabled
1 = Transmit Interrupts Enabled
Idle Line Interrupt Enable
0 = Idle Li ne Interrupt D isabled
1 = Idle Line Interrupt Enabled
Receive Interrupt Enable
SCI Clock Polarity
0 = Clock Polarity is Positive
1 = Clock Polarity is Negative
SCI Timer Interrupt Rate
0 = ÷ 32, 1 = ÷ 1
Timer In terrupt Enable
0 = Time r Interrupts Disabled
1 = Timer Interrupts Enabled
0 = Receive Interrupt Disabled
1 = Idle Line Interrupt Enabled
X:$FFFF9C Read/Wr ite
REIE
16
SCI Receive Exception Inerrupt
0 = Receive Interrupt Disable
1 = Receive Interrupt Enable
= Reserved, Program as 0
Reset $000000
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-27
Figure B-18. SCI Clock Control Registers (SCCR)
Application:
Date:
Programmer: Sheet 2 of 2
SCI
SCI Clock Control Register (SCC R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD7 CD5 CD4 CD3 CD2 CD1 CD0
23
*= Reserved, Program as 0
CD6
*
0TCM RCM SCP COD CD11 CD10 CD9 CD8
Clock Divider Bits (CD11–CD0)
CD11–CD0 Icyc Rate
$000 Icyc/1
$001 Icyc/2
$002 Icyc/3
••
••
••
$FFE Icyc/4095
$FFF Icyc/4096
SCI C lo c k Pr es ca ler
0 = ÷1 1 = ÷ 8
Clock Out Divider
0 = Divide c lock by 16 before feed to SC LK
1 = Feed clock to directly to SCLK
TCM RCM TX Clock RX Clock SCLK Pin Mode
0 0 Internal Internal Output Synchronous/Asynchronous
0 1 Internal External Input Asynchronous only
1 0 External Internal Input Asynchronous on ly
1 1 External External Input Synchronous/Asynchronous
Receiver Clock Mode/So urce
0 = Internal clock for Receiver
1 = External clock from SCLK
Tra ns mit ter Cloc k Mo de /Sou rce
0 = Internal clock for Transmitter
1 = External clock from S CLK
Address X:$FFFF9B Read/Write
Reset = $000000
DSP56303 User’s Manual, Rev. 2
B-28 Freescale Semiconductor
Programming Reference
Figure B-19. Timer Prescaler Load Register (TPLR)
Application:
Date:
Programmer: Sheet 1 of 3
Timers
151413121110987654321019 18 17 1623 22 21 20
PS0PS1
*
0Prescaler Preload Value (PL [20–0])
*= Reserved, Program as 0
Timer Prescaler Load Regi ster (TPLR) X :$FF FF 83 Read/Wri te
Reset = $0000 00
PS (1–0) P rescaler Clock Source
00 Internal CLK/2
01 TIO0
10 TIO1
11 TIO2
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-29
Figu re B-20. Timer Control/Status Register (TCSR)
Application:
Date:
Programmer: Sheet 2 of 3
1514131211109876543210
TC3 TC1 TC0 TCIE TQIE TE
19 18 17 1623 22 21 20
TCF TC2PCE DO DI DIRTOF TRM INV
Timers
*
0*
0
*
0*
0
*
0*
0*
0*
0*
0
Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Ena bl ed
Timer Overflow Interrupt Enab le Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Invert er Bit 8
0 = 0- to-1 tr ansiti ons on TIO input increment the counter,
or high pul s e width meas ured, or high p ulse output on TIO
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measure d, or low puls e outp ut on TIO
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
Tim er Control/S tat us Regis te r TCSR0:$FFFF8F Read/Write
TCSR1:$F FFF8B Read /Write
TCSR2:$F FF F87 Read/W rite
Reset = $000000
*
= Reserved, Program as 0
Timer Reload Mode Bit 9
1 = Timer is reloaded when
selected condition occurs
0 = Timer operates as a free
ru nn in g coun te r
Timer Overflow Flag Bit 20
0 = “1” has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
Direction Bit 1 1
0 = TIO pin is input
1 = TIO pin is output
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Timer Compare Flag Bit 21
0 = “1” has been written to TCSR(TCF),
or timer compare interrupt serviced
1 = Timer Compare has occurred
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or T IO
1 = Clock source is pres caler output
Timer Control Bits 4–7 (TC[3–0])
TC (3:0) TIO Clock Mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GPIO
Output
Output
Input
Input
Input
Input
Output
–
Output
Output
–
–
–
–
–
Internal
Internal
Internal
External
Internal
Internal
Internal
Internal
–
Internal
Internal
–
–
–
–
–
Timer
Timer Pulse
Timer Toggle
Event Counter
Input Width
Input Period
Capture
Pulse Width Modulation
Reserved
Watchdog Pulse
Watchdog Toggle
Reserved
Reserved
Reserved
Reserved
Reserved
DSP56303 User’s Manual, Rev. 2
B-30 Freescale Semiconductor
Programming Reference
Figure B-21. Timer Load, Compare, and Count Registers (TLR, TCPR, TCR)
Application:
Date:
Programmer: Sheet 3 of 3
Timers
151413121110987654321019 18 17 1623 22 21 20
Timer Reload Value
Timer Load Reg ister (TLR[0–2]) TLR0—X: $FFFF8 E Write Onl y
Reset = $xxxxxx, val ue is indeterminate after reset T LR1 — X:$FF FF8A Writ e Onl y
TLR 2—X: $FFFF8 6 Write Onl y
Timer Compare Register (TCP R[0–2 ]) TCPR0—X: $F FFF 8D Read /Write
Reset = $xxxxxx, value is indeterminate after reset T CPR1—X:$F FFF89 Read /Write
TCPR2—X :$FFFF85 Read/Write
Timer Count Register (TCR[0–2 ]) TCR0—X:$FFFF8C Read Only
TCR1— X:$FFF F88 Read Only
TCR2— X:$FFF F84 Read Only
Reset = $000000
151413121110987654321019 18 17 1623 22 21 20
Value Compared to Counte r Value
151413121110987654321019 18 17 1623 22 21 20
Timer Count Value
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-31
Figure B-22. Host Data Direction and Host Data Registers (HDDR, HDR)
Application:
Date:
Programmer: Sheet 1 of 4
GPIO
1514131211109876543210
DR5 DR4 DR3 DR2 DR1 DR0DR6DR15 DR14 DR13 DR12 DR8DR11 DR9DR10
X:$FFFFC8 Write
Reset = $00
Host Data Direction Register (HDDR)
DRx = 0 → HIx is Input
DRx = 1 → HIx is Output
1514131211109876543210
D5 D4 D3 D2 D1 D0D6D15 D14 D13 D12 D8D11 D9D10
X: $FFFFC 9 Wri t e
Reset = Undefined
Host Data Register (HDR)
DRx holds va lue of co rresponding HI08 GP IO pin.
DR7
D7
Function depends on H DDR.
Port B (HI08)
DSP56303 User’s Manual, Rev. 2
B-32 Freescale Semiconductor
Programming Reference
Figure B-23. Port C Registers (PCRC, PRRC, PDRC)
Application:
Date:
Programmer: Sheet 2 of 4
GPIO
236543210
PCC5 PCC4 PCC3 PCC2 PCC1 PCC0
Port C Control Register (PCRC) X:$FFFFBF Read/Write
Reset = $000000
*
0
*
= Reserved, Prog ram as 0
*
0
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPI O
Port C (E SSI0 )
236543210
PRC5 PRC4 PRC3 PRC2 PRC1 PRC0
Port C Direction Register (PRRC) X:$FFFFBE Read/Write
Reset = $000000
*
0
*
0
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
236543210
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
Port C GPIO Data Register (PDRC) X:$FFF FBD Read/Write
Reset = $000000
*
0
*
0
if port pin n i s GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output , then value wri tten to
PDn is reflected on port pin n
Programm ing Sheet s
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor B-33
Figure B-24. Port D Registers (PCRD, PRRD, PDRD)
Application:
Date:
Programmer: Sheet 3 of 4
GPIO Port D (ESSI1 )
236543210
PCD5 PCD4 PCD3 PCD2 PCD1 PCD0
Port D Control Register (PCRD) X:$FFFFAF Read/Write
Reset = $000000
*
0
*
0
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPI O
236543210
PRD5 PRD4 PRD3 PRD2 PRD1 PRD0
Port D Direction Register (PRRD) X:$FFFFAE Read/Write
Reset = $000000
*
0
*
0
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
236543210
PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
Port D GPIO Data Register (PDRD) X:$FFF FAD Read/Write
Reset = $000000
*
0
*
0
if port pin n i s GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output , then value wri tten to
PDn is reflected on port pin n
*
= Reserved, Prog ram as 0
DSP56303 User’s Manual, Rev. 2
B-34 Freescale Semiconductor
Programming Reference
Figure B-25. Port E Registers (PCRE, PRRE, PDRE)
Application:
Date:
Programmer: Sheet 4 of 4
GPIO Port E (SCI)
*
= Reserved, Prog ram as 0
236543210
PCE2 PCE1 PCE0
Port E Control Register (PCRE) X:$FF FF9F Read /Write
Reset = $000000
*
0
*
0
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPI O
236543210
PRE2 PRE1 PRE0
Port E Direction Regi ster (PRRE) X:$FFFF9E Read/Write
Reset = $000000
*
0
*
0
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
236543210
PDE2 PDE1 PDE0
Port E G PIO Data Register (PDRE) X:$FFFF9D Read/Write
Reset = $000000
*
0
*
0
if port pin n i s GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output , then value wri tten to
PDn is reflected on port pin n
*
0*
0*
0
*
0*
0*
0
*
0*
0*
0
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-1
A
adder 1-7
Address Arithmetic Logic Unit (Address ALU) 1-7
Addr ess Attribute Priori ty Disable (APD) bit 4-13
Addre ss Attr ibut e Reg isters ( AAR ) 4-21, 4-26
Bus Access Type (BAT) 4-28
Bus Address Attribute Polarity (BAAP) 4-27
Bus Address to Com pare (BAC) 4-26
Bu s Number of A ddr ess Bits to Compare (BNC) 4-26
Bus Pa ck i ng En ab l e (BP AC ) 4-27
Bus Pro g r am M em o ry En ab l e ( BP EN ) 4-27
Bus X Data Memory Enable (BXEN) 4-27
Bus Y Data Memory Enable (BYEN) 4-27
programming sheet B-16
Address Genera tion Unit (AG U) 1-7
Address Mode Wakeup 8-3
Ad dre ss Trac e En a bl e (A TE ) bit 4-13
Ad dre ss Trace mod e 1-5
addressing modes 1-8
Alignm ent Control (ALC) bit 7-14
Arithmetic Saturation Mode (SM) bit 4-8
Async hronous Bus Arbitra tion Enable (A BE) bit 4-13
as ynchronous data transfe r 8-2
Asynchronous mode 7-9, 8-2, 8-13, 8-15, 8-16
Asynchronous Multidrop mode 8-15
B
barr el shifter 1-6
bit- oriente d instru ctions 5-1
BCHG 5-1
BCLR 5-1
BRCLR 5-1
BRSET 5-1
BSCLR 5-1
BSET 5-1
BSSET 5-1
BTST 5-1
JCLR 5-1
JSCLR 5-1
JSET 5-1
JSSET 5-1
bootstrap 3-1, 3-2
code 8-7
program 4-6, A-1
program options, invoking 4-6
ROM 1-5
Bound ary S can Regis ter ( BS R) 4-34
Burst Mode Enable (BE) bit 4-14
bus address 2-2
data 2-2
external addres s 2-5
external data 2-5
internal 1-10
multiplexed 2-2
non-multiplexed 2-2
Bu s Acc ess Typ e (B AT) bits 4-28
Bus Address Attribute Pola rity (BAAP) bi t 4-27
Bus Address to Compare (BAC) bits 4-26
Bus Area 0 Wait State Control (BA0W) bits 4-23
Bus Area 1 Wait State Control (BA1W) bits 4-23
Bus Area 2 Wait State Control (BA2W) bits 4-22
Bus Area 3 Wait State Control (BA3W) bits 4-22
Bus Column In-Page Wait State (BCW) bit 4-25
Bus Control Register (BCR) 4-21
Bit Definitions 4-22
Bus Area 0 Wait State Control (BA0W) 4-23
Bus Area 1 Wait State Control (BA1W) 4-23
Bus Area 2 Wait State Control (BA2W) 4-22
Bus Area 3 Wait State Control (BA3W) 4-22
Bus Default Area Wait State Control (BDFW) 4-22
Bus Request Hold (BRH) 4-22
Bus Request Hold (BRH) bit 4-22
Bus St ate (BBS) bit 4-22
programmi ng sheet B-14
Bus Default Area Wait State Control (BDFW) bits 4-22
Bus DRAM Page Size (BPS) bit 4-25
Bus Interface Unit (BIU)
Address Attribut e Re gisters (AAR) 4-21
Bus Control Register (BCR) 4-21
DRAM Control Register (DCR) 4-21
Bus Mastership Enable (BME) bit 4-25
Bus Num ber of Address Bits to Compare (BNC) bits 4-26
Bus Pack ing Enable (BPAC) bit 4-27
Index
DSP56303 User’s Manual, Rev. 2
Index-2 Freescale Semiconductor
Index
Bus Page Logic Enable (BPLE) bit 4-25
Bus Program Memory Enable (BPEN) bit 4-27
Bus Refresh Enable (BREN) bit 4-24
Bus Refresh Prescaler (BRP) bit 4-24
Bus Refresh Rate (BRF) bit 4-24
Bus Re leas e Timing (BRT) bit 4-13
Bu s Re quest Hold (BRH) bi t 4-22
Bu s Row O u t-of-P age Wait Stat es (BRW) bi t 4-25
Bus Software Triggere d Reset (BSTR) bit 4-24
Bus X Data Memory Enabl e (BXEN) bit 4-27
Bus Y Data Memory Enabl e (BYEN) bit 4-27
C
Cache Burst Mode Enable (B E) bit 4-14
Cache Enab le (CE ) b i t 4-7, 4-8
Carry (C) bit 4-11
Centra l Processing Unit (CPU) 1-1
Chip Operating Mode (MD–MA) bits 4-14
chip-select
logic 6-16
signal 6-3
Clock 2-4
Clock Divider (CD) bits 8-17
cloc k generator 7-10, 7-16
Clock Generator (CL KGEN) 1-8
Clock Out Divider (COD) 8-17
Clock Output Dis able (COD) bit 4-20
Cloc k Polari ty (CKP) bit 7-20
Clock Prescaler (SCP) 8-17
Clock Source Direction (SCKD) bit 7-21
CMOS 1-5
codec 7-3, 7-9, 7-11
COM byte 4-12
Command Vector Register (CVR) 6-21, 6-24
Host Com mand (HC) 6-24
Host Vector (H V) 6-24
programming sheet B-21
Co ndition Code Registe r ( CCR) 4-7
Carry (C) 4-11
Extension (E) 4-11
Limi t (L) 4-10
Negative (N) 4-11
Overflow (V) 4-11
Scaling (S) 4-10
Unnormalized (U) 4-11
Zero (Z) 4-11
Co ntr ol Regis ter A (CRA)
Alignment Control (ALC) 7-14
Frame Rate Divider Control (DC) 7-15
Prescale Modulus Select (PM) 7-15
Pres cale r Rang e (PSR) 7-15
programming sheet B-23
Select SCK (SSC1) 7-13
Word Lengt h Control (WL) 7-14
Control Register B ( CRB)
Clo ck P olarity (CKP) 7-20
Clock Source Dire ction (SCKD) 7-21
Frame Sync Length (FSL) 7-21
Frame Sync Polarity (FSP) 7-20
Frame Sync Relative Timing (FS R) 7-21
Mode Select (MOD) 7-20
programmi ng sheet B-24
Rece ive En able (R E) 7-19
Receive Exception Interrupt Enable (RE I E) 7-18
Receive Interrupt Enable (RIE) 7-18
Re ceive Last Slo t Int err u p t Enab l e ( RL I E) 7-18
Serial Control Direction 0 (SCD0) 7-22
Serial Control Direction 1 (SCD1) 7-22
Serial Control Direction 2 (SCD2) 7-21
Serial Output Fla g 0 (OF0) 7-22
Serial Output Fla g 1 (OF1) 7-22
Shift Dire ctions (S HFD) 7-21
Synchr onous /Asynchronous (S YN) 7-20
Transmit 0 Enable (TE0) 7-19
Transmit 1 Enable (TE1) 7-19
Transmit 2 Enable (TE2) 7-20
Transmi t Excepti on Interrupt Enable ( TEI E) 7-18
Transmit Interrupt Enable (TIE) 7-18
Transmi t Last Slot Interrup t E nab l e (TLIE) 7-18
Core Priority (CP) bits 4-8
Core-DMA Priority (CDP) bits 4-14
crystal frequency 8-6
Crystal Range (XTLR) bit 4-21
D
data and control host processor registers 6-12
Data Arithmetic Logic Unit (Data ALU) 1-6
Data Input (DI) bit 9-25
dat a memory expansion 1-9
Data Outpu t (DO) bit 9-25
data strobe 6-3
data transfer methods 5-2
Debug support 1-5
Direct Memory Access (DMA) 6-5, 6-8
Request Source bits 4-28
trans fers an d host bus 6-8
triggered by timer 9-21
Direction (DIR) bit 9-25
Divisi on F actor (DF) bits 4-21
DMA Address Mode (DAM) bit 4-33
DMA Channel Enable (DE) bit 4-28
DMA Channel Priority (DPR) bit 4-30
DMA Continuous Mode Enable (DCON) bit 4-31
DMA Control Registers (DCR5–DCR0)
programmi ng sheet B-17
DMA Control Registers (DCRs) 4-28
bit definitions 4-28
DMA Address Mode (DAM) 4-33
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-3
Index
DMA Channel Enable (DE) 4-28
DMA Channel Priori ty (DPR) 4-30
DMA Continuous Mode Enable (DCON) 4-31
DMA Destin ation Spac e (D DS) 4-33
DMA Interrupt Enable (DIE) 4-28
DMA Request Source (DRS) 4-32
DMA Source Space (DSS) 4-33
DMA Three- Dim ens ional Mode (D3D) 4-32
DMA Transfer Mode (DTM) 4-29
DMA Destin ation Spac e (D DS) bit 4-33
DMA Interrupt Enable (DIE) bit 4-28
DMA Request S ource (DRS) bit 4-32
DMA Source Space (DSS ) bit 4-33
DMA Three- Dim ensional Mode (D3D) bit 4-32
DMA Transfer Mode (DTM) bit 4-29
DO FOREVER (FV) Flag bit 4-9
DO loop 1-8
Do Loop Flag (LF) bit 4-9
double data strobe mode 2-2
Double Host Request (HDRQ) bit 6-8, 6-23
Doub l e-Pr ecisi on M ul tip l y Mo d e (D M) bi t 4-9
DRAM Control Regist er (DCR) 4-21, 4-23
Bit D efinitions 4-24
Bus Column In-Page Wait State (BCW) 4-25
Bus DRAM Page Si ze (BPS) 4-25
Bus Mastership Enable (BME) 4-25
Bus Page Logic Enable (BPLE) 4-25
Bus Refresh Enable (BREN) 4-24
Bus Refresh Prescaler (BRP) 4-24
Bus Refresh Rate (BRF) 4-24
Bu s Row O u t-of-P age Wait Stat es (BRW) 4-25
Bus Software Triggere d Reset (BSTR) 4-24
programming sheet B-15
DSP core
programming model 6-11
DSP56300
core 1-1
Family Manual 1-1, 1-5, 6-8
DSP56303
Tec hnical Data 1-1
DSP-to-host
data word 6-2
handshaking protocols 6-2
interrupts 6-2
mapping 6-2
transfer modes 6-2
transfers 6-5, 6-19
dynamic memory configuration switching 3-5
E
Enha nce d Sy nchronous Serial Interf ac e (ESSI) 1-12, 2-2,
2-15, 2-16, 7-1
24-bit fractional data 7-14
after reset 7-6
Asynchr onous mode 7-3, 7-4, 7-10, 7-19
audio enhancem ents 7-2
byte format 7-11
clock generator 7-10, 7-16
Clock S ources 7-3
codec 7-11
control and time slot registers 7-6
control direction of S C2 I/O signal 7-21
Control Register A (CRA)
Alignment Control (ALC) 7-14
Frame Rate Divider Control (DC) 7-15
Prescale Mo d u l us Select (PM) 7-15
Prescaler Ran g e ( PSR) 7-15
programmi ng sheet B-23
Selec t SCK (SSC1) 7-13
Word Length Control (WL) 7-14
Control Register B ( CRB)
Clo ck P olarity (CKP) 7-20
Clock Source Dire ctions (SCKD) 7-21
Frame Sync Length (FSL) 7-21
Frame Sync Polarity (FSP) 7-20
Frame Sync Relative Timing (FS R) 7-21
Mode Select (MOD) 7-20
programmi ng sheet B-24
Rece ive En able (R E) 7-19
Receive Exception Interrupt Enable (RE I E) 7-18
Receive Interrupt Enable (RIE) 7-18
Rece ive Last Slo t Int er ru p t En ab l e 7-18
Serial Control Direction 0 (S CD0) 7-22
Serial Control Direction 1 (S CD1) 7-22
Serial Control Direction 2 (S CD2) 7-21
Serial Output Fla g 0 (OF0) 7-22
Serial Output Fla g 1 (OF1) 7-22
Shift Direction (SHFD) 7-21
Synchr onous /Asynchronous (S YN) 7-20
Transmit 0 Enable (TE0) 7-19
Transmit 1 Enable (TE1) 7-19
Transmit 2 Enable (TE2) 7-20
Transmi t Excepti on Interrupt Enable ( TEI E) 7-18
Transmit Interrupt Enable (TIE) 7-18
Transmit La st Slot Interrupt Enable (TLIE) 7-18
control regis ters 7-12
data and control signals 7-2
DMA 7-6
exception configuration 7-8
exceptions 7-7
receive last slot interrupt 7-7
transmit data 7-8
transmit data with exception status 7-7
tran smit la st slot inter r upt 7-7
flags 7-12
frame rate divide r 7-9
frame sync
generator 7-16
length 7-10
DSP56303 User’s Manual, Rev. 2
Index-4 Freescale Semiconductor
Index
polarity 7-11
selection 7-10
signal 7-7, 7-9, 7-17
word le ngth 7-11
initialization 7-6
initialization example 7-6
internally generated clock and frame sync 7-7
interrupt 7-7
Interrupt Service Routine (IS R) 7-8
interrupt trigge r event 7-9
interrupts 7-7
multiple serial device selection 7-4
network enhancements 7-2
Network mode 7-2, 7-7, 7-9, 7-19, 7-20
Normal mode 7-2, 7-9, 7-19
On-Demand m ode 7-9, 7-14, 7-19
operating mode 7-6, 7-9, 7-20
polling 7-7
Port Control Register (PCR) 7-6, 7-33
Port C ontrol Register C (PCRC) 7-33
Port Control Register D (PCRD) 7-33
Port Data Register (PDR) 7-34
Port Data Regis ter C (PDRC) 7-34
Port Data Register D (PDRD) 7-34
Port Dire ction Register (P RR) 7-34
Port Dire ction Register C (PRRC) 7-34
Port Dire ction Register D (PR RD) 7-34
prescale divider 7-15
programming model 7-12
receive data interr upt request 7-27
Receive Data Regis ter (RX) 7-12, 7-28
Receive Sh if t Re g ister 7-28
rece ive shift regis ter clock output 7-4
Receive Slot Mask Register (RSM)
programming sheet B-25
Rece iv e S lot Mask Re gis t ers (RSM A an d RSM B) 7-12,
7-32
reset 7-6
RX clock 7-10
RX frame sync 7-10
RX frame sync pulses act ive 7-10
se lec t source of clock signal 7-21
Se rial Clock (SCK), ESSI 7-3
Serial Control 0 (SC00 and SC10) 7-3
Serial Control 1 (SC01 and SC11) 7-4
Serial Control 2 (SC02 and SC12) 7-5
Serial Input Flag (IF0) 7-4
Serial Output Flag 0 (OF0) bit 7-4
Serial Output Flags (OF0–OF1) 7-17
Serial Receive Data (SRD) 7-3
Serial Transmit Data (STD) 7-2
SPI protocol 7-2
Synchronous mode 7-3, 7-4, 7-10, 7-12
Synchronous Serial Inte rface Sta tus Register
(SSISR) 7-12, 7-26
bit definitions 7-27
Rece iv e D at a R eg iste r Ful l ( RD F) 7-27
Rece iv er F r ame Sy nc Flag ( RFS) 7-27
Receiver Overrun Error Flag (ROE) 7-27
Serial Input Flag 0 (IF0) 7-28
Serial Input Flag 1 (IF1) 7-28
Transmit Data Register Empty (TDE) 7-27
Trans mit Fram e Sync Flag (TFS ) 7-27
Transmitter Unde rrun Error Flag (TUE) 7-27
Synchr onous /Asynchronous (SYN) bit 7-10
Time Slot Register (TSR) 7-8, 7-31
Transmit Data Registers (TX0–TX2) 7-12, 7-31
Transmit Enable (TE) 7-17
Transmit Shift Registers 7-28
Tr ansm it Slot Mask Reg ister (TSM)
programmi ng sheet B-25
Transmit S lot Mask Registers (TS MA and
TSMB) 7-12, 7-31
TX clock 7-10
variable prescaler 7-15
word length frame sync 7-11
word length frame sy nc timing 7-11
EOM byte 4-12
ESSI0 Interrupt Priority L evel (S0L ) bits 4-16
ESSI1 Interrupt Priority L evel (S1L ) bits 4-16
expansion memory 3-1
Extended Mode Register (EMR) 4-7
Arithmetic Saturation Mode (SM) 4-8
Ca ch e En a bl e ( CE ) 4-8
Core Priority (C P) 4-8
DO FOREVER (FV) Flag 4-9
Rounding Mode ( RM) 4-8
Sixteen-Bit Arith me tic Mode (SA) 4-8
Extensi on (E) bit 4-11
external address bus 2-5
external bus control 2-5, 2-7
External Bus Disable (EBD) bit 4-14
external data bus 2-5
External Memory Expansion Port 2-5
F
frame rate divide r 7-9
Frame Ra te Divider Control (DC) bits 7-15
frame sync
generator 7-16
length 7-10
selection 7-10
signal 7-7, 7-9, 7-17
Frame Sync Leng th (F S L) bit s 7-21
Frame Sync Polarity (FSP) bi t 7-20
Frame Sync Relative Timing (FS R) bit 7-21
Framing Error Fl ag (FE) bit 8-15
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-5
Index
G
general-purpose flags for host-DSP com munication 6-6
General-Pu rpos e Input/Output (GPIO) 1-12, 2-2, 2-17
functions 6-3
Host Data Direction Register (HDDR ) 6-12, 6-30
Host Data Register (HDR) 6-12, 6-30
Port B 5-6
Port C 5-7
Port D 5-7
Port E 5-7
Global Data Bus (GDB) 1-10
Ground 2-3
PLL 2-3
H
HACK si gnal 6-18
handshaking mechanisms
HI08 6-5
hardwa re stack 1-8
HI08 1-12
ISR Transmit Data Register Empty 6-25
HI08 Int errupt Priority Level (HPL) bit s 4-16
Host Acknowledge Enable (HAEN) bit 6-18
Host Acknowledge Polarity (HAP) bit 6-16
Host Address Line 8 Enable (HA8EN) 6-18
Host Address Line 9 Enable (HA9EN) 6-18, 7-19
Host Address Strobe Polarity (HASP) bit 6-17
Host Base Addre ss Register (HBAR) 6-12, 6-15, 6-30
programming sheet B-19
Host Chip Select Enable (HCSEN) bit 6-18
Host Chip Sel ect Po larity (HSCP) bit 6-17
Host Command (HC) bit 6-24
Host Command Interrupt Enable (HCIE) bit 6-13
Host Command Pending (HCP) bit 6-14
Host Control Register (HCR) 6-12, 6-28
Host Command Interrupt Enable (HCIE) 6-13
Host Flags 2,3 (HF) 6-12
Host Receive Interrupt Enable (HRIE) 6-13
Host Transmit Interrupt Enable (HTIE) 6-13
programming sheet B-20
Host Data Direction Register (HDDR ) 6-3, 6-12, 6-14
programming sheet B-31
Host Data Direction Register (HDRR) 6-30
Host Data Register (HDR) 6-12, 6-15, 6-30
programming sheet B-31
Host Data Strobe Pola rity (HDSP) bi t 6-17
Host Dual Data Strobe (HDDS) bit 6-17
Host En a ble (H EN) bit 6-17
Host Flag 0 (HF 0) bit 6-23
Host Flag 1 (HF 1) bit 6-23
Host Flag 2 (HF 2) bit 6-25
Host Flag 3 (HF 3) bit 6-25
Host Flag s 0, 1 (HF) bit s 6-14
Host Flags 2,3 (HF) bits 6-12
Host GP IO Port Enable (HGEN) bit 6-18
Host Interfa ce (HI08) 2-2, 2-9, 2-10, 2-12, 6-1
chip-s elect logic 6-16
Command Vector Register (CVR) 6-7, 6-21
Host Com ma nd ( H C) 6-24
Host Vector (HV) 6-24
programmi ng sheet B-21
configuring host request mode 6-8
control operating m ode 6-16
core communication with HI08 regi sters 6-11
core interru pts
hos t command 6-7
receive data re gis ter full 6-7
transmit data empty 6-7
data registers 6-21
data strobe 6-3
Direct Memory Access (DMA) 6-8
DMA transfers and host bus 6-8
double-buffered mechani sm 6-5
DSP co re 6-5
programmi ng mod el 6-11
DSP core interrupts 6-6
DSP interrupt rou tines 6-21
DSP-side
control regis ters 6-12
data registers 6-12
re gisters aft er rese t 6-20
DSP-to-host
data word 6-2
hands haking protocols 6-2
interrupts 6-2
mapping 6-2
transfer modes 6-2
transfers 6-5, 6-19
dual hos t reques t enabled 6-9
dual-s trobe mode 6-19
enabling host request s 6-8
external host address inputs 6-27
external host program mer’s model 6-20
four kinds of reset 6-27
four reset typ es 6-20
general-purpose flags for host-DSP commu nication 6-6
GPIO configuration options 6-14
GPIO functions 6-3
HACK signal 6-18
HACK/HRRQ ha ndshake flags 6-21
handshaking mechanism s 6-5
hands haking protocols 6-5
choosing 6-6
Core DMA access 6-5
host req uest 6-5
interrupts 6-5
pros and cons of polling 6-6
DSP56303 User’s Manual, Rev. 2
Index-6 Freescale Semiconductor
Index
software polling 6-5
hardwa re re set 6-20, 6-27
HI08-to-DSP core interface 6-1
HI08-to-host
interface 6-1
Host Base Addre ss Register (HBAR) 6-12, 6-15, 6-30
programming sheet B-19
hos t co mman d 6-7, 6-21
Host Control Register (HCR) 6-12, 6-28
Host Command Interrupt Enable (HCIE) 6-13
Host Flags 2, 3 (HF) 6-12
Host Receive Interrupt Enable (HRIE) 6-13
Host Transmit Interrupt Enable (HTIE) 6-13
programming sheet B-20
Host Data Direction Register (HDDR ) 6-3, 6-12, 6-14
programming sheet B-31
Host Data Direction Register (HDRR) 6-30
Host Data Register (HDR) 6-12, 6-15, 6-30
programming sheet B-31
host inte rrupt request pins (IRQx) 6-8
Host Port Control Register (H PCR) 6-3, 6-12, 6-16,
6-20, 6-28, 6-29
Host Acknowledge Enable (H AEN) 6-18
Host Acknowledge Polarity (HAP) 6-16
Host Address Line 8 Enable (HA8EN) 6-18
Host Address Line 9 Enable (HA9EN) 6-18, 7-19
Host Address Strobe Polarity (HASP) 6-17
Host Chip Select Enable (HCSEN) 6-18
Host Chip S elect Pola r ity (HCSP) 6-17
Host Data Strobe Polarity (HDSP) 6-17
Host Dual Data Strobe (HDDS) 6-17
Host En a ble (H EN) 6-17
Host GPIO Port Enable (HGEN) 6-18
Host Multiplexed Bus (HMUX) 6-17
Host Request Enable (HREN) 6-18
Host Request Open Drain (HROD) 6-17
Host Request Polarity (HRP ) 6-16
programming sheet B-4, B-19
host processor registers 6-12
Host Receiv e (HRX) regis te r 6-5, 6-19, 6-30
Hos t Re ceive Data Register (HRX) 6-19
Hos t Re ceive Request (HRRQ) 6-8
host request line 6-3
host request pins 6-9
host side
Command Vector Register (CVR) 6-24
Interface Control Regist er (ICR ) 6-22
Interface Stat u s Reg i ster (ISR) 6-24
Interface Vector Re g i st er (IVR) 6-26
Receive Byte Regi ster s (R XH, RXM, RXL ) 6-26
Transmit Byte Registers (TXH, TXM, TXL) 6-27
host side regist ers after reset 6-27
Host Status Register (HSR) 6-12, 6-13, 6-30
Host C omm a nd Pe n d i ng (HCP ) 6-14
Host Flags 0, 1 (HF) 6-14
Host Receive Data Full (HRDF) 6-14
Host Trans mit Data Empty (HT DE) 6-14
Host Transmit (HTX) register 6-6, 6-19, 6-26, 6-30
Host Transmit Data Register (HTDR)
programmi ng sheet B-18, B-22
host-side
register map 6-22
host-to-DSP
data transfers 6-5, 6-19
data word 6-1
hands haking protocols 6-1
instructions 6-1
mapping 6-1
HREQ/HTRQ hands hake fla gs 6-21
instructions and addressi ng modes. 6-4
Interface Control Register (ICR) 6-21, 6-22
Double Host Request (HDRQ) 6-8, 6-23
Host Flag 0 (HF0) 6-23
Host Flag 1 (HF1) 6-23
Host Little Endian (HLEND) 6-23
Initialize (INIT) 6-22
Receive Request Enable (RREQ) 6-23
Tr ansmit Reque st Enabl e (TR EQ ) 6-23
Interface Status Register (ISR) 6-21, 6-24
Host Flag 2 (HF2) 6-25
Host Flag 3 (HF3) 6-25
Hos t Request (H REQ) 6-25
Rece iv e D at a F u ll (R D F ) 6-6
Receive Data Register Full (RXDF) 6-26
Transmit Data Empty (TDE) 6-6
Transmit Dat a Register Empty (TXDE) 6-25
Transmitter Ready (TRDY) 6-25
interrupt routines 6-7
Interrupt Ve ctor Register (IVR) 6-21, 6-26
programmi ng sheet B-22
interrupt-based techniques 6-20
masking interrupts 6-7
MOVEP instruction 6-12
multiplexed bus mode 6-3, 6-15, 6-18
non-multiplexed bus mode 6-3, 6-18
pipeline 6-5
polling technique s 6-20, 6-26
programmi ng mod el
DSP side 6-11
host side 6-20
quick reference 6-28
Receive Byte Re gisters ( RX H , RH M, RH L) 6-6
Receive Byte Re gisters ( RX H , RX M, RX L) 6-5, 6-26
regi s t e r ban k s 6-4
request service from host 6-8
resets
hardware and software 6-3, 6-12
single-strobe mode 6-19
softwa re polling 6-6
software reset 6-27
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-7
Index
STOP comman d 6-21
STOP instruc tion 6-27
Stop mode 6-21
tim ing requir ements 6-6
Transmit Byte Registers 6-5
Transmit Byte Registers (TXH, TXM, TXL) 6-27
Transmit Data Registers (TXH, T XM, TXL) 6-5
T ransmit R e gist ers (TXH, TXM, TXL) 6-6
vect or registers 6-21
Host Lit le Endian (HLEND) bit 6-23
Host Multiplexed Bus (HMUX) bit 6-17
host port
configuration 2-9
usa ge conside r ations 2-9
Host Port Control Register (H PCR) 6-3, 6-12, 6-16, 6-20,
6-28, 6-29
Host Acknowledge Enable (H AEN) 6-18
Host Acknowledge Polarity (HAP) 6-16
Host Address Line 8 Enable (HA8EN) 6-18
Host Address Line 9 Enable (HA9EN) 6-18, 7-19
Host Address Strobe Polarity (HASP) 6-17
Host Chip Select Enable (HCSEN) 6-18
Host Chip S elect Pola r ity (HCSP) 6-17
Host Data Strobe Polarity (HDSP) 6-17
Host Dual Data Strobe (HDDS) 6-17
Host En a ble (H EN) 6-17
Host GPIO Port Enable (HGEN) 6-18
Host Multiplexed Bus (HMUX) 6-17
Host Request Enable (HREN) 6-18
Host Request Open Drain (HROD) 6-17
Host Request Polarity (HRP ) 6-16
programming sheet B-4, B-19
host proc essor add ress spac e 6-21
Host Receiv e (HRX) regis te r 6-5, 6-12, 6-19, 6-30
Host Receive Data Full (HRDF) bit 6-6, 6-14
Host Receive Interrupt Enable (HRIE) bit 6-13
Hos t Re ceive Request (HRRQ) 6-8
host request 6-5
double 2-2
enabling 6-8
single 2-2
Host Request (HREQ) bit 6-25
Host Request Ena ble (HREN) bit 6-18
host request line 6-3
Host Reque s t Open Dra in (HROD) bit 6-17
host request pins 6-9
Host Request Polarity (HRP ) bit 6-16
Host Status Register (HSR) 6-12, 6-13, 6-30
Host C omm a nd Pe n d i ng (HCP ) 6-14
Host Flags 0, 1 (HF) 6-14
Host Receiv e Data Full (HRDF) 6-14
Host Tra ns mi t Dat a Em pty (HT D E) 6-14
Host Transmi t (H TX) reg ister 6-6, 6-12, 6-19, 6-30
Host Tr a nsm i t Data Empty (HT D E) bit 6-6, 6-14
Host Transmit Data Register (HTDR)
programmi ng sheet B-18, B-22
Host Transmit Interrupt Enabl e (HTIE) bit 6-13
Host Vector (HV) bit s 6-24
Hosts Interface (HI08)
Interrupt Control Registe r (ICR)
programmi ng sheet B-21
host - to - D S P tr ans fe r s 6-5
I
I/O space
X data memory 3-3, 3-4
Idle Line Flag (IDLE) bit 8-16
Idle Line Int errupt Enable (ILIE) bit 8-12
Idle Li ne Wake up mode 8-3
Initializ e (INIT) bit 6-22
initializi ng the timer 9-3
instruction cache 1-5, 3-2
location 3-6
Interface Control Register (ICR) 6-22
Double Host Request (HDRQ) 6-8, 6-23
Host Flag 0 (HF0) 6-23
Host Flag 1 (HF1) 6-23
Host Little Endian (HLEND) 6-23
Initialize (INIT) 6-22
Receive Request Enable (RREQ) 6-23
Tr ansmit Reque st Enabl e (TR EQ ) 6-23
Interface Status Register (ISR) 6-24
Host Flag 2 (HF2) 6-25
Host Flag 3 (HF3) 6-25
Hos t Request (H REQ) 6-25
Rece iv e D at a F u ll (R D F ) 6-6
Receive Data Register Full (RXDF) 6-26
Transmit Data Empty (TDE) 6-6
Transmit Dat a Register Empty (TXDE) 6-25
Transmitter Ready (TRDY) 6-25
Interface Vector Re gister (IVR) 6-26
internal buses 1-10
internal I/ O memory map B-2
internal pro gram memory 3-1, 3-2
interrupt 1-8, 5-2
configuring 4-15
Host Interfa ce (HI08) 6-5, 6-6
priorities B-8
source priorities 4-18
sources 4-15, 4-16, B-6
table 4-15
table, memory map 4-16
trigger mode 4-16
vector 4-16
interrupt and mode control 2-8
interrupt conditions 5-2
interru pt control 2-8
Interrupt Control Registe r (ICR)
programmi ng sheet B-21
DSP56303 User’s Manual, Rev. 2
Index-8 Freescale Semiconductor
Index
Interrupt Mas k (I) bits 4-10
Interrupt Priority Register Core (IPR C) 4-15
IRQD–IRQA Priority and Mode (IDL–IAL) 4-15
Interrupt Priority Re gister Peripherals (IPRP) 4-15, 4-16
ESSI0 Interrupt Priority Level (S0L) 4-16
ESSI1 Interrupt Priority Level (S1L) 4-16
HI08 Interrupt Priority Level (HPL) 4-16
SCI Interr upt Prior ity L evel (SCL) 4-16
Timer Interrupt Priority Level (TOL) 4-16
Interrupt Priority Register-Peripherals (IPR-P)
programming sheet B-12
interrupt routines
Host Interface (HI08) 6-7
Interrupt Service Routine (IS R) 7-8, 9-4
interrupt trigge r event 7-9
Interrupt Vector Register (IVR) 6-21
programming sheet B-22
Inverter (INV) bit 9-25, 9-27
IRQD–IRQA Priority and Mode (IDL–IAL) bits 4-15
J
Joi nt Te s t Action Group (JTAG) 1-9, 2-18, 4-34
Test Acc es Port(TAP) 1-5
L
Limit (L) bit 4-10
Loop Addre s s re gis ter (LA) 1-8
Loop Counter regi ster (LC) 1-8
M
M68HC11 SCI interfa ce 8-14
manual conventions 1-2
map ping control registers 5-1
MC68000 fami ly 6-26
MC68681 DUART 8-14
memory
allocation switching 3-2
configuration 3-5
dynamic switc hing 3-5
expansion 3-1
external expansion port 1-10
maps 3-6
on-chip 1-9
Memory Expansion Port 1-5
memory map
internal I/O B-2
Memory Switch mode 3-2
X data Memory 3-3
X data memory 3-4
Memory Switch Mode (MS) bit 4-14
MODD, MODC, MODB, and MODA 8-7
mode control 2-8
Mode Register (MR) 4-7
Do Loop Flag (LF) 4-9
Double-P recision Mult iply Mode (DM) 4-9
Interrupt Mask (I) 4-10
Scaling (S) Mode 4-10
Sixt een-Bit Com patibility (SC) mode 4-9
Mode Select (MOD) bit 7-20
move (MOVE, MOVEP) instruc tions 5-1
MOVEP instruction 6-12
Multidrop mode 8-2
multiplexed bus mode 2-2, 6-3, 6-15, 6-18
Multiplication Fac tor (MF) bits 4-21
Multiplier-Accumula tor (MAC) 1-6
N
Negati ve (N) bit 4-11
Network mode 7-7
non-multiplexed bus mode 2-2, 6-3
O
off-chip memory 1-5, 3-1
On-Chip Emulation (OnCE) module 1-5, 1-9, 2-18
on-chip memory 1-5, 1-9
On-Demand mode 7-9, 7-14
operat ing frequency 1-5
operat ing m ode 4-1
Host Interfa ce (HI08) 6-16
Operating Mode Regi ster (OMR) 1-8, 4-12
Address Attribute Priority Disabl e (APD) 4-13
Address Trace Enable (ATE) 4-13
Asynchronous Bus Arbitration Enabl e (ABE ) 4-13
Bus Release Timing (BRT) 4-13
Cache Burst Mode Enable (BE) 4-14
Chip Operating Mode (MD–MA) 4-14
COM byte 4-12
Core-DMA Priority (CDP) 4-14
EOM byte 4-12
External Bus Disable (EBD) 4-14
Memory Switc h Mode (MS) 4-14
programmi ng sheet B-11
SCS byte 4-12
Stack Extension Enable (SEN) 4-12
Stack Exten si on Overflow Flag (E OV) 4-12
Stack Extension Underflow F lag (EUN) 4-13
Stack Extensi on Wr ap F lag (WRP) 4-12
Stack Extensi on XY Select (XYS) 4-13
Stop Delay Mode ( SD) 4-14
TA Synchronize Select (TAS) 4-13
Overflow (V) bit 4-11
Overrun Error Flag (OR) bit 8-16
P
Parity Error (PE) bit 8-15
Periphera l I/O Expansion Bus 1-10
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-9
Index
peripherals progr am mi ng
bit- oriente d instru ctions 5-1
data transfer methods 5-2
guidelines 5-1
individual reset state 5-1
initialization steps 5-1
interrupts 5-2
map ping control registers 5-1
move (MOVE, MOVEP) instructions 5-1
polling 5-2
read ing status regi sters 5-2
PINIT 4-20
PLL 1-8, 2-4
PLL Control (PCTL) register 4-20
Clock Output Dis able (COD) 4-20
Cr ystal Range ( X TLR) 4-21
Division Factor (DF) 4-21
PLL Enable (PEN) 4-20
PLL Mult iplication Factor (MF) 4-21
PLL Stop State (PSTP) 4-20
Predivider Factor (PD) 4-20
programming sheet B-13
XTAL Disable (XTLD) 4-20
PLL Enable (PEN) bit 4-20
PLL Stop State (PSTP) bit 4-20
polling 5-2
Port A 2-5, 4-21
Port B 2-2, 2-12
HI08 5-6
programming sheet B-31
Port C 2-2, 2-15, 2-16
control registe rs 7-33
ESSI0 5-7
Port C Control Register (PCRC) 7-33
programming sheet B-32
Port C Data Register (PDRC) 7-34
programming sheet B-32
Port C Direction Register (PRRC) 7-34
programming sheet B-32
Port D 2-2
control registe rs 7-33
ESSI1 5-7
Port D Control Register (PCRD) 7-33
programming sheet B-33
Port D Data Register (PDRD) 7-34
programming sheet B-33
Port D Di rection Register (PRRD) 7-34
programming sheet B-33
Port E 2-17, 5-7
Port E Control Regis ter (PCRE) 8-22
programming sheet B-34
Port E Data Register (PDRE) 8-23
programming sheet B-34
Port E Direction Re gis te r (PRRE) 8-22
programming sheet B-34
position independe nt code (PIC) 1-8
power 2-3
low 1-5
management 1-5
stan dby mo des 1-5
Pred ivider Facto r (PD ) b i ts 4-20
prescale divider for ESSI 7-15
Prescale Modulus Select (PM) bits 7-15
Presca ler Clock Enable (PCE) bit 9-24
prescaler counter 9-21
Presca ler Counter Value (PC) bits 9-23
Prescaler Preload Value (PL) bits 9-23
Prescaler Ran g e ( PSR) b i t 7-15
Prescaler Source (PS) bi ts 9-23
Program Addre s s Bus (PAB) 1-10
Program Addres s Genera tor (PAG) 1-7
Progra m Control Unit (P CU) 1-7
Progra m Coun ter register (PC) 1-8
Program Data Bus (PDB) 1-10
Progra m Decode Controller (PDC) 1-7
program memory 1-5, 3-1, 3-2
program memory expansion 1-9
bus 1-10
Progra m ROM, bootstrap 3-1
programmi ng mod el
core 4-1
DSP co re 6-11
ESSI 7-12
HI08 6-11
DSP side 6-11
host side 6-20
HI08 quick reference 6-28
peripherals 5-1
SCI 8-8
timer 9-21
program mi ng sheets
list B-1
R
RAM
program 3-1
reading status registers 5-2
Receive Byte Re gisters ( RX H , RX M, RX L) 6-5, 6-26
Receive Clock Mode Source (RCM) 8-17
Receive Data (RXD) signal 8-4
Rece iv e D at a F u ll (R D F ) bit 6-6
Rece iv e D at a R eg iste r (RX ) 7-28
Rece iv e D at a R eg iste r Ful l ( RD F) bit 7-27
Rece iv e D at a R eg iste r Ful l ( RD R F) bi t 8-16
Receive Data Register Full (RXDF) bit 6-26
Receive Enable (RE) bit 7-19
Receive Exception Interrupt Enable (RE I E) bit 7-18
Rece iv e Fr ame Sy nc F la g (RFS ) 7-27
Receive Interrupt Enable (RIE) bit 7-18
DSP56303 User’s Manual, Rev. 2
Index-10 Freescale Semiconductor
Index
Rece ive La st Slot Interrupt Enable (RLI E) bit 7-18
Receive Request Enable (RR EQ ) b i t 6-23
Receive Sh if t Regi ster 7-28
Receive Slot Mask Registers (RSMA and RSMB) 7-12,
7-32
Rece ive with Exception Interrupt Enabl e (RE I E) bit 8-11
Rece ived Bit 8 (R8) bit 8-15
Receiver Enabl e ( R E) bit 8-13
Receiver Overrun Error Fl ag ( R O E) 7-27
Rece iver Wake up Ena ble (RWU) bit 8-13
regis ter banks 6-4
RESET 2-8
resets
hardwa re an d software 6-3
ROM, bootst rap 1-5, 3-1, 3-2
Rounding Mode (RM) bit 4-8
RX clock 7-10
RXH, RXM, RXL re gisters 6-26
S
Scaling (S) bit 4-10
Scaling (S) Mode bits 4-10
SCI Clock Control Re gister (SCCR) 8-8, 8-17
bit definitions 8-17
Clock Divider (CD) 8-17
Clock Out Divider (COD) 8-17
Clock Prescaler (SCP) 8-17
programming sheet B-27
Rece ive Clock Mode Sour ce (RCM) 8-17
Transmit Clock Source (TCM) 8-17
SCI Clock Polarity (SCKP) bit 8-11
SCI Control Regis ter (SCR) 8-8, 8-10
bit definitions 8-11
Idle Line Interrupt Enable (ILIE) 8-12
programming sheet B-26
Receive with E x ception Int errupt Enable (REIE) 8-11
Receiver Enabl e ( R E) 8-13
Rece iver Wakeup Enable (RWU) 8-13
SCI Clock Polarity (SCKP) 8-11
SCI Receive Interrupt Enable (RIE) 8-12
SCI Shift Direction (SSFTD) 8-14
SCI Transmit Interrupt Enable (TIE) 8-12
Send Break (SBK) 8-14
Timer Interrupt Enable (TMIE) 8-11
Timer Interrupt Rate (STIR) 8-11
Transmitter Enable ( TE) 8-12
Wakeup Mode Select (WAKE) 8-13
Wired-OR Mode Select (WOMS) 8-13
Word Select (WDS) 8-14
SCI Interr upt Prior ity Leve l (SCL) bits 4-16
SCI pins
RXD, TXD, SCLK 8-3
SCI Receive Data Register (SRX) 8-8, 8-20
SCI Receive Interrupt Enable (RIE) bit 8-12
SCI Serial Clock signal (SCLK) 8-4
SCI Shift Direction (SSFTD) 8-14
SCI Status Register (SSR) 8-8, 8-15
bit definitions 8-15
Framing Error Flag (FE) 8-15
Idle Line Flag (IDLE) 8-16
Overrun Error Flag (OR) 8-16
Parity Error (PE ) 8-15
Rece iv e D at a R eg iste r Ful l ( RD R F) 8-16
Received Bit 8 (R8) 8-15
Transmit Data Register Empty (TDRE) 8-16
Transmitter Empty (TRNE) 8-16
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Register (S TX or STXA) 8-19
SCI Transmit Data Register (STX) 8-8, 8-21
SCI Transmit Interrup t Enable (TIE) bit 8-12
SCLK 8-2, 8-6
SCS byte 4-12
Select SC K (SSC1) bit 7-13
Send Break (SBK) bi t 8-14
Serial Clock (SCK) 7-3
Serial Clock (SCLK), SCI 8-2
Serial Com munications Interface (SCI) 1-13, 2-2, 2-17
Address Mode Wakeup 8-3
Asynchr onous mode 8-2
bootstrap loading 8-7
crystal frequency 8-6
data registers 8-19
Data Word Formats 8-9
enable wakeup function 8-13
enable/disable SCI receive data with excepti on
interrupt 8-11
exceptions 8-8
Idle Line 8-8
Rece iv e D at a 8-8
Rece iv e D at a w i th E x ce pt i on S ta tu s 8-8
Timer 8-8
Transmit Data 8-8
GPIO 5-7
GPIO functionality 8-22
I/O signals 8-3
Idle Li ne Wake up mode 8-3
individual reset st ate (PCR = $0) 8-6
initialization 8-6
Inter-pro cessor messages 8-2
interrupts 8-6
Multidrop mode 8-2
operat ing m ode 8-1
Asynchronous 8-1
Synchronous 8-1
programmi ng mod el 8-8
data registers 8-20
Receive Data (RXD) 8-4
recover synchronization 8-2
reset 8-4
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-11
Index
SCI Clock Control Re gister (SCCR) 8-6, 8-7, 8-8, 8-17
bit definitions 8-17
Clock Divider (CD) 8-17
Clock Out Divider (COD) 8-17
Clock Prescaler (SCP) 8-17
programming sheet B-27
Rece ive Clock Mode Sour ce (RCM) 8-17
Transmit Clock Source (TCM) 8-17
SCI Control Regis ter (SCR) 8-6, 8-7, 8-8, 8-10
bit defintions 8-11
Idle Line Interrupt Enable (ILIE) 8-12
programming sheet B-26
Receive with E xception Int er ru p t Enable
(REIE) 8-11
Receiver Enabl e ( R E) 8-13
Rece iver Wakeup Enable (RWU) 8-13
SCI Clock Polarity (SCKP) 8-11
SCI Receive Interrupt Enable (RIE) 8-12
SCI Shift Direction (SSFTD) 8-14
SCI Transmit Interrupt Enable (TIE) 8-12
Send Break (SBK) 8-14
Timer Interrupt Enable (TMIE) 8-11
Timer Interrupt Rate (STIR) 8-11
Transmitter Enable ( TE) 8-12
Wakeup Mode Select (WAKE) 8-13
Wired-OR Mode Select (WOMS) 8-13
Word Select (WDS) 8-14
SCI Receive Data Register (SRX) 8-8, 8-20
SCI Status Register (SSR) 8-8, 8-15
bit definitions 8-15
Framing Error Flag (FE) 8-15
Idle Line Flag (IDLE) 8-16
Overrun Error Flag (OR ) 8-16
Parity Error (PE) 8-15
Receive Data Regis ter Fu ll (RDRF) 8-16
Received Bit 8 (R8) 8-15
Transmit Data Register Empty (TDRE) 8-16
Transm itter Empty (TRNE) 8-16
SCI Tran smi t Data Ad dress Re g iste r (STXA) 8-9
SCI Transmit Data Register (STX) 8-8
se lect wakeup on idle line mode 8-13
Se rial Clock (SCLK) 8-4, 8-19
st at e af te r re set 8-5
Synchronous mode 8-2
transmi ssi on prio rity
preamble, break, and data 8-7
tra n s mit and re ceive s h if t re g isters 8-2
Transmit Data (TXD) 8-4
Transmit Data Register (STX or STXA) 8-19
Transmit Data Register (STX) 8-21
Wired-OR mode 8-3
Serial Control 0 (SC00 and SC10) signals 7-3
Serial Control 1 (SC01 and SC11) signals 7-4
Serial Control 2 (SC02 and SC12) signals 7-5
Serial Control Direct ion 0 (SCD0) bi t 7-22
Serial Control Direc tion 1 (SCD1) bit 7-22
Serial Control Direc tion 2 (SCD2) bit 7-21
Serial Input Flag 0 (IF0) bit 7-4, 7-28
Serial Input Flag 1 (IF1) bit 7-28
Serial Output Flag (OF0–OF1) bit s 7-17
Serial Output Flag 0 (OF0) bit 7-4, 7-22
Serial Output Flag 1 (OF1) bit 7-22
Serial Receive Data (SRD) signal 7-3
Serial Tran smit Data (STD) signal 7-2
setting timer operating mode 9-3
Shift Direc tion (SHFD) bit 7-21
signals 2-1
signals, func tional groups 2-2
singl e dat a strobe mode 2-2
Sixt een-Bit Ar ithme tic Mode (SA) bit 4-8
Sixt een-Bit Com patibility (SC) mode bit 4-9
Sixt een-bit Com p atibility mode 3-5
Size register (SZ) 1-8
softwa re polling 6-5
SRAM, interf acing 1-10
Stack Counter register (SC) 1-8
Stack Extension Enable (SEN) bit 4-12
Stack Extension Overflow F lag (E OV) bit 4-12
Stack Extension Underflow F lag (EUN) bit 4-13
Stack Ext ension Wrap Flag (WRP) bi t 4-12
Stack Extension XY Select (XYS) bit 4-13
Stack Pointer (SP) 1-8
stan dby mo de
Stop 1-5
Wait 1-5
Status Register (SR) 1-8, 4-7, 4-8
bit definitions 4-8
Condition Code Register (CCR) 4-7
C arr y (C) 4-11
Extension (E) 4-11
Limit (L) 4-10
Negati ve (N) 4-11
Overflow (V) 4-11
Scaling (S) 4-10
Unnormalized (U) 4-11
Zero (Z) 4-11
Extended Mode Register (EMR) 4-7
Arithmetic Saturation Mode (SM) 4-8
Ca ch e En a bl e ( CE ) 4-8
Core Priority (C P) 4-7, 4-8
DO FOREVER (FV) Flag 4-9
Instruction Cache Enable (CE) 4-7
Rounding Mode ( RM) 4-8
Sixteen-Bit Arith me tic Mode (SA) 4-8
Mode Register (MR) 4-7
Do Loop Flag (LF) 4-9
Double-P recision Mult iply Mode (DM) 4-9
Interrupt Mask (I) 4-10
Scaling (S) Mode 4-10
Sixt een-Bit Com patibility (SC) Mode 4-9
DSP56303 User’s Manual, Rev. 2
Index-12 Freescale Semiconductor
Index
programming sheet B-10
status registers, reading 5-2
St op Dela y Mode (SD) bit 4-14
STOP instruc tion 6-20, 8-5
Stop standby mode 1-5
Switch mode 1-5
switching memory configuration dynamically 3-5
switching memor y sizes 3-2
Synchronous mode 7-9, 7-10, 7-12, 8-2, 8-16
Synchronous Serial Inte rface Sta tus Register (SSISR) 7-12,
7-26
Receive Data Regis ter Fu ll (RDF) 7-27
Receiver Frame Sync Fl ag ( R FS) 7-27
Receiver Overrun Error Fl ag ( R O E) 7-27
Serial Input Flag 0 (IF0) 7-28
Serial Input Flag 1 (IF1) 7-28
Transmit Data Register Empty (TDE) 7-27
Transmit Fra me Sync Fla g (TFS) 7-27
Transmit te r Underrun Error Flag (TUE ) 7-27
Synchronous/Asynchronous (SYN) bit 7-20
T
TA Sy nchronize Select (T AS) bit 4-13
Test Access Port (TAP) 1-5, 1-9
Time Slot Re gister (TSR) 7-31
timer 2-2, 2-17
after Reset 9-3
enabling 9-4
exception 9-4
Compare 9-4
Overflow 9-4
GPIO 5-8
initialization 9-3
operating modes 9-5
Capture (mode 6) 9-5, 9-11, 9-15
Even t Counter (mode 3) 9-5, 9-10
GPIO (mode 0) 9-5
Input P eriod (mode 5) 9-5, 9-11, 9-13
Input Width ( mode 4) 9-5, 9-11, 9-12
overview 9-5
Pul se (mod e 1) 9-5, 9-7
Pul se Width Modulation (PWM) (mode 7) 9-5,
9-11, 9-16
reserved 9-20
setting 9-3
si gna l m e asu r ement m odes 9-11
Toggle (mode 2) 9-5, 9-8
watchdog modes 9-18
Watch dog P ulse (mode 9) 9-5, 9-18
Watchdog Toggle (mode 10) 9-5, 9-18
prescaler counter 9-21
programming model 9-21
sp ec ial ca ses 9-21
timer compare interrupts 9-27
Timer Compare Register (TCPR) 9-28
Timer Control/Status Register (TCSR) 9-24
Data Input (DI) 9-25
Data Outpu t (DO) 9-25
Direction (DIR) 9-25
Inverter (INV) 9-25, 9-27
Prescaler Cloc k En able ( PCE) 9-24
Timer Compare Flag (TCF) 9-24
Timer Compare Interrupt Enable (TCIE) 9-27
Timer Control (TC) 9-26
T im er En ab l e (TE) 9-27
Timer Overflow Flag (TOF) 9-24
Timer Overflow Interrupt Enable (TOIE) 9-27
Timer Reload Mode (TRM) 9-25
Timer Count Register (TCR) 9-29
Timer Load Registers (TLR) 9-28
Timer P rescaler Count Register (TPCR) 9-23
Prescaler Counter Value (PC) 9-23
T im er P res c al er Lo ad Re g ist er ( TP L R) 9-22
bit definitions 9-23
Prescaler Preload Val u e (PL) 9-23
Prescaler Sour ce (PS) 9-23
Timer Compare Flag (TCF) bit 9-24
Timer Compare Interrupt Enable (TCIE) bit 9-27
Timer Compare Register (TCPR) 9-4, 9-28
Timer Control (T C) bits 9-26
Timer Control/Status Register (TCSR) 9-3, 9-24
bit definitions 9-24
Data Input (DI) 9-25
Data Outpu t (DO) 9-25
Direction (DIR) 9-25
Inverter (INV) 9-25, 9-27
Prescaler Cloc k En able ( PCE) 9-24
programmi ng sheet B-29
Ti mer Compare Flag (TCF) 9-24
Timer Compare Interrupt Enable (TCIE) 9-27
Timer Control (T C) 9-26
Timer Enab l e (TE) 9-27
Timer Overfl ow Flag (TOF) 9-24
Timer Overflow Interrupt Enable (TOIE) 9-27
Timer Reload Mode (TRM) 9-25
Timer Count Register (TCR) 9-29
Timer Enable (TE) bit 9-27
Timer Interrupt Enable (TMIE) bit 8-11
Timer Interrupt Prio rity Level (TOL) bits 4-16
Timer Interrupt Rate (STIR) bit 8-11
Timer Load Registers (TLR) 9-4, 9-28
programmi ng sheet B-30
Time r module
architecture 9-1
timer block diagram 9-2
Timer Overflow Flag (TOF) bit 9-24
Timer O verflow Int errupt Enable (TOIE) bit 9-27
Timer P rescaler Count Register (TPCR) 9-23
bit definitions 9-23
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor Index-13
Index
Prescaler Counter Value (PC) 9-23
Timer Prescaler Load Register (TPLR) 9-4, 9-22
bit definitions 9-23
Prescaler Preload Va lue (PL) 9-23
Prescaler Source (PS) 9-23
programming sheet B-28
Timer Reloa d Mode (TRM) bit 9-25
Tra ns mi t 0 Enabl e (TE 0) b it 7-19
Tra ns mi t 1 Enabl e (TE 1) b it 7-19
Tra ns mi t 2 Enabl e (TE 2) b it 7-20
Transmit Byte Registers (TXH, TXM, TXL) 6-5, 6-27
Transmit Clock Source (T DM) bit 8-17
Transmit Data Empty (TDE) bit 6-6
Transmit Data Register Empty (TDE) bit 7-27
Transmit Data Register Empty (T DRE) bit 8-16
Transmit Data Register Empty (TXDE) bit 6-25
Transmit Data Registers (TX0–TX2) 7-12, 7-31
Transmit Data Registers (TXH, T XM, TXL) 6-5
Transmit Data signal (TXD) 8-4
Transmit Enable (TE) bits 7-17
Transmit Exception Interrupt Enable (TEIE) bit 7-18
Transmit Fra me Sync Fla g (TFS) 7-27
Transmit Interrupt Enable (TIE) bit 7-18
Transmit Last Slot Interrupt Enable (TLIE) bit 7-18
Tr ansmit Req uest Enable (TREQ) bit 6-23
Transmit Shift Registers 7-28
Transmit Slot Mas k Registers (TSMA and TSMB ) 7-12,
7-31
Transmitter Empty (TRNE) bit 8-16
Transmitter E nable (TE) bit 8-12
Transmitter Ready (TRDY) bit 6-25
Transmit te r Underrun Error Flag (TUE ) 7-27
tr iple timer module 1-13
TX cl o ck 7-10
TXD signal 8-4
TXH, TX M , TXL r egi ste rs 6-27
U
Unnormali ze d (U) bit 4-11
V
Vector Base Address register (VBA) 1-8
W
Wait standby mode 1-5
Wakeup Mode Select (WAKE) bit 8-13
Wired-OR Mode Select (WOMS) bit 8-13
Word Lengt h Control (WL) bits 7-14
Word Select (WDS) bits 8-14
X
X data memory 1-5, 3-3
X I/O space 3-3, 3-4
X Memory Address Bus (XAB) 1-10
X Memory Data Bus (XDB) 1-10
X Memory Expansion Bus 1-10
XTAL Disable (XTLD) bit 4-20
Y
Y data memory 1-5, 3-4
Y Memory Address Bus (YAB) 1-10
Y Memory Data Bus (YDB) 1-10
Y Memory Expansion Bus 1-10
Z
Zero (Z) bit 4-11
DSP56303 User’s Manual, Rev. 2
Index-14 Freescale Semiconductor
Index
