SQ3426AEEV
www.vishay.com Vishay Siliconix
S15-1583-Rev. B, 02-Jul-15 1Document Number: 62982
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Automotive N-Channel 60 V (D-S) 175 °C MOSFET
Marking Code: 8Nxxx
FEATURES
• TrenchFET® power MOSFET
• Typical ESD protection 800 V HBM
• AEC-Q101 qualified
• 100 % Rg and UIS tested
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. When mounted on 1" square PCB (FR4 material).
PRODUCT SUMMARY
VDS (V) 60
RDS(on) (Ω) at VGS = 10 V 0.042
RDS(on) (Ω) at VGS = 4.5 V 0.063
ID (A) 7
Configuration Single
N-Channel MOSFET
(4) S
(1, 2, 5, 6) D
(3) G
Top View
TSOP-6 Single
1
D
2
D
3
G
D
6
D
5
S
4
ORDERING INFORMATION
Package TSOP-6
Lead (Pb)-free and Halogen-free SQ3426AEEV-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 60 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current TC = 25 °C ID
7
A
TC = 125 °C 4
Continuous Source Current (Diode Conduction) IS6
Pulsed Drain Current aIDM 29
Single Pulse Avalanche Current L = 0.1 mH IAS 10
Single Pulse Avalanche Energy EAS 5mJ
Maximum Power Dissipation aTC = 25 °C PD
5W
TC = 125 °C 1.6
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to +175 °C
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL LIMIT UNIT
Junction-to-Ambient PCB Mount b RthJA 110 °C/W
Junction-to-Foot (Drain) RthJF 30
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 2Document Number: 62982
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 60 - - V
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.5 2 2.5
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 12 V - - ± 500 nA
VDS = 0 V, VGS = ± 20 V - - ± 1 mA
Zero Gate Voltage Drain Current IDSS
VGS = 0 V VDS = 60 V - - 1
μA VGS = 0 V VDS = 60 V, TJ = 125 °C - - 50
VGS = 0 V VDS = 60 V, TJ = 175 °C - - 150
On-State Drain Current a I
D(on) V
GS = 10 V VDS ≥ 5 V 10 - - A
Drain-Source On-State Resistance a R
DS(on)
VGS = 10 V ID = 5 A - 0.032 0.042
Ω
VGS = 10 V ID = 5 A, TJ = 125 °C - 0.056 -
VGS = 10 V ID = 5 A, TJ = 175 °C - 0.071 -
VGS = 4.5 V ID = 4 A - 0.035 0.063
Forward Transconductance a gfs VDS = 15 V, ID = 4 A - 21 - S
Dynamic b
Input Capacitance Ciss
VGS = 0 V VDS = 30 V, f = 1 MHz
- 800 1100
pF Output Capacitance Coss -75100
Reverse Transfer Capacitance Crss -3555
Total Gate Charge c Qg
VGS = 10 V VDS = 30 V, ID = 6 A
-11.514
nC Gate-Source Charge c Qgs -1.9-
Gate-Drain Charge c Qgd -3.5-
Gate Resistance Rg f = 1 MHz 1.9 3.8 5.7 Ω
Turn-On Delay Time c td(on)
VDD = 30 V, RL = 7.5 Ω
ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω
-710
ns
Rise Time c tr -1014
Turn-Off Delay Time c td(off) -2025
Fall Time c tf -46
Source-Drain Diode Ratings and Characteristics b
Pulsed Current a ISM --29A
Forward Voltage VSD IF = 1.6 A, VGS = 0 - 0.75 1.2 V
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 3Document Number: 62982
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
Gate Current vs. Gate-Source Voltage
Output Characteristics
Transconductance
Capacitance
Transfer Characteristics
On-Resistance vs. Drain Current
100
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
0 6 12 18 24 30
IGSS -Gate Current (A)
VGS -Gate Source Voltage (V)
TJ= 25 °C
TJ= 150 °C
0
3
6
9
12
15
012345
I
D
- Drain Current (A)
V
DS
-Drain-to-Source Voltage (V)
V
GS
= 10 V thru 4 V
V
GS
= 3 V
V
GS
= 2 V
0
10
20
30
40
50
012345
gfs - Transconductance (S)
ID - Drain Current (A)
TC = 125 °C
TC = -55 °C
TC = 25 °C
0
200
400
600
800
1000
1200
0 102030405060
C - Capacitance (pF)
VDS-Drain-to-Source Voltage (V)
Ciss
Coss
Crss
0
3
6
9
12
15
012345
ID - Drain Current (A)
VGS - Gate-to-Source Voltage (V)
TC = -55 °C
TC = 125 °C
TC = 25 °C
0.00
0.02
0.04
0.06
0.08
0.10
03691215
RDS(on) - On-Resistance (Ω)
ID - Drain Current (A)
VGS = 4.5 V
VGS = 10 V
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 4Document Number: 62982
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
Gate Charge
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
On-Resistance vs. Gate-Source Voltage
Threshold Voltage
Drain-Source Breakdown vs. Junction Temperature
0
2
4
6
8
10
036912
VGS -Gate-to-Source Voltage (V)
Qg-Total Gate Charge (nC)
ID= 6 A
0.001
0.01
0.1
1
10
100
0.0 0.2 0.4 0.6 0.8 1.0 1.2
IS - Source Current (A)
VSD - Source-to-Drain Voltage (V)
TJ = 25 °C
TJ = 150 °C
0.5
0.9
1.3
1.7
2.1
2.5
- 50 - 25 0 25 50 75 100 125 150 175
RDS(on) - On-Resistance (Normalized)
TJ - Junction Temperature (°C)
ID = 3.2 A
VGS = 4.5 V
VGS = 10 V
- 1.0
- 0.7
- 0.4
- 0.1
0.2
0.5
- 50 - 25 0 25 50 75 100 125 150 175
VGS(th) - Variance (V)
TJ - Temperature (°C)
ID = 250 μA
ID = 5 mA
60
64
68
72
76
80
- 50 - 25 0 25 50 75 100 125 150 175
VDS - Drain-to-Source Voltage (V)
TJ - Junction Temperature (°C)
ID = 1 mA
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 5Document Number: 62982
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
Safe Operating Area
Normalized Thermal Transient Impedance, Junction-to-Ambient
0.01
0.01 0.1 1 10010
0.1
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specied
ID - Drain Current (A)
Limited by RDS(on)*
BVDSS Limited
1 ms
10 ms
1 s,
10 s, DC
100 ms
100 μs
IDM Limited
TC = 25 °C
Single Pulse
10-3 10-2 110 100010-1
10-4 100
0.2
0.1
0.05
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
Single Pulse
t
1
t
2
Notes:
P
DM
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 110 °C/W
3. T
JM
-T
A
=P
DM
Z
thJA(t)
t
1
t
2
4. Surface Mounted
Duty Cycle = 0.5
0.02
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 6Document Number: 62982
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
Normalized thermal Transient Impedance, Junction-to-Foot
Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62982.
1
0.1
0.01
0.2
Duty Cycle = 0.5
Square WavePulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Single Pulse
0.1
10-3 10-2 110-1
10-4
0.02
0.05
SQ3426AEEV
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S15-1583-Rev. B, 02-Jul-15 7Document Number: 62982
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Note
a. As of April 2014
REVISION HISTORY a
REVISION DATE DESCRIPTION OF CHANGE
B 23-Jun-15 • Updated dynamic characteristics, added gate leakage graph, removed 2nd transfer characteristic graph
Vishay Siliconix
Package Information
Document Number: 71200
18-Dec-06
www.vishay.com
1
1 2 3
Gauge Plane
L
5 4
R
R
C 0.15 M B A
b
C 0.08
0.17 Ref
Seating Plane
-C-
Seating Plane
A
1
A
2 A
-A-
D
-B-
E
1 E
L
2
(L
1
)
c
4x 1
4x 1
e
e1
1 2 3
6 5 4
C 0.15 M B A
b
-B-
E
1 E
e
e1
5-LEAD TSOP 6-LEAD TSOP
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A
1 0.01 - 0.10 0.0004 - 0.004
A
2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E
1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e
1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L
1 0.60 Ref 0.024 Ref
L
2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8
1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
AN823
Vishay Siliconix
Document Number: 71743
27-Feb-04
www.vishay.com
1
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
FIGURE 1. Recommended Copper Spreading Footprint
0.049
1.25
0.010
0.25
0.014
0.35
0.074
1.875 0.122
3.1
0.026
0.65
0.167
4.25
0.049
1.25
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate +6_C/Second Maximum
Temperature @ 155 " 15_C120 Seconds Maximum
Temperature Above 180_C70 − 180 Seconds
Maximum Temperature 240 +5/−0_C
Time at Maximum Temperature 20 − 40 Seconds
Ramp-Down Rate +6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
AN823
Vishay Siliconix
www.vishay.com
2Document Number: 71743
27-Feb-04
255 − 260_C
1X4_C/s (max) 3-6_C/s (max)
10 s (max)
Reflow Zone
Pre-Heating Zone
3_C/s (max)
140 − 170_C
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
60-120 s (min)
217_C
60 s (max)
THERMAL PERFORMANCE
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf 30_C/W
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
0.6
0.8
1.0
1.2
1.4
1.6
−50 −25 0 25 50 75 100 125 150
VGS = 4.5 V
ID = 6.1 A
On-Resistance vs. Junction Temperature
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
rDS(on) − On-Resiistance
(Normalized)
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.119
(3.023)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.099
(2.510)
0.064
(1.626)
0.028
(0.699)
0.039
(1.001)
0.020
(0.508)
0.019
(0.493)
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Revision: 08-Feb-17 1Document Number: 91000
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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