LTC3649
1
3649fb
For more information www.linear.com/LTC3649
TYPICAL APPLICATION
FEATURES DESCRIPTION
60V, 4A Synchronous
Step-Down Regulator with
Rail-to-Rail Programmable Output
The LT C
®
3649 is a high efficiency 60V, 4A synchronous
monolithic step-down regulator. The regulator features
a single resistor programmable output voltage, internal
compensation and high efficiencies over a wide VOUT range.
The step-down regulator operates from an input voltage
range of 3.1V to 60V and provides an adjustable rail-to-rail
output range from (VIN – 0.5V) to ground while delivering
up to 4A of output current. The switching frequency is
also adjusted with an external resistor. A user-selectable
mode input is provided to allow the user to trade off ripple
noise for efficiency at light loads; Burst Mode operation
provides the highest efficiency at light loads, while forced
continuous mode provides low output ripple. The MODE/
SYNC pin can also be used to allow the user to synchronize
the switching frequency to an external clock.
The LTC3649 operates with a peak current mode architec-
ture that allows for fast transient response with inherent
cycle-to-cycle current limit protection. It also features
programmable output current limit, current monitoring
and input voltage regulation.
Efficiency with VOUT = 5V
APPLICATIONS
n Wide VIN Range: 3.1V to 60V
n Wide VOUT Range: 0V to (VIN – 0.5V)
n Single Resistor VOUT Programming
n Integrated 110mΩ Top N-Channel/50mΩ Bottom
N-Channel MOSFETs
n 95% Efficiency with 12VIN and 5VOUT
n Regulated IQ: 440µA, Shutdown IQ: 18µA
n Accurate Current Monitoring (±4%) without Sense
Resistor
n Accurate Resistor Programmable Frequency
(300kHz to 3MHz) with ±50% Frequency Sync Range
n Accurate Programmable Output Current
n Input Voltage Regulation for MPPT Applications
n ±0.8% Output Voltage Accuracy
n Peak Current Mode Operation
n Programmable Wire Drop Compensation
n Burst Mode
®
Operation, Forced Continuous Mode
n Internal Compensation and Programmable Soft-Start
n Overtemperature Protection
n Available in Thermally Enhanced 28-Lead (4mm ×
5mm) QFN and TSSOP Packages
n Industrial Applications
n Automotive Applications
L, LT , LT C , LT M , Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are
registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258.
VIN
5.5V TO 60V
22µF
RUN
VIN SW
VOUT
EXTVCC
MODE/SYNC
SGND
PGND
ITH
VINREG
INTVCC
2.2µF
10nF
100k
ISET
10nF
3649 TA01a
47µF
×2
VOUT
5V
4A
10k
IMON
200k
fSW = 500kHz
RT
LTC3649
BOOST
6.8µH
0.1µF
24V to 5VOUT Burst Mode Operation
VIN = 12V
VIN = 24V
IOUT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
80
82
84
86
88
90
92
94
96
98
100
EFFICIENCY (%)
3649 TA01b
LTC3649
2
3649fb
For more information www.linear.com/LTC3649
http://www.linear.com/product/LTC3649#orderinfo
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN Voltage (Note 3) .................................. 64V to –0.3V
ISET, OUT Voltage ..................................... 64V to –0.3V
RUN Voltage............................................... 64V to –0.3V
MODE/SYNC Voltage .................................. 6V to –0.3V
PGDFB, RT ...........................................INTVCC +0.3V to –0.3V
EXTVCC Voltage ......................................... 28V to –0.3V
(Notes 1, 2)
9 10
TOP VIEW
29
SGND
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
PGND
PGND
VIN
VIN
RUN
SGND
MODE/SYNC
PGOOD
SW
SW
SW
SW
BOOST
INTVCC
EXTVCC
ITH
PGND
PGND
PGND
SW
SW
SW
PGDFB
IMON
VINREG
RT
VOUT
ISET
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGND
PGND
PGND
PGND
PGND
VIN
VIN
RUN
SGND
MODE/SYNC
PGOOD
PGDFB
IMON
VINREG
SW
SW
SW
SW
SW
SW
SW
BOOST
INTVCC
EXTVCC
ITH
ISET
VOUT
RT
29
SGND
TJMAX = 125°C, θJA = 30°C/W, θJC = 5°C to 10°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3649EUFD#PBF LTC3649EUFD#TRPBF 3649 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3649IUFD#PBF LTC3649IUFD#TRPBF 3649 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3649EFE#PBF LTC3649EFE#TRPBF LTC3649 28-Lead Plastic TSSOP –40°C to 125°C
LTC3649IFE#PBF LTC3649IFE#TRPBF LTC3649 28-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
IMON, PGOOD Voltage ................................. 4V to –0.3V
VINREG, ITH Voltage ..................................... 4V to –0.3V
Operating Junction
Temperature Range (Notes 5, 7) ............ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
LTC3649
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For more information www.linear.com/LTC3649
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C. (Note 5) VIN = 24V, VEXTVCC = 0V unless otherwise noted. (Notes 5, 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range 3.1 60 V
VOUT Output Operating Voltage Range (Note 4) 0.05 VIN V
IVIN Input Quiescent Current Shutdown Mode; VRUN = 0V
Burst Mode Operation
FC Mode (Note 6)
18
440
1.4
30
600
2.5
µA
µA
mA
IISET Reference Current VISET = 3.3V
l
49.6
49.4
50
50
50.4
50.6
µA
µA
ΔVOUT(LOAD+LINE)Output Voltage Load + Line Regulation l0.1 0.5 %
VEA(OFFSET) Error Amp Input Offset VISET = 3.3V –5 5 mV
gm (EA) Error Amplifier Transconductance VITH = 0.7V, VOUT = 3.3V 400 550 700 µS
ILSW Topside NMOS Switch Leakage 0.1 1 µA
RSW-GND SW Resistance to GND 0.5 1 1.5 MΩ
RDS(ON) Topside NMOS On-Resistance
Bottom Side NMOS On-Resistance
110
50
mΩ
mΩ
DMAX Maximum Duty Cycle VISET = VIN (Note 4) 95 %
tON(MIN) Minimum On-Time 60 ns
VRUN RUN Input Rising
RUN Hysteresis
l1.08 1.2
120
1.32 V
mV
IRUN RUN Input Current VRUN = 12V 0 10 nA
VMODE/SYNC Burst Mode Operation
FC Mode
1.2
0.4 V
V
IMODE/SYNC MODE/SYNC Input Current VMODE/SYNC = 0V –8 –5 µA
ILIM Peak Current Limit
l
5.7
5.4
6
6
6.3
6.6
A
A
VUVLO VINTVCC Undervoltage Lockout VIN Rising l2.4 2.65 2.9 V
VUVLO(HYS) VINTVCC Undervoltage Lockout Hysteresis 200 mV
VOVLO VIN Overvoltage Lockout Rising 64 68 V
VOVLO(HYS) VIN Overvoltage Lockout Hysteresis 2 4 V
fOSC Oscillator Frequency RT = 100kΩ l0.92 1.00 1.08 MHz
fSYNC SYNC Capture Range % of Programmed Frequency 50 150 %
VINTVCC VINTVCC LDO Output Voltage
VIN > 5.0V, VEXTVCC > 3.2V
3.25
2.85
3.45
3.0
3.65
3.15
V
V
VEXTVCC EXTVCC Switchover Voltage
l
3.1
3.25
3.15 3.2 V
V
RVOUT VOUT Resistance to GND VOUT = 5V 80 100 120 kΩ
IPGDFB PGDFB Leakage Current VPGDFB = 0.6V 0 100 nA
OVPGDFB Output Overvoltage PGOOD Upper Threshold PGFB Rising 0.63 0.645 0.66 V
UVPGDFB Output Undervoltage PGOOD Lower Threshold PGFB Falling 0.54 0.555 0.57 V
ΔVPGDFB PGOOD Hysteresis PGFB Returning 10 mV
RPGOOD PGOOD Pull-Down Resistance 550 Ω
IPGOOD(LEAK) PGOOD Leakage Current VPGOOD = 3.3V 100 nA
tPGOOD PGOOD Delay PGOOD Low to High
PGOOD High to Low
16
64
Switch Cycles
Switch Cycles
AIMON IOUT/IIMON Ratio of Output Current to IIMON
Current
l
38.5
36
40
40
41.5
44
k
k
IIMON IMON Pin Current IOUT = 4A
l
96
90
100
100
104
110
µA
µA
VIMON Regulated IMON Voltage Under Output Current Regulation l1.94 2.0 2.06 V
VVINREG Input Voltage Regulation Voltage l1.85 2.0 2.15 V
IVINREG VINREG Leakage Current VVINREG = 3.3V 0 0.1 µA
LTC3649
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For more information www.linear.com/LTC3649
ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
ISET Voltage Line Regulation Quiescent Current vs Temperature Shutdown Current vs VIN
Load Regulation ISET Current vs Temperature ISET Current vs VISET
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are referred to VSGND/VPGND.
Note 3: Transient absolute maximum voltages should not be applied for
more than 4% of the switching duty cycle.
Note 4: VOUT can be programmed to VIN if the ISET pin is driven to that
voltage. If a resistor is used to program VISET, the current into the ISET pin
will decrease as VISET approaches VIN. Refer to the ISET current vs VISET
graph as an example and reference. Furthermore, during high IOUT and
high duty cycle operation, VOUT may be limited by the voltage drop across
the top switch. Refer to the High Duty Cycle/Dropout Operation section for
more details.
Note 5: The LTC3649 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3649E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3649I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 6: The quiescent current in FC mode does not include switching loss
of the power FETs.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
IOUT (A)
0
NORMALIZED VOUT (%)
99
4
3649 G01
98 21 3
102
101
100
FC MODE
BM
VIN = 24V
VOUT = 5V
TEMPERATURE (°C)
–55
ISET (µA)
49.7
125
3649 G02
49.5 –15–35 5 4525 65 10585
50.5
49.9
50.1
50.3
VISET
0
ISET (µA)
47
24
3649 G03
46
4 8 1612 20
51
48
49
50
VIN = 24V
VIN (V)
0
VISET (V)
4.96
60
3649 G04
4.95
10 20 4030 50
5.01
4.97
4.99
5.00
RISET = 100kΩ
TEMPERATURE (°C)
–55
IQ (µA)
100
125
3649 G05
0–15–35 5 4525 65 10585
500
200
300
400
SHUTDOWN
SLEEP
VIN (V)
0
IQ (µA)
4
60
3649 G06
0
10 20 4030 50
20
8
12
16
TA = 25°C, unless otherwise noted.
LTC3649
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3649fb
For more information www.linear.com/LTC3649
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency/Period
vs RT
Switching Frequency
vs Temperature Output Regulation with VIN Slew
Burst Mode Operation
Continuous Conduction Mode
Operation
Run Rising Threshold
vs Temperature
RDS(ON) vs Temperature Transient Response, CCM Transient Response, Burst Mode
TEMPERATURE (°C)
–55
RDSON (mΩ)
40
125
3649 G07
0
–35 –15 65 105855 4525
200
80
120
160
MTOP
MBOT
VOUT
100mV/DIV
AC-COUPLED
IL
2A/DIV
3649 G08
VIN = 24V, VOUT = 5V
IOUT = 0A TO 4A, L = 2.2µH, fSW = 1MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
FC MODE, COUT = 2× 47µF
20µs/DIV
VOUT
100mV/DIV
AC-COUPLED
IL
2A/DIV
3649 G09
VIN = 24V, VOUT = 5V
IOUT = 0.2A TO 4A, L = 2.2µH, fSW = 1MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
BURST MODE, COUT = 2× 47µF
20µs/DIV
RT RESISTOR (kΩ)
0
FREQUENCY (MHz)
PERIOD (ns)
0.5
350
3649 G10
0
150 20050 100 300250
3.0
1.0
1.5
2.0
2.5
1000
500
0
3500
1500
2000
2500
3000
FREQUENCY
PERIOD
TEMPERATURE (°C)
–55
FREQUENCY (kHz)
990
125
3649 G11
985
–15–35 5 4525 65 10585
1010
995
1000
1005
VOUT
2V/DIV
VIN
50V/DIV
IL
1A/DIV
3649 G12
VIN = 12V TO 60V, VOUT = 5V
IOUT = 0A, L = 2.2µH, fSW = 2.25MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
FC MODE, COUT = 2× 47µF
10ms/DIV
SW
10V/DIV
IL
1A/DIV
3649 G13
VIN = 24V, VOUT = 5V
IOUT = 100mA, L = 2.2µH, fSW = 1MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
BURST MODE, COUT = 2× 47µF
2µs/DIV
SW
10V/DIV
IL
1A/DIV
3649 G14
VIN = 24V, VOUT = 5V
IOUT = 0A, L = 2.2µH, fSW = 1MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
FC MODE, COUT = 2× 47µF
500ns/DIV
TEMPERATURE (°C)
–55
RUN RISING THRESHOLD (V)
1.185
125
3649 G15
1.180
–15–35 5 4525 65 10585
1.210
1.190
1.195
1.200
1.205
TA = 25°C, unless otherwise noted.
LTC3649
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For more information www.linear.com/LTC3649
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current at
5VOUT
Efficiency vs Load Current at
3.3VOUT
Output Capacitor Charging with
Fixed Average Current Limit
Load Step with Cable Drop
Compensation
Start-up Waveform VIMON vs Load (Temperature) VIMON Error vs Frequency
VOUT
2V/DIV
VRUN
2V/DIV
VPGOOD
2V/DIV
IL
2A/DIV
3649 G16
VIN = 24V, RISET = 100kΩ
RLOAD = 120Ω, L = 2.2µH, fSW = 1MHz
RITH = 4kΩ, CITH = 2.2nF, CITHP = 47pF
BURST MODE, COUT = 2× 47µF
1ms/DIV
IOUT (A)
0
VIMON (V)
0.2
4
3649 G17
0
0.5 1 1.5 2.52 3.53
1.2
1.0
0.4
0.6
0.8
VIN = 24V
VOUT = 5V
fSW = 1MHz
RIMON = 10kΩ
–45°C
25°C
130°C
FREQUENCY (kHz)
300
% ERROR NORMALIZED TO 1MHz
–1.5
2800
3649 G18
–2.0
1300800 23001800
0.5
–1.0
–0.5
0
VIN = 24V
VOUT = 5V
IOUT = 4A
LOAD (A)
0
EFFICIENCY (%)
55
4
3649 G19
50
0.5 1 1.5 2.52 3.53
100
95
80
85
90
75
60
65
70 fSW = 500kHz
L = 6.8µH
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 60V
LOAD (A)
0
EFFICIENCY (%)
55
4
3649 G20
50
0.5 1 1.5 2.52 3.53
100
95
80
85
90
75
60
65
70 fSW = 500kHz
L = 4.7µH
VIN = 12V
VIN = 24V
VIN = 48V
VIN = 60V
VOUT
2V/DIV
VRUN
2V/DIV
IL
2A/DIV
3649 G21
VIN = 24V, RISET = 100kΩ
RLOAD = 10Ω, L = 2.2µH RITH = 4kΩ,
CITH = 2.2nF, CITHP = 47pF, RIMON = 40kΩ,
CIMON = 0.47nF, COUT = 2× 47µF + 36mF
20ms/DIV
VOUT
500mV/DIV
VIMON
1V/DIV
IL
2A/DIV
3649 G22
CABLE DROP RESISTANCE OF 200mΩ
50ms/DIV
TA = 25°C, unless otherwise noted.
LTC3649
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For more information www.linear.com/LTC3649
PIN FUNCTIONS
(QFN/TSSOP)
PGND (Pins 1, 2, 26-28/Pins 1-5): Ground Pins for Power
Switch.
VIN (Pin 3, 4/
Pins
6, 7): Input Supply Pin of the Step-
Down Regulator.
RUN (Pin 5/Pin 8): Logic Controlled RUN Input. Do not
leave this pin floating. Place a resistor divider from VIN to
GND for an accurate VIN undervoltage threshold.
SGND (Pins 6, 29/Pins 9, 29): Signal Ground Pin of the
Step-Down Regulator. The exposed pad must be soldered
to PCB ground for electrical connection and rated thermal
performance.
MODE/SYNC (Pin 7/Pin 10): Mode Select and Oscillator
Synchronization Input of the Step-Down Regulator. Leave
MODE/SYNC floating for forced continuous mode opera-
tion or tie MODE/SYNC to GND for Burst Mode operation.
Furthermore, connecting MODE/SYNC to an external clock
will synchronize the internal oscillator to the external clock
signal and put the part in forced continuous mode.
PGOOD (Pin 8/Pin 11): VOUT Within Regulation Indicator.
PGOOD is pulled to GND when VPGFB is more than 0.645V
or less than 0.555V.
PGDFB (Pin 9/Pin 12): Power Good Feedback. Place a resis-
tor divider from VOUT to GND to detect power good level.
IMON (Pin 10/Pin 13): Output Current Monitoring Pin.
The current coming out of this pin is equal to 1/40,000
of the average output current.
VINREG (Pin 11/Pin 14): Input Voltage Regulation Sense
Input. Place a resistor divider from VIN to GND to program
the level of input voltage regulation.
RT (Pin 12/Pin 15): Oscillator Frequency Programming
Pin. Connect an external resistor between 333.3k to 33.3k
from RT to GND to program the frequency from 300kHz
to 3MHz respectively. Since the synchronization range is
limited to ±50% of the set frequency, be sure that either
the external clock is within this range or RT is set to ac-
commodate the external clock for proper frequency lock.
VOUT (Pin 13/Pin 16): Output Voltage Error Amplifier Input
Pin. Connect to the output of the LTC3649 voltage regulator.
ISET (Pin 14/Pin 17): Accurate 50µA Bias Current and
Positive Input to the Error Amplifier. Connect an external
resistor from this pin to SGND to program the output
voltage. Connecting an external capacitor from ISET to
ground will soft start the output voltage by reducing cur-
rent inrush during start-up.
ITH (Pin 15/Pin 18): Error Amplifier Output and Switching
Regulator Compensation Point. The current comparator’s
trip threshold is linearly proportional to this voltage. Tying
this pin to INTVCC activates internal compensation.
EXTVCC (Pin 16/ Pin 19): External Power Input to the
Internal Regulator. The internal regulator will draw cur-
rent from EXTVCC instead of VIN when EXTVCC is tied to a
voltage higher than 3.2V and VIN is above 5V. For output
voltages at or above 3.3V and less than 28V, this pin can
be tied to VOUT. If this pin is tied to a supply other than
VOUT, locally bypass with at least a 1µF to GND.
INTVCC (Pin 17/Pin 20): Low Dropout Regulator. Locally
bypass with at least 2.2µF to GND.
BOOST (Pin 18/Pin 21): Boosted Floating Driver Supply
for Internal Top Power MOSFET. Place a 0.1µF bootstrap
capacitor between BOOST and SW.
SW (Pins 19-25/Pins 22-28): Switch Node Connection to
the Inductor of the Step-Down Regulator.
LTC3649
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For more information www.linear.com/LTC3649
FUNCTIONAL DIAGRAM
MODE/SYNC
RT
VIN
+
–
+
–
PEAK
CURRENT
COMPARATOR
REVERSE
COMPARATOR
–
+
0A
BOOST
–
+
+1/40k IMON
INTVCC EXTVCC
SW
PGND
INTVCC PGDFB
PGOOD
3649 FD
SGND
1/50k
LDO
PGOOD
LOGIC
OSC
CLK
–
+2V2V
50µA
ISET
VOUT
VIN
VINREG
ITH
RUN
BUCK LOGIC
AND
GATE DRIVE
The LTC3649 is a current mode monolithic step-down
regulator. The accurate 50µA bias current on the ISET pin
allows the user to program the output voltage in a unity-
gain buffer fashion with just one external resistor from the
ISET pin to GND (RSET). The output voltage is set such that:
VOUT = 50µA • RSET
The LTC3649 operates through a wide VIN range, and its
frequency can be programmed to a wide range with the RT
resistor. To suit a variety of applications, the MODE/SYNC
pin allows the user to trade off output ripple for efficiency.
OPERATION
Main Control Loop
In normal operation, the internal top power MOSFET is
turned on at the beginning of a clock pulse. The inductor
current is allowed to ramp up to a peak level. Once that
level is reached, the top power switch is turned off and
the bottom switch is turned on until the next clock cycle.
The peak inductor current is determined by sensing the
voltage drop across the SW and VIN nodes of the top power
MOSFET. The voltage on the ITH pin sets the comparator
threshold corresponding to inductor peak current. The error
amplifier, EA, adjusts this ITH voltage by comparing the
VOUT voltage with the voltage on ISET. If the load current
increases, it causes a drop in VOUT relative to VISET. This
causes the ITH voltage to rise until the average inductor
current matches that of the load current.
LTC3649
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For more information www.linear.com/LTC3649
OPERATION
Low Current Operation
Burst Mode operation can be selected by connecting the
MODE/SYNC pin to GND. In this mode, the LTC3649 will
automatically transition from continuous mode operation
to Burst Mode operation when the load current is low. A
reverse current comparator looks at the voltage across SW
to GND and turns off the bottom power MOSFET when
that voltage difference approaches zero. This prevents the
inductor current from going negative. An internal burst
clamp is set to be approximately 1A, which means that in
Burst Mode operation, the peak inductor current will never
go below 1A regardless of what the ITH voltage demands
the peak current to be. As a result, when the load is low
enough, VOUT will rise relative to VISET because the average
programmed inductor current is above the load current,
thus driving VITH low. Once the ITH voltage is driven below
an internal threshold (~400mV), the switching regulator
will enter its sleep mode and wait for VOUT to drop and
VITH to rise above the threshold before it starts to switch
again. During sleep mode, the quiescent current of the
part is reduced to less than 400µA to conserve input
power. The LTC3649 is designed to operate with single
burst pulse behavior to minimize output voltage ripple
while keeping the efficiency high at light loads. Lastly, if
at any point the top power MOSFET is on for roughly 8
consecutive clock cycles, the part will turn on the bottom
power MOSFET for a brief duration such that the BOOST
capacitor can be replenished.
Forced Continuous Mode Operation
Floating the MODE/SYNC pin defaults the LTC3649 into
forced continuous mode operation. In this mode, the
part switches continuously regardless of load current,
and the inductor peak current is allowed to decrease to
approximately –1A to allow for negative average current.
High Duty Cycle/Dropout Operation
As the input voltage decreases towards the desired output
voltage, the duty cycle will increase towards 100%. How-
ever, given the architecture, there are two restrictions that
prevent the LTC3649 from operating in full dropout mode.
The first restriction is due to how the ISET voltage is pro-
grammed. If a resistor is placed between ISET and GND to
set the output voltage, the 50µA of current out of the ISET
pin is only guaranteed to be accurate when VISET is more
than 500mV below VIN. As the input voltage drops below
that 500mV threshold, the ISET current will decrease, thus
limiting the programmed voltage. Typically, VISET will never
get within 300mV of VIN. Since VISET programs VOUT, this
limitation essentially enforces a maximum duty cycle for
the switcher. This limitation can be overcome if an accu-
rate external supply is used to drive the ISET pin directly.
The second limitation against full dropout operation
is the requirement for the BOOST to SW capacitor to
refresh. When the top power MOSFET is on for multiple
clock cycles during dropout operation, the BOOST to SW
capacitor slowly gets depleted by the internal circuitry of
the chip. When the bottom switch does not turn on for at
least 80ns for 8 periods, it is forced to turn on in order to
guarantee sufficient voltage on the bootstrap capacitor.
During a refresh, the bottom switch will only turn on for
roughly 30% of the period to limit inductor ripple, thus
limiting output voltage ripple.
Output Current Monitoring and Regulation
The LTC3649 has the ability to accurately sense the aver-
age inductor current without the use of an external sense
resistor. The IMON pin output current is 1/40000th scale
of the inductor current. Placing a resistor from IMON to
GND allows the voltage on that node to be equal to:
VIMON =RIMON • IL
40000
Since the IMON current mirrors the inductor current, it
is necessary to place a capacitor from IMON to GND to
filter the voltage on the node. The choice of this capacitor
is discussed below.
In addition to simply sensing the inductor current, the
LTC3649 can also be programmed to regulate the aver-
age output current limit. The regulator will limit the peak
inductor current if it senses that the voltage on IMON
has exceeded 2V. As a result, the programmed average
inductor current depends on the size of RIMON such that:
ILAVG =2V • 40000
R
IMON
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OPERATION
If current monitoring is needed but current limiting is not,
simply pick an RIMON resistor small enough such that VIMON
will never approach 2V. A 10k resistor along with a 10nF
capacitor is typically a good RC pair to use in this case.
If current limiting is useful for the application, it is im-
portant to carefully pick the value of the capacitor from
IMON to GND, CIMON. If CIMON is picked to be too large,
then the switching regulator will be slow to react to a
large output transients, and the average inductor current
will rise above the programmed level until the loop can
react. If CIMON is picked to be too small, then the loop can
become unstable. Typically, an RC time constant that is
at least 10 times slower than the switching frequency is
a good place to start.
CIMON • RIMON ≥
10
2π• fSW
=
1.59
fSW
Cable Drop Compensation
In certain applications, the point of load will be separated
from the switching regulator with a significant amount
of wire resistance. Thus, the voltage at the point of load,
VPOL, will be reduced from VOUT near the regulator by
the resistance of the trace/wire multiplied by the current.
In those applications, it is useful to adjust for the VOUT
regulation point depending on the average output current
to maintain an accurate VPOL.
The IMON feature of the LTC3649 along with its single
resistor output voltage programmability allows this fea-
ture to be implemented with the following configuration
shown in Figure 1.
SW
VOUT
VPOL(DESIRED)
= VOUT – IOUT • RCABLE
RSET1
CSET1
CSET2
COUT
LOAD
3649 F01
RSET2
RCABLE
ISET IMON
LTC3649
Figure 1. Cable Drop Compensation Application
The general idea behind this setup is that once the induc-
tor current rises, the current out of the IMON pin will rise
proportionally. As a result, the ISET voltage will increase,
thus increasing the regulated output voltage. This rise of
VOUT offsets the voltage drop across the cable, RCABLE,
thus keeping VPOL constant.
RSET2 should be sized to account for the amount of cable
resistance:
RSET2 = 40000 • RCABLE
Furthermore, in order to regulate VPOL at the desired
voltage:
(RSET1 + RSET2) • 50µA = VPOL(DESIRED)
CSET1 is still required if soft-start is desired for the ap-
plication, and CSET2 is required to filter out the AC ripple
noise of the inductor current. Once again, typically CSET2
and RSET2 should be sized to have a RC time constant 10
times slower than the switching frequency.
Input Voltage Regulation
In certain applications, the input supply to the power regu-
lator can exhibit fairly high output impedance. As a result,
when the regulator is running at heavy loads, VIN might
droop more than desired. The input voltage regulation loop
allows the application to be programmed to decrease the
peak inductor current level, and consequently the input
current draw, when it senses that the input voltage has
dropped below a programmed threshold. This threshold is
programmed by connecting a resistor divider from VIN to
GND with its intermediate node fed back to VINREG. With
this setup, if VVINREG ever falls below 2V, the regulator
will decrease the output current level in order to maintain
a 2V level at the pin. If this feature is not required, tie the
VINREG pin to INTVCC to prevent this control loop from
interfering with normal operation.
Another useful application for the input voltage regulation
loop is for momentary hold up supplies. Suppose an input
supply is suddenly removed from the application, VIN will
immediately start to drop until it reaches the programmed
input voltage regulation point. When this happens and
CCM operation is selected, the regulator will actually take
charge from the output capacitor and boost charge back to
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OPERATION
the input to hold the input voltage at the regulated point.
The regulator will continue to perform this operation until
the output capacitor has dissipated so much energy that it
can no longer hold up the input voltage. This momentary
input voltage holdup proves to be a handy tool for certain
applications.
INTVCC Regulator
The LTC3649 has two onboard internal low dropout (LDO)
regulators that power the drivers and internal bias circuitry.
Regardless of which one is in operation, the INTVCC must
be bypassed to GND with a minimum of 2.2µF ceramic
capacitor. Good bypassing is necessary to supply the
high transient current required by the power MOSFET
gate drivers.
The first LDO is powered from VIN, and the INTVCC volt-
age is regulated to 3.3V. The power dissipated across
this LDO would thus equal to (VIN – 3.3) • IINTVCC. For
a typical 1MHz application running in CCM, the current
drawn from INTVCC by the chip is roughly 20mA. Thus,
if the input voltage is high, the power loss and heat rise
due to this LDO is significant.
To combat this issue, a separate LDO exists that is powered
from EXTVCC. As long as the input voltage is above 5V
and the EXTVCC voltage is above 3.2V, this LDO will take
over and regulate the INTVCC voltage to 3.1V. In applica-
tions where the output voltage is programmed to 3.3V or
above, it is recommended that the VOUT (<28V) pin be
directly tied to the EXTVCC pin. Otherwise, if a separate
lower voltage rail exists on board that can supply INTVCC
current, then attaching that supply to EXTVCC will also
suffice provided that a 1µF ceramic bypass capacitor is
placed from the EXTVCC pin to GND physically close to
the chip. Both examples should significantly reduce the
power loss through the LDO.
VIN Undervoltage Programming
LTC3649 offers an accurate RUN threshold to start the
regulator. As a result, a resistor divider from IN to GND
can be placed with the intermediate node fed back to RUN
to set an accurate VIN undervoltage threshold. As the input
voltage rises, the RUN voltage will increase above the VRUN
rising threshold (1.2V), and the regulator will turn on.
Similarly, once on, if the input voltage decreases below the
VRUN falling threshold (1.1V), the regulator will turn off.
VIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3649 constantly
monitors the VIN pin for an overvoltage condition. When
VIN rises above 70V, the regulator suspends operation
by shutting off both power MOSFETs and discharges the
ISET pin voltage to ground. Once VIN drops below the
VOVLO threshold, the regulator resumes normal switching
operation.
Programming Switching Frequency
Connecting a resistor from the RT pin to GND programs
the switching frequency from 300kHz to 3MHz according
to the following formula:
f (kHz) =10
5
R
T
(kΩ)
Do not float the RT pin.
The internal phase-locked loop has a synchronization range
of ±50% around its programmed frequency. Therefore,
during external clock synchronization, the proper RT value
should be selected such that the external clock frequency
is within this 50% range of the RT programmed frequency.
Output Voltage Tracking and Soft-Start
The LTC3649 allows the user to program its output voltage
ramp rate by means of the ISET pin. Since VOUT servos
its voltage to that of VISET, placing an external capacitor
CSET from the ISET pin to GND will program the ramp-up
rate of the ISET pin and thus the VOUT voltage.
VOUT(t)= IISET •RSET 1−e
1
RSET •CSET
t
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
From 0% to 90% VOUT:
tSS ≅ –RSET • CSET • In(1 – 0.9)
tSS ≅ 2.3 • RSET • CSET
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OPERATION
The soft-start time tSS (from 0% to 90% of VOUT) is 2.3
times the time constant (RSET • CSET). The ISET pin can also
be driven by an external supply capable of sinking 50µA.
When starting up into a pre-biased VOUT, the LTC3649 will
stay in Burst Mode operation and keep the power switches
off until the voltage on ISET has ramped up to be equal
to VOUT, at which point the switcher will begin switching
and VOUT will ramp up with ISET.
Output Power Good
When the LTC3649’s output voltage is within the 7.5%
window of the regulation point, which is divided down
as a VPGDFB voltage in the range of 0.555V to 0.645V,
the output voltage is in regulation and the PGOOD pin is
pulled high with an external resistor connected to INTVCC
or another voltage rail. Otherwise, an internal open-drain
pull-down device will pull the PGOOD pin low. To prevent
unwanted PGOOD glitches during transients or dynamic
VOUT changes, the LTC3649’s PGOOD falling edge includes
a blanking delay of approximately 64 clock cycles.
Internal/External ITH Compensation
For ease of use, the user can simplify the loop compen-
sation by tying the ITH pin to INTVCC to enable internal
compensation. Because the internal compensation is
required to provide a stable output voltage for a wide
range of switching frequencies, it is designed to have a
loop response that is typically much slower than optimal.
This thus becomes a trade-off between simplicity and
OPTI-LOOP
®
optimization, where ITH components are
external and are selected to optimize the loop transient
response with minimum output capacitance.
Minimum On-Time Considerations
Due to the architecture of the LTC3649, a minimum on-time
restriction is imposed such that the top power MOSFET
can have enough time to turn on and accurately determine
if it has reached its peak current level before shutting off.
The typical minimum on-time of the regulator is 60ns.
Thus, given an application with varying input and output
voltage ranges, the frequency must be designed to be
slow enough to ensure the minimum on-time restriction
is not violated.
Freq (kHz) ≤
V
OUT(MIN)
60 • 10−6• VIN(MAX)
In the rare cases where the minimum on-time restriction is
violated, the frequency of the LTC3649 will automatically
and gradually fold back down to one-fifth of its programmed
switching frequency to allow the output to remain in regu-
lation. This feature is designed for applications where the
input voltage only experiences momentary spikes in volt-
age. In such applications, the frequency does not have to
be programmed so slow to account for those momentary
spikes, thus significantly saving component size and cost.
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APPLICATIONS INFORMATION
Input Capacitor (CIN) Selection
The input capacitance, CIN, is needed to filter the square
wave current at the drain of the top power MOSFET. To
prevent large input voltage droops from occurring, a low
effective series resistance (ESR) input capacitor sized for
the maximum RMS current should be used. The maximum
RMS current is given by:
IRMS ≅IOUT(MAX)
VOUT
VIN
VIN
VOUT
−1
This formula has a maximum at VIN = 2VOUT, where
IRMS ≅ IOUT/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further de-
rate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design. For low input voltage applications, sufficient bulk
input capacitance is needed to minimize transient effects
during output load changes.
Output Capacitor (COUT) Selection
The selection of COUT is determined by the ESR that is
required to minimize voltage ripple and load step transients
as well as the amount of bulk capacitance that is necessary
to ensure that the control loop is stable. Loop stability can
be checked by viewing the load transient response. The
output ripple, ΔVOUT, is determined by:
ΔVOUT < ΔIL
1
8 • f • C
OUT
+ESR
⎛
⎝
⎜⎞
⎠
⎟
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capaci-
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
and small footprints.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When only a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
use X5R or X7R dielectric formulations. These dielectrics
have the best temperature and voltage characteristics of
all the ceramics for a given value and size.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. Typically, five cycles are required to
respond to a load step, but only in the first cycle does the
output voltage drop linearly. The output droop, VDROOP, is
usually about three times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
COUT =3Δ
I
OUT
f • V
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements. In most applications,
the input capacitor is merely required to supply high fre-
quency bypassing, since the impedance to the supply is
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APPLICATIONS INFORMATION
very low. A 10μF ceramic capacitor is usually enough for
these conditions. Place this input capacitor as physically
close to the VIN pin as possible.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
ΔIL=VOUT
f • L 1−VOUT
VIN(MAX)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
Lower ripple current reduces core losses in the inductor
and reduces output voltage ripple. However, at extremes,
low ripple causes inductor current sensing issues. High-
est efficiency operation is obtained at low frequency with
reasonably small ripple current. However, achieving this
requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 50% of IOUT(MAX). To guarantee that ripple
current does not exceed specified inductor saturation cur-
rent ratings, the inductance should be chosen according to:
L=VOUT
f • ΔIL(MAX)
1−VOUT
VIN(MAX)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
Table 1. Inductor Selection Table
INDUCTOR INDUCTANCE (µH) DCR (mΩ) MAX CURRENT (A) DIMENSIONS (mm) HEIGHT (mm) MANUFACTURER
XAL8080 Series 4.7 8.89 17.4 8.6 × 8.1 8.0 Coilcraft
www.coilcraft.com
6.8 13.20 14.0 8.6 × 8.1 8.0
10.0 21.00 10.9 8.6 × 8.1 8.0
XAL1010 Series 3.3 3.70 27.4 11.3 × 10 10.0
4.7 5.20 25.4 11.3 × 10 10.0
5.6 6.30 23.6 11.3 × 10 10.0
6.8 8.10 21.8 11.3 × 10 10.0
8.2 11.70 18.3 11.3 × 10 10.0
10.0 13.40 17.5 11.3 × 10 10.0
FDV0840 Series 2.1 10.40 10.6 9.1 × 8.4 4.0 Toko
www.toko.com
3.9 18.80 8.4 9.1 × 8.4 4.0
4.9 24.60 6.9 9.1 × 8.4 4.0
6.9 31.70 6.1 9.1 × 8.4 4.0
IHLP-4040DZ-A1
Series
2.2 8.20 25.6 11.5 × 10.3 4.0 Vishay
www.vishay.com
3.3 13.70 18.6 11.5 × 10.3 4.0
4.7 15.00 17.0 11.5 × 10.3 4.0
5.6 17.60 16.0 11.5 × 10.3 4.0
6.8 21.20 13.5 11.5 × 10.3 4.0
10.0 33.20 12.0 11.5 × 10.3 4.0
WE-HCI 1050 Series 2.4 3.50 17.0 10.6 × 10.6 5.0 Wurth Elektronik
www.we-online.com
3.3 5.90 15.0 10.6 × 10.6 5.0
4.2 7.10 14.0 10.6 × 10.6 5.0
5.5 10.30 12.0 10.6 × 10.6 5.0
6.5 12.50 10.0 10.6 × 10.6 5.0
7.8 13.60 9.5 10.6 × 10.6 5.0
10.0 16.30 8.5 10.6 × 10.6 5.0
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APPLICATIONS INFORMATION
Once the value for L is known, the type of inductor must
be selected. Core loss is very dependent on the material,
frequency and inductance selected. Higher inductance
reduces ripple. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses
will increase.
Ferrite materials have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
minimize copper loss and preventing saturation. However,
ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Wurth Elektronik. Refer to
Table 1 for more details.
Checking Transient Response
The OPTI-LOOP external compensation allows the tran-
sient response to be optimized for a wide range of loads
and output capacitors via the ITH pin. This allows for
optimization of the control loop behavior and provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test point
truly reflects these closed-loop responses. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin.
The ITH external component network shown in the Figure 2
circuit will provide an adequate starting point for most
applications. The RC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested value) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1µs to 10µs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to the ΔILOAD •
ESR, where ESR is the effective series resistance of COUT.
ΔILOAD also begins to charge or discharge COUT generat-
ing a feedback error signal used by the regulator to return
VOUT to its steady-state value. During this recovery time,
VOUT can be monitored for overshoot or ringing that would
indicate a stability problem.
+
VIN
24V
CIN
22µF
RUN
VIN SW
VOUT
MODE/SYNC
SGND
PGND
VINREG
INTVCC
CVCC
2.2µF
CSET
10nF
RSET
66k
ISET
3649 F02
COUT
47µF
×2
VOUT
3.3V
RIMON
10k
CIMON
10nF
IMON
RT
100k
RT
RITH
3k
ITH
LTC3649
BOOST
L
1.5µH
CBOOST
0.1µF
CITH
4.7nF
Figure 2. 24V to 3.3V, 1MHz Buck Regulator with Output Current Monitoring
LTC3649
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The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the RITH and
the bandwidth of the loop increases with decreasing CITH. If
RITH is increased by the same factor that CITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in most critical frequency ranges of
the feedback loop.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>10µF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A hot swap controller is designed spe-
cifically for this purpose and usually incorporates current
limiting, short-circuit protection, and soft-start operation.
Input Disconnect/Input Short Considerations
If at any point the input supply is removed with the output
voltage still held high through its capacitor, power will be
drawn from the output capacitor to power the chip, until
the output voltage drops below the minimum VIN require-
ments of the chip.
However, if the VIN pin is grounded while the output is
held high, regardless of the RUN state, parasitic body
diodes inside the LTC3649 will pull current from the output
APPLICATIONS INFORMATION
through the SW pin. Depending on the size of the output
capacitor and the resistivity of the short, high currents may
flow through the internal body diode, and cause damage
to the part. If a VIN discharge is possible, preventative
measures should be taken to prevent current flow through
the internal body diode. Simple solutions would be plac-
ing a Schottky diode in series with the supply (Figure 3),
or placing a Schottky diode from VOUT to VIN (Figure 4).
Output Short Considerations
In an event where the output of the LTC3649 is shorted
to GND through a low resistance, high inductance trace/
wire, it is likely for the output voltage to momentarily drop
below GND. In a typical application where the output is
tied directly to the VOUT pin, it would violate the ABSMAX
specification of the pin and potentially cause damage to
the IC. To prevent damage in this case, connect a 100Ω
resistor between the output and the VOUT pin.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual power losses to de-
termine what is limiting the efficiency and which change
would produce the most improvement. Percent efficiency
can be expressed as:
% Efficiency = 100% – (P1 + P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, three main sources usually account
for most of the losses in LTC3649 circuits: 1) I2R losses,
2) switching and biasing losses, 3) other losses.
C
IN
22µF
V
IN
V
IN
LTC3649
3649 F03
C
IN
22µF
C
OUT
47µF
L
V
IN
V
IN
V
OUT
LTC3649
SW
3649 F04
Figure 3. Schottky Diode in Series with the Supply Figure 4. Schottky Diode from VOUT to VIN
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APPLICATIONS INFORMATION
1. I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET RDS(ON) and the duty
cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
2. The switching current is the sum of the MOSFET driver
and control currents. The power MOSFET driver cur-
rent results from switching the gate capacitance of
the power MOSFETs. Each time a power MOSFET gate
is switched from low to high to low again, a packet of
charge dQ moves from IN to ground. The resulting dQ/
dt is a current out of IN that is typically much larger
than the DC control bias current. In continuous mode:
IGATECHG = f(QT + QB)
where QT and QB are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. The power loss is thus:
Switching Loss = IGATECHG • VIN
The gate charge loss is a function of current through
the INTVCC pin as well as frequency. Thus, their effects
will be more pronounced in application with high LDO
supply voltages (either EXTVCC or VIN) and higher
frequencies.
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3649 internal power devices
switch quickly enough that these losses are not signifi-
cant compared to other sources. Other losses including
diode conduction losses during dead-time and inductor
core losses which generally account for less than 2%
total additional loss.
Thermal Conditions
In a majority of applications, the LTC3649 does not dis-
sipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN and FE packages. How-
ever, in applications where the LTC3649 is running at high
ambient temperature, high VIN, high switching frequency,
and maximum output current load, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
180°C, both power switches will be turned off until the
temperature drops by 15°C.
To avoid the LTC3649 from exceeding the maximum junc-
tion temperature, some thermal analysis must be done.
The goal of the thermal analysis is to determine whether
the power dissipated exceeds the maximum junction
temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
As an example, consider the case when the LTC3649
is used in applications where VIN = 24V, IOUT = 4A,
f = 1MHz, and VOUT = 3.3V. The equivalent power MOSFET
resistance RSW is:
RSW =RDS(ON)TOP •VOUT
VIN
+RDS(ON)BOT • 1−VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
=110mΩ•3.3V
24V +50mΩ• 1−3.3V
24V
⎛
⎝
⎜⎞
⎠
⎟
=58.25mΩ
In the case where the EXTVCC pin is connected to the OUT
pin, the VIN current will be minimal as most of the current
used to bias up internal circuitry and gate drive will come
directly from EXTVCC. Typically for a 1MHz application, the
current drawn from EXTVCC will be 20mA.
Therefore, the total power dissipated by the part is:
PD = IOUT2 • RSW + VEXTVCC • IEXTVCC
= 16A2 • 58.25mΩ + 3.3V • 20mA
= 998mW
LTC3649
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For more information www.linear.com/LTC3649
APPLICATIONS INFORMATION
The FE28 package junction-to-ambient thermal resistance,
θJA, is around 30°C/W. Therefore, the junction temperature
of the regulator operating in a 25°C ambient temperature
is approximately:
TJ = 0.998W • 30°C/W + 25°C = 54.94°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. Redoing the calculation
assuming that RSW increased 10% at 54.94°C yields a
new junction temperature of 60°C. If the application calls
for a higher ambient temperature and/or higher switching
frequency, care should be taken to reduce the temperature
rise of the part by using a heat sink or air flow.
If EXTVCC is not connected to VOUT, the IC current will come
from VIN. In this case, the total power dissipation will be:
PD = 16A2 • 58.25mΩ + 24V • 20mA = 1.41W
This will result in an extra 400mW of power dissipation.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3649 (refer to Figure 5). Check the following in
your layout:
1. Do the capacitors CIN connect to the VIN and GND as
close as possible? These capacitors provide the AC
current to the internal power MOSFETs and their drivers.
2. Are COUT and L closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
3. Solder the exposed pad (Pin 29) on the bottom of the
package to the GND plane. Connect this GND plane to
other layers with thermal vias to help dissipate heat
from the LTC3649.
4. The ground terminal of the ISET resistor must be
connected to the other quiet signal GND and together
connected to the power GND on only one point. The
ISET resistor should be placed and routed away from
noisy components and traces, such as the SW line, and
its trace should be minimized
Figure 5. Sample PCB Layout
LTC3649
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For more information www.linear.com/LTC3649
APPLICATIONS INFORMATION
5. Keep sensitive components away from the SW pin. The
ISET resistor, RT resistor, the compensation compo-
nents CITH and RITH, and the INTVCC bypass caps should
be routed away from the SW trace and the inductor.
6. A ground plane is preferred.
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
Design Example
As a design example, consider the LTC3649 in an applica-
tion with the following specifications:
VIN = 24V to 36V
VOUT = 5V
IOUT(MAX) = 4A
IOUT(MIN) = 500mA
fSW = 1MHz
First, the RSET is selected based on:
RSET =
V
OUT
50µA =
5V
50µA =100kΩ
For best accuracy, 0.5% 100k resistor is selected.
For a typical soft-start time of 2ms (0% to 90% of final
VOUT value), the CSET should be:
2ms = 2.3 • RSET • CSET
⇒CSET = 8.7nF
A typical 10nF capacitor can be used for CSET.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized. Select from
the characteristic curves the correct RT resistor for the
1MHz switching frequency. Based on that, RT should be
100k. Then calculate the inductor value to achieve a cur-
rent ripple that is about 40% of the maximum load current
at maximum VIN:
L=5V
1MHz • 1.6A
⎛
⎝
⎜⎞
⎠
⎟1−5V
36V
⎛
⎝
⎜⎞
⎠
⎟=2.7µH
COUT will be selected based on the ESR that is required
to satisfy the output ripple requirement and the bulk ca-
pacitance needed for loop stability. For this design, two
47µF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
IRMS =4A 5V
36V
⎛
⎝
⎜⎞
⎠
⎟36V
5V −1
⎛
⎝
⎜⎞
⎠
⎟
1/2
=1.38A
Decoupling the VIN pin with one 22µF ceramic capacitor
is adequate for most applications.
LTC3649
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For more information www.linear.com/LTC3649
TYPICAL APPLICATIONS
0.5V to 32V, 2.1A Low-Noise High Efficiency Lab Supply
0.1µF
40V
10nF
10pF
3649 TA02
VIN
40V
10k
2.2µF
10k 1.5k
LTC3649
BOOST
SW
VOUT
PGDFB
PGOOD
PGND
VIN
RUN
MODE/SYNC
VINREG
INTVCC
IMONISET RTSGNDITHEXTVCC
10µF10µF
1.5nF
47µF
200k
0.1µF
10µH
47µF
IN
IMON
ILIM
SHDN
OUT
CDC
SET
22µF
VOUT
0.5V TO 32V
LT3086
GND
357Ω
100k
LTC3649
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For more information www.linear.com/LTC3649
Dual Phase Operation
0.1µF 4700pF
3649 TA03
VIN
12V NOM
9V TO 36V
RUN
IMON1
IMON2
2.2µF
LTC3649
BOOST
SW
VOUT
PGDFB
PGOOD
PGND
VIN
VINREG
RUN
MODE/SYNC
INTVCC
IMONISET RTSGNDITHEXTVCC
10µF10µF
10µF10µF
0.1µF 4700pF
47µF
47µF
100k
100k
0.1µF
L1
3.3µH
V+OUT1
GND
100k
OUT2
SET MOD
LTC6908-1 EXT SYNC
1MHz
2nF
10pF 1k
10k
10k
49.9k
10pF
LTC3649
PGND
PGOOD
PGDFB
VOUT
SW
BOOST
INTVCC
MODE/SYNC
RUN
VINREG
VIN
IMONISET RTSGNDITHEXTVCC
47µF
47µF
0.1µF
3.3µH
VOUT
5V AT 8A
2.2µF
TYPICAL APPLICATIONS
LTC3649
22
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For more information www.linear.com/LTC3649
TYPICAL APPLICATIONS
Wide Input Signal Range Audio Driver
Cable Drop Compensation
1.5nF5nF
3649 TA04
VIN
24V
2.2µF 10nF
1.5k
LTC3649
BOOST
SW
VOUT
PGDFB
PGOOD
PGND
VIN
RUN
IMONISET RTSGNDITHEXTVCC
10µF
LINE LEVEL
RECOMMENDED
SIGNAL
10µF
10nF
200k10k
10nF
240k
0.1µF
4.7µH 10µF
10µF
10µF
SPEAKER
0.1µF
MKP TYPE
INTVCC
MODE/SYNC
44µF
VINREG
3649 TA05
VIN
5.5V to 60V
2.2µF
LTC3649
BOOST
SW
VOUT
VIN
RUN
IMONISET RTSGNDITH
10µF
RISET = 100k
10µF
0.1µF
10pF
RT
100k
95.3k
4.02k
1nF
2k
3.9pF
0.1µF
3.3µH
CABLE
RESISTANCE
50mΩ
50mΩ
PGDFB
PGOOD
PGND
100µF RLOAD
VOUT
5V AT 0A
5V AT 4A
MODE/SYNC
INTVCC
VINREG
EXTVCC
LTC3649
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For more information www.linear.com/LTC3649
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3649#packaging for the most recent package drawings.
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±
0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50
±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
LTC3649
24
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For more information www.linear.com/LTC3649
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3649#packaging for the most recent package drawings.
FE28 (EB) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 27 26 2524 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60
±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EB
LTC3649
25
3649fb
For more information www.linear.com/LTC3649
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REV DATE DESCRIPTION PAGE NUMBER
A 06/16 Clarified shutdown current to 18μA
Clarified IMON conditions
Clarified Programming Switching Frequency section
1
3
11
B 05/17 Clarified INTVCC capacitor on Typical Applications 21, 22
REVISION HISTORY
LTC3649
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For more information www.linear.com/LTC3649
LINEAR TECHNOLOGY CORPORATION 2015
LT 0517 REV B • PRINTED IN USA
www.linear.com/LTC3649
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5VOUT with Remote Sensing
22µF
2.2µF
47µF
×2
0.1µF
3.3µH
100k
10nF
2k
100pF
1.5nF
100k
24V
RUN
LTC3649
IN
BOOST
SW
V
IN
ISET
ITH
R
T
MODE/SYNC
PGDFB
PGOOD
SGND
PGND
V
OUT
RESISTANCE
CABLE
3649 TA06
0.1Ω
0.1Ω
47µF
VOUT
5V
EXTVCC
INTVCC
VINREG
