NX2139A
1
Rev. 2.4
06/13/12
TYPICAL APPLICATION
DESCRIPTION
The NX2139A controller IC is a compact Buck control-
ler IC with 16 lead MLPQ package designed for step
down DC to DC converter in portable applications. It
can be selected to operate in synchronous mode or
non-synchronous mode to improve the efficiency at light
load.Constant on time control provides fast response,
good line regulation and nearly constant frequency un-
der wide voltage input range. The NX2139A controller
is optimized to convert single supply up to 22V bus
voltage to as low as 0.75V output voltage. Over cur-
rent protection and FB UVLO followed by latch fea-
ture. A built-in LDO controller can drive an external N-
MOSFET to provide a second output voltage from ei-
ther PWM output source or other power source. Both
PWM controller and LDO controller have separate EN
feature. Other features includes: 5V gate drive capa-
bility, power good indicator, over voltage protection,
internal Boost schottky diode and adaptive dead band
control.
n Internal Boost Schottky Diode
n Ultrasonic mode operation available
nBus voltage operation from 4.5V to 22V
n Less than 1uA shutdown current with Enable low
nExcellent dynamic response with constant on time
control
n Selectable between Synchronous CCM mode and
diode emulation mode to improve efficiency at
light load
n Programmable switching frequency
nCurrent limit and FB UVLO with latch off
nOver voltage protection with latch off
nLDO controller with seperate enable
nTwo independent Power Good indicator available
n Pb-free and RoHS compliant
ORDERING INFORMATION
FEATURES
SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER
APPLICATIONS
nNotebook PCs and Desknotes
nTablet PCs/Slates
nOn board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
nHand-held portable instruments
PRODUCTION DATA SHEET
Figure1 - Typical application of NX2139A
Device Temperature Package Pb-Free
NX2139ACMTR -10 oC to 100oC3X3 MLPQ-16L Yes
Pb Free Product
VIN 7V~22V
TON
HDRV
BST
SW
LDRV
OCSET
FB
VOUT
ENSW
/MODE
5V
10 VCC
PVCC
PGOOD
Vout 1.8V/7A
GND
1.5V@2A
LDODRV
LDOFB
ENLDO
LDOPG
5V
LDOPG
PGOOD 1MEG
4
9
2
15
14
5
PAD
6
7
3
1
10
8
11
13
12
16
100k
1u 1u
100k
50
33n 20k
1n
7.5k
7.5k
7.5k
2x10uF
10.5k
2R5TPE330MC
5k
1u
2x10uF
1n
IRF7807
AO4714
1.5uH
N X 2 1 3 9 A
330uF
M3
SI4800
330p
2.2
NX2139A
2
Rev. 2.4
06/13/12
9
10
11
12
4
3
2
1
VCC
TON
FB
PGOOD PVCC
OCSET
SW
HDRV
8
7
6
5
LDODRV
LDRV
LDOPG
LDOFB
16 15 14 13
ENLDO
VO
ENSW/MODE
BST
AGND
17
ABSOLUTE MAXIMUM RATINGS
VCC,PVCC to GND & BST to S W voltage ............ -0.3V to 6.5V
TON to GND ......................................................... -0.3V to 28V
HDRV to S W Voltage .......................................... -0.3V to 6.5V
SW to GND ......................................................... -2V to 30V
All other pins ........................................................ VCC+0.3V
Storage
Temperature Range ................................. -65
oC to 150 oC
Operating Junction Temperature Range .................-40 oC to 150 oC
ESD Susceptibility ............................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM R ATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
3x3 16-LEAD PLASTIC MLPQ
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5 V, VIN=15V and TA =25oC, unless otherwise
specified.
o
JA CWθ≈46/
PARAMETER SYM Test Condition Min TYP MAX Units
VIN
recommended voltage range VIN 4.5 22 V
Shut down current ENLDO=GND, ENSW=GND 1 uA
VCC,PVCC Supply
Input voltage range VCC 4.5 5.5 V
Operating quiescent current
VFB=0.85V, ENLDO=GND,
ENSW=5V 1.8 mA
Shut down current ENLDO=GND, ENSW=GND 1 uA
NX2139A
3
Rev. 2.4
06/13/12
N
PARAMETER SYM Test Condition Min TYP MAX Units
VCC UVLO
Under-voltage Lockout
threshold
VCC
_UVLO
3.9 4.1 4.5 V
Falling VCC threshold 3.7 3.9 4.3 V
ON and OFF time
TON operating current VIN=15V, Rton=1Mohm 15 uA
ON -time
VIN=9V,VOUT=0.75V,
Rton=1Mohm 312 390 468 ns
Minimum off time
380 590 800 ns
FB voltage
Internal FB voltage Vref 0.739 0.75 0.761 V
Input bias current 100 nA
Line regulation VCC from 4.5V to 5.5V -1 1%
OUTPUT voltage
Output range 0.75 3.3 V
VOUT shut down discharge
resistance ENSW/MODE=GND 30 ohm
Soft start time 1.5 ms
PGOOD
Pgood high rising threshold 90 % Vref
PGOOD delay after softstart NOTE1 1.6 ms
PGOOD propagation delay
filter NOTE1 2us
Power good hysteresis 5%
Pgood output switch
impedance
13 ohm
Pgood leakage current 1 uA
SW zero cross comparator
Offset voltage 5 mV
High Side Driver
(CL=3300pF)
Output Impedance , Sourcing
Current
Rsource(Hdrv) I=200mA 1.5 ohm
Output Impedance , Sinking
Current
Rsink(Hdrv) I=200mA 1.5 ohm
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(L to
H)
Ldrv going Low to Hdrv going
High, 10% to 10%
30 ns
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
Current
Rsource(Ldrv) I=200mA 1.5 ohm
Output Impedance, Sinking
Current
Rsink(Ldrv) I=200mA 0.5 ohm
Rise Time TLdrv(Rise) 10% to 90% 50 ns
TLdrv(Fall)
90% to 10%
50
ns
10 nsDeadband Time Tdead(H to
L)
SW going Low to Ldrv going
High, 10% to 10%
NX2139A
4
Rev. 2.4
06/13/12
NOTE1: This parameter is guaranteed by design but not tested in production(GBNT).
PARAMETER SYM Test Condition Min TYP MAX Units
ENSW/MODE threshold and
bias current
PFM/Non Synchronous Mode
80%
VCC
VCC+0
.3V V
Ultrasonic Mode
60%
VCC
80%
VCC V
Synchronous Mode
Leave it open or use limits in
spec 2
60%
VCC V
Shutdown mode 00.8 V
ENSW/MODE=VCC 5 uA
ENSW/MODE=GND -5 uA
LDO Controller
Quiescent current
PWM OFF, LDOEN=HI,
IOUT=0mA 1 mA
LDOEN logic high voltage 2V
LDOEN logic low voltage 0.8 V
LDOFB reference voltage
0.728
0.75
0.773
V
Output UVLO threshold 70 %Vref
Open loop gain NOTE1 60 DB
LDOFB input bias current 1uA
LDODrv sourcing current LDOFB=0.72V 2mA
LDODrv sinking current LDOFB=0.78V 2mA
LDO PGOOD threshold 90 %Vref
LDO PGOOD propagation
delay filter NOTE1 2us
LDO PGOOD impedance 13 ohm
Current Limit
Ocset setting current 20 24 28 uA
Over temperature
Threshold NOTE1 155 oC
Hysteresis 15 o
C
Under voltage
FB threshold 70 %Vref
Over voltage
Over voltage tripp point 125 %Vref
Internal Schottky Diode
Forward voltage drop Forward current=50mA 500 mV
Input bias current
NX2139A
5
Rev. 2.4
06/13/12
PIN DESCRIPTIONS
PIN NUMBER PIN SYMBOL PIN DESCRIPTION
This pin is directly connected to the output of the switching regulator and
senses the VOUT voltage. An internal MOSFET discharges the output during
turn off.
This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is
placed as close as possible to this pin and ground pin.
This pin is the error amplifiers inverting input. This pin is connected via
resistor divider to the output of the switching regulator to set the output DC
voltage from 0.75V to 3.3 V.
PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc
or lower voltage. When FB pin reaches 90% of the reference voltage
PGOOD transitions from LO to HI state.
PGOOD indicator for LDO, requires a pull up resistor to Vcc or lower volt-
age. When LDOFB pin reaches 90% of the reference voltage PGOOD
transitions from LO to HI state.
This pin is the error amplifiers inverting input. This pin is connected via
resistor divider to the output of the LDO to set the output DC voltage.
The drive signal for external LDO N channel MOSFE T.
Low side gate driver output.
Provide the voltage supply to the lower MOSFET drivers. Place a high
frequency decoupling capacitor 1uF X5R to this pin.
This pin is connected to the drain of the external low side MOSFET and is
the input of over current protection(OCP) comparato r. An internal current
source is flown to the external resistor which sets the OCP voltage across
the Rdson of the low side MOSFE T.
This pin is connected to source of high side FE Ts and provide return path for
the high side driver. It is also the input of zero current sensing comparato r.
High side gate driver output.
This pin supplies voltage to high side FET drive r. A high freq 1uF X7R
ceramic capacitor and 2.2ohm resistor in series are recommended to be
placed as close as possible to and connected to this pin and S W pin.
LDO enable input functions only when ENS W/MODE is not shutdown.
Switching converter enable input. Connect to VCC for PFM/Non synchronous
mode, connected to an external resistor divider equals to 70%VCC for ultra-
sonic, connected to GND for shutdown mode, floating or connected to 2V for
the synchronous mode.
VIN sensing input. A resistor connects from this pin to VIN will set the fre-
quency. A 1nF capacitor from this pin to GND is recommended to ensure the
proper operation.
Power ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PAD
VOUT
VCC
FB
PGOOD
LDOPG
LDOFB
LDODRV
LDRV
PVCC
OCSET
SW
HDRV
BST
ENLDO
ENSW/
MODE
TON
GND
NX2139A
6
Rev. 2.4
06/13/12
BLOCK DIAGRAM
Figure 2 - Simplified block diagram of the NX2139A
soft
start
VIN
BST(13)
HDRV(12)
LDRV(8)
PGND
SW(11)
PVCC(9)
5V
FET Driver
start ODB
HD_IN
start
VOUT(1)
0.9*Vref
SS_finished
PGOOD(4)
OCSET(10)
ENSW
/MODE(15)
start
POR
FB(3)
GND(17 PAD)
TON(16)
HD
VREF=0.75V
FBUVLO_latch
R
SQ
Mini offtime
400ns
OCP_COMP
HD
Diode
emulation
OCP_COMP
0.7*Vref
FB
1.25*Vref/0.7VREF
FB
OVP
FBUVLO_latch
VOUT
Sync
PFM_nonultrasonic
4.3/4.1
VCC(2)
Bias POR
Disable
Disable_B
0.9*Vref
LDOSS_finished
LDOPG(5)
ENLDO(14)
LDO_POR
LDODRV(7)
LDOFB(6)
0.7*Vref
LDOFBUVLO_latch
LDOFBUVLO_latch
VOUT
VIN
1.5V@2A~5A
1.8V
Thermal
shutdown
soft start
ON time
pulse
genearation
VOUT
MODE
SELECTION
LDO_EN
VCC
1M
1M
NX2139A
7
Rev. 2.4
06/13/12
Figure 3 - Demo board schematic
VIN 7V~22V
TON
HDRV
BST
SW
LDRV
OCSET
FB
VOUT
ENSW
/MODE
5V
10 VCC
PVCC
PGOOD
Vout 1.8V/7A
GND
1.5V@2A
LDODRV
LDOFB
ENLDO
LDOPG
5V
LDOPG
PGOOD 1MEG
4
9
2
15
14
5
PAD
6
7
3
1
10
8
11
13
12
16
100k
1u 1u
100k
50
33n 20k
1n
7.5k
7.5k
7.5k
CO2
2x10uF
10.5k
2R5TPE330MC
5k
1u
CI1
2x10uF
1n
IRF7807
AO4714
1.5uH
N X 2 1 3 9 A
330uF
R1
R2
R3
R4
R5
R6
R7
R8
R9 R10
R11
M1
M2
Lo
CO1
C1 C2
C3
C5
C4
C6
2.2
1.5n
R12
C7
M3
SI4800
330p
C8
2.2R13
TYPICAL APPLICATION
(VIN=7V to 22V, SW VOUT=1.8V/7A, LDO VOUT=1.5V/2A)
NX2139A
8
Rev. 2.4
06/13/12
Bill of Materials
Item Quantity Reference Value Manufacture
1 2 CI1 10uF/25V/X5R
2 2 CO2 10uF/6.3V/X5R
3 1 CO1 2R5TPE330MC SANYO
4 3 C1,C2,C4 1uF
5 2 C3,C5 1nF
6 1 C6 33nF
7 1 C7 1.5nF
8 1 C8 330pF
9 1 Lo DO5010H-152 COILCRAFT
10 1M1 IRF7807 IR
11 1M2 AO4714 AOS
12 1M3 SI4800 PHILIPS
13 2R1,R3 100k
14 1R2 10
15 1R4 1M
16 1R5 5k
17 1R6 10.5k
18 3R7,R10,R11 7.5k
19 1R8 50
20 1R9 20k
21 2R12,R13 2.2
22 1U1 NX2139A NEXSEM INC.
NX2139A
9
Rev. 2.4
06/13/12
Fig.6 LDO output transient with S W in PFM mode
(CH1 1.8V OUTPUT AC, CH2 1.5V LDO AC, CH4
LDO OUTPUT CURRENT)
Demoboard Waveforms
Fig.4 Startup (CH1 1.8V OUTPUT, CH2 1.5V LDO,
CH3 SW PGOOD, CH4 LDO PGOOD)
Fig.5 Turn off (CH1 1.8V OUTPU T, CH2 1.5V LDO,
CH3 SW PGOOD, CH4 LDO PGOOD)
Fig. 9 VOUT ripple @ VIN=12 V,IOUT=4A (CH1 SW,
CH3 VOUT AC)
Fig.7 SW output transient (CH1 1.8V OUTPUT AC,
CH2 1.5V LDO AC, CH4 1.8V OUTPUT CURRENT)
Fig.8 Start into short (CH1 VIN, CH2 5V VCC, CH4
INDUCTOR CURRENT)
NX2139A
10
Rev. 2.4
06/13/12
Fig. 10 Output efficiency
VIN=12V, VOUT=1.8V
50.00%
60.00%
70.00%
80.00%
90.00%
100.00%
10 100 1000 10000
OUTPUT CURRENT(mA)
OUTPUT EFFICIENCY(%)
NX2139A
11
Rev. 2.4
06/13/12
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2139A,
the schematic is figure 1.
VIN = 7 to 22V
VOUT=1.8V
FS=220kHz
IOUT=7A
DVRIPPLE <=60mV
DVDROOP<=60mV @ 3A step
On_Time and Frequency Calculation
The constant on time control technique used in
NX2139A delivers high efficienc y, excellent transient
dynamic response, make it a good candidate for step
down notebook applications.
An internal one shot timer turns on the high side
driver with an on time which is proportional to the input
supply VIN as well inversely proportional to the output
voltage VOUT. During this time, the output inductor
charges the output cap increasing the output voltage
by the amount equal to the output ripple. Once the
timer turns off, the Hdrv turns off and cause the output
voltage to decrease until reaching the internal FB volt-
age of 0.75V on the PFM comparator. At this point the
comparator trips causing the cycle to repeat itself. A
minimum off time of 400nS is internally set.
The equation setting the On Time is as follows:
12
TONOUT
IN
4.4510RV
TON V0.5V
−
×××
=− ...(1)
OUT
S
IN
V
F
VTON
=× ...(2)
In this application example, the RTON is chosen
to be 1Mohm, when VIN=22V, the TON is 372nS and
FS is around 220kHz.
Output Inductor Selection
The value of inductor is decided by inductor ripple
current and working frequenc y. Larger inductor value
normally means smaller ripple current. However if the
inductance is chosen too large, it brings slow response
and lower efficiency. The ripple current is a design free-
dom which can be decided by design engineer accord-
ing to various application requirements. The inductor
value can be calculated by using the following equa-
tions:
(
)
INOUT ON
OUT
RIPPLE
RIPPLEOUTPUT
V-VT
L= I
I=kI
×
× ...(3)
where k is percentage of output current.
In this example, inductor from COILCRAFT
DO5010H-152 with L=1.5uH is chosen.
Current Ripple is recalculated as below:
INOUT ON
RIPPLE
OUT
(V-V)T
I= L
(22V-1.8V)372nS
= 1.5uH
=5A
×
× ...(4)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specifica-
tion for the load transient. The optimum design may
require a couple of iterations to satisfy both conditions.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(5).
∆
∆=×∆+
××
RIPPLE
RIPPLERIPPLE
SOUT
I
VESRI 8FC ...(5)
Where ESR is the output capacitors' equivalent
series resistance,C OUT is the value of output capaci-
tors.
Typically POSCAP is recommended to use in
NX2139's applications. The amount of the output volt-
age ripple is dominated by the first term in equation(5)
NX2139A
12
Rev. 2.4
06/13/12
and the second term can be neglected.
For this example, one POSCAP 2R5TPE330MC
is chosen as output capacito r, the ESR and inductor
current typically determines the output voltage ripple.
When VIN reach maximum voltage, the output volt-
age ripple is in the worst case.
RIPPLE
desire
RIPPLE
V60mV
ESR=12m
I5A
∆
==Ω
∆ ...(6)
If low ESR is required, for most applications, mul-
tiple capacitors in parallel are needed. The number of
output capacitor can be calculate as the following:
ERIPPLE
RIPPLE
ESRI
NV
×∆
=∆ ...(7)
12m5A
N60mV
Ω×
=
N =1
The number of capacitor has to be round up to a
integer. Choose N =1.
Based On Transient Requirement
Typically, the output voltage droop during tran-
sient is specified as
∆Vdroop ∆V
tran
< @step load DISTEP
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacito r, the other section
is a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over-
shoot when load from high load to light load with a
DISTEP transient load, if assuming the bandwidth of sys-
tem is high enough, the overshoot can be estimated
as the following equation.
2
OUT
overshootstep OUT
V
VESRI 2LC
∆=×∆+×τ
×× ...(8)
where
Ï„
is the a function of capacito r,etc.
crit
step
OUTcrit
OUT
0ifLL
LI
ESRCifLL
V
≤

×∆
τ=−×≥

 ...(9
where
OUTOUTEEOUT
crit stepstep
ESRCVESRCV
LII
××××
==
∆∆
...(10)
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected
output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacito r. For low frequency ca-
pacitor such as electrolytic capacito r, the product of
ESR and capacitance is high and
crit
LL
≤ is true. In
that case, the transient spec is mostly like to depen-
dent on the ESR of capacito r.
Most case, the output capacitor is multiple ca-
pacitor in parallel. The number of capacitor can be cal-
culated by the following
Estep
2
OUT
tranEtran
ESRI V
NV2LCV
×∆
=+×τ
∆×××∆ ...(11)
where
crit
step
EEcrit
OUT
0ifLL
LI
ESRCifLL
V
≤

×∆
τ=−×≥

 ...(12)
For example, assume voltage droop during tran-
sient is 60mV for 3A load step.
If one POSCAP 2R5TPE330MC(330uF, 12mohm
ESR) is used, the crticial inductance is given as
EEOUT
crit step
ESRCV
LI
12m3300F1.8V
23.76H
3A
××
==
∆
Ω×µ×
=µ
The selected inductor is 1.5uH which is smaller
than critical inductance. In that case, the output volt-
age transient mainly dependent on the ESR.
number of capacitor is
Estep
tran
ESRI
NV
12m3A
60mV
0.6
×∆
=∆
Ω×
=
=
Choose N=1.
NX2139A
13
Rev. 2.4
06/13/12
Based On Stability Requirement
ESR of the output capacitor can not be chosen
too low which will cause system unstable. The zero
caused by output capacitor's ESR must satisfy the re-
quirement as below:
SW
ESR
OUT
F
1
F
2ESRC4
=≤
×π×× ...(13)
Besides that, ESR has to be bigger enough so
that the output voltage ripple can provide enough volt-
age ramp to error amplifier through FB pin. If ESR is
too small, the error amplifier can not correctly dectect
the ramp, high side MOSFET will be only turned off for
minimum time 400nS. Double pulsing and bigger out-
put ripple will be observed. In summar y, the ESR of
output capacitor has to be big enough to make the sys-
tem stable, but also has to be small enough to satify
the transient and DC ripple requirements.
Input Capacitor Selection
Input capacitors are usually a mix of high fre-
quency ceramic capacitors and bulk capacitors. Ce-
ramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS cur-
rent rating. The RMS current in the input capacitors
can be calculated as:
RMSOUT
ONS
IID1-D
DTF
=××
=× ...(14)
When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of
input RMS current is 1.9A.
For higher efficiency, low ESR capacitors are
recommended. One 10uF/X5R/25V and two 4.7uF/
X5R/25V ceramic capacitors are chosen as input
capacitors.
Power MOSFETs Selection
The NX2139A requires at least two N-Channel
power MOSFETs. The selection of MOSFETs is based
on maximum drain source voltage, gate source volt-
age, maximum current rating, MOSFET on resistance
and power dissipation. The main consideration is the
power loss contribution of MOSFETs to the overall con-
verter efficienc y. In this application, one IRF7807 for
high side and one AO4714 with integrated schottky di-
ode for low side are used.
There are two factors causing the MOSFET
power loss:conduction loss, switching loss.
Conduction loss is simply defined as:
×××
×−××
+
2
HCONOUTDS(ON)
2
LCONOUTDS(ON)
TOTALHCONLCON
P=IDRK
P=I(1D)RK
P=PP
...(15)
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case. Conduction loss should not exceed
package rating or overall system thermal budget.
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
SWINOUTSWS
1
PVITF
2
=××××
...(16)
where I OUT is output current, TSW is the sum of T R
and TF which can be found in mosfet datasheet, and
FS is switching frequenc y. Swithing loss PSW is fre-
quency dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFE T.
MOSFET gate driver loss is the loss generated by dis-
charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
...(17)
where QHGATE is the high side MOSFE Ts gate
charge,QLGATE is the low side MOSFE Ts gate
charge,VHGS is the high side gate source voltage, and
VLGS is the low side gate source voltage.
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
NX2139A
14
Rev. 2.4
06/13/12
at 0.75V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.75V
when the output voltage is at the desired value.
The following equation applies to figure 11, which
shows the relationship between
OUT
V,
REF
Vand volt-
age divide r.
Vout
Vref
Fb
R2
R1
Figure 11 - Voltage Divider
2REF
1
OUT REF
RV
R=
V-V
×
...(18)
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divide r.
Mode Selection
NX2139A can be operated in PFM mode, ultra-
sonic PFM mode, CCM mode and shutdown mode by
applying different voltage on ENS W/MODE pin.
When VCC applied to ENS W/MODE pin,
NX2139A is In PFM mode. The low side MOSFET emu-
lates the function of diode when discontinuous con-
tinuous mode happens, often in light load condition.
During that time, the inductor current crosses the zero
ampere border and becomes negative current. When
the inductor current reaches negative territory, the low
side MOSFET is turned off and it takes longer time for
the output voltage to drop, the high side MOSFET waits
longer to be turned on. At the same time, no matter
light load and heavy load, the on time of high side
MOSFET keeps the same. Therefore the lightier load,
the lower the switching frequency will be. In ultrosonic
PFM mode, the lowest frequency is set to be 25kHz to
avoid audio frequency modulation. This kind of reduc-
tion of frequency keeps the system running at light light
with high efficienc y.
In CCM mode, inductor current zero-crossing
sensing is disabled, low side MOSFET keeps on even
when inductor current becomes negative. In this way
the efficiency is lower compared with PFM mode at
light load, but frequency will be kept constant.
Over Current Protection
Over current protection for NX2139A is achieved
by sensing current through the low side MOSFE T. An
typical internal current source of 24uA flows through
an external resistor connected from OCSET pin to SW
node sets the over current protection threshold. When
synchronous FET is on, the voltage at node SW is given
as
SWLDSON
V=-IR×
The voltage at pin OCSET is given as
OCPOCPSW
IR+V
×
When the voltage is below zero, the over current
occurs as shown in figure below.
OCP
comparator
OCP
24uA
OCP
I
OCP
RSW
vbus
Figure 12 - Over Voltage Protection
The over current limit can be set by the following
equation.
=×
SETOCPOCPDSON
IIR/R
If the low side MOSFET RDSON=10mΩ at the OCP
occuring moment, and the current limit is set at 12A,
then
SETDSON
OCP
OCP
IR 12A10m
R5k
I24uA
××Ω
===Ω
Choose ROCP=5kΩ
NX2139A
15
Rev. 2.4
06/13/12
Power Good Output
Power good output is open drain output, a pull
up resistor is needed. Typically when softstart is
finised and FB pin voltage is over 90% of V REF, the
PGOOD pin is pulled to high after a 1.6ms dela y.
Smart Over Output Voltage Protection
Active loads in some applications can leak cur-
rent from a higher voltage than VOUT, cause output
volt-
age to rise. When the FB pin voltage is sensed over
112% of VREF, the high side MOSFET will be turned off
and low side MOSFET will be turned on to discharge
the VOUT. NX2139A resumes its switching operation af-
ter FB pin voltage drops to V REF.
If FB pin voltage keeps rising and is sensed over
125% of VREF, the low side MOSFET will be latched to
be on to discharge the output voltage and over voltage
protection is triggered. To resume the switching opera-
tion, resetting voltage on pin VCC or pin EN is neces-
sary.
Under Output Voltage Protection
Typically when the FB pin voltage is under 70%
of V
REF, the high side and low side MOSFET will be
turned off. To resume the switching operation, VCC or
ENSW has to be reset.
LDO Selection Guide
NX2139A offers a LDO controller. The selection
of MOSFET to meet LDO is more straight forward.
The MOSFET has to be logic level MOSFET and its
Rdson at 4.5V should meet the dropout requirement.
For example.
VLDOIN =1.8V
VLDOOUT =1.5V
ILoad =2A
The maximum Rdson of MOSFET should be
RDSONLDOINLDOOUTLOAD
R(VV)I
(1.8V1.5V)/2A0.15
=−×
=−=Ω
Most of MOSFE Ts can meet the requirement.
More important is that MOSFET has to be selected
right package to handle the thermal capability. For LDO,
maximum power dissipation is given as
LOSSLDOINLDOOUTLOAD
P(VV)I
(1.8V1.5V)2A0.6W
=−×
=−×=
Select MOSFET SI4800 with 33m Ω RDSON is
sufficient.
LDO Compensation
The diagram of LDO controller including VCC
regulator is shown in the following figure.
Rf1
Rf2
Rc Cc
+
LDO input
Rload
ESR
Co
Vref
LDOFB
LDODRV
Rb
Cb
Figure 13 - NX2139 A LDO controller.
Rb and Cb have fixed value which is used to com-
pensate the comparater of the LDO controller. Set
Rb=50ohm, Cb=33nF.
For most low frequency capacitor such as elec-
trolytic, POSCAP, OSCON, etc, the compensation pa-
rameter can be calculated as follows.
m
C
Of1m
gESR
1
C=
2FR1+gESR
×
×
×π×××
where FO is the desired crossover frequenc y.
Typically, when the POSCAP and electrical ca-
pacitor is chosen as output capacito r, crossover fre-
quency F
O has to be 2 to 3 times higher than zero
caused by ESR. In this example, we select Fo=150kHz.
gm is the forward trans-conductance of MOSFET.
For SI4800, gm=19.
Select Rf1=7.5kohm.
Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.
C
119S18m
C= =36pF
2150kHz7.5k1+19S18m
×Ω
×
×π××Ω×Ω
Typically CC is chosen to be 1 to 1.5 times smaller
than calculated value to compensate parasitic effect.
NX2139A
16
Rev. 2.4
06/13/12
Here C
C is chosen to be 33p F. For electrolytic or
POSCAP, RC is typically selected to be zero.
Rf2 is determined by the desired output voltage.
f1REF
f2
LDOOUTREF
RV
R=
VV
7.5k0.75V
=
1.5V0.75V
=7.5k
×−
Ω×
−
Ω
Choose Rf2=7.5kΩ.
When ceramic capacitors or some low ESR bulk
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency FO has to be chosen much higher
than zero caused by RC and CC and much lower than
zero caused by ESR . For example, 10uF ceramic is
used as output capacito r. We select Fo=300kHz,
Rf1=7.5kohm and select MOSFET SI4800(g
m=19). RC
and CC can be calculated as follows.
OUT
m
OOOUT
Cf1
OUT
m
m
OUT
V
1+g
2FCI
R=R V
ggI
1.5V
1+19S
2300kHz20uF
2A
=7.5k
1.5V
19S 19S 2A
=14.9k
×
×π××
××
×
×
×π××
Ω××
×
Ω
Typically RC is chosen to be 1 to 1.5 times smaller
than calculated value to compensate parasitic effect.
Choose RC=20kΩ.
O
C
Cm
10C
C=
Rg
1020uF
=
20k19S
=0.53nF
×
××
Ω×
Choose CC=1000pF.
Current Limit for LDO
Current limit of LDO is achieved by sensing the
LDO feedback voltage. When LDO_FB pin is below
70% of VREF, the IC goes into latch mode. The IC will
turn off all the channel until VCC or ENS W resets.
Power Good for LDO
Power good output is open drain output, a pull
up resistor is needed. Typically when softstart is
finised and LDOFB pin voltage is over 90% of V REF,
the LDOPGOOD pin is pulled to high.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFE T, low-side
MOSFET, inductor and output capacitors. A noisy en-
vironment is generated by the power components due
to the switching powe r. Small signal components are
connected to sensitive pins or nodes. A multilayer lay-
out which includes power plane, ground plane and sig-
nal plane is recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-
cally touching the drain pin of the upper MOSFE T, a
plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is re-
quired.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane and as close as possible. A snubber needs to be
placed as close to this junction as possible.
NX2139A
17
Rev. 2.4
06/13/12
5. Source of the lower MOSFET needs to be con-
nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other by-
passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divide r.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals, should be kept away from the in-
ductor and other noise sources. The resistor divider
must be located as close as possible to the FB pin of
the device.
9. All GNDs need to go directly thru via to GND
plane.
10. In multilayer PCB, separate power ground
and analog ground. These two grounds must be con-
nected together on the PC board layout at a single point.
The goal is to localize the high current path to a sepa-
rate loop that does not interfere with the more sensi-
tive analog control function.
NX2139A
18
Rev. 2.4
06/13/12
Demoboard Schematic
Figure 14 - NX2139A schematic for the demoboard layout
R7
1M
VCC
C7
10u
LDOOUT
R10
7.5k
5V
VCC
R6
10
C15
330p
R4
2.2
U1
NX2139/MLPQ-16/3x3
DH 12
BST 13
SW 11
DL 8
LIN_DRV
7
VOUT 1
FB 3
EN
15
VCC
2
VCCP
9
PGOOD
4
OCP 10
LIN_FB
6
TON 16
GND
17
LIN_PGOOD
5
LIN_EN
14
R3
10k
GND
R5
10.5k
LDOIN
C3
10u
CIN2
4.7u/25V
M3
SI4800
1
4
8
5
6
72
3
CO1
2R5TPE330MC
C18
1n
R17
20k
BUS
1
5V
1
C19
33n
R18
50
R11
100k
CIN3
4.7u/25V
C6
1n
LDOOUT
R15
2.2
C9
1.5n
CIN1
10u/25V
R2
0
C2
1u
VOUT
Lo
DO5010H-152
1 2
LDODRV
LDOIN
OUT
R19
7.5k
C16
1u
R20
7.5k
C17
1u
CO2
4.7u/6.3V
M1
IRF7807
1
4
8
5
6
72
3
M2
AO4714
1
4
8
5
6
72
3
R8
100k
BUS
NX2139A
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Rev. 2.4
06/13/12
Demoboard Layout
Figure 15 Top layer
Figure 16 Ground layer
NX2139A
20
Rev. 2.4
06/13/12
Figure 18 Bottom layer
Figure 17 Power layer
NX2139A
21
Rev. 2.4
06/13/12
MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS
SYMBOL
NAME MIN MAX MIN MAX
A0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3
B0.180 0.300 0.007 0.012
D2.950 3.050 0.116 0.120
D2 1.600 1.750 0.063 0.069
E2.950 3.050 0.116 0.120
E2 1.600 1.750 0.063 0.069
e
L0.325 0.450 0.013 0.018
M
0.203REF
0.50BSC
1.5REF
Dimensions In Inches
0.008REF
0.50BSC
0.059REF
Dimensions In Millimeters