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availability and additional information.
MOS INTEGRATED CIRCUIT
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
PRELIMINARY DATA SHEET
Document No. E0136E30 (Ver. 3.0)
Date Published October 2001 (K)
Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic
random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank),
respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
• Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• x4, x8, x16 organization
• Byte write control (x4, x8) by DM
• Byte write control (x16) by LDM and UDM
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• Maximum clock frequency up to 133 MHz
• SSTL_2 compatible with all signals
• 4,096 refresh cycles/64 ms
• 66-pin Plastic TSOP (II) (10.16 mm (400))
• Burst termination by Precharge command and Burst stop command
Preliminary Data Sheet E0136E30
2
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Ordering Information
Part Number Organization
(word x bit x bank)
Clock frequency
MHz (MAX.)
Package
EDD1204ALTA-7A 8M x 4 x 4 133 66-pin Plastic TSOP (II)
EDD1204ALTA-75 133 (10.16 mm (400))
EDD1204ALTA-1A 100
EDD1208ALTA-7A 4M x 8 x 4 133
EDD1208ALTA-75 133
EDD1208ALTA-1A 100
EDD1216ALTA-7A 2M x 16 x 4 133
EDD1216ALTA-75 133
EDD1216ALTA-1A 100
Preliminary Data Sheet E0136E30 3
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Part Number
ELPIDA Memory
Density & Bank
12: 128M/4 Bank
Bit Organization
4: x4
8: x8
16: x16
Interface
A: SSTL_2
Mask Revision
Package
TA: TSOP (II)
Speed
7A: 7.5 ns (133 MHz)
75: 7.5 ns (133 MHz)
1A: 10 ns (100 MHz)
Function
D: DDR (I)
Material Type
D: Mono
E D D 12 04 A L TA - 7A
Preliminary Data Sheet E0136E30
4
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Pin Configurations
/xxx indicates active low signal.
[EDD1204ALTA]
66-pin Plastic TSOP (II) (10.16 mm (400))
8M word x 4 bit x 4 bank
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
V
REF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A9, A11 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ3 : Data inputs/outputs
DQS : Data strobe
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DM : DQ write mask enable
VDD : Supply voltage
VSS : Ground
VDDQ : Supply voltage for DQ and DQS
VSSQ : Ground for DQ and DQS
VREF : Input reference
NC : No connection
Preliminary Data Sheet E0136E30 5
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
[EDD1208ALTA]
66-pin Plastic TSOP (II) (10.16 mm (400))
4M word x 8 bit x 4 bank
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
NC
V
REF
V
SS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A9 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ7 : Data inputs/outputs
DQS : Data strobe
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DM : DQ write mask enable
VDD : Supply voltage
VSS : Ground
VDDQ : Supply voltage for DQ and DQS
VSSQ : Ground for DQ and DQS
VREF : Input reference
NC : No connection
Preliminary Data Sheet E0136E30
6
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
[EDD1216ALTA]
66-pin Plastic TSOP (II) (10.16 mm (400))
2M word x 16bit x 4 bank
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A8 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ15 : Data inputs/outputs
LDQS, UDQS : Data strobe
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
LDM, UDM : DQ write mask enable
VDD : Supply voltage
VSS : Ground
VDDQ : Supply voltage for DQ, LDQS and UDQS
VSSQ : Ground for DQ, LDQS and UDQS
VREF : Input reference
NC : No connection
Preliminary Data Sheet E0136E30 7
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Block Diagram
A0 - A11, BA0, BA1
/CS
/RAS
/CAS
/WE
Command Decoder
Input & Output Buffer
Latch Circuit
Data Control Circuit
Column Decoder
Row Decoder
Memory Cell Array
Bank A
Sense Amp.
Bank B
Bank C
Bank D
Control Logic
Column
Address
Buffer
and
Burst
Counter
Row
Address
Buffer
and
Refresh
Counter
Mode
Register
Clock
Generator
DQ
CLK
/CLK
CKE
DQS
DM
DLL
CLK, /CLK
Preliminary Data Sheet E0136E30
8
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
CONTENTS
1. Input/Output Pin Function....................................................................................................................................10
2. Commands ............................................................................................................................................................11
3. Simplified State Diagram......................................................................................................................................15
4. Truth Table ............................................................................................................................................................16
4.1 Command Truth Table...............................................................................................................................16
4.2 DM Truth Table..........................................................................................................................................16
4.3 CKE Truth Table ........................................................................................................................................16
4.4 Operative Command Table Note1 ................................................................................................................17
4.5 Command Truth Table for CKE .................................................................................................................20
5. Initialization ...........................................................................................................................................................21
6. Programming the Mode Register.........................................................................................................................22
7. Mode Register .......................................................................................................................................................23
7.1 Burst Length and Sequence ......................................................................................................................24
8. Address Bits of Bank-Select and Precharge ......................................................................................................25
9. Precharge ..............................................................................................................................................................26
9.1 Read to Precharge Command Interval ......................................................................................................26
9.2 Write to Precharge Command Interval ......................................................................................................27
10. Auto Precharge ...................................................................................................................................................28
10.1 Read with Auto Precharge.......................................................................................................................28
10.2 Write with Auto Precharge.......................................................................................................................29
11. Read/Write Command Interval...........................................................................................................................30
11.1 Read to Read Command Interval ............................................................................................................30
11.2 Write to Write Command Interval ............................................................................................................31
11.3 Write to Read Command Interval ............................................................................................................32
11.4 Read to Write Command Interval ............................................................................................................33
Preliminary Data Sheet E0136E30 9
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
12. Burst Termination ...............................................................................................................................................34
12.1 Burst Stop Command in Read Cycle .......................................................................................................34
12.2 Terminating a Burst Read Cycle by Precharge Command......................................................................35
12.3 Terminating a Burst Write Cycle by Precharge Command......................................................................36
13. Electrical Specifications.....................................................................................................................................37
13.1 Absolute Maximum Ratings .....................................................................................................................37
13.2 Recommended Operating Conditions......................................................................................................37
13.3 Pin Capacitance (TA = 25 °C, f = 100 MHz) .............................................................................................37
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) ...........................38
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) ...........................39
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)...............................39
13.6.1 Test Conditions .........................................................................................................................39
13.6.2 Timing Diagram .........................................................................................................................40
13.6.3 Synchronous Characteristics.....................................................................................................41
13.6.4 Synchronous Characteristics Example......................................................................................42
13.6.5 Asynchronous Characteristics...................................................................................................42
14. Package Drawing ................................................................................................................................................74
15. Recommended Soldering Conditions ...............................................................................................................75
16. Revision History..................................................................................................................................................76
Preliminary Data Sheet E0136E30
10
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
1. Input/Output Pin Function
Pin name Input/Output Function
CLK, /CLK Input CLK and /CLK are the master clock inputs. The timing reference point for the differential
clock is when CLK and /CLK cross.
All control and address inputs except for DQ and DM are latched by a rising edge of CLK.
By both of rising and falling edges of CLK, output DQ and DQS are validated.
CKE Input CKE controls power down mode. When the EDD12xxALTA is not in burst mode and CKE
is negated, the device enters power down mode and deactivates internal clock signals,
input buffers and output drivers. During power down mode, CKE must remain low.
/CS Input /CS low starts a command input cycle. When /CS is high, commands are ignored but the
current operations will be continued.
/RAS, /CAS,
/WE
Input As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in
conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Refer to
the command table.
A0 – A11 Input Row address is determined by A0 - A11 at the rising edge of CLK in active command
cycle.
It does not depend on the bit organization.
Column address is determined by A0 - A9, A11 at the rising edge of CLK in read or write
command cycle. It depends on the bit organization: A0 - A9, A11 for x4 device, A0 - A9
for x8 device, A0 - A8 for x16 device.
A10 defines precharge mode. When A10 is high in precharge command cycle, all banks
are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, precharge starts automatically after the
burst access.
BA0, BA1 Input BA0, BA1 are bank select signals. In command cycle, BA0 and BA1 low select Bank A,
BA0 high and BA1 low select bank B, BA0 low and BA1 high select bank C and then BA0
and BA1 high select bank D.
DQ0 – DQ15 Input/Output DQ pins have the same function as I/O pins on conventional DRAMs.
DQS, LDQS,
UDQS
Input/Output Active on the both edges for data input and output.
DM, LDM, UDM Input DM's are latched by both of rising and falling edges of the DQS. In write mode, DM's
control byte mask. Unlike regular SDRAMs, DM's do not control read operation.
VREF Input VREF is reference voltage for SSTL input buffers.
VDD, VDDQ, VSS,
VSSQ
(Power Supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply
pins for the output buffers.
Preliminary Data Sheet E0136E30 11
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
2. Commands
Extended mode register set command
(/CS, /RAS, /CAS, /WE Low)
The EDD12xxALTA
has an extended mode register that defines enabling or
disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data
input pins.
After power on, the extended mode register set command must be executed for
enabling or disabling DLL.
The extended mode register can be set only when all banks are in idle state.
During tMRD, the EDD12xxALTA
can not accept any other commands.
Fig.1 Extended mode register
set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA1
BA0
Mode register set command
(/CS, /RAS, /CAS, /WE Low)
The EDD12xxALTA has a mode register that defines how the device operates.
In this command, A0 through A11, BA0 and BA1 are the data input pins.
After power on, the mode register set command must be executed to initialize the
device.
The mode register can be set only when all banks are in idle state.
During tMRD, the EDD12xxALTA
can not accept any other commands.
Fig.2 Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The EDD12xxALTA
has four banks, each with 4,096 rows.
This command activates the bank and the row address selected by BA0 and
BA1, and by A0 through A11 respectively.
This command corresponds to a conventional DRAM's /RAS falling.
Fig.3 Bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Row
Row
Preliminary Data Sheet E0136E30
12
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Precharge command
(/CS, /RAS, /WE= Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0, BA1
and A10. When A10 is High, all banks are precharged, regardless of BA0 and
BA1.
When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the EDD12xxALTA can't accept the activate command to
the precharging bank during tRP (precharge to activate command period).
This command can terminate the current burst operation.
This command corresponds to a conventional DRAM's /RAS rising.
Fig.4 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Precharge select)
A10
BA0, BA1
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
This command begins the burst read operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
Read data is available after /CAS latency requirements which have been met.
And it is synchronized with DQS.
Fig.5 Read command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select)
Col.
A10
BA0, BA1
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
This command begins burst write operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
Write data must be input by DQ0 through DQ15. Byte mask data must be input
by DM, LDM, and UDM. Both data must be synchronized with DQS that is
inputted after this command.
Fig.6 Write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select)
Col.
A10
BA0, BA1
Preliminary Data Sheet E0136E30 13
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
bank activate command.
During tRFC (refresh command to refresh or activate command period), the
EDD12xxALTA cannot accept any other command.
Fig.7 CBR (auto) refresh
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low.
When CKE goes high, the EDD12xxALTA will exit the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.8 Self refresh entry command
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current read burst operation.
Fig.9 Burst stop command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Preliminary Data Sheet E0136E30
14
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command.
This command doesn't begin or terminate any operation.
Fig.10 No operation
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Preliminary Data Sheet E0136E30 15
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
3. Simplified State Diagram
WRITA
PRE/PALL
PRE/PALL
READA
READ
BST
PRE (Precharge termination)
PRE (Precharge termination)
ACT
MRS, EMRS REF
PWDN
PDEX
SELF
IDLE
Mode
Register
Set
CBR (auto)
Refresh
BANK
ACTIVE
Self
Refresh
Power
Down
Precharge
READ
READA
POWER
ON
WRIT READ
Automatic sequence
Manual input
READ
Self
Refresh
Recovery
Bank
Activating
SREX
READA
READA
(t
RP
)
(Burst end)
(tWR/tDAL)
(t
WR
)
(Burst end)
(t
MRD
)(t
RFC
)
WRITA
WRIT
PWDN
PDEX
Preliminary Data Sheet E0136E30
16
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
4. Truth Table
4.1 Command Truth Table
Function Symbol CKE /CS /RAS /CAS /WE Address
n-1 n BA0 BA1 A10 A0-9,A11
Device deselect DESL H x H x x x x x x
No operation NOP H x L H H H x x x
Burst stop BST H x L H H L x x x
Read READ H x L H L H V L V
Read with auto precharge READA H
Write WRIT H x L H L L V L V
Write with auto precharge WRITA H
Bank active ACT H x L L H H V
Prechrage select bank PRE H x L L H L V L x
Precharge all banks PALL x H x
Mode register set MRS H x L L L L L L L V
Extended mode register set EMRS H L L V
4.2 DM Truth Table
CKE DM Function Symbol
n-1 n U L
Data write enable ENB H x L
Data mask MASK H x H
Upper byte write enable ENBU H x L x
Lower byte write enable ENBL H x x L
Upper byte write inhibit MASKU H x H x
Lower byte write inhibit MASKL H x x H
4.3 CKE Truth Table
Current State Function Symbol CKE /CS /RAS /CAS /WE Address
n-1 n
Idle CBR (auto) refresh command REF H H L L L H x
Idle Self refresh entry SELF H L
Self refresh Self refresh exit SREX L H H x x x x
L H H x x
Idle Power down entry PWDN H L H x x x x
L H H x x
Bank(s) active Power down entry PWDN H L H x x x x
L H H x x
Power down Power down exit PDEX L H H x x x x
L H H x x
Remark H = High level, L = Low level, V = Valid, x = High or Low level (Don't care)
Preliminary Data Sheet E0136E30 17
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
4.4 Operative Command Table Note1
(1/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Idle H x x x x DESL Nop or Power down
L H H H x NOP Nop or Power down
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT Bank activating
L L H L BA, A10 PRE/PALL Nop 3
L L L H x REF/SELF CBR (auto) refresh or Self refresh 4
L L L L Op-Code MRS Mode register set 4
L L L L Op-Code EMRS Extended mode register set 4
Row active H x x x x DESL Nop
L H H H x NOP Nop
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA Begin read/read with AP
L H L L BA, CA, A10 WRIT/WRITA Begin write/write with AP
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL Precharge/Precharge all banks 5
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Read H x x x x DESL Nop (Row active after burst end)
L H H H x NOP Nop (Row active after burst end)
L H H L x BST terminate burst, Row active 6
L H L H BA, CA, A10 READ/READA terminate burst, Begin new read/
read with AP
6
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL terminate burst,
Precharge/Precharge all banks
6
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Write H x x x x DESL Nop (Row active after tWR)
L H H H x NOP Nop (Row active after tWR)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA terminate burst, Begin read/read with AP 6
L H L L BA, CA, A10 WRIT/WRITA terminate burst, Begin new write/
write with AP
6
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL terminate burst, Precharge/Precharge all
banks
6
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Preliminary Data Sheet E0136E30
18
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
(2/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Read with auto H x x x x DESL Nop (Precharge after burst end)
precharge L H H H x NOP Nop (Precharge after burst end)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Write with H x x x x DESL Nop (Idle after tDAL)
auto precharge L H H H x NOP Nop (Idle after tDAL)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Precharge H x x x x DESL Nop (Idle after tRP)
L H H H x NOP Nop (Idle after tRP)
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL Nop (Idle after tRP) 3
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Row activating H x x x x DESL Nop (Row active after tRCD)
L H H H x NOP Nop (Row active after tRCD)
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Preliminary Data Sheet E0136E30 19
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
(3/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Write recovering H x x x x DESL Nop (Row active after tWR)
L H H H x NOP Nop (Row active after tWR)
L H H L x BST Nop (Row active after tWR)
L H L H BA, CA, A10 READ/READA Begin read/read with AP
L H L L BA, CA, A10 WRIT/WRITA Begin new write/write with AP
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Write recovering H x x x x DESL Nop (Idle after tDAL)
with auto precharge L H H H x NOP Nop (Idle after tDAL)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
L L L H x REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
L L L L Op-Code EMRS ILLEGAL
Refresh H x x x x DESL Nop (Idle after tRFC)
L H H H x NOP Nop (Idle after tRFC)
L H H L x BST Nop (Idle after tRFC) 2
L H L x x READ/WRIT ILLEGAL 2
L L H x x ACT/PRE/PALL ILLEGAL 3
L L L x x REF/SELF/MRS/E
MRS
ILLEGAL
Mode register H x x x x DESL Nop (Idle after tMRD)
accessing L H H H x NOP Nop (Idle after tMRD)
L H H L x BST ILLEGAL 2
L H x x x READ/WRIT ILLEGAL 2
L L x x x ACT/PRE/PALL/R
EF/SELF/MRS/EM
RS
ILLEGAL 2
Remark H = High level, L = Low level, x = High or Low level (Don't care),
BA = Bank address, RA = Row address, CA = Column address, A10 = Precharge control address,
Op-Code = Operand code, Nop = No operation, AP = Auto precharge,
ILLEGAL = Device operation and/or data-integrity are not guaranteed
Notes 1. All entries assume that CKE is active (High level) during the preceding clock cycle and the current clock
cycle.
2. ILLEGAL to bank in specified states; function may be legal in the bank indicated by BA0, BA1 depending on
the state of that bank.
3. Nop to bank precharging or in idle state. May precharge bank indicated by BA0, BA1.
4. ILLEGAL if any bank is not idle.
5. ILLEGAL if tRAS is not satisfied.
6. Must satisfy command interval and/or burst terminate condition.
Preliminary Data Sheet E0136E30
20
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
4.5 Command Truth Table for CKE
Current State CKE /CS /RAS /CAS /WE Add Command Action Notes
n-1 n
Self refresh H x x x x x x ILLEGAL(Impossible)
L H H x x x x SREX Exit S.R, self refresh recovery 2
L H H x x
L L x x x x x Maintain self refresh
Self refresh recovery H H H x x x x DESL Nop (Idle after tRC)
H H L H H H x NOP Nop (Idle after tRC)
H L x x x x x ILLEGAL
L x x x x x x ILLEGAL (Impossible)
Power down H x x x x x x ILLEGAL (Impossible)
L H H x x x x PDEX Exit power down, Idle
L H H x x
L L x x x x x Maintain power down
All banks idle H H V V V V x Refer to operative command table
H L H x x x x PWDN Power down entry 1
H L L H H H x PWDN Power down entry 1
H L L x x L x ILLEGAL
H L L H L x x ILLEGAL
H L L L H x x ILLEGAL
H L L L L H x SELF Self refresh entry 1
L x x x x x x Power down
Row active H x x x x x x Refer to operative command table
L x x x x x x Power down 1
Any state except H H V V V V V Refer to operative command table
listed above H L x x x x x ILLEGAL
L x x x x x x ILLEGAL (Impossible)
Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid,
Add = Address (A0 - A11, BA0, BA1),
ILLEGAL = Device operation and/or data-integrity are not guaranteed
Notes 1. Self refresh can be entered only from all banks idle state.
Power down can be entered only from all banks idle or row active state.
2. CKE low to high transition will re-enable CLK and other inputs asynchronously.
A Minimum setup time must be satisfied before any command other than exit.
Preliminary Data Sheet E0136E30 21
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
5. Initialization
The EDD12xxALTA is initialized in the power-on sequence according to the following.
(1) Power must first be applied to VDD, then VDDQ, and finally to VREF. VTT must be applied.
(2) Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS
output will be in Hi-Z state.
(3) To stabilize internal circuits, when power is applied a 100
µ
s or longer pause must precede any signal toggling.
(4) After the pause, all banks must be precharged using precharge command. The precharge all banks command is
convenient.
(5) EMRS command must be performed to enable or disable DLL. Then MRS command must be applied to reset
DLL. After this MRS command additional 200 cycles are required before read command.
(6) All banks must be precharged using precharge command again. Then two or more CBR (auto) refresh command
must be performed.
(7) After the refresh the mode register can be programmed by MRS command.
Case 1: MRS after the REF
CLK
Command REF MRS
t
RP
t
MRD
t
RFC
t
RFC
PALL REF
Any
Command
t
MRD
DLL
enable / disable DLL reset
CKE
Min. 200 cycles before Read command
t
MRD
MRSEMRSPALL
Minimum 2 REF cycles must be performed.
Remark Two refresh commands may be follow the first MRS command.
Preliminary Data Sheet E0136E30
22
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0
as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has five fields;
Option : A11 through A9, A7
DLL reset : A8
/CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be issued during tMRD.
/CAS Latency
/CAS latency is the critical parameter. It tells how many clocks must elapse before the data is available.
The value is determined by the frequency of the clock and the speed grade of the device.
Burst Length
Burst length is the number of words that will be output or input in read or write cycle. After read burst is completed,
the output bus becomes Hi-Z.
The burst length is programmable as 2, 4 and 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data is addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen depends on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing.
7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both
sequences support bursts of 2, 4 and 8.
The extended mode register has two fields;
Option : A11 through A1
DLL enable : A0
Preliminary Data Sheet E0136E30 23
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
7. Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vender specific
x x x x x 0 1 V V V V V V V
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 DLL Extended mode register set
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register set
0 0 0 0 0 DLL 0 LTMODE WT BL
Remark V = Valid, x = Don't care
/WE
/CAS
/RAS
/CS
CKE
CLK
A0 - A11,
BA0, BA1
Mode register set timming
Bit 8 DLL
0 Normal
1 Reset
Bit 0 DLL
0 Enable
1 Disable
Bit 2 - Bit 0 WT = 0 WT = 1
000 R R
001 2 2
Burst 010 4 4
Length 011 8 8
100 R R
101 R R
110 R R
111 R R
Wrap Bit 3 Mode
Type 0 Sequential
1 Interleave
Bit 6 - Bit 4 /CAS Latency
000 R
001 R
Latency 010 2
Mode 011 R
100 R
101 R
110 2.5
111 R
Remark R: Reserved
Preliminary Data Sheet E0136E30
24
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
7.1 Burst Length and Sequence
[Burst Length = Two]
Starting Address
(column address A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
0 0, 1 0, 1
1 1, 0 1, 0
[Burst Length = Four]
Starting Address
(column address A1 - A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
00 0, 1, 2, 3 0, 1, 2, 3
01 1, 2, 3, 0 1, 0, 3, 2
10 2, 3, 0, 1 2, 3, 0, 1
11 3, 0, 1, 2 3, 2, 1, 0
[Burst Length = Eight]
Starting Address
(column address A2 - A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Preliminary Data Sheet E0136E30 25
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
8. Address Bits of Bank-Select and Precharge
[Activate Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row Address
BA1 BA0 Result
0 0 Select Bank A, ''Activate'' command
0 1 Select Bank B, ''Activate'' command
1 0 Select Bank C, ''Activate'' command
1 1 Select Bank D, ''Activate'' command
[Precharge Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row Address
BA1 BA0 A10 Result
0 0 0 Precharge Bank A
0 1 0 Precharge Bank B
1 0 0 Precharge Bank C
1 1 0 Precharge Bank D
x x 1 Precharge All Banks
Remark x = Don't care
[Read/Write Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column Address
A10 Result
0 Disables Auto-Precharge
1 Enables Auto-Precharge
BA1 BA0 Result
0 0 Enables Read/Write commands for Bank A
0 1 Enables Read/Write commands for Bank B
1 0 Enables Read/Write commands for Bank C
1 1 Enables Read/Write commands for Bank D
Preliminary Data Sheet E0136E30
26
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
9. Precharge
9.1 Read to Precharge Command Interval
The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is
issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The
parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
/CAS latency = 2 : (burst length/2) clocks after the read command is issued.
/CAS latency = 2.5 : (burst length/2) clocks after the read command is issued.
CLK
T0 T2T1 T3 T4 T5
Burst length = 4
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(Must satisfy tRAS)
PRE
PRE
Hi-Z
Hi-Z
DQS
DQS
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30 27
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
9.2 Write to Precharge Command Interval
In order to write all burst data to the memory cell correctly, the asynchronous parameter tWR must be satisfied. The
tWR specification defines the earliest time that a precharge command can be issued.
CLK
Burst length = 4
Q1 Q2 Q3
WRITE
DQ
Command
Q4
/CAS latency = 2, 2.5
/CLK
DM
(Must satisfy tRAS)
PRE
Hi-Z
DQS Preamble Postamble
tWR
T0 T2T1 T3 T4 T5
Preliminary Data Sheet E0136E30
28
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
10. Auto Precharge
During a read or write command cycle, A10 controls auto precharge. A10 high in the read or write command (read
with auto precharge command or write with auto precharge command), auto precharge is selected and begin
automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge starts, an activate command to the bank can be issued after tRP is satisfied.
In write cycle, tDAL must be satisfied to issue the next activate command to the bank being precharged.
10.1 Read with Auto Precharge
When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from
a read with auto precharge command.
CLK
Burst length = 4
Q1 Q2 Q3
READA
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READA
Burst length / 2 cycle
(When t
RAS
is satisfied)
ACT
ACT
Hi-Z
Hi-Z
t
RP
Auto precharge starts
Auto precharge starts
T0 T2T1 T3 T4 T5
Remark READA means Read with Auto Precharge command
Preliminary Data Sheet E0136E30 29
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
10.2 Write with Auto Precharge
When a write with auto precharge command is issued, the auto precharge begins after tWR is satisfied.
CLK
Burst length = 2
WRITEA
DQ
Command
DQS
/CAS latency = 2, 2.5
/CLK
CKE
ACT
t
WR
(When t
RAS
is satisfied)
D2
t
RP
Auto precharge starts
T0 T2T1 T3 T4 T5 T6
D1
Remark WRITEA means Write with Auto Precharge command
Preliminary Data Sheet E0136E30
30
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
11. Read/Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new read command is issued, it will be effective after /CAS latency, even if the previous
read operation is not completed. READ will be interrupted by another READ.
The interval between commands is minimum 1 cycle. Each read command can be issued in every clock without any
restriction.
CLK
Burst length = 4
QB1 QB2 QB3
READ A
DQ
Command
QB4
DQ
Command
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ A
1 cycle
READ B
READ B
Hi-Z
Hi-Z
QA1 QA2
QB1 QB2 QB3
QA1 QA2
T0 T2T1 T3 T4 T5 T6
QB4
Preliminary Data Sheet E0136E30 31
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
11.2 Write to Write Command Interval
During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will
begin with new write command. WRITE will be interrupted by another WRITE.
The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without
any restriction.
CLK
Burst length = 4
WRITE A
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
1 cycle
DA1DQ DA2 DB1 DB2 DB3 DB4
WRITE B
T0 T2T1 T3 T4 T5
Preliminary Data Sheet E0136E30
32
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
11.3 Write to Read Command Interval
The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance
at least 1 cycle prior to the first output data.
The minimum time interval between the rising clock edge after the last input data and the read command is tWTR.
When the read command is issued, the invalid data from the burst write cycle must be masked by DM.
CLK
WRITE A
DQS
Command
/CAS latency = 2
/CLK
CKE
READ B
DQ DA1
DM
QB1 QB2 QB3 QB4
WRITE A
DQS
Command READ B
DQ DA1 DA2
DM
QB1 QB2
/CAS latency = 2.5
DQ and DQS : Input DQ and DQS : Output
DA2
t
WTR
QB3
T0 T2T1 T3 T4 T5 T6
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30 33
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
11.4 Read to Write Command Interval
To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid
data conflict. The data bus must be high impedance when the write command is issued.
When the write command is issued, any residual data from the burst read cycle must be terminated by the burst
stop command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 2 cycles prior to the
write command.
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8 Burst length = 8
T9
READ A
DQS
Command
/CAS latency = 2
/CLK
CKE
T10 T11
WRITE B
DQ QA1 QA2
T12 T13 T14
DB1 DB2
READ A
DQS
Command WRITE B
DQ QA1 QA4
/CAS latency = 2.5
DQ and DQS : Output DQ and DQS : Input
BST
BST
DB1 DB2
QA3 QA4
Hi-Z
Hi-Z
QA2 QA3
DB
DB
T0 T2T1 T3 T4 T5 T6
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30
34
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
12. Burst Termination
12.1 Burst Stop Command in Read Cycle
During a burst read cycle, when the burst stop command is issued at the rising edge of the clock (CLK), the burst
read data are terminated and the data bus goes to high impedance after the /CAS latency from the burst stop
command.
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8 Burst length = 8
T9
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
T10 T11
READ
(When tRAS is satisfied)
BST
BST
Hi-Z
Hi-Z
T0 T2T1 T3 T4 T5
Remark BST means Burst Stop command
Preliminary Data Sheet E0136E30 35
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
12.2 Terminating a Burst Read Cycle by Precharge Command
During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of
the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read
operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge
command. The precharge command can be issued after tRAS (MIN.) is satisfied.
CLK
Burst length = Full page
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(When t
RAS
is satisfied)
PRE
PRE
Hi-Z
Hi-Z
T0 T2T1 T3 T4 T5
Preliminary Data Sheet E0136E30
36
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
12.3 Terminating a Burst Write Cycle by Precharge Command
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same banks. In order to write the last input data to the memory cell correctly, tWR (MIN.) must be satisfied. When
the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle
must be masked by DM.
CLK
Burst length = 8
WRITE
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
tWR
PRE
DQ D1 D2
DM
T0 T2T1 T3 T4 T5
Preliminary Data Sheet E0136E30 37
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100
µ
s and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
13.1 Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to VSS V
DD, VDDQ −0.5 to +3.6 V
Voltage on any pin relative to VSS V
T −0.5 to +3.6 V
Short circuit output current IO 50 mA
Power dissipation PD 1 W
Storage temperature Tstg −55 to + 125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
13.2 Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VDD 2.3 2.5 2.7 V
Supply voltage for DQ, DQS VDDQ 2.3 2.5 2.7 V
Input reference voltage VREF 0.49 × VDDQ 0.51 × VDDQ V
Termination voltage VTT V
REF − 0.04 VREF V
REF + 0.04 V
High level dc input voltage VIH (DC) VREF + 0.18 VDD + 0.3 V
Low level dc input voltage VIL (DC) −0.3 VREF − 0.18 V
Input differential voltage (CLK and /CLK) VID (DC) 0.36 VDDQ + 0.6 V
Input crossing point voltage (CLK and /CLK) VIX 0.5 × VDDQ–0.2 0.5 × VDDQ+0.2 V
Operating ambient temperature TA 0 70 °C
13.3 Pin Capacitance (TA = 25 °
°°
°C, f = 100 MHz)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11, BA0, BA1 2.5 3.5 pF
C
I2 CLK, /CLK, CKE, /CS, /RAS, /CAS, /WE 2.5 3.5 pF
Data input/output capacitance CIO1 DQS, LDQS, UDQS 4 5 pF
C
IO2 DQ0 - DQ15, DM, LDM, UDM 4 5 pF
Preliminary Data Sheet E0136E30
38
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Maximum Parameter Symbol Test condition /CAS
latency
Grade
x4 x8 x16
Unit Notes
-7A 115 mA 1
-75 115
Operating current
(ACT-PRE)
IDD0 tRC = tRC(MIN.), tCK = tCK (MIN.), One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
-1A 100
CL = 2 -7A 140 150 170 mA
-75 130 140 160
-1A 130 140 160
CL = 2.5 -7A 150 160 180
-75 150 160 180
Operating current
(ACT-READ-PRE)
IDD1 tRC = tRC(MIN.), tCK = tCK (MIN.), One
bank, Active-read-precharge,
IO = 0 mA, Burst length = 2,
Address and control inputs
changing once per clock cycle
-1A 140 150 170
Precharge power down
standby current
IDD2P CKE ≤ VIL(MAX.), tCK = tCK(MIN.),
All banks idle, Power down mode
2 mA
Idle standby current IDD2N CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All banks idle, Address and other control inputs
changing once per clock cycle
45 mA
Active power down
standby current
IDD3P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active,
Power down mode
25 mA
Active standby current IDD3N /CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =
tRAS(MAX.), One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
65 mA
CL = 2 -7A 200 210 230 mA 2
-75 170 180 200
-1A 170 180 200
CL = 2.5 -7A 210 220 240
-75 210 220 240
Operating current
(Burst read)
IDD4R tCK = tCK(MIN.), Continuous burst
read, Burst length = 2, IO =
0mA, One bank active,
Address and control inputs
changing once per clock cycle
-1A 180 190 210
CL = 2 -7A 195 205 225 mA 2
-75 160 170 190
-1A 160 170 190
CL = 2.5 -7A 195 205 225
-75 195 205 225
Operating current
(Burst write)
IDD4W tCK = tCK(MIN.), Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
-1A 160 170 190
CBR (auto) refresh current IDD5 tRFC = tRFC(MIN.) -7A 250 mA
-75 250
-1A 220
Self refresh current IDD6 CKE ≤ 0.2 V 2 mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output
open.
Preliminary Data Sheet E0136E30 39
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition MIN. MAX. Unit Notes
Input leakage current II(L) Any input 0 V ≤ VIN ≤ VDD, all other pins not under
test = 0 V
−2 2
µ
A
Output leakage current IO(L) D
OUT is disabled, VO = 0 to VDDQ + 0.3 V −5 5
µ
A
Output high current IOH V
OUT = 1.95 V –15.2 mA
Output low current IOL V
OUT = 0.35 V 15.2 mA
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)
13.6.1 Test Conditions
Parameter Symbol MIN. MAX. Unit Notes
Input Reference voltage (Input timing measurement reference level) VREF 0.49 x VDDQ 0.51 x VDDQ V
Termination voltage (Output timing measurement reference level) VTT V
REF − 0.04 VREF + 0.04 V 1
High level ac input voltage VIH(ac) VREF + 0.31 V
Low level ac input voltage VIL(ac) VREF − 0.31 V
Input differential voltage (CLK and /CLK) VID(ac) 0.7 VDDQ + 0.6 V
Input signal slew rate SLEW 1 V/ns 2
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level.
2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing.
SLEW = (VIH(ac)-VIL(ac))/ ∆t
Output
R
T
= 50
Ω
C
LOAD
= 30 pF
V
TT
Preliminary Data Sheet E0136E30
40
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13.6.2 Timing Diagram
tCK
tDQSCK tDQSCK
tCH tCL
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Valid Valid
tRPRE
Valid
tAC
tAC
tQH tQH
tDQSQ
tRPST
tDQSCK
Valid Valid
Valid Valid
tDQSCK
Valid
tDQSQ
tDH
tDS tDH
tDS
tWPST
tDQSLtDQSH
tDSH
Valid Valid
tRPST
tAC
tAC tDQSQ tDQSQ
tQH tQH
t
WPRES
t
WPRE
tDQSS
CLK
DQS
(Output)
(CL = 2.5)
DQ
(Output)
(CL = 2.5)
/CLK
Command
(Input)
Address
(Input)
DQS
(Output)
(CL = 2)
DQ
(Output)
(CL = 2)
DQS
(Input)
tDQSS
(MIN.)
DQ and DM
(Input)
V
ID
(ac)
VTT
VTT
VTT
VTT
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
VREF
tDH
tDS tDH
tDS
tWPST
tDQSLtDQSH
tDSS
Valid Valid
t
WPRES
t
WPRE
tDQSS
DQS
(Input)
tDQSS
(MAX.)
DQ and DM
(Input)
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
+ 0.31 V
V
REF
- 0.31 V
V
REF
VREF
tRPRE
Preliminary Data Sheet E0136E30 41
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13.6.3 Synchronous Characteristics
Parameter Symbol -7A -75 1A Unit Note
MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time CL = 2.5 tCK 7.5 12 7.5 12 10 12 ns
CL = 2 7.5 12 10 12 10 12
CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.75 0.75 –0.8 0.8 ns
DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.75 0.75 –0.8 0.8 ns
DQS-DQ skew (for DQS and associated
DQ signals)
tDQSQ 0.5 0.5 0.6 ns
DQS-DQ skew (for DQS and all DQ
signals)
tDQSQA 0.5 0.5 0.6 ns
Data out low-impedance time from CLK,
/CLK
tLZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns
Data out high-impedance time from CLK,
/CLK
tHZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns
Half clock period tHP MIN.
(tCH, tCL)
MIN.
(tCH, tCL)
MIN.
(tCH, tCL)
ns
Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQ output hold time from DQS tQH t
HP –
0.75
t
HP –
0.75
t
HP – 1 ns
DQ and DM input setup time tDS 0.5 0.5 0.6 ns
DQ and DM input hold time tDH 0.5 0.5 0.6 ns
DQ and DM input pulse width (for each
input)
tDIPW 1.75 1.75 2 ns
Write preamble setup time tWPRES 0 0 0 ns
Write preamble tWPRE 0.25 0.25 0.25 tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Write command to first DQS latching
transition
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK
DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK
DQS falling edge to CLK setup time tDSS 0.2 0.2 0.2 tCK
DQS falling edge hold time from CLK tDSH 0.2 0.2 0.2 tCK
Address and control input setup time tIS 0.9 0.9 1.1 ns
Address and control input hold time tIH 0.9 0.9 1.1 ns
Address and control input pulse width tIPW 2.2 2.2 2.5 ns
Internal write to read command delay tWTR 1 1 1 t
CK
Preliminary Data Sheet E0136E30
42
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
13.6.4 Synchronous Characteristics Example
Symbol tCK =7.5 ns tCK =10 ns Unit
MIN. MAX. MIN. MAX.
tCH 3.4 4.1 4.5 5.5 ns
tCL 3.4 4.1 4.5 5.5 ns
tRPRE 6.75 8.25 9 11 ns
tRPST 3 4.5 4 6 ns
tWPRE 1.88 2.5 ns
tWPST 3 4.5 4 6 ns
tDQSS 5.6 9.4 7.5 12.5 ns
tDQSH 2.63 3.5 ns
tDQSL 2.63 3.5 ns
tDSS 1.5 2 ns
tDSH 1.5 2 ns
tWTR 7.5 10 ns
13.6.5 Asynchronous Characteristics
Parameter Symbol -7A -75 -1A Unit
MIN. MAX. MIN. MAX. MIN. MAX.
ACT to REF/ACT command period
(operation)
tRC 65 65 70 ns
REF to REF/ACT command period (refresh) tRFC 75 75 80 ns
ACT to PRE command period tRAS 45 120,000 45 120,000 50 120,000 ns
PRE to ACT command period tRP 20 20 20 ns
ACT to READ/WRITE delay tRCD 20 20 20 ns
ACT(one) to ACT(another) command period tRRD 15 15 15 ns
Write recovery time tWR 2 2 2 CLK
Auto precharge write recovery time + precharge
time
tDAL 35 35 35 ns
Mode register set command cycle time tMRD 15 15 15 ns
Exit self refresh to command tXSNR 75 75 80 ns
Average periodic Refresh interval tREF1 15.6 15.6 15.6 µs
Preliminary Data Sheet E0136E30 43
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
AC Parameters for Read Timing 1 (Manual Precharge, Burst Length = 4, /CAS Latency = 2.5)
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t
RAS
t
RC
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BA0
t
IH
t
RP
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
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CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
tRCD
tIS
tCH tCL
tCK
t
IS
t
IH
L
Activate Command
for Bank A
Precharge Command
for Bank A
Read Command
for Bank A
Activate Command
for Bank A
tCK
tCL tCH
/CLK
t
IS
t
IH
DQS
DQ
;
;
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t
AC
t
DQSQ
;
;
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t
DQSQ
t
DQSQ
t
DQSQ
t
AC
t
AC
t
AC
;
t
QH
t
QH
t
QH
t
QH
t
DQSCK
t
DQSCK
t
DQSCK
t
DQSCK
t
RPRE
t
RPST
Hi-Z
VTT Hi-Z
VTT
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Preliminary Data Sheet E0136E30
44
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
AC Parameters for Read Timing 2 (Auto Precharge, Burst Length = 4, /CAS Latency = 2.5)
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t
RAS
t
RRD
t
RC
;
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BA0
tIH
;;
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
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;
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;
;
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
t
RCD
t
IS
t
CH
t
CL
t
CK
t
IS
t
IH
t
IS
t
IH
;;
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Activate Command
for Bank C
Activate Command
for Bank D
Bank C Read Command
with Auto Precharge
Activate Command
for Bank C
DQS
DQ
Hi-Z
V
TT
;
;
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;
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;
;
t
AC
t
DQSQ
;;
;;
;;
;;
t
DQSQ
t
DQSQ
t
DQSQ
t
AC
t
AC
t
AC
;;
t
QH
t
QH
t
QH
t
QH
t
DQSCK
t
DQSCK
t
DQSCK
t
DQSCK
t
RPRE
t
RPST
t
CK
t
CL
t
CH
/CLK
Auto Precharge
Start for Bank C
Hi-Z
V
TT
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Preliminary Data Sheet E0136E30 45
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Relationship between Frequency and Latency
Speed version -7A -75 -1A
Clock cycle time [ns] 7.5 7.5 7.5 10 10 10
Frequency [MHz] 133 133 133 100 100 100
/CAS latency 2.5 2 2.5 2 2.5 2
[tRCD] 3 3 3 2 2 2
/RAS latency (/CAS latency + [tRCD]) 5.5 5 5.5 4 4.5 4
[tRC] 9 9 9 7 7 7
[tRFC] 10 10 10 8 8 8
[tRAS] 6 6 6 5 5 5
[tRRD] 2 2 2 2 2 2
[tRP] 3 3 3 2 2 2
[tWR] 2 2 2 2 2 2
[tDAL] 5 5 5 4 4 4
[tMRD] 2 2 2 2 2 2
[tXSNR] 10 10 10 8 8 8
Preliminary Data Sheet E0136E30
46
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
AC Parameters for Write Timing (Burst Length = 8, /CAS Latency = 2.5)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
CKE
BA0
A10
ADD
DM
DQ Hi-Z
t
IS
t
IH
tRCD tRC
tRRD tRCD tRAS tRC
tWR tRP
t
IH
t
IS
t
IH
tIS
/CS
/RAS
/CAS
/WE
BA1
Auto Precharge
Start for Bank C
Activate
Command
for Bank C
Activate
Command
for Bank B
Bank B
Write Command
without Auto Precharge
Activate
Command
for Bank B
Bank C
Write Command
with Auto Precharge
Precharge
Command
for Bank B
Activate
Command
for Bank C
/CLK
tDS tDH
DQS
t
DQSS
tWPST
Hi-Z
V
TT
V
TT
t
WPRES
t
WPRE
tDAL
Preliminary Data Sheet E0136E30 47
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Mode Register Set (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
V
TT
t
MRD
ADDRESS KEY
t
RP
All Banks
Precharge
Command
Mode
Register Set
Command
Activate
Command
is valid
H
V
TT
DQS
/CLK
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30
48
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Power On Sequence and CBR (auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
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T2 T3 T4 T5T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Hi-Z
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Low level is necessary
2 refresh cycles are necessary
tRP tRFC
All Banks
Precharge
Command
is necessary
All Banks
Precharge
Command
is necessary
Mode
Register Set
Command
is necessary
Refresh
Command
is necessary
Activate
Command
Refresh
Command
is necessary
BA0
;;
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DQS Hi-Z
/CLK
More than 200 cycles are necessary before Read command
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tMRD
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VTT
VTT
tRFC
;;
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ADDRESS KEY
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ADDRESS KEY ADDRESS KEY
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Extended Mode
Register Set
Command
(DLL enable /
disable)
is necessary
Mode
Register Set
Command
(DLL reset)
is necessary
tMRD tMRD
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Preliminary Data Sheet E0136E30 49
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
/CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 2.5)
Only /CS signal needs to be issued at minimum rate
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
H
L
Hi-Z
L
BA0 L
RAa
QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
RAa CAa CAb
/CLK
DQS Hi-Z
V
TT
V
TT
Preliminary Data Sheet E0136E30
50
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Power Down Mode (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
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QAa3
CAa
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Hi-Z
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
t
IS
QAa1 QAa2
Activate
Command
for Bank A
Power Down
Mode Entry
Read
Command
for Bank A
Precharge
Command
for Bank A
PRECHARGE STANDBY
Power Down
Mode Exit
QAa4
/CLK
DQS Hi-Z
V
TT
V
TT
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
Preliminary Data Sheet E0136E30 51
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
CBR (auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
VTT
tRP
H
tRFC tRFC
Q1
Precharge
Command
is necessary
CBR (auto) Refresh CBR (auto) Refresh Activate
Command Read
Command
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
/CLK
Q2
VTT
DQS Hi-Z
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
52
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Self Refresh (Entry and Exit)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tm+2 Tk Tj Tj+1 Tj+2
tRP tXSNR tXSNR
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
Precharge
Command
is necessary
Self Refresh
Entry Self Refresh
Exit
Next Clock
Enable
Self Refresh
Entry
(or Activate Command)
Activate
Command
Self Refresh
Exit
Next Clock
Enable
/CLK
;
;
DQS Hi-Z
VTT
VTT
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30 53
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
VTT
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
QAa1 QAa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
;
;
;
H
RAd
RAa CAdCAcCAa RAdCAb
;;
;;
;;
;;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
QAd1 QAd2 QAd3 QAd4
DQS
VTT
/CLK
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30
54
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
H
RAa
RAa CAaCAcCAa RAaCAb
;;
;;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
RAa
;;
;;
/CLK
DM
DQ
VTT
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
QAd1 QAd2 QAd3 QAd4
DQS
VTT
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
Hi-Z
Hi-Z
Preliminary Data Sheet E0136E30 55
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
DM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
H
RDd
RDa CDdCDcCDa RDdCDb
RDa
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
/CLK
DQ
DQS VTT
DDd1 DDd2 DDd3 DDd4
VTT
Hi-Z
BA0
BA1
Preliminary Data Sheet E0136E30
56
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
H
RDd
RDa CDdCDcCDa RDdCDb
RDa
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
/CLK
BA0
DM
DQ
BA1
DQS VTT
DDd1 DDd2 DDd3 DDd4
VTT
Hi-Z
Preliminary Data Sheet E0136E30 57
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
Hi-Z
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
QDa1 QDa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5
H
RDb
RDa CDbCBaCDa RDbRBa
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
RBa
;
;
;
;
QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank D
QDb1 QDb2 QDb3 QDb4 QDb5 QDb6 QDb7 QDb8
DQS
Hi-Z
V
TT
V
TT
/CLK
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
58
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
Hi-Z
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
H
RBb
RBa CBbCAaCBa RBbRAa
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
RBa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;;
;;
;
;
;
;
;
;;
;;
RAa
;
;
;;
;
;;
;;
;
;
;
;
;
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
;
;
;
;
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 QBb1 QBb2 QBb3 QBb4 QBb5 QBb6
/CLK
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
DQS
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
V
TT
V
TT
Hi-Z
QBb7
Preliminary Data Sheet E0136E30 59
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
;
;
;
;
;
;
;
DAa5 DAa6
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8
H
RAa CAbCDaCAa RDa
;
;
;
;
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAb
RAb
;
;
;
;
DAa1 DAa2 DAa3 DAa4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
;
;
;
;
;
;
;
;
;
;
;
;
BA0
Hi-Z
BA1
/CLK
DQS Hi-Z
VTT
VTT
DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
60
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
L
H
RAa CAbCDaRDa
RAa RDa RAb
CAa RAb
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank D
Write
Command
for Bank A
A10
ADD
DM
DQ
BA0
Hi-Z
BA1
/CLK
DQS
Hi-Z
V
TT
V
TT
T22
DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8DAa1 DAa2 DAa3 DAa4 DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
Hi-Z
Preliminary Data Sheet E0136E30 61
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Read and Write (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
Hi-Z at the end of
wrap function
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
H
RAa CAcCAb
;
;
;
;
;
;;
;;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
CAa
;;
;;
RAa
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
Word Masking
/CLK
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 DAb1 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 QAc1 QAc2 QAc3 QAc4 QAc5 QAc6 QAc7 QAc8
DQS
Hi-Z
V
TT
V
TT
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
62
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Read and Write (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
H
RAa CAcCAb
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
CAa
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa
;
;
;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;
;
;
;
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
/CLK
DM
DQ
Word Masking
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 DAb1 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 QAc1 QAc2 QAc3
DQS
Hi-Z
V
TT
V
TT
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
QAc1 QAc2 QAc3
Preliminary Data Sheet E0136E30 63
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Interleaved Column Read Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
RAa RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
RDa
CAa
;
;
CDa CDb CDc CAb
;
;
;
;
;
;
;
;
CDd
;
;
;
;
;
;
;
;
Activate
Command
for Bank A Activate
Command
for bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
Read
Command
for Bank A
DQ
VTT
DQS
VTT
Dc4
Dc1 Dc2 Dc3
Db4
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Ab4
Ab1 Ab2 Ab3 Dd1 Dd2 Dd3 Dd4 Dd5 Dd6 Dd7 Dd8
/CLK
Hi-Z
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
64
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Interleaved Column Read Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
RDa
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAb
CDc
RDa CDaCAa
Activate
Command
for Bank A Activate
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A Precharge
Command
for Bank D
Precharge
Command
for Bank A
Read
Command
for Bank A
CDb
DQ
VTT
DQS
VTT
Dc4
Dc1 Dc2 Dc3
Db4
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Ab4
Ab1 Ab2 Ab3 Ab5 Ab6 Ab7 Ab8
/CLK
Hi-Z
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30 65
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Interleaved Column Write Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Hi-Z
H
RAa RBa
RAa RBa
CAa CBa CBb CBc CAb CBd
BA1
Activate
Command
for Bank A
Write
Command
for Bank A Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
/CLK
Aa1 Aa2 Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2 Bd3 Bd4
Ab1 Ab2
Bb1 Bb2
Aa5 Aa6 Aa7 Aa8 Ba3 Ba4 Bc3 Bc4 Bd5 Bd6 Bd7 Bd8
Ab3 Ab4
Bb3 Bb4
DQS Hi-Z
V
TT
V
TT
Preliminary Data Sheet E0136E30
66
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Hi-Z
H
RAa RBa
RAa CAb
CBc
RBa CBa CBbCAa CBd
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
BA1
Aa1 Aa2 Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2 Bd3 Bd4
Ab1 Ab2
Bb1 Bb2
Aa5 Aa6 Aa7 Aa8 Ba3 Ba4 Bc3 Bc4 Bd5 Bd6 Bd7 Bd8
Ab3 Ab4
Bb3 Bb4
DQS
/CLK
Hi-Z
V
TT
V
TT
T23
Preliminary Data Sheet E0136E30 67
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Auto Precharge after Read Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
H
;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;;
;;
;
;
;;
;
;
;;
;;
;
;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
RAc
;
;
;
;
;
;
RDa
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAbCAa RDbCDaRDa CAcCDb RAc
Activate
Command
for Bank A
Activate
Command
for Bank D
Bank A
Read Command
without Auto Precharge
Bank D
Read Command
with Auto Precharge
Activate
Command
for Bank D
Bank A
Read Command
with Auto Precharge
Auto Precharge
Start for Bank D Bank D
Read Command
with Auto Precharge
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank A
Bank A
Read Command
with Auto Precharge
V
TT
DQS
V
TT
/CLK
Hi-Z
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30
68
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Auto Precharge after Read Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
H
;
;
;
;
;
;
;;
;;
;;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAbCAa RDbCDaRDa CDb
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
Activate
Command
for Bank A
Activate
Command
for Bank D
Bank A
Read Command
without Auto Precharge
Bank D
Read Command
with Auto Precharge Activate
Command
for Bank D
Bank A
Read Command
with Auto Precharge
Auto Precharge
Start for Bank A Bank D
Read Command
with Auto Precharge
Auto Precharge
Start for Bank D
V
TT
DQS
V
TT
/CLK
Hi-Z
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30 69
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Auto Precharge after Write Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
Activate
Command
for Bank A Bank A
Write Command
without Auto Precharge
Activate
Command
for Bank D
Activate
Command
for Bank D
Bank D
Write Command
with Auto Precharge
Bank D
Write Command
with Auto Precharge
Bank A
Write Command
with Auto Precharge
Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A
Activate
Command
for Bank ABank A
Write Command
with Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
L
H
RDb RAcRDaRAa
RAa CAbCAa RDbCDaRDa CAcCDb RAc
T22
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ Hi-Z
BA1
/CLK
DQS Hi-Z
VTT
VTT
Preliminary Data Sheet E0136E30
70
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Auto Precharge after Write Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
H
RDbRAa
RAa CAbCAa RDbCDaRDa CDb
RDa
Activate
Command
for Bank A Bank A
Write Command
without Auto Precharge
Activate
Command
for Bank D Bank D
Write Command
with Auto Precharge
Bank A
Write Command
with Auto Precharge
Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A
Activate
Command
for Bank D Bank D
Write Command
with Auto Precharge
T22
BA0
DM
DQ Hi-Z
BA1
/CLK
DQS Hi-Z
V
TT
V
TT
Preliminary Data Sheet E0136E30 71
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
Byte Write Operation (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
LDM
Upper DQ
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
Hi-Z
Hi-Z
;;
;;
;;
;;
;;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
UDM
Lower DQ
Activate
Command Read
Command Lower Byte
not Write Upper Byte
not Write
/CLK
UDQS
LDQS
V
TT
V
TT
V
TT
V
TT
Hi-Z
Hi-Z
Read
Command
Lower Byte
not Write
Preliminary Data Sheet E0136E30
72
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RAb
CAa
;
;
RAa RAb
CAb
t
RP
t
RP
t
RAS
Activate
Command
for Bank A Activate
Command
for Bank A
Write
Command
for Bank A
PRE Command
Termination PRE Command
Termination
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
t
RAS
;
;
;
;
;
;
;
;
;
;
RAc
RAc
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
BA1
DQS
/CLK
Hi-Z
Write
Mask
DAa1 DAa2 DAa3 DAa4 QAb1 QAb2 QAb3 QAb4 QAb5 QAb6
Hi-Z
V
TT
V
TT
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Preliminary Data Sheet E0136E30 73
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa RAb
CAa
;
;
RAa RAb
CAb
t
RP
t
RP
t
RAS
Activate
Command
for Bank A Activate
Command
for Bank A
Write
Command
for Bank A
PRE Command
Termination
Precharge
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
PRE Command
Termination
;
;
;
;
;
;
t
RAS
Write
Mask
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAc
RAc
;
;
;
DAa1 DAa2 DAa3 DAa4 QAb1 QAb2 QAb3 QAb4 QAb5 QAb6
DQS
/CLK
Hi-Z
V
TT
V
TT
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
Preliminary Data Sheet E0136E30
74
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
14. Package Drawing
M
66 34
133
P
A
CN
B
M
D
L
K
J
H
I
G
Fdetail of lead end
NOTES
1. Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
S
S
E
R
L
S
ITEM
B
C
I
66-PIN PLASTIC TSOP (II) (10.16 mm (400))
A
D
E
F
G
H
J
K
L
MILLIMETERS
0.65 (T.P.)
0.865 MAX.
10.16±0.10
22.22±0.05
0.10±0.05
0.24
1.1±0.1
11.76±0.20
1.00
+0.08
−0.07
0.80±0.2
0.145+0.025
−0.015
0.50
0.12
M
P
R
3°+5°
−3°
0.25
0.60±0.15
S
0.10
N
S66G5-65-9LG-1
Preliminary Data Sheet E0136E30 75
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
15. Recommended Soldering Conditions
Please contact our sales offices for soldering conditions of EDD12xxALTA.
Type of Surface Mount Device
EDD12xxALTA: 66-pin Plastic TSOP (II) (10.16 mm (400))
Preliminary Data Sheet E0136E30
76
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
16. Revision History
Version / Page Description
Date
This edition Previous
edition
Type of
revision
Location
Ver. 1.0 / — — — —
April. 2001 — — — —
Ver. 2.0 / 27 27 Modification Figure of Write to Precharge Command Interval
May. 2001 29 29 Modification Figure of Write with Auto precharge
36 36 Modification Figure of Precharge Termination in Write Cycle
41 41 Modification tCK (CL = 2.5) (MIN.) : 8 ns to 10 ns
42 42 Modification tWR (MIN.) : 15/15/15 ns to 2/2/2 CLK
46 46 Modification AC Parameters for Write Timing
55 55 Modification Random Column Write (1/2)
56 56 Modification Random Column Write (2/2)
60 60 Modification Random Row Write (2/2)
65 65 Modification Interleaved Column Write Cycle (1/2)
66 66 Modification Interleaved Column Write Cycle (2/2)
69 69 Modification Auto Precharge after Write Burst (1/2)
70 70 Modification Auto Precharge after Write Burst (2/2)
Ver. 3.0 38 38 Addition DC Characteristics specification
October 2001 39 39 Modification VIH (ac) (MIN.): VREF + 0.35 to VREF + 0.31
VIL (ac) (MAX.): VREF + 0.35 to VREF - 0.31
41 41 Modification tHP (MIN.): tCH, tCL to MIN. (tCH, tCL)
42 42 Modification tWPRE (MIN.) (tCK = 7.5ns): 0.25 ns to 1.88 ns
42 42 Modification tDAL (MIN.): TBD to 35 ns
45 45 Modification [tDAL]: to 5/5/5/4/4/4
Preliminary Data Sheet E0136E30 77
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
EDD1204ALTA, EDD1208ALTA, EDD1216ALT
A
M01E0107
No part of this document may be copied or reproduced in any form or by any means without the prior
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Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
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express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
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If you export the products or technology described in this document that are controlled by the Foreign
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