178
TM
March 1997
HS-3182
ARINC 429 Bus Interface Line Driver Circuit
Features
• TTL and CMOS Compatible Inputs
• Adjustable Rise and Fall Times via Two External
Capacitors
• Program ma ble Output Differential Vol tage via VREF
Input
• Operates at Data Rates Up to 100 Kilobits/Sec
• Output Short Ci rcuit Proof and Contains Over-Voltage
Protection
• Outputs are Inhi bited (0 Volts) If DATA (A) and DATA
(B) Inputs are Both in the “Logic One” State
• DATA (A) and DATA (B) Signals are “AND’d” with
Clock and Sync Signals
• Full Military Temperature Range
Description
The HS-3182 is a monolithic dielectri cally i solated bipol ar diff er-
ential line driver designed to meet the specifications of AR INC
429. This Device is intended to be used with a companion chi p,
HS-3282 CMOS ARINC Bus Interface Circuit, which provides
the data formatting and processor interface function.
All logic inputs are TTL and CMOS compatible. In addition to
the DATA (A) and DATA (B) inputs, there are also inputs for
CLOCK and SYNC signals which are AND’d with the DATA
inputs. This feature enhances system performance and al lows
the HS-3182 to be used with devices other than the HS-3182.
Three power supplies are necessary to operate the
HS-3182: +V = +15V ± 10%, -V = -15V ± 10% , and V 1 = 5V
± 5%. VREF is used to pr ogram the dif feren tial o utput vol tage
swing such that VOUT (DIFF) = ± 2VREF. Typically, VREF =
V1 = 5V ± 5%, but a separate power supply may be used for
VREF wh ich should not ex ceed 6V.
The driver output impedance is 75Ω ± 20% at 25oC. Driver
output rise and fall times are independently programmed
through the use of two external capacitors connected to the
CA and CB inputs. Typical capacitor values are CA = CB =
75pF for high-speed operation (100KBPS), and CA = CB =
300pF for low-speed operation (12 to 14.5KBPS). The out-
puts are protected against over-voltage and short circuit as
shown in the Block Diagram. The HS-3182 is designed to
operate with a case temperature range of -55oC to +125oC,
or 0oC to +7 0 oC.
Pinouts HS-3182 (SBDIP )
TOP VIEW HS -318 2 (CLCC)
TOP VIEW
Ordering Information
PACKAGE TEMPERATURE
RANGE PART NUMBER PKG.
NO
SBDIP -40oC to +85oC HS1-3182-9+ D16.3
-55oC to +125oC HS1-3182-8 D16.3
SMD# -55oC to +125oC 5962-8687901EA D16.3
CLCC -55oC to +125oC HS4-3182-8 J28.A
SMD# -55oC to +125oC 5962-86879013A J28.A
TRUTH TABLE
SYNC CLK DATA (A) DATA (B) AOUT BOUT COMMENTS
X L X X 0V 0V Null
L X X X 0V 0V Null
H H L L 0V 0V Null
HH L H -V
REF +VREF Low
HH H L +V
REF -VREF High
H H H H 0V 0V Null
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
VREF
GND
SYNC
DATA (A)
CA
AOUT
GND
-V
V1
CLK
DATA (B)
CB
BOUT
NC
+V
NC
23
24
25
22
21
20
19
11
3 2 14
14 15 16 17 1812 13
28 27 26
10
5
6
7
8
9
NC
DATA (A)
NC
NC
CA
NC
NC
CLK
NC
DATA (B)
CB
NC
NC
NC
NC
AOUT
-V
GND
+V
NC
BOUT
SYNC
GND
NC
VREF
V1
NC
NC
FN2963.1
CA UTION: These devic es ar e sensitive to elect r ostatic dis charge; follow proper IC H andling Pr ocedures.
1-8 88-IN TE RSIL or 321- 72 4- 7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc . 2002. All Rights Re s erved
179
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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Block Diagram
Typical Application
NOTE: The rise and fall time of the outputs are set to ARINC specified values by CA and CB. Typical CA = CB = 75pF for high speed and
300pF for low speed operation. The output HI and low levels are set to ARINC specifications by VREF.
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
CURRENT
REGULATOR
DATA (A)
CLOCK
VREF
SYNC
DATA (B)
V1
(4)
(14)
(1)
(3)
(13)
(16)
(2)
(9) (5)
+V CA
OUTPUT
DRIVER
(A)
ROUT/2
ROUT/2
OUTPUT
DRIVER
(B)
GND
(8)
-V CB
(7) (12)
OVER-VOLTAGE
PROTECTION
FA
FB
CL
AOUT
BOUT
RL
(6)
(11)
HS-3182
ARINC DRIVER
CIRCUIT
16 LEAD DIP
GNDGND -V
DATA (B)
DATA (A)
SYNC
CLOCK
V1VREF CACB+V
AOUT
BOUT
TO BUS
(SEE
NOTE)
PIN NUMBER 10, 15 = NC
-15V
(7)(8)(2)
(9) +15V
CACB
(12)(5)
+5V
(1)(16)
(14)
(3)
PIN NUMBERS INDICATED BY ( )
HS-3282
CMOS ARINC
CIRCUIT
429D0
429D0
31
32
(4)
(13)
HS-3182
180
Absolute Maximum Ratings Thermal Information
Voltage Between +V and -V Terminals . . . . . . . . . . . . . . . . . . . 40V
V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Logic Input Voltage. . . . . . . . . . . . . . . . . . . . GND -0.3V to V1 +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . See Note 1
Output Over-Voltage Protection . . . . . . . . . . . . . . . . . . . See Note 2
Recom mend ed Operati ng Conditions
Operating Voltage
+V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V ± 10%
-V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V ± 10%
V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ± 5%
VREF (For ARINC 429). . . . . . . . . . . . . . . . . . . . . . . . . . .5V ± 5%
Operating Temperature Range
HS-3182-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
HS-3182-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Thermal Resistance (Typical) θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . 75oC/W 18oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 60oC/W 14oC/W
Storage Temperature Range . . . . . . . . . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
NOTES:
1. Heat sink may be required for 100K bits/s at +125oC and output short circuit at + 125oC.
2. The fuses used for output ov er-volt age protection may be blo wn by a fault at eac h output of greater than ± 6.5V relative to GND.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Performance Specifications
DC PARAMETER SYMBOL (NOTE 1)
CONDITIONS MIN MAX UNITS
Supply Current +V (Operating) ICCOP (+V) No Load (0-100K bits/s) - 16 mA
Supply Curren t -V (Operat ing) ICCOP (-V) N o Load (0-100K bits/s) -16 - mA
Sup ply Current V1 (Operating) ICCOP (V1) No Load (0-100K bits/s) - 975 µA
Sup ply Current VREF (Operating) ICCOP (VREF) No Load (0-100K bits/s) -1.0 - mA
Logic “1” Input Voltage VIH 2.0 - V
Logic “0” Input Voltage VIL -0.5V
Output Voltage High (Output to GND) VOH No Load ( 0- 100K bits/s) VREF
(-250mV) VREF
(+250mV)
Output Voltage Low (Output to GND) VOL No Load ( 0- 100K bits/s) -VREF
(-250mV) -VREF
(+250mV)
Output Voltage Null VNULL No Load (0- 100K bits/s) -250 +250 mV
Input Current (Input Low) IIL -20 - µA
Input Current (Input High) IIH -10µA
Ou tp ut Short C ircui t Curre nt
(Output High) IOHSC Short to GND - -80 mA
Ou tp ut Short C ircui t Curre nt
(Output Low) IOLSC Short to GND 80 - mA
Ou tput Im pe danc e Z OTA = +25oC6090Ω
NOTE:
1 . +V = +15V ± 10%, -V = -15V ± 10%, V1 = VREF = 5V ± 5%, unless otherwise specified TA = 0oC to +70oC for HS-3182-5 and
TA = -55oC to +125oC for HS-3182-8.
HS-3182
181
AC Electrical Performance Specifications
AC PARAMETER SYMBOL (NOTE 1)
CONDITIONS MIN MAX UNITS
Rise Time (AOUT, BOUT)t
RCA = CB = 75pF, Note 2 1 2 µS
(at TA = -55oC Only) 0.9 2.4 µS
CA = CB = 300pF, Note 2 3 9 µS
Fa l l Time (AOUT, BOUT)t
FCA = CB = 75pF, Note 3 1 2 µS
(at TA = -55oC Only) 0.9 2.4 µS
CA = CB = 300pF, Note 3 3 9 µS
Propagation Delay Input to Output tPLH CA = CB = 75pF, No Load - 3.3 µS
Propagation Delay Input to Output tPHL CA = CB = 75pF, No Load - 3.3 µS
NOTES:
1. +V = +15V, -V = -15V, V1 = VREF = 5V, unless otherwise specified TA = 0oC to +70oC for HS-3182-5 and TA = -55oC to +125oC for
HS-3182-8.
2. tR me as ured 50 % to 90 % t im e s 2, no load.
3. tF measured 50% to 10 % time s 2, no load.
Electrical Perf orman ce Speci fications
PARAMETER SYMBOL (NOTE 1)
CONDITIONS MIN MAX UNITS
In p ut Cap acitance CIN TA = +25oC - 15 pF
Supply Current +V (Short Circuit) ISC (+V) Short to GND, TA = +25 oC-150mA
Supply Current -V (Short Circuit) I SC (-V) Short to GND, TA = + 25 oC-150-mA
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are ch ar-
ac terize d upon initia l design and after major process an d/or design chang es affecting these parameters.
Power Specifications Nominal Power at +25oC, +V = +15V, -V = -15V, V1 = VREF = 5V, Notes 1, 3
DATA RATE
(K BITS/s) LOAD +V V- V1CHIP POWER POWER DISSIPATION
IN LOAD
0-100 No Load 11mA -10mA 600µA325mW 0
12.5-14 Full Load, Note 2 24mW -24mW 600µA 660mW 60mW
100 Full Load, Not e 2 4 6mW -46mW 600µA 1 Watt 325mW
NOTES:
1. Heat sink may be required for 100K bits/s at +125oC and output short circuit at + 125oC.
Thermal characteristics: T(CASE) = T(Junction) - θ(Junction - Case) P(Dissipation).
Where: T(Juncti on M ax ) = +17 5oC
θ(Juncti on - Case) = 10.9oC/W (6.1oC/W for LCC)
θ(Juncti on - A m bient) = 73.5oC/W (54.0 oC/W for LCC)
2. Full Load for ARINC 429: RL = 400Ω and CL = 30,0 00pF in par allel between AOUT and BOUT (see block diagram).
3. Outp ut Ove r-Vo ltage Prot ect ion: The f uses u sed for output ov er-vo lta ge prot ectio n may b e blown by a f ault at ea ch outp ut of greater than
±6. 5V r elative to GND.
HS-3182
182
Driver Waveforms
NOTES: tR measured 50% t o 90% t imes 2
tF measured 50% to 10% times 2
VIH = 5V VOL = -4.75V to -5.25V
VIL = 0V VOH = 4.75V to 5.25V
When the Data (A) input is in the Logic One state and the Data (B)
inpu t is in the L og ic Zero st ate , AOUT is eq ua l t o VREF and BOUT is
equal to -VREF. This constitutes the Output High state. Data (A) and
Dat a (B) b ot h in th e Log ic Z ero s tate c aus es bo th AOUT an d BOUT
to be equal to 0V which designates the output Null state. Data (A) in
the Logic Zero state and Data (B) in the Logic One state causes
AOUT to be equal to -VREF and B OUT to be equal to VREF which is
the Output Low state.
Burn-In Schematic
NOTES: R = 400Ω ± 5%
C1 = 0.03µF ± 20%
C2 = C3 = 500pF, NPO
+V = +15 .5 V ± 0.5V
-V = -15.5V ± 0.5 V
V1 = +5.5V ± 0. 5V
A 0.0µF de coupling ca pacit or is req uired o n ea ch o f the three
supply lines (+V, -V and V1) at every 3rd Burn-In socket.
Ambient Temp. Max. = +125oC.
Package = 16 Lead Side Brazed DIP.
Pulse Conditions = A & B = 6.25kHz ± 10%. B is delayed one-half
c ycle and in sync wit h A.
VIH = 2.0V Min.
VIL = 0.5V Max.
DATA (A) 0V
DATA (B) 0V
VREF
AOUT 0V
BOUT 0V
tPHL
-VREF
AOUT - BOUT
0V
DIFFERENTIAL
OUTPUT
50%
50%
50%
50% tPLH
tR
tF
2VREF
-VREF
VREF
HIGH
NULL
LOW
-2VREF
ADJ. BY
CB
ADJ. BY
CA
5V
0V
5V
0V
+4 .75V TO +5.2 5V
-4.75V TO -5.25V
+4 .75V TO +5.2 5V
-4.75V TO -5.25V
+9.5V TO +10.5V
NOTE: OUTPUTS UNLOADED
-9.5V TO -10.5V
V1DATA (B) +V
C1
GND
-VDATA (A)
16 15 14 13 12 11 10 9
12345678
C3
C2
R
HS-3182
VIL
VIH
VIH
VIL
A
B
HS-3182
