Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit BH616UV8010
BSI
R0201
-
B
H616UV801
0
Revision
1.0
Jul
. 2005
1
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
V
CC = 3.0V Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 2.5uA at 25OC
V
CC = 2.0V Data retention current : 2.5uA at 25OC
Ÿ High speed access time :
-70 70ns at 1.8V at 85OC
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refreash
Ÿ Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 by 16 bits and operates
in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
n PRODUCT FAMILY POWER CONSUMPTION
SPEED
(ns) STANDBY
(ICCSB1, Max) Operating
(ICC, Max)
PRODUCT
FAMILY OPERATING
TEMPERATURE
VCC
RANGE VCC=1.8~3.6V VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
PKG TYPE
+0OC to +70OC
70 13uA
10uA
10mA
7mA
BH616UV8010DI
BH616UV8010TI
BH616UV8010AI -25OC to +85OC
1.65V ~ 3.6V
70 15uA
12uA
10mA
7mA
DICE
TSOP1-48
BGA-48-0608
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
G
H
F
E
D
C
B
A
1
2
3
4
5
6
A9
A11
A10
NC
A12
A14
A13
A15
WE
DQ13
DQ5
DQ7
DQ6
A17
A16
A7
VSS
VCC
DQ12
DQ1
1
DQ4
DQ3
VSS
A5
OE
A3
A0
A6
A4
A1
A2
CE2
UB
DQ10
DQ1
CE
1
DQ2
DQ0
48-ball BGA top view
LB
DQ8
DQ9
V
SS
VCC
DQ14
DQ15
A18
NC
A8
A15
A1
4
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BH616UV8010TC
BH616UV8010TI
48
47
46
45
4
4
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 8192
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A15
A16
A2A1
Data
Input
Buffer
Control
DQ
0
.
.
.
.
.
.
DQ15
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
16
16
16
16
9
512
8192
1024
10
A18
Data
Output
Buffer
A13
CE2
CE1
WE
OE
UB
LB
VCC
VSS
A0
.
.
.
.
.
.
A14
A17
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
2
n PIN DESCRIPTIONS
Name Function
A0-A18 Address Input These 19 address inputs select one of the 524,288 x 16 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0-DQ15 Data Input/Output
Ports 16 bi-directional ports are used to read data from or write data into the RAM.
VCC Power Supply
VSS Ground
n TRUTH TABLE
MODE CE1 CE2 WE OE LB UB DQ0~DQ7
DQ8~DQ15
VCC CURRENT
H X X X X X High Z High Z ICCSB, ICCSB1
X L X X X X High Z High Z ICCSB, ICCSB1
Chip De-selected
(Power Down)
X X X X H H High Z High Z ICCSB, ICCSB1
Output Disabled
L H H H X X High Z High Z ICC
L L DOUT DOUT ICC
H L High Z DOUT ICC
Read L H H L
L H DOUT High Z ICC
L L DIN DIN ICC
H L X DIN ICC
Write L H L X
L H DIN X ICC
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
3
n ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND -0.5(2) to 4.6V
V
TBIAS Temperature Under
Bias -40 to +125
OC
TSTG Storage Temperature -60 to +150
OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 20 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
2. –2.0V in case of AC pulse width less than 30 ns
n OPERATING RANGE
RANG AMBIENT
TEMPERATURE VCC
Commercial 0OC to + 70OC 1.65V ~ 3.6V
Industrial -25OC to + 85OC 1.65V ~ 3.6V
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
SYMBOL
PAMAMETER
CONDITIONS
MAX.
UNITS
CIN Input
Capacitance VIN = 0V 6 pF
CIO Input/Output
Capacitance VI/O = 0V 8 pF
1. This parameter is guaranteed and not 100% tested.
n DC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP.(1)
MAX. UNITS
VCC Power Supply 1.65 -- 3.6 V
VCC=1.8V
0.4
VIL Input Low Voltage VCC=3.6V
-0.3(2) -- 0.8 V
VCC=1.8V
1.4
VIH Input High Voltage VCC=3.6V
2.0 -- VCC+0.3(3)
V
IIL Input Leakage Current VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL -- -- 1 uA
ILO Output Leakage Current VI/O = 0V to VCC,
CE1 = VIH or CE2 = VIL or OE = VIH or
UB = LB = VIH -- -- 1 uA
VCC = Max, IOL = 0.2mA VCC=1.8V
0.2
VOL Output Low Voltage VCC = Max, IOL = 2.0mA VCC=3.6V
-- -- 0.4 V
VCC = Min, IOH = -0.1mA VCC=1.8V
VCC-0.2
VOH Output High Voltage VCC = Min, IOH = -1.0mA VCC=3.6V
2.4 -- -- V
VCC=1.8V
4.5 7
ICC Operating Power Supply
Current
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = FMAX(4) VCC=3.6V
-- 5.0 10 mA
VCC=1.8V
1.0 1.5
ICC1 Operating Power Supply
Current
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz VCC=3.6V
-- 1.5 2.0 mA
VCC=1.8V
0.5
ICCSB Standby Current – TTL CE1 = VIH, or CE2 = VIL,
IDQ = 0mA VCC=3.6V
-- -- 1.0 mA
VCC=1.8V
2.5 12
ICCSB1 (5) Standby Current – CMOS CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V VCC=3.6V
-- 2.5 15 uA
1. Typical characteristics are at TA=25OC.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICCSB1(MAX.) is 10uA/13uA at VCC=1.8V/3.6V and TA=0OC ~ 70OC.
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
4
n DATA RETENTION CHARACTERISTICS (TA = -25OC to +85OC)
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1)
MAX. UNITS
VDR VCC for Data Retention CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V 1.0 -- -- V
VCC=1.0V
0.5 3.0
ICCDR(3) Data Retention Current CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V VCC=2.0V
-- 2.5 12 uA
tCDR Chip Deselect to Data
Retention Time 0 -- -- ns
tR Operation Recovery Time See Retention Waveform tRC (2) -- -- ns
1. TA=25OC.
2. tRC = Read Cycle Time.
3. ICCDR(MAX.) is 2.5uA /10uA at VCC=1.0V/2.0V and TA=0OC ~ 70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels VCC / 0V
Input Rise and Fall Times 1V/ns
Input and Output Timing
Reference Level 0.5Vcc
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1,
tCHZ2, tBDO, tOHZ, tWHZ, tOW
CL = 5pF+1TTL
Output Load
Others CL = 30pF+1TTL
1. Including jig and scope capacitance.
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L” WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H” WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
(1)
1
TTL
Output
ALL INPUT PULSES
→
←
90%
V
CC
GND
Rise Time:
1V/ns Fall Time:
1V/ns
90%
→
←
10%
10%
Data Retention Mode
V
CC
t
CDR
V
CC
tR
VIH
VIH
CE1≧VCC - 0.2V
V
DR
≧1.0V
CE1
VCC
CE2
Data Retention Mode
V
CC
tCDR
V
CC
tR
VIL
VIL
VCC
V
DR
≧1.0V
CE2≦0.2V
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
5
n AC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
READ CYCLE
CYCLE TIME : 70ns
JEDEC
PARAMETER
NAME
PARANETER
NAME DESCRIPTION MIN. TYP. MAX. UNITS
tAVAX tRC Read Cycle Time 70 -- -- ns
tAVQX tAA Address Access Time -- -- 70 ns
tE1LQV tACS1 Chip Select Access Time (CE1)
-- -- 70 ns
tE2LQV tACS2 Chip Select Access Time (CE2)
-- -- 70 ns
tBLQV tBA Data Byte Control Access Time (LB, UB)
-- -- 70 ns
tGLQV tOE Output Enable to Output Valid -- -- 30 ns
tE1LQX tCLZ1 Chip Select to Output Low Z (CE1)
10 -- -- ns
tE2LQX tCLZ2 Chip Select to Output Low Z (CE2)
10 -- -- ns
tBLQX tBE Data Byte Control to Output Low Z (LB, UB)
10 -- -- ns
tGLQX tOLZ Output Enable to Output Low Z 5 -- -- ns
tE1HQZ tCHZ1 Chip Select to Output High Z (CE1)
-- -- 25 ns
tE2HQZ tCHZ2 Chip Select to Output High Z (CE2)
-- -- 25 ns
tBHQZ tBDO Data Byte Control to Output High Z (LB, UB)
-- -- 25 ns
tGHQZ tOHZ Output Enable to Output High Z -- -- 25 ns
tAVQX tOH Data Hold from Address Change 10 -- -- ns
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
t
OH
t
AA
DOUT
ADDRESS
tOH
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
6
READ CYCLE 2 (1,3,4)
READ CYCLE 3 (1, 4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
t
OH
t
RC
t
OE
tBE
tBDO
DOUT
CE1
OE
ADDRESS
tCLZ1
(5)
t
ACS1
t
CHZ
(1,5)
tOHZ
(5)
t
OLZ
t
AA
LB, UB
t
BA
tCLZ2
(5)
tCHZ2
(2,5)
CE2
tACS2
tCLZ
(5,6)
D
OUT
CE2
CE
1
t
ACS2
(6)
t
ACS1
tCHZ
(5, 6)
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
7
n AC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
WRITE CYCLE CYCLE TIME : 70ns
JEDEC
PARAMETER
NAME
PARANETER
NAME DESCRIPTION MIN. TYP. MAX. UNITS
tAVAX tWC Write Cycle Time 70 -- -- ns
tAVWL tAS Address Set up Time 0 -- -- ns
tAVWH tAW Address Valid to End of Write 50 -- -- ns
tELWH tCW Chip Select to End of Write 50 -- -- ns
tBLWH tBW Data Byte Control to End of Write (LB, UB)
50 -- -- ns
tWLWH tWP Write Pulse Width 35 -- -- ns
tWHAX tWR1 Write Recovery Time (CE1, WE)
0 -- -- ns
tE2LAX tWR2 Write Recovery Time (CE2)
0 -- -- ns
tWLQZ tWHZ Write to Output High Z -- -- 20 ns
tDVWH tDW Data to Write Time Overlap 30 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 ns
tWHQX tOW End of Write to Output Active 5 -- -- ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
tWR1
(3)
tCW
(11)
tWP
(2)
tAW
tOHZ
(4,10)
t
AS
tWR2
(3)
t
DH
t
DW
DIN
DOUT
WE
LB, UB
CE1
OE
ADDRESS
(5)
tBW
tCW
(11)
CE2
(5)
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
8
WRITE CYCLE 2 (1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. t
WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
t
WC
tCW
(11)
tWP
(2)
tAW
tWHZ
(4,10)
t
AS
tWR
(3)
t
DH
t
DW
DIN
D
OUT
WE
LB, UB
CE1
ADDRESS
(5)
t
OW
(7)
(8)
(8,9)
tBW
(
12
)
tCW
(11)
CE2
(5)
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
9
n ORDERING INFORMATION
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
n
PACKAGE
T: TSOP 1-48
A
: BGA-48-0608
D:DICE
BH616UV8010 X X Z Y Y
GRADE
I
:
-
25
o
C ~ +
85
o
C
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
48 mini-BGA (6 x 8)
D1
VIEW A
1.4
Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0
6.0
E N
48
3.75
E1D1
5.25
NOTES:
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
10
PACKAGE DIMENSIONS
TSOP1-48 Pin (12mm x 20mm)
BSI
B
H
6
16U
V
8010
R0201-BH616UV8010
Revision
1.0
Jul. 2005
11
n Revision History
Revision No. History Draft Date Remark
1.0 Initial Production Version July 15,2005 Initial
