ee eee ee WS27CO10L LOW POWER 1 MEG (128K x 8) CMOS EPROM KEY FEATURES DESC SMD No. 5962-89614 JEDEC Standard Pin Configuration 32 Pin CERDIP Package 32 Pin Leaded Chip Carrier (CLDCC) 32 Pin Plastic Leaded Chip Carrier (PLDCC) High Performance CMOS 90 ns Access Time Standby Current <100 PA * EPI Processing Latch-Up Immunity to 200 mA ESD Protection Exceeds 2000 Volts GENERAL DESCRIPTION The WS27C010L is a performance oriented 1 Meg UV Erasable Electrically Programmable Read Only Memory organized as 128K words x 8 bits/word. It is manufactured using an advanced CMOS technology which enables it to operate at data access times as fast as 90 nsec. The memory was designed utilizing WSI's patented self-aligned split gate EPROM cell, resulting in a low power device with a very cost effective die size. The WS27C0O10L 1 Meg EPROM provides extensive code store capacity for microprocessor, DSP, and microcontroller-based systems. {ts 90 nsec access time over the full operating temperature range provides the potential of no-wait state operation. And where this parameter is important, the WS27C010L provides the user with a very fast 35 nsec To output enable time. The WS27C010L is offered in both a 32 pin 600 mil CERDIP, and both a Plastic and a Ceramic 32 pad Leaded Chip Carrier (PLDCC and CLDCC respectively) for surface mount applications. Its standard JEDEC EPROM pinouts provide for automatic upgrade density paths for existing 128K and 256K EPROM users. PIN CONFIGURATION TOP VIEW Chip Carrier CERDIP VepQ1 ~ = 32{] Voce Aye U2 311] PGM Ais (3 309) Nc : Ayo 4 aot a n 2 : ay A U5 281 Ata Ach, a A, 6 271] Ag os ae Ag 7 261] Ag a f= : Ni Ags 250] Aq A F- yu Ag U9 241 OE er: s[ OF Ay 10 230] Aig Ay E: a Ato a, O11 22{] CE a 7 a Ag O12 211] O7 r3 13 al 14 15 16 17 18 19 20 oA ta He Sw a 5 deni O, 15 180 Oy O22 Og 04 Os Og eno 16 1761 Og PRODUCT SELECTION GUIDE PARAMETER WS27CO10L-90 | WS27C010L-10 | WS27CO010L-12 | WS27CO10L-15 Address Access Time (Max) 90 ns 100 ns 120 ns 150 ns Chip Select Time (Max) 90 ns 100 ns 120 ns 150 ns Output Enable Time (Max) 30 ns 35 ns 35 ns 40 ns 3-7 9539690 0003e31 55T MWAFWS27CO10L ABSOLUTE MAXIMUM RATINGS* Storage Temperature... ee eeeeeeeees 65 to + 150C Voltage on any Pin with Respect to Ground ...........ee eee cseeneseeeneens 0.6V to +7V Vpp with Respect to Ground................... ~-0.6V to + 14V Voc Supply Voltage with Respect to Ground oo... ec ccecscssseereeeeee 0.6V to +7V ESD Protection >2000V OPERATING RANGE RANGE TEMPERATURE Voc Commercial 0C to +70C +5V + 10%" Products with part numbers ending in /5" have +5% Vcc range. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. DC READ CHARACTERISTICS Over Operating Range. (See Above) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS Vit Input Low Voltage -0.5 0.8 Vv Vie Input High Voltage 2.0 Voeco+1 Vv Voi Output Low Voltage lo. = 2.1 MA 0.4 Vv Vou Output High Voltage low = 400 PA 3.5 Vv Isp1 Voc Standby Current (CMOS)| CE = Vgg + 0.3 V (Note 2) 100 yA Isge Voc Standby Current CE = Vin 1 mA lec Voc Active Current (TTL) Woe 1) = Vin = : ee = ~ Ipp Vpp Supply Current Vpp = Veo 100 HA Vpp Vpp Read Voltage Veco 0.4 Voc Vv hy Input Leakage Current Vin = 5.5 V or Gnd -10 10 pA lLo Output Leakage Current Vout = 5-5 V or Gnd -10 10 pA NOTES: 1. The supply current is the sum of loc and Ipp. The maximum current value is with Outputs Op to O7 unloaded. 2. CMOS inputs: V;, = GND + 0.3V, Vi = Voc + 0.3 V. AC READ CHARACTERISTICS Over Operating Range with Vpp = Voc SYMBOL PARAMETER 27C010L-90 | 27CO10L-10 | 27C010L-12 | 27CO10L-15 UNITS MIN MAX MIN MAX MIN MAX | MIN MAX tacc Address to Output Delay 90 100 120 150 toe CE to Output Delay 90 100 120 150 tor OE to Output Delay 30 35 35 40 oF | Oaput Rost he 9) | [=| je} fel Output Hold from Addresses,| 0 0 0 0 tou CE or OE, Whichever Occurred First (Note 3) NOTE: 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven see timing diagram. 3-8 WIS; Me 9539690 0003232 456 MWAFAC READ TIMING DIAGRAM WS27C010L ADDRESS VALID -_ tee | toe tacc ton (8) LA | tog! Vin Ly ADDRESSES x Vit N Vin CE ViL Vin OE Vii Vin OUTPUT Vit mon K VALID OUTPUT yp HIGH Z NOTE: 4. OE may be delayed up to tog tog after the falling edge of CE without impact on tog. CAPACITANCE) T, = 25C, f = 1 MHz SYMBOL PARAMETER CONDITIONS TYP() MAX UNITS Cin Input Capacitance Vin = OV 4 6 pF Court Output Capacitance Vout = 0V 8 12 pF Cypp Vpp Capacitance Vpp =0V 18 25 pF NOTES: 5. This parameter is only sampled and is not 100% tested. 6. Typical values are for Ta = 25C and nominal supply voltages. TEST LOAD (High Impedance Test Systems) A.C. TESTING INPUT/OUTPUT WAVEFORM 2.01 V O~/A_ D.U.T. O--4 8202 100 pF > L. (INCLUDING SCOPE AND JIG L CAPACITANCE 2a 20 oe 0.4 0.8 A.C. testing inputs are driven at 2.4 V for a logic "1" and 0.4 V TEST ( ) ( y 2.0 ea 0.8 for a logic O." Timing measurements are made at 2.0 V fora logic "1" and 0.8 V for a logic "9". NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters. 4.0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between Vcc and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures. MB 9539690 0003233 3ee MWAF = 3-9WS27CO10L PROGRAMMING INFORMATION DC CHARACTERISTICS (T,, = 25 + 5C, Voc = 6.25 + 0.25 V, Vpp = 12.75 + 0.25 V. See Notes 8, 9 and 10) SYMBOLS PARAMETER MIN MAX UNITS ho Input Leakage Current (Vin = Veg or Gnd) -10 10 pA ie | Hep en OPO yy co | om loc Veco Supply Current 50 mA Vit Input Low Voltage -0.1 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.3 v Vor Output Low Voltage During Verify (Ig, = 2.1 mA) 0.4 v Vou Output High Voltage During Verify (Io. = 400 LA) 3.5 Vv NOTES: 8. Vcc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp. 9. Vpp must not be greater than 14 volts including overshoot. During CE = PGM = Vi, Vpp must not be switched from 5 volts to 12.75 volts or vice-versa. 10. During power up the PGM pin must be brought high (2 V,,) either coincident with or before power is applied to Vpp. AC CHARACTERISTICS (1, = 25 +5C, Voc = 6.25 + 0.25 V, Vpp = 12.75 + 0.25 V) SYMBOLS PARAMETER MIN TYP MAX UNITS tas Address Setup Time 2 ps toes Output Enable Setup Time 2 ps tos Data Setup Time 2 us tay Address Hold Time 0 ys ton Data Hold Time 2 ps tor Chip Disable to Output Float Delay 0 55 ns toe Data Valid From Output Enable 55 ns tys/tces Vpp Setup Time/CE Setup Time 2 ys tpw PGM Pulse Width 0.1 3 4 ms PROGRAMMING WAVEFORM ADDRESSES ADDRESS STABLE tas | tan DATA DATA IN STABLE DATA gut > tos >| = toy a toe | Vpp Vep Vec Ving = tys >) CE Vin toes Vin L PGM Vin t t tpw bt toes Vin OE Vit k / ONL 3-10 MM! 9539690 0003234 269 SWAFWS27CO010L MODE SELECTION The modes of operation of the WS27CO10L are listed below. A single 5 V power supply is required in the read mode. All inputs are TTL levels except for Vpp and Ag for device signature. MODE PINS CE OE | PGM Ag Ao Vpp | Voc | OUTPUTS Read Vi Vit x) x x x 5.0V Dout Output Disable X Vin X X x X 5.0V High Z Standby Vin X x X Xx X 5.0 V High Z Programming Vi Vin Viv 4 X Vep'?) | 6.25 V Di Program Verify Vin Vie Vin X X | Vpp"2! | 6.25 V Dour Program Inhibit Vig X X X X | Vpp"4) | Sov High Z ; Manufacturer(3] Vj, Vin 4 Vv") Vin x 5.0V 23H Signature Device(3) Vi Vit Xx Vu? | Vig X 5.0V C1H NOTES: 11.X can be Vj or Vin. 12.Viyq = Vpp = 12.75 0.25 V. 13.A,Ag, Aig Ate = Vice ORDERING INFORMATION PART NUMBER Sins). PAC AGE AR GE TEMPERATURE | MANUFACTURING RANGE PROCEDURE WS27C010L-90D 90 32 Pin CERDIP, 0.6" D4 Commercial Standard WS27C010L-90J 90 32 Pin PLDCC J4 Commercial Standard WS27C010L-10D/5 100 32 Pin CERDIP, 0.6" D4 Commercial Standard WS27C010L-10J/5 100 32 Pin PLDCC J4 Commercial Standard WS27C010L-10L/5 100 32 Pin CLDCC L3 Commercial Standard WS27C010L-12D 120 32 Pin CERDIP, 0.6" D4 Commercial Standard WS27C010L-12J 120 32 Pin PLDCC J4 Commercial Standard WS27C010L-12L 120 32 Pin CLDCC L3 Commercial Standard WS27C010L-15D 150 32 Pin CERDIP, 0.6" D4 Commercial Standard WS27C010L-15J 150 32 Pin PLDCC J4 Commercial Standard WS27C010L-15L 150 32 Pin CLDCC L3 Commercial Standard NOTE: 14. The actual part marking will not include the initials WS." 15. Products with part numbers ending in /5 have a +5% Vg tolerance range. PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 6-1 The WS27CO10L is pragrammed using Algorithm E shown on page 6-11. (This product can also be programmed by using National Semiconductor's 27C010 Programming Algorithm.) MS 9539690 0003235 115 MBUAF 317