User's Manual 8 78K0/Kx2 User's Manual: Hardware 8-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.4.01 Jul 2010 Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/Kx2 microcontrollers and design and develop application systems and programs for these devices. The target products are as follows. Conventional-specification Products 78K0/KB2 Expanded-specification Products PD78F0500, 78F0501, 78F0502, 78F0503, PD78F0500A, 78F0501A, 78F0502A, 78F0503D, 78F0500(A), 78F0501(A), 78F0502(A), 78F0503A, 78F0503DA, 78F0500A(A), 78F0503(A), 78F0500(A2), 78F0501(A2), 78F0501A(A), 78F0502A(A), 78F0503A(A), 78F0502(A2), 78F0503(A2) 78F0500A(A2), 78F0501A(A2), 78F0502A(A2), 78F0503A(A2) 78K0/KC2 PD78F0511, 78F0512, 78F0513, 78F0514, PD78F0511A, 78F0512A, 78F0513A, 78F0515, 78F0513D, 78F0515D, 78F0511(A), 78F0514A, 78F0515A, 78F0513DA, 78F0515DA, 78F0512(A), 78F0513(A), 78F0514(A), 78F0511A(A), 78F0512A(A), 78F0513A(A), 78F0515(A), 78F0511(A2), 78F0512(A2), 78F0514A(A), 78F0515A(A), 78F0511A(A2), 78F0513(A2), 78F0514(A2), 78F0515(A2) 78F0512A(A2), 78F0513A(A2), 78F0514A(A2), 78F0515A(A2) 78K0/KD2 78K0/KE2 78K0/KF2 PD78F0521, 78F0522, 78F0523, 78F0524, PD78F0521A, 78F0522A, 78F0523A, 78F0525, 78F0526, 78F0527, 78F0527D, 78F0524A, 78F0525A, 78F0526A, 78F0527A, 78F0521(A), 78F0522(A), 78F0523(A), 78F0527DA, 78F0521A(A), 78F0522A(A), 78F0524(A), 78F0525(A), 78F0526(A), 78F0523A(A), 78F0524A(A), 78F0525A(A), 78F0527(A), 78F0521(A2), 78F0522(A2), 78F0526A(A), 78F0527A(A), 78F0521A(A2), 78F0523(A2), 78F0524(A2), 78F0525(A2), 78F0522A(A2), 78F0523A(A2), 78F0524A(A2), 78F0526(A2), 78F0527(A2) 78F0525A(A2), 78F0526A(A2), 78F0527A(A2) PD78F0531, 78F0532, 78F0533, 78F0534, PD78F0531A, 78F0532A, 78F0533A, 78F0535, 78F0536, 78F0537, 78F0537D, 78F0534A, 78F0535A, 78F0536A, 78F0537A, 78F0531(A), 78F0532(A), 78F0533(A), 78F0537DA, 78F0531A(A), 78F0532A(A), 78F0534(A), 78F0535(A), 78F0536(A), 78F0533A(A), 78F0534A(A), 78F0535A(A), 78F0537(A), 78F0531(A2), 78F0532(A2), 78F0536A(A), 78F0537A(A), 78F0531A(A2), 78F0533(A2), 78F0534(A2), 78F0535(A2), 78F0532A(A2), 78F0533A(A2), 78F0534A(A2), 78F0536(A2), 78F0537(A2) 78F0535A(A2), 78F0536A(A2), 78F0537A(A2) PD78F0544, 78F0545, 78F0546, 78F0547, PD78F0544A, 78F0545A, 78F0546A, 78F0547D, 78F0544(A), 78F0545(A), 78F0547A, 78F0547DA, 78F0544A(A), 78F0546(A), 78F0547(A), 78F0544(A2), 78F0545A(A), 78F0546A(A), 78F0547A(A), 78F0545(A2), 78F0546(A2), 78F0547(A2) 78F0544A(A2), 78F0545A(A2), 78F0546A(A2), 78F0547A(A2) Differences Between Conventional-specification Products and Expanded-specification Products The differences between the conventional-specification products (PD78F05xx, 78F05xxD) and expandedspecification products (PD78F05xxA, 78F05xxDA) of the 78K0/Kx2 microcontrollers are described below. * * * * * * A/D conversion time X1 oscillator characteristics Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width (AC characteristics) The number of flash memory rewrites and retention time Processing time of the self programming library Interrupt response time of the self programming library For details, see 1.1 Differences Between Conventional-specification Products (PD78F05xx, 78F05xxD) and Expanded-specification Products (PD78F05xxA, 78F05xxDA). Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The manual for the 78K0/Kx2 microcontrollers is separated into two parts: this manual and the instructions edition (common to the 78K0 microcontrollers). * * * * * How to Read This Manual 78K0/Kx2 78K/0 Series User's Manual (This Manual) User's Manual Instructions Pin functions Internal block functions Interrupts Other on-chip peripheral functions Electrical specifications * CPU functions * Instruction set * Explanation of each instruction It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) grade products and (A2) grade products of the 78K0/Kx2 microcontrollers: Only the quality grade differs between standard products and (A), (A2) grade products. Read the part number as follows. * PD78F05xx PD78F05xx(A), 78F05xx(A2) * PD78F05xxA PD78F05xxA(A), 78F05xxA(A2) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark "<R>" shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. * How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0. * To check the details of a register when you know the register name: See APPENDIX C REGISTER INDEX. * To know details of the 78K0 microcontroller instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Conventions Data significance: Active low representations: Note: Caution: Remark: Numerical representations: Higher digits on the left and lower digits on the right xxx (overscore over pin and signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information ...xxxx or xxxxB Binary ...xxxx Decimal Hexadecimal ...xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/Kx2 User's Manual This manual 78K/0 Series Instructions User's Manual U12326E 78K0/Kx2 Flash Memory Programming (Programmer) Application Note U17739E 78K0/Kx2 Flash Memory Self Programming User's Manual U17516E 78K0/Kx2 EEPROM TM Emulation Application Note U17517E 78K0 Microcontrollers Self Programming Library Type01 User's Manual U18274E 78K0 Microcontrollers EEPROM Emulation Library Type01 User's Manual U18275E Documents Related to Flash Memory Programming Document Name Document No. PG-FP5 Flash Memory Programmer User's Manual U18865E PG-FP4 Flash Memory Programmer User's Manual U15260E Documents Related to Development Tools (Hardware) Document Name Document No. QB-78K0KX2 In-Circuit Emulator User's Manual U17341E QB-MINI2 On-Chip Debug Emulator with Programming Function User's Manual U18371E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Documents Related to Development Tools (Software) Document Name RA78K0 Ver.3.80 Assembler Package User's Manual Note 1 Document No. Operation U17199E Language U17198E Structured Assembly Language 78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document) CC78K0 Ver.3.70 C Compiler User's Manual Operation Note 2 U17197E ZUD-CD-07-0181-E U17201E Language 78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification Document) Note 1 U17200E Note 2 ZUD-CD-07-0103-E SM+ System Simulator Operation U18601E User's Manual User Open Interface U18212E ID78K0-QB Ver.2.94 Integrated Debugger User's Manual Operation U18330E ID78K0-QB Ver.3.00 Integrated Debugger User's Manual Operation U18492E PM plus Ver.5.20 Note 3 Note 4 PM+ Ver.6.30 Notes 1. User's Manual U16934E User's Manual U18416E This document is installed into the PC together with the tool when installing RA78K0 Ver. 4.01. For descriptions not included in "78K0 Assembler Package RA78K0 Ver. 4.01 Operating Precautions", refer to the user's manual of RA78K0 Ver. 3.80. 2. This document is installed into the PC together with the tool when installing CC78K0 Ver. 4.00. For descriptions not included in "78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions", refer to the user's manual of CC78K0 Ver. 3.70. 3. 4. PM plus Ver. 5.20 is the integrated development environment included with RA78K0 Ver. 3.80. PM+ Ver. 6.30 is the integrated development environment included with RA78K0 Ver. 4.01. Software tool (assembler, C compiler, debugger, and simulator) products of different versions can be managed. Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Document No. X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www2.renesas.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. CONTENTS CHAPTER 1 OUTLINE............................................................................................................................. 19 1.1 Differences Between Conventional-specification Products (PD78F05xx and 78F05xxD) and Expanded-specification Products (PD78F05xxA and 78F05xxDA) ..................................... 19 1.1.1 A/D conversion time ........................................................................................................................ 20 1.1.2 X1 oscillator characteristics............................................................................................................. 20 1.1.3 Time Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width (AC characteristics) ............................................................................................................... 21 1.1.4 Number of flash memory rewrites and retention time ...................................................................... 22 1.1.5 Processing time for self programming library .................................................................................. 23 1.1.6 Interrupt response time for self programming library ....................................................................... 29 1.2 Features......................................................................................................................................... 33 1.3 Applications .................................................................................................................................. 34 1.4 Ordering Information.................................................................................................................... 35 1.5.1 78K0/KB2 ........................................................................................................................................ 42 1.5.2 78K0/KC2........................................................................................................................................ 44 1.5.3 78K0/KD2........................................................................................................................................ 47 1.5.4 78K0/KE2 ........................................................................................................................................ 48 1.5.5 78K0/KF2 ........................................................................................................................................ 50 1.6 Pin Identification........................................................................................................................... 51 1.7 Block Diagram .............................................................................................................................. 52 1.7.1 78K0/KB2 ........................................................................................................................................ 52 1.7.2 78K0/KC2........................................................................................................................................ 53 1.7.3 78K0/KD2........................................................................................................................................ 54 1.7.4 78K0/KE2 ........................................................................................................................................ 55 1.7.5 78K0/KF2 ........................................................................................................................................ 56 1.8 Outline of Functions..................................................................................................................... 57 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 60 2.1 Pin Function List .......................................................................................................................... 60 2.1.1 78K0/KB2 ........................................................................................................................................ 61 2.1.2 78K0/KC2........................................................................................................................................ 64 2.1.3 78K0/KD2........................................................................................................................................ 67 2.1.4 78K0/KE2 ........................................................................................................................................ 70 2.1.5 78K0/KF2 ........................................................................................................................................ 74 2.2 Description of Pin Functions ...................................................................................................... 78 2.2.1 P00 to P06 (port 0) .......................................................................................................................... 78 2.2.2 P10 to P17 (port 1) .......................................................................................................................... 79 2.2.3 P20 to P27 (port 2) .......................................................................................................................... 81 2.2.4 P30 to P33 (port 3) .......................................................................................................................... 82 2.2.5 P40 to P47 (port 4) .......................................................................................................................... 83 2.2.6 P50 to P57 (port 5) .......................................................................................................................... 84 2.2.7 P60 to P67 (port 6) .......................................................................................................................... 84 2.2.8 P70 to P77 (port 7) .......................................................................................................................... 85 2.2.9 P120 to P124 (port 12) .................................................................................................................... 86 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 9 2.2.10 P130 (port 13) ............................................................................................................................... 87 2.2.11 P140 to P145 (port 14) .................................................................................................................. 88 2.2.12 AVREF, AVSS, VDD, EVDD, VSS, EVSS ............................................................................................... 89 2.2.13 RESET .......................................................................................................................................... 90 2.2.14 REGC............................................................................................................................................ 90 2.2.15 FLMD0 .......................................................................................................................................... 90 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 91 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 96 3.1 Memory Space .............................................................................................................................. 96 3.1.1 Internal program memory space ................................................................................................... 111 3.1.2 Memory bank (products whose flash memory is at least 96 KB only) ........................................... 113 3.1.3 Internal data memory space.......................................................................................................... 114 3.1.4 Special function register (SFR) area ............................................................................................. 116 3.1.5 Data memory addressing .............................................................................................................. 116 3.2 Processor Registers................................................................................................................... 125 3.2.1 Control registers ............................................................................................................................ 125 3.2.2 General-purpose registers............................................................................................................. 129 3.2.3 Special function registers (SFRs) .................................................................................................. 130 3.3 Instruction Address Addressing............................................................................................... 136 3.3.1 Relative addressing....................................................................................................................... 136 3.3.2 Immediate addressing ................................................................................................................... 137 3.3.3 Table indirect addressing .............................................................................................................. 138 3.3.4 Register addressing ...................................................................................................................... 139 3.4 Operand Address Addressing .................................................................................................. 139 3.4.1 Implied addressing ........................................................................................................................ 139 3.4.2 Register addressing ...................................................................................................................... 140 3.4.3 Direct addressing .......................................................................................................................... 141 3.4.4 Short direct addressing ................................................................................................................. 142 3.4.5 Special function register (SFR) addressing ................................................................................... 143 3.4.6 Register indirect addressing.......................................................................................................... 144 3.4.7 Based addressing.......................................................................................................................... 145 3.4.8 Based indexed addressing ............................................................................................................ 146 3.4.9 Stack addressing........................................................................................................................... 147 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PRODUCTS WHOSE FLASH MEMORY IS AT LEAST 96 KB ONLY)....................................................................................................... 148 4.1 4.2 4.3 4.4 Memory Bank .............................................................................................................................. 148 Difference in Representation of Memory Space ..................................................................... 149 Memory Bank Select Register (BANK) ..................................................................................... 150 Selecting Memory Bank ............................................................................................................. 151 4.4.1 Referencing values between memory banks................................................................................. 151 4.4.2 Branching instruction between memory banks.............................................................................. 153 4.4.3 Subroutine call between memory banks........................................................................................ 155 4.4.4 Instruction branch to bank area by interrupt .................................................................................. 157 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 10 CHAPTER 5 PORT FUNCTIONS ......................................................................................................... 159 5.1 Port Functions ............................................................................................................................ 159 5.2 Port Configuration...................................................................................................................... 163 5.2.1 Port 0............................................................................................................................................. 164 5.2.2 Port 1............................................................................................................................................. 175 5.2.3 Port 2............................................................................................................................................. 181 5.2.4 Port 3............................................................................................................................................. 183 5.2.5 Port 4............................................................................................................................................. 186 5.2.6 Port 5............................................................................................................................................. 188 5.2.7 Port 6............................................................................................................................................. 189 5.2.8 Port 7............................................................................................................................................. 194 5.2.9 Port 12........................................................................................................................................... 196 5.2.10 Port 13......................................................................................................................................... 199 5.2.11 Port 14......................................................................................................................................... 200 5.3 Registers Controlling Port Function ........................................................................................ 204 5.4 Port Function Operations .......................................................................................................... 221 5.4.1 Writing to I/O port .......................................................................................................................... 221 5.4.2 Reading from I/O port.................................................................................................................... 221 5.4.3 Operations on I/O port................................................................................................................... 221 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 221 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 224 CHAPTER 6 CLOCK GENERATOR .................................................................................................... 225 6.1 6.2 6.3 6.4 Functions of Clock Generator................................................................................................... 225 Configuration of Clock Generator ............................................................................................ 226 Registers Controlling Clock Generator.................................................................................... 229 System Clock Oscillator ............................................................................................................ 240 6.4.1 X1 oscillator................................................................................................................................... 240 6.4.2 XT1 oscillator ................................................................................................................................ 240 6.4.3 When subsystem clock is not used ............................................................................................... 243 6.4.4 Internal high-speed oscillator ........................................................................................................ 243 6.4.5 Internal low-speed oscillator.......................................................................................................... 243 6.4.6 Prescaler ....................................................................................................................................... 243 6.5 Clock Generator Operation ....................................................................................................... 244 6.6 Controlling Clock........................................................................................................................ 248 6.6.1 Example of controlling high-speed system clock ........................................................................... 248 6.6.2 Example of controlling internal high-speed oscillation clock.......................................................... 251 6.6.3 Example of controlling subsystem clock........................................................................................ 254 6.6.4 Example of controlling internal low-speed oscillation clock ........................................................... 256 6.6.5 Clocks supplied to CPU and peripheral hardware ......................................................................... 257 6.6.6 CPU clock status transition diagram.............................................................................................. 258 6.6.7 Condition before changing CPU clock and processing after changing CPU clock ........................ 265 6.6.8 Time required for switchover of CPU clock and main system clock .............................................. 266 6.6.9 Conditions before clock oscillation is stopped ............................................................................... 268 6.6.10 Peripheral hardware and source clocks ...................................................................................... 269 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 11 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 270 7.1 7.2 7.3 7.4 Functions of 16-Bit Timer/Event Counters 00 and 01............................................................. 270 Configuration of 16-Bit Timer/Event Counters 00 and 01 ...................................................... 271 Registers Controlling 16-Bit Timer/Event Counters 00 and 01.............................................. 277 Operation of 16-Bit Timer/Event Counters 00 and 01 ............................................................. 289 7.4.1 Interval timer operation.................................................................................................................. 289 7.4.2 Square-wave output operation ...................................................................................................... 292 7.4.3 External event counter operation .................................................................................................. 295 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input ......................................... 299 7.4.5 Free-running timer operation......................................................................................................... 312 7.4.6 PPG output operation.................................................................................................................... 321 7.4.7 One-shot pulse output operation ................................................................................................... 325 7.4.8 Pulse width measurement operation ............................................................................................. 330 7.5 Special Use of TM0n................................................................................................................... 338 7.5.1 Rewriting CR01n during TM0n operation ...................................................................................... 338 7.5.2 Setting LVS0n and LVR0n ............................................................................................................ 338 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 ............................................................. 340 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 345 8.1 8.2 8.3 8.4 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 345 Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 345 Registers Controlling 8-Bit Timer/Event Counters 50 and 51................................................ 348 Operations of 8-Bit Timer/Event Counters 50 and 51 ............................................................. 354 8.4.1 Operation as interval timer ............................................................................................................ 354 8.4.2 Operation as external event counter ............................................................................................. 356 8.4.3 Square-wave output operation ...................................................................................................... 357 8.4.4 PWM output operation................................................................................................................... 358 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 362 CHAPTER 9 8-BIT TIMERS H0 AND H1........................................................................................... 363 9.1 9.2 9.3 9.4 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 363 Configuration of 8-Bit Timers H0 and H1 ................................................................................. 363 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 367 Operation of 8-Bit Timers H0 and H1........................................................................................ 373 9.4.1 Operation as interval timer/square-wave output ............................................................................ 373 9.4.2 Operation as PWM output ............................................................................................................. 376 9.4.3 Carrier generator operation (8-bit timer H1 only)........................................................................... 382 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 12 CHAPTER 10 WATCH TIMER.............................................................................................................. 389 10.1 10.2 10.3 10.4 Functions of Watch Timer ....................................................................................................... 389 Configuration of Watch Timer................................................................................................. 391 Register Controlling Watch Timer .......................................................................................... 391 Watch Timer Operations .......................................................................................................... 394 10.4.1 Watch timer operation ................................................................................................................. 394 10.4.2 Interval timer operation................................................................................................................ 394 10.5 Cautions for Watch Timer........................................................................................................ 395 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 396 11.1 11.2 11.3 11.4 Functions of Watchdog Timer................................................................................................. 396 Configuration of Watchdog Timer .......................................................................................... 397 Register Controlling Watchdog Timer.................................................................................... 398 Operation of Watchdog Timer................................................................................................. 399 11.4.1 Controlling operation of watchdog timer ...................................................................................... 399 11.4.2 Setting overflow time of watchdog timer...................................................................................... 400 11.4.3 Setting window open period of watchdog timer ........................................................................... 401 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 403 12.1 12.2 12.3 12.4 Functions of Clock Output/Buzzer Output Controller .......................................................... 403 Configuration of Clock Output/Buzzer Output Controller.................................................... 404 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 404 Operations of Clock Output/Buzzer Output Controller ........................................................ 408 12.4.1 Operation as clock output............................................................................................................ 408 12.4.2 Operation as buzzer output ......................................................................................................... 408 CHAPTER 13 A/D CONVERTER ......................................................................................................... 409 13.1 13.2 13.3 13.4 Function of A/D Converter....................................................................................................... 409 Configuration of A/D Converter .............................................................................................. 410 Registers Used in A/D Converter............................................................................................ 412 A/D Converter Operations ....................................................................................................... 421 13.4.1 Basic operations of A/D converter ............................................................................................... 421 13.4.2 Input voltage and conversion results ........................................................................................... 422 13.4.3 A/D converter operation mode .................................................................................................... 424 13.5 How to Read A/D Converter Characteristics Table............................................................... 426 13.6 Cautions for A/D Converter ..................................................................................................... 428 CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 432 14.1 14.2 14.3 14.4 Functions of Serial Interface UART0 ...................................................................................... 432 Configuration of Serial Interface UART0................................................................................ 433 Registers Controlling Serial Interface UART0....................................................................... 436 Operation of Serial Interface UART0 ...................................................................................... 441 14.4.1 Operation stop mode................................................................................................................... 441 14.4.2 Asynchronous serial interface (UART) mode .............................................................................. 442 14.4.3 Dedicated baud rate generator.................................................................................................... 448 14.4.4 Calculation of baud rate .............................................................................................................. 449 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 13 CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 453 15.1 15.2 15.3 15.4 Functions of Serial Interface UART6 ...................................................................................... 453 Configuration of Serial Interface UART6................................................................................ 457 Registers Controlling Serial Interface UART6....................................................................... 460 Operation of Serial Interface UART6 ...................................................................................... 469 15.4.1 Operation stop mode................................................................................................................... 469 15.4.2 Asynchronous serial interface (UART) mode .............................................................................. 470 15.4.3 Dedicated baud rate generator.................................................................................................... 483 15.4.4 Calculation of baud rate .............................................................................................................. 484 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 490 16.1 16.2 16.3 16.4 Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 490 Configuration of Serial Interfaces CSI10 and CSI11 ............................................................. 491 Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................... 493 Operation of Serial Interfaces CSI10 and CSI11.................................................................... 499 16.4.1 Operation stop mode................................................................................................................... 499 16.4.2 3-wire serial I/O mode ................................................................................................................. 500 CHAPTER 17 SERIAL INTERFACE CSIA0........................................................................................ 512 17.1 17.2 17.3 17.4 Functions of Serial Interface CSIA0 ....................................................................................... 512 Configuration of Serial Interface CSIA0 ................................................................................. 513 Registers Controlling Serial Interface CSIA0 ........................................................................ 515 Operation of Serial Interface CSIA0........................................................................................ 524 17.4.1 Operation stop mode................................................................................................................... 524 17.4.2 3-wire serial I/O mode ................................................................................................................. 525 17.4.3 3-wire serial I/O mode with automatic transmit/receive function.................................................. 530 CHAPTER 18 SERIAL INTERFACE IIC0............................................................................................ 550 18.1 18.2 18.3 18.4 Functions of Serial Interface IIC0 ........................................................................................... 550 Configuration of Serial Interface IIC0 ..................................................................................... 553 Registers to Control Serial Interface IIC0 .............................................................................. 556 I2C Bus Mode Functions........................................................................................................... 569 18.4.1 Pin configuration ......................................................................................................................... 569 2 18.5 I C Bus Definitions and Control Methods .............................................................................. 570 18.5.1 Start conditions ........................................................................................................................... 570 18.5.2 Addresses ................................................................................................................................... 571 18.5.3 Transfer direction specification.................................................................................................... 571 18.5.4 Acknowledge (ACK) .................................................................................................................... 572 18.5.5 Stop condition ............................................................................................................................. 573 18.5.6 Wait ............................................................................................................................................. 574 18.5.7 Canceling wait ............................................................................................................................. 576 18.5.8 Interrupt request (INTIIC0) generation timing and wait control.................................................... 576 18.5.9 Address match detection method ................................................................................................ 577 18.5.10 Error detection........................................................................................................................... 577 18.5.11 Extension code.......................................................................................................................... 578 18.5.12 Arbitration.................................................................................................................................. 579 18.5.13 Wakeup function........................................................................................................................ 580 18.5.14 Communication reservation....................................................................................................... 581 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 14 18.5.15 Cautions .................................................................................................................................... 584 18.5.16 Communication operations........................................................................................................ 585 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence................................................................. 593 18.6 Timing Charts ........................................................................................................................... 614 CHAPTER 19 MULTIPLIER/DIVIDER ................................................................................................... 621 19.1 19.2 19.3 19.4 Functions of Multiplier/Divider................................................................................................ 621 Configuration of Multiplier/Divider ......................................................................................... 621 Register Controlling Multiplier/Divider................................................................................... 625 Operations of Multiplier/Divider.............................................................................................. 626 19.4.1 Multiplication operation................................................................................................................ 626 19.4.2 Division operation........................................................................................................................ 628 CHAPTER 20 INTERRUPT FUNCTIONS............................................................................................. 630 20.1 20.2 20.3 20.4 Interrupt Function Types ......................................................................................................... 630 Interrupt Sources and Configuration ..................................................................................... 630 Registers Controlling Interrupt Functions............................................................................. 635 Interrupt Servicing Operations ............................................................................................... 656 20.4.1 Maskable interrupt acknowledgment ........................................................................................... 656 20.4.2 Software interrupt request acknowledgment ............................................................................... 658 20.4.3 Multiple interrupt servicing........................................................................................................... 659 20.4.4 Interrupt request hold .................................................................................................................. 662 CHAPTER 21 KEY INTERRUPT FUNCTION ..................................................................................... 663 21.1 Functions of Key Interrupt ...................................................................................................... 663 21.2 Configuration of Key Interrupt ................................................................................................ 664 21.3 Register Controlling Key Interrupt ......................................................................................... 665 CHAPTER 22 STANDBY FUNCTION .................................................................................................. 666 22.1 Standby Function and Configuration ..................................................................................... 666 22.1.1 Standby function ......................................................................................................................... 666 22.1.2 Registers controlling standby function......................................................................................... 667 22.2 Standby Function Operation ................................................................................................... 669 22.2.1 HALT mode ................................................................................................................................. 669 22.2.2 STOP mode ................................................................................................................................ 674 CHAPTER 23 RESET FUNCTION........................................................................................................ 681 23.1 Register for Confirming Reset Source ................................................................................... 691 CHAPTER 24 POWER-ON-CLEAR CIRCUIT...................................................................................... 692 24.1 24.2 24.3 24.4 Functions of Power-on-Clear Circuit...................................................................................... 692 Configuration of Power-on-Clear Circuit ............................................................................... 693 Operation of Power-on-Clear Circuit ...................................................................................... 693 Cautions for Power-on-Clear Circuit ...................................................................................... 696 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 15 CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 698 25.1 25.2 25.3 25.4 Functions of Low-Voltage Detector........................................................................................ 698 Configuration of Low-Voltage Detector ................................................................................. 699 Registers Controlling Low-Voltage Detector......................................................................... 699 Operation of Low-Voltage Detector ........................................................................................ 702 25.4.1 When used as reset .................................................................................................................... 703 25.4.2 When used as interrupt ............................................................................................................... 708 25.5 Cautions for Low-Voltage Detector ........................................................................................ 713 CHAPTER 26 OPTION BYTE............................................................................................................... 716 26.1 Functions of Option Bytes ...................................................................................................... 716 26.2 Format of Option Byte.............................................................................................................. 717 CHAPTER 27 FLASH MEMORY .......................................................................................................... 721 27.1 27.2 27.3 27.4 27.5 27.6 Internal Memory Size Switching Register .............................................................................. 721 Internal Expansion RAM Size Switching Register ................................................................ 722 Writing with Flash Memory Programmer ............................................................................... 724 Programming Environment ..................................................................................................... 724 Communication Mode .............................................................................................................. 725 Connection of Pins on Board.................................................................................................. 727 27.6.1 FLMD0 pin................................................................................................................................... 728 27.6.2 Serial interface pins..................................................................................................................... 728 27.6.3 RESET pin .................................................................................................................................. 730 27.6.4 Port pins ...................................................................................................................................... 730 27.6.5 REGC pin .................................................................................................................................... 730 27.6.6 Other signal pins ......................................................................................................................... 731 27.6.7 Power supply............................................................................................................................... 731 27.7 Programming Method .............................................................................................................. 732 27.7.1 Controlling flash memory............................................................................................................. 732 27.7.2 Flash memory programming mode.............................................................................................. 732 27.7.3 Selecting communication mode .................................................................................................. 733 27.7.4 Communication commands......................................................................................................... 734 27.8 Security Settings ...................................................................................................................... 735 27.9 Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) ...... 737 27.10 Flash Memory Programming by Self-Programming ........................................................... 739 27.10.1 Boot swap function .................................................................................................................... 753 27.11 Creating ROM Code to Place Order for Previously Written Product ................................ 755 27.11.1 Procedure for using ROM code to place an order ..................................................................... 755 CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY)................. 756 28.1 Connecting QB-MINI2 to PD78F05xxD and 78F05xxDA ..................................................... 756 28.2 Reserved Area Used by QB-MINI2 .......................................................................................... 758 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 16 CHAPTER 29 INSTRUCTION SET....................................................................................................... 759 29.1 Conventions Used in Operation List ...................................................................................... 759 29.1.1 Operand identifiers and specification methods............................................................................ 759 29.1.2 Description of operation column .................................................................................................. 760 29.1.3 Description of flag operation column ........................................................................................... 760 29.2 Operation List ........................................................................................................................... 761 29.3 Instructions Listed by Addressing Type................................................................................ 769 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) ................................... 772 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) .................................... 802 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +110C) ........830 CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C) ........859 CHAPTER 34 PACKAGE DRAWINGS ................................................................................................ 888 34.1 34.2 34.3 34.4 34.5 78K0/KB2................................................................................................................................... 888 78K0/KC2................................................................................................................................... 891 78K0/KD2................................................................................................................................... 896 78K0/KE2 ................................................................................................................................... 898 78K0/KF2 ................................................................................................................................... 908 CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS........................................................... 912 CHAPTER 36 CAUTIONS FOR WAIT................................................................................................. 917 36.1 Cautions for Wait...................................................................................................................... 917 36.2 Peripheral Hardware That Generates Wait ............................................................................ 918 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 920 A.1 Software Package ...................................................................................................................... 923 A.2 Language Processing Software ............................................................................................... 923 A.3 Flash Memory Programming Tools.......................................................................................... 924 A.3.1 When using flash memory programmer FG-FP5, FL-PR5, FG-FP4, and FL-PR4 ........................ 924 A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................. 925 A.4 Debugging Tools (Hardware).................................................................................................... 925 A.4.1 When using in-circuit emulator QB-78K0KX2 ............................................................................... 925 A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................. 927 A.5 Debugging Tools (Software)..................................................................................................... 928 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 17 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 929 APPENDIX C REGISTER INDEX ......................................................................................................... 936 C.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 936 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 940 APPENDIX D LIST OF CAUTIONS............................................................................................... 944 APPENDIX E REVISION HISTORY...................................................................................................... 974 E.1 Major Revisions in This Edition................................................................................................ 974 E.2 Revision History of Preceding Editions................................................................................... 975 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 18 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 78K0/Kx2 RENESAS MCU CHAPTER 1 OUTLINE 1.1 Differences Between Conventional-specification Products (PD78F05xx and 78F05xxD) and Expanded-specification Products (PD78F05xxA and 78F05xxDA) The differences between the conventional-specification products (PD78F05xx and 78F05xxD) and expandedspecification products (PD78F05xxA and 78F05xxDA) of the 78K0/Kx2 microcontrollers are described below. * A/D conversion time * X1 oscillator characteristics * Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width (AC characteristics) * The number of flash memory rewrites and retention time * Processing time of the self programming library * Interrupt response time of the self programming library R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 19 78K0/Kx2 CHAPTER 1 OUTLINE 1.1.1 A/D conversion time (1) Conventional-specification products (PD78F05xx and 78F05xxD) Parameter Conversion time Symbol tCONV Conditions 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Note MIN. MAX. Unit 6.1 36.7 s 12.2 36.7 s 27 66.6 s MIN. MAX. Unit 6.1 66.6 s 12.2 66.6 s 27 66.6 s TYP. (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) Parameter Conversion time Symbol tCONV Conditions 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Note Note Standard and (A) grade products only 1.1.2 X1 oscillator characteristics (1) Conventional-specification products (PD78F05xx and 78F05xxD) Resonator Parameter Conditions Ceramic X1 clock 4.0 V VDD 5.5 V resonator oscillation 2.7 V VDD < 4.0 V frequency (fX) 1.8 V VDD < 2.7 V MIN. MAX. Unit Note 2 20.0 MHz Note 2 10.0 1.0 1.0 Note 1 1.0 5.0 (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) Resonator Parameter Conditions Ceramic X1 clock 2.7 V VDD 5.5 V resonator oscillation 1.8 V VDD < 2.7 V MIN. Note 2 1.0 Note 1 1.0 TYP. MAX. Unit 20.0 MHz 5.0 frequency (fX) Notes 1. Standard and (A) grade products only 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 20 78K0/Kx2 1.1.3 CHAPTER 1 OUTLINE Time Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width (AC characteristics) (1) Conventional-specification products (PD78F05xx and 78F05xxD) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions MIN. Main system clock (fXP) 4.0 V VDD 5.5 V operation 2.7 V VDD < 4.0 V fPRS fPRS = fXH (XSEL = 1) fEXCLK tEXCLKH, tEXCLKL 32 s 0.2 32 s s 4.0 V VDD 5.5 V 20 MHz 2.7 V VDD < 4.0 V 10 MHz 1.8 V VDD < 2.7 V 0.4 Note 3 114 Notes 1, 5 5 MHz 7.6 8.4 MHz 7.6 10.4 MHz Note 6 20.0 MHz Note 6 10.0 MHz 5.0 MHz 1.0 2.7 V VDD < 4.0 V 1.0 Note 1 1.0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 122 Note 1 4.0 V VDD 5.5 V 1.8 V VDD < 2.7 V External main system clock input high-level width, low-level width 0.1 s Note 2 1.8 V VDD < 2.7 V External main system clock frequency Unit 32 Note 1 2.7 V VDD 5.5 V fPRS = fRH (XSEL = 0) MAX. 125 1.8 V VDD < 2.7 V Subsystem clock (fSUB) operation Peripheral hardware clock frequency TYP. Note 1 24 ns 48 ns 96 ns (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fXP) 2.7 V VDD 5.5 V Note 1 operation 1.8 V VDD < 2.7 V Subsystem clock (fSUB) operation Peripheral hardware clock frequency fPRS fEXCLK External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL Notes 1. 2. 3. 4. 5. 6. 2.7 V VDD < 4.0 V Note 4 1.8 V VDD < 2.7 V Note 1 1.8 V VDD < 2.7 V Notes 1, 5 Note 1 Note 1 122 MAX. Unit 32 s 32 s 125 s 20 MHz 20 MHz 5 MHz 7.6 8.4 MHz 7.6 10.4 MHz 1.0 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V Note 3 114 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V Note 2 TYP. 0.1 0.4 4.0 V VDD 5.5 V fPRS = fXH (XSEL = 1) fPRS = fRH (XSEL = 0) External main system clock frequency MIN. Note 6 1.0 20.0 MHz 5.0 MHz 24 ns 96 ns Standard and (A) grade products only The 78K0/KB2 is not provided with a subsystem clock. 0.38 s when operating with the 8 MHz internal oscillator. Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fXH/2 (10 MHz) or less. The multiplier/divider, however, can operate on fXH (20 MHz). Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fRH/2 or less. 2.0 MHz (MIN.) when using UART6 during on-board programming. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 21 78K0/Kx2 CHAPTER 1 OUTLINE 1.1.4 Number of flash memory rewrites and retention time Item Conventional-specification Expanded-specification Products (PD78F05xxA and 78F05xxDA) Products (PD78F05xx and 78F05xxD) Number of rewrites per chip 100 times (Retention: 10 (retention time) years) * When a flash memory programmer is used, and the libraries Note 1 provided by Renesas Electronics are used 1,000 times (Retention: 15 years) * For program update * When the EEPROM emulation libraries Note 2 10,000 times provided by Renesas Electronics are used (Retention: 5 * The rewritable ROM size: 4 KB years) * For data update Conditions other than the above Note 3 100 times (Retention: 10 years) Notes 1. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) is excluded. 2. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) is excluded. 3. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) are used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 22 78K0/Kx2 CHAPTER 1 OUTLINE 1.1.5 Processing time for self programming library (1) Conventional-specification products (PD78F05xx and 78F05xxD) (1/3) <1> When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 4.25 Initialize library 977.75 Mode check library Block blank check library 753.875 753.125 12770.875 12765.875 Block erase library 36909.5 356318 36904.5 356296.25 Word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375) Block verify library 25618.875 25613.875 Self programming end library Get information library 4.25 Option value: 03H 871.25 (871.375) 866 (866.125) Option value: 04H 863.375 (863.5) 858.125 (858.25) Option value: 05H 1024.75 (1043.625) 1037.5 (1038.375) Set information library 105524.75 790809.375 105523.75 EEPROM write library 1496.5 2691.5 1489.5 790808.375 2684.5 (1496.875) (2691.875) (1489.875) (2684.875) <2> When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 4.25 Initialize library 443.5 Mode check library Block blank check library Block erase library 36363.25 Word write library 219.625 218.875 12236.625 12231.625 355771.75 36358.25 679.75 1874.75 672.75 1867.75 (680.125) (1875.125) (673.125) (1868.125) Block verify library 25072.625 25067.625 Self programming end library Get information library 355750 4.25 Option value: 03H 337 (337.125) 331.75 (331.875) Option value: 04H 329.125 (239.25) 323.875 (324) Option value: 05H 502.25 (503.125) 497 (497.875) Set information library 104978.5 541143.125 104977.5 EEPROM write library 962.25 2157.25 955.25 541142.125 2150.25 (962.625) (2157.625) (955.625) (2150.625) Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 23 78K0/Kx2 CHAPTER 1 OUTLINE (1) Conventional-specification products (PD78F05xx and 78F05xxD) (2/3) <3> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 34/fCPU Initialize library 49/fCPU + 485.8125 Mode check library Block blank check library Block erase library Word write library Block verify library 35/fCPU + 374.75 29/fCPU + 374.75 174/fCPU + 6382.0625 134/fCPU + 6382.0625 174/fCPU + 174/fCPU + 134/fCPU + 134/fCPU + 31093.875 298948.125 31093.875 298948.125 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 644.125 1491.625 644.125 1491.625 174/fCPU + 13448.5625 Self programming end library Get information library 134/fCPU + 13448.5625 34/fCPU Option value: 03H 171 (172 )/fCPU + 432.4375 129 (130)/fCPU + 432.4375 Option value: 04H 181 (182)/fCPU + 427.875 139 (140)/fCPU + 427.875 Option value: 05H 404 (411)/fCPU + 496.125 Set information library 75/fCPU + 75/fCPU + 652400 79157.6875 EEPROM write library 362 (369)/fCPU + 496.125 67fCPU + 67fCPU + 652400 79157.6875 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 799.875 1647.375 799.875 1647.375 Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. fCPU: CPU operation clock frequency 4. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 24 78K0/Kx2 CHAPTER 1 OUTLINE (1) Conventional-specification products (PD78F05xx and 78F05xxD) (3/3) <4> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 34/fCPU Initialize library 49/fCPU + 224.6875 Mode check library Block blank check library Block erase library Word write library Block verify library 35/fCPU + 113.625 29/fCPU + 113.625 174/fCPU + 6120.9375 134/fCPU + 6120.9375 174/fCPU + 174/fCPU + 134/fCPU + 30820.75 298675 30820.75 298675 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 383 1230.5 383 1230.5 174/fCPU + 13175.4375 Self programming end library Get information library 134/fCPU + 134/fCPU + 13175.4375 34/fCPU Option value: 03H 171 (172)/fCPU + 171.3125 Option value: 04H 181 (182)/fCPU + 166.75 139 (140)/fCPU + 166.75 Option value: 05H 404 (411)/fCPU + 231.875 362 (369)/fCPU + 231.875 Set information library EEPROM write library 129 (130)/fCPU + 171.3125 75/fCPU + 75/fCPU + 67/fCPU + 67/fCPU + 78884.5625 527566.875 78884.5625 527566.875 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 538.75 1386.25 538.75 1386.25 Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. fCPU: CPU operation clock frequency 4. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 25 78K0/Kx2 CHAPTER 1 OUTLINE (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) (1/3) <1> When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Self programming start library Initialize library Mode check library Block blank check library Max. Static Model of C Compiler/Assembler Min. Max. 4.0 4.5 4.0 4.5 1105.9 1106.6 1105.9 1106.6 905.7 906.1 904.9 905.3 12776.1 12778.3 12770.9 12772.6 Block erase library 26050.4 349971.3 26045.3 349965.6 Word write library 1180.1 + 203 x w 1184.3 + 2241 1172.9 + 203 x w 1176.3 + 2241 Block verify library 25337.9 25340.2 25332.8 25334.5 4.0 4.5 4.0 4.5 Option value: 03H 1072.9 1075.2 1067.5 1069.1 Option value: 04H 1060.2 1062.6 1054.8 1056.6 Option value: 05H 1023.8 1028.2 1018.3 1022.1 Set information library 70265.9 759995.0 70264.9 759994.0 EEPROM write library 1316.8 + 347 x w 1320.9 + 2385 1309.0 + 347 x w 1312.4 + 2385 xw Self programming end library Get information library xw xw xw <2> When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Self programming start library Initialize library Mode check library Static Model of C Compiler/Assembler Min. Max. Min. 4.0 4.5 4.0 Max. 4.5 449.5 450.2 449.5 450.2 249.3 249.7 248.6 248.9 Block blank check library 12119.7 12121.9 12114.6 12116.3 Block erase library 25344.7 349266.4 25339.6 349260.8 Word write library 445.8 + 203 x w 449.9 + 2241 x w 438.5 + 203 x w 441.9 + 2241 x w Block verify library 24682.7 24684.9 24677.6 24679.3 4.0 4.5 4.0 4.5 Option value: 03H 417.6 419.8 412.1 413.8 Option value: 04H 405.0 407.4 399.5 401.3 Option value: 05H 367.4 371.8 361.9 365.8 Set information library 69569.3 759297.3 69568.3 759296.2 EEPROM write library 795.1 + 347 x w 799.3 + 2385 x w 787.4 + 347 x w 790.8 + 2385 x w Self programming end library Get information library Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 26 78K0/Kx2 CHAPTER 1 OUTLINE (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) (2/3) <3> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Min. Self programming start library Max. 34/fCPU Initialize library 55/fCPU + 594 Mode check library Block blank check library Block erase library 36/fCPU + 495 30/fCPU + 495 179/fCPU + 6429 136/fCPU + 6429 179/fCPU + 19713 179/fCPU + 136/fCPU + 19713 136/fCPU + 268079 Word write library 268079 333/fCPU + 647 + 333/fCPU + 647 + 272/fCPU + 647 + 272/fCPU + 647 + 136 x w 1647 x w 136 x w 1647 x w Block verify library 179/fCPU + 13284 Self programming end library Get information library 136/fCPU + 13284 34/fCPU Option value: 03H 180/fCPU + 581 134fCPU + 581 Option value: 04H 190/fCPU + 574 144/fCPU + 574 350/fCPU + 535 Option value: 05H 304/fCPU + 535 Set information library 80/fCPU + 43181 80/fCPU + 572934 72/fCPU + 43181 72/fCPU + 572934 EEPROM write library 333/fCPU + 729 + 333/fCPU + 729 + 268/fCPU + 729 + 268/fCPU + 729 + 209 x w 1722 x w 209 x w 1722 x w Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. fCPU: CPU operation clock frequency 4. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 27 78K0/Kx2 CHAPTER 1 OUTLINE (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) (3/3) <4> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Min. Self programming start library Max. 34/fCPU Initialize library 55/fCPU + 272 Mode check library Block blank check library Block erase library 36/fCPU + 173 30/fCPU + 173 179/fCPU + 6108 136/fCPU + 6108 179/fCPU + 19371 179/fCPU + 136/fCPU + 19371 136/fCPU + 267738 Word write library 267738 333/fCPU + 247 + 333/fCPU + 247 + 272/fCPU + 247 + 272/fCPU + 247 + 136 x w 1647 x w 136 x w 1647 x w Block verify library 179/fCPU + 12964 Self programming end library Get information library 136/fCPU + 12964 34/fCPU Option value: 03H 180/fCPU + 261 134/fCPU + 261 Option value: 04H 190/fCPU + 254 144/fCPU + 254 Option value: 05H 350/fCPU + 213 304/fCPU + 213 Set information library 80/fCPU + 42839 80/fCPU + 572592 72/fCPU + 42839 72/fCPU + 572592 EEPROM write library 333/fCPU + 516 + 333/fCPU + 516 + 268/fCPU + 516 + 268/fCPU + 516 + 209 x w 1722 x w 209 x w 1722 x w Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. fCPU: CPU operation clock frequency 4. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 28 78K0/Kx2 CHAPTER 1 OUTLINE 1.1.6 Interrupt response time for self programming library (1) Conventional-specification products (PD78F05xx and 78F05xxD) (1/2) <1> When internal high-speed oscillation clock is used Interrupt Response Time (s (Max.)) Library Name Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 933.6 668.6 927.9 Block erase library 1026.6 763.6 1020.9 662.9 757.9 Word write library 2505.8 1942.8 2497.8 1934.8 Block verify library 958.6 693.6 952.9 687.9 Set information library 476.5 211.5 475.5 210.5 EEPROM write library 2760.8 2168.8 2759.5 2167.5 Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) <2> When high-speed system clock is used (normal model of C compiler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 179/fCPU + 507 179/fCPU + 407 179/fCPU + 1650 Block erase library 179/fCPU + 559 179/fCPU + 460 179/fCPU + 1702 179/fCPU + 767 Word write library 333/fCPU + 1589 333/fCPU + 1298 333/fCPU + 2732 333/fCPU + 1605 Block verify library 179/fCPU + 518 179/fCPU + 418 179/fCPU + 1661 179/fCPU + 725 Set information library 80/fCPU + 370 80/fCPU + 165 80/fCPU + 1513 80/fCPU + 472 29/fCPU + 1759 29/fCPU + 1468 29/fCPU + 1759 29/fCPU + 1468 333/fCPU + 834 333/fCPU + 512 333/fCPU + 2061 333/fCPU + 873 Note EEPROM write library 179/fCPU + 714 Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 29 78K0/Kx2 CHAPTER 1 OUTLINE (1) Conventional-specification products (PD78F05xx and 78F05xxD) (2/2) <3> When high-speed system clock is used (static model of C compiler/assembler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 136/fCPU + 507 136/fCPU + 407 136/fCPU + 1650 Block erase library 136/fCPU + 559 136/fCPU + 460 136/fCPU + 1702 136/fCPU + 767 Word write library 272/fCPU + 1589 272/fCPU + 1298 272/fCPU + 2732 272/fCPU + 1605 Block verify library 136/fCPU + 518 136/fCPU + 418 136/fCPU + 1661 136/fCPU + 725 Set information library Note EEPROM write library 136/fCPU + 714 72/fCPU + 370 72/fCPU + 165 72/fCPU + 1513 72/fCPU + 472 19/fCPU + 1759 19/fCPU + 1468 19/fCPU + 1759 19/fCPU + 1468 268/fCPU + 834 268/fCPU + 512 268/fCPU + 2061 268/fCPU + 873 Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 30 78K0/Kx2 CHAPTER 1 OUTLINE (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) (1/2) <1> When internal high-speed oscillation clock is used Interrupt Response Time (s (Max.)) Library Name Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 1100.9 431.9 1095.3 426.3 Block erase library 1452.9 783.9 1447.3 778.3 Word write library 1247.2 579.2 1239.2 571.2 Block verify library 1125.9 455.9 1120.3 450.3 Set information library 906.9 312.0 905.8 311.0 EEPROM write library 1215.2 547.2 1213.9 545.9 Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) <2> When high-speed system clock is used (normal model of C compiler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 179/fCPU + 567 179/fCPU + 246 179/fCPU + 1708 179/fCPU + 569 Block erase library 179/fCPU + 780 179/fCPU + 459 179/fCPU + 1921 179/fCPU + 782 Word write library 333/fCPU + 763 333/fCPU + 443 333/fCPU + 1871 333/fCPU + 767 Block verify library 179/fCPU + 580 179/fCPU + 259 179/fCPU + 1721 179/fCPU + 582 Set information library 80/fCPU + 456 80/fCPU + 200 80/fCPU + 1598 80/fCPU + 459 29/fCPU + 767 29/fCPU + 447 29/fCPU + 767 29/fCPU + 447 333/fCPU + 696 333/fCPU + 376 333/fCPU + 1838 333/fCPU + 700 Note EEPROM write library Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 31 78K0/Kx2 CHAPTER 1 OUTLINE (2) Expanded-specification products (PD78F05xxA and 78F05xxDA) (2/2) <3> When high-speed system clock is used (static model of C compiler/assembler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 136/fCPU + 567 136/fCPU + 246 136/fCPU + 1708 136/fCPU + 569 Block erase library 136/fCPU + 780 136/fCPU + 459 136/fCPU + 1921 136/fCPU + 782 Word write library 272/fCPU + 763 272/fCPU + 443 272/fCPU + 1871 272/fCPU + 767 Block verify library 136/fCPU + 580 136/fCPU + 259 136/fCPU + 1721 136/fCPU + 582 72/fCPU + 456 72/fCPU + 200 72/fCPU + 1598 72/fCPU + 459 19/fCPU + 767 19/fCPU + 447 19/fCPU + 767 19/fCPUv + 447 268/fCPU + 696 268/fCPU + 376 268/fCPU + 1838 268/fCPU + 700 Set information library Note EEPROM write library Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 32 78K0/Kx2 CHAPTER 1 OUTLINE 1.2 Features { Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with high-speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) { General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) { ROM (flash memory), RAM capacities ROM Note 128 KB 96 KB 60 KB High- Expansion Note Speed RAM Note RAM 1 KB 1 KB 1 KB 78K0/KD2 78K0/KE2 78K0/KF2 30/36 pins 78K0/KB2 38/44 pins 48 pins 52 pins 64 pins 80 pins - - - PD78F0527D, 78F0527DA PD78F0537D, 78F0537DA PD78F0547D, 78F0547DA PD78F0527, PD78F0537, PD78F0547 78F0527A 78F0537A 78F0547A PD78F0526, PD78F0536, PD78F0546, 78F0526A 78F0536A 78F0546A PD78F0515D, PD78F0525, PD78F0535, PD78F0545, 78F0515DA 78F0525A 78F0535A 78F0545A PD78F0514, PD78F0524, PD78F0534, PD78F0544, 78F0514A 78F0524A 78F0534A 78F0544A PD78F0513, PD78F0523, PD78F0533, 78F0513A 78F0523A 78F0533A 6 KB - 4 KB - 2 KB 78K0/KC2 - - - PD78F0515, 78F0515A 48 KB 32 KB 24 KB 16 KB 8 KB 1 KB 1 KB 1 KB 768 B 512 B - 1 KB - - - - - PD78F0503D, 78F0503DA PD78F0513D, 78F0513DA PD78F0503, PD78F0513, 78F0503A 78F0513A PD78F0502, PD78F0512, PD78F0512, PD78F0522, PD78F0532, 78F0502A 78F0512A 78F0512A 78F0522A 78F0532A PD78F0501, PD78F0511, PD78F0511, PD78F0521, PD78F0531, 78F0501A 78F0511A 78F0511A 78F0521A 78F0531A PD78F0500, - - - - - - - - 78F0500A Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). For IMS and IXS, see 27.1 Internal Memory Size Switching Register and 27.2 Internal Expansion RAM Size Switching Register. { Buffer RAM: 32 bytes (can be used for transfer in CSI with automatic transmit/receive function) (78K0/KF2 only) { On-chip single-power-supply flash memory { Self-programming (with boot swap function) { On-chip debug function (PD78F05xxD and 78F05xxDA only)Note Note The PD78F05xxD and 78F05xxDA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. { On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) { On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 33 78K0/Kx2 CHAPTER 1 OUTLINE { On-chip 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V) { On-chip multiplier/divider (16 bits x 16 bits, 32 bits/16 bits), key interrupt function, clock output/buzzer output controller, I/O ports, timer, and serial interface { Power supply voltage * Standard products, (A) grade products: VDD = 1.8 to 5.5 V * (A2) grade products: VDD = 2.7 to 5.5 V { Operating ambient temperature * Standard products, (A) grade products: TA = -40 to +85C * (A2) grade products: Remark TA = -40 to +125C The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. 1.3 Applications { Automotive equipment (compatible with (A) and (A2) grade products) * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control { Car audio { AV equipment, home audio { PC peripheral equipment (keyboards, etc.) { Household electrical appliances * Air conditioners * Microwave ovens, electric rice cookers { Industrial equipment * Pumps * Vending machines * FA (Factory Automation) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 34 78K0/Kx2 CHAPTER 1 OUTLINE 1.4 Ordering Information [Part Number] PD78F05xy X X XX (X) - XXX - XX Semiconductor A AX, G Lead- Product contains no lead in any area free Product contains no lead in any area (Terminal finish is Ni/Pd/Au plating) Quality Grade None Standard (TA = - 40 to +85 C) (A), A Special (TA = - 40 to +85 C) (A2), A2 Special (TA = - 40 to +125 C) Package Type 50y MC-5A4 (KB2) MC-CAB FC-AA3 MC-GAA 51y (KC2) GB-UES 30-pin plastic SSOP (7.62 mm (300)) 36-pin plastic FLGA (4x4) 38-pin plastic SSOP (7.62 mm (300)) 44-pin plastic LQFP (10x10) GB-GAF GA-8EU Product Type 48-pin plastic LQFP (fine pitch) (7x7) GA-GAM None Conventional-specification products 52y GB-UET (KD2) GB-GAG 52-pin plastic LQFP (10x10) A Expanded-specification products 53y (KE2) 64-pin plastic LQFP (fine pitch) (10x10) GB-UEU GB-GAH GC-UBS None D On-chip Debug Function GC-GAL Not mounted GK-UET Mounted GK-GAJ GA-9EV 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (fine pitch) (7x7) GA-HAB 54y (KF2) FC-AA1 64-pin plastic FLGA (5x5) F1-AA2 64-pin plastic FBGA (4x4) GC-UBT 80-pin plastic LQFP (14x14) GC-GAD GK-8EU 80-pin plastic LQFP (fine pitch) (12x12) GK-GAK Product Type F Flash memory version 5x1 High-speed Expansion RAM Flash Memory RAM Capacity Capacity Capacity _ 512 bytes 8 KB _ 768 bytes 16 KB 5x2 1 KB _ 24 KB 5x3 1 KB _ 32 KB 5x4 1 KB 1 KB 48 KB 5x5 1 KB 2 KB 60 KB 5x6 1 KB 4 KB 96 KB 5x7 1 KB 6 KB 128 KB 5x0 Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by Renesas Electronics to know the specification of quality grade on the devices and its recommended applications. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 35 78K0/Kx2 CHAPTER 1 OUTLINE [List of Part Number] (1/6) 78K0/Kx2 Package Microcontrollers 78K0/KB2 Product Quality type grace 30-pin plastic Conventional- Standard PD78F0500MC-5A4-A, 78F0501MC-5A4-A, SSOP (7.62 mm specification 78F0502MC-5A4-A, 78F0503MC-5A4-A, (300)) products products 78F0503DMC-5A4-A Note (A) grade PD78F0500MC(A)-CAB-AX, 78F0501MC(A)-CAB-AX, products 78F0502MC(A)-CAB-AX, 78F0503MC(A)-CAB-AX (A2) grade PD78F0500MC(A2)-CAB-AX, 78F0501MC(A2)-CAB-AX, products 78F0502MC(A2)-CAB-AX, 78F0503MC(A2)-CAB-AX Expanded- Standard PD78F0500AMC-CAB-AX, 78F0501AMC-CAB-AX, specification products 78F0502AMC-CAB-AX, 78F0503AMC-CAB-AX, 78F0503DAMC-CAB-AX products Note (A) grade PD78F0500AMCA-CAB-G, 78F0501AMCA-CAB-G, products 78F0502AMCA-CAB-G, 78F0503AMCA-CAB-G (A2) grade PD78F0500AMCA2-CAB-G, 78F0501AMCA2-CAB-G, products 78F0502AMCA2-CAB-G, 78F0503AMCA2-CAB-G 36-pin plastic Conventional- Standard PD78F0500FC-AA3-A, 78F0501FC-AA3-A, FLGA (4x4) specification 78F0502FC-AA3-A, 78F0503FC-AA3-A, products products 78F0503DFC-AA3-A Note Expanded- Standard PD78F0500AFC-AA3-A, 78F0501AFC-AA3-A, specification products 78F0502AFC-AA3-A, 78F0503AFC-AA3-A, products 78K0/KC2 Part Number 78F0503DAFC-AA3-A Note 38-pin plastic Expanded- Standard PD78F0511AMC-GAA-AX, 78F0512AMC-GAA-AX, SSOP (7.62 mm specification products 78F0513AMC-GAA-AX, 78F0513DAMC-GAA-AX (300)) products (A) grade PD78F0511AMCA-GAA-G, 78F0512AMCA-GAA-G, products 78F0513AMCA-GAA-G (A2) grade PD78F0511AMCA2-GAA-G, 78F0512AMCA2-GAA-G, products 78F0513AMCA2-GAA-G Note 44-pin plastic Conventional- Standard PD78F0511GB-UES-A, 78F0512GB-UES-A, LQFP (10x10) specification products 78F0513GB-UES-A, 78F0513DGB-UES-A products (A) grade PD78F0511GB(A)-GAF-AX, 78F0512GB(A)-GAF-AX, products 78F0513GB(A)-GAF-AX (A2) grade PD78F0511GB(A2)-GAF-AX, 78F0512GB(A2)-GAF-AX, products 78F0513GB(A2)-GAF-AX Expanded- Standard PD78F0511AGB-GAF-AX, 78F0512AGB-GAF-AX, specification products 78F0513AGB-GAF-AX, 78F0513DAGB-GAF-AX products (A) grade PD78F0511AGBA-GAF-G, 78F0512AGBA-GAF-G, Note Note products 78F0513AGBA-GAF-G (A2) grade PD78F0511AGBA2-GAF-G, 78F0512AGBA2-GAF-G, products 78F0513AGBA2-GAF-G Note The PD78F0503D, 78F0503DA, 78F0513D, and 78F0513DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 36 78K0/Kx2 CHAPTER 1 OUTLINE (2/6) 78K0/Kx2 Package Microcontrollers 78K0/KC2 Product Quality type grace Part Number 48-pin plastic Conventional- Standard PD78F0511GA-8EU-A, 78F0512GA-8EU-A, LQFP (fine pitch) specification 78F0513GA-8EU-A, 78F0514GA-8EU-A, 78F0515GA-8EU-A, (7x7) products products 78F0515DGA-8EU-A Note (A) grade PD78F0511GA(A)-GAM-AX, 78F0512GA(A)-GAM-AX, products 78F0513GA(A)-GAM-AX, 78F0514GA(A)-GAM-AX, 78F0515GA(A)-GAM-AX (A2) grade PD78F0511GA(A2)-GAM-AX, 78F0512GA(A2)-GAM-AX, products 78F0513GA(A2)-GAM-AX, 78F0514GA(A2)-GAM-AX, 78F0515GA(A2)-GAM-AX Expanded- Standard PD78F0511AGA-GAM-AX, 78F0512AGA-GAM-AX, specification products 78F0513AGA-GAM-AX, 78F0514AGA-GAM-AX, 78F0515AGA-GAM-AX, 78F0515DAGA-GAM-AX products Note (A) grade PD78F0511AGAA-GAM-G, 78F0512AGAA-GAM-G, products 78F0513AGAA-GAM-G, 78F0514AGAA-GAM-G, 78F0515AGAA-GAM-G (A2) grade PD78F0511AGAA2-GAM-G, 78F0512AGAA2-GAM-G, products 78F0513AGAA2-GAM-G, 78F0514AGAA2-GAM-G, 78F0515AGAA2-GAM-G 78K0/KD2 52-pin plastic Conventional- Standard PD78F0521GB-UET-A, 78F0522GB-UET-A, LQFP (10x10) specification 78F0523GB-UET-A, 78F0524GB-UET-A, products products 78F0525GB-UET-A, 78F0526GB-UET-A, 78F0527GB-UET-A, 78F0527DGB-UET-A Note (A) grade PD78F0521GB(A)-GAG-AX, 78F0522GB(A)-GAG-AX, products 78F0523GB(A)-GAG-AX, 78F0524GB(A)-GAG-AX, 78F0525GB(A)-GAG-AX, 78F0526GB(A)-GAG-AX, 78F0527GB(A)-GAG-AX (A2) grade PD78F0521GB(A2)-GAG-AX, 78F0522GB(A2)-GAG-AX, products 78F0523GB(A2)-GAG-AX, 78F0524GB(A2)-GAG-AX, 78F0525GB(A2)-GAG-AX, 78F0526GB(A2)-GAG-AX, 78F0527GB(A2)-GAG-AX Expanded- Standard PD78F0521AGB-GAG-AX, 78F0522AGB-GAG-AX, specification products 78F0523AGB-GAG-AX, 78F0524AGB-GAG-AX, products 78F0525AGB-GAG-AX, 78F0526AGB-GAG-AX, 78F0527AGB-GAG-AX, 78F0527DAGB-GAG-AX Note (A) grade PD78F0521AGBA-GAG-G, 78F0522AGBA-GAG-G, products 78F0523AGBA-GAG-G, 78F0524AGBA-GAG-G, 78F0525AGBA-GAG-G, 78F0526AGBA-GAG-G, 78F0527AGBA-GAG-G (A2) grade PD78F0521AGBA2-GAG-G, 78F0522AGBA2-GAG-G, products 78F0523AGBA2-GAG-G, 78F0524AGBA2-GAG-G, 78F0525AGBA2-GAG-G, 78F0526AGBA2-GAG-G, 78F0527AGBA2-GAG-G Note The PD78F0515D, 78F0515DA, 78F0527D, and 78F0527DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 37 78K0/Kx2 CHAPTER 1 OUTLINE (3/6) 78K0/Kx2 Package Microcontrollers 78K0/KE2 Product Quality type grace Part Number 64-pin plastic Conventional- Standard PD78F0531GB-UEU-A, 78F0532GB-UEU-A, LQFP (fine pitch) specification 78F0533GB-UEU-A, 78F0534GB-UEU-A, (10x10) products products 78F0535GB-UEU-A, 78F0536GB-UEU-A, 78F0537GB-UEU-A, 78F0537DGB-UEU-A Note (A) grade PD78F0531GB(A)-GAH-AX, 78F0532GB(A)-GAH-AX, products 78F0533GB(A)-GAH-AX, 78F0534GB(A)-GAH-AX, 78F0535GB(A)-GAH-AX, 78F0536GB(A)-GAH-AX, 78F0537GB(A)-GAH-AX (A2) grade PD78F0531GB(A2)-GAH-AX, 78F0532GB(A2)-GAH-AX, products 78F0533GB(A2)-GAH-AX, 78F0534GB(A2)-GAH-AX, 78F0535GB(A2)-GAH-AX, 78F0536GB(A2)-GAH-AX, 78F0537GB(A2)-GAH-AX Expanded- Standard PD78F0531AGB-GAH-AX, 78F0532AGB-GAH-AX, specification products 78F0533AGB-GAH-AX, 78F0534AGB-GAH-AX, 78F0535AGB-GAH-AX, 78F0536AGB-GAH-AX, products 78F0537AGB-GAH-AX, 78F0537DAGB-GAH-AX Note (A) grade PD78F0531AGBA-GAH-G, 78F0532AGBA-GAH-G, products 78F0533AGBA-GAH-G, 78F0534AGBA-GAH-G, 78F0535AGBA-GAH-G, 78F0536AGBA-GAH-G, 78F0537AGBA-GAH-G (A2) grade PD78F0531AGBA2-GAH-G, 78F0532AGBA2-GAH-G, products 78F0533AGBA2-GAH-G, 78F0534AGBA2-GAH-G, 78F0535AGBA2-GAH-G, 78F0536AGBA2-GAH-G, 78F0537AGBA2-GAH-G Note The PD78F0537D and 78F0537DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 38 78K0/Kx2 CHAPTER 1 OUTLINE (4/6) 78K0/Kx2 Package Microcontrollers 78K0/KE2 Product Quality type grace Part Number 64-pin plastic Conventional- Standard PD78F0531GC-UBS-A, 78F0532GC-UBS-A, LQFP (14x14) specification 78F0533GC-UBS-A, 78F0534GC-UBS-A, products 78F0535GC-UBS-A, 78F0536GC-UBS-A, products 78F0537GC-UBS-A, 78F0537DGC-UBS-A Note (A) grade PD78F0531GC(A)-GAL-AX, 78F0532GC(A)-GAL-AX, products 78F0533GC(A)-GAL-AX, 78F0534GC(A)-GAL-AX, 78F0535GC(A)-GAL-AX, 78F0536GC(A)-GAL-AX, 78F0537GC(A)-GAL-AX (A2) grade PD78F0531GC(A2)-GAL-AX, 78F0532GC(A2)-GAL-AX, products 78F0533GC(A2)-GAL-AX, 78F0534GC(A2)-GAL-AX, 78F0535GC(A2)-GAL-AX, 78F0536GC(A2)-GAL-AX, 78F0537GC(A2)-GAL-AX Expanded- Standard PD78F0531AGC-GAL-AX, 78F0532AGC-GAL-AX, specification products 78F0533AGC-GAL-AX, 78F0534AGC-GAL-AX, 78F0535AGC-GAL-AX, 78F0536AGC-GAL-AX, products 78F0537AGC-GAL-AX, 78F0537DAGC-GAL-AX Note (A) grade PD78F0531AGCA-GAL-G, 78F0532AGCA-GAL-G, products 78F0533AGCA-GAL-G, 78F0534AGCA-GAL-G, 78F0535AGCA-GAL-G, 78F0536AGCA-GAL-G, 78F0537AGCA-GAL-G (A2) grade PD78F0531AGCA2-GAL-G, 78F0532AGCA2-GAL-G, products 78F0533AGCA2-GAL-G, 78F0534AGCA2-GAL-G, 78F0535AGCA2-GAL-G, 78F0536AGCA2-GAL-G, 78F0537AGCA2-GAL-G Note The PD78F0537D and 78F0537DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 39 78K0/Kx2 CHAPTER 1 OUTLINE (5/6) 78K0/Kx2 Package Microcontrollers 78K0/KE2 Product Quality type grace Part Number 64-pin plastic Conventional- Standard PD78F0531GK-UET-A, 78F0532GK-UET-A, LQFP (12x12) specification 78F0533GK-UET-A, 78F0534GK-UET-A, products products 78F0535GK-UET-A, 78F0536GK-UET-A, 78F0537GK-UET-A, 78F0537DGK-UET-A Note (A) grade PD78F0531GK(A)-GAJ-AX, 78F0532GK(A)-GAJ-AX, products 78F0533GK(A)-GAJ-AX, 78F0534GK(A)-GAJ-AX, 78F0535GK(A)-GAJ-AX, 78F0536GK(A)-GAJ-AX, 78F0537GK(A)-GAJ-AX (A2) grade PD78F0531GK(A2)-GAJ-AX, 78F0532GK(A2)-GAJ-AX, products 78F0533GK(A2)-GAJ-AX, 78F0534GK(A2)-GAJ-AX, 78F0535GK(A2)-GAJ-AX, 78F0536GK(A2)-GAJ-AX, 78F0537GK(A2)-GAJ-AX Expanded- Standard PD78F0531AGK-GAJ-AX, 78F0532AGK-GAJ-AX, specification products 78F0533AGK-GAJ-AX, 78F0534AGK-GAJ-AX, 78F0535AGK-GAJ-AX, 78F0536AGK-GAJ-AX, products 78F0537AGK-GAJ-AX, 78F0537DAGK-GAJ-AX Note (A) grade PD78F0531AGKA-GAJ-G, 78F0532AGKA-GAJ-G, products 78F0533AGKA-GAJ-G, 78F0534AGKA-GAJ-G, 78F0535AGKA-GAJ-G, 78F0536AGKA-GAJ-G, 78F0537AGKA-GAJ-G (A2) grade PD78F0531AGKA2-GAJ-G, 78F0532AGKA2-GAJ-G, products 78F0533AGKA2-GAJ-G, 78F0534AGKA2-GAJ-G, 78F0535AGKA2-GAJ-G, 78F0536AGKA2-GAJ-G, 78F0537AGKA2-GAJ-G 64-pin plastic Conventional- Standard TQFP (fine pitch) specification (7x7) products products PD78F0531GA-9EV-A, 78F0532GA-9EV-A, 78F0533GA-9EV-A, 78F0534GA-9EV-A, 78F0535GA-9EV-A, 78F0536GA-9EV-A, 78F0537GA-9EV-A, 78F0537DGA-9EV-A Note Expanded- Standard PD78F0531AGA-HAB-AX, 78F0532AGA-HAB-AX, specification products 78F0533AGA-HAB-AX, 78F0534AGA-HAB-AX, products 78F0535AGA-HAB-AX, 78F0536AGA-HAB-AX, 78F0537AGA-HAB-AX, 78F0537DAGA-HAB-AX Note Note The PD78F0537D and 78F0537DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 40 78K0/Kx2 CHAPTER 1 OUTLINE (6/6) 78K0/Kx2 Package Microcontrollers 78K0/KE2 Product Quality type grace Part Number 64-pin plastic Conventional- Standard PD78F0531FC-AA1-A, 78F0532FC-AA1-A, FLGA (5x5) specification 78F0533FC-AA1-A, 78F0534FC-AA1-A, 78F0535FC-AA1-A, products 78F0536FC-AA1-A, 78F0537FC-AA1-A, products 78F0537DFC-AA1-A Note Expanded- Standard PD78F0531AFC-AA1-A, 78F0532AFC-AA1-A, specification products 78F0533AFC-AA1-A, 78F0534AFC-AA1-A, 78F0535AFC-AA1-A, 78F0536AFC-AA1-A, products Note 78F0537AFC-AA1-A, 78F0537DAFC-AA1-A <R> 64-pin plastic Expanded- Standard PD78F0531AF1-AA2-A, 78F0532AF1-AA2-A, FBGA (4x4) specification products 78F0533AF1-AA2-A, 78F0534AF1-AA2-A, 78F0535AF1-AA2-A, 78F0536AF1-AA2-A, products 78F0537AF1-AA2-A, 78F0537DAF1-AA2-A 78K0/KF2 80-pin plastic Conventional- Standard PD78F0544GC-UBT-A, 78F0545GC-UBT-A, LQFP (14x14) specification 78F0546GC-UBT-A, 78F0547GC-UBT-A, products products 78F0547DGC-UBT-A Note (A) grade PD78F0544GC(A)-GAD-AX, 78F0545GC(A)-GAD-AX, products 78F0546GC(A)-GAD-AX, 78F0547GC(A)-GAD-AX (A2) grade PD78F0544GC(A2)-GAD-AX, 78F0545GC(A2)-GAD-AX, products 78F0546GC(A2)-GAD-AX, 78F0547GC(A2)-GAD-AX Expanded- Standard PD78F0544AGC-GAD-AX, 78F0545AGC-GAD-AX, specification products 78F0546AGC-GAD-AX, 78F0547AGC-GAD-AX, products 78F0547DAGC-GAD-AX Note (A) grade PD78F0544AGCA-GAD-G, 78F0545AGCA-GAD-G, products 78F0546AGCA-GAD-G, 78F0547AGCA-GAD-G (A2) grade PD78F0544AGCA2-GAD-G, 78F0545AGCA2-GAD-G, products 78F0546AGCA2-GAD-G, 78F0547AGCA2-GAD-G 80-pin plastic Conventional- Standard PD78F0544GK-8EU-A, 78F0545GK-8EU-A, LQFP (fine pitch) specification 78F0546GK-8EU-A, 78F0547GK-8EU-A, (12x12) products products 78F0547DGK-8EU-A Note (A) grade PD78F0544GK(A)-GAK-AX, 78F0545GK(A)-GAK-AX, products 78F0546GK(A)-GAK-AX, 78F0547GK(A)-GAK-AX (A2) grade PD78F0544GK(A2)-GAK-AX, 78F0545GK(A2)-GAK-AX, products 78F0546GK(A2)-GAK-AX, 78F0547GK(A2)-GAK-AX Expanded- Standard PD78F0544AGK-GAK-AX, 78F0545AGK-GAK-AX, specification products 78F0546AGK-GAK-AX, 78F0547AGK-GAK-AX, 78F0547DAGK-GAK-AX products Note Note Note (A) grade PD78F0544AGKA-GAK-G, 78F0545AGKA-GAK-G, products 78F0546AGKA-GAK-G, 78F0547AGKA-GAK-G (A2) grade PD78F0544AGKA2-GAK-G, 78F0545AGKA2-GAK-G, products 78F0546AGKA2-GAK-G, 78F0547AGKA2-GAK-G The PD78F0537D, 78F0537DA, 78F0547D, and 78F0547DA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 41 78K0/Kx2 CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) 1.5.1 78K0/KB2 * 30-pin plastic SSOP (7.62 mm (300)) ANI1/P21 1 30 ANI2/P22 ANI0/P20 2 29 ANI3/P23 P01/TI010/TO00 3 28 AVSS P00/TI000 4 27 AVREF P120/INTP0/EXLVI 5 26 P10/SCK10/TxD0 RESET 6 25 P11/SI10/RxD0 FLMD0 7 24 P12/SO10 P122/X2/EXCLK/OCD0BNote 8 23 P13/TxD6 P121/X1/OCD0ANote 9 22 P14/RxD6 REGC 10 21 P15/TOH0 VSS 11 20 P16/TOH1/INTP5 VDD 12 19 P17/TI50/TO50 P60/SCL0 13 18 P30/INTP1 P61/SDA0 14 17 P31/INTP2/OCD1ANote P33/TI51/TO51/INTP4 15 16 P32/INTP3/OCD1BNote Note Products with on-chip debug function only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 3. ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 42 78K0/Kx2 CHAPTER 1 OUTLINE * 36-pin plastic FLGA (4x4) Top View Bottom View 6 5 4 3 2 1 A B C D E F F E D C B A Index mark Pin Name Pin No. A1 NC Pin Name Pin No. Note 1 Note 2 Pin Name Pin No. C1 P17/TI50/TO50 E1 AVREF A2 P32/INTP3/OCD1B C2 P14/RxD6 E2 AVSS A3 P30/INTP1 C3 P13/TxD6 E3 ANI2/P22 A4 P61/SDA0 C4 P00/TI000 E4 ANI1/P21 A5 P33/TI51/TO51/INTP4 C5 VDD E5 FLMD0 A6 NC C6 P121/X1/OCD0A E6 RESET D1 P11/SI10/RxD0 F1 NC Note 1 Note 2 Note 2 Note 1 B1 P31/INTP2/OCD1A B2 P16/TOH1/INTP5 D2 P12/SO10 F2 ANI3/P23 B3 P15/TOH0 D3 P10/SCK10/TxD0 F3 ANI0/P20 B4 P60/SCL0 D4 REGC F4 P01/TI010/TO00 B5 EVDD D5 VSS F5 P120/INTP0/EXLVI B6 EVSS D6 P122/X2/EXCLK/ F6 NC OCD0B Note 1 Note 2 Notes 1. It is recommended to connect NC to VSS. 2. Products with on-chip debug function only Cautions 1. Make AVSS and EVSS the same potential as VSS. 2. Make EVDD the same potential as VDD. 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 4. ANI0/P20 to ANI3/P23 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 43 78K0/Kx2 CHAPTER 1 OUTLINE 1.5.2 78K0/KC2 * 38-pin plastic SSOP (7.62 mm (300)) ANI1/P21 1 38 ANI2/P22 ANI0/P20 2 37 ANI3/P23 P01/TI010/TO00 3 36 ANI4/P24 P00/TI000 4 35 ANI5/P25 P120/INTP0/EXLVI 5 34 AVSS RESET 6 33 AVREF P124/XT2/EXCLKS 7 32 P10/SCK10/TxD0 P123/XT1 8 31 P11/SI10/RxD0 FLMD0 9 30 P12/SO10 P122/X2/EXCLK/OCD0BNote 10 29 P13/TxD6 P121/X1/OCD0ANote 11 28 P14/RxD6 REGC 12 27 P15/TOH0 VSS 13 26 P16/TOH1/INTP5 VDD 14 25 P17/TI50/TO50 P60/SCL0 15 24 P30/INTP1 P61/SDA0 16 23 P31/INTP2/OCD1ANote P62/EXSCL0 17 22 P32/INTP3/OCD1BNote P63 18 21 P70/KR0 P33/TI51/TO51/INTP4 19 20 P71/KR1 Note Products with on-chip debug function only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 3. ANI0/P20 to ANI5/P25 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 44 78K0/Kx2 CHAPTER 1 OUTLINE ANI7/P27 ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 P01/TI010/TO00 P00/TI000 P120/INTP0/EXLVI * 44-pin plastic LQFP (10 x 10) 44 43 42 41 40 39 38 37 36 35 34 P41 1 33 AVSS P40 2 32 AVREF RESET 3 31 P10/SCK10/TxD0 P124/XT2/EXCLKS 4 30 P11/SI10/RxD0 P123/XT1 5 29 P12/SO10 FLMD0 6 28 P13/TxD6 Note 7 27 P14/RxD6 P121/X1/OCD0ANote 8 26 P15/TOH0 REGC 9 25 P16/TOH1/INTP5 VSS 10 24 P17/TI50/TO50 VDD 11 23 P30/INTP1 P122/X2/EXCLK/OCD0B P31/INTP2/OCD1ANote P32/INTP3/OCD1B Note P70/KR0 P71/KR1 P72/KR2 P73/KR3 P63 P33/TI51/TO51/INTP4 P62/EXSCL0 P60/SCL0 P61/SDA0 12 13 14 15 16 17 18 19 20 21 22 Note Products with on-chip debug function only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 45 78K0/Kx2 CHAPTER 1 OUTLINE VDD VSS REGC P121/X1/OCD0ANote P122/X2/EXCLK/OCD0BNote FLMD0 P123/XT1 P124/XT2/EXCLKS RESET P40 P41 P120/INTP0/EXLVI * 48-pin plastic LQFP (fine pitch) (7 x 7) 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 P140/PCL/INTP6 P00/TI000 P01/TI010/TO00 P130 ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 P31/INTP2/OCD1ANote P30/INTP1 P17/TI50/TO50 P16/TOH1/INTP5 P15/TOH0 P14/RxD6 P13/TxD6 P12/SO10 P11/Sl10/RxD0 P10/SCK10/TxD0 AVREF AVSS P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P75 P74 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P32/INTP3/OCD1BNote Note Products with on-chip debug function only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 46 78K0/Kx2 CHAPTER 1 OUTLINE 1.5.3 78K0/KD2 ANI7/P27 ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 P130 P03 P02 P01/TI010/TO00 P00/TI000 * 52-pin plastic LQFP (10 x 10) 52 51 50 49 48 47 46 45 44 43 42 41 40 P140/PCL/INTP6 1 39 AVSS P120/INTP0/EXLVI 2 38 AVREF P41 3 37 P10/SCK10/TXD0 P40 4 36 P11/SI10/RXD0 RESET 5 35 P12/SO10 P124/XT2/EXCLKS 6 34 P13/TXD6 P123/XT1 7 33 P14/RXD6 FLMD0 8 32 P15/TOH0 Note 9 31 P16/TOH1/INTP5 P121/X1/OCD0ANote 10 30 P17/TI50/TO50 REGC 11 29 P30/INTP1 VSS 12 28 P31/INTP2/OCD1ANote VDD 13 27 P32/INTP3/OCD1BNote P122/X2/EXCLK/OCD0B P70/KR0 P71/KR1 P72/KR2 P73/KR3 P74/KR4 P75/KR5 P76/KR6 P77/KR7 P33/TI51/TO51/INTP4 P63 P62/EXSCL0 P60/SCL0 P61/SDA0 14 15 16 17 18 19 20 21 22 23 24 25 26 Note Products with on-chip debug function only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 47 78K0/Kx2 CHAPTER 1 OUTLINE 1.5.4 78K0/KE2 * 64-pin plastic LQFP (fine pitch) (10 x 10) * 64-pin plastic LQFP (14 x 14) * 64-pin plastic LQFP (12 x 12) P140/PCL/INTP6 P141/BUZ/INTP7 P00/TI000 P01/TI010/TO00 P02/SO11Note2 P03/SI11Note2 P04/SCK11Note2 P130 ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 * 64-pin plastic TQFP (fine pitch) (7 x 7) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P120/INTP0/EXLVI P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK/OCD0BNote1 P121/X1/OCD0ANote1 REGC VSS EVSS VDD EVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AVSS AVREF P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P53 P52 P51 P50 P31/INTP2/OCD1ANote1 P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TO01Note2/TI011Note2 P05/SSI11Note2/TI001Note2 P32/INTP3/OCD1BNote1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes 1. Products with on-chip debug function only 2. Products whose flash memory is at least 48 KB only Cautions 1. Make AVSS and EVSS the same potential as VSS. 2. Make EVDD the same potential as VDD. 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 4. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 48 78K0/Kx2 CHAPTER 1 OUTLINE * 64-pin plastic FLGA (5 x 5) * 64-pin plastic FBGA (4 x 4) Top View Bottom View 8 7 6 5 4 3 2 1 H G F E D C B A A B C D E F G H Index mark Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name A1 AVSS C1 ANI4/P24 E1 P130 A2 AVREF C2 ANI3/P23 E2 ANI0/P20 Note 2 Pin No. Pin Name G1 P141/BUZ/INTP7 G2 P140/PCL/INTP6 G3 P43 A3 P11/SI10/RxD0 C3 ANI7/P27 E3 P03/SI11 A4 P13/TxD6 C4 P10/SCK10/TxD0 E4 P42 G4 RESET A5 P16/TOH1/INTP5 C5 P17/TI50/TO50 E5 P77/KR7 G5 REGC A6 P53 C6 P30/INTP1 E6 P33/TI51/TO51/INTP4 G6 VSS A7 P51 C7 P31/INTP2/ Note 1 OCD1A E7 P74/KR4 G7 VDD A8 P32/INTP3/ Note 1 OCD1B C8 P06/TO01 E8 P76/KR6 G8 P61/SDA0 B1 ANI5/P25 D1 ANI1/P21 F1 P01/TI010/TO00 H1 P120/INTP0/EXLVI B2 ANI6/P26 D2 ANI2/P22 F2 P00/TI000 H2 P124/XT2/EXCLKS H3 P123/XT1 Note 2 TI011 Note 2 P02/SO11 P72/KR2 F4 P41 H4 FLMD0 D5 P70/KR0 F5 P40 H5 P122/X2/EXCLK/ Note 1 OCD0B D6 P71/KR1 F6 P60/SCL0 H6 P121/X1/OCD0A D7 P75/KR5 F7 P62/EXSCL0 H7 EVSS D8 P73/KR3 F8 P63 H8 EVDD P12/SO10 D3 P04/SCK11 B4 P15/TOH0 D4 B5 P14/RxD6 B6 P52 B7 P50 B8 P05/SSI11 / Note 2 F3 B3 Note 2 / Note 2 Note 1 Note 2 TI001 Notes 1. Product with on-chip debug function only 2. Products whose flash memory is at least 48 KB only Cautions 1. 2. 3. 4. Remark Make AVSS and EVSS the same potential as VSS. Make EVDD the same potential as VDD. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 49 78K0/Kx2 CHAPTER 1 OUTLINE 1.5.5 78K0/KF2 * 80-pin plastic LQFP (14 x 14) P140/PCL/INTP6 P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB0 P00/TI000 P01/TI010/TO00 P02/SO11 P03/SI11 P04/SCK11 P130 ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 * 80-pin plastic LQFP (fine pitch) (12 x 12) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P120/INTP0/EXLVI P47 P46 P45 P44 P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK/OCD0BNote P121/X1/OCD0ANote REGC VSS EVSS VDD EVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSS AVREF P57 P56 P55 P54 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P53 P52 P51 P50 P31/INTP2/OCD1ANote P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P64 P65 P66 P67 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TI011/TO01 P05/TI001/SSI11 P32/INTP3/OCD1BNote 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note Products with on-chip debug function only Cautions 1. Make AVSS and EVSS the same potential as VSS. 2. Make EVDD the same potential as VDD. 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). 4. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark For pin identification, see 1.6 Pin Identification. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 50 78K0/Kx2 CHAPTER 1 OUTLINE 1.6 Pin Identification ANI0 to ANI7: Analog input P120 to P124: Port 12 AVREF: Analog reference voltage P130: Port 13 AVSS: Analog ground P140 to P145: Port 14 BUSY0: Serial busy input PCL: Programmable clock output BUZ: Buzzer output REGC Regulator capacitance EVDD: Power supply for port RESET: Reset EVSS: Ground for port RxD0, RxD6: Receive data EXCLK: External clock input SCK10, SCK11, SCKA0: Serial clock input/output (main system clock) SCL0: Serial clock input/output External clock input SDA0: Serial data input/output (subsystem clock) SI10, SI11, SIA0: Serial data input External potential input SO10, SO11, SOA0: Serial data output for low-voltage detector SSI11: Serial interface chip select input EXSCL0: External serial clock input STB0: Serial strobe FLMD0: Flash programming mode TI000, TI010, INTP0 to INTP7: External interrupt input TI001, TI011, KR0 to KR7: Key return TI50, TI51: NC: Non-connection TO00, TO01, EXCLKS: EXLVI: Timer input TO50, TO51, OCD0A, OCD0B, OCD1A, OCD1B: On chip debug input/output TOH0, TOH1: Timer output P00 to P06: Port 0 TxD0, TxD6: Transmit data P10 to P17: Port 1 VDD: Power supply P20 to P27: Port 2 VSS: Ground P30 to P33: Port 3 X1, X2: Crystal oscillator (main system clock) P40 to P47: Port 4 XT1, XT2: Crystal oscillator (subsystem clock) P50 to P57: Port 5 P60 to P67: Port 6 P70 to P77: Port 7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 51 78K0/Kx2 CHAPTER 1 OUTLINE 1.7 Block Diagram 1.7.1 78K0/KB2 TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) 16-bit timer/ event counter 00 TOH0/P15 Port 0 2 P00, P01 Port 1 8 P10 to P17 Port 2 4 P20 to P23 Port 3 4 P30 to P33 Port 6 2 P60, P61 Port 12 3 P120 to P122 8-bit timer H0 TOH1/P16 8-bit timer H1 Internal low-speed oscillator Watchdog timer 8-bit timer/ event counter 50 TI50/TO50/P17 8-bit timer/ event counter 51 TI51/TO51/P33 78K/0 CPU core Flash memory Power on clear/ low voltage indicator Serial interface UART0 RxD6/P14 TxD6/P13 Serial interface UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 Serial interface CSI10 Internal high-speed RAM System control ANI0/P20 to ANI3/P23 AVREF AVSS RxD6/P14 (LINSEL) INTP0/P120 INTP1/P30 to INTP4/P33 2. OCD0BNote 1/X2, OCD1BNote 1/P32 RESET X1/P121 X2/EXCLK/P122 REGC Serial interface IIC0 4 A/D converter 4 Interrupt control INTP5/P16 Notes 1. OCD0ANote 1/X1, OCD1ANote 1/P31 Internal high-speed oscillator Voltage regulator SDA0/P61 SCL0/P60 EXLVI/P120 Reset control On-chip debug Note 1 RxD0/P11 TxD0/P10 POC/LVI control VDD, VSS, FLMD0 EVDDNote 2 EVSSNote 2 Available only in the products with on-chip debug function. Available only in the 36-pin products. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 52 78K0/Kx2 CHAPTER 1 OUTLINE 1.7.2 78K0/KC2 TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) 16-bit timer/ event counter 00 TOH0/P15 Port 0 2 P00, P01 Port 1 8 P10 to P17 Port 2 8 P20 to P25, P26Note 1, P27Note 1 Port 3 4 P30 to P33 Port 4 2 P40Note 1, P41Note 1 Port 6 4 P60 to P63 Port 7 6 P70, P71, P72Note 1, P73Note 1, P74Note 2, P75Note 2 Port 12 5 P120 to P124 8-bit timer H0 TOH1/P16 8-bit timer H1 Internal low-speed oscillator Watchdog timer 8-bit timer/ event counter 50 TI50/TO50/P17 8-bit timer/ event counter 51 TI51/TO51/P33 78K/0 CPU core Watch timer RxD0/P11 TxD0/P10 Serial interface UART0 RxD6/P14 TxD6/P13 Serial interface UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 Serial interface CSI10 EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI5/P25, ANI6/P26Note 1, ANI7/P27Note 1 AVREF AVSS Flash memory P130Note 2 Port 14Note 2 P140Note 2 Clock output controlNote 2 Internal high-speed RAM Internal expansion RAMNote 3 Key return On-chip debugNote 4 A/D converter System control Interrupt control INTP5/P16 KR0/P70, KR1/P71, KR2/P72Note 1, KR3/P73Note 1 VDD VSS FLMD0 OCD0ANote 4/X1, OCD1ANote 4/P31 OCD0BNote 4/X2, OCD1BNote 4/P32 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 Internal high-speed oscillator Voltage regulator Notes 1. 4 EXLVI/P120 Reset control 8 INTP6/P140Note 2 POC/LVI control Multiplier & dividerNote 3 Serial interface IIC0 4 PCL/P140Note 2 Power-on-clear/ low-voltage indicator RxD6/P14 (LINSEL) INTP0/P120 INTP1/P30 to INTP4/P33 Port 13Note 2 REGC Available only in the 44-pin and 48-pin products. 2 Available only in the 48-pin products. 3. Available only in the products whose flash memory is at least 48 KB. 4. Available only in the products with on-chip debug function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 53 78K0/Kx2 CHAPTER 1 OUTLINE 1.7.3 78K0/KD2 TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) 16-bit timer/ event counter 00 TOH0/P15 Port 0 4 P00 to P03 Port 1 8 P10 to P17 Port 2 8 P20 to P27 Port 3 4 P30 to P33 Port 4 2 P40, P41 Port 6 4 P60 to P63 Port 7 8 P70 to P77 Port 12 5 P120 to P124 8-bit timer H0 TOH1/P16 8-bit timer H1 Internal low-speed oscillator Watchdog timer 8-bit timer/ event counter 50 TI50/TO50/P17 8-bit timer/ event counter 51 TI51/TO51/P33 Watch timer 78K/0 CPU CORE Flash memory Port 13 P130 Port 14 P140 BANKNote 1 Clock output control RxD0/P11 TxD0/P10 Serial interface UART0 RxD6/P14 TxD6/P13 Serial interface UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 Serial interface CSI10 EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI7/P27 AVREF AVSS Power on clear/low voltage indicator Internal high-speed RAM Internal expansion RAMNote 2 Key return 8 A/D converter System control KR0/P70 to KR7/P77 OCD0ANote 3/X1, OCD1ANote 3/P31 OCD0BNote 3/X2, OCD1BNote 3/P32 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 Internal high-speed oscillator Interrupt control INTP5/P16 8 EXLVI/P120 Reset control On-chip debugNote 3 4 POC/LVI control Multiplier & dividerNote 2 Serial interface IIC0 RxD6/P14 INTP0/P120(LINSEL) INTP1/P30 to INTP4/P33 PCL/P140 VDD VSS FLMD0 INTP6/P140 Voltage regulator Notes 1. Available only in the products whose flash memory is at least 96 KB. 2. Available only in the products whose flash memory is at least 48 KB. 3. Available only in the products with on-chip debug function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 REGC 54 78K0/Kx2 CHAPTER 1 OUTLINE 1.7.4 78K0/KE2 TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) 16-bit TIMER/ EVENT COUNTER 00 TO01Note2/TI011Note2/P06 TI001Note2/P05 16-bit TIMER/ EVENT COUNTER 01Note2 TOH0/P15 PORT 0 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 4 P30 to P33 PORT 4 4 P40 to P43 PORT 5 4 P50 to P53 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 PORT 12 5 P120 to P124 8-bit TIMER H0 TOH1/P16 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER 8-bit TIMER/ EVENT COUNTER 50 TI50/TO50/P17 8-bit TIMER/ EVENT COUNTER 51 TI51/TO51/P33 WATCH TIMER PORT 13 78K/0 CPU CORE FLASH MEMORY PORT 14 P130 2 P140, P141 BANKNote1 RxD0/P11 TxD0/P10 SERIAL INTERFACE UART0 RxD6/P14 TxD6/P13 SERIAL INTERFACE UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 SERIAL INTERFACE CSI10 SI11Note2/P03 SO11Note2/P02 SCK11Note2/P04 SSI11Note2/P05 CLOCK OUTPUT CONTROL PCL/P140 POWER ON CLEAR/ LOW VOLTAGE INDICATOR KEY RETURN POC/LVI CONTROL 8 EXLVI/P120 KR0/P70 to KR7/P77 RESET CONTROL SERIAL INTERFACE IIC0 ON-CHIP DEBUGNote3 8 SYSTEM CONTROL A/D CONVERTER VDD, VSS, FLMD0 EVDD EVSS 4 INTP5/P16 INTP6/P140, INTP7/P141 BUZ/P141 MULTIPLIER& DIVIDERNote2 RxD6/P14 (LINSEL) INTP0/P120 INTP1/P30 to INTP4/P33 INTERNAL EXPANSION RAMNote2 SERIAL INTERFACE CSI11Note2 EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI7/P27 AVREF AVSS INTERNAL HIGH-SPEED RAM BUZZER OUTPUT INTERRUPT CONTROL 2 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 INTERNAL HIGH-SPEED OSCILLATOR VOLTAGE REGULATOR Notes 1. Available only in the products whose flash memory is at least 96 KB. 2. Available only in the products whose flash memory is at least 48 KB. 3. Available only in the products with on-chip debug function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 OCD0ANote3/X1, OCD1ANote3/P31 OCD0BNote3/X2, OCD1BNote3/P32 REGC 55 78K0/Kx2 CHAPTER 1 OUTLINE 1.7.5 78K0/KF2 TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) 16-bit timer/ event counter 00 TO01/TI011/P06 TI001/P05 16-bit timer/ event counter 01 TOH0/P15 Port 0 7 P00 to P06 Port 1 8 P10 to P17 Port 2 8 P20 to P27 Port 3 4 P30 to P33 8-bit timer H1 Port 4 8 P40 to P47 Internal low-speed oscillator Port 5 8 P50 to P57 Port 6 8 P60 to P67 Port 7 8 P70 to P77 Port 12 5 P120 to P124 8-bit timer H0 TOH1/P16 Watchdog timer 8-bit timer/ event counter 50 TI50/TO50/P17 8-bit timer/ event counter 51 TI51/TO51/P33 Watch timer Port 13 78K/0 CPU core BANK RxD0/P11 TxD0/P10 Serial interface UART0 RxD6/P14 TxD6/P13 Serial interface UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 Serial interface CSI10 SI11/P03 SO11/P02 SCK11/P04 SSI11/P05 Serial interface CSI11 SIA0/P143 SOA0/P144 SCKA0/P142 STB0/P145 BUSY0/P141 Serial interface CSIA0 Notes 1. 2. Internal expansion RAM 6 P140 to P145 Buzzer output BUZ/P141 Clock output control PCL/P140 Power on clear/ low voltage indicator Key return POC/LVI control 8 EXLVI/P120 KR0/P70 to KR7/P77 Reset control On-chip debugNote 2 System control OCD0ANote 2/X1, OCD1ANote 2/P31 OCD0BNote 2/X2, OCD1BNote 2/P32 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 Internal high-speed oscillator 8 A/D converter VDD, VSS, FLMD0 EVDD EVSS 4 INTP5/P16 INTP6/P140, INTP7/P141 Internal high-speed RAM Serial interface IIC0 RxD6/P14 (LINSEL) INTP0/P120 INTP1/P30 to INTP4/P33 Port 14 Note 1 Multiplier & divider EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI7/P27 AVREF AVSS Flash memory P130 Voltage regulator REGC Interrupt control 2 Available only in the products whose flash memory is at least 96 KB. Available only in the products with on-chip debug function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 56 78K0/Kx2 CHAPTER 1 OUTLINE 1.8 Outline of Functions (1/2) 78K0/Kx2 78K0/KB2 Item 78K0/KC2 30/36 Pins Flash memory (KB) High-Speed RAM (KB) 38/44 Pins 48 Pins 8 16 24 32 16 24 32 16 24 32 48 60 0.5 0.75 1 1 0.75 1 1 0.75 1 1 1 1 - - - - - - - - - - 1 2 Expansion RAM (KB) Bank (flash memory) - Power supply voltage Standard products, (A) grade products: VDD = 1.8 to 5.5 V, (A2) grade products: VDD = 2.7 to 5.5 V Regulator Provided 0.1 s (20 MHz: VDD = 2.7 to 5.5 V)/0.4 s (5 MHz: VDD = 1.8 to 5.5 V) Main Clock Minimum instruction execution time High-speed system 20 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V Internal high-speed oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V - Subsystem Port Timer 240 kHz (TYP.): VDD = 1.8 to 5.5 V 23 31 (38 pins)/ 37 (44 pins) 41 N-ch O.D. (6 V tolerance) 2 4 4 16 bits (TM0) 1 ch 8 bits (TM5) 2 ch 8 bits (TMH) Note 1 Note 1 Total 2 ch - Watch 1 ch WDT Serial interface Note 1 Note 1 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Internal low-speed oscillation 1 ch 3-wire CSI - Automatic transmit/ receive 3-wire CSI - UART/3-wire CSI Note 2 1 ch UART supporting LIN-bus 1 ch 2 1 ch 10-bit A/D 4 ch 6 ch (38 pins)/ 8 ch (44 pins) Interrupt I C bus External 6 7 Internal 14 8 ch 8 16 - Key interrupt 2 ch (38 pins)/ 4 ch (44 pins) RESET pin Reset Note 1 4 ch Provided 1.59 V 0.15 V POC LVI The detection level of the supply voltage is selectable. WDT Provided - Clock output/buzzer output On-chip debug function Operating ambient temperature Clock output only - Multiplier/divider PD78F0503D, 78F0503DA PD78F0513D, only 78F0513DA only Provided PD78F0515D, 78F0515DA only Standard products, (A) grade products: TA = -40 to +85C, (A2) grade products: TA = -40 to +125C Notes 1. This is applicable to a standard expanded-specification product (PD78F05xxA and 78F05xxDA). See CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA: -40 to +125C) for products with other specifications and grades. 2. Select either of the functions of these alternate-function pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 57 78K0/Kx2 CHAPTER 1 OUTLINE (2/2) 78K0/Kx2 78K0/KD2 Item 78K0/KE2 52 Pins Flash memory (KB) High-Speed RAM (KB) Expansion RAM (KB) 64 Pins 24 32 48 60 96 128 16 24 32 48 60 96 128 48 60 96 128 0.75 1 1 1 1 1 1 0.75 1 1 1 1 1 1 1 1 1 1 - - - 1 2 4 6 - - - 1 2 4 6 1 2 4 6 4 6 4 6 4 6 - - Provided 0.1 s (20 MHz: VDD = 2.7 to 5.5 V)/0.4 s (5 MHz: VDD = 1.8 to 5.5 V) Main Clock Minimum instruction execution time High-speed system 20 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V Internal high-speed oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V Subsystem Port 240 kHz (TYP.): VDD = 1.8 to 5.5 V Total 45 N-ch O.D. (6 V tolerance) 4 Serial interface Timer 16 bits (TM0) Note 1 Note 1 55 71 4 4 2 ch 8 bits (TM5) 2 ch 8 bits (TMH) 2 ch Watch 1 ch WDT 1 ch - 1 ch - Automatic transmit/ receive 3-wire CSI UART/3-wire CSI Note 1 1 ch 3-wire CSI Note 1 Note 1 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Internal low-speed oscillation 1 ch Note 1 ch UART supporting LIN-bus 1 ch 2 1 ch 10-bit A/D 8 ch I C bus Interrupt - Standard products, (A) grade products: VDD = 1.8 to 5.5 V, (A2) grade products: VDD = 2.7 to 5.5 V Regulator External 8 Internal 9 16 19 Key interrupt 20 8 ch RESET pin Reset 80 Pins 16 Bank (flash memory) Power supply voltage 78K0/KF2 Provided 1.59 V 0.15 V POC LVI The detection level of the supply voltage is selectable. WDT Provided Clock output/buzzer output Clock output only - Multiplier/divider On-chip debug function Operating ambient temperature Provided PD78F0527D, 78F0527DA only Provided - Provided PD78F0537D, 78F0537DA only PD78F0547D, 78F0547DA only Standard products, (A) grade products: TA = -40 to +85C, (A2) grade products: TA = -40 to +125C Notes 1. This is applicable to a standard expanded-specification product (PD78F05xxA and 78F05xxDA). See CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA: -40 to +125C) for products with other specifications and grades. 2. Select either of the functions of these alternate-function pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 58 78K0/Kx2 CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/ Event Counters 00 and 01 8-Bit Timers H0 and H1 Watch Timer Watchdog Timer 8-Bit Timer/ Event Counters 50 and 51 TM00 TM01 TM50 TM51 TMH0 TMH1 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel - - - - PPG output 1 output 1 output - - - - - - PWM output - - 1 output 1 output 1 output 1 output - - Pulse width measurement 2 inputs 2 inputs - - - - - - Square-wave output 1 output 1 output 1 output 1 output 1 output 1 output - - Carrier generator - - - - - Timer output - - - - - - Watchdog timer - - - - - - - 1 channel 2 2 1 1 1 1 1 - Function Interval timer External event counter Interrupt source Notes 1. - Nore 2 - - Nore 1 1 channel - In the watch timer, the watch timer function and interval timer function can be used simultaneously. 2. Remark 1 output Note 1 1 channel TM51 and TMH1 can be used in combination as a carrier generator mode. The timer mounted depends on the product. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is less than at least 32 KB 48 KB 16-bit timer/event counter 00 - 16-bit timer/event counter 01 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 8-bit timer H1 Watch timer - Watchdog timer : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 59 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies (AVREF, VDD) * 78K0/KB2: 30-pin plastic SSOP (7.62 mm (300)) * 78K0/KC2: 38-pin plastic SSOP (7.62 mm (300)), 44-pin plastic LQFP (10x10), 48-pin plastic LQFP (fine pitch) (7x7) * 78K0/KD2: 52-pin plastic LQFP (10x10) Power Supply Corresponding Pins AVREF P20 to P27 VDD Pins other than P20 to P27 Table 2-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD) * 78K0/KB2: 36-pin plastic FLGA (4x4) * 78K0/KE2: 64-pin plastic LQFP (fine pitch) (10x10), 64-pin plastic LQFP (14x14), 64-pin plastic LQFP (12x12), 64-pin plastic TQFP (fine pitch) (7x7), 64-pin plastic FLGA (5x5), 64-pin plastic FBGA (4x4) * 78K0/KF2: 80-pin plastic LQFP (14x14), 80-pin plastic LQFP (fine pitch) (12x12) Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 and P121 to P124 VDD * P121 to P124 * Pins other than port R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 60 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.1.1 78K0/KB2 (1) Port functions: 78K0/KB2 Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O Port 1. Input port 8-bit I/O port. P11 SI10/RxD0 Input/output can be specified in 1-bit units. P12 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 SCK10/TxD0 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P23 I/O Port 2. Analog input ANI0 to ANI3 Input port INTP1 4-bit I/O port. Input/output can be specified in 1-bit units. P30 I/O 4-bit I/O port. P31 Input/output can be specified in 1-bit units. P32 Use of an on-chip pull-up resistor can be specified by a software P33 P60 Port 3. Port 6. Input port 2-bit I/O port. P61 Note INTP3/OCD1B Note INTP4/TI51/TO51 setting. I/O INTP2/OCD1A SCL0 SDA0 Output is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. P120 P121 P122 I/O Port 12. 3-bit I/O port. Input/output can be specified in 1-bit units. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP0/EXLVI X1/OCD0A Note X2/EXCLK/ OCD0B Note Note PD78F0503D and 78F0503DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 61 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (1/2): 78K0/KB2 Function Name ANI0 to ANI3 I/O Input Function After Reset A/D converter analog input Analog Alternate Function P20 to P23 input EXLVI Input - FLMD0 INTP0 Input Potential input for external low-voltage detection Flash memory programming mode setting External interrupt request input for which the valid edge (rising Input port - Input port edge, falling edge, or both rising and falling edges) can be INTP1 - P120/EXLVI P30 specified INTP2 P120/INTP0 INTP3 P31/OCD1A Note P32/OCD1B Note INTP4 P33/TI51/TO51 INTP5 P16/TOH1 - REGC Connecting regulator output (2.5 V) stabilization capacitance - - - - for internal operation. Connect to VSS via a capacitor (0.47 to 1 F). RESET Input System reset input RxD0 Input Serial data input to UART0 Input port P11/SI10 RxD6 Input Serial data input to UART6 Input port P14 TxD0 Output Serial data output from UART0 Input port P10/SCK10 TxD6 Output Serial data output from UART6 Input port P13 SCK10 I/O Clock input/output for CSI10 Input port SI10 Input Serial data input to CSI10 P11/RxD0 SO10 Output Serial data output from CSI10 P12 SCL0 2 I/O Clock input/output for I C SDA0 TI000 Input port 2 Serial data I/O for I C Input External count clock input to 16-bit timer/event counter 00 P10/TxD0 P60 P61 Input port P00 Input port P01/TO00 Input port P17/TO50 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 TI010 Input Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 TI50 Input TI51 External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 P33/TO51/INTP4 TO00 Output 16-bit timer/event counter 00 output Input port P01/TI010 TO50 Output 8-bit timer/event counter 50 output Input port P17/TI50 TO51 TOH0 8-bit timer/event counter 51 output Output TOH1 Input port 8-bit timer H1 output X1 - X2 - EXCLK 8-bit timer H0 output P33/TI51/INTP4 Input Connecting resonator for main system clock External clock input for main system clock P15 P16/INTP5 Note Input port P121/OCD0A Input port P122/EXCLK/OCD0B Input port P122/X2/OCD0B Note Note Note PD78F0503D and 78F0503DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 62 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/2): 78K0/KB2 Function Name I/O - VDD Function After Reset Alternate Function - - - - - - - - - - - - For 30-pin products: Positive power supply for pins other than P20 to P23 For 36-pin products: Positive power supply for P121, P122, and non-port pins EVDD Note 1 - For 36-pin products: Positive power supply for port pins other than P20 to P23, P121, and P122. Make the same potential as VDD. - AVREF A/D converter reference voltage input and positive power supply for P20 to P23 and A/D converter - VSS For 30-pin products: Ground potential for pins other than P20 to P23 For 36-pin products: Ground potential for P121, P122, and non-port pins Note 1 EVSS - For 36-pin products: Ground potential for port pins other than P20 to P23, P121, and P122. Make the same potential as VSS. - AVSS A/D converter ground potential. Make the same potential as VSS. OCD0A Note 2 OCD1A Note 2 OCD0B Note 2 OCD1B Note 2 Input Connection for on-chip debug mode setting pins Input port (PD78F0503D and 78F0503DA only) - P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Notes 1. 36-pin products only 2. PD78F0503D and 78F0503DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 63 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.1.2 78K0/KC2 (1) Port functions (1/2): 78K0/KC2 Function Name I/O I/O P00 Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O P10 Port 1. Input port 8-bit I/O port. P11 SI10/RxD0 Input/output can be specified in 1-bit units. P12 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 SCK10/TxD0 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P25 P26 Note 1 , P27 I/O Port 2. Analog input 8-bit I/O port. Note 1 ANI0 to ANI5 ANI6 Note 1 , ANI7 Note 1 Input/output can be specified in 1-bit units. P30 I/O P31 P32 P33 P40 Note 1 , P41 Note 1 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port Port 4. Input port INTP1 INTP2/OCD1A Note 2 INTP3/OCD1B Note 2 TI51/TO51/INTP4 - 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 I/O Port 6. Input port 4-bit I/O port. P61 SDA0 Output of P60 to P63 is N-ch open-drain output (6 V tolerance). P62 SCL0 EXSCL0 Input/output can be specified in 1-bit units. - P63 I/O P70, P71 P72 P74 Note 1 , P73 Note 3 , P75 Note 1 Note 3 Port 7. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software Input port KR0, KR1 KR2 Note 1 , KR3 Note 1 - setting. Notes 1. 44-pin and 48-pin products only For the 38-pin products, be sure to set bits 6 and 7 of PM2 to "1", and bits 0 and 1 of PM4, bits 2 and 3 of PM7, bits 6 and 7 of P2, bits 0 and 1 of P4, and bits 2 and 3 of P7 to "0". 2. PD78F0513D, 78F0513DA, 78F0515D and 78F0515DA (product with on-chip debug function) only 3. 48-pin products only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 64 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2): 78K0/KC2 Function Name I/O Port 12. I/O P120 Function After Reset Input port 5-bit I/O port. P121 Note 1 XT1 specified by a software setting. P124 P130 Note 1 X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 INTP0/EXLVI X1/OCD0A Input/output can be specified in 1-bit units. P122 Alternate Function XT2/EXCLKS Note 2 Output Port 13. - Output port 1-bit output-only port. P140 Note 2 Port 14. I/O Input port Note 2 PCL/INTP6 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Notes 1. PD78F0513D, 78F0513DA, 78F0515D and 78F0515DA (product with on-chip debug function) only 2. 48-pin products only (2) Non-port functions (1/2): 78K0/KC2 Function Name Input ANI0 to ANI5 ANI6 Note 1 I/O , ANI7 Function A/D converter analog input After Reset Analog input Note 1 Alternate Function P20 to P25 P26 Note 1 , P27 EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0 EXSCL0 Input External clock input for serial interface. Input port P62 Note 1 To input an external clock, input a clock of 6.4 MHz. - FLMD0 INTP0 Input Flash memory programming mode setting External interrupt request input for which the valid edge (rising - Input port edge, falling edge, or both rising and falling edges) can be INTP1 - P120/EXLVI P30 specified P31/OCD1A Note 2 INTP3 P32/OCD1B Note 2 INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP2 INTP6 Note 3 Note 3 P140/PCL KR0, KR1 KR2 Note 1 PCL Note 3 Input , KR3 Key interrupt input Input port Note 1 P70, P71 P72 Output Clock output (for trimming of high-speed system clock, Input port Note 1 , P73 P140/INTP6 Note 1 Note 3 subsystem clock) Notes 1. 44-pin and 48-pin products only For the 38-pin products, be sure to set bits 6 and 7 of PM2 to "1", and bits 2 and 3 of PM7, bits 6 and 7 of P2, and bits 2 and 3 of P7 to "0". 2. PD78F0513D, 78F0513DA, 78F0515D and 78F0515DA (product with on-chip debug function) only 3. 48-pin products only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 65 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/2): 78K0/KC2 Function Name I/O - REGC Function Connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect to VSS via a capacitor (0.47 to 1 F). After Reset Alternate Function - - - - RESET Input System reset input RxD0 Input Serial data input to UART0 Input port P11/SI10 RxD6 Input Serial data input to UART6 Input port P14 SCK10 I/O Clock input/output for CSI10 Input port P10/TxD0 2 SCL0 I/O Clock input/output for I C Input port P60 SDA0 I/O Serial data I/O for I C Input port P61 SI10 Input Serial data input to CSI10 Input port P11/RxD0 SO10 Output Serial data output from CSI10 Input port P12 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Input port P00 2 TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 Input TI50 TI51 External count clock input to 8-bit timer/event counter 50 P01/TO00 Input port External count clock input to 8-bit timer/event counter 51 P17/TO50 P33/TO51/INTP4 TO00 Output 16-bit timer/event counter 00 output Input port P01/TI010 TO50 Output 8-bit timer/event counter 50 output Input port P17/TI50 TO51 8-bit timer/event counter 51 output Output TOH0 TOH1 8-bit timer H0 output P33/TI51/INTP4 Input port 8-bit timer H1 output P15 P16/INTP5 TxD0 Output Serial data output from UART0 Input port P10/SCK10 TxD6 Output Serial data output from UART6 Input port P13 Connecting resonator for main system clock Input port P121/OCD0A X1 - X2 - EXCLK XT1 P122/EXCLK/ Note OCD0B Input External clock input for main system clock Input port P122/X2/ Note OCD0B - Connecting resonator for subsystem clock Input port P123 - XT2 EXCLKS Input External clock input for subsystem clock Input port P124/EXCLKS Input port P124/XT2 VDD - Positive power supply for pins other than P20 to P27 - - AVREF - A/D converter reference voltage input and positive power supply for P20 to P27 and A/D converter - - VSS - Ground potential for pins other than P20 to P27 - - AVSS - A/D converter ground potential. Make the same potential as VSS. - - OCD0A Note OCD1A Note OCD0B Note OCD1B Note Input - Note Connection for on-chip debug mode setting pins (PD78F0513D, 78F0513DA, 78F0515D and 78F0515DA only) Input port P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note PD78F0513D, 78F0513DA, 78F0515D and 78F0515DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 66 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.1.3 78K0/KD2 (1) Port functions (1/2): 78K0/KD2 Function Name P00 I/O I/O Port 0. After Reset Input port 4-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 - Use of an on-chip pull-up resistor can be specified by a software P03 P10 Function - setting. I/O Port 1. Input port 8-bit I/O port. P11 SI10/RxD0 Input/output can be specified in 1-bit units. P12 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 SCK10/TxD0 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 I/O Port 2. Analog input ANI0 to ANI7 Input port INTP1 8-bit I/O port. Input/output can be specified in 1-bit units. P30 I/O 4-bit I/O port. P31 Input/output can be specified in 1-bit units. P32 Use of an on-chip pull-up resistor can be specified by a software P33 P40, P41 Port 3. Port 4. Note INTP3/OCD1B Note TI51/TO51/INTP4 setting. I/O INTP2/OCD1A - Input port 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 I/O Port 6. Input port 4-bit I/O port. P61 SDA0 Output is N-ch open-drain output (6 V tolerance). P62 SCL0 EXSCL0 Input/output can be specified in 1-bit units. - P63 P70 to P77 I/O Port 7. Input port KR0 to KR7 Input port INTP0/EXLVI 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 P121 P122 I/O Port 12. 5-bit I/O port. Input/output can be specified in 1-bit units. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. X1/OCD0A Note X2/EXCLK/ OCD0B Note P123 XT1 P124 XT2/EXCLKS Note PD78F0527D and 78F0527DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 67 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2): 78K0/KD2 Function Name P130 I/O Output Function After Reset Port 13. Alternate Function - Output port 1-bit output-only port. P140 I/O Port 14. Input port PCL/INTP6 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. (2) Non-port functions (1/2): 78K0/KD2 Function Name ANI0 to ANI7 I/O Input Function A/D converter analog input After Reset Analog Alternate Function P20 to P27 input EXLVI EXSCL0 Input Input Potential input for external low-voltage detection 2 External clock input for I C Input port P120/INTP0 Input port P62 To input an external clock, input a clock of 6.4 MHz. - FLMD0 INTP0 Input - Flash memory programming mode setting External interrupt request input for which the valid edge Input port (rising edge, falling edge, or both rising and falling edges) INTP1 - P120/EXLVI P30 can be specified P31/OCD1A Note INTP3 P32/OCD1B Note INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP6 P140/PCL INTP2 KR0 to KR7 Input Key interrupt input Input port P70 to P77 PCL Output Clock output (for trimming of high-speed system clock, Input port P140/INTP6 subsystem clock) - REGC Connecting regulator output (2.5 V) stabilization capacitance - - - - for internal operation. Connect to VSS via a capacitor (0.47 to 1 F). RESET Input System reset input RxD0 Input Serial data input to UART0 RxD6 SCK10 Input port Serial data input to UART6 I/O Clock input/output for CSI10 P14 Input port 2 SCL0 Clock input/output for I C 2 P11/SI10 P10/TxD0 P60 SDA0 I/O Serial data I/O for I C Input port P61 SI10 Input Serial data input to CSI10 Input port P11/RxD0 SO10 Output Serial data output from CSI10 Input port P12 TxD0 Output Serial data output from UART0 Input port P10/SCK10 TxD6 Serial data output from UART6 P13 Note PD78F0527D and 78F0527DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 68 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/2): 78K0/KD2 Function Name TI000 I/O Input Function External count clock input to 16-bit timer/event counter 00 After Reset Input port Alternate Function P00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Capture trigger input to capture register (CR000) of 16-bit TI010 P01/TO00 timer/event counter 00 TI50 Input TI51 P33/TO51/INTP4 Output 16-bit timer/event counter 00 output Input port P01/TI010 TO50 Output 8-bit timer/event counter 50 output Input port P17/TI50 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 8-bit timer H0 output P15 TOH1 8-bit timer H1 output P16/INTP5 X1 - X2 - Connecting resonator for main system clock Input port P121/OCD0A Note Note P122/EXCLK/OCD0B Input External clock input for main system clock Input port P122/X2/OCD0B XT1 - Connecting resonator for subsystem clock Input port P123 XT2 - Input port P124/EXCLKS Input port P124/XT2 EXCLKS <R> P17/TO50 TO00 EXCLK <R> Input port External count clock input to 8-bit timer/event counter 51 TO51 <R> External count clock input to 8-bit timer/event counter 50 Input External clock input for subsystem clock VDD - Positive power supply for pins other than P20 to P27 - - AVREF - A/D converter reference voltage input and positive power - - Note supply for P20 to P27 and A/D converter VSS - Ground potential for pins other than P20 to P27 - - AVSS - A/D converter ground potential. Make the same potential as - - VSS. OCD0A Note OCD1A Note OCD0B Note OCD1B Note Input Connection for on-chip debug mode setting pins (PD78F0527D and 78F0527DA only) - Input port P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note PD78F0527D and 78F0527DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 69 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.1.4 78K0/KE2 (1) Port functions (1/2): 78K0/KE2 Function Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 SO11 Use of an on-chip pull-up resistor can be specified by a software P03 TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Alternate Function SI11 setting. Note 1 Note 1 P04 SCK11 P05 TI001 Note 1 Note 1 SSI11 / Note 1 Note 1 / TI011 P06 TO01 I/O P10 Port 1. Input port 8-bit I/O port. P11 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 SCK10/TxD0 SI10/RxD0 Input/output can be specified in 1-bit units. P12 Note 1 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 I/O Port 2. Analog input ANI0 to ANI7 Input port INTP1 8-bit I/O port. Input/output can be specified in 1-bit units. P30 I/O Port 3. 4-bit I/O port. P31 INTP2/OCD1A Input/output can be specified in 1-bit units. P32 INTP3/OCD1B Use of an on-chip pull-up resistor can be specified by a software P33 I/O Port 4. Note 2 TI51/TO51/INTP4 setting. P40 to P43 Note 2 Input port - Input port - 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P53 I/O Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 P61 P62 I/O Port 6. Input port 4-bit I/O port. Output of P60 to P63 is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. SCL0 SDA0 EXSCL0 - P63 Notes 1. Available only in the products whose flash memory is at least 48 KB. 2. PD78F0537D and 78F0537DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 70 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2): 78K0/KE2 Function Name P70 to P77 I/O Function Port 7. I/O After Reset Alternate Function Input port KR0 to KR7 Input port INTP0/EXLVI 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 Port 12. I/O 5-bit I/O port. P121 X1/OCD0A Input/output can be specified in 1-bit units. P122 Note X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 XT1 specified by a software setting. P124 P130 Note XT2/EXCLKS Output Port 13. - Output port 1-bit output-only port. P140 Port 14. I/O Input port 2-bit I/O port. P141 PCL/INTP6 BUZ/INTP7 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note PD78F0537D and 78F0537DA (product with on-chip debug function) only (2) Non-port functions (1/3): 78K0/KE2 Function Name I/O Function After Reset Alternate Function ANI0 to ANI7 Input A/D converter analog input Analog input P20 to P27 BUZ Output Buzzer output Input port P141/INTP7 EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0 Input port P62 EXSCL0 Input 2 External clock input for I C. To input an external clock, input a clock of 6.4 MHz. FLMD0 INTP0 - Input Flash memory programming mode setting External interrupt request input for which the valid edge (rising - Input port edge, falling edge, or both rising and falling edges) can be INTP1 - P120/EXLVI P30 specified P31/OCD1A Note INTP3 P32/OCD1B Note INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP6 P140/PCL INTP2 P141/BUZ INTP7 KR0 to KR7 Input Key interrupt input Input port P70 to P77 PCL Output Clock output (for trimming of high-speed system clock, Input port P140/INTP6 subsystem clock) REGC - Connecting regulator output (2.5 V) stabilization capacitance - - for internal operation. Connect to VSS via a capacitor (0.47 to 1 F). Note PD78F0537D and 78F0537DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 71 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/3): 78K0/KE2 Function Name I/O Function RESET Input System reset input RxD0 Input Serial data input to UART0 RxD6 After Reset Alternate Function - - Input port Serial data input to UART6 I/O SCK10 SCK11 Clock input/output for CSI10 Note 1 SCL0 P14 Input port Clock input/output for CSI11 2 I/O Clock input/output for I C 2 P11/SI10 P10/TxD0 P04 Input port P60 SDA0 I/O Serial data I/O for I C Input port P61 SI10 Input Serial data input to CSI10 Input port P11/RxD0 SI11 Note 1 Output SO10 SO11 Serial data input to CSI11 Note 1 SSI11 Note 1 TI000 Serial data output from CSI10 P03 Input port Serial data output from CSI11 P12 P02 Input Chip select input to CSI11 Input port P05/TI001 Input External count clock input to 16-bit timer/event counter 00 Input port P00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Note 1 External count clock input to 16-bit timer/event counter 01 TI001 P05/SSI11 Note 1 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 Capture trigger input to capture register (CR000) of 16-bit TI010 P01/TO00 timer/event counter 00 Note 1 Capture trigger input to capture register (CR001) of 16-bit TI011 P06/TO01 Note 1 timer/event counter 01 Input TI50 TI51 Input port External count clock input to 8-bit timer/event counter 51 Output TO00 TO01 External count clock input to 8-bit timer/event counter 50 Note 1 TO50 Output Input port 8-bit timer/event counter 50 output Output 8-bit timer H0 output Input port TxD6 Serial data output from UART0 Input port - X2 - Connecting resonator for main system clock P17/TI50 P15 P16/INTP5 Input port Serial data output from UART6 <R> X1 Note 1 P33/TI51/INTP4 8-bit timer H1 output Output P01/TI010 P06/TI011 8-bit timer/event counter 51 output TOH1 TxD0 P33/TO51/INTP4 16-bit timer/event counter 01 output TO51 TOH0 16-bit timer/event counter 00 output P17/TO50 P10/SCK10 P13 Input port P121/OCD0A Note 2 P122/EXCLK/ Note 2 OCD0B Input External clock input for main system clock Input port P122/X2/ Note 2 OCD0B <R> XT1 - Connecting resonator for subsystem clock Input port P123 XT2 - Input port P124/EXCLKS Input port P124/XT2 EXCLK EXCLKS Input External clock input for subsystem clock Notes 1. Available only in the products whose flash memory is at least 48 KB. 2. PD78F0537D and 78F0537DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 72 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (3/3): 78K0/KE2 Function Name I/O Function After Reset Alternate Function VDD - Positive power supply for P121 to P124 and other than ports - - EVDD - Positive power supply for ports other than P20 to P27 and - - - - P121 to P124. Make EVDD the same potential as VDD. - <R> AVREF A/D converter reference voltage input and positive power supply for P20 to P27 and A/D converter VSS - Ground potential for P121 to P124 and other than ports - - EVSS - Ground potential for ports other than P20 to P27 and P121 to - - - - P124. Make EVSS the same potential as VSS. - AVSS A/D converter ground potential. Make the same potential as VSS. OCD0A Note OCD1A Note OCD0B Note OCD1B Note Input Connection for on-chip debug mode setting pins (PD78F0537D and 78F0537DA only) - Input port P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note PD78F0537D and 78F0537DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 73 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.1.5 78K0/KF2 (1) Port functions (1/2): 78K0/KF2 Function Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 SO11 Use of an on-chip pull-up resistor can be specified by a software P03 TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Alternate Function SI11 setting. P04 SCK11 P05 TI001/SSI11 P06 TI011/TO01 P10 I/O Port 1. Input port 8-bit I/O port. P11 SI10/RxD0 Input/output can be specified in 1-bit units. P12 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 SCK10/TxD0 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 I/O Port 2. Analog input ANI0 to ANI7 Input port INTP1 8-bit I/O port. Input/output can be specified in 1-bit units. P30 I/O 4-bit I/O port. P31 Input/output can be specified in 1-bit units. P32 Use of an on-chip pull-up resistor can be specified by a software P33 P40 to P47 Port 3. Port 4. Note INTP3/OCD1B Note TI51/TO51/INTP4 setting. I/O INTP2/OCD1A Input port - Input port - 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 P61 P62 P63 to P67 I/O Port 6. 8-bit I/O port. Output of P60 to P63 is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Only for P64 to P67, use of an on-chip pull-up resistor can be Input port SCL0 SDA0 EXSCL0 - specified by a software setting. Note PD78F0547D and 78F0547DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 74 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2): 78K0/KF2 Function Name P70 to P77 I/O I/O Function After Reset Port 7. Alternate Function Input port KR0 to KR7 Input port INTP0/EXLVI 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 5-bit I/O port. P121 X1/OCD0A Input/output can be specified in 1-bit units. P122 Note X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 XT1 specified by a software setting. P124 P130 Note XT2/EXCLKS Output Port 13. - Output port 1-bit output-only port. P140 I/O Port 14. Input port 6-bit I/O port. P141 BUZ/BUSY0/INTP7 Input/output can be specified in 1-bit units. P142 SCKA0 Use of an on-chip pull-up resistor can be specified by a P143 PCL/INTP6 SIA0 software setting. P144 SOA0 P145 STB0 Note PD78F0547D and 78F0547DA (product with on-chip debug function) only (2) Non-port functions (1/3): 78K0/KF2 Function Name ANI0 to ANI7 I/O Input Function A/D converter analog input After Reset Analog Alternate Function P20 to P27 input BUSY0 Input CSIA0 busy input Input port P141/BUZ/INTP7 BUZ Output Buzzer output Input port P141/BUSY0/INTP7 EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0 Input port P62 EXSCL0 Input 2 External clock input for I C. To input an external clock, input a clock of 6.4 MHz. FLMD0 INTP0 - Input - Flash memory programming mode setting External interrupt request input for which the valid edge Input port (rising edge, falling edge, or both rising and falling edges) INTP1 - P120/EXLVI P30 can be specified P31/OCD1A Note INTP3 P32/OCD1B Note INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP6 P140/PCL INTP2 P141/BUZ/BUSY0 INTP7 KR0 to KR7 Input Key interrupt input Input port P70 to P77 Note PD78F0547D and 78F0547DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 75 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/3): 78K0/KF2 Function Name PCL I/O Output Function Clock output (for trimming of high-speed system clock, After Reset Input port Alternate Function P140/INTP6 subsystem clock) - REGC Connecting regulator output (2.5 V) stabilization capacitance - - - - for internal operation. Connect to VSS via a capacitor (0.47 to 1 F). RESET Input System reset input RxD0 Input Serial data input to UART0 Input port P11/SI10 RxD6 Input Serial data input to UART6 Input port P14 SCK10 I/O Clock input/output for CSI10, CSI11 Input port P10/TxD0 SCK11 P04 SCKA0 I/O Clock input/output for CSIA0 SCL0 I/O Clock input/output for I C 2 2 Input port P142 Input port P60 SDA0 I/O Serial data I/O for I C Input port P61 SI10 Input Serial data input to CSI10, CSI11 Input port P11/RxD0 SI11 P03 SIA0 Input Serial data input to CSIA0 Input port P143 SO10 Output Serial data output from CSI10, CSI11 Input port P12 SO11 P02 SOA0 Output Serial data output from CSIA0 Input port P144 SSI11 Input Chip select input to CSI11 Input port P05/TI001 STB0 Output Strobe output from CSIA0 Input port P145 TI000 Input External count clock input to 16-bit timer/event counter 00 Input port P00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 External count clock input to 16-bit timer/event counter 01 TI001 P05/SSI11 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 TI010 Input Capture trigger input to capture register (CR000) of 16-bit Input port P01/TO00 timer/event counter 00 Capture trigger input to capture register (CR001) of 16-bit TI011 P06/TO01 timer/event counter 01 TI50 Input TI51 TO00 16-bit timer/event counter 00 output Output 8-bit timer/event counter 50 output TOH1 8-bit timer H0 output P01/TI010 P06/TI011 Input port 8-bit timer/event counter 51 output Output P17/TO50 P33/TO51/INTP4 Input port 16-bit timer/event counter 01 output TO51 TOH0 Input port External count clock input to 8-bit timer/event counter 51 Output TO01 TO50 External count clock input to 8-bit timer/event counter 50 P17/TI50 P33/TI51/INTP4 Input port 8-bit timer H1 output P15 P16/INTP5 TxD0 Output Serial data output from UART0 Input port P10/SCK10 TxD6 Output Serial data output from UART6 Input port P13 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 76 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (3/3): 78K0/KF2 Function Name I/O X1 - X2 - EXCLK Function Connecting resonator for main system clock After Reset Alternate Function Note Input port P121/OCD0A Input port P122/EXCLK/OCD0B Input External clock input for main system clock Input port P122/X2/OCD0B XT1 - Connecting resonator for subsystem clock Input port P123 XT2 - Input port P124/EXCLKS Input port P124/XT2 EXCLKS Input External clock input for subsystem clock VDD - Positive power supply for P121 to P124 and other than ports - - EVDD - Positive power supply for ports other than P20 to P27 and - - - - Note Note P121 to P124. Make EVDD the same potential as VDD. - AVREF A/D converter reference voltage input and positive power supply for P20 to P27 and A/D converter VSS - Ground potential for P121 to P124 and other than ports - - EVSS - Ground potential for ports other than P20 to P27 and P121 - - - - to P124. Make EVSS the same potential as VSS. - AVSS A/D converter ground potential. Make the same potential as VSS. OCD0A Note OCD1A Note OCD0B Note OCD1B Note Input Connection for on-chip debug mode setting pins (PD78F0547D and 78F0547DA only) - Input port P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note PD78F0547D and 78F0547DA (product with on-chip debug function) only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 77 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. See 1.4 Ordering Information and 2.1 Pin Function List. 2.2.1 P00 to P06 (port 0) P00 to P06 function as an I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P00/TI000 P01/TI010/TO00 P02/SO11 - P02 Note P03/SI11 - P03 Note P04/SCK11 - - P04 P05/TI001/SSI11 - - P05 P06/TI011/TO01 - - P02 Note P03 Note Note Note Note P06 Note The 78K0/KE2 products whose flash memory is less than 32 KB and 78K0/KD2 products are only provided with port functions and not alternate functions. Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P06 function as an I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input. (a) TI000, TI001 These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01. (b) TI010, TI011 These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01 These are timer output pins of 16-bit timer/event counters 00 and 01. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 78 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (d) SI11 This is a serial data input pin of serial interface CSI11. (e) SO11 This is a serial data output pin of serial interface CSI11. (f) SCK11 This is a serial clock I/O pin of serial interface CSI11. (g) SSI11 This is a chip select input pin of serial interface CSI11. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Remark : Mounted The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial data input pin of serial interface CSI10. (b) SO10 This is a serial data output pin of serial interface CSI10. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 79 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (c) SCK10 This is a serial clock I/O pin of serial interface CSI10. (d) RxD0 This is a serial data input pin of serial interface UART0. (e) RxD6 This is a serial data input pin of serial interface UART6. (f) TxD0 This is a serial data output pin of serial interface UART0. (g) TxD6 This is a serial data output pin of serial interface UART6. (h) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (i) TO50 This is a timer output pin of 8-it timer/event counter 50. (j) TOH0, TOH1 These are the timer output pins of 8-bit timers H0 and H1. (k) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 80 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (port 2) P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 - P25/ANI5 - P26/ANI6 - P27/ANI7 - Note Note Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter. Caution ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 81 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (port 3) P30 to P33 function as an I/O port. These pins also function as pins for external interrupt request input and timer I/O. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 P30/INTP1 P31/INTP2/ OCD1A Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Note P32/INTP3/ OCD1B 78K0/KF2 Note P33/INTP4/TI51/ TO51 Note OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as an I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input and timer I/O. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin from 8-bit timer/event counter 51. Caution 1. In the product with an on-chip debug function (PD78F05xxD and 78F05xxDA), be sure to pull the P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 82 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS Caution 2. Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. P31/INTP2/OCD1A Flash memory programmer connection On-chip debug During reset emulator connection During reset released Note Connect to EVSS Input: via a resistor. Connect to EVDD (when it is not used Note Note or EVSS via a resistor. as an on-chip debug Output: Leave open. mode setting pin) Note With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect them to VDD. Remark P31 and P32 of the product with an on-chip debug function (PD78F05xxD and 78F05xxDA) can be used as on-chip debug mode setting pins (OCD1A and OCD1B) when the on-chip debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY). 2.2.5 P40 to P47 (port 4) P40 to P47 function as an I/O port. P40 to P47 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). 78K0/KB2 78K0/KC2 78K0/KD2 P40 - P41 - P42 - - P43 - P44 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB - - - - P45 - - - P46 - - - P47 - - - Note Note Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 0 and 1 of PM4 and P4 to "0". Remark : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 83 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.2.6 P50 to P57 (port 5) P50 to P57 function as an I/O port. P50 to P57 can be set to input or output port in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P50 - P51 - P52 - P53 - P54 - - P55 - - P56 - - P57 - - Remark : Mounted, -: Not mounted 2.2.7 P60 to P67 (port 6) P60 to P67 function as an I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and external clock input. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P60/SCL0 P61/SDA0 P62/EXSCL0 - P63 - P64 - - P65 - - P66 - - P67 - - Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 84 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port mode P60 to P67 function as an I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). Only for P64 to P67, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 6 (PU6). Output of P60 to P63 is N-ch open-drain output (6 V tolerance). (2) Control mode P60 to P67 function as serial interface data I/O, clock I/O, and external clock input. (a) SDA0 This is a serial data I/O pin for serial interface IIC0. (b) SCL0 This is a serial clock I/O pin for serial interface IIC0. (c) EXSCL0 This is an external clock input pin to serial interface IIC0. To input an external clock, input a clock of 6.4 MHz. 2.2.8 P70 to P77 (port 7) P70 to P77 function as an I/O port. These pins also function as key interrupt input pins. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P70/KR0 - P71/KR1 - P72/KR2 - P73/KR3 - P74/KR4 - P75/KR5 Note 1 Note 1 P74 Note 2 - P75 Note 2 P76/KR6 - - P77/KR7 - - Notes 1. 78K0/KF2 This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 2 and 3 of PM7 and P7 to "0". 2. This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only provided with port functions and not alternate functions. Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 85 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (1) Port mode P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. (a) KR0 to KR7 These are the key interrupt input pins. 2.2.9 P120 to P124 (port 12) P120 to P124 function as an I/O port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P120/INTP0/EXLVI Note P123/XT1 - P124/XT2/EXCLKS - P121/X1/OCD0A P122/X2/EXCLK/ OCD0B 78K0/KF2 Note Note OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. (1) Port mode P120 to P124 function as an I/O port. P120 to P124 can be set to input or output port using port mode register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. (a) INTP0 This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 86 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are the pins for connecting a resonator for main system clock. (d) EXCLK This is an external clock input pin for main system clock. (e) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. (f) EXCLKS This is an external clock input pin for subsystem clock. Caution Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. P121/X1/OCD0A Flash memory programmer connection On-chip debug During reset emulator connection During reset released Connect to VSS via a resistor. Input: (when it is not used Connect to VDD or VSS via a resistor. as an on-chip debug Output: Leave open. mode setting pin) Remark X1 and X2 of the product with an on-chip debug function (PD78F05xxD and 78F05xxDA) can be used as on-chip debug mode setting pins (OCD0A and OCD0B) when the on-chip debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY). 2.2.10 P130 (port 13) P130 functions as an output-only port. 78K0/KB2 P130 78K0/KC2 - 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Note Note This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. Remarks 1. When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure for Remark in 5.2.10 Port 13). 2. : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 87 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.2.11 P140 to P145 (port 14) P140 to P145 function as an I/O port. These pins also function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P140/PCL/INTP6 - P141/BUZ/BUSY0/ - - - P142/SCKA0 - - - - P143/SIA0 - - - - P144/SOA0 - - - - P145/STB0 - - - - Note 1 P141/BUZ/INTP7 Note 2 INTP7 Notes 1. 2. This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 78K0/KE2 products are not provided with the BUSY0 input function. Remark : Mounted, -: Not mounted The following operation modes can be specified in 1-bit units. (1) Port mode P140 to P145 function as an I/O port. P140 to P145 can be set to input or output port in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 to P145 function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. (c) BUZ This is a buzzer output pin. (d) BUSY0 This is a serial interface CSIA0 busy input pin. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 88 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (e) SIA0 This is a serial interface CSIA0 serial data input pin. (f) SOA0 This is a serial interface CSIA0 serial data output pin. (g) SCKA0 This is a serial interface CSIA0 serial clock I/O pin. (h) STB0 This is a serial interface CSIA0 strobe output pin. 2.2.12 AVREF, AVSS, VDD, EVDD, VSS, EVSS 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB AVREF AVSS - - VDD EVDD Note Note VSS EVSS Note This is not mounted onto 30-pin products of the 78K0/KB2. Remark : Mounted, -: Not mounted (a) AVREF This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27 and A/D converter. When the A/D converter is not used, connect this pin directly to EVDD or VDDNote. Note Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. (b) AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 89 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS (c) VDD and EVDD VDD is the positive power supply pin for P121 to P124 and other than portsNote. EVDD is the positive power supply pin for ports other than P20 to P27 and P121 to P124. Always make EVDD the same potential as VDD. Note With products that are not mounted with an EVDD pin, use VDD as a positive power supply pin other than P20 to P27. (d) VSS and EVSS VSS is the ground potential pin for P121 to P124 and other than ports. EVSS is the ground potential pin for ports other than P20 to P27 and P121 to P124. Always make EVSS the same potential as VSS. Note With products that are not mounted with an EVSS pin, use VSS as a ground potential pin other than P20 to P27. 2.2.13 RESET This is the active-low system reset input pin. 2.2.14 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 F). REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. 2.2.15 FLMD0 This is a pin for setting flash memory programming mode. Connect FLMD0 to EVSS or VSS in the normal operation mode. In flash memory programming mode, connect this pin to the flash memory programmer. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 90 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Remark The pins mounted depend on the product. See 1.5 Ordering Information (Top View) and 2.1 Pin Function List. Table 2-3. Pin I/O Circuit Types (1/3) Pin Name I/O Circuit Type P00/TI000 5-AQ I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P01/TI010/TO00 P02/SO11 5-AG P03/SI11 Note 1 P04/SCK11 P05/TI001/SSI11 P06/TI011/TO01 5-AQ P10/SCK10/TxD0 P11/SI10/RxD0 5-AG P12/SO10 P13/TxD6 P14/RxD6 5-AQ P15/TOH0 5-AG P16/TOH1/INTP5 5-AQ P17/TI50/TO50 ANI0/P20 to ANI7/P27 Note 2 11-G < Digital input setting and analog input setting> Independently connect to AVREF or AVSS via a resistor. <Digital output setting> Leave open. Notes 1. "5-AG" type: 78K0/KE2 whose flash memory is less than 32 KB and 78K0/KD2 "5-AQ" type: 78K0/KE2 whose flash memory is at least 48 KB and 78K0/KF2 (Products other than the above are not mounted with P03 to P06.) 2. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 91 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (2/3) Pin Name I/O Circuit Type P30/INTP1 5-AQ P31/INTP2/OCD1A I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Note 1 P32/INTP3/OCD1B P33/TI51/TO51/INTP4 5-AG P40 to P47 P50 to P57 P60/SCL0 Input: 13-AI Independently connect to EVDD or EVSS via a resistor, or connect directly to EVSS. P61/SDA0 Output: Leave this pin open at low-level output after clearing P62/EXSCL0 the output latch of the port to 0. P63 13-P P64 to P67 5-AG Input: 5-AQ Output: Leave open. 37 Input: P70/KR0 to P77/KR7 Independently connect to EVDD or EVSS via a resistor. P120/INTP0/EXLVI P121/X1/OCD0A Notes 1, 2 P122/X2/EXCLK/ OCD0B Independently connect to VDD or VSS via a resistor. Output: Leave open. Notes 2 P123/XT1 Note 2 P124/XT2/EXCLKS Note 2 P130 3-C Output Leave open. Notes 1. Process the P31/INTP2/OCD1A and P121/X1/OCD0A pins of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. P31/INTP2/OCD1A Flash memory programmer connection On-chip debug During reset emulator During reset connection (when released it is not used as an P121/X1/OCD0A Connect to EVSS via a Connect to VSS via a resistor. resistor. Input: Connect to EVDD or Input: EVSS via a resistor. Output: Leave open. Connect to VDD or VSS via a resistor. Output: Leave open. on-chip debug mode setting pin) 2. Use recommended connection above in I/O port mode (see Figure 6-3 and Figure 6-4 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 92 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (3/3) Pin Name P140/PCL/INTP6 I/O Circuit Type I/O Input: I/O 5-AQ Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 5-AG P145/STB0 - <R> AVREF - <When one or more of P20 to P27 are set as a digital port> Make this pin the same potential as EVDD and VDD. <When all of P20 to P27 are set as analog ports> Make this pin to have a potential where 1.8 V AVREF VDD. - <R> AVSS FLMD0 38-A <R> RESET 2 Make this pin the same potential as the EVSS and VSS. - Connect to EVSS or VSS Input - <R> REGC - - Note . Connect directly to EVDD or via a resistor. Connect to VSS via capacitor (0.47 to 1 F). Note FLMD0 is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory on-board, connect this pin to EVSS or VSS via a resistor (10 k: recommended). The same applies when executing on-chip debugging with a product with an on-chip debug function (PD78F05xxD and 78F05xxDA). Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 93 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AG EVDD Pull-up enable P-ch EVDD IN Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch EVSS Input enable Type 3-C Type 5-AQ EVDD pullup enable EVDD P-ch Data P-ch EVDD OUT data P-ch IN/OUT N-ch output disable N-ch EVSS EVSS input enable Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 94 78K0/Kx2 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-G Type 37 VDD Data AVREF P-ch X2, XT2 Data P-ch IN/OUT Output disable N-ch RESET Output disable VSS N-ch P-ch VDD Comparator N-ch Input enable AVSS P-ch + Data _ P-ch N-ch X1, XT1 Series resistor string voltage Output disable AVSS N-ch RESET VSS Input enable Input enable Type 13-P Type 38-A IN/OUT Data Output disable IN N-ch EVSS input enable Input enable Type 13-AI IN/OUT data output disable N-ch EVSS input enable Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 95 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/Kx2 microcontrollers can access a 64 KB memory space. Figures 3-1 to 3-11 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Kx2 microcontrollers are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. 2. To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) (78K0/KB2, and 38-pin products and 44-pin products of the 78K0/KC2) 78K0/KB2 38-pin products and IMS ROM Capacity Internal High-Speed RAM Capacity 44-pin products of the 78K0/KC2 PD78F0500, - 42H 8 KB 512 bytes 04H 16 KB 768 bytes C6H 24 KB 1 KB C8H 32 KB 1 KB 78F0500A PD78F0501, PD78F0511, 78F0501A 78F0511A PD78F0502, PD78F0512, 78F0502A 78F0512A PD78F0503, PD78F0513, 78F0503A, 78F0513A, Note 78F0503D 78F0503DA , Note Note 78F0513D 78F0513DA , Note Note The ROM and RAM capacities of the products with the on-chip debug function can be debugged by setting IMS, according to the debug target products. Set IMS according to the debug target products. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 96 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-2. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) (48-pin products of the 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) 48-pin 78K0/KD2 78K0/KE2 78K0/KF2 IMS IXS products ROM Internal Internal Capacity High- Expansion of the Speed RAM 78K0/KC2 RAM Capacity Capacity PD78F0511, PD78F0521, PD78F0531, 78F0511A 78F0521A 78F0531A PD78F0512, 78F0512A PD78F0522, 78F0522A - 04H 0CH 16 KB 768 bytes - PD78F0532, 78F0532A - C6H 0CH 24 KB 1 KB - - C8H 0CH 32 KB 1 KB - PD78F0544, 78F0544A CCH 0AH 48 KB 1 KB CFH 08H 60 KB CCH 04H 96 KB 00H 128 KB PD78F0513, PD78F0523, PD78F0533, 78F0513A 78F0523A 78F0533A PD78F0514, PD78F0524, PD78F0534, 78F0514A 78F0524A 78F0534A PD78F0515, PD78F0525, PD78F0535, 78F0515A, Note 1 78F0515D , 78F0525A 78F0535A PD78F0545, 78F0545A PD78F0526, 78F0526A PD78F0536, 78F0536A PD78F0546, 78F0546A PD78F0527, 78F0527A, Note 1 78F0527D , Note 1 78F0527DA PD78F0537, 78F0537A, Note 1 78F0537D , Note 1 78F0537DA PD78F0547, 78F0547A, Note 1 78F0547D , Note 1 78F0547DA 1 KB 2 KB Note 1 78F0515DA - - Note 2 4 KB Note 2 CCH Note 2 6 KB Note 2 Notes 1. The ROM and RAM capacities of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS and IXS according to the debug target products. 2. The PD78F05x6 and 78F05x6A (x = 2 to 4) have internal ROMs of 96 KB, and the PD78F05x7, 78F05x7A, 78F05x7D and 78F05x7DA (x = 2 to 4) have those of 128 KB. However, the set value of IMS of these devices is the same as those of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.3 Memory Bank Select Register (BANK). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 97 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (PD78F0500 and 78F0500A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH 1FFFH Program area Internal high-speed RAM 512 x 8 bits 1085H 1084H 1080H 107FH FD00H FCFFH Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Reserved Program area 1915 x 8 bits 0085H 0084H 0080H 007FH 2000H 1FFFH 0040H 003FH Program memory space Flash memory 8192 x 8 bits Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. 1FFFH Block 07H 1C00H 1BFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 98 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F0501, 78F0501A, 78F0511, 78F0511A, 78F0521, 78F0521A, 78F0531, and 78F0531A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits 3FFFH Program area 1FFFH Internal high-speed RAM 768 x 8 bits 1085H 1084H 1080H 107FH FC00H FBFFH Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Reserved Program area 1915 x 8 bits 0085H 0084H 0080H 007FH 4000H 3FFFH Program memory space 0040H 003FH Flash memory 16384 x 8 bits Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. 3FFFH Block 0FH 3C00H 3BFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 99 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F0502, 78F0502A, 78F0512, 78F0512A, 78F0522, 78F0522A, 78F0532, and 78F0532A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits 5FFFH Program area 1FFFH Internal high-speed RAM 1024 x 8 bits 1085H 1084H 1080H 107FH FB00H FAFFH areaNote 1 Option byte 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Reserved 0085H 0084H 0080H 007FH Program area 1915 x 8 bits Option byte areaNote 1 5 x 8 bits 6000H 5FFFH Program memory space CALLT table area 64 x 8 bits 0040H 003FH Flash memory 24576 x 8 bits Boot cluster 0Note 2 Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. 5FFFH Block 17H 5C00H 5BFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 100 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD78F0503, 78F0503A, 78F0513, 78F0513A, 78F0523, 78F0523A, 78F0533 and 78F0533A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH 7FFFH Program area 1085H 1084H 1080H 107FH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Option byte areaNote 1 5 x 8 bits 1FFFH Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits Reserved 0800H 07FFH 0085H 0084H 0080H 007FH 8000H 7FFFH 0040H 003FH Program memory space Flash memory 32768 x 8 bits 0000H 0000H Program area 1915 x 8 bits Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. 7FFFH Block 1FH 7C00H 7BFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 101 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD78F0503D, 78F0503DA, 78F0513D, and 78F0513DA) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH 7FFFH Program area 108FH 108EH General-purpose registers 32 x 8 bits FEE0H FEDFH 1085H 1084H Internal high-speed RAM 1024 x 8 bits 1FFFH On-chip debug security ID setting areaNote 1 10 x 8 bits Boot cluster 1 Option byte areaNote 1 5 x 8 bits 1080H 107FH Program area 1000H 0FFFH FB00H FAFFH CALLF entry area 2048 x 8 bits Data memory space 0800H 07FFH Program area 1905 x 8 bits Reserved 008FH 008EH 0085H 0084H 0080H 007FH On-chip debug security ID setting areaNote 1 10 x 8 bits Option byte areaNote 1 5 x 8 bits 8000H 7FFFH Program memory space Boot cluster 0Note 2 CALLT table area 64 x 8 bits 0040H 003FH Flash memory 32768 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to 0085H to 008EH. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. 7FFFH Block 1FH 7C00H 7BFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 102 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (PD78F0514, 78F0514A, 78F0524, 78F0524A, 78F0534, 78F0534A, 78F0544, and 78F0544A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH Data memory space General-purpose registers 32 x 8 bits BFFFH Internal high-speed RAM 1024 x 8 bits Program area 1FFFH 1085H 1084H 1080H 107FH Reserved Buffer RAM 32 x 8 bitsNote 3 FA00H F9FFH F800H F7FFH 1000H 0FFFH Reserved CALLF entry area 2048 x 8 bits Internal expansion RAM 1024 x 8 bits 0800H 07FFH Program area 1915 x 8 bits F400H F3FFH 0085H 0084H 0080H 007FH Reserved C000H BFFFH Program memory space Boot cluster 1 Program area Program RAM area RAM space in which instruction can be fetched Option byte areaNote 1 5 x 8 bits 0040H 003FH Flash memory 49152 x 8 bits Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). 3. The buffer RAM is incorporated only in the PD78F0544 and 78F0544A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0514, 78F0514A, 78F0524, 78F0524A, 78F0534, and 78F0534A. Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. BFFFH Block 2FH BC00H BBFFH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 103 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Memory Map (PD78F0515, 78F0515A, 78F0525, 78F0525A, 78F0535, 78F0535A, 78F0545, and 78F0545A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH General-purpose registers 32 x 8 bits EFFFH Internal high-speed RAM 1024 x 8 bits Program area 1FFFH 1085H 1084H 1080H 107FH Reserved Buffer RAM 32 x 8 bitsNote 3 Data memory space FA00H F9FFH F800H F7FFH Boot cluster 1 Program area 1000H 0FFFH Reserved CALLF entry area 2048 x 8 bits Program RAM area RAM space in which instruction can be fetched Option byte areaNote 1 5 x 8 bits Internal expansion RAM 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits F000H EFFFH Program memory space 0085H 0084H 0080H 007FH Flash memory 61440 x 8 bits 0040H 003FH Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). 3. The buffer RAM is incorporated only in the PD78F0545 and 78F0545A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0515, 78F0515A, 78F0525, 78F0525A, 78F0535, and 78F0535A. Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. EFFFH EC00H EBFFH Block 3BH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 104 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map (PD78F0515D and 78F0515DA) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH EFFFH Program area 1FFFH General-purpose registers 32 x 8 bits 108FH 108EH 1085H 1084H 1080H 107FH Internal high-speed RAM 1024 x 8 bits Data memory space On-chip debug security ID setting areaNote 1 10 x 8 bits Option byte areaNote 1 5 x 8 bits FB00H FAFFH Boot cluster 1 Program area 1000H 0FFFH Reserved CALLF entry area 2048 x 8 bits F800H F7FFH RAM space in which instruction can be fetched 0800H 07FFH Program area 1905 x 8 bits Internal expansion RAM 2048 x 8 bits 008FH 008EH F000H EFFFH On-chip debug security ID setting areaNote1 10 x 8 bits 0085H 0084H Option byte areaNote 1 5 x 8 bits 0080H 007FH Program memory space Boot cluster 0Note 2 CALLT table area 64 x 8 bits Flash memory 61440 x 8 bits 0040H 003FH Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to 0085H to 008EH. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. EFFFH EC00H EBFFH Block 3BH 07FFH 0400H 03FFH 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Block 01H Block 00H 1 KB 105 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Memory Map (PD78F0526, 78F0526A, 78F0536, 78F0536A, 78F0546, and 78F0546A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH 7FFFH Program area Reserved 1FFFH 1085H 1084H 1080H 107FH Buffer RAM 32 x 8 bitsNote 3 Data memory space FA00H F9FFH F800H F7FFH Program RAM area Reserved RAM space in which instruction can be fetched E800H E7FFH Internal expansion RAM 4096 x 8 bits 1000H 0FFFH (Memory bank 2) CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits C000H BFFFH 0085H 0084H 0080H 007FH Flash memory 16384 x 8 bits (memory bank 0) 8000H Program 7FFFH memory space Common area (Memory bank 3) Flash memory 32768 x 8 bits Boot cluster 1 Program area Reserved Bank area Option byte areaNote 1 5 x 8 bits (Memory bank 1) 0040H 003FH Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). 3. The buffer RAM is incorporated only in the PD78F0546 and 78F0546A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0526, 78F0526A, 78F0536, and 78F0536A. Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) BFFFH BC00H BBFFH Bank area (Memory bank 1) (Memory bank 2) (Memory bank 3) Block 2FH Block 3FH Block 4FH Block 5FH Block 20H Block 30H Block 40H Block 50H 84FFH 83FFH 8000H 7FFFH Block 1FH 7C00H 7BFFH Common area 07FFH 0400H 03FFH 1 KB 0000H Block 01H Block 00H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 106 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Memory Map (PD78F0527, 78F0527A, 78F0537, 78F0537A, 78F0547, and 78F0547A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH 7FFFH Program area Reserved 1FFFH 1085H 1084H 1080H 107FH Buffer RAM 32 x 8 bitsNote 3 Data memory space FA00H F9FFH F800H F7FFH Reserved Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area (Memory bank 4) Program RAM area Internal expansion RAM 6144 x 8 bits RAM space in which instruction can be fetched E000H DFFFH (Memory bank 2) 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Reserved Program area 1915 x 8 bits C000H BFFFH 0085H 0084H 0080H 007FH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H Program 7FFFH memory space Common area (Memory bank 5) (Memory bank 3) Flash memory 32768 x 8 bits 0040H 003FH (Memory bank 1) Option byte areaNote 1 5 x 8 bits Boot cluster 0Note 2 CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). 3. The buffer RAM is incorporated only in the PD78F0547 and 78F0547A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0527, 78F0527A, 78F0537 and 78F0537A. Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) (Memory bank 1) (Memory bank 5) (Memory bank 2) BFFFH BC00H BBFFH Bank area Block 2FH Block 3FH ... 84FFH 83FFH 8000H 7FFFH Block 7FH Block 4FH Block 20H Block 30H Block 40H Block 70H Block 1FH 7C00H 7BFFH Common area 07FFH 1 KB 0400H 03FFH 0000H Block 01H Block 00H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 107 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Memory Map (PD78F0527D, 78F0527DA, 78F0537D, 78F0537DA, 78F0547D, and 78F0547DA) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH 7FFFH General-purpose registers 32 x 8 bits FEE0H FEDFH FB00H FAFFH FA20H FA1FH Program area 108FH 108EH Internal high-speed RAM 1024 x 8 bits 1085H 1084H Reserved 1080H 107FH Buffer RAM 32 x 8 bitsNote 3 Data memory space FA00H F9FFH F800H F7FFH 1FFFH On-chip debug security ID setting areaNote 1 10 x 8 bits Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area 1000H 0FFFH Reserved CALLF entry area 2048 x 8 bits (Memory bank 4) Program RAM area RAM space in which instruction can be fetched E000H DFFFH Internal expansion RAM 6144 x 8 bits (Memory bank 2) 0800H 07FFH Program area 1905 x 8 bits 008FH 008EH Reserved C000H BFFFH 0085H 0084H 0080H 007FH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H 7FFFH Program memory space Common area (Memory bank 5) (Memory bank 3) Flash memory 32768 x 8 bits 0040H 003FH (Memory bank 1) On-chip debug security ID setting areaNote 1 10 x 8 bits Boot cluster 0Note 2 Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to 0085H to 008EH. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security Settings). 3. The buffer RAM is incorporated only in the PD78F0547D and 78F0547DA (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0527D, 78F0527DA, 78F0537D and 78F0537DA. Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) (Memory bank 1) (Memory bank 5) (Memory bank 2) BFFFH BC00H BBFFH Bank area Block 2FH Block 3FH ... 84FFH 83FFH 8000H 7FFFH Block 7FH Block 4FH Block 20H Block 30H Block 40H Block 70H Block 1FH 7C00H 7BFFH Common area 07FFH 1 KB 0400H 03FFH 0000H Block 01H Block 00H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 108 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-3. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) (1) Products whose flash memory is less than 60 KB (without memory bank) Address Value Block Block Address Value Address Value Block Address Value Block Number Number Number Number 0000H to 03FFH 00H 4000H to 43FFH 10H 8000H to 83FFH 20H C000H to C3FFH 30H 0400H to 07FFH 01H 4400H to 47FFH 11H 8400H to 87FFH 21H C400H to C7FFH 31H 0800H to 0BFFH 02H 4800H to 4BFFH 12H 8800H to 8BFFH 22H C800H to CBFFH 32H 0C00H to 0FFFH 03H 4C00H to 4FFFH 13H 8C00H to 8FFFH 23H CC00H to CFFFH 33H 1000H to 13FFH 04H 5000H to 53FFH 14H 9000H to 93FFH 24H D000H to D3FFH 34H 1400H to 17FFH 05H 5400H to 57FFH 15H 9400H to 97FFH 25H D400H to D7FFH 35H 1800H to 1BFFH 06H 5800H to 5BFFH 16H 9800H to 9BFFH 26H D800H to DBFFH 36H 1C00H to 1FFFH 07H 5C00H to 5FFFH 17H 9C00H to 9FFFH 27H DC00H to DFFFH 37H 2000H to 23FFH 08H 6000H to 63FFH 18H A000H to A3FFH 28H E000H to E3FFH 38H 2400H to 27FFH 09H 6400H to 67FFH 19H A400H to A7FFH 29H E400H to E7FFH 39H 2800H to 2BFFH 0AH 6800H to 6BFFH 1AH A800H to ABFFH 2AH E800H to EBFFH 3AH 2C00H to 2FFFH 0BH 6C00H to 6FFFH 1BH AC00H to AFFFH 2BH EC00H to EFFFH 3BH 3000H to 33FFH 0CH 7000H to 73FFH 1CH B000H to B3FFH 2CH 3400H to 37FFH 0DH 7400H to 77FFH 1DH B400H to B7FFH 2DH 3800H to 3BFFH 0EH 7800H to 7BFFH 1EH B800H to BBFFH 2EH 3C00H to 3FFFH 0FH 7C00H to 7FFFH 1FH BC00H to BFFFH 2FH Remark PD78F0500, 78F0500A: PD78F05x1, 78F05x1A (x = 0 to 3): PD78F05x2, 78F05x2A (x = 0 to 3): PD78F05x3, 78F05x3A (x = 0 to 3), Block numbers 00H to 07H 78F0503D, 78F0503DA, 78F0513D, 78F0513DA: Block numbers 00H to 1FH Block numbers 00H to 0FH Block numbers 00H to 17H PD78F05x4, 78F05x4A (x = 1 to 4): Block numbers 00H to 2FH PD78F05x5, 78F05x5A (x = 1 to 4), 78F0515D, 78F0515DA: Block numbers 00H to 3BH R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 109 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) Address Value 0000H to 03FFH 00H 8000H to 83FFH 0400H to 07FFH 01H 0800H to 0BFFH 0 Block Address Value Number 20H 8000H to 83FFH 8400H to 87FFH 21H 02H 8800H to 8BFFH 0C00H to 0FFFH 03H 1000H to 13FFH 2 Block Address Value Number Memory Bank Block Number Memory Bank Address Value Memory Bank (2) Products whose flash memory is at least 96 KB (with memory bank) 4 Block Number 40H 8000H to 83FFH 8400H to 87FFH 41H 8400H to 87FFH 61H 22H 8800H to 8BFFH 42H 8800H to 8BFFH 62H 8C00H to 8FFFH 23H 8C00H to 8FFFH 43H 8C00H to 8FFFH 63H 04H 9000H to 93FFH 24H 9000H to 93FFH 44H 9000H to 93FFH 64H 1400H to 17FFH 05H 9400H to 97FFH 25H 9400H to 97FFH 45H 9400H to 97FFH 65H 1800H to 1BFFH 06H 9800H to 9BFFH 26H 9800H to 9BFFH 46H 9800H to 9BFFH 66H 1C00H to 1FFFH 07H 9C00H to 9FFFH 27H 9C00H to 9FFFH 47H 9C00H to 9FFFH 67H 2000H to 23FFH 08H A000H to A3FFH 28H A000H to A3FFH 48H A000H to A3FFH 68H 2400H to 27FFH 09H A400H to A7FFH 29H A400H to A7FFH 49H A400H to A7FFH 69H 2800H to 2BFFH 0AH A800H to ABFFH 2AH A800H to ABFFH 4AH A800H to ABFFH 6AH 2C00H to 2FFFH 0BH AC00H to AFFFH 2BH AC00H to AFFFH 4BH AC00H to AFFFH 6BH 3000H to 33FFH 0CH B000H to B3FFH 2CH B000H to B3FFH 4CH B000H to B3FFH 6CH 3400H to 37FFH 0DH B400H to B7FFH 2DH B400H to B7FFH 4DH B400H to B7FFH 6DH 3800H to 3BFFH 0EH B800H to BBFFH 2EH B800H to BBFFH 4EH B800H to BBFFH 6EH 3C00H to 3FFFH 0FH BC00H to BFFFH 2FH BC00H to BFFFH 4FH BC00H to BFFFH 6FH 4000H to 43FFH 10H 8000H to 83FFH 30H 8000H to 83FFH 50H 8000H to 83FFH 4400H to 47FFH 11H 8400H to 87FFH 31H 8400H to 87FFH 51H 8400H to 87FFH 71H 4800H to 4BFFH 12H 8800H to 8BFFH 32H 8800H to 8BFFH 52H 8800H to 8BFFH 72H 4C00H to 4FFFH 13H 8C00H to 8FFFH 33H 8C00H to 8FFFH 53H 8C00H to 8FFFH 73H 5000H to 53FFH 14H 9000H to 93FFH 34H 9000H to 93FFH 54H 9000H to 93FFH 74H 5400H to 57FFH 15H 9400H to 97FFH 35H 9400H to 97FFH 55H 9400H to 97FFH 75H 5800H to 5BFFH 16H 9800H to 9BFFH 36H 9800H to 9BFFH 56H 9800H to 9BFFH 76H 5C00H to 5FFFH 17H 9C00H to 9FFFH 37H 9C00H to 9FFFH 57H 9C00H to 9FFFH 77H 6000H to 63FFH 18H A000H to A3FFH 38H A000H to A3FFH 58H A000H to A3FFH 78H 6400H to 67FFH 19H A400H to A7FFH 39H A400H to A7FFH 59H A400H to A7FFH 79H 6800H to 6BFFH 1AH A800H to ABFFH 3AH A800H to ABFFH 5AH A800H to ABFFH 7AH 6C00H to 6FFFH 1BH AC00H to AFFFH 3BH AC00H to AFFFH 5BH AC00H to AFFFH 7BH 7000H to 73FFH 1CH B000H to B3FFH 3CH B000H to B3FFH 5CH B000H to B3FFH 7CH 7400H to 77FFH 1DH B400H to B7FFH 3DH B400H to B7FFH 5DH B400H to B7FFH 7DH 7800H to 7BFFH 1EH B800H to BBFFH 3EH B800H to BBFFH 5EH B800H to BBFFH 7EH 7C00H to 7FFFH 1FH BC00H to BFFFH 3FH BC00H to BFFFH 5FH BC00H to BFFFH 7FH Remark 1 3 5 60H 70H PD78F05x6, 78F05x6A (x = 2 to 4): Block numbers 00H to 5FH PD78F05x7, 78F05x7A, 78F05x7D, 78F05x7DA (x = 2 to 4): Block numbers 00H to 7FH R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 110 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/Kx2 microcontrollers incorporate internal ROM (flash memory), as shown below. Table 3-4. Internal ROM Capacity 78K0/KB2 30/36 Pins PD78F0500, PD78F0500A 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Internal ROM (Flash memory) 38/44 Pins 48 Pins 52 Pins 64 Pins 80 Pins - - - - - 8192 x 8 bits (0000H to 1FFFH) PD78F0501, 78F0501A PD78F0511, 78F0511A PD78F0511, 78F0511A PD78F0521, 78F0521A PD78F0531, 78F0531A - 16384 x 8 bits (0000H to 3FFFH) PD78F0502, 78F0502A PD78F0512, 78F0512A PD78F0512, 78F0512A PD78F0522, 78F0522A PD78F0532, 78F0532A - 24576 x 8 bits PD78F0503D, 78F0503DA PD78F0513D, 78F0513DA PD78F0513, 78F0513A PD78F0523, 78F0523A PD78F0533, 78F0533A - PD78F0503, 78F0503A PD78F0513, 78F0513A PD78F0514, 78F0514A PD78F0524, 78F0524A PD78F0534, 78F0534A PD78F0544, 78F0544A 49152 x 8 bits PD78F0515D, 78F0515DA PD78F0525, PD78F0535, 78F0535A PD78F0545, 78F0545A 61440 x 8 bits 78F0525A PD78F0526, 78F0526A PD78F0536, 78F0536A PD78F0546, 78F0546A 98304 x 8 bits - - - - (0000H to 5FFFH) 32768 x 8 bits (0000H to 7FFFH) (0000H to BFFFH) (0000H to EFFFH) PD78F0515, 78F0515A - - - (0000H to 7FFFH (common area: 32 KB) + 8000H to BFFFH (bank area: 16 KB) x 4) - - - PD78F0527D, 78F0527DA PD78F0537D, 78F0537DA PD78F0547D, 78F0547DA 131072 x 8 bits PD78F0527, 78F0527A PD78F0537, 78F0537A PD78F0547, 78F0547A (common area: 32 KB) (0000H to 7FFFH + 8000H to BFFFH (bank area: 16 KB) x 6) The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 111 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Vector Table Vector Table Address Interrupt Source KB2 KC2 KD2 KE2 KF2 0000H RESET input, POC, LVI, WDT 0004H INTLVI 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTP4 0010H INTP5 0012H INTSRE6 0014H INTSR6 0016H INTST6 0018H INTCSI10/INTST0 001AH INTTMH1 001CH INTTMH0 001EH INTTM50 0020H INTTM000 0022H INTTM010 0024H INTAD 0026H INTSR0 0028H INTWTI - 002AH INTTM51 002CH INTKR - 002EH INTWT - 0030H INTP6 - 0032H INTP7 0034H INTIIC0/NTDMU Note 1 Note 2 - Note 2 - - Note 2 Note 2 INTCSI11 - - - INTTM001 - - - INTTM011 - - - 003CH INTACSI - - - - 003EH BRK 0036H 0038H 003AH Note 3 Note 3 Note 3 Notes 1. 48-pin products only. 2. INTIIC0: products whose flash memory is less than 32 KB INTIIC/INTDMU: products whose flash memory is at least 48 KB 3. Products whose flash memory is at least 48 KB only. Remark : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 112 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, see CHAPTER 26 OPTION BYTE. (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). (5) On-chip debug security ID setting area (PD78F05xxD and 78F05xxDA only) A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at 0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY). 3.1.2 Memory bank (products whose flash memory is at least 96 KB only) The 16 KB area 8000H to BFFFH is assigned to memory banks 0 to 3 in the PD78F05x6 and 78F05x6A (x = 2 to 4), and assigned to memory banks 0 to 5 in the PD78F05x7, 78F05x7A, 78F05x7D and 78F05x7DA (x = 2 to 4). The banks are selected by using a memory bank select register (BANK). For details, see CHAPTER 4 MEMORY BANK SELECT FUNCTION (PRODUCTS WHOSE FLASH MEMORY IS AT LEAST 96 KB ONLY). Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branch and access cannot be directly executed between different memory banks. Execute branch or access between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 113 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space 78K0/Kx2 microcontrollers incorporate the following RAMs. (1) Internal high-speed RAM The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. Table 3-6. Internal High-Speed RAM Capacity 78K0/KB2 30/36 Pins PD78F0500, PD78F0500A 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Internal High-Speed RAM 38/44 Pins 48 Pins 52 Pins 64 Pins 80 Pins - - - - - 512 x 8 bits (FD00H to FEFFH) PD78F0501, 78F0501A PD78F0511, 78F0511A PD78F0511, 78F0511A PD78F0521, 78F0521A PD78F0531, 78F0531A - PD78F0502, 78F0502A PD78F0512, 78F0512A PD78F0512, 78F0512A PD78F0522, 78F0522A PD78F0532, 78F0532A - PD78F0503D, PD78F0513D, 78F0513DA PD78F0513, 78F0513A PD78F0523, 78F0523A PD78F0533, 78F0533A - 78F0503DA PD78F0503, 78F0503A 78F0513A 768 x 8 bits (FC00H to FEFFH) 1024 x 8 bits (FB00H to FEFFH) PD78F0513, - - PD78F0514, 78F0514A PD78F0524, 78F0524A PD78F0534, 78F0534A PD78F0544, 78F0544A - - PD78F0515D, 78F0515DA PD78F0525, 78F0525A PD78F0535, 78F0535A PD78F0545, 78F0545A PD78F0515, 78F0515A - - - PD78F0526, 78F0526A PD78F0536, 78F0536A PD78F0546, 78F0546A - - - PD78F0527D, 78F0527DA PD78F0537D, 78F0537DA PD78F0547D, 78F0547DA PD78F0527, 78F0527A PD78F0537, 78F0537A PD78F0547, 78F0547A R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 114 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE (2) Internal expansion RAM The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. Table 3-7. Internal Expansion RAM Capacity 78K0/KB2 30/36 Pins PD78F0500, PD78F0500A 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Internal Expansion 38/44 Pins 48 Pins 52 Pins 64 Pins 80 Pins RAM - - - - - - PD78F0501, 78F0501A PD78F0511, 78F0511A PD78F0511, 78F0511A PD78F0521, 78F0521A PD78F0531, 78F0531A - PD78F0502, 78F0502A PD78F0512, 78F0512A PD78F0512, 78F0512A PD78F0522, 78F0522A PD78F0532, 78F0532A - PD78F0503D, PD78F0513D, 78F0513DA PD78F0513, 78F0513A PD78F0523, 78F0523A PD78F0533, 78F0533A - 78F0503DA PD78F0503, 78F0503A PD78F0513, 78F0513A PD78F0514, 78F0514A PD78F0524, 78F0524A PD78F0534, 78F0534A PD78F0544, 78F0544A 1024 x 8 bits PD78F0515D, 78F0515DA PD78F0525, PD78F0535, 78F0535A PD78F0545, 78F0545A 2048 x 8 bits 78F0525A PD78F0526, 78F0526A PD78F0536, 78F0536A PD78F0546, 78F0546A 4096 x 8 bits PD78F0527D, 78F0527DA PD78F0537D, 78F0537DA PD78F0547D, 78F0547DA 6144 x 8 bits PD78F0527, 78F0527A PD78F0537, 78F0537A PD78F0547, 78F0547A - - - - (F400H to F7FFH) (F000H to F7FFH) PD78F0515, 78F0515A - - - - - - (E800H to F7FFH) (E000H to F7FFH) (3) Buffer RAM (78K0/KF2 only) The 78K0/KF2 products incorporate 32 bytes (FA00H to FA1FH) of buffer RAM. The buffer RAM can be used for transfer in CSI with automatic transmit/receive function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 115 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see Table 38 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/Kx2 microcontrollers, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-12 to 3-19 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 116 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Correspondence Between Data Memory and Addressing (PD78F0500 and 78F0500A) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH FE20H FE1FH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits SFR addressing Register addressing Short direct addressing Internal high-speed RAM 512 x 8 bits FD00H FCFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 2000H 1FFFH Flash memory 8192 x 8 bits 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 117 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing (PD78F0501, 78F0501A, 78F0511, 78F0511A, 78F0521, 78F0521A, 78F0531, and 78F0531A) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 768 x 8 bits FE20H FE1FH FC00H FBFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 118 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Correspondence Between Data Memory and Addressing (PD78F0502, 78F0502A, 78F0512, 78F0512A, 78F0522, 78F0522A, 78F0532, and 78F0532A) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 6000H 5FFFH Flash memory 24576 x 8 bits 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 119 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Correspondence Between Data Memory and Addressing (PD78F0503, 78F0503A, 78F0513, 78F0513A, 78F0523, 78F0523A, 78F0533, 78F0533A, 78F0503D, 78F0503DA, 78F0513D, and 78F0513DA) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH Direct addressing FB00H FAFFH Register indirect addressing Based addressing Based indexed addressing Reserved 8000H 7FFFH Flash memory 32768 x 8 bits 0000H R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 120 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Correspondence Between Data Memory and Addressing (PD78F0514, 78F0514A, 78F0524, 78F0524A, 78F0534, 78F0534A, 78F0544, and 78F0544A) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bitsNote FA00H F9FFH F800H F7FFH Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH Reserved C000H BFFFH Flash memory 49152 x 8 bits 0000H Note The buffer RAM is incorporated only in the PD78F0544 and 78F0544A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0514, 78F0514A, 78F0524, 78F0524A, 78F0534, and 78F0534A. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 121 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Correspondence Between Data Memory and Addressing (PD78F0515, 78F0515A, 78F0525, 78F0525A, 78F0535, 78F0535A, 78F0545, 78F0545A, 78F0515D and 78F0515DA) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bitsNote FA00H F9FFH F800H F7FFH Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 2048 x 8 bits F000H EFFFH Flash memory 61440 x 8 bits 0000H Note The buffer RAM is incorporated only in the PD78F0545 and 78F0545A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0515, 78F0515A, 78F0525, 78F0525A, 78F0535, 78F0535A, 78F0515D, and 78F0515DA. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 122 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-18. Correspondence Between Data Memory and Addressing (PD78F0526, 78F0526A, 78F0536, 78F0536A, 78F0546, and 78F0546A) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bitsNote 1 FA00H F9FFH F800H F7FFH Direct addressing Register indirect addressing Reserved Based addressing Based indexed addressing Internal expansion RAM 4096 x 8 bits 16384 x 8 bits (memory bank 2)Note 2 E800H E7FFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0)Note 2 8000H 7FFFH Flash memory 32768 x 8 bits 16384 x 8 bits (memory bank 3)Note 2 16384 x 8 bits (memory bank 1)Note 2 0000H Notes 1. The buffer RAM is incorporated only in the PD78F0546 and 78F0546A (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0526, 78F0526A, 78F0536 and 78F0536A. 2. To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 123 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Correspondence Between Data Memory and Addressing (PD78F0527, 78F0527A, 78F0537, 78F0537A, 78F0547, 78F0547A, 78F0527D, 78F0527DA, 78F0537D, 78F0537DA, 78F0547D and 78F0547DA) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bitsNote 1 FA00H F9FFH F800H F7FFH Direct addressing Register indirect addressing Reserved Based addressing Based indexed addressing Internal expansion RAM 6144 x 8 bits 16384 x 8 bits (memory bank 4)Note 2 16384 x 8 bits (memory bank 2)Note 2 E000H DFFFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0)Note 2 8000H 7FFFH 16384 x 8 bits (memory bank 5)Note 2 Flash memory 32768 x 8 bits 16384 x 8 bits (memory bank 3)Note 2 16384 x 8 bits (memory bank 1)Note 2 0000H Notes 1. The buffer RAM is incorporated only in the PD78F0547, 78F0547A, 78F0547D and 78F0547DA (78K0/KF2). The area from FA00H to FA1FH cannot be used with the PD78F0527, 78F0527A, 78F0537, 78F0537A, 78F0527D, 78F0527DA, 78F0537D and 78F0537DA. 2. To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 124 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/Kx2 microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-20. Format of Program Counter 0 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon vectored interrupt request acknowledgement or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 3-21. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 0 ISP CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 125 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see 20.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-22. Format of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-23 and 3-24. Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 126 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-23. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP SP R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 127 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Figure 3-24. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP SP R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 128 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-25. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FEFFH H Register bank 0 HL L FEF8H D Register bank 1 DE E FEF0H B BC Register bank 2 C FEE8H A AX Register bank 3 X FEE0H 15 0 7 0 (b) Absolute name 16-bit processing 8-bit processing FEFFH R7 Register bank 0 RP3 R6 FEF8H R5 Register bank 1 RP2 R4 FEF0H R3 RP1 Register bank 2 R2 FEE8H R1 RP0 Register bank 3 R0 FEE0H 15 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0 7 0 129 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-8 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, SM+ for 78K0, and SM+ for 78K0/KX2, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 130 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (1/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits After Reset K B 2 K C 2 K D 2 K E 2 K F 2 FF00H Port register 0 P0 R/W - 00H FF01H Port register 1 P1 R/W - 00H FF02H Port register 2 P2 R/W - 00H FF03H Port register 3 P3 R/W - 00H FF04H Port register 4 P4 R/W - 00H - FF05H Port register 5 P5 R/W - 00H - - - FF06H Port register 6 P6 R/W - 00H FF07H Port register 7 P7 R/W - 00H - FF08H 10-bit A/D conversion result register ADCR R - - 0000H FF09H 8-bit A/D conversion result register ADCRH R - - 00H FF0AH Receive buffer register 6 RXB6 R - - FFH FF0BH Transmit buffer register 6 TXB6 R/W - - FFH FF0CH Port register 12 P12 R/W - 00H FF0DH Port register 13 P13 R/W - 00H - Note FF0EH Port register 14 P14 R/W - 00H - Note FF0FH Serial I/O shift register 10 SIO10 R - - 00H FF10H 16-bit timer counter 00 TM00 R - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H CR010 R/W - - 0000H FF15H 16-bit timer capture/compare register 010 FF16H 8-bit timer counter 50 TM50 R - - 00H FF17H 8-bit timer compare register 50 CR50 R/W - - 00H FF18H 8-bit timer H compare register 00 CMP00 R/W - - 00H FF19H 8-bit timer H compare register 10 CMP10 R/W - - 00H FF1AH 8-bit timer H compare register 01 CMP01 R/W - - 00H FF1BH 8-bit timer H compare register 11 CMP11 R/W - - 00H FF1FH 8-bit timer counter 51 TM51 R - - 00H FF20H Port mode register 0 PM0 R/W - FFH FF21H Port mode register 1 PM1 R/W - FFH FF22H Port mode register 2 PM2 R/W - FFH FF23H Port mode register 3 PM3 R/W - FFH FF24H Port mode register 4 PM4 R/W - FFH - FF25H Port mode register 5 PM5 R/W - FFH - - - FF26H Port mode register 6 PM6 R/W - FFH FF27H Port mode register 7 PM7 R/W - FFH - FF11H FF12H FF13H FF14H FF28H A/D converter mode register ADM R/W - 00H FF29H Analog input channel specification register ADS R/W - 00H FF2CH Port mode register 12 PM12 R/W - FFH FF2EH Port mode register 14 PM14 R/W - FFH - Note FF2FH A/D port configuration register ADPC R/W - 00H Note This register is incorporated only in 48-pin products. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 131 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (2/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After 1 Bit 8 Bits 16 Bits Reset K B 2 K C 2 K D 2 K E 2 K F 2 FF30H Pull-up resistor option register 0 PU0 R/W - 00H FF31H Pull-up resistor option register 1 PU1 R/W - 00H FF33H Pull-up resistor option register 3 PU3 R/W - 00H FF34H Pull-up resistor option register 4 PU4 R/W - 00H - FF35H Pull-up resistor option register 5 PU5 R/W - 00H - - - FF36H Pull-up resistor option register 6 PU6 R/W - 00H - - - - FF37H Pull-up resistor option register 7 PU7 R/W - 00H - FF3CH Pull-up resistor option register 12 PU12 R/W - 00H FF3EH Pull-up resistor option register 14 PU14 R/W - 00H - Note 1 FF40H Clock output selection register CKS R/W - 00H - Note 1 FF41H 8-bit timer compare register 51 CR51 R/W - - 00H FF43H 8-bit timer mode control register 51 TMC51 R/W - 00H FF48H External interrupt rising edge enable register EGP R/W - 00H FF49H External interrupt falling edge enable register EGN R/W - 00H FF4AH Serial I/O shift register 11 SIO11 R - - 00H - - - Note 2 FF4CH Transmit buffer register 11 SOTB11 R/W - - 00H - - - Note 2 FF4FH Input switch control register ISC R/W - 00H FF50H Asynchronous serial interface operation mode register 6 ASIM6 R/W - 01H FF53H Asynchronous serial interface reception error status register 6 ASIS6 R - - 00H FF55H Asynchronous serial interface transmission status register 6 ASIF6 R - - 00H FF56H Clock selection register 6 CKSR6 R/W - - 00H FF57H Baud rate generator control register 6 BRGC6 R/W - - FFH FF58H Asynchronous serial interface control register 6 ASICL6 R/W - 16H FF60H Remainder data register 0 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 00H - Note 2 Note 2 Note 2 - FF61H SDR0H - FF62H MDA0L MDA0LL R/W - FF63H MDA0LH - FF64H MDA0H MDA0HL R/W - Multiplication/division data register A0 FF65H FF66H SDR0 SDR0L R - R/W - MDA0HH Multiplication/division data register B0 MDB0 MDB0L - 00H - Note 2 Note 2 Note 2 FF68H Multiplier/divider control register 0 DMUC0 R/W - 00H - Note 2 Note 2 Note 2 FF69H 8-bit timer H mode register 0 TMHMD0 R/W - 00H FF67H MDB0H Notes 1. 2. This register is incorporated only in 48-pin products. This register is incorporated only in products whose flash memory is at least 48 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 132 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (3/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits After Reset K B 2 K C 2 K D 2 K E 2 K F 2 R/W - 00H TMC50 R/W - 00H TMHMD1 R/W - 00H TMCYC1 R/W - 00H KRM R/W - 00H - WTM R/W - 00H - ASIM0 R/W - 01H BRGC0 R/W - - 1FH FF6AH Timer clock selection register 50 TCL50 FF6BH 8-bit timer mode control register 50 FF6CH 8-bit timer H mode register 1 FF6DH 8-bit timer H carrier control register 1 FF6EH Key return mode register FF6FH Watch timer operation mode register FF70H Asynchronous serial interface operation mode register 0 FF71H Baud rate generator control register 0 FF72H Receive buffer register 0 RXB0 R - - FFH FF73H Asynchronous serial interface reception error status register 0 ASIS0 R - - 00H FF74H Transmit shift register 0 TXS0 W - - FFH FF80H Serial operation mode register 10 CSIM10 R/W - 00H FF81H Serial clock selection register 10 CSIC10 R/W - 00H FF84H Transmit buffer register 10 SOTB10 R/W - - 00H FF88H Serial operation mode register 11 CSIM11 R/W - 00H - - - Note FF89H Serial clock selection register 11 CSIC11 R/W - 00H - - - Note 1 1 FF8CH Timer clock selection register 51 TCL51 R/W - 00H FF90H Serial operation mode specification register 0 CSIMA0 R/W - 00H - - - - FF91H Serial status register 0 CSIS0 R/W - 00H - - - - FF92H Serial trigger register 0 CSIT0 R/W - 00H - - - - FF93H Division value selection register 0 BRGCA0 R/W - - 03H - - - - FF94H Automatic data transfer address point specification register 0 ADTP0 R/W - - 00H - - - - FF95H Automatic data transfer interval specification register 0 ADTI0 R/W - - 00H - - - - FF96H Serial I/O shift register 0 SIOA0 R/W - - 00H - - - - FF97H Automatic data transfer address count register 0 ADTC0 R - - 00H - - - - FF99H Watchdog timer enable register WDTE R/W - - 1AH/ Note 2 9AH FF9FH Clock operation mode select register OSCCTL R/W - 00H FFA0H Internal oscillation mode register RCM R/W - FFA1H Main clock mode register MCM R/W - 00H Note 3 80H FFA2H Main OSC control register MOC R/W - 80H FFA3H Oscillation stabilization time counter status register OSTC R - 00H FFA4H Oscillation stabilization time select register OSTS R/W - - 05H Notes 1. This register is incorporated only in products whose flash memory is at least 48 KB. 2. The reset value of WDTE is determined by setting of option byte. 3 The value of this register is 00H immediately after a reset release but automatically changes to 80H after oscillation accuracy stabilization of high-speed internal oscillator has been waited. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 133 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (4/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit After Reset 8 Bits 16 Bits K B 2 K C 2 K D 2 K E 2 K F 2 R/W - - 00H IICC0 R/W - 00H SVA0 R/W - - 00H IICCL0 R/W - 00H IIC function expansion register 0 IICX0 R/W - 00H IIC status register 0 IICS0 R - 00H IIC flag register 0 IICF0 R/W - Reset control flag register RESF R - - 00H 16-bit timer counter 01 TM01 R - - 0000H - - - Note FFA5H IIC shift register 0 FFA6H IIC control register 0 FFA7H Slave address register 0 FFA8H IIC clock selection register 0 FFA9H FFAAH FFABH FFACH FFB0H IIC0 00H Note 1 FFB1H 2 16-bit timer capture/compare register 001 CR001 CR011 FFB5H 16-bit timer capture/compare register 011 FFB6H 16-bit timer mode control register 01 TMC01 FFB2H FFB3H FFB4H R/W - - 0000H - - - Note 2 R/W - - 0000H - - - Note 2 R/W - 00H - - - Note 2 FFB7H Prescaler mode register 01 PRM01 R/W - 00H - - - Note 2 FFB8H Capture/compare control register 01 CRC01 R/W - 00H - - - Note 2 FFB9H 16-bit timer output control register 01 TOC01 R/W - 00H - - - Note 2 FFBAH 16-bit timer mode control register 00 TMC00 R/W - 00H FFBBH Prescaler mode register 00 PRM00 R/W - 00H FFBCH Capture/compare control register 00 CRC00 R/W - 00H FFBDH 16-bit timer output control register 00 TOC00 R/W - FFBEH Low-voltage detection register LVIM R/W - 00H FFBFH Low-voltage detection level selection register LVIS R/W - 00H FFE0H Interrupt request flag register 0L IF0 IF0L R/W FFE1H Interrupt request flag register 0H IF0H R/W FFE2H Interrupt request flag register 1L IF1L R/W FFE3H Interrupt request flag register 1H FFE4H Interrupt mask flag register 0L FFE5H Interrupt mask flag register 0H FFE6H Interrupt mask flag register 1L FFE7H Interrupt mask flag register 1H Notes 1. IF1 IF1H R/W MK0 MK0L R/W MK0H R/W MK1 MK1L R/W MK1H R/W Note 3 Note 3 00H 00H 00H 00H FFH FFH FFH FFH 00H The reset value of RESF varies depending on the reset source. 2. This register is incorporated only in products whose flash memory is at least 48 KB. 3. The reset values of LVIM and LVIS vary depending on the reset source. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 134 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE Table 3-8. Special Function Register List (5/5) Address Special Function Register (SFR) Name Symbol R/W 1 Bit K D 2 K E 2 K F 2 FFH FFH FFH FFH CFH R/W R/W PR1L R/W PR1H R/W IMS R/W - - Memory bank select register BANK R/W - - 00H - - Internal expansion RAM size switching Notes 3,4 register IXS R/W - - 0CH Note Note Note Note 2 2 2 2 Priority specification flag register 0H FFEAH Priority specification flag register 1L FFEBH Priority specification flag register 1H FFF0H Internal memory size switching Notes 3,4 register FFF3H FFF4H Processor clock control register PCC 4. K C 2 PR0L Priority specification flag register 0L FFE9H Notes 1. 2. 3. K B 2 PR0H FFE8H FFFBH After Reset 8 Bits 16 Bits Manipulatable Bit Unit PR0 PR1 R/W - 01H Note 1 Note 1 Note 1 This register is incorporated only in products whose flash memory is at least 96 KB. Set this register only in products with internal expansion RAM. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Kx2 microcontrollers are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated in Tables 3-1 and 3-2. The ROM and RAM capacities of the products with the on-chip debug function can be debugged by setting IMS and IXS, according to the debug target products. Set IMS and IXS according to the debug target products. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 135 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to PC and branched by the following addressing (for details of instructions, refer to the 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC indicates the start address of the instruction after the BR instruction. PC + 15 8 7 0 6 S jdisp8 15 0 PC When S = 0, all bits of are 0. When S = 1, all bits of are 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 136 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. However, before branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr. 15 8 7 0 PC In the case of CALLF !addr11 instruction 7 6 4 3 0 CALLF fa10-8 fa7-0 15 PC R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0 11 10 0 0 0 8 7 0 1 137 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address that is indicated by addr5 and is stored in the memory table from 0040H to 007FH, and allows branching to the entire memory space. [Illustration] 15 addr5 0 7 Operation code 1 6 0 0 6 5 0 1 0 0 0 7 0 0 0 8 7 6 0 0 1 1 0 ta4-0 0 1 0 ta4-0 0 1 15 Effective address 0 0 1 0 5 0 Memory (Table) 0 5 1 0 ... The value of the effective address is the same as that of addr5. 0 0 Low Addr. High Addr. Effective address+1 15 8 7 0 PC R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 138 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/Kx2 microcontroller instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets ROR4/ROL4 A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 139 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 140 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (lower) addr16 (upper) Memory R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 141 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See the [Illustration] shown below. [Operand format] Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] LB1 EQU 0FE30H ; Defines FE30H by LB1. : MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to that address Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 7 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 142 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name sfrp 16-bit manipulatable special function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 1 8 7 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 1 1 1 1 1 0 1 143 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier Description - [DE], [HL] [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 8 7 E D DE 0 7 Memory 0 The memory address specified with the register pair DE The contents of the memory addressed are transferred. 7 0 A R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 144 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - Description [HL + byte] [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 8 7 L H HL 0 7 Memory 0 +10 The contents of the memory addressed are transferred. 7 0 A R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 145 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - Description [HL + B], [HL + C] [Description example] MOV A, [HL +B]; when selecting B register Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 8 7 L H HL 0 + 7 0 B 7 Memory 0 The contents of the memory addressed are transferred. 7 0 A R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 146 78K0/Kx2 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] PUSH DE; when saving DE register Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP SP R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 FEE0H FEDEH Memory 0 FEE0H FEDFH D FEDEH E 147 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION CHAPTER 4 MEMORY BANK SELECT FUNCTION (PRODUCTS WHOSE FLASH MEMORY IS AT LEAST 96 KB ONLY) 4.1 Memory Bank The PD78F05x6, 78F05x6A, 78F05x7, 78F05x7A, 78F05x7D and 78F05x7DA of 78K0/KD2, 78K0/KE2, and 78K0/KF2 implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. The PD78F05x6 and 78F05x6A have memory banks 0 to 3, and the PD78F05x7, 78F05x7A, 78F05x7D and 78F05x7DA have memory banks 0 to 5, as shown below. The memory banks are selected by using a memory bank select register (BANK). Figure 4-1. Internal ROM (Flash Memory) Configuration (a) PD78F05x6 and 78F05x6A (products whose flash memory is 96 KB) (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H 7FFFH Common area Flash memory 32768 x 8 bits 0000H (b) PD78F05x7, 78F05x7A, 78F05x7D, and 78F05x7DA (products whose flash memory is 128 KB) (Memory bank 5) (Memory bank 4) (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H 7FFFH Common area Flash memory 32768 x 8 bits 0000H Remark x = 2 to 4 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 148 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.2 Difference in Representation of Memory Space With the 78K0/Kx2 microcontroller products which support the memory bank, addresses can be viewed in the following two different ways. * Memory bank number + CPU address * Flash memory real address (HEX FORMAT [BANK]) Figure 4-2. Address View (a) Memory bank number + CPU address (b) Flash memory real address (HEX FORMAT [BANK]) Memory bank 5 Memory bank 4 Memory bank 3 Memory bank 2 Memory bank 1 BFFFH Bank area Memory bank 0 (16 KB) 8000H 7FFFH Common area 1FFFFH 1C000H 1BFFFH 18000H 17FFFH 14000H 13FFFH 10000H 0FFFFH 0C000H 0BFFFH Common (32 KB) 08000H 07FFFH Memory bank 5 (16 KB) Memory bank 4 (16 KB) Memory bank 3 (16 KB) Memory bank 2 (16 KB) Memory bank 1 (16 KB) Memory bank 0 (16 KB) Common (32 KB) 00000H 0000H "Memory bank number + CPU address" is represented with a vacancy in the address space, while the flash memory real address is shown with no vacancy in the address space. "Memory bank number + CPU address" is used for addressing in the user program. For on-board programming and self programming not using the self programming sample libraryNote 1, the flash memory real address is used. Note that the HEX file that is output by the assembler (RA78K0) by default uses the flash memory real address. For address representation of the other tools such as the simulator and the debuggerNote 2, see Table 4-1. Notes 1. "Memory bank number + CPU address" can be used when performing self programming, using the self programming sample library, because the addresses are automatically translated. 2. SM+ for 78K0, SM+ for 78K0/Kx2, and ID78K0-QB R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 149 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address 08000H-0BFFFH Memory bank 0 Flash Memory Real Address Note 2 Address Representation in Note 1 Simulator and Debugger 08000H-0BFFFH 08000H-0BFFFH Memory bank 1 0C000H-0FFFFH 18000H-1BFFFH Memory bank 2 10000H-13FFFH 28000H-2BFFFH Memory bank 3 14000H-17FFFH 38000H-3BFFFH Memory bank 4 18000H-1BFFFH 48000H-4BFFFH Memory bank 5 1C000H-1FFFFH 58000H-5BFFFH Notes 1. SM+ for 78K0, SM+ for 78K0/Kx2, and ID78K0-QB 2. Set the memory bank to be used by the memory bank select register (BANK) (see Figure 4-3). For details, see the RA78K0 Ver. 3.80 Assembler Package Operation User's Manual (U17199E) and the 78K0 Microcontrollers Self Programming Library Type01 User's Manual (U18274E). 4.3 Memory Bank Select Register (BANK) The memory bank select register (BANK) is used to select a memory bank to be used. BANK can be set by an 8-bit memory manipulation instruction. Reset signal generation clears BANK to 00H. Figure 4-3. Format of Memory Bank Select Register (BANK) Address: FFF3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 BANK 0 0 0 0 0 BANK2 BANK1 BANK0 BANK2 BANK1 BANK0 Bank setting PD78F05x6 and 78F05x6A PD78F05x7, 78F05x7A, 78F05x7D, and 78F05x7DA 0 0 0 Common area (32 KB) + memory bank 0 (16 KB) 0 0 1 Common area (32 KB) + memory bank 1 (16 KB) 0 1 0 Common area (32 KB) + memory bank 2 (16 KB) 0 1 1 Common area (32 KB) + memory bank 3 (16 KB) 1 0 0 Setting prohibited Common area (32 KB) + memory bank 4 (16 KB) 1 0 1 Common area (32 KB) + memory bank 5 (16 KB) Other than above Caution Setting prohibited Be sure to change the value of the BANK register in the common area (0000H to 7FFFH). If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never change the value of the BANK register in the bank area. Remark x = 2 to 4 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 150 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register. The value of the BANK register must not be changed in the bank area (8000H to BFFFH). Therefore, to change the memory bank, branch an instruction to the common area (0000H to 7FFFH) and change the value of the BANK register in that area. Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branching and accessing cannot be directly executed between different memory banks. Execute branching or accessing between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. 4.4.1 Referencing values between memory banks Values cannot be directly referenced from one memory bank to another. To access another memory bank from one memory bank, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then reference a value. Memory bank n Bank area Memory bank m Referencing value Common area Memory bank n Bank area Common area R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Memory bank m Referencing value 151 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION * Software example (to store a value to be referenced in register A) RAMD R_BNKA: R_BNKN: R_BNKRN: DSEG DS DS DS SADDR 2 1 1 ETRC ENTRY: CSEG UNIT MOV MOVW CALL R_BNKN,#BANKNUM R_BNKA,#DATA1 !BNKRD : : CSEG AT PUSH MOV XCH HL A,R_BNKN A,BANK MOV XCHW MOVW XCHW MOV XCH MOV MOV POP R_BNKRN,A AX,HL AX,R_BNKA AX,HL A,[HL] A,R_BNKRN BANK,A A,R_BNKRN HL BNKC ; Secures RAM for specifying an address at the reference destination. ; Secures RAM for specifying a memory bank number at the reference destination. ; Secures RAM for saving a memory bank number at the reference source. DATA DATA1: CSEG DB ; Stores the memory bank number at the reference destination. ; Stores the address at the reference destination. ; Calls a subroutine for referencing between memory banks. 7000H BNKRD: RET DATA1 ; Subroutine for referencing between memory banks. ; Saves the contents of the HL register. ; Acquires the memory bank number at the reference destination. ; Swaps the memory bank number at the reference source for that at the reference ; destination ; Saves the memory bank number at the reference source. ; Saves the contents of the X register. ; Acquires the address at the reference destination. ; Specifies the address at the reference destination. ; Reads the target value. ; Acquires the memory bank number at the reference source. ; Specifies the memory bank number at the reference source. ; Write the target value to the A register. ; Restores the contents of the HL register. ; Return BANK3 0AAH END R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 152 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again. Memory bank n Bank area Memory bank m Instruction branch Common area Memory bank n Bank area Memory bank m Instruction branch Common area R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 153 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION * Software example 1 (to branch from all areas) RAMD R_BNKA: R_BNKN: RSAVEAX: DSEG DS DS DS SADDR 2 1 2 ETRC ENTRY: CSEG UNIT MOV MOVW BR : : R_BNKN,#BANKNUM R_BNKA,#TEST !BNKBR CSEG AT MOVW MOV MOV MOVW PUSH MOVW RET RSAVEAX,AX A,R_BNKN BANK,A AX,R_BNKA AX RSAVEAX,AX CSEG BANK3 BNKC BNKBR: BN3 TEST: ; Secures RAM for specifying a memory bank at the branch destination. ; Secures RAM for specifying a memory bank number at the branch destination. ; Secures RAM for saving the AX register. TEST ; Stores the memory bank number at the branch destination in RAM. ; Stores the address at the branch destination in RAM. ; Branches to inter-memory bank branch processing. 7000H ; Saves the AX register. ; Acquires the memory bank number at the branch destination. ; Specifies the memory bank number at the branch destination. ; Specifies the address at the branch destination. ; Sets the address at the branch destination to stack. ; Restores the AX register. ; Branch MOV : : END * Software example 2 (to branch from common area to any bank area) ETRC ENTRY: BN3 TEST: CSEG AT 2000H MOV BR R_BNKN,#BANKNUM TEST !TEST CSEG BANK3 ; Stores the memory bank number at the branch destination in RAM. ; Stores the address at the branch destination in RAM. MOV : : END R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 154 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction. At this time, save the current value of the BANK register to RAM. Restore the value of the BANK register before executing the RET instruction. Memory bank n Bank area Memory bank m CALL instruction Common area Memory bank n Bank area Common area Memory bank m CALL instruction RET instruction BR instruction CALL instruction RET instruction Change BANK and save memory bank number at calling source. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 155 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION * Software example RAMD R_BNKA: R_BNKN: R_BNKRN: RSAVEAX: DSEG DS DS DS DS SADDR 2 1 1 2 ETRC ENTRY: CSEG UNIT MOV MOVW CALL R_BNKN,#BANKNUM R_BNKA,#TEST !BNKCAL : : CSEG AT MOVW MOV XCH MOV CALL RSAVEAX,AX A,R_BNKN A,BANK R_BNKRN,A !BNKCALS MOVW XCH MOV MOVW RET RSAVEAX,AX A,R_BNKRN BANK,A AX,RSAVEAX ; Saves the AX register. ; Acquires the memory bank number at the calling source. ; Specifies the memory bank number at the calling source. ; Restores the AX register. ; Returns to the calling source. MOVW PUSH MOVW RET AX,R_BNKA AX AX,RSAVEAX ; Specifies the address at the calling destination. ; Sets the address at the calling destination to stack. ; Restores source AX register. ; Branches to the calling destination. CSEG BANK3 BNKC BNKCAL: ; Secures RAM for specifying an address at the calling destination. ; Secures RAM for specifying a memory bank number at the calling destination. ; Secures RAM for saving a memory bank number at the calling source. ; Secures RAM for saving the AX register. TEST ; Store the memory bank number at the calling destination in RAM. ; Stores the address at the calling destination in RAM. ; Branches to an inter-memory bank calling processing routine. 7000H ; Inter-memory bank calling processing routine ; Saves the AX register. ; Acquires the memory bank number at the calling destination. ; Changes the bank and acquires the memory bank number at the calling source. ; Saves the memory bank number at the calling source to RAM. ; Calls a subroutine to branch to the calling destination. BNKCALS: BN3 TEST: ; MOV : : RET END Remark In the software example above, multiplexed processing is not supported. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 156 78K0/Kx2 CHAPTER 4 MEMORY BANK SELECT FUNCTION 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs. Therefore, specify the branch destination address specified by the vector table in the common area (0000H to 7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and execute the CALL instruction. At this time, save the BANK register value before the change to RAM, and restore the value of the BANK register before executing the RETI instruction. Remark Allocate interrupt servicing that requires a quick response in the common area. Memory bank n Instruction branch Bank area Memory bank m Common area Vector table Save the original memory bank number. Specify the address and memory bank at the destination, and execute the call instruction. * Software example (when using interrupt request of 16-bit timer/event counter 00) VCTBL CSEG DW AT 0020H BNKITM000 ; Specifies an address at the timer interrupt destination. RAMD DSEG R_BNKRN: DS SADDR 1 ; Secures RAM for saving the memory bank number before the interrupt occurs. BNKC CSEG AT BNKITM000: PUSH AX 7000H ; Inter-memory bank interrupt servicing routine ; Saves the contents of the AX register. MOV MOV MOV CALL MOV MOV A,BANK R_BNKRN,A BANK,#BANKNUM TEST !TEST A,R_BNKRN BANK,A ; Saves the memory bank number before the interrupt to RAM. ; Specifies the memory bank number of the interrupt routine. ; Calls the interrupt routine. ; Restores the memory bank number before the interrupt. POP AX ; Restores the contents of the AX register. RETI BN3 TEST: CSEG BANK3 ; Interrupt servicing routine MOV : : RET END R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 157 78K0/Kx2 Remark CHAPTER 4 MEMORY BANK SELECT FUNCTION Note the following points to use the memory bank select function efficiently. * Allocate a routine that is used often in the common area. * If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. * If the reference destination and the branch destination of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. * Allocate interrupt servicing that requires a quick response in the common area. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 158 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 5-1. Pin I/O Buffer Power Supplies (AVREF, VDD) * 78K0/KB2: 30-pin plastic SSOP (7.62 mm (300)) * 78K0/KC2: 38-pin plastic SSOP (7.62 mm (300)), 44-pin plastic LQFP (10x10), 48-pin plastic LQFP (fine pitch) (7x7) * 78K0/KD2: 52-pin plastic LQFP (10x10) Power Supply Corresponding Pins AVREF P20 to P27 VDD Pins other than P20 to P27 Table 5-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD) * 78K0/KB2: 36-pin plastic FLGA (4x4) * 78K0/KE2: 64-pin plastic LQFP (fine pitch) (10x10), 64-pin plastic LQFP (14x14), 64-pin plastic LQFP (12x12), 64pin plastic TQFP (fine pitch) (7x7), 64-pin plastic FLGA (5x5) , 64-pin plastic FBGA (4x4) * 78K0/KF2: 80-pin plastic LQFP (14x14), 80-pin plastic LQFP (fine pitch) (12x12) Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 and P121 to P124 VDD * P121 to P124 * Non-port pins 78K0/Kx2 microcontrollers are provided with digital I/O ports, which enable variety of control operations. The functions of each port are shown in Table 5-3. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 159 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Functions (1/3) KB2 KC2 KD2 KES KF2 Function I/O Function Name P00 I/O P01 After Alternate Reset Function Port 0. Input TI000 I/O port. port TI010/TO00 Input/output can be specified in 1-bit units. - - Note 1 Note 2 P02 - - Note 1 Note 2 P03 - - - Note 2 P04 SCK11 - - - Note 2 P05 TI001/SSI11 - - - Note 2 P06 TI011/TO01 P10 P11 SO11 Use of an on-chip pull-up resistor can be specified by SI11 a software setting. I/O Port 1. Input SCK10/TxD0 I/O port. port SI10/RxD0 Input/output can be specified in 1-bit units. P12 P13 P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 P21 SO10 Use of an on-chip pull-up resistor can be specified by TxD6 a software setting. I/O Port 2. Analog ANI0 I/O port. input ANI1 Input/output can be specified in 1-bit units. P22 P23 ANI3 - P24 ANI4 - P25 ANI5 - Note 3 P26 ANI6 - Note 3 P27 ANI7 P30 P31 I/O Port 3. Analog INTP1 I/O port. input INTP2/ Input/output can be specified in 1-bit units. P32 ANI2 Use of an on-chip pull-up resistor can be specified by a software setting. P33 OCD1A Note 4 INTP3/ OCD1B Note 4 TI51/TO51/ INTP4 Notes 1. 2. The 78K0/KD2 products are only provided with port functions (P02 and P03) and not alternate functions. The 78K0/KE2 products whose flash memory is less than 32 KB are only provided with port functions (P02 to P06) and not alternate functions. The 78K0/KE2 products whose flash memory is at least 48 KB are provided with port functions (P02 to P06) and alternate functions. 3. This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 6 and 7 of PM2 to "1" and bits 6 and 7 of P2 to "0". 4. OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 160 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Functions (2/3) KB2 KC2 KD2 KES KF2 Function I/O Function Name - - Note 1 Note 1 P40 I/O P41 After Alternate Reset Function Port 4. Input - I/O port. port - Input/output can be specified in 1-bit units. - - - P42 - - - P43 - - - - P44 - - - - - P45 - - - - - P46 - - - - - P47 - - - P50 - - - - Use of an on-chip pull-up resistor can be specified by - a software setting. - I/O P51 Port 5. Input - I/O port. port - Input/output can be specified in 1-bit units. - - - P52 - - - P53 - - - - P54 - - - - - P55 - - - - - P56 - - - - - P57 P60 P61 - Use of an on-chip pull-up resistor can be specified by - a software setting. - I/O Port 6. Input SCL0 I/O port. port SDA0 Output of P60 to P63 is N-ch open-drain output - P62 - P63 Input/output can be specified in 1-bit units. - - - - - P64 Only for P64 to P67, use of an on-chip resistor can - be specified by a software setting. - - - - - P65 - - - - P66 - - - - P67 - P70 - P71 EXSCL0 (6 V tolerance). - - I/O Port 7. Input KR0 I/O port. port KR1 Input/output can be specified in 1-bit units. - Note 1 P72 - Note 1 P73 - Note 2 P74 KR4 - Note 2 P75 KR5 - - P76 KR6 - - P77 KR7 Use of an on-chip pull-up resistor can be specified by a software setting. KR2 KR3 Notes 1. This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 0 2. This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only and 1 of PM4, bits 2 and 3 of PM7, bits 0 and 1 of P4, and bits 2 and 3 of P7 to "0". provided with port functions (P74 to P75) and not alternate functions. Remark : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 161 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Functions (3/3) KB2 KC2 KD2 KES KF2 Function I/O Function Name P120 I/O P121 After Alternate Reset Function Port 12. Input INTP0/EXLVI I/O port. port X1/OCD0A Input/output can be specified in 1-bit units. P122 Note 3 X2/EXCLK/ Only for P120, use of an on-chip pull-up resistor can OCD0B be specified by a software setting. Note 3 - P123 XT1 - P124 XT2/EXCLKS - Note 1 P130 - Note 1 - - - Note 2 P140 Output I/O P141 - Port 13. Output Output-only port. port Port 14. Input PCL/INTP6 I/O port. port BUZ/BUSY0/ Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by INTP7 - - - - P142 - - - - P143 SIA0 - - - - P144 SOA0 - - - - P145 STB0 Notes 1. a software setting. SCKA0 This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. 2. The 78K0/KE2 products are not provided with the BUSY0 input function. 3. OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted, -: Not mounted R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 162 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration Ports include the following hardware. Table 5-4. Port Configuration Item Control registers Configuration * 78K0/KB2 Port mode register (PMxx): PM0 to PM3, PM6, PM12 Port register (Pxx): P0 to P3, P6, P12 Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU12 A/D port configuration register (ADPC) * 38-pin and 44-pin products of 78K0/KC2 Port mode register (PMxx): PM0 to PM4, PM6, PM7, PM12 Port register (Pxx): P0 to P4, P6, P7, P12 Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU4, PU7, PU12 A/D port configuration register (ADPC) * 48-pin products of 78K0/KC2, 78K0/KD2 Port mode register (PMxx): PM0 to PM4, PM6, PM7, PM12, PM14 Port register (Pxx): P0 to P4, P6, P7, P12 to P14 Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU4, PU7, PU12, PU14 A/D port configuration register (ADPC) * 78K0/KE2 Port mode register (PMxx): PM0 to PM7, PM12, PM14 Port register (Pxx): P0 to P7, P12 to P14 Pull-up resistor option register (PUxx): PU0, PU1, PU3 to PU5, PU7, PU12, PU14 A/D port configuration register (ADPC) * 78K0/KF2 Port mode register (PMxx): PM0 to PM7, PM12, PM14 Port register (Pxx): P0 to P7, P12 to P14 Pull-up resistor option register (PUxx): PU0, PU1, PU3 to PU7, PU12, PU14 A/D port configuration register (ADPC) Port * 78K0/KB2: Total: 23 (CMOS I/O: 21, N-ch open drain I/O: 2) * 38-pin products of 78K0/KC2: Total: 31 (CMOS I/O: 27, N-ch open drain I/O: 4) * 44-pin products of 78K0/KC2: Total: 37 (CMOS I/O: 33, N-ch open drain I/O: 4) * 48-pin products of 78K0/KC2: Total: 41 (CMOS I/O: 36, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor * 78K0/KD2: Total: 45 (CMOS I/O: 40, CMOS output: 1, N-ch open drain I/O: 4) * 78K0/KE2: Total: 55 (CMOS I/O: 50, CMOS output: 1, N-ch open drain I/O: 4) * 78K0/KF2: Total: 71 (CMOS I/O: 66, CMOS output: 1, N-ch open drain I/O: 4) * 78K0/KB2: Total: 15 * 38-pin products of 78K0/KC2: Total: 17 * 44-pin products of 78K0/KC2: Total: 21 * 48-pin products of 78K0/KC2: Total: 24 * 78K0/KD2: Total: 28 * 78K0/KE2: Total: 38 * 78K0/KF2: Total: 54 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 163 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 78K0/KB2 78K0/KC2 78K0/KD2 P00/TI000 P01/TI010/TO00 P02/SO11 - P03/SI11 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P02 Note - P03 Note P04/SCK11 - - P05/TI001/SSI11 - - P06/TI011/TO01 - - P02 Note P03 Note Note Note Note P04 P05 P06 Note The 78K0/KE2 products whose flash memory is less than 32 KB and 78K0/KD2 products are only provided with port functions and not alternate functions. Remark : Mounted, -: Not mounted Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O, serial interface data I/O, clock I/O, and chip select input. Reset signal generation sets port 0 to input mode. Figures 5-1 to 5-6 show block diagrams of port 0. Caution To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 164 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-1. Block Diagram of P00 EVDD WRPU PU0 PU00 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00) P00/TI000 WRPM PM0 PM00 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 165 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-2. Block Diagram of P01 EVDD WRPU PU0 PU01 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P01) P01/TI010/TO00 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 166 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P02 (1/2) (1) 78K0/KE2 products whose flash memory is less than 32 KB and 78K0/KD2 EVDD WRPU PU0 PU02 P-ch Internal bus Selector RD WRPORT P0 Output latch (P02) P02 WRPM PM0 PM02 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 167 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P02 (2/2) (2) 78K0/KE2 products whose flash memory is at least 48 KB and 78K0/KF2 EVDD WRPU PU0 PU02 P-ch Internal bus Selector RD WRPORT P0 Output latch (P02) P02/SO11 WRPM PM0 PM02 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 168 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P03 and P05 (1/2) (1) 78K0/KE2 products whose flash memory is less than 32 KB and 78K0/KD2 EVDD WRPU PU0 PU03, PU05 P-ch Internal bus Selector RD WRPORT P0 Output latch (P03, P05) P03, P05 WRPM PM0 PM03, PM05 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remarks 1. 78K0/KD2: P03 (not mounted with P05) 78K0/KE2 products whose flash memory is less than 32 KB: P03 and P05 2. With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 169 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P03 and P05 (2/2) (2) 78K0/KE2 products whose flash memory is at least 48 KB and 78K0/KF2 EVDD WRPU PU0 PU03, PU05 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P03, P05) P03/SI11, P05/SSI11/TI001 WRPM PM0 PM03, PM05 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 170 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P04 (1/2) (1) 78K0/KE2 products whose flash memory is less than 32 KB EVDD WRPU PU0 PU04 P-ch Selector Internal bus RD WRPORT P0 Output latch (P04) P04 WRPM PM0 PM04 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 171 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P04 (2/2) (2) 78K0/KE2 products whose flash memory is at least 48 KB and 78K0/KF2 EVDD WRPU PU0 PU04 P-ch Alternate function Internal bus Selector RD WRPORT P0 Output latch (P04) P04/SCK11 WRPM PM0 PM04 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 172 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P06 (1/2) (1) 78K0/KE2 products whose flash memory is less than 32 KB EVDD WRPU PU0 PU06 P-ch Internal bus Selector RD WRPORT P0 Output latch (P06) P06 WRPM PM0 PM06 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 173 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P06 (2/2) (2) 78K0/KE2 products whose flash memory is at least 48 KB and 78K0/KF2 EVDD WRPU PU0 PU06 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P06) P06/TI011/TO01 WRPM PM0 PM06 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 174 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Remark : Mounted Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. Reset signal generation sets port 1 to input mode. Figures 5-7 to 5-11 show block diagrams of port 1. Cautions 1. To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H). 2. To use P13/TxD6 as general-purpose port, clear bit 0 (TXDLV6) of asynchronous serial interface control register 6 (ASICL6) to 0 (normal output of TxD6). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 175 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P10 EVDD WRPU PU1 PU10 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P10) P10/SCK10/TxD0 WRPM PM1 PM10 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 176 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-8. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P11, P14) P11/SI10/RxD0, P14/RxD6 WRPM PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 177 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P12 and P15 EVDD WRPU PU1 PU12, PU15 P-ch Internal bus Selector RD WRPORT P1 Output latch (P12, P15) WRPM P12/SO10 P15/TOH0 PM1 PM12, PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 178 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P13 EVDD WRPU PU1 PU13 P-ch Selector Internal bus RD WRPORT P1 Output latch (P13) P13/TxD6 WRPM PM1 PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 179 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-11. Block Diagram of P16 and P17 EVDD WRPU PU1 PU16, PU17 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P16, P17) P16/TOH1/INTP5, P17/TI50/TO50 WRPM PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 180 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 - P25/ANI5 - P26/ANI6 - P27/ANI7 - Note Note Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". Remark : Mounted, -: Not mounted Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit. To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using ADPC and in the output mode by using PM2. Table 5-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins ADPC Digital I/O selection Analog input selection PM2 ADS P20/ANI0 to P27/ANI7 Pin Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated. Figure 5-12 shows a block diagram of port 2. Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 181 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P20 to P27 Internal bus Selector RD WRPORT P2 Output latch (P20 to P27) P20/ANI0 to P27/ANI7 WRPM PM2 PM20 to PM27 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal Caution For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 182 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 P30/INTP1 P31/INTP2/ OCD1A Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Note P32/INTP3/ OCD1B 78K0/KF2 Note P33/INTP4/TI51/ TO51 Note OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input and timer I/O. Reset signal generation sets port 3 to input mode. Figures 5-13 and 5-14 show block diagrams of port 3. Cautions 1. In the product with an on-chip debug function (P78F05xxD and D78F05xxDA), be sure to pull the P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction. 2. Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. P31/INTP2/OCD1A Flash memory programmer connection On-chip debug During reset emulator connection During reset released (when it is not used as an on-chip debug Note Connect to EVSS Input: via a resistor. Connect to EVDD Note Note or EVSS via a resistor. Output: Leave open. mode setting pin) Note With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect them to VDD. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 183 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Remark P31 and P32 of the product with an on-chip debug function (PD78F05xxD and 78F05xxDA) can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD AND 78F05xxDA ONLY). Figure 5-13. Block Diagram of P30 to P32 EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P30 to P32) WRPM P30/INTP1, P31/INTP2/OCD1A, P32/INTP3/OCD1B PM3 PM30 to PM32 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 184 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P33) P33/INTP4/TI51/TO51 WRPM PM3 PM33 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 185 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P40 - P41 - P42 - - P43 - - P44 - - - P45 - - - P46 - - - P47 - - - Note Note Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 0 and 1 of PM4 and P4 to "0". Remark : Mounted, -: Not mounted Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to input mode. Figure 5-15 shows a block diagram of port 4. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 186 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block Diagram of P40 to P47 EVDD WRPU PU4 PU40 to PU47 P-ch Internal bus RD Selector WRPORT P4 Output latch (P40 to P47) WRPM P40 to P47 PM4 PM40 to PM47 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal Caution For the 38-pin products of 78K0/KC2, be sure to set bits 0 and 1 of PM4 and P4 to "0". Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 187 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P50 - P51 - P52 - P53 - P54 - - P55 - - P56 - - P57 - - Remark : Mounted, -: Not mounted Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Reset signal generation sets port 5 to input mode. Figure 5-16 shows a block diagram of port 5. Figure 5-16. Block Diagram of P50 to P57 EVDD WRPU PU5 PU50 to PU57 P-ch RD Internal bus Selector WRPORT P5 Output latch (P50 to P57) WRPM P50 to P57 PM5 PM50 to PM57 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 188 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P60/SCL0 P61/SDA0 P62/EXSCL0 - P63 - P64 - - P65 - - P66 - - P67 - - Remark : Mounted, -: Not mounted Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O, clock I/O, and external clock input. Reset signal generation sets port 6 to input mode. Figures 5-17 to 5-20 show block diagrams of port 6. Remark When using P62/EXSCL0 as an external clock input pin of the serial interface, input a clock of 6.4 MHz to it. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 189 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-17. Block Diagram of P60 and P61 Alternate function Selector RD Internal bus WRPORT P6 Output latch (P60, P61) P60/SCL0, P61/SDA0 WRPM PM6 PM60, PM61 Alternate function P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Caution A through current flows through P60 and P61 if an intermediate potential is input to these pins, because the input buffer is also turned on when P60 and P61 are in output mode. Consequently, do not input an intermediate potential when P60 and P61 are in output mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 190 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-18. Block Diagram of P62 Alternate function Internal bus Selector RD WRPORT P6 Output latch (P62) P62/EXSCL0 WRPM PM6 PM62 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Caution A through current flows through P62 if an intermediate potential is input to this pin, because the input buffer is also turned on when P62 is in output mode. Consequently, do not input an intermediate potential when P62 is in output mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 191 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P63 Selector Internal bus RD WRPORT P6 Output latch (P63) P63 WRPM PM6 PM63 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 192 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-20. Block Diagram of P64 to P67 EVDD WRPU PU6 PU64 to PU67 P-ch Selector Internal bus RD WRPORT P6 Output latch (P64 to P67) P64 to P67 WRPM PM6 PM64 to PM67 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 193 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 7 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P70/KR0 - P71/KR1 - P72/KR2 - P73/KR3 - P74/KR4 - P75/KR5 - P76/KR6 - - P77/KR7 - - Notes 1. 78K0/KF2 Note 1 Note 1 P74 Note 2 P75 Note 2 This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 2 and 3 of PM7 and P7 to "0". 2. This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only provided with port functions and not alternate functions. Remark : Mounted, -: Not mounted Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). This port can also be used for key return input. Reset signal generation sets port 7 to input mode. Figure 5-21 shows a block diagram of port 7. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 194 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-21. Block Diagram of P70 to P77 EVDD WRPU PU7 PU70 to PU77 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P70 to P77) P70/KR0 to P77/KR7 WRPM PM7 PM70 to PM77 P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal Caution For the 38-pin products of 78K0/KC2, be sure to set bits 2 and 3 of PM7 and P7 to "0". Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 195 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 12 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P120/INTP0/EXLVI Note P123/XT1 - P124/XT2/EXCLKS - P121/X1/OCD0A P122/X2/EXCLK/ OCD0B 78K0/KF2 Note Note OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxD and 78F05xxDA) only. Remark : Mounted, -: Not mounted Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Reset signal generation sets port 12 to input mode. Figures 5-22 and 5-23 show block diagrams of port 12. Caution 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 196 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Caution 2. Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator. P121/X1/OCD0A Flash memory programmer connection On-chip debug During reset emulator connection During reset released (when it is not used Connect to VSS via a resistor. Input: Connect to VDD or VSS via a resistor. as an on-chip debug Output: Leave open. mode setting pin) X1 and X2 of the product with an on-chip debug function (PD78F05xxD and 78F05xxDA) can be used as Remark on-chip debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD AND 78F05xxDA ONLY). Figure 5-22. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function Selector Internal bus RD WRPORT P12 Output latch (P120) P120/INTP0/EXLVI WRPM PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 197 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-23. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS Selector RD WRPORT P12 Output latch (P122/P124) P122/X2/EXCLK/OCD0B, P124/XT2/EXCLKS WRPM PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS Internal bus OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS Selector RD WRPORT P12 Output latch (P121/P123) WRPM P121/X1/OCD0A, P123/XT1 PM12 PM121/PM123 OSCCTL OSCSEL/ OSCSELS P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 OSCCTL: Clock operation mode select register RD: Read signal WRxx: Write signal R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 198 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 13 78K0/KB2 78K0/KC2 - P130 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Note Note This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. Remark : Mounted, -: Not mounted Port 13 is an output-only port. Figure 5-24 shows a block diagram of port 13. Figure 5-24. Block Diagram of P130 Internal bus RD WRPORT P13 Output latch (P130) P13: Port register 13 RD: Read signal P130 WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 199 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 14 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB P140/PCL/INTP6 - P141/BUZ/BUSY0/ - - - P142/SCKA0 - - - - P143/SIA0 - - - - P144/SOA0 - - - - P145/STB0 - - - - Note 1 P141/BUZ/INTP7 Note 2 INTP7 Notes 1. 2. This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 78K0/KE2 products are not provided with the BUSY0 input function. Remark : Mounted, -: Not mounted Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input, buzzer output, clock output, serial interface data I/O, clock I/O, busy input, and strobe output. Reset signal generation sets port 14 to input mode. Figures 5-25 to 5-28 shows a block diagram of port 14. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 200 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-25. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P140, P141) P140/PCL/INTP6, P141/BUZ/BUSY0/INTP7 WRPM PM14 PM140, PM141 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 201 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-26. Block Diagram of P142 EVDD WRPU PU14 PU142 P-ch Alternate function Internal bus Selector RD WRPORT P14 Output latch (P142) P142/SCKA0 WRPM PM14 PM142 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 202 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-27. Block Diagram of P143 EVDD WRPU PU14 PU143 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P143) P143/SIA0 WRPM PM14 PM143 P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 203 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-28. Block Diagram of P144 and P145 EVDD WRPU PU14 PU144, PU145 P-ch Internal bus Selector RD WRPORT P14 Output latch (P144, P145) WRPM P144/SOA0, P145/STB0 PM14 PM144, PM145 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal Remark With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. 5.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. * Port mode registers (PMxx) * Port registers (Pxx) * Pull-up resistor option registers (PUxx) * A/D port configuration register (ADPC) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 204 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function. Figure 5-29. Format of Port Mode Register (78K0/KB2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 1 1 1 1 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W PM12 1 1 1 1 1 PM122 PM121 PM120 FF2CH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 3, 6, 12; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of PM6, bits 3 to 7 of PM12 to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 205 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-30. Format of Port Mode Register (78K0/KC2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 1 1 1 1 1 1 PM41 PM40 FF24H FFH R/W PM6 1 1 1 1 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 1 1 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14Note 1 1 1 1 1 1 1 PM140Note FF2EH FFH R/W PM75Note PM74Note Pmn pin I/O mode selection PMmn (m = 0 to 4, 6, 7, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Note 48-pin products only Caution For the 38-pin products, be sure to set bits 2 to 7 of PM0, bits 6 and 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to "1". Also, be sure to set bits 0 and 1 of PM4, and bits 2 and 3 of PM7 to "0". For the 44-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to "1". For the 48-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 6 and 7 of PM7, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to "1". R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 206 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-31. Format of Port Mode Register (78K0/KD2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 1 1 1 1 1 1 PM41 PM40 FF24H FFH R/W PM6 1 1 1 1 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14 1 1 1 1 1 1 1 PM140 FF2EH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 4, 6, 7, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution Be sure to set bits 4 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 207 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-32. Format of Port Mode Register (78K0/KE2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W PM6 1 1 1 1 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14 1 1 1 1 1 1 PM141 PM140 FF2EH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 7, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of PM5, bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to "1". R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 208 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-33. Format of Port Mode Register (78K0/KF2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R/W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 FF2EH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 7, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and 7 of PM14 to "1". R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 209 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-34. Format of Port Register (78K0/KB2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 0 0 0 0 0 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 0 0 0 0 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P6 0 0 0 0 0 0 P61 P60 FF06H 00H (output latch) R/W P12 0 0 0 0 0 P120 FF0CH 00H (output latch) R/W P122 Note P121Note m = 0 to 3, 6, 12; n = 0 to 7 Pmn Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note "0" is always read from the output latch of P121 and P122 if the pin is in the external clock input mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 210 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-35. Format of Port Register (78K0/KC2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 0 0 0 0 0 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 0 0 0 0 0 0 P41 P40 FF04H 00H (output latch) R/W P6 0 0 0 0 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 0 0 P75Note 1 P74Note 1 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P120 FF0CH 00H (output latch) R/W P13Note 1 0 0 0 0 0 0 0 P130Note 1 FF0DH 00H (output latch) R/W P14Note 1 0 0 0 0 0 0 0 P140Note 1 FF0EH 00H (output latch) R/W P124Note 2 P123Note 2 P122Note 2 P121Note 2 m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7 Pmn Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Notes 1. 2. 48-pin products only "0" is always read from the output latch of P121 to P124 if the pin is in the external clock input mode. Caution For the 38-pin products, be sure to set bits 6 and 7 of P2, bits 0 and 1 of P4, and bits 2 and 3 of P7 to "0". R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 211 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-36. Format of Port Register (78K0/KD2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 0 0 0 P03 P02 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 0 0 0 0 0 0 P41 P40 FF04H 00H (output latch) R/W P6 0 0 0 0 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P120 FF0CH 00H (output latch) R/W P13 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W P14 0 0 0 0 0 0 0 P140 FF0EH 00H (output latch) R/W P124Note P123Note P122Note P121Note m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7 Pmn Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note "0" is always read from the output latch of P121 to P124 if the pin is in the external clock input mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 212 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-37. Format of Port Register (78K0/KE2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 P06 P05 P04 P03 P02 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 0 0 0 0 P43 P42 P41 P40 FF04H 00H (output latch) R/W P5 0 0 0 0 P53 P52 P51 P50 FF05H 00H (output latch) R/W P6 0 0 0 0 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P120 FF0CH 00H (output latch) R/W P13 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W P14 0 0 0 0 0 0 P141 P140 FF0EH 00H (output latch) R/W Pmn P124Note P123Note P122Note P121Note m = 0 to 7, 12 to 14; n = 0 to 7 Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note "0" is always read from the output latch of P121 to P124 if the pin is in the external clock input mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 213 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-38. Format of Port Register (78K0/KF2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 P06 P05 P04 P03 P02 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 P47 P46 P45 P44 P43 P42 P41 P40 FF04H 00H (output latch) R/W P5 P57 P56 P55 P54 P53 P52 P51 P50 FF05H 00H (output latch) R/W P6 P67 P66 P65 P64 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P120 FF0CH 00H (output latch) R/W P13 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W P14 0 0 P145 P144 P143 P142 P141 P140 FF0EH 00H (output latch) R/W Pmn P124Note P123Note P122Note P121Note m = 0 to 7, 12 to 14; n = 0 to 7 Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note "0" is always read from the output latch of P121 to P124 if the pin is in the external clock input mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 214 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of these registers. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-39. Format of Pull-up Resistor Option Register (78K0/KB2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 0 0 0 0 0 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3, 12; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 215 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-40. Format of Pull-up Resistor Option Register (78K0/KC2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 0 0 0 0 0 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 0 0 0 0 0 0 PU41 PU40 FF34H 00H R/W PU7 0 0 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14Note 0 0 0 0 0 0 0 PU140Note FF3EH 00H R/W PU75Note PU74Note Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3, 4, 7, 12, 14; n = 0 to 7) Note 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected 48-pin products only R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 216 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-41. Format of Pull-up Resistor Option Register (78K0/KD2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 0 0 0 PU03 PU02 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 0 0 0 0 0 0 PU41 PU40 FF34H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14 0 0 0 0 0 0 0 PU140 FF3EH 00H R/W Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3, 4, 7, 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 217 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-42. Format of Pull-up Resistor Option Register (78K0/KE2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 0 0 0 0 PU43 PU42 PU41 PU40 FF34H 00H R/W PU5 0 0 0 0 PU53 PU52 PU51 PU50 FF35H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14 0 0 0 0 0 0 PU141 PU140 FF3EH 00H R/W Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 218 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-43. Format of Pull-up Resistor Option Register (78K0/KF2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 FF34H 00H R/W PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 FF35H 00H R/W PU6 PU67 PU66 PU65 PU64 0 0 0 0 FF36H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14 0 0 PU145 PU144 PU143 PU142 PU141 PU140 FF3EH 00H R/W Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected (4) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark P20/ANI0 to P23/ANI3 pins: 78K0/KB2 P20/ANI0 to P25/ANI5 pins: 38-pin products of 78K0/KC2 P20/ANI0 to P27/ANI7 pins: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 219 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Figure 5-44. Format of A/D Port Configuration Register (ADPC) Address: FF2FH Products 38-pin other than products the right of KC2 After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 P27/ P26/ P25/ P24/ P23/ P22/ P21/ P20/ ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 KB2 Note 1 Note 1 Note 1 Digital I/O (D)/analog input (A) switching 0 0 0 0 A A A A A A 0 0 0 1 A A A A A 0 0 1 0 A A A A A 0 0 1 1 A A A A 0 1 0 0 A A A 0 1 0 1 A A 0 1 1 0 A A 0 1 1 1 A D 1 0 0 0 D D A A A A D A D D A D D D A D D D D A D D D D D D D D D D D D D D D D D D D D D D D Note 2 Note 2 Other than above Notes 1. Setting permitted 2. Setting prohibited Setting prohibited Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). 2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the peripheral hardware clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 220 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 5.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 5.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. The data of the output latch is cleared when a reset signal is generated. 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-6. Remark The port pins mounted depend on the product. See Table 5-3. Port Functions. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 221 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Table 5-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name PMxx Pxx x I/O P00 TI000 Input 1 P01 TI010 Input 1 x TO00 Output 0 0 P02 SO11 Output 0 0 P03 SI11 Input 1 x P04 SCK11 Input 1 x Output 0 1 SSI11 Input 1 x TI001 Input 1 x P06 TI011 Input 1 x TO01 Output 0 0 P10 SCK10 Input 1 x Output 0 1 P05 TxD0 Output 0 1 SI10 Input 1 x RxD0 Input 1 x P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P14 RxD6 Input 1 x P15 TOH0 Output 0 0 P16 TOH1 Output 0 0 INTP5 Input 1 x TI50 Input 1 x Output 0 0 Input 1 x P11 P17 TO50 P20 to P27 Note Note ANI0 to ANI7 Note The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), the analog input channel specification register (ADS), and PM2. ADPC Analog input selection PM2 Input mode Output mode ADS ANI0/P20 to ANI7/P27 Pins Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Digital I/O selection Remark x: Input mode - Digital input Output mode - Digital output Don't care PMxx: Port mode register Pxx: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 222 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS Table 5-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function Function Name PMxx Pxx 1 x I/O P30 to P32 INTP1 to INTP3 Input P33 INTP4 Input 1 x TI51 Input 1 x TO51 Output 0 0 P60 SCL0 I/O 0 0 P61 SDA0 I/O 0 0 P62 EXSCL0 Input 1 x P70 to P77 KR0 to KR7 Input 1 x P120 INTP0 Input 1 x EXLVI Input 1 x Note - x x Note - x x x x P121 X1 P122 X2 EXCLK P123 XT1 Note P124 XT2 Note Note EXCLKS Input Note - x x - x x Input x x Output 0 0 P140 PCL INTP6 Input 1 x P141 BUZ Output 0 0 INTP7 Input 1 x BUSY0 Input 1 x SCKA0 Input 1 x Output 0 1 P142 P143 SIA0 Input 1 x P144 SOA0 Output 0 0 P145 STB0 Output 0 0 Note When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 are I/O port pins). At this time, setting of PM121 to PM124 and P121 to P124 is not necessary. Remarks 1. x: Don't care PMxx: Port mode register Pxx: Port output latch 2. X1, X2, P31, and P32 of the product with an on-chip debug function (PD78F05xxD and 78F05xxDA) can be used as on-chip debug mode setting pins (OCD0A, OCD0B, OCD1A, and OCD1B) when the on-chip debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD AND 78F05xxDA ONLY). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 223 78K0/Kx2 CHAPTER 5 PORT FUNCTIONS 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. <Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 1 is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the 78K0/Kx2 microcontrollers. <1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output latch by the manipulation in <3>. Figure 5-45. Bit Manipulation Instruction (P10) 1-bit manipulation instruction (set1 P1.0) is executed for P10 bit. P10 Low-level output P11 to P17 P10 High-level output P11 to P17 Pin status: High level Port 1 output latch 0 0 0 Pin status: High level Port 1 output latch 0 0 0 0 0 1 1 1 1 1 1 1 1 1-bit manipulation instruction for P10 bit <1> Port register 1 (P1) is read in 8-bit units. * In the case of P10, an output port, the value of the port output latch (0) is read. * In the case of P11 to P17, input ports, the pin status (1) is read. <2> Set the P10 bit to 1. <3> Write the results of <2> to the output latch of port register 1 (P1) in 8-bit units. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 224 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC). <2> Internal high-speed oscillator This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a reset release, the CPU always starts operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP instruction or using the internal oscillation mode register (RCM). An external main system clock (fEXCLK = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or using RCM. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by using the main clock mode register (MCM). (2) Subsystem clockNote * Subsystem clock oscillator This circuit oscillates at a frequency of fXT = 32.768 kHz by connecting a 32.768 kHz resonator across XT1 and XT2. Oscillation can be stopped by using the processor clock control register (PCC) and clock operation mode select register (OSCCTL). An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by setting PCC and OSCCTL. Note The 78K0/KB2 is not provided with a subsystem clock. Remark fX: X1 clock oscillation frequency fRH: Internal high-speed oscillation clock frequency fEXCLK: External main system clock frequency fXT: XT1 clock oscillation frequency fEXCLKS: External subsystem clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 225 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (3) Internal low-speed oscillation clock (clock for watchdog timer) * Internal low-speed oscillator This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when "internal low-speed oscillator can be stopped by software" is set by option byte. The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates with the internal low-speed oscillation clock. * Watchdog timer * TMH1 (when fRL, fRL/27, or fRL/29 is selected) Remark fRL: Internal low-speed oscillation clock frequency 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Oscillators X1 oscillator Note XT1 oscillator Internal high-speed oscillator Internal low-speed oscillator Note The 78K0/KB2 is not provided with an XT1 oscillator (subsystem clock). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 226 78K0/Kx2 Internal bus Main OSC control register (MOC) Clock operation mode select register (OSCCTL) AMPH EXCLK OSCSEL Main clock mode register (MCM) MCS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 Processor clock control register (PCC) PCC2 PCC1 PCC0 XSEL MCM0 3 3 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) Peripheral hardware clock switch High-speed system clock oscillator X1/P121 X2/EXCLK /P122 fXH Crystal/ceramic oscillation fX External input clock fEXCLK Peripheral hardware clock (fPRS) Controller fXP System clock switch Internal highfRH speed oscillator (8 MHz (TYP.)) Prescaler fXP 2 fXP 22 fXP 23 fXP 24 Internal lowfRL speed oscillator (240 kHz (TYP.)) LSRSTOP RSTOP Internal oscillation mode register (RCM) Internal bus CPU clock (fCPU) Watchdog timer, 8-bit timer H1 227 CHAPTER 6 CLOCK GENERATOR RSTS Option byte 1: Cannot be stopped 0: Can be stopped Selector R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 6-1. Block Diagram of Clock Generator (78K0/KB2) 78K0/Kx2 Internal bus Main OSC control register (MOC) Clock operation mode select register (OSCCTL) AMPH EXCLK OSCSEL Main clock mode register (MCM) MCS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 Processor clock control register (PCC) XTSTART CLS XSEL MCM0 CSS PCC2 PCC1 PCC0 3 4 STOP High-speed system clock oscillator X1/P121 X2/EXCLK/ P122 X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) fXH Crystal/ceramic oscillation fX External input clock fEXCLK To subsystem clock oscillator Peripheral hardware clock switch Controller Main system fXP clock switch Internal highfRH speed oscillator (8 MHz (TYP.)) Crystal oscillation XT2/EXCLKS/ P124 External input clock 1/2 fXT fSUB fXP 22 fXP 23 fXP 24 fSUB 2 Internal lowspeed oscillator fRL (240 kHz (TYP.)) Watch timer, clock output CPU clock (fCPU) Watchdog timer, 8-bit timer H1 fEXCLKS RSTS Clock operation mode select register (OSCCTL) LSRSTOP RSTOP Internal oscillation mode register (RCM) Internal bus Option byte 1: Cannot be stopped 0: Can be stopped 228 CHAPTER 6 CLOCK GENERATOR XTSTART EXCLKS OSCSELS Processor clock control register (PCC) Prescaler fXP 2 Subsystem clock oscillator XT1/P123 Peripheral hardware clock (fPRS) Selector R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 6-2. Block Diagram of Clock Generator (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) 78K0/Kx2 Remark CHAPTER 6 CLOCK GENERATOR fX: X1 clock oscillation frequency fRH: Internal high-speed oscillation clock frequency fEXCLK: External main system clock frequency fXH: High-speed system clock frequency fXP: Main system clock frequency fPRS: Peripheral hardware clock frequency fCPU: CPU clock frequency fXT: XT1 clock oscillation frequency fEXCLKS: External subsystem clock frequency fSUB: Subsystem clock frequency fRL: Internal low-speed oscillation clock frequency 6.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. * Clock operation mode select register (OSCCTL) * Processor clock control register (PCC) * Internal oscillation mode register (RCM) * Main OSC control register (MOC) * Main clock mode register (MCM) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the onchip oscillator. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 229 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KB2) Address: FF9FH After reset: 00H R/W Symbol <7> <6> 5 4 3 2 1 <0> OSCCTL EXCLK OSCSEL 0 0 0 0 0 AMPH EXCLK OSCSEL 0 0 I/O port mode I/O port 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 I/O port mode I/O port 1 1 External clock input mode I/O port High-speed system clock pin operation mode AMPH P121/X1 pin P122/X2/EXCLK pin External clock input Operating frequency control 0 1 MHz fXH 10 MHz 1 10 MHz < fXH 20 MHz Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. <R> 2. Set AMPH before setting the main clock mode register (MCM). 3. Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the high-speed system clock (external clock input) is selected as the CPU clock, supply of the CPU clock is stopped for the duration of 160 external clocks after AMPH is set to 1. 4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal highspeed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, the oscillation stabilization time is counted after the STOP mode is released. 5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). 6. Be sure to clear bits 1 to 5 to 0. Remark fXH: High-speed system clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 230 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-4. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Address: FF9FH After reset: 00H R/W Symbol <7> <6> OSCCTL EXCLK OSCSEL EXCLKS <5> <4> EXCLK OSCSEL High-speed system clock pin operation mode 0 0 Note Note 3 2 1 <0> 0 0 0 AMPH P121/X1 pin I/O port mode I/O port P122/X2/EXCLK pin 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 I/O port mode I/O port 1 1 External clock input mode I/O port AMPH Note OSCSELS External clock input Operating frequency control 0 1 MHz fXH 10 MHz 1 10 MHz < fXH 20 MHz EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor clock control register (PCC)). See (3) Setting of operation mode for subsystem clock pin. Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. <R> 2. Set AMPH before setting the main clock mode register (MCM). 3. Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the high-speed system clock (external clock input) is selected as the CPU clock, supply of the CPU clock is stopped for the duration of 160 external clocks after AMPH is set to 1. 4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal highspeed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, the oscillation stabilization time is counted after the STOP mode is released. 5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). 6. Be sure to clear bits 1 to 3 to 0. Remark fXH: High-speed system clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 231 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 6-5. Format of Processor Clock Control Register (PCC) (78K0/KB2) Address: FFFBH After reset: 01H R/W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 Other than above Cautions 1. 2. Remark CPU clock (fCPU) selection Setting prohibited Be sure to clear bits 3 to 7 to 0. The peripheral hardware clock (fPRS) is not divided when the division ratio of the PCC is set. fXP: Main system clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 232 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-6. Format of Processor Clock Control Register (PCC) (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Address: FFFBH After reset: 01H Symbol 7 PCC 0 R/W 6 XTSTART Note2 Note 1 <5> <4> 3 2 1 0 CLS CSS 0 PCC2 PCC1 PCC0 CLS CPU clock status 0 Main system clock 1 Subsystem clock CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 0 0 0 fSUB/2 0 0 1 0 1 0 1 0 1 1 1 0 0 Other than above CPU clock (fCPU) selection Setting prohibited Notes 1. Bit 5 is read-only. 2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock operation mode select register (OSCCTL)). See (3) Setting of operation mode for subsystem clock pin. Cautions 1. Be sure to clear bits 3 and 7 to "0". 2. The peripheral hardware clock (fPRS) is not divided when the division ratio of the PCC is set. Remark fXP: Main system clock oscillation frequency fSUB: Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Kx2 microcontrollers. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 233 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Note 2 Main System Clock High-Speed System Clock At 10 MHz Operation fXP Note 1 Subsystem Clock Internal High-Speed Note 1 Oscillation Clock At 20 MHz Operation At 8 MHz (TYP.) Operation At 32.768 kHz Operation 0.2 s 0.1 s 0.25 s (TYP.) - 0.4 s 0.2 s 0.5 s (TYP.) - fXP/2 2 0.8 s 0.4 s 1.0 s (TYP.) - fXP/2 3 1.6 s 0.8 s 2.0 s (TYP.) - fXP/2 4 3.2 s 1.6 s 4.0 s (TYP.) - fXP/2 fSUB/2 - Note 2 Notes 1. 122.1 s - The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (highspeed system clock/internal high-speed oscillation clock) (see Figure 6-9). 2. The 78K0/KB2 is not provided with a subsystem clock. (3) Setting of operation mode for subsystem clock pin The operation mode for the subsystem clock pinNote can be set by using bit 6 (XTSTART) of the processor clock control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register (OSCCTL) in combination. Note The 78K0/KB2 is not provided with a subsystem clock. Table 6-3. Setting of Operation Mode for Subsystem Clock Pin (78K0/KC2, 78K0/KD2, 78K0/KE2, 78K0/KF2) PCC OSCCTL Subsystem Clock Pin Operation Mode P123/XT1 Pin P124/XT2/EXCLKS Pin Bit 6 Bit 5 Bit 4 XTSTART EXCLKS OSCSELS 0 0 0 I/O port mode I/O port 0 0 1 XT1 oscillation mode Crystal resonator connection 0 1 0 I/O port mode I/O port 0 1 1 External clock input mode I/O port 1 x x XT1 oscillation mode Crystal resonator connection Caution External clock input Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating with main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS. Remark x: don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 234 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80HNote 1. Figure 6-7. Format of Internal Oscillation Mode Register (RCM) Address: FFA0H After reset: 80H Note 1 R/W Note 2 Symbol <7> 6 5 4 3 2 <1> <0> RCM RSTS 0 0 0 0 0 LSRSTOP RSTOP RSTS Status of internal high-speed oscillator 0 Waiting for accuracy stabilization of internal high-speed oscillator 1 Stability operating of internal high-speed oscillator LSRSTOP Internal low-speed oscillator oscillating/stopped 0 Internal low-speed oscillator oscillating 1 Internal low-speed oscillator stopped RSTOP Internal high-speed oscillator oscillating/stopped 0 Internal high-speed oscillator oscillating 1 Internal high-speed oscillator stopped Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator has been stabilized. 2. Bit 7 is read-only. Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. <1> 78K0/KB2 * When MCS = 1 (when CPU operates with the high-speed system clock) <2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 235 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 6-8. Format of Main OSC Control Register (MOC) Address: FFA2H After reset: 80H R/W Symbol <7> 6 5 4 3 2 1 0 MOC MSTOP 0 0 0 0 0 0 0 MSTOP Control of high-speed system clock operation X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is enabled 1 X1 oscillator stopped External clock from EXCLK pin is disabled Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock other than the high-speed system clock. Specifically, set under either of the following conditions. <1> 78K0/KB2 * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) <2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP to 1. 2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select register (OSCCTL) is 0 (I/O port mode). 3. The peripheral hardware cannot operate when the peripheral hardware clock is stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 236 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-9. Format of Main Clock Mode Register (MCM) Address: FFA1H After reset: 00H R/W Note Symbol 7 6 5 4 3 <2> <1> <0> MCM 0 0 0 0 0 XSEL MCS MCM0 XSEL MCM0 Selection of clock supplied to main system clock and peripheral hardware Main system clock (fXP) Peripheral hardware clock (fPRS) 0 Internal high-speed oscillation clock Internal high-speed oscillation clock 0 1 (fRH) (fRH) 1 0 1 1 0 High-speed system clock (fXH) High-speed system clock (fXH) MCS Main system clock status 0 Operates with internal high-speed oscillation clock 1 Operates with high-speed system clock Note Bit 1 is read-only. Cautions 1. XSEL can be changed only once after a reset release. 2. Do not rewrite MCM0 when the CPU clock operates with the subsystem clock. 3. A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0. * Watchdog timer (operates with internal low-speed oscillation clock) * When "fRL", "fRL/27", or "fRL/29" is selected as the count clock for 8-bit timer H1 (operates with internal low-speed oscillation clock) * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 237 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 6-10. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 204.8 s min. 102.4 s min. 13 819.2 s min. 409.6 s min. 14 1.64 ms min. 819.2 s min. 15 3.27 ms min. 1.64 ms min. 16 6.55 ms min. 3.27 ms min. 1 0 0 0 0 2 /fX min. 1 1 0 0 0 2 /fX min. 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 fX = 20 MHz 11 2 /fX min. 2 /fX min. 2 /fX min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 238 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 6-11. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 204.8 s 102.4 s 13 819.2 s 409.6 s 14 1.64 ms 819.2 s 15 3.27 ms 1.64 ms 16 6.55 ms 3.27 ms 0 0 1 2 /fX 0 1 0 2 /fX 0 1 1 1 0 1 2 /fX 0 0 2 /fX 1 2 /fX Other than above fX = 20 MHz 11 Setting prohibited Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 239 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-12 shows an example of the external circuit of the X1 oscillator. Figure 6-12. Example of External Circuit of X1 Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS X1 X2 External clock EXCLK Cautions are listed on the next page. 6.4.2 XT1 oscillator The XT1 oscillatorNote oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLKS pin. Figure 6-13 shows an example of the external circuit of the XT1 oscillator. Note The 78K0/KB2 is not provided with an XT1 oscillator. Figure 6-13. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 External clock EXCLKS Cautions are listed on the next page. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 240 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-12 and 6-13 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-14 shows examples of incorrect resonator connection. Figure 6-14. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS Remark X1 X2 VSS X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 241 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-14. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (e) Signals are fetched VSS Remark X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 242 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clockNote for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Note The 78K0/KB2 is not provided with a subsystem clock. Input (PM123/PM124 = 1): Independently connect to VDD or VSS via a resistor. Output (PM123/PM124 = 0): Leave open. Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL) PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12) 6.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/Kx2 microcontrollers. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)). 6.4.5 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/Kx2 microcontrollers. The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock. "Can be stopped by software" or "Cannot be stopped" can be selected by the option byte. When "Can be stopped by software" is set, oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte. 6.4.6 Prescaler The prescaler generates the CPU clock by dividing the main system clock when the main system clock is selected as the clock to be supplied to the CPU. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 243 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6-1 and 6-2). * Main system clock fXP * High-speed system clock fXH X1 clock fX External main system clock fEXCLK * Internal high-speed oscillation clock fRH * Subsystem clock fSUB Note * XT1 clock fXT * External subsystem clock fEXCLKS * Internal low-speed oscillation clock fRL * CPU clock fCPU * Peripheral hardware clock fPRS Note The 78K0/KB2 is not provided with a subsystem clock. The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the 78K0/Kx2 microcontrollers, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance can be improved. When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-15. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 244 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-15. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply voltage (VDD) 1.8 VNotes 1,2 1.59 V (TYP.) 0.5 V/ms (MIN.)Notes 1,2 0V Internal reset signal <1> CPU clock <3> Waiting for voltage stabilization (1.93 to 5.39 ms) Reset processing (11 to 45 s) <5> Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected)Note 5 Note 3 <4> X1 clock oscillation stabilization time: 211/fX to 216/fXNote 4 Starting X1 oscillation <4> is set by software. Starting XT1 oscillation is set by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). Notes 1. 2. 3. With standard and (A) grade products, if the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE = 1) (see Figure 6-16). When a low level has been input to the RESET pin until the voltage reaches 1.8 V, the CPU operates with the same timing as <2> and thereafter in Figure 6-15, after the reset has been released by the RESET pin. With (A2) grade products, if the voltage rises with a slope of less than 0.75 V/ms (MIN.) from power application until the voltage reaches 2.7 V, input a low level to the RESET pin from power application until the voltage reaches 2.7 V. When a low level has been input to the RESET pin until the voltage reaches 2.7 V, the CPU operates with the same timing as <2> and thereafter in Figure 6-15, after the reset has been released by the RESET pin. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 245 78K0/Kx2 Notes 4. 5. Caution CHAPTER 6 CLOCK GENERATOR When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). The 78K0/KB2 is not provided with a subsystem clock. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 246 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-16. Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) 2.7 V (TYP.) Power supply voltage (VDD) 0V Internal reset signal <1> <3> Reset processing (11 to 45 s) <5> Internal high-speed oscillation clock CPU clock Switched by software High-speed system clock <5> Subsystem clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Waiting for oscillation accuracy <4> stabilization (86 to 361 s) Subsystem clock (fSUB) (when XT1 oscillation selected)Note 2 X1 clock oscillation stabilization time: 211/fX to 216/fXNote 1 Starting X1 oscillation <4> is set by software. Starting XT1 oscillation is set by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-speed oscillation clock. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). Notes 1. 2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). The 78K0/KB2 is not provided with a subsystem clock. Cautions 1. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. 2. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 247 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock). 6.6 Controlling Clock 6.6.1 Example of controlling high-speed system clock The following two types of high-speed system clocks are available. * X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. * External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins. Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating X1 clock (2) When using external main system clock (3) When using high-speed system clock as CPU clock and peripheral hardware clock (4) When stopping high-speed system clock (1) Example of setting procedure when oscillating the X1 clock <1> Setting frequency (OSCCTL register) Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used. Note AMPH Operating Frequency Control 0 1 MHz f XH 10 MHz 1 10 MHz < f XH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU is stopped for 4.06 to 16.12 s. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode. EXCLK OSCSEL Operation Mode of High- P121/X1 Pin P122/X2/EXCLK Pin Speed System Clock Pin 0 1 X1 oscillation mode Crystal/ceramic resonator connection <3> Controlling oscillation of X1 clock (MOC register) If MSTOP is cleared to 0, the X1 oscillator starts oscillating. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 248 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock. Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. 2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C)). (2) Example of setting procedure when using the external main system clock <1> Setting frequency (OSCCTL register) Using AMPH, set the frequency to be used. Note AMPH Operating Frequency Control 0 1 MHz f XH 10 MHz 1 10 MHz < f XH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. The clock supply to the CPU is stopped for the duration of 160 external clocks after AMPH is set to 1. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode. EXCLK OSCSEL Operation Mode of High- P121/X1 Pin P122/X2/EXCLK Pin Speed System Clock Pin 1 1 External clock input mode I/O port External clock input <3> Controlling external main system clock input (MOC register) When MSTOP is cleared to 0, the input of the external main system clock is enabled. Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is operating. 2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C)). (3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral hardware clock <1> Setting high-speed system clock oscillationNote (See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 249 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (f XP ) 1 1 Peripheral Hardware Clock (f PRS ) High-speed system clock (f XH ) High-speed system clock (f XH ) Caution If the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 Other than above CPU Clock (fCPU) Selection Setting prohibited (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. * Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used) * Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used) (a) To execute a STOP instruction <1> Setting to stop peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is stopped (the input of the external clock is disabled). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 250 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to a clock other than the high-speed system clock. * 78K0/KB2 MCS CPU Clock Status 0 Internal high-speed oscillation clock 1 High-speed system clock * 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 CLS MCS CPU Clock Status 0 0 Internal high-speed oscillation clock 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the high-speed system clock (MOC register) When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled). Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 Example of controlling internal high-speed oscillation clock The following describes examples of clock setting procedures for the following cases. (1) When restarting oscillation of the internal high-speed oscillation clock (2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or highspeed system clock as peripheral hardware clock (3) When stopping the internal high-speed oscillation clock R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 251 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1 <1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register) When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating. <2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register) Wait until RSTS is set to 1Note 2. Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> * Restarting oscillation of the internal high-speed oscillation clockNote (See 6.6.2 (1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock). * Oscillating the high-speed system clockNote (This setting is required when using the high-speed system clock as the peripheral hardware clock. See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high-speed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (f XP ) 0 0 0 1 1 0 Peripheral Hardware Clock (f PRS ) Internal high-speed oscillation clock (f RH ) Internal high-speed oscillation clock (f RH ) High-speed system clock (f XH ) <3> Selecting the CPU clock division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 Other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 CPU Clock (fCPU) Selection Setting prohibited 252 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. * Executing the STOP instruction to set the STOP mode * Setting RSTOP to 1 and stopping the internal high-speed oscillation clock (a) To execute a STOP instruction <1> Setting of peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. To operate the CPU immediately after the STOP mode has been released, set MCM0 to 0, switch the CPU clock to the internal high-speed oscillation clock, and check that RSTS is 1. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and internal high-speed oscillation clock is stopped. (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock. When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change the CPU clock to a clock other than the internal high-speed oscillation clock. * 78K0/KB2 MCS CPU Clock Status 0 Internal high-speed oscillation clock 1 High-speed system clock * 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 CLS MCS CPU Clock Status 0 0 Internal high-speed oscillation clock 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the internal high-speed oscillation clock (RCM register) When RSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 253 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.3 Example of controlling subsystem clock The following two types of subsystem clocksNote are available. * XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. * External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. Note The 78K0/KB2 is not provided with a subsystem clock. Cautions 1. The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release. 2. Do not start the peripheral hardware operation with the external clock from peripheral hardware pins when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. The following describes examples of setting procedures for the following cases. (1) When oscillating XT1 clock (2) When using external subsystem clock (3) When using subsystem clock as CPU clock (4) When stopping subsystem clock (1) Example of setting procedure when oscillating the XT1 clock <1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers) When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from port mode to XT1 oscillation mode. XTSTART EXCLKS OSCSELS Operation Mode of P123/XT1 Pin Subsystem Clock Pin 0 0 1 1 x x Remark XT1 oscillation mode P124/XT2/ EXCLKS Pin Crystal/ceramic resonator connection x: don't care <2> Waiting for the stabilization of the subsystem clock oscillation Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins. XTSTART EXCLKS OSCSELS 0 1 1 Operation Mode of Subsystem Clock Pin External clock input mode P123/XT1 Pin I/O port P124/XT2/ EXCLKS Pin External clock input Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 254 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR (3) Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillationNote (See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. CSS PCC2 PCC1 PCC0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Other than above CPU Clock (fCPU) Selection fSUB/2 Setting prohibited (4) Example of setting procedure when stopping the subsystem clock <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock. When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to a clock other than the subsystem clock. CLS MCS 0 0 Internal high-speed oscillation clock CPU Clock Status 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the subsystem clock (OSCCTL register) When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled). Cautions 1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. 2. The subsystem clock oscillation cannot be stopped using the STOP instruction. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 255 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. * Watchdog timer * 8-bit timer H1 (if fRL is selected as the count clock) In addition, the following operation modes can be selected by the option byte. * Internal low-speed oscillator cannot be stopped * Internal low-speed oscillator can be stopped by software The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte. (1) Example of setting procedure when stopping the internal low-speed oscillation clock <1> Setting LSRSTOP to 1 (RCM register) When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped. (2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock <1> Clearing LSRSTOP to 0 (RCM register) When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted. Caution If "Internal low-speed oscillator cannot be stopped" is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 256 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 6-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting (78K0/KB2) XSEL MCM0 EXCLK 0 x x X1 clock 1 0 0 External main system clock 1 0 1 X1 clock 1 1 0 External main system clock 1 1 1 Supplied Clock Clock Supplied to CPU Clock Supplied to Peripheral Hardware Internal high-speed oscillation clock Internal high-speed oscillation clock Remarks 1. The 78K0/KB2 is not provided with a subsystem clock. 2. XSEL: MCM0: Bit 2 of the main clock mode register (MCM) Bit 0 of MCM EXCLK: Bit 7 of the clock operation mode select register (OSCCTL) x: don't care Table 6-5. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) XSEL CSS MCM0 EXCLK 0 0 x x X1 clock 1 0 0 0 External main system clock 1 0 0 1 X1 clock 1 0 1 0 External main system clock 1 0 1 1 Internal high-speed oscillation clock 0 1 x x X1 clock 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 Supplied Clock Clock Supplied to CPU Clock Supplied to Peripheral Hardware Internal high-speed oscillation clock Internal high-speed oscillation clock Subsystem clock External main system clock Remark XSEL: Bit 2 of the main clock mode register (MCM) CSS: Bit 4 of the processor clock control register (PCC) MCM0: Bit 0 of MCM EXCLK: Bit 7 of the clock operation mode select register (OSCCTL) x: don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 257 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.6 CPU clock status transition diagram Figure 6-17 and 6-18 shows the CPU clock status transition diagram of this product. Figure 6-17. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KB2) Power ON Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) VDD < 1.59 V (TYP.) (A) VDD 1.59 V (TYP.) Reset release Internal low-speed oscillation: Operating Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Stops (I/O port mode) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Selectable by CPU (B) VDD 1.8 V (MIN.)Note CPU: Operating with internal highspeed oscillation (F) CPU: Internal highspeed oscillation STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops (D) Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Operating (C) CPU: Internal highspeed oscillation HALT CPU: Operating with X1 oscillation or EXCLK input (E) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Operable (G) CPU: X1 oscillation/EXCLK input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operating CPU: X1 oscillation/EXCLK input STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops Note Standard and (A) grade products: 1.8 V, (A2) grade products: 2.7 V Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45 s). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 258 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Figure 6-18. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Power ON VDD < 1.59 V (TYP.) (A) VDD 1.59 V (TYP.) Reset release Internal low-speed oscillation: Operating Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating (D) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU VDD 1.8 V (MIN.)Note (B) CPU: Operating with internal highspeed oscillation (H) CPU: Internal highspeed oscillation STOP CPU: Operating with XT1 oscillation or EXCLKS input CPU: Internal highspeed oscillation HALT (C) (G) CPU: XT1 oscillation/EXCLKS input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operating (E) CPU: Operating with X1 oscillation or EXCLK input Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU <R> Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Operable Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operable (I) CPU: X1 oscillation/EXCLK input STOP (F) CPU: X1 oscillation/EXCLK input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Operable Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Operable Note Standard and (A) grade products: 1.8 V, (A2) grade products: 2.7 V Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45 s). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 259 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-6 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-6. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) (B) SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register AMPH EXCLK OSCSEL MSTOP Status Transition (A) (B) (C) (X1 clock: 1 MHz fXH 0 0 1 0 XSEL MCM0 1 1 1 1 1 1 1 1 Must be checked 10 MHz) (A) (B) (C) (external main clock: 1 MHz 0 1 1 0 fXH 10 MHz) Must not be checked (A) (B) (C) (X1 clock: 10 MHz < fXH 1 0 1 0 Must be checked 20 MHz) (A) (B) (C) (external main clock: 10 MHz < 1 1 1 0 fXH 20 MHz) Caution OSTC Register Must not be checked Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C)). (3) CPU operating with subsystem clock (D) after reset release (A)Note (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) Note The 78K0/KB2 is not provided with a subsystem clock. (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS Waiting for OSCSELS CSS Oscillation Status Transition Stabilization (A) (B) (D) (XT1 clock) (A) (B) (D) (external subsystem clock) 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Don't care 260 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-6. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Note EXCLK AMPH OSCSEL OSTC MSTOP XSEL Note MCM0 Register Status Transition (B) (C) (X1 clock: 1 MHz fXH 10 MHz) 0 0 1 0 Must be 1 1 1 1 1 1 1 1 checked (B) (C) (external main clock: 1 MHz fXH 0 1 1 0 10 MHz) Must not be checked (B) (C) (X1 clock: 10 MHz < fXH 20 MHz) 1 0 1 0 Must be checked (B) (C) (external main clock: 10 MHz < fXH 1 1 1 0 20 MHz) Must not be checked Unnecessary if these registers are already set Unnecessary if the CPU is operating with the high-speed system clock Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C)). (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)Note Note The 78K0/KB2 is not provided with a subsystem clock. (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS OSCSELS Waiting for CSS Oscillation Status Transition (B) (D) (XT1 clock) (B) (D) (external subsystem clock) Stabilization 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Unnecessary if the CPU is operating with the subsystem clock Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 261 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-6. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 0 Confirm this flag is 1. 0 Status Transition (C) (B) Unnecessary if the CPU is operating with the internal high-speed oscillation clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)Note Note The 78K0/KB2 is not provided with a subsystem clock. (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS Waiting for OSCSELS CSS Oscillation Status Transition Stabilization (C) (D) (XT1 clock) (C) (D) (external subsystem clock) 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) Note The 78K0/KB2 is not provided with a subsystem clock. (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 CSS 0 Confirm this flag 0 0 Status Transition (D) (B) is 1. Unnecessary if the CPU is operating Unnecessary if with the internal high-speed XSEL is 0 oscillation clock Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18. 2. MCM0: Bit 0 of the main clock mode register (MCM) EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL) RSTS, RSTOP: Bits 7 and 0 of the internal oscillation mode register (RCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 262 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-6. CPU Clock Transition and SFR Register Setting Examples (4/5) Note (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) Note The 78K0/KB2 is not provided with a subsystem clock. (Setting sequence of SFR registers) Note Setting Flag of SFR Register AMPH EXCLK OSCSEL MSTOP OSTC XSEL Note MCM0 CSS 1 1 0 1 1 0 1 1 0 1 1 0 Register Status Transition (D) (C) (X1 clock: 1 MHz fXH 0 0 1 0 10 MHz) Must be checked (D) (C) (external main clock: 1 MHz 0 1 1 0 fXH 10 MHz Must not be checked (D) (C) (X1 clock: 10 MHz < fXH 1 0 1 0 20 MHz) Must be checked (D) (C) (external main clock: 10 MHz < 1 1 1 0 fXH 20 MHz) Must not be checked Unnecessary if these registers Unnecessary if the Unnecessary if this register are already set CPU is operating is already set with the high-speed system clock Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C)). (10) * HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B) * HALT mode (F) set while CPU is operating with high-speed system clock (C) * HALT mode (G) set while CPU is operating with subsystem clock (D)Note Status Transition (B) (E) Setting Executing HALT instruction (C) (F) (D) (G) Note Note The 78K0/KB2 is not provided with a subsystem clock. Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18. 2. EXCLK, OSCSEL, AMPH: Bits 7, 6, and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) CSS: Bit 4 of the processor clock control register (PCC) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 263 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Table 6-6. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) * STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B) * STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition Setting (B) (H) Stopping peripheral functions that (C) (I) cannot operate in STOP mode Executing STOP instruction Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18. 2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) CSS: Bit 4 of the processor clock control register (PCC) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 264 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-7. Changing CPU Clock CPU Clock Before Change KB2, KC2, KD2, KE2, KF2 Internal highspeed oscillation clock X1 clock External main system clock KC2, KD2, KE2, KF2 (other than KB2) Internal highspeed oscillation clock Condition Before Change After Change X1 clock Stabilization of X1 oscillation * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. External main system clock Enabling input of external clock from EXCLK pin * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. Internal highspeed oscillation clock Oscillation of internal high-speed oscillator * RSTOP = 0 X1 oscillation can be stopped (MSTOP = 1). XT1 clock Stabilization of XT1 oscillation * XTSTART = 0, EXCLKS = 0, OSCSELS = 1, or XTSTART = 1 * After elapse of oscillation stabilization time Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 clock External main system clock Internal highspeed oscillation clock Processing After Change External main system clock input can be disabled (MSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). External subsystem clock Enabling input of external clock from EXCLKS pin * XTSTART = 0, EXCLKS = 1, OSCSELS = 1 Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 clock X1 oscillation can be stopped (MSTOP = 1). External main system clock External main system clock input can be disabled (MSTOP = 1). XT1 clock, external subsystem clock Remark Internal highspeed oscillation clock Oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock * RSTOP = 0, MCS = 0 XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time * MCS = 1 * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. External main system clock Enabling input of external clock from EXCLK pin and selection of high-speed system clock as main system clock * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * MCS = 1 * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. The 78K0/KB2 is not provided with a subsystem clock. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 265 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the preswitchover clock for several clocks (see Table 6-8 and 6-9). Whether the CPU is operating on the main system clock or the subsystem clockNote can be ascertained using bit 5 (CLS) of the PCC register. Note The 78K0/KB2 is not provided with a subsystem clock. Table 6-8. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor (78K0/KB2) Set Value Before Set Value After Switchover Switchover PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 8 clocks 0 1 0 4 clocks 4 clocks 0 1 1 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 clock 1 clock Remark 16 clocks 16 clocks 16 clocks 16 clocks 8 clocks 8 clocks 8 clocks 4 clocks 4 clocks 2 clocks 1 clock The number of clocks listed in Table 6-8 is the number of CPU clocks before switchover. Table 6-9. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Set Value Before Set Value After Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 1 0 0 0 0 0 0 16 clocks 1 0 0 1 0 0 0 1 0 0 0 0 0 1 8 clocks 0 1 0 4 clocks 4 clocks 0 1 1 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 clock 1 clock 1 clock x x x 2 clocks 2 clocks 2 clocks 2 clocks 1 0 1 0 0 1 x x x 16 clocks 16 clocks 16 clocks 2fXP/fSUB clocks 8 clocks 8 clocks 8 clocks fXP/fSUB clocks 4 clocks 4 clocks fXP/2fSUB clocks 2 clocks fXP/4fSUB clocks fXP/8fSUB clocks 2 clocks Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remark 1. The number of clocks listed in Table 6-9 is the number of CPU clocks before switchover. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 266 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR Remark 2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fXP = 10 MHz, fSUB = 32.768 kHz) fXP/fSUB = 10000/32.768 305.1 306 clocks By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the preswitchover clock for several clocks (see Table 6-10). Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be ascertained using bit 1 (MCS) of MCM. Table 6-10. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 0 1 + 2fRH/fXH clock 1 Cautions 1. 1 1 + 2fXH/fRH clock When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. 2. Do not rewrite MCM0 when the CPU clock operates with the subsystem clock. Remarks 1. The number of clocks listed in Table 6-10 is the number of main system clocks before switchover. 2. Calculate the number of clocks in Table 6-10 by removing the decimal portion. Example When switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz) 1 + 2fRH/fXH = 1 + 2 x 8/10 = 1 + 2 x 0.8 = 1 + 1.6 = 2.6 2 clocks R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 267 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.9 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 6-11. Conditions Before the Clock Oscillation Is Stopped and Flag Settings (78K0/KB2) Note Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register Internal high-speed MCS = 1 oscillation clock (The CPU is operating on the high-speed system clock) X1 clock MCS = 0 External main system clock (The CPU is operating on the internal high-speed oscillation clock) RSTOP = 1 MSTOP = 1 Note The 78K0/KB2 is not provided with a subsystem clock. Table 6-12. Conditions Before the Clock Oscillation Is Stopped and Flag Settings (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register Internal high-speed MCS = 1 or CLS = 1 oscillation clock (The CPU is operating on a clock other than the internal high-speed RSTOP = 1 oscillation clock) X1 clock MCS = 0 or CLS = 1 External main system clock (The CPU is operating on a clock other than the high-speed system clock) XT1 clock CLS = 0 External subsystem clock (The CPU is operating on a clock other than the subsystem clock) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 MSTOP = 1 OSCSELS = 0 268 78K0/Kx2 CHAPTER 6 CLOCK GENERATOR 6.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/Kx2 microcontrollers. Remark The peripheral hardware depends on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. Table 6-13. Peripheral Hardware and Source Clocks Peripheral Hardware Clock (fPRS) Subsystem Clock Note 1 (fSUB) Internal LowSpeed Oscillation Clock (fRL) TM50 Output 00 Y N N N Y (TI000 pin) 01 Y N N N Y (TI001 pin) Source Clock Peripheral Hardware 16-bit timer/ event counter External Clock from Peripheral Hardware Pins Note 2 Note 2 8-bit timer/ event counter 50 Y N N N Y (TI50 pin) Note 2 51 Y N N N Y (TI51 pin) Note 2 8-Bit timer H0 Y N N Y N H1 Y N Y N N Watch timer Y Y N N N Watchdog timer N N Y N N Buzzer output Y N N N N Clock output Y Y N N N A/D converter Y N N N N UART0 Y N N Y N UART6 Y N N Y N CSI10 Y N N N Y (SCK10 pin) CSI11 Y N N N Y (SCK11 pin) CSIA0 Y N N N Y (SCKA0 pin) IIC0 Y N N N Serial interface Note 2 Note 2 Note 2 Y (EXSCL0, Note 2 SCL0 pin) Notes 1. The 78K0/KB2 is not provided with a subsystem clock. 2. Do not start the peripheral hardware operation with the external clock from peripheral hardware pins when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Remark Y: Can be selected, N: Cannot be selected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 269 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB 16-bit timer/event counters 00 16-bit timer/event - counters 00 Remark : Mounted, -: Not mounted 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 have the following functions. (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (3) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (4) One-shot pulse output 16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. (5) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (6) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 270 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Time/counter 16-bit timer counter 0n (TM0n) Register 16-bit timer capture/compare registers 00n, 01n (CR00n, CR01n) Timer input TI00n, TI01n pins Timer output TO0n pin, output controller Control registers 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products Figures 7-1 and 7-2 show the block diagrams. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) Selector CRC002CRC001 CRC000 Noise eliminator TI010/TO00/P01 Selector To CR010 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00 output TO00/TI010/ P01 Match 2 Output latch (P01) Noise eliminator TI000/P00 Clear PM01 16-bit timer capture/compare register 010 (CR010) Selector fPRS Selector fPRS fPRS/22 fPRS/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus (Cautions 1 to 3 are listed on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 271 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) Selector CRC012CRC011 CRC010 Noise eliminator TI011/TO01/P06 Selector To CR011 16-bit timer capture/compare register 001 (CR001) INTTM001 Match Noise eliminator 16-bit timer counter 01 (TM01) Output controller TO01 output TO01/TI011/ P06 Match 2 Output latch (P06) Noise eliminator TI001/P05/ SSI11 Clear PM06 16-bit timer capture/compare register 011 (CR011) Selector fPRS Selector fPRS fPRS/24 fPRS/26 INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has been once captured remains stored in CR00n unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value. (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 272 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) After reset: 0000H FF11H (TM00), FFB1H (TM01) 15 14 13 12 11 10 9 R FF10H (TM00), FFB0H (TM01) 8 7 6 5 4 3 2 1 0 TM0n (n = 0, 1) The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of 16bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when TMC0n3 and TMC0n2 = 00. The count value is reset to 0000H in the following cases. * At reset signal generation * If TMC0n3 and TMC0n2 are cleared to 00 * If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid edge to the TI00n pin * If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match * OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin Caution Even if TM0n is read, the value is not captured by CR01n. (2) 16-bit timer capture/compare register 00n (CR00n), 16-bit timer capture/compare register 01n (CR01n) CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by using CRC0n. Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00). The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see 7.5.1 Rewriting CR01n during TM0n operation. These registers can be read or written in 16-bit units. Reset signal generation clears these registers to 0000H. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 273 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) FF13H (CR000), FFB3H (CR001) 15 14 13 12 11 10 9 After reset: 0000H R/W FF12H (CR000), FFB2H (CR001) 8 7 6 5 4 3 2 1 0 CR00n (n = 0, 1) (i) When CR00n is used as a compare register The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM00n) is generated if they match. The value is held until CR00n is rewritten. Caution CR00n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) When CR00n is used as a capture register The count value of TM0n is captured to CR00n when a capture trigger is input. As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin can be selected by using CRC0n or PRM0n. Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) FF15H (CR010), FFB5H (CR011) 15 14 13 12 11 10 9 After reset: 0000H R/W FF14H (CR010), FFB4H (CR011) 8 7 6 5 4 3 2 1 0 CR01n (n = 0, 1) (i) When CR01n is used as a compare register The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM01n) is generated if they match. Caution CR01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) When CR01n is used as a capture register The count value of TM0n is captured to CR01n when a capture trigger is input. It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by PRM0n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 274 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (iii) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation CR00n Register Setting Range 0000H < N FFFFH Operation as interval timer 0000H M FFFFH Normally, this setting is not used. Mask the Operation as square-wave output match interrupt signal (INTTM01n). Operation as external event counter Operation in the clear & start mode CR01n Register Setting Range Note Note 0000H N FFFFH Note M FFFFH Note M<N Note M FFFFH (M N) 0000H entered by TI00n pin valid edge input Operation as free-running timer M < N FFFFH Operation as PPG output Operation as one-shot pulse output Note 0000H 0000H N FFFFH (N M) 0000H Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer counter (TM0n register) is changed from 0000H to 0001H. * When the timer counter is cleared due to overflow * When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by TI00n pin valid edge input) * When the timer counter is cleared due to compare match (when clear & start mode is entered by match between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H)) Timer counter clear TM0n register Compare register set value (0000H) Operation Timer operation enable bit disabled (00) (TMC0n3, TMC0n2) Operation enabled (other than 00) Interrupt request signal Interrupt signal is not generated Interrupt signal is generated Remarks 1. N: CR00n register set value, M: CR01n register set value 2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n). 3. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 275 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. Capture Operation of CR00n and CR01n External Input Signal TI01n Pin Input TI00n Pin Input Capture Operation Capture operation of CRC0n1 = 1 Set values of ES0n1 and CRC0n1 bit = 0 Set values of ES1n1 and CR00n TI00n pin input ES0n0 TI01n pin input ES1n0 (reverse phase) Position of edge to be Position of edge to be captured captured 01: Rising 01: Rising 00: Falling 00: Falling 11: Both edges 11: Both edges (cannot be captured) INTTM00n signal is not Interrupt signal Capture operation of TI00n pin input Note CR01n Interrupt signal INTTM00n signal is generated even if value generated each time is captured. value is captured. Set values of ES0n1 and ES0n0 Position of edge to be captured 01: Rising 00: Falling 11: Both edges Interrupt signal INTTM01n signal is generated each time value is captured. Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit. Caution To capture the count value of the TM0n register to the CR00n register by using the phase reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated after the value has been captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM00n signal. Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n). ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n). 2. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 276 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 Registers used to control 16-bit timer/event counters 00 and 01 are shown below. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) TMC0n is an 8-bit register that sets the 16-bit timer/event counter 0n operation mode, TM0n clear mode, and output timing, and detects an overflow. Rewriting TMC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). However, it can be changed when TMC0n3 and TMC0n2 are cleared to 00 (stopping operation) and when OVF0n is cleared to 0. TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TMC0n to 00H. Caution 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 00 (operation stop mode), respectively. Set TMC0n2 and TMC0n3 to 00 to stop the operation. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 277 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 0 0 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00). 0 1 Free-running timer mode 1 0 Clear & start mode entered by TI000 pin valid edge input 1 1 Clear & start mode entered upon a match between TM00 and CR000 TMC001 Note Condition to reverse timer output (TO00) 0 * Match between TM00 and CR000 or match between TM00 and CR010 1 * Match between TM00 and CR000 or match between TM00 and CR010 * Trigger input of TI000 pin valid edge OVF00 Clear (0) Set (1) TM00 overflow flag Clears OVF00 to 0 or TMC003 and TMC002 = 00 Overflow occurs. OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match between TM00 and CR000). It can also be set to 1 by writing 1 to OVF00. Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 278 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC01 0 0 0 0 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 0 0 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 01 operation. Stops supplying operating clock. Clears 16-bit timer counter 01 (TM01). 0 1 Free-running timer mode 1 0 Clear & start mode entered by TI001 pin valid edge input 1 1 Clear & start mode entered upon a match between TM01 and CR001 TMC011 Note Condition to reverse timer output (TO01) 0 * Match between TM01 and CR001 or match between TM01 and CR011 1 * Match between TM01 and CR001 or match between TM01 and CR011 * Trigger input of TI001 pin valid edge OVF01 Clear (0) Set (1) TM01 overflow flag Clears OVF01 to 0 or TMC013 and TMC012 = 00 Overflow occurs. OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match between TM01 and CR001). It can also be set to 1 by writing 1 to OVF01. Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 279 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CRC0n to 00H. Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC001 CR000 capture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00. If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot be detected. CRC000 CR000 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and CR000), be sure to set CRC000 to 0. Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 280 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock N-3 TM0n N-2 N-1 N N+1 TI00n Rising edge detection CR01n N INTTM01n Figure 7-10. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC01 0 0 0 0 0 CRC012 CRC011 CRC010 CRC012 CR011 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC011 CR001 capture trigger selection 0 Captures on valid edge of TI011 pin 1 Captures on valid edge of TI001 pin by reverse phase Note The valid edge of the TI011 and TI001 pin is set by PRM01. If ES011 and ES010 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI001 pin cannot be detected. CRC010 CR001 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and CR001), be sure to set CRC010 to 0. Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the INTTM001 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see Figure 7-9 Example of CR01n Capture Operation (When Rising Edge Is Specified)). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 281 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation. However, TOC0n4 can be rewritten during timer operation as a means to rewrite CR01n (see 7.5.1 Rewriting CR01n during TM0n operation). TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TOC0n to 00H. Caution Be sure to set TOC0n using the following procedure. <1> Set TOC0n4 and TOC0n1 to 1. <2> Set only TOE0n to 1. <3> Set either of LVS0n or LVR0n to 1. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 282 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software 0 - 1 One-shot pulse output The value of this bit is always "0" when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode. If it is set to 1, TM00 is cleared and started. OSPE00 One-shot pulse output operation control 0 Successive pulse output 1 One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI000 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and CR000. TOC004 TO00 output control on match between CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM010) is generated even when TOC004 = 0. LVS00 LVR00 Setting of TO00 output status 0 0 No change 0 1 Initial value of TO00 output is low level (TO00 output is cleared to 0). 1 0 Initial value of TO00 output is high level (TO00 output is set to 1). 1 1 Setting prohibited * LVS00 and LVR00 can be used to set the initial value of the TO00 output level. If the initial value does not have to be set, leave LVS00 and LVR00 as 00. * Be sure to set LVS00 and LVR00 when TOE00 = 1. LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited. * LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the TO00 output level can be set. Even if these bits are cleared to 0, TO00 output is not affected. * The values of LVS00 and LVR00 are always 0 when they are read. * For how to set LVS00 and LVR00, see 7.5.2 Setting LVS0n and LVR0n. * The actual TO00/TI010/P01 pin output is determined depending on PM01 and P01, besides TO00 output. TOC001 TO00 output control on match between CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM000) is generated even when TOC001 = 0. TOE00 TO00 output control 0 Disables output (TO00 output fixed to low level) 1 Enables output R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 283 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC01 0 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger via software 0 - 1 One-shot pulse output The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot pulse output mode. If it is set to 1, TM01 is cleared and started. OSPE01 One-shot pulse output operation control 0 Successive pulse output 1 One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI001 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and CR001. TOC014 TO01 output control on match between CR011 and TM01 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM011) is generated even when TOC014 = 0. LVS01 LVR01 Setting of TO01 output status 0 0 No change 0 1 Initial value of TO01 output is low level (TO01 output is cleared to 0). 1 0 Initial value of TO01 output is high level (TO01 output is set to 1). 1 1 Setting prohibited * LVS01 and LVR01 can be used to set the initial value of the TO01 output level. If the initial value does not have to be set, leave LVS01 and LVR01 as 00. * Be sure to set LVS01 and LVR01 when TOE01 = 1. LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited. * LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the TO01 output level can be set. Even if these bits are cleared to 0, TO01 output is not affected. * The values of LVS01 and LVR01 are always 0 when they are read. * For how to set LVS01 and LVR01, see 7.5.2 Setting LVS0n and LVR0n. * The actual TO01/TI011/P06 pin output is determined depending on PM06 and P06, besides TO01 output. TOC011 TO01 output control on match between CR001 and TM01 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM001) is generated even when TOC011 = 0. TOE01 TO01 output control 0 Disables output (TO01 output is fixed to low level) 1 Enables output R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 284 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PRM0n to 00H. Cautions 1. Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11 (to specify the valid edge of the TI00n pin as a count clock). * Clear & start mode entered by the TI00n pin valid edge * Setting the TI00n pin as a capture trigger 2. If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 285 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES101 ES100 ES001 ES000 0 0 PRM001 PRM000 ES101 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES001 ES000 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 TI010 pin valid edge selection TI000 pin valid edge selection Note 1 Count clock selection fPRS = 2 MHz 0 0 fPRS 0 1 fPRS/2 fPRS/2 1 1 Notes 1. Note 2 0 1 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz Note 3 2 MHz 5 MHz 10 MHz 20 MHz 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 8 7.81 kHz 19.53 kHz 39.06 kHz 78.12 kHz TI000 valid edge Notes 4, 5 The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), 3. This is settable only if 4.0 V VDD 5.5 V. when 1.8 V VDD < 2.7 V, the setting of PRM001 = PRM000 = 0 (count clock: fPRS) is prohibited. 4. The external clock from the TI000 pin requires a pulse longer than twice the cycle of the peripheral hardware clock (fPRS). 5. Do not start timer operation with the external clock from the TI000 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 286 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-14. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM01 ES111 ES110 ES011 ES010 0 0 PRM011 PRM010 ES111 ES110 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES011 ES010 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM011 PRM010 TI011 pin valid edge selection TI001 pin valid edge selection Note 1 Count clock selection fPRS = 2 MHz 0 0 fPRS 0 1 fPRS/2 fPRS/2 1 1 Notes 1. Note 2 0 1 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz Note 3 2 MHz 5 MHz 10 MHz 20 MHz 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz 6 31.25 kHz 78.125 kHz 156.25 kHz 312.5 kHz TI001 valid edge Notes 4, 5 The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of PRM011 = PRM010 = 0 (count clock: fPRS) is prohibited. 3. This is settable only if 4.0 V VDD 5.5 V. 4. The external clock from the TI001 pin requires a pulse longer than twice the cycle of the peripheral 5. Do not start timer operation with the external clock from the TI001 pin when the internal high-speed hardware clock (fPRS). oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 287 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latches of P01 and P06 to 0. When using the P00/TI000, P01/TO00/TI010, P05/TI001/SSI11, and P06/TO01/TI011 pins for timer input, set PM00, PM01, PM05, and PM06 to 1. At this time, the output latches of P00, P01, P05, and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM0 to FFH. Figure 7-15. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH Symbol 7 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) Remark 6 5 4 R/W 3 2 0 Output mode (output buffer on) 1 Input mode (output buffer off) 1 0 The figure shown above presents the format of port mode register 0 of 78K0/KF2 products. For the format of port mode register 0 of other products, see (1) Port mode registers (PMxx) in 5.3 Registers Controlling Port Function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 288 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal (INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-16. Block Diagram of Interval Timer Operation Clear Count clock 16-bit counter (TM0n) Match signal INTTM00n signal Operable bits TMC0n3, TMC0n2 CR00n register Figure 7-17. Basic Timing Example of Interval Timer Operation N N N N Interval (N + 1) Interval (N + 1) TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) N Compare match interrupt (INTTM00n) Interval (N + 1) Remark n = 0: Interval (N + 1) 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 289 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Interval time = (M + 1) x Count clock cycle Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 290 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Example of Software Processing for Interval Timer Function N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 CR00n register N INTTM00n signal <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 291 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 Square-wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H. When TMC0n3 and TMC0n2 are set to 11 (count clear & start mode entered upon a match between TM0n and CR00n), the counting operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H, an interrupt signal (INTTM00n) is generated, and TO0n output is inverted. This TO0n output that is inverted at fixed intervals enables TO0n to output a square wave. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-20. Block Diagram of Square-Wave Output Operation Clear Count clock Output controller 16-bit counter (TM0n) Match signal TO0n output TO0n pin INTTM00n signal Operable bits TMC0n3, TMC0n2 CR00n register Figure 7-21. Basic Timing Example of Square-Wave Output Operation N N N N Interval (N + 1) Interval (N + 1) TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) N TO0n output Compare match interrupt (INTTM00n) Interval (N + 1) Remark n = 0: Interval (N + 1) 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 292 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-22. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 OVF0n 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n output. Inverts TO0n output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Square wave frequency = 1 / [2 x (M + 1) x Count clock cycle] Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the square-wave output function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 293 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Example of Software Processing for Square-Wave Output Function N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 00 N CR00n register TO0n output INTTM00n signal TO0n output control bit (TOC0n1, TOE0n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 294 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 External event counter operation When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM0n and CR00n (INTTM00n) is generated. To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an external event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and TMC0n2 = 10). The INTTM00n signal is generated with the following timing. * Timing of generation of INTTM00n signal (second time or later) = Number of times of detection of valid edge of external event x (Set value of CR00n + 1) However, the first match interrupt immediately after the timer/event counter has started operating is generated with the following timing. * Timing of generation of INTTM00n signal (first time only) = Number of times of detection of valid edge of external event input x (Set value of CR00n + 2) To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of fPRS. The valid edge is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-24. Block Diagram of External Event Counter Operation fPRS Clear TI00n pin Edge detection 16-bit counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Output controller TO0n output TO0n pin INTTM00n signal CR00n register Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 295 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-25. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 0/1 0/1 0: Disables TO0n output 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0/1 0/1 0 0 PRM0n1 PRM0n0 1 1 Selects count clock (specifies valid edge of TI00n). 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 296 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-25. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interrupt signal (INTTM00n) is generated when the number of external events reaches (M + 1). Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used in the external event counter mode. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 297 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Example of Software Processing in External Event Counter Mode N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) 00 N TO0n output Compare match interrupt (INTTM00n) TO0n output control bits (TOC0n4, TOC0n1, TOE0n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 298 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear & start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected, TM0n overflows and continues counting. The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after the start of the operation. CR00n and CR01n are used as compare registers and capture registers. (a) When CR00n and CR01n are used as compare registers Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and CR01n. (b) When CR00n and CR01n are used as capture registers The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin). When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to 0000H. <R> Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n may be cleared. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. (1) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: compare register) Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) TI00n pin Edge detection Clear Count clock Timer counter (TM0n) Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller TO0n output TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 299 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H M TM0n register N M N M N M N 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) M Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n output (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 0AH M TM0n register N M N M N M N 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) M N Compare match interrupt (INTTM01n) TO0n output (a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n (TMC0n). (a) The TO0n output level is inverted when TM0n matches a compare register. (b) The TO0n output level is inverted when TM0n matches a compare register or when the valid edge of the TI00n pin is detected. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 300 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: capture register) Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) Edge detector TI00n pin Clear Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Capture signal Output controller TO0n output TO0n pin Interrupt signal (INTTM01n) Capture register (CR01n) Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H M N P TM0n register Q S 0000H Operable bits (TMC0n3, TMC0n2) 10 00 Capture & count clear input (TI00n pin input) Compare register (CR00n) 0001H Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n output This is an application example where the TO0n output level is inverted when the count value has been captured & cleared. The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated, and the TO0n output level is inverted. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 301 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H M N P TM0n register Q S 0003H 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Capture & count clear input (TI00n pin input) Compare register (CR00n) 0003H Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n output 4 4 4 4 This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to 0000H), and the TO0n output level is inverted when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n) is generated and the TO0n output level is inverted. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 302 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Operation in clear & start mode by entered TI00n pin valid edge input (CR00n: capture register, CR01n: compare register) Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) TI00n pin Edge detection Clear Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM01n) Operable bits TMC0n3, TMC0n2 Compare register (CR01n) Capture signal Remark n = 0: Capture register (CR00n) Output controller TO0n output TO0n pin Interrupt signal (INTTM00n) 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 303 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H TM0n register M P N 0000H Operable bits (TMC0n3, TMC0n2) S 00 10 Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) 0000H M N S P L Compare register (CR01n) 0001H Compare match interrupt (INTTM01n) TO0n output This is an application example where the TO0n output level is to be inverted when the count value has been captured & cleared. TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge detection of the TI00n pin. When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 304 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H TM0n register M 0003H 0000H Operable bits (TMC0n3, TMC0n2) S P N 00 10 Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) 0000H M N S P L Compare register (CR01n) 0003H Compare match interrupt (INTTM01n) TO0n output 4 4 4 4 This is an application example where the width set to CR01n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. TM0n is cleared (to 0000H) at the rising edge detection of the TI00n pin and captured to CR00n at the falling edge detection of the TI00n pin. The TO0n output level is inverted when TM0n is cleared (to 0000H) because the rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a compare register (CR01n). When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the input signal of the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n interrupt is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 305 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: capture register, CR01n: capture register) Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Clear Timer counter (TM0n) Count clock Capture register (CR01n) Capture signal Interrupt signal (INTTM01n) TI00n pin Edge detection TI01n pinNote Edge detection Selector TO0n output Output controller Capture register (CR00n) Capture signal TO0n pinNote Interrupt signal (INTTM00n) Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (1/3) (a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH L TM0n register N M O Q P R S T 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) 0000H L Capture register (CR01n) 0000H L M N O P Q R S T Capture interrupt (INTTM01n) TO0n output This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n output is inverted when the rising or falling edge of the TI00n pin is detected. When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n signal when it is not used. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 306 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (2/3) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH FFFFH N M 00 T Q S P 0000H Operable bits (TMC0n3, TMC0n2) R O L TM0n register 10 Capture trigger input (TI01n pin input) Capture register (CR00n) 0000H L M N O P Q R S T Capture interrupt (INTTM00n) Capture & count clear input (TI00n) L Capture register (CR01n) Capture interrupt (INTTM01n) 0000H L This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is captured to CR00n when the rising or falling edge of the TI01n pin is detected. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 307 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (3/3) (c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH O M TM0n register N L Q W T R P 0000H Operable bits (TMC0n3, TMC0n2) S 10 00 Capture & count clear input (TI00n pin input) Capture register (CR00n) 0000H Capture register (CR01n) L 0000H N M P O R Q T S W Capture interrupt (INTTM01n) Capture input (TI01n) L Capture interrupt (INTTM00n) L This is an application example where the pulse width of the signal input to the TI00n pin is measured. By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the TI00n pin (i.e., rising edge) and to CR01n at the falling edge of the TI00n pin. The high- and low-level widths of the input pulse can be calculated by the following expressions. * High-level width = [CR01n value] - [CR00n value] x [Count clock cycle] * Low-level width = [CR00n value] x [Count clock cycle] If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the INTTM01n signal is generated. However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the pulse width of the TI00n pin, mask the INTTM00n signal when it is not used. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 308 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 0 OVF0n 0/1 0 0: Inverts TO0n output on match between TM0n and CR00n/CR01n. 1: Inverts TO0n output on match between TM0n and CR00n/CR01n and valid edge of TI00n pin. Clears and starts at valid edge input of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 0/1 0/1 0: Disables TO0n outputNote 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 309 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pinNote input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. Note The timer output (TO0n) cannot be used when detection of the valid edge of the TI01n pin is used. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 310 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input M TM0n register M N M N M N N 0000H Operable bits (TMC0n3, TMC0n2) 00 00 10 Count clear input (TI00n pin input) Compare register (CR00n) M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n output <1> <2> <1> Count operation start flow <2> <2> <2> <3> <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, TMC0n.TMC0n1 bit, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 10. TMC0n3, TMC0n2 bits = 10 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP <2> TM0n register clear & start flow Edge input to TI00n pin When the valid edge is input to the TI00n pin, the value of the TM0n register is cleared. Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 311 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Free-running timer operation When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (free-running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to 0000H) and continues counting. Clear OVF0n to 0 by executing the CLR instruction via software. The following three types of free-running timer operations are available. * Both CR00n and CR01n are used as compare registers. * One of CR00n or CR01n is used as a compare register and the other is used as a capture register. * Both CR00n and CR01n are used as capture registers. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. (1) Free-running timer mode operation (CR00n: compare register, CR01n: compare register) Figure 7-37. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) Timer counter (TM0n) Count clock Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Interrupt signal (INTTM00n) TO0n output Output controller TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 312 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) * TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H FFFFH N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 Compare register (CR00n) M N M N M N M 01 00 M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n output OVF0n bit 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where two compare registers are used in the free-running timer mode. The TO0n output level is reversed each time the count value of TM0n matches the set value of CR00n or CR01n. When the count value matches the register value, the INTTM00n or INTTM01n signal is generated. (2) Free-running timer mode operation (CR00n: compare register, CR01n: capture register) Figure 7-39. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) Timer counter (TM0n) Count clock Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) TI00n pin Remark n = 0: Edge detection Capture signal Capture register (CR01n) Interrupt signal (INTTM00n) Output TO0n output controller TO0n pin Interrupt signal (INTTM01n) 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 313 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-40. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) * TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H FFFFH M N TM0n register P S Q 0000H Operable bits (TMC0n3, TMC0n2) 00 01 Capture trigger input (TI00n) Compare register (CR00n) 0000H Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n output Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where a compare register and a capture register are used at the same time in the freerunning timer mode. In this example, the INTTM00n signal is generated and the TO0n output level is reversed each time the count value of TM0n matches the set value of CR00n (compare register). In addition, the INTTM01n signal is generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is detected. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 314 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Free-running timer mode operation (CR00n: capture register, CR01n: capture register) Figure 7-41. Block Diagram of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock TI00n pin Edge detection TI01n pin Edge detection Selector Capture signal Capture signal Capture register (CR01n) Capture register (CR00n) Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the TO0n output level is not inverted. However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1) of 16bit timer mode control register 0n (TMC0n) is set to 1. 2. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 315 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 50H, CRC0n = 05H, TMC0n = 04H FFFFH M N TM0n register A 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C B Q D E 01 Capture trigger input (TI00n) Capture register (CR01n) 0000H M N S Q P Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H A B C E D Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate capture registers in the free-running timer mode. The count value is captured to CR01n when the valid edge of the TI00n pin input is detected and to CR00n when the valid edge of the TI01n pin input is detected. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 316 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H FFFFH O L 00 T Q M 0000H Operable bits (TMC0n3, TMC0n2) R N TM0n register S P 01 Capture trigger input (TI01n) Capture register (CR00n) 0000H L M N O P Q R S T Capture interrupt (INTTM00n) Capture trigger input (TI00n) L Capture register (CR01n) Capture interrupt (INTTM01n) 0000H L This is an application example where both the edges of the TI01n pin are detected and the count value is captured to CR00n in the free-running timer mode. When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to be detected, the count value cannot be captured to CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 317 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0 1 0/1 OVF0n 0 0: Inverts TO0n output on match between TM0n and CR00n/CR01n. 1: Inverts TO0n output on match between TM0n and CR00n/CR01n valid edge of TI00n pin. Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 0/1 0/1 0: Disables TO0n output 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 318 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pin input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 319 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-44. Example of Software Processing in Free-Running Timer Mode FFFFH M M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N N 00 M N N 00 01 Compare register (CR00n) M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n output <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n/CR01n register, TMC0n.TMC0n1 bit, port setting TMC0n3, TMC0n2 bits = 0, 1 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 01. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 0, 0 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 320 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 PPG output operation A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows. * Pulse cycle = (Set value of CR00n + 1) x Count clock cycle * Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1) Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during TM0n operation. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-45. Block Diagram of PPG Output Operation Clear Timer counter (TM0n) Count clock Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Interrupt signal (INTTM00n) TO0n output Output controller TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 321 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-46. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n output Specifies initial value of TO0n output F/F 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. 00: Disables one-shot pulse output (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 322 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-46. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is cleared. (g) 16-bit capture/compare register 01n (CR01n) An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is not cleared. Caution Set values to CR00n and CR01n such that the condition 0000H CR01n < CR00n FFFFH is satisfied. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 323 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-47. Example of Software Processing for PPG Output Operation M TM0n register M N N M N 0000H Operable bits (TMC0n3, TMC0n2) 00 00 11 Compare register (CR00n) M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n output N+1 M+1 N+1 M+1 N+1 M+1 <2> <1> <2> Count operation stop flow <1> Count operation start flow TMC0n3, TMC0n2 bits = 00 START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. TMC0n3, TMC0n2 bits = 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remarks 1. PPG pulse cycle = (M + 1) x Count clock cycle PPG duty = (N + 1)/(M + 1) 2. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 324 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register 0n (TMC0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI00n pin valid edge) and setting bit 5 (OSPE0n) of 16-bit timer output control register 0n (TOC0n) to 1. When bit 6 (OSPT0n) of TOC0n is set to 1 or when the valid edge is input to the TI00n pin during timer operation, clearing & starting of TM0n is triggered, and a pulse of the difference between the values of CR00n and CR01n is output only once from the TO0n pin. Cautions 1. Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. 2. To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do not change the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be unexpectedly output. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-48. Block Diagram of One-Shot Pulse Output Operation TI00n edge detection OSPT0n bit Clear OSPE0n bit Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Interrupt signal (INTTM00n) TO0n output Output controller TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 325 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0/1 1 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n output Specifies initial value of TO0n output Inverts TO0n output on match between TM0n and CR00n/CR01n. Enables one-shot pulse output Software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 326 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR00n, an interrupt signal (INTTM00n) is generated and the TO0n output level is inverted. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR01n, an interrupt signal (INTTM01n) is generated and the TO0n output level is inverted. Caution Do not set the same value to CR00n and CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 327 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH N N M TM0n register N M M 0000H Operable bits (TMC0n3, TMC0n2) 00 01 or 10 00 One-shot pulse enable bit (OSPE0n) One-shot pulse trigger bit (OSPT0n) One-shot pulse trigger input (TI00n pin) Overflow plug (OVF0n) Compare register (CR00n) N Compare match interrupt (INTTM00n) Compare register (CR01n) M Compare match interrupt (INTTM01n) TO0n output M+1 TO0n output control bits (TOE0n, TOC0n4, TOC0n1) <1> <2> N-M M+1 N-M TO0n output level is not inverted because no oneshot trigger is input. <2> <3> * Time from when the one-shot pulse trigger is input until the one-shot pulse is output = (M + 1) x Count clock cycle * One-shot pulse output active level width = (N - M) x Count clock cycle Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,] 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 328 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting TMC0n3, TMC0n2 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. Starts count operation <2> One-shot trigger input flow TOC0n.OSPT0n bit = 1 or edge input to TI00n pin Write the same value to the bits other than the OSTP0n bit. <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 329 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.8 Pulse width measurement operation TM0n can be used to measure the pulse width of the signal input to the TI00n and TI01n pins. Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI00n pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n). If it is set (to 1), clear it to 0 by software. Figure 7-51. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock TI00n pin Edge detection TI01n pin Edge detection Selector Capture signal Capture signal Capture register (CR01n) Capture register (CR00n) Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) Figure 7-52. Block Diagram of Pulse Width Measurement (Clear & Start Mode Entered by TI00n Pin Valid Edge Input) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock Edge detection Edge detection TI01n pin Remark n = 0: Selector Capture signal TI00n pin Clear Capture signal Capture register (CR01n) Capture register (CR00n) Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 330 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 A pulse width can be measured in the following three ways. * Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. (1) Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. When the valid edge of the TI01n pin is detected, the count value of TM0n is captured to CR00n. Specify detection of both the edges of the TI00n and TI01n pins. By this measurement method, the previous count value is subtracted from the count value captured by the edge of each input signal. Therefore, save the previously captured value to a separate register in advance. If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the current captured value and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-53. Timing Example of Pulse Width Measurement (1) * TMC0n = 04H, PRM0n = F0H, CRC0n = 05H FFFFH M TM0n register N A 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C B Q D E 01 Capture trigger input (TI00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H A B C E D Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear Remark n = 0: 0 write clear 0 write clear 0 write clear 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 331 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge detected on the TI00n pin. When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. By this measurement method, values are stored in separate capture registers when a width from one edge to another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one capture register from that of another, a high-level width, low-level width, and cycle are calculated. If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-54. Timing Example of Pulse Width Measurement (2) * TMC0n = 04H, PRM0n = 10H, CRC0n = 07H FFFFH M TM0n register N A 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C B Q D E 01 Capture trigger input (TI00n) Capture register (CR00n) 0000H Capture register (CR01n) 0000H A B M C N E D S Q P Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) L Capture interrupt (INTTM00n) L Remark n = 0: 0 write clear 0 write clear 0 write clear 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 332 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore, a cycle is stored in CR01n if TM0n does not overflow. If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle. Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-55. Timing Example of Pulse Width Measurement (3) * TMC0n = 08H, PRM0n = 10H, CRC0n = 07H FFFFH TM0n register N C D S A 0000H Operable bits 00 (TMC0n3, TMC0n2) Q P B M 10 00 <1> <1> <1> <1> Capture & count clear input (TI00n) <2> Capture register (CR00n) 0000H Capture register (CR01n) 0000H <3> <2> <3> A M <2> <3> B N <2> <3> C S D P Q Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) L Capture interrupt (INTTM00n) L <1> (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR01n) x Count Pulse cycle = clock cycle <2> High-level pulse width = (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR00n) x Count clock cycle <3> Low-level pulse width = (Pulse cycle - High-level pulse width) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 333 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 1 0/1 1 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting valid edge of TI00n is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection (setting when CRC0n1 = 1 is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 334 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a capture register. Either the TI00n or TI01n pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a capture register. The signal input to the TI00n pin is used as a capture trigger. When the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 335 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH D10 TM0n register D11 D00 D13 D12 D01 D02 D03 D04 0000H Operable bits (TMC0n3, TMC0n2) 00 01 00 Capture trigger input (TI00n) Capture register (CR01n) D10 0000H D11 D12 D13 Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H D00 D01 D02 D03 D04 Capture interrupt (INTTM00n) <1> <2> <2> <2> <2> <2> <2> <2> <2> <2><3> (b) Example of clear & start mode entered by TI00n pin valid edge FFFFH D3 D2 D5 D0 TM0n register D8 D6 D7 D4 D1 0000H Operable bits (TMC0n3, TMC0n2) 00 10 00 Capture & count clear input (TI00n) Capture register 0000H (CR00n) Capture interrupt (INTTM00n) D3 D1 D5 D7 L Capture register (CR01n) 0000H D2 D0 D4 D6 D8 Capture interrupt (INTTM01n) <1> Remark n = 0: <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 336 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, port setting TMC0n3, TMC0n2 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. Starts count operation <2> Capture trigger input flow Edge detection of TI00n, TI01n pins Stores count value to CR00n, CR01n registers Generates capture interruptNote Calculated pulse width from capture value <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note The capture interrupt signal (INTTM00n) is not generated when the reverse-phase edge of the TI00n pin input is selected to the valid edge of CR00n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 337 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/Kx2 microcontrollers when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00). However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if CR01n is used for PPG output and the duty factor is changed. (When changing the value of CR01n to a smaller value than the current one, rewrite it immediately after its value matches the value of TM0n. When changing the value of CR01n to a larger value than the current one, rewrite it immediately after the values of CR00n and TM0n match. If the value of CR01n is rewritten immediately before a match between CR01n and TM0n, or between CR00n and TM0n, an unexpected operation may be performed.). Procedure for changing value of CR01n <1> Disable interrupt INTTM01n (TMMK01n = 1). <2> Disable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 0). <3> Change the value of CR01n. <4> Wait for one cycle of the count clock of TM0n. <5> Enable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 1). <6> Clear the interrupt flag of INTTM01n (TMIF01n = 0) to 0. <7> Enable interrupt INTTM01n (TMMK01n = 0). Remark For TMIF01n and TMMK01n, see CHAPTER 20 INTERRUPT FUNCTIONS. 7.5.2 Setting LVS0n and LVR0n (1) Usage of LVS0n and LVR0n LVS0n and LVR0n are used to set the default value of the TO0n output and to invert the timer output without enabling the timer operation (TMC0n3 and TMC0n2 = 00). Clear LVS0n and LVR0n to 00 (default value: low-level output) when software control is unnecessary. Remark n = 0: LVS0n LVR0n Timer Output Status 0 0 Not changed (low-level output) 0 1 Cleared (low-level output) 1 0 Set (high-level output) 1 1 Setting prohibited 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 338 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-58. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n bit Setting TOC0n.LVS0n, LVR0n bits Setting TMC0n.TMC0n3, TMC0n2 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Figure 7-59. Timing Example of LVR0n and LVS0n TOC0n.LVS0n bit TOC0n.LVR0n bit Operable bits (TMC0n3, TMC0n2) 00 01, 10, or 11 TO0n output INTTM00n signal <1> <2> <1> <3> <4> <4> <4> <1> The TO0n output goes high when LVS0n and LVR0n = 10. <2> The TO0n output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the high level even if LVS0n and LVR0n are cleared to 00). <3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and LVR0n were set to 10 before the operation was started, the TO0n output starts from the high level. After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00 (disabling the timer operation). <4> The TO0n output level is inverted each time an interrupt signal (INTTM00n) is generated. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 339 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-3 shows the restrictions for each channel. Table 7-3. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation Restriction - As interval timer As square-wave output As external event counter As clear & start mode entered by Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is TI00n pin valid edge input used. (TOC0n = 00H) - As free-running timer As PPG output 0000H CP01n < CR00n FFFFH As one-shot pulse output Setting the same value to CR00n and CP01n is prohibited. As pulse width measurement Using timer output (TO0n) is prohibited (TOC0n = 00H) (2) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. Figure 7-60. Start Timing of TM0n Count Count pulse TM0n count value 0000H 0001H 0002H 0003H 0004H Timer start (3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n) Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external event counter). Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 340 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n pin is detected). When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated. Figure 7-61. Timing of Holding Data by Capture Register Count pulse TM0n count value N N+1 N+2 M M+1 M+2 Edge input INTTM01n Capture read signal Value captured to CR01n X Capture operation N+1 Capture operation is performed but read value is not guaranteed. (b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops. (5) Setting valid edge Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1. (6) Re-triggering one-shot pulse Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 341 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H Figure 7-62. Operation Timing of OVF0n Flag Count pulse CR00n FFFFH TM0n FFFEH FFFFH 0000H 0001H OVF0n INTTM00n (b) Clearing OVF0n flag Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. (8) One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 342 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly. (b) Pulse width to accurately capture value by signals input to TI01n and TI00n pins To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 7-9). (c) Generation of interrupt signal The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9). (d) Note when CRC0n1 (bit 1 of capture/compare control register 0n (CRC0n)) is set to 1 When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal when the external interrupt is not used. (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. (b) Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge of TI00n is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM0n is used for sampling. When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9). (11) Timer operation The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. Remarks 1. fPRS: Peripheral hardware clock frequency 2. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 343 78K0/Kx2 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (12) Reading of 16-bit timer counter 0n (TM0n) TM0n can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. Figure 7-63. 16-bit Timer Counter 0n (TM0n) Read Timing Count clock TM0n count value 0034H Read buffer 0034H 0035H 0036H 0035H 0037H 0037H 0038H 0039H 003AH 0038H 003BH 003BH Read signal Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 344 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 are mounted onto all 78K0/Kx2 microcontroller products. 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n) Timer input TI5n Timer output TO5n Control registers Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 345 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Selector Match Selector INTTM50 Note 1 S Q INV 8-bit timer OVF counter 50 (TM50) Selector TI50/TO50/P17 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/28 fPRS/213 Mask circuit 8-bit timer compare register 50 (CR50) R To TMH0 To UART0 To UART6 TO50 output TO50/TI50/ P17 Output latch (P17) Note 2 S 3 Invert level R Clear PM17 TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500 8-bit timer mode control register 50 (TMC50) Timer clock selection register 50 (TCL50) Internal bus Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Selector INTTM51 Note 1 S Q INV 8-bit timer OVF counter 51 (TM51) R Selector Match Selector TI51/TO51/ P33/INTP4 fPRS fPRS/2 fPRS/24 fPRS/26 fPRS/28 fPRS/212 Mask circuit 8-bit timer compare register 51 (CR51) Note 2 S 3 Clear TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) R Invert level TO51 output TO51/TI51/ P33/INTP4 Output latch (P33) PM33 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. Timer output F/F 2. PWM output F/F R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 346 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) After reset: 00H R Symbol TM5n (n = 0, 1) In the following situations, the count value is cleared to 00H. <1> Reset signal generation <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In the PWM mode, TO5n output becomes inactive when the values of TM5n and CR5n match, but no interrupt is generated. The value of CR5n can be set within 00H to FFH. Reset signal generation clears CR5n to 00H. Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) After reset: 00H R/W Symbol CR5n (n = 0, 1) Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 347 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TCL5n to 00H. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 348 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 0 0 fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz TI50 pin falling edge 0 0 1 TI50 pin rising edge 0 1 0 fPRS 0 1 1 fPRS/2 1 1 1 1 Notes 1. 0 Note 1 Count clock selection 0 0 1 1 0 1 0 1 Note 3 Note 2 Note 2 2 MHz 5 MHz 10 MHz 20 MHz Note 4 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/2 8 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz fPRS/2 13 0.24 kHz 0.61 kHz 1.22 kHz 2.44 kHz The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. Do not start timer operation with the external clock from the TI50 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. 3. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), 4. This is settable only if 4.0 V VDD 5.5 V. when 1.8 V VDD < 2.7 V, the setting of TCL502, TCL501, TCL500 = 0, 1, 0 (count clock: fPRS) is prohibited. Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to "0". Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 349 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL51 0 0 0 0 0 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 0 0 fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz TI51 pin falling edge 0 0 1 TI51 pin rising edge 0 1 0 fPRS 0 1 1 fPRS/2 1 1 1 1 Notes 1. 0 Note 1 Count clock selection 0 0 1 1 0 1 0 1 Note 3 Note 2 Note 2 2 MHz 5 MHz 10 MHz 20 MHz Note 4 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/2 8 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz fPRS/2 12 0.49 kHz 1.22 kHz 2.44 kHz 4.88 kHz The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. Do not start timer operation with the external clock from the TI51 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. 3. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), 4. This is settable only if 4.0 V VDD 5.5 V. when 1.8 V VDD < 2.7 V, the setting of TCL512, TCL511, TCL510 = 0, 1, 0 (count clock: fPRS) is prohibited. Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to "0". Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 350 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH After reset: 00H R/W Note Symbol <7> 6 5 4 <3> <2> 1 <0> TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear & start occurs on a match between TM50 and CR50 1 PWM (free-running) mode LVS50 LVR50 0 0 No change 0 1 Timer output F/F clear (0) (default value of TO50 output: low level) 1 0 Timer output F/F set (1) (default value of TO50 output: high level) 1 1 Setting prohibited TMC501 Timer output F/F status setting In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE50 Timer output control 0 Output disabled (TO50 output is low level) 1 Output enabled Note Bits 2 and 3 are write-only. (Cautions and Remarks are listed on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 351 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H R/W Note Symbol <7> 6 5 4 <3> <2> 1 <0> TMC51 TCE51 TMC516 0 0 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC516 TM51 operating mode selection 0 Mode in which clear & start occurs on a match between TM51 and CR51 1 PWM (free-running) mode LVS51 LVR51 0 0 No change 0 1 Timer output F/F clear (0) (default value of TO51 output: low) 1 0 Timer output F/F set (1) (default value of TO51 output: high) 1 1 Setting prohibited TMC511 Timer output F/F status setting In other modes (TMC516 = 0) In PWM mode (TMC516 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE51 Timer output control 0 Output disabled (TO51 output is low level) 1 Output enabled Note Bits 2 and 3 are write-only. Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n 3. When TCE5n = 1, setting the other bits of TMC5n is prohibited. 4. The actual TO50/TI50/P17 and TO51/TI51/P33/INTP4 pin outputs are determined depending on PM17 and P17, and PM33 and P33, besides TO5n output. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n output regardless of the value of TCE5n. 4. n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 352 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 8-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 8-10. Format of Port Mode Register 3 (PM3) Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 PM33 PM32 PM31 PM30 PM3n P3n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 353 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Set TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 2. n = 0, 1 Figure 8-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H Count start CR5n N N 00H 01H Clear N 00H 01H N Clear N N N TCE5n INTTM5n Interrupt acknowledged Interval time Remark Interrupt acknowledged Interval time Interval time = (N + 1) x t N = 01H to FFH n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 354 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H 00H 00H CR5n 00H 00H TCE5n INTTM5n Interval time (c) When CR5n = FFH t Count clock TM5n CR5n 01H FFH FEH FFH 00H FEH FFH FFH 00H FFH TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 355 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n pin input edge. TI5n pin falling edge TCL5n = 00H TI5n pin rising edge TCL5n = 01H * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 00000000B) <2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 8-bit timer/event counter 51: PM33 Remark For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value 00H 01H CR5n 02H 03H 04H 05H N-1 N 00H 01H 02H 03H N INTTM5n Remark N = 00H to FFH n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 356 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. LVS5n LVR5n Timer Output F/F Status Setting 0 1 Timer output F/F clear (0) (default value of TO5n output: low level) 1 0 Timer output F/F set (1) (default value of TO5n output: high level) Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. * Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 2. n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 357 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 8.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 358 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select PWM mode. The timer output F/F is not changed. TMC5n1 Active Level Selection 0 Active-high 1 Active-low Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation <1> PWM output (TO5n output) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 8-14 and 8-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 359 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n 00H 01H CR5n N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n <2> Active level <1> Inactive level <3> Inactive level <5> Inactive level <2> Active level (b) CR5n = 00H t Count clock TM5n 00H 01H CR5n 00H FFH 00H 01H 02H FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n L (Inactive level) (c) CR5n = FFH t TM5n 00H 01H CR5n FFH FFH 00H 01H 02H FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n <1> Inactive level <2> Active level <2> Active level <5> Inactive level <3> Inactive level Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) and (c) correspond to <1> to <3> and <5> in PWM output operation in 8.4.4 (1) PWM output basic operation. 2. n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 360 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n N N+1 N+2 CR5n N TCE5n INTTM5n FFH 00H 01H 02H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 M H TO5n <2> <1> CR5n change (N M) (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock TM5n N N+1 N+2 CR5n TCE5n INTTM5n N FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H N M M+1 M+2 M H TO5n <1> CR5n change (N M) <2> Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 361 78K0/Kx2 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 8-16. 8-Bit Timer Counter 5n (TM5n) Start Timing Count clock TM5n count value 00H 01H 02H 03H 04H Timer start (2) Reading of 8-bit timer counter 5n (TM5n) TM5n can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. Figure 8-17. 8-bit Timer Counter 5n (TM5n) Read Timing Count clock TM5n count value 34H Read buffer 34H 35H 36H 35H 37H 37H 38H 39H 38H 3AH 3BH 3BH Read signal Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 362 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 are mounted onto all 78K0/Kx2 microcontroller products. 8-bit timers H0 and H1 have the following functions. * Interval timer * Square-wave output * PWM output * Carrier generator (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1 Item Configuration Timer register 8-bit timer counter Hn Registers 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Timer output TOHn, output controller Control registers 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register 1 (TMCYC1) Note Port mode register 1 (PM1) Port register 1 (P1) Note 8-bit timer H1 only Remark n = 0, 1 Figures 9-1 and 9-2 show the block diagrams. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 363 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 3 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) 2 TOH0 output Decoder TOH0/P15 Selector fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/210 8-bit timer/ event counter 50 output Selector Match Interrupt generator F/F R Output controller Level inversion Output latch (P15) PM15 8-bit timer counter H0 Clear PWM mode signal 1 0 INTTMH0 364 CHAPTER 9 8-BIT TIMERS H0 AND H1 Timer H enable signal 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 0 1 (CMP01) 8-bit timer H compare register 1 1 (CMP11) 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) INTTM51 Reload/ interrupt control 2 TOH1 output TOH1/ INTP5/ P16 Decoder Selector Selector Match fPRS fPRS/22 fPRS/24 fPRS/26 fPRS/212 fRL fRL/27 fRL/29 Interrupt generator F/F R Output controller Level inversion Output latch (P16) PM16 8-bit timer counter H1 Carrier generator mode signal Clear PWM mode signal 1 0 INTTMH1 365 CHAPTER 9 8-BIT TIMERS H0 AND H1 Timer H enable signal 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn. Rewrite the value of CMP0n while the timer is stopped (TMHEn = 0). A reset signal generation clears this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 6 5 After reset: 00H 3 4 R/W 2 1 0 Caution CMP0n cannot be rewritten during timer count operation. CMP0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8-bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request signal is generated. In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn). At the same time, the count value is cleared. CMP1n can be refreshed (the same value is written) and rewritten during timer count operation. If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the value of CMP1n is not changed. A reset signal generation clears this register to 00H. Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 After reset: 00H 4 3 R/W 2 1 0 Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 366 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1)Note * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 367 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H TMHMD0 After reset: 00H R/W <7> 6 5 4 TMHE0 CKS02 CKS01 CKS00 TMHE0 3 <1> <0> TOEN0 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) CKS01 CKS02 Count clock selectionNote 1 CKS00 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 5 MHz 10 MHz 20 MHzNote 3 1 MHz 2.5 MHz 5 MHz 10 MHz 1.25 MHz 2.5 MHz 0 0 0 fPRSNote 2 2 MHz 0 0 1 fPRS/2 0 1 0 fPRS/2 500 kHz 0 1 1 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 0 0 1 1 0 1 Other than above 2 10 fPRS/2 4.88 kHz 9.77 kHz 19.54 kHz TM50 output Setting prohibited Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above 1.95 kHz 5 MHz Note 4 TMMD01 TMMD00 Setting prohibited TOLEV0 Timer output level control (in default mode) 0 Low level 1 High level TOEN0 Notes 1. 2 TMMD01 TMMD00 TOLEV0 Timer output control 0 Disables output 1 Enables output The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 368 78K0/Kx2 Notes 2. CHAPTER 9 8-BIT TIMERS H0 AND H1 If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of CKS02 = CKS01 = CKS00 = 0 (count clock: fPRS) is prohibited. 3. This is settable only if 4.0 V VDD 5.5 V. 4. Note the following points when selecting the TM50 output as the count clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable (TOE50 = 1) TO50 output in any mode. Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). 3. The actual TOH0/P15 pin output is determined depending on PM15 and P15, besides TOH0 output. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 369 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 2 <1> <0> TOEN1 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) CKS12 CKS11 Count clock selectionNote 1 CKS10 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 10 MHz 20 MHzNote 3 0 0 0 fPRSNote 2 2 MHz 5 MHz 0 0 1 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz 0 1 0 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz 1 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 12 0.49 kHz 1.22 kHz 0 1 1 0 fPRS/2 0 fPRS/2 7 1 0 1 fRL/2 1.88 kHz (TYP.) 1 1 0 fRL/29 0.47 kHz (TYP.) 1 1 1 fRL 240 kHz (TYP.) TMMD11 TMMD10 2.44 kHz 4.88 kHz Timer operation mode 0 0 Interval timer mode 0 1 Carrier generator mode 1 0 PWM output mode 1 1 Setting prohibited TOLEV1 Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Notes 1. 3 TMMD11 TMMD10 TOLEV1 Timer output control 0 Disables output 1 Enables output The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 370 78K0/Kx2 Notes 2. CHAPTER 9 8-BIT TIMERS H0 AND H1 If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of CKS12 = CKS11 = CKS10 = 0 (count clock: fPRS) is prohibited. 3. This is settable only if 4.0 V VDD 5.5 V. Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. 4. The actual TOH1/INTP5/P16 pin output is determined depending on PM16 and P16, besides TOH1 output. Remarks 1. fPRS: Peripheral hardware clock frequency 2. fRL: Internal low-speed oscillation clock frequency (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FF6DH After reset: 00H R/WNote <0> TMCYC1 0 0 RMC1 NRZB1 0 0 Low-level output 0 1 High-level output at rising edge of INTTM51 signal input 1 0 Low-level output 1 1 Carrier pulse output at rising edge of INTTM51 signal input NRZ1 0 0 0 RMC1 NRZB1 NRZ1 Remote control output Carrier pulse output status flag 0 Carrier output disabled status (low-level status) 1 Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) Note Bit 0 is read-only. Caution Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same value is written). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 371 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 9-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 372 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. Setting <1> Set each register. Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMHMDn TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Default setting of timer output level Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting The interval time is as follows if N is set as a comparison value. * Interval time = (N +1)/fCNT <2> Count operation starts when TMHEn = 1. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and the 8-bit timer counter Hn is cleared to 00H. <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMHn signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 3. n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 373 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H CMP0n FEH) Count clock Count start 8-bit timer counter Hn 00H 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP0n TMHEn INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at the rising edge of the count clock. <3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level is maintained. Remark n = 0, 1 01H N FEH R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 374 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 375 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. PWM output (TOHn output) outputs an active level and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. PWM output (TOHn output) outputs an inactive level when 8-bit timer counter Hn and the CMP1n register match. Setting <1> Set each register. Figure 9-11. Register Setting in PWM Output Mode (i) TMHMDn Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 Timer output enabled Default setting of timer output level PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and an active level is output. At the same time, the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. <4> When the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output and the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 376 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. * PWM pulse output cycle = (N + 1)/fCNT * Duty = (M + 1)/(N + 1) Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating. However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed until the value is transferred to the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). 3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 3. n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 377 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H CMP0n A5H CMP1n 01H A5H 00H 01H 02H A5H 00H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <2> <3> <4> TOHn (TOLEVn = 1) <1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, PWM output outputs an inactive level. <2> When the values of the 8-bit timer counter Hn and the CMP0n register match, an active level is output. At this time, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM output to an inactive level. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 378 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP0n FFH CMP1n 00H FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP0n FFH CMP1n FEH FEH FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 379 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 380 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H (03H) 02H CMP11 <2> 03H <2>' TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, PWM output outputs an inactive level. <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer counter Hn is cleared, an active level is output, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, an inactive level is output. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM output to an inactive level. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 381 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, the 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and the 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during the 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of the 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. RMC1 Bit NRZB1 Bit Output 0 0 Low-level output 0 1 High-level output at rising edge of INTTM51 signal input 1 0 Low-level output 1 1 Carrier pulse output at rising edge of INTTM51 signal input R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 382 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 9-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 1 0 <2> NRZB1 1 0 1 <3> RMC1 <1> The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the INTTM5H1 signal. <2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. <3> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. Remark INTTM5H1 is an internal signal and not an interrupt source. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 383 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Setting <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode (i) TMHMD1 Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 0 1 0/1 TOEN1 1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... carrier output enable bit (v) TCL51 and TMC51 register setting * See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, the 8-bit timer H1 starts counting. <3> When TCE51 of the 8-bit timer mode control register 51 (TMC51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of the 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of the 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. <9> When the NRZ1 bit is high level, a carrier clock is output by TOH1 output. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 384 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. * Carrier clock output cycle = (N + M + 2)/fCNT * Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. 3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 4. The set value of the CMP11 register can be changed while the timer counter is operating. However, it takes the duration of three operating clocks (signal selected by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11 register has been changed until the value is transferred to the register. 5. Be sure to set the RMC1 bit before the count operation is started. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 385 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H N 00H N 00H N 00H CMP01 N CMP11 N N 00H N 00H N TMHE11 INTTMH1 <3> <4> <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value 00H 01H K 00H 01H L K CR51 00H 01H M 00H 01H L N 00H 01H N M TCE51 <5> INTTM51 INTTM5H1 NRZB1 0 1 0 1 0 <6> NRZ1 0 1 0 1 0 Carrier clock TOH1 <7> <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. Remark INTTM5H1 is an internal signal and not an interrupt source. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 386 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H N 00H 01H M 00H N 00H 01H CMP01 N CMP11 M M 00H N 00H TMHE1 INTTMH1 <3> <4> <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value 00H 01H K 00H 01H L 00H 01H K CR51 M 00H 01H N 00H 01H M L N TCE51 <5> INTTM51 INTTM5H1 NRZB1 NRZ1 0 1 0 0 1 1 0 0 1 0 Carrier clock <6> TOH1 <7> <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). Remark INTTM5H1 is an internal signal and not an interrupt source. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 387 78K0/Kx2 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>' M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default. <2> When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. <3> The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the CMP11 register is changed (<3>'). However, it takes three count clocks or more since the value of the CMP11 register has been changed until the value is transferred to the register. Even if a match signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. <5> The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 388 78K0/Kx2 CHAPTER 10 WATCH TIMER CHAPTER 10 WATCH TIMER 78K0/KB2 78K0/KC2 78K0/KD2 - Watch timer 78K0/KE2 78K0/KF2 Remark : Mounted, -: Not mounted 10.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Clear Selector fPRS/27 fWX/24 5-bit counter fWX/25 INTWT Clear fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Selector fSUB 11-bit prescaler fW fWX Selector Selector Figure 10-1. Block Diagram of Watch Timer WTM7 WTM6 WTM5 INTWTI WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) fWX: fW or fW/29 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 389 78K0/Kx2 CHAPTER 10 WATCH TIMER (1) Watch timer When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at fSUB = 32.768 kHz fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 4 488 s 1.02 ms 410 s 205 s 102 s 5 977 s 2.05 ms 819 s 410 s 205 s 13 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 14 0.5 s 1.05 s 0.419 s 0.210 s 0.105 s 2 /fW 2 /fW 2 /fW 2 /fW Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) (2) Interval timer Interrupt request signals (INTWTI) are generated at preset time intervals. Table 10-2. Interval Timer Interval Time Interval Time When Operated at When Operated at When Operated at When Operated at When Operated at fSUB = 32.768 kHz fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 4 488 s 1.02 ms 410 s 205 s 102 s 5 977 s 2.05 ms 820 s 410 s 205 s 6 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 7 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 8 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 9 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 10 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 11 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 390 78K0/Kx2 CHAPTER 10 WATCH TIMER 10.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 10-3. Watch Timer Configuration Item Configuration Counter 5 bits x 1 Prescaler 11 bits x 1 Control register Watch timer operation mode register (WTM) 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears WTM to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 391 78K0/Kx2 CHAPTER 10 WATCH TIMER Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH Symbol WTM After reset: 00H R/W 7 6 5 4 3 2 <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Note WTM7 Watch timer count clock selection (fW) fSUB = 32.768 kHz 0 fPRS/2 1 fSUB WTM6 - 7 fPRS = 2 MHz 15.625 kHz fPRS = 5 MHz 39.062 kHz fPRS = 20 MHz 78.125 kHz 156.25 kHz - 32.768 kHz WTM5 fPRS = 10 MHz WTM4 Prescaler interval time selection 4 0 0 0 2 /fW 0 0 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW 1 1 0 2 /fW 1 1 1 2 /fW WTM3 WTM2 5 6 7 8 9 10 11 Selection of watch timer interrupt time 14 0 0 2 /fW 0 1 2 /fW 1 0 2 /fW 1 1 2 /fW 13 5 4 WTM1 5-bit counter operation control 0 Clear after operation stop 1 Start WTM0 Watch timer operation enable 0 Operation stop (clear both prescaler and 5-bit counter) 1 Operation enable Note The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 392 78K0/Kx2 Caution CHAPTER 10 WATCH TIMER Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. 7 Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 393 78K0/Kx2 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 29 x 1/fW seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 10-4. Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at Selection 0 0 0 1 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz (WTM7 = 1) (WTM7 = 0) (WTM7 = 0) (WTM7 = 0) (WTM7 = 0) 14 0.5 s 1.05 s 0.419 s 0.210 s 0.105 s 13 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 5 977 s 2.05 ms 819 s 410 s 205 s 4 488 s 1.02 ms 410 s 205 s 102 s 2 /fW 2 /fW 1 0 2 /fW 1 1 2 /fW Remarks 1. fW: fSUB = 32.768 kHz 7 Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation stops. Table 10-5. Interval Timer Interval Time WTM6 WTM5 WTM4 Interval Time at fPRS = 5 MHz at fPRS = 10 MHz at fPRS = 20 MHz (WTM7 = 0) (WTM7 = 0) (WTM7 = 0) 1.02 ms 410 s 205 s 102 s 977 s 2.05 ms 820 s 410 s 205 s 6 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 7 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 8 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 9 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 10 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 11 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms 2 /fW 1 2 /fW 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW 1 1 0 2 /fW 1 1 1 2 /fW Remarks 1. fW: (WTM7 = 0) 488 s 0 0 0 at fPRS = 2 MHz 5 0 0 1 at fSUB = 32.768 kHz (WTM7 = 1) 4 0 0 When Operated When Operated When Operated When Operated When Operated 7 Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 394 78K0/Kx2 CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Overflow Start Overflow Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Remark T fW: Watch timer clock frequency Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 395 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer is mounted onto all 78K0/Kx2 microcontroller products. The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If data is written to WDTE during a window close period * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while the CPU hangs up) * If the CPU accesses an area that is not set by the IMS and IXS registers (excluding FB00H to FFCFH and FFE0H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 23 RESET FUNCTION. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 396 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Option Byte (0080H) Window open period Bits 6 and 5 (WINDOW1, WINDOW0) Controlling counter operation of watchdog timer Bit 4 (WDTON) Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0) Remark For the option byte, see CHAPTER 26 OPTION BYTE. Figure 11-1. Block Diagram of Watchdog Timer CPU access error detector CPU access signal WDCS2 to WDCS0 of option byte (0080H) fRL/2 Clock input controller 17-bit counter 210/fRL to 217/fRL Selector Count clear signal WINDOW1 and WINDOW0 of option byte (0080H) WDTON of option byte (0080H) Overflow signal Reset output controller Internal reset signal Window size determination signal Clear, reset control Watchdog timer enable register (WDTE) Internal bus R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 397 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 11-2. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H Symbol After reset: 9AH/1AHNote 7 6 R/W 5 4 3 2 1 0 WDTE Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To operate watchdog timer, set WDTON to 1. WDTON Setting Value WDTE Reset Value 0 (watchdog timer count operation disabled) 1AH 1 (watchdog timer count operation enabled) 9AH Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 398 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 26). WDTON Operation Control of Watchdog Timer Counter/Illegal Access Detection 0 Counter operation disabled (counting stopped after reset), illegal access detection operation disabled 1 Counter operation enabled (counting started after reset), illegal access detection operation enabled * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see 11.4.2 and CHAPTER 26). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for details, see 11.4.3 and CHAPTER 26). 2. After a reset release, the watchdog timer starts counting. 3. By writing "ACH" to WDTE after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is written during a window close period, an internal reset signal is generated. 5. If the overflow time expires without "ACH" written to WDTE, an internal reset signal is generated. A internal reset signal is generated in the following cases. * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check during a CPU program loop) * If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFCFH and FFE0H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. If the watchdog timer is cleared by writing "ACH" to WDTE, the actual overflow time may be different from the overflow time set by the option byte by up to 2/fRL seconds. 3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 399 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) Watchdog timer operation stops. In HALT mode Watchdog timer operation continues. In STOP mode If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops operating. At this time, the counter is not cleared to 0. 5. The watchdog timer continues its operation during self-programming and EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 11.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing "ACH" to WDTE during the window open period before the overflow time. The following overflow time is set. Table 11-3. Setting of Overflow Time of Watchdog Timer WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer 10 0 0 0 2 /fRL (3.88 ms) 0 0 1 2 /fRL (7.76 ms) 0 1 0 2 /fRL (15.52 ms) 0 1 1 2 /fRL (31.03 ms) 1 0 0 2 /fRL (62.06 ms) 1 0 1 2 /fRL (124.12 ms) 1 1 0 2 /fRL (248.24 ms) 1 1 1 2 /fRL (496.48 ms) 11 12 13 14 15 16 17 Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. The watchdog timer continues its operation during self-programming and EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. Remarks 1. fRL: Internal low-speed oscillation clock frequency 2. ( ): fRL = 264 kHz (MAX.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 400 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. * If "ACH" is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again. * Even if "ACH" is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated. Example: If the window open period is 25% Counting starts Overflow time Window close period (75%) Internal reset signal is generated if ACH is written to WDTE. Window open period (25%) Counting starts again when ACH is written to WDTE. Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. The window open period to be set is as follows. Table 11-4. Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Period of Watchdog Timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V VDD < 2.7 V. 3. The watchdog timer continues its operation during self-programming and EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 401 78K0/Kx2 CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 211/fRL, the window close time and open time are as follows. (when 2.7 V VDD 5.5 V) Setting of Window Open Period 25% 50% 75% 100% Window close time 0 to 7.11 ms 0 to 4.74 ms 0 to 2.37 ms None Window open time 7.11 to 7.76 ms 4.74 to 7.76 ms 2.37 to 7.76 ms 0 to 7.76 ms <When window open period is 25%> * Overflow time: 211/fRL (MAX.) = 211/264 kHz (MAX.) = 7.76 ms * Window close time: 0 to 211/fRL (MIN.) x (1 - 0.25) = 0 to 211/216 kHz (MIN.) x 0.75 = 0 to 7.11 ms * Window open time: 211/fRL (MIN.) x (1 - 0.25) to 211/fRL (MAX.) = 211/216 kHz (MIN.) x 0.75 to 211/264 kHz (MAX.) = 7.11 to 7.76 ms R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 402 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 78K0/KB2 Clock output 78K0/KC2 78K0/KD2 78K0/KE2 38/44 pins: - - 48 pins: - Buzzer output 78K0/KF2 Remark : Mounted, -: Not mounted 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 12-1 and 12-2 show the block diagram of clock output/buzzer output controller. Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller (78K0/KD2, 48-pin Products of 78K0/KC2) fPRS Prescaler fPRS to fPRS/27 fSUB Selector 8 Clock controller PCL/INTP6/P140 Output latch (P140) CLOE CCS3 CCS2 CCS1 PM140 CCS0 Clock output select register (CKS) Internal bus R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 403 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Block Diagram of Clock Output/Buzzer Output Controller (78K0/KE2, 78K0/KF2) fPRS Prescaler fPRS/210 to fPRS/213 4 Selector 8 BUZ/BUSY0/INTP7/P141 Output latch (P141) BZOE fSUB BCS0, BCS1 Selector fPRS to fPRS/27 Clock controller CLOE BZOE BCS1 BCS0 CLOE CCS3 CCS2 PM141 CCS1 PCL/INTP6/P140 Output latch (P140) PM140 CCS0 Clock output selection register (CKS) Internal bus 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CKS to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 404 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-3. Format of Clock Output Selection Register (CKS) (78K0/KD2, 48-pin Products of 78K0/KC2) Address: FF40H After reset: 00H R/W Symbol 7 6 5 <4> 3 2 1 0 CKS 0 0 0 CLOE CCS3 CCS2 CCS1 CCS0 CLOE PCL output enable/disable specification 0 Clock division circuit operation stopped. PCL fixed to low level. 1 Clock division circuit operation enabled. PCL output enabled. CCS3 CCS2 0 0 CCS1 0 Note 1 CCS0 0 PCL output clock selection fSUB = fPRS = fPRS = 32.768 kHz 10 MHz 20 MHz - Note 2 fPRS Setting 10 MHz Note 3 prohibited 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 5 MHz 10 MHz fPRS/2 2 2.5 MHz 5 MHz fPRS/2 3 1.25 MHz 2.5 MHz fPRS/2 4 625 kHz 1.25 MHz 0 1 0 1 fPRS/2 5 312.5 kHz 625 kHz 0 1 1 0 fPRS/2 6 156.25 kHz 312.5 kHz 7 78.125 kHz 156.25 kHz 0 1 1 1 fPRS/2 1 0 0 0 fSUB Other than above Notes 1. fPRS/2 32.768 kHz - Setting prohibited The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V VDD < 3. The PCL output clock prohibits settings if they exceed 10 MHz. 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited. Caution Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 405 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-4. Format of Clock Output Selection Register (CKS) (78K0/KE2, 78K0/KF2) Address: FF40H Symbol CKS After reset: 00H R/W <7> 6 5 <4> 3 2 1 0 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification 0 Clock division circuit operation stopped. BUZ fixed to low level. 1 Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection Note 1 fPRS = 10 MHz 0 0 0 1 1 0 1 1 fPRS/2 9.77 kHz 19.54 kHz fPRS/2 11 4.88 kHz 9.77 kHz fPRS/2 12 2.44 kHz 4.88 kHz fPRS/2 13 1.22 kHz 2.44 kHz CLOE PCL output enable/disable specification 0 Clock division circuit operation stopped. PCL fixed to low level. 1 Clock division circuit operation enabled. PCL output enabled. CCS3 fPRS = 20 MHz 10 CCS2 0 0 CCS1 0 Note 1 CCS0 0 PCL output clock selection fPRS fSUB = fPRS = fPRS = 32.768 kHz 10 MHz 20 MHz - Note 2 Setting 10 MHz prohibited 0 0 0 0 0 0 0 1 1 0 1 fPRS/2 5 MHz 10 MHz fPRS/2 2 2.5 MHz 5 MHz fPRS/2 3 1.25 MHz 2.5 MHz 0 1 0 0 fPRS/2 4 625 kHz 1.25 MHz 0 1 0 1 fPRS/2 5 312.5 kHz 625 kHz 0 1 1 0 fPRS/2 6 156.25 kHz 312.5 kHz 7 78.125 kHz 156.25 kHz 0 1 1 1 fPRS/2 1 0 0 0 fSUB Other than above Notes 1. 1 Note 3 32.768 kHz - Setting prohibited The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 406 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Notes 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (XSEL = 0) when 1.8 V VDD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited. 3. The PCL output clock prohibits settings if they exceed 10 MHz. Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). 2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUSY0/BUZ pin for buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM14 to FFH. Figure 12-5. Format of Port Mode Register 14 (PM14) Address: FF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 PM14n Remark P14n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) The figure shown above presents the format of port mode register 14 of 78K0/KF2 products. For the format of port mode register 14 of other products, see (1) Port mode registers (PMxx) in 5.3 Registers Controlling Port Function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 407 78K0/Kx2 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Operations of Clock Output/Buzzer Output Controller 12.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 12-6, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock. Figure 12-6. Remote Control Output Application Example CLOE * * Clock output 12.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 408 78K0/Kx2 CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER 78K0/KB2 10-bit A/D 78K0/KC2 38 pins: 4 ch 78K0/KD2 78K0/KE2 6 ch 78K0/KF2 8 ch 44/48 pins: 8 ch converter 13.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 13-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Voltage comparator AVSS Successive approximation register (SAR) Controller 3 ADS2 ADS1 ADS0 ADPC3 ADPC2 ADPC1 ADPC0 Analog input channel specification register (ADS) ADCS FR2 FR1 FR0 AVSS INTAD A/D conversion result register (ADCR) 5 4 Tap selector Selector Sample & hold circuit LV1 LV0 ADCE A/D converter mode register (ADM) A/D port configuration register (ADPC) Internal bus Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 409 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above (2) Sample & hold circuit The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the sampled voltage value. Figure 13-2. Circuit Configuration of Series Resistor String AVREF P-ch ADCS Series resistor string AVSS (4) Voltage comparator The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register converts the result of comparison by the voltage comparator, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 410 78K0/Kx2 CHAPTER 13 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from ADCR and ADCRH when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the VDD pin when port 2 is used as a digital port. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. (10) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. (13) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) Port mode register 2 (PM2) This register switches the ANI0/P20 to ANI7/P27 pins to input or output. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 411 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * A/D port configuration register (ADPC) * Analog input channel specification register (ADS) * Port mode register 2 (PM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-3. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM After reset: 00H R/W <7> 6 5 4 3 2 1 <0> ADCS 0 FR2Note 1 FR1Note 1 FR0Note 1 LV1Note 1 LV0Note 1 ADCE ADCS A/D conversion operation control 0 Stops conversion operation 1 Enables conversion operation Comparator operation controlNote 2 ADCE Notes 1. 0 Stops comparator operation 1 Enables comparator operation For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time Selection (Conventional-specification Products (PD78F05xx and 78F05xxD)), and Table 13-3 A/D Conversion Time Selection (Expanded-specification Products (PD78F05xxA and 78F05xxDA)). 2. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. Table 13-1. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (comparator operation, only comparator consumes power) Note 1 0 Conversion mode (comparator operation stopped 1 1 Conversion mode (comparator operation) ) Note Ignore the first conversion data. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 412 78K0/Kx2 CHAPTER 13 A/D CONVERTER Figure 13-4. Timing Chart When Comparator Is Used Comparator operation ADCE Comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 s or longer. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other than the identical data. 2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 413 78K0/Kx2 CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time Selection (Conventional-specification Products (PD78F05xx and 78F05xxD)) (1) 2.7 V AVREF 5.5 V (LV0 = 0) A/D Converter Mode Register (ADM) FR2 FR1 FR0 LV1 LV0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 Conversion Time Selection fPRS = 2 MHz fPRS = 10 MHz Conversion Clock (fAD) Note fPRS = 20 MHz 26.4 s 13.2 s fPRS/12 176/fPRS 17.6 s 8.8 s fPRS/8 132/fPRS 13.2 s Note 6.6 s fPRS/6 88/fPRS 8.8 s Setting prohibited fPRS/4 264/fPRS Setting prohibited Note Note Note 1 0 0 0 0 66/fPRS 33.0 s 6.6 s fPRS/3 1 0 1 0 0 44/fPRS 22.0 s Setting prohibited fPRS/2 Other than above Note Setting prohibited Note This can be set only when 4.0 V AVREF 5.5 V. (2) 2.3 V AVREF < 2.7 V (LV0 = 1) A/D Converter Mode Register (ADM) Conversion Time Selection FR2 FR1 FR0 LV1 LV0 0 0 0 0 1 480/fPRS 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 Conversion Clock (fAD) fPRS = 2 MHz fPRS = 5 MHz Setting prohibited Setting prohibited fPRS/12 320/fPRS 64.0 s fPRS/8 240/fPRS 48.0 s fPRS/6 1 160/fPRS 32.0 s fPRS/4 0 1 120/fPRS 60.0 s Setting prohibited fPRS/3 0 1 80/fPRS 40.0 s Setting prohibited fPRS/2 Other than above Setting prohibited Cautions 1. Set the conversion times with the following conditions. * 4.0 V AVREF 5.5 V: fAD = 0.6 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz * 2.3 V AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz (Standard products and (A) grade products only) 2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. 3. Change LV0 from the default value, when 2.3 V AVREF < 2.7 V. 4. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 414 78K0/Kx2 CHAPTER 13 A/D CONVERTER Table 13-3. A/D Conversion Time Selection (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (1) 2.7 V AVREF 5.5 V (LV0 = 0) A/D Converter Mode Register (ADM) Conversion Time Selection FR1 FR0 LV1 LV0 fPRS = 2 MHz 0 0 0 0 0 264/fPRS Setting prohibited 52.8 s 26.4 s 13.2 s fPRS/12 0 176/fPRS 35.2 s 17.6 s 8.8 s fPRS/8 0 132/fPRS 66.0 s 26.4 s 13.2 s Note 6.6 s fPRS/6 0 88/fPRS 44.0 s 17.6 s 8.8 s Setting prohibited fPRS/4 66/fPRS 33.0 s 44/fPRS 22.0 s 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 fPRS = 10 MHz Note fPRS = 20 MHz Clock (fAD) FR2 0 fPRS = 5 MHz Conversion Note 13.2 s Note 6.6 s fPRS/3 8.8 s Setting prohibited fPRS/2 Note Other than above Setting prohibited Note This can be set only when 4.0 V AVREF 5.5 V. (2) 2.3 V AVREF 5.5 V (LV0 = 1) A/D Converter Mode Register (ADM) FR2 0 FR1 0 FR0 0 LV1 0 Conversion Time Selection LV0 1 fPRS = 2 MHz fPRS = 5 MHz Conversion fPRS = fPRS = 10 MHz 20 MHz 480/fPRS Setting prohibited Setting prohibited 48.0 s Note 2 Clock (fAD) 24.0 s fPRS/12 Note 2 0 0 1 0 1 320/fPRS 64.0 s 32.0 s 16.0 s fPRS/8 0 1 0 0 1 240/fPRS 48.0 s 24.0 s 12.0 s fPRS/6 1 160/fPRS 32.0 s 16.0 s Setting prohibited fPRS/4 1 120/fPRS 60.0 s 24.0 s 12.0 s fPRS/3 1 40.0 s 16.0 s Setting prohibited fPRS/2 0 1 1 1 0 0 1 0 1 0 0 0 80/fPRS Note 2 Note 2 Note 1 Note 2 Note 1 Other than above Notes 1. This can be set only when 4.0 V AVREF 5.5 V. 2. This can be set only when 2.7 V AVREF 5.5 V. Note 1 Note 1 Note 1 Setting prohibited Cautions 1. Set the conversion times with the following conditions. (1) 2.7 V AVREF 5.5 V (LV0 = 0) * 4.0 V AVREF 5.5 V: fAD = 0.33 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.33 to 1.8 MHz (2) 2.3 V AVREF 5.5 V (LV0 = 1) * 4.0 V AVREF 5.5 V: fAD = 0.6 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz * 2.3 V AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz (Standard products and (A) grade products only) 2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. 3. Change LV0 from the default value, when 2.3 V AVREF < 2.7 V. 4. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 415 78K0/Kx2 CHAPTER 13 A/D CONVERTER Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait periodNote SAR clear Sampling Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 36 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8 bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF08H, FF09H After reset: 0000H R FF09H Symbol ADCR FF08H 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 416 78K0/Kx2 CHAPTER 13 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-7. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF09H Symbol 7 After reset: 00H 6 R 5 4 3 2 1 0 ADCRH Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 417 78K0/Kx2 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above Figure 13-8. Format of Analog Input Channel Specification Register (ADS) Address: FF29H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 ADS2 ADS1 ADS0 KB2 ADS2 ADS1 ADS0 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 Products 38-pin other than products the right of KC2 Analog input channel specification Note 1 Note 1 Note 1 Note 2 Note 2 Notes 1. Setting permitted 2. Setting prohibited Cautions 1. Be sure to clear bits 3 to 7 to "0". 2 Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 3. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 418 78K0/Kx2 CHAPTER 13 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above Figure 13-9. Format of A/D Port Configuration Register (ADPC) Address: FF2FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Products 38-pin other than products the right of KC2 KB2 Note 1 Note 1 Note 1 Digital I/O (D)/analog input (A) switching P27/ P26/ P25/ P24/ P23/ P22/ P21/ P20/ ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 0 0 0 0 A A A A A A A A 0 0 0 1 A A A A A A A D 0 0 1 0 A A A A A A D D 0 0 1 1 A A A A A D D D 0 1 0 0 A A A A D D D D 0 1 0 1 A A A D D D D D 0 1 1 0 A A D D D D D D 0 1 1 1 A D D D D D D D 1 0 0 0 D D D D D D D D Note 2 Note 2 Other than above Notes 1. Setting permitted 2. Setting prohibited Setting prohibited Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 419 78K0/Kx2 CHAPTER 13 A/D CONVERTER (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of P20 to P27 at this time may be 0 or 1. If PM20 to PM27 are set to 0, they cannot be used as analog input port pins. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above Figure 13-10. Format of Port Mode Register 2 (PM2) Address: FF22H Symbol PM2 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2n P2n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". Remark The format of port mode register 2 of 78K0/KB2 products is different from the above format. See 5.3 Registers Controlling Port Function (1) Port mode registers (PMxx). ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of ADPC, ADS, and PM2. Table 13-4. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC Analog input selection PM2 Input mode Output mode ADS ANI0/P20 to ANI7/P27 Pins Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Digital I/O selection R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Input mode - Digital input Output mode - Digital output 420 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 2 (PM2). <3> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select one channel for A/D conversion using the analog input channel specification register (ADS). <5> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1. (<6> to <12> are operations performed by hardware.) <6> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <7> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <8> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <9> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <10> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <11> Comparison is continued in this way up to bit 0 of SAR. <12> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <13> Repeat steps <6> to <12>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <5>. To start A/D conversion again when ADCE = 0, set ADCE to 1, wait for 1 s or longer, and start <5>. To change a channel of A/D conversion, start from <4>. Caution Make sure the period of <1> to <5> is 1 s or more. Remark Two types of A/D conversion result registers are available. * ADCR (16 bits): Store 10-bit A/D conversion value * ADCRH (8 bits): Store 8-bit A/D conversion value R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 421 78K0/Kx2 CHAPTER 13 A/D CONVERTER Figure 13-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined Conversion result ADCR INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or ( ADCR 64 - 0.5) x where, INT( ): AVREF 1024 VAIN < ( ADCR 64 + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: A/D conversion result register (ADCR) value SAR: Successive approximation register Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 422 78K0/Kx2 CHAPTER 13 A/D CONVERTER Figure 13-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-12. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 423 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been completed, the next A/D conversion operation is immediately started. If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result immediately before is retained. Figure 13-13. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result immediately before is retained ADCR, ADCRH ANIn ANIn Stopped Conversion result immediately before is retained ANIm INTAD Remarks 1. 78K0/KB2: n = 0 to 3, 38-pin products of the 78K0/KC2: n = 0 to 5, other products: n = 0 to 7 2. 78K0/KB2: m = 0 to 3, 38-pin products of the 78K0/KC2: m = 0 to 5, other products: m = 0 to 7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 424 78K0/Kx2 CHAPTER 13 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2). <3> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select a channel to be used by using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS). <5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <6> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Change the channel> <8> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS to start A/D conversion. <9> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <10> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Complete A/D conversion> <11> Clear ADCS to 0. <12> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <5> is 1 s or more. 2. <1> may be done between <2> and <4>. 3. <1> can be omitted. However, ignore data of the first conversion after <5> in this case. 4. The period from <6> to <9> differs from the conversion time set using bits 5 to 1 (FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time set using FR2 to FR0, LV1, and LV0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 425 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-14. Overall Error Figure 13-15. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 Analog input 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 426 78K0/Kx2 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-16. Zero-Scale Error Figure 13-17. Full-Scale Error Full-scale error Ideal line 011 010 001 Zero-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 13-18. Integral Linearity Error Figure 13-19. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Integral linearity error 0......0 0 Analog input Differential linearity error 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Conversion time 427 78K0/Kx2 CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by instruction upon the end of conversion ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or ADCRH. <2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 13-20 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 428 78K0/Kx2 CHAPTER 13 A/D CONVERTER Figure 13-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI7 C = 100 to 1,000 pF AVSS VSS (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as I/O port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 13-20). (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Remark ANI0 to ANI3: 78K0/KB2 ANI0 to ANI5: 38-pin products of the 78K0/KC2 ANI0 to ANI7: Products other than above R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 429 78K0/Kx2 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the prechange analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-21. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ADCR, ADCRH ANIn ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF Remarks 1. 78K0/KB2: n = 0 to 3, 38-pin products of the 78K0/KC2: n = 0 to 5, other products: n = 0 to 7 2. 78K0/KB2: m = 0 to 3, 38-pin products of the 78K0/KC2: m = 0 to 5, other products: m = 0 to 7 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 430 78K0/Kx2 CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 13-5. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF R1 C1 C2 4.0 V AVREF 5.5 V 8.1 k 8 pF 5 pF 2.7 V AVREF < 4.0 V 31 k 8 pF 5 pF 2.3 V AVREF < 2.7 V 381 k 8 pF 5 pF Remarks 1. The resistance and capacitance values shown in Table 13-5 are not guaranteed values. 2. 78K0/KB2: n = 0 to 3, 38-pin products of the 78K0/KC2: n = 0 to 5, other products: n = 0 to 7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 431 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 are mounted onto all 78K0/Kx2 microcontroller products. Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 14.4.2 Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate generator. * Maximum transfer rate: 625 kbps * Two-pin configuration TXD0: Transmit data output pin RXD0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full-duplex operation). * Fixed to LSB-first communication Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 432 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Registers Configuration Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 433 78K0/Kx2 Filter RXD0/ SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial interface operation mode register 0 (ASIM0) fPRS/2 fPRS/23 fPRS/25 Selector R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 14-1. Block Diagram of Serial Interface UART0 Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator INTSR0 Reception control Receive buffer register 0 (RXB0) INTST0 Transmission control Transmit shift register 0 (TXS0) Reception unit fXCLK0 Internal bus 8-bit timer/ event counter 50 output Baud rate generator control register 0 (BRGC0) 7 Baud rate generator 7 TXD0/ SCK10/P10 Output latch (P10) PM10 Registers Transmission unit CHAPTER 14 SERIAL INTERFACE UART0 434 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation and POWER0 = 0 set this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH. Cautions 1. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 2. Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 435 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Note 2 . Enables operation of the internal operation clock. TXE0 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission. RXE0 Notes 1. 2. Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 436 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL0 Reception operation Note Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL0 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission, clear TXE0 to 0, and then clear POWER0 to 0. 2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear RXE0 to 0, and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 8. Be sure to set bit 0 to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 437 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H. 00H is read when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0) to clear the error flag. Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS0 0 0 0 0 0 PE0 FE0 OVE0 PE0 Status flag indicating parity error 0 If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read. 1 If the parity of transmit data does not match the parity bit on completion of reception. FE0 Status flag indicating framing error 0 If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read. 1 If the stop bit is not detected on completion of reception. OVE0 Status flag indicating overrun error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If receive data is set to the RXB0 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 438 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH. Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol 7 6 5 4 3 2 1 0 BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00 TPS01 TPS00 0 0 TM50 output 0 1 fPRS/2 Base clock (fXCLK0) selection fPRS = 2 MHz 1 Note 1. 0 fPRS = 5 MHz Note 1 fPRS = 10 MHz fPRS = 20 MHz Note 2 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz 1 1 MDL04 MDL03 MDL02 MDL01 MDL00 k 0 0 x x x x Setting prohibited 0 1 0 0 0 8 fXCLK0/8 0 1 0 0 1 9 fXCLK0/9 0 1 0 1 0 10 fXCLK0/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 0 1 0 26 fXCLK0/26 1 1 0 1 1 27 fXCLK0/27 1 1 1 0 0 28 fXCLK0/28 1 1 1 0 1 29 fXCLK0/29 1 1 1 1 0 30 fXCLK0/30 1 1 1 1 1 31 fXCLK0/31 Selection of 5-bit counter output clock * * * * * The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 439 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 Note 2. Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable (TOE50 = 1) TO50 output in any mode. Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the TPS01 and TPS00 bits. 3. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fPRS: Peripheral hardware clock frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4. x: Don't care 5. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 14-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 440 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE0 0 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Notes 1. 2. Enables/disables reception Disables reception (synchronously resets the reception circuit). The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 5 PORT FUNCTIONS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 441 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 14-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER0 0 1 TXE0 0 0 RXE0 PM10 0 x Note 1 x Note P10 x Note x Note 1 0 0 1 1 1 0 1 PM11 x Note x Note P11 x Note x Note x 1 1 x UART0 Pin Function Operation TxD0/SCK10/P10 RxD0/SI10/P11 Stop SCK10/P10 SI10/P11 Reception SCK10/P10 RxD0 Transmission TxD0 SI10/P11 Transmission/ TxD0 RxD0 reception Note Can be set as port function or serial interface CSI10. Remark x: don't care POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 PM1x: Port mode register P1x: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 442 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity bit D7 Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 D1 D2 D3 D4 D5 D6 D7 Stop 443 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 444 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 14-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST0 2. Stop bit length: 2 TXD0 (output) Stop INTST0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 445 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception. INTSR0 occurs upon completion of reception and in case of a reception error. Figure 14-9. Reception Completion Interrupt Request Timing RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 446 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt (INTSR0) servicing (see Figure 14-3). The contents of ASIS0 are cleared to 0 when ASIS0 is read. Table 14-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-10. Noise Filter Circuit Base clock RXD0/SI10/P11 In Q Internal signal A Match detector R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 In Q Internal signal B LD_EN 447 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 14-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fPRS/2 POWER0, TXE0 (or RXE0) fPRS/23 Selector 5-bit counter fXCLK0 5 PRS/2 f 8-bit timer/ event counter 50 output Match detector BRGC0: TPS01, TPS00 Remark 1/2 Baud rate BRGC0: MDL04 to MDL00 POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 BRGC0: Baud rate generator control register 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 448 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit counter. 14.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. * Baud rate = fXCLK0 2xk [bps] fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) Table 14-4. Set Value of TPS01 and TPS00 TPS01 TPS00 Base clock (fXCLK0) selection fPRS = 2 MHz 0 0 TM50 output 0 1 fPRS/2 1 0 1 1 fPRS = 5 MHz Note 1 fPRS = 10 MHz fPRS = 20 MHz Note 2 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz Notes 1. The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage 4.0 V VDD 5.5 V Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable (TOE50 = 1) TO50 output in any mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 449 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (2) Error of baud rate The baud rate error can be calculated by the following expression. Actual baud rate (baud rate with error) * Error (%) = Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78,125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] (3) Example of setting baud rate Table 14-5. Set Data of Baud Rate Generator Baud fPRS = 2.0 MHz Rate TPS01, [bps] TPS00 4800 2H 9600 k fPRS = 5.0 MHz Calculated ERR TPS01, Value [%] TPS00 26 4808 0.16 3H 2H 13 9615 0.16 10400 2H 12 10417 19200 1H 26 24000 1H 31250 1H k fPRS = 10.0 MHz Calculated ERR TPS01, Value [%] TPS00 16 4883 1.73 - 3H 8 9766 1.73 0.16 2H 30 10417 19231 0.16 2H 16 21 23810 -0.79 2H 16 31250 0 k fPRS = 20.0 MHz Calculated ERR TPS01, Value [%] TPS00 - - - - 3H 16 9766 1.73 0.16 3H 15 10417 19531 1.73 3H 8 13 24038 0.16 2H 2H 10 31250 0 k Calculated ERR Value [%] - - - - - - - 0.16 3H 30 10417 0.16 19531 1.73 3H 16 19531 1.73 26 24038 0.16 3H 13 24038 0.16 2H 20 31250 0 3H 10 31250 0 33600 1H 15 33333 -0.79 2H 9 34722 3.34 2H 19 32895 -2.1 3H 9 34722 3.34 38400 1H 13 38462 0.16 2H 8 39063 1.73 2H 16 39063 1.73 3H 8 39063 1.73 56000 1H 9 55556 -0.79 1H 22 56818 1.46 2H 11 56818 1.46 2H 22 56818 1.46 62500 1H 8 62500 0 1H 20 62500 0 2H 10 62500 0 2H 20 62500 0 76800 - - - - 1H 16 78125 1.73 2H 8 78125 1.73 2H 16 78125 1.73 115200 - - - - 1H 11 113636 -1.36 1H 22 113636 -1.36 2H 11 113636 -1.36 153600 - - - - 1H 8 156250 1.73 1H 16 156250 1.73 2H 8 156250 1.73 312500 - - - - - - - - 1H 8 312500 0 1H 16 312500 0 625000 - - - - - - - - - - - - 1H 8 625000 0 Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) k: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) fPRS: Peripheral hardware clock frequency ERR: Baud rate error R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 450 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: Set value of BRGC0 FL: 1-bit data length Margin of latch timing: 2 clocks R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 451 78K0/Kx2 CHAPTER 14 SERIAL INTERFACE UART0 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 x FLmax = 11 x FL - 11 FLmax = 21k - 2 k+2 2xk x FL = 21k - 2 2xk FL FL x 11 20k Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 14-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 16 +4.14% -4.19% 24 +4.34% -4.38% 31 +4.44% -4.47% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 452 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 are mounted onto all 78K0/Kx2 microcontroller products. Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 15.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 15.4.2 Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate generator. * Maximum transfer rate: 625 kbps * Two-pin configuration TXD6: Transmit data output pin RXD6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full duplex operation). * MSB- or LSB-first communication selectable * Inverted transmission operation * Sync break field transmission from 13 to 20 bits * More than 11 bits can be identified for sync break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is used in LIN communication operation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 453 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-1 and 15-2 outline the transmission and reception operations of LIN. Figure 15-1. LIN Transmission Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field LIN Bus 8 bits Note 1 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 (output) INTST6Note 3 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 15.4.2 (2) (h) SBF transmission). 3. Remark INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 454 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field 13-bit SBF reception SF reception ID reception Data reception Data reception LIN Bus <5> <2> RXD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows. <1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. <2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. <3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter 00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field (see 7.4.8 Pulse width measurement operation). Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. <4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). <5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. Figure 15-3 shows the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 455 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Selector Figure 15-3. Port Configuration for LIN Reception Operation P14/RxD6 RXD6 input Port mode (PM14) Port mode (PM120) Selector Output latch (P120) P00/TI000 Port mode (PM00) Output latch (P00) Remark Selector P120/INTP0/EXLVI INTP0 input Port input switch control (ISC0) <ISC0> 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector Selector Output latch (P14) TI000 input Port input switch control (ISC1) <ISC1> 0: Select TI000 (P00) 1: Select RxD6 (P14) ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11) The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the sync field (SF) length and divides it by the number of bits. * Serial interface UART6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 456 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Registers Configuration Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 457 78K0/Kx2 TI000, INTP0Note Filter INTSR6 fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) fXCLK6 Baud rate generator RXD6/ P14 Reception control INTSRE6 Selector R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 15-4. Block Diagram of Serial Interface UART6 Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) Transmission control Transmit shift register 6 (TXS6) Reception unit Internal bus Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) Baud rate generator 8 INTST6 TXD6/ P13 Registers Note Selectable with input switch control register (ISC). PM13 458 CHAPTER 15 SERIAL INTERFACE UART6 Output latch (P13) Transmission unit 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6) of ASIM6 are 1). 3. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 459 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 . Enables operation of the internal operation clock TXE6 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission RXE6 Notes 1. Note 2 Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception If POWER6 = 0 is set while transmitting data, the output of the TxD6 pin will be fixed to high level (if TXDLV6 = 0). Furthermore, the input from the RxD6 pin will be fixed to high level. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 460 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL6 Reception operation Note Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL6 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 ISRM6 Enables/disables occurrence of reception completion interrupt in case of error 0 "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). 1 "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission, clear TXE6 to 0, and then clear POWER6 to 0. 2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 7. Fix the PS61 and PS60 bits to 0 when used in LIN communication operation. 8. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 461 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer register 6 (RXB6) to clear the error flag. Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read 1 If receive data is set to the RXB6 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. For the stop bit of the receive data, only the first stop bit is checked regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 462 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 6 (TXE6) of ASIM6 to 0 clears this register to 00H. Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 TXBF6 Transmit buffer data flag 0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) 1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 463 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Note 2 0 0 0 0 fPRS 0 0 0 1 fPRS/2 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Note 1 fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz Note 3 2 MHz 5 MHz 10 MHz 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 4 125 kHz 312.5 kHz 625 kHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/2 7 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz 1.25 MHz 1 0 0 0 fPRS/2 8 1 0 0 1 fPRS/2 9 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz fPRS/2 10 1.953 kHz 4.88 kHz 9.77 kHz 1 0 1 0 1 0 1 1 Other than above Notes 1. Base clock (fXCLK6) selection TM50 output 19.53 kHz Note 4 Setting prohibited The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: fPRS) is prohibited. 3. This is settable only if 4.0 V VDD 5.5 V. 4. Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable (TOE50 = 1) TO50 output in any mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 464 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8-bit counter 0 0 0 0 0 0 x x x Setting prohibited 0 0 0 0 0 1 0 0 4 fXCLK6/4 0 0 0 0 0 1 0 1 5 fXCLK6/5 0 0 0 0 0 1 1 0 6 fXCLK6/6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 0 252 fXCLK6/252 1 1 1 1 1 1 0 1 253 fXCLK6/253 1 1 1 1 1 1 1 0 254 fXCLK6/254 1 1 1 1 1 1 1 1 255 fXCLK6/255 * Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255) 3. x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 465 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF reception or SBF transmission. Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) Address: FF58H After reset: 16H R/W Note Symbol <7> <6> 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger 0 - 1 SBF reception trigger SBTT6 SBF transmission trigger 0 - 1 SBF transmission trigger Note Bit 7 is read-only. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 466 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length. 1 0 0 SBF is output with 20-bit length. DIR6 First-bit specification 0 MSB 1 LSB TXDLV6 Enables/disables inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF6 flag is held (1). 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. 6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during transmission. 7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. 8. When the TXDLV6 bit is set to 1 (inverted TxD6 output), the TxD6/SCLA0/P60 pin cannot be used as a general-purpose port, regardless of the settings of POWER6 and TXE6. When using the TxD6/SCLA0/P60 pin as a general-purpose port, clear the TXDLV6 bit to 0 (normal TxD6 output). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 467 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the P14/RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 15-11. Format of Input Switch Control Register (ISC) Address: FF4FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 (P00) 1 RXD6 (P14) ISC0 INTP0 input source selection 0 INTP0 (P120) 1 RXD6 (P14) (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TXD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/RXD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 15-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 468 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit TXE6 0 Notes 1. . Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Note 2 Enables/disables reception Disables reception (synchronously resets the reception circuit). If POWER6 = 0 is set while transmitting data, the output of the TxD6 pin will be fixed to high level (if TXDLV6 = 0). Furthermore, the input from the RxD6 pin will be fixed to high level. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation. To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1. Remark To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 5 PORT FUNCTIONS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 469 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 15-8). <2> Set the BRGC6 register (see Figure 15-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 P13 0 0 0 x Note x Note 1 0 1 x Note x Note 1 0 0 1 1 1 0 1 PM14 x Note P14 x x 1 x Note 1 Note x Note x UART6 Operation TXD6/P13 Pin Function Stop P13 P14 Reception P13 RXD6 RXD6/P14 Transmission TXD6 P14 Transmission/ reception TXD6 RXD6 Note Can be set as port function. Remark x: don't care POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 PM1x: Port mode register P1x: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 470 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 471 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 D1 D2 D3 D4 D5 D6 D7 Stop 472 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 473 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the transmit data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 15-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) Stop INTST6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 474 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is use in LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 Transmission Status 0 Transmission is completed. 1 Transmission is in progress. Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, the next transmission may complete before execution of INTST6 interrupt servicing after transmission of one data frame. As a countermeasure, detection can be performed by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 475 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6. Transmission completion interrupt occurs? No Yes Transfer executed necessary number of times? Yes No Read ASIF6 TXSF6 = 0? No Yes Yes of Completion transmission processing Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 476 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 477 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission TXD6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop INTST6 TXB6 Data (n - 1) TXS6 Data (n) Data (n - 1) Data (n) FF TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) TXE6: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Bit 6 of asynchronous serial interface operation mode register (ASIM6) 478 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 15-19. Reception Completion Interrupt Request Timing RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 479 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt (INTSR6/INTSRE6) servicing (see Figure 15-6). The contents of ASIS6 are cleared to 0 when ASIS6 is read. Table 15-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 15-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 480 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 15-21. Noise Filter Circuit Base clock RXD6/P14 In Internal signal A Q In Internal signal B Q LD_EN Match detector (h) SBF transmission When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 15-1 LIN Transmission Operation. When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered, and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) to 1. Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6), or until SBTT6 is set to 1. Figure 15-22. SBF Transmission TXD6 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6 SBTT6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 481 78K0/Kx2 (i) CHAPTER 15 SERIAL INTERFACE UART6 SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 15-23. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 RXD6 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) 1 RXD6 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 Remark RXD6: "0" RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 482 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 483 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-24. Configuration of Baud Rate Generator POWER6 fPRS fPRS/2 fPRS/22 Baud rate generator POWER6, TXE6 (or RXE6) fPRS/23 fPRS/24 fPRS/25 fPRS/26 Selector 8-bit counter fXCLK6 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Match detector CKSR6: TPS63 to TPS60 Remark 1/2 Baud rate BRGC6: MDL67 to MDL60 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 CKSR6: Clock selection register 6 BRGC6: Baud rate generator control register 6 (2) Generation of serial clock A serial clock to be generated can be specified by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). The clock to be input to the 8-bit counter can be set by bits 3 to 0 (TPS63 to TPS60) of CKSR6 and the division value (fXCLK6/4 to fXCLK6/255) of the 8-bit counter can be set by bits 7 to 0 (MDL67 to MDL60) of BRGC6. 15.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 484 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Table 15-4. Set Value of TPS63 to TPS60 TPS63 TPS62 TPS61 TPS60 Base Clock (fXCLK6) Selection fPRS = 2 MHz Note 2 0 0 0 0 fPRS 0 0 0 1 fPRS/2 0 0 1 0 fPRS/2 2 0 0 1 1 fPRS = 5 MHz Note 1 fPRS = 10 MHz fPRS = 20 MHz Note 3 2 MHz 5 MHz 10 MHz 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 0 1 0 0 fPRS/2 4 125 kHz 312.5 kHz 625 kHz 0 1 0 1 fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz 0 1 1 0 fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 0 1 1 1 fPRS/2 7 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz 1.25 MHz 1 0 0 0 fPRS/2 8 1 0 0 1 fPRS/2 9 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz fPRS/2 10 1.953 kHz 4.88 kHz 9.77 kHz 1 0 1 0 1 0 1 1 Other than above Notes 1. TM50 output 19.53 kHz Note 4 Setting prohibited The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage 4.0 V VDD 5.5 V Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: fPRS) is prohibited. 3. This is settable only if 4.0 V VDD 5.5 V. 4. Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable (TOE50 = 1) TO50 output in any mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 485 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (2) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M / (2 x 33) = 10000000 / (2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] (3) Example of setting baud rate Table 15-5. Set Data of Baud Rate Generator Baud Rate [bps] fPRS = 2.0 MHz TPS63- k TPS60 fPRS = 5.0 MHz Calculated ERR TPS63Value [%] TPS60 k fPRS = 10.0 MHz Calculated ERR TPS63Value [%] TPS60 k fPRS = 20.0 MHz Calculated ERR TPS63Value [%] TPS60 k Calculated ERR Value [%] 300 8H 13 301 0.16 7H 65 301 0.16 8H 65 301 0.16 9H 65 301 0.16 600 7H 13 601 0.16 6H 65 601 0.16 7H 65 601 0.16 8H 65 601 0.16 1200 6H 13 1202 0.16 5H 65 1202 0.16 6H 65 1202 0.16 7H 65 1202 0.16 2400 5H 13 2404 0.16 4H 65 2404 0.16 5H 65 2404 0.16 6H 65 2404 0.16 4800 4H 13 4808 0.16 3H 65 4808 0.16 4H 65 4808 0.16 5H 65 4808 0.16 9600 3H 13 9615 0.16 2H 65 9615 0.16 3H 65 9615 0.16 4H 65 9615 0.16 19200 2H 13 19231 0.16 1H 65 19231 0.16 2H 65 19231 0.16 3H 65 19231 0.16 24000 1H 21 23810 -0.79 3H 13 24038 0.16 4H 13 24038 0.16 5H 13 24038 0.16 31250 1H 16 31250 0 4H 5 31250 0 5H 5 31250 0 6H 5 31250 0 38400 1H 13 38462 0.16 0H 65 38462 0.16 1H 65 38462 0.16 2H 65 38462 0.16 48000 0H 21 47619 -0.79 2H 13 48077 0.16 3H 13 48077 0.16 4H 13 48077 0.16 76800 0H 13 76923 0.16 0H 33 75758 -1.36 0H 65 76923 0.16 1H 65 76923 0.16 115200 0H 9 111111 -3.55 1H 11 113636 -1.36 0H 43 116279 0.94 0H 87 114943 -0.22 153600 - - - - 1H 8 156250 1.73 0H 33 151515 -1.36 1H 33 151515 -1.36 312500 - - - - 0H 8 312500 0 1H 8 312500 0 2H 8 312500 0 625000 - - - - 0H 4 625000 0 1H 4 625000 0 2H 4 625000 0 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 4, 5, 6, ..., 255) Peripheral hardware clock frequency fPRS: ERR: Baud rate error R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 486 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 15-25. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 15-25, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: Set value of BRGC6 FL: 1-bit data length Margin of latch timing: 2 clocks R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 487 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 x FLmax = 11 x FL - 11 FLmax = 21k - 2 k+2 2xk x FL = 21k - 2 2xk FL FL x 11 20k Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 15-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 4 +2.33% -2.44% 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 488 78K0/Kx2 CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 15-26. Data Frame Length During Continuous Transmission Start bit of second byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 489 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB Serial interface CSI10 - Serial interface CSI11 Remark : Mounted, -: Not mounted 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data lines (SI1n and SO1n). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 16.4.2 3-wire serial I/O mode. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 490 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Transmit controller Controller Clock start/stop controller & clock phase controller Transmit buffer register 1n (SOTB1n) Registers Serial I/O shift register 1n (SIO1n) Serial operation mode register 1n (CSIM1n) Control registers Serial clock selection register 1n (CSIC1n) Port mode register 0 (PM0) or port mode register 1 (PM1) Port register 0 (P0) or port register 1 (P1) Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products Figure 16-1. Block Diagram of Serial Interface CSI10 Internal bus 8 8 SI10/P11/RXD0 Serial I/O shift register 10 (SIO10) Transmit data controller PM10 Transmit buffer register 10 (SOTB10) Output selector SO10 output SO10/P12 Output latch (P12) Output latch PM12 Output latch (P10) Selector Transmit controller SCK10/P10/TxD0 fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Clock start/stop controller & clock phase controller INTCSI10 491 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 Internal bus SI11/P03 8 8 Serial I/O shift register 11 (SIO11) Transmit buffer register 11 (SOTB11) Transmit data controller Output selector SO11 output SO11/P02 Output latch (P02) Output latch SSI11 PM04 PM02 Output latch (P04) Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 Selector SCK11/P04 SSI11 Clock start/stop controller & clock phase controller INTCSI11 (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n). SOTB1n can be written or read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a low level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2) Communication operation. (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n. Reset signal generation clears this register to 00H. Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, reception is started when data is read from SIO11 with a low level input to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication operation. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 492 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) (1) Serial operation mode register 1n (CSIM1n) CSIM1n is used to select the operation mode and enable or disable operation. CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD10 0 Note 5 1 DIR10 6. . Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode Note 6 First bit specification 0 MSB 1 LSB CSOT10 Notes 1. 2. 3. 4. 5. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 output (see Figure 16-1) is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). Caution Be sure to clear bit 5 to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 493 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD11 0 Note 5 1 SSE11 Transmit/receive mode control Receive mode (transmission disabled). Notes 6, 7 SSI11 pin use selection 0 SSI11 pin is not used 1 SSI11 pin is used Note 8 First bit specification 0 MSB 1 LSB CSOT11 2. . Transmit/receive mode DIR11 Notes 1. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). 3. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. 4. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication). 5. The SO11 output (see Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is started when data is read from SIO11. 6. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication). 7. Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1. 8. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 494 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100 CKP10 DAP10 0 0 Specification of data transmission/reception timing 1 SCK10 SO10 Type D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 0 1 2 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 1 0 3 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 1 1 4 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing CKS102 CKS101 Notes 1, 2 CKS100 CSI10 serial clock selection Mode fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 1 MHz 2.5 MHz 5 MHz Setting prohibited 0 0 0 fPRS/2 0 0 1 fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 625 kHz 0 1 0 0 1 1 fPRS/2 4 125 kHz 312.5 kHz 1 0 0 fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 1 0 1 fPRS/2 6 31.25 kHz 78.13 kHz fPRS/2 7 15.63 kHz 39.06 kHz 78.13 kHz 1 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 1 1 0 1 External clock input from SCK10 Master mode 1.25 MHz 625 kHz 156.25 kHz 312.5 kHz Note 3 156.25 kHz Slave mode 495 78K0/Kx2 Notes 1. CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. Set the serial clock to satisfy the following conditions. Conventional-specification Products (PD78F05xx and 78F05xxD) and Supply Voltage Expanded-specification Products (PD78F05xxA and 78F05xxDA) Standard Products 3. (A) Grade Products (A2) Grade Products 4.0 V VDD 5.5 V Serial clock 6.25 MHz Serial clock 5 MHz Serial clock 5 MHz 2.7 V VDD < 4.0 V Serial clock 4 MHz Serial clock 2.5 MHz Serial clock 2.5 MHz 1.8 V VDD < 2.7 V Serial clock 2 MHz Serial clock 1.66 MHz - Do not start communication with the external clock from the SCK10 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 496 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 0 0 Specification of data transmission/reception timing Type 1 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 0 1 2 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 1 0 3 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 1 1 4 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing CKS112 CKS111 Notes 1, 2 CKS110 fPRS = 2 MHz 1. 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 625 kHz 0 0 1 fPRS/2 0 1 1 fPRS/2 4 125 kHz 312.5 kHz 1 0 0 fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 1 0 1 fPRS/2 6 31.25 kHz 78.13 kHz fPRS/2 7 15.63 kHz 39.06 kHz 78.13 kHz 1 1 Note Setting prohibited fPRS/2 1 1 0 1 fPRS = 20 MHz 5 MHz 0 0 fPRS = 10 MHz 2.5 MHz 0 1 fPRS = 5 MHz 1 MHz 0 0 Mode CSI11 serial clock selection External clock input from SCK11 Master mode 1.25 MHz 625 kHz 156.25 kHz 312.5 kHz 156.25 kHz Note 3 Slave mode The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 497 78K0/Kx2 Notes 2. CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Set the serial clock to satisfy the following conditions. Conventional-specification Products (PD78F05xx and 78F05xxD) and Expanded-specification Products (PD78F05xxA and 78F05xxDA) Supply Voltage Standard Products 3. (A) Grade Products (A2) Grade Products 4.0 V VDD 5.5 V Serial clock 6.25 MHz Serial clock 5 MHz Serial clock 5 MHz 2.7 V VDD < 4.0 V Serial clock 4 MHz Serial clock 2.5 MHz Serial clock 2.5 MHz 1.8 V VDD < 2.7 V Serial clock 2 MHz Serial clock 1.66 MHz - Do not start communication with the external clock from the SCK11 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark fPRS: Peripheral hardware clock frequency (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, clear PM10 and PM04 to 0, and set the output latches of P10 and P04 to 1. When using P12/SO10 and P02/SO11 as the data output pins of the serial interface, clear PM12, PM02, and the output latches of P12 and P02 to 0. When using P10/SCK10 and P04/SCK11 as the clock input pins of the serial interface, P11/SI10/RXD0 and P03/SI11 as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1. PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 16-7. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH Symbol 7 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) Remark 6 5 4 R/W 3 2 0 Output mode (output buffer on) 1 Input mode (output buffer off) 1 0 The figure shown above presents the format of port mode register 0 of 78K0/KF2 products. For the format of port mode register 0 of other products, see (1) Port mode registers (PMxx) in 5.3 Registers Controlling Port Function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 498 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol After reset: FFH 7 6 5 4 R/W 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11, P03/SI11, and P04/SCK11 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode register 1n (CSIM1n). To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0. (a) Serial operation mode register 1n (CSIM1n) CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CSIM1n to 00H. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products * Serial operation mode register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 . To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). 2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 499 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 * Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 1 0 Notes 1. Disables operation and asynchronously resets the internal circuit Note 2 . To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). 2. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines. (1) Registers used * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC1n register (see Figures 16-5 and 16-6). <2> Set bits 4 to 6 (DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see Figures 16-3 and 16-4). <3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 1n (SOTB1n). Data transmission/reception is started. Read data from serial I/O shift register 1n (SIO1n). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 500 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 CSI10 P10 Pin Function Operation 0 x 0 Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop SI10/RXD0/ SO10/P12 P11 RXD0/P11 P12 Note 2 SCK10/ TXD0/P10 TXD0/ P10 1 0 x 1 x Note 1 x Note 1 1 x Slave reception 1 x 1 Note 1 x Note 1 0 0 1 x SI10 P12 Note 2 Note 4 Slave Note 4 RXD0/P11 SO10 Note 4 1 x 1 0 0 1 x Slave SCK10 (input) SCK10 Note 4 (input) transmission 1 Note 3 SI10 SO10 SCK10 Note 4 (input) transmission/ Note 4 reception 1 0 x 1 x Note 1 x Note 1 0 1 Master reception SI10 P12 Note 2 SCK10 (output) 1 x 1 Note 1 x Note 1 0 0 0 Master 1 RXD0/P11 SO10 transmission 1 1 1 x 0 0 0 Master 1 SCK10 (output) SI10 SO10 transmission/ SCK10 (output) reception Notes 1. Can be set as port function. 2. To use P12/SO10 as general-purpose port, set the serial clock selection register 10 (CSIC10) in the default status (00H). 3. To use P10/SCK10/TXD0 as port pins, clear CKP10 to 0. 4. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. Remark x: don't care CSIE10: Bit 7 of serial operation mode register 10 (CSIM10) TRMD10: Bit 6 of CSIM10 CKP10: Bit 4 of serial clock selection register 10 (CSIC10) CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 PM1x: Port mode register P1x: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 501 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 CSI11 CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 Pin Function Operation 0 0 x 1 0 0 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 SI11/ SO11/ SCK11/ SSI11/ P03 P02 P04 TI001/P05 x Note 1 x Note 1 Stop P03 P02 x Note 1 x Note 1 Slave SI11 P02 Note 2 P04 Note 3 TI001/ Note 2 SCK11 TI001/ (input) P05 P05 x 1 1 x reception Note 4 Note 4 1 1 1 1 x 0 Note 1 x Note 1 0 0 1 x x Note 1 SSI11 x x Note 1 Slave P03 SO11 Note 4 transmission SCK11 TI001/ (input) P05 Note 4 1 1 1 1 0 x 1 0 0 1 x x Note 1 x x SSI11 Note 1 Slave SI11 SO11 transmission/ Note 4 1 1 0 1 0 x 1 x Note 1 x Note 1 0 1 x Note 1 x x Master 1 1 x 0 x Note 1 0 0 0 1 x Note 1 x Note 1 Master SI11 P02 P03 SO11 transmission 1 1 0 1 x 0 0 0 1 x Note 1 x Note 1 Master P05 SSI11 Note 2 reception Note 1 TI001/ (input) Note 4 reception Note 1 SCK11 SI11 SO11 transmission/ SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 reception Notes 1. Can be set as port function. 2. To use P02/SO11 as general-purpose port, set the serial clock selection register 11 (CSIC11) in the default status (00H). 3 To use P04/SCK11 as port pins, clear CKP11 to 0. 4 To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1. Remark x: don't care CSIE11: Bit 7 of serial operation mode register 11 (CSIM11) TRMD11: Bit 6 of CSIM11 CKP11: Bit 4 of serial clock selection register 11 (CSIC11) CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11 PM0x: Port mode register P0x: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 502 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. Reception is started when data is read from serial I/O shift register 1n (SIO1n). However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the slave mode. <1> Low level input to the SSI11 pin Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read. <2> High level input to the SSI11 pin Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read, transmission/reception or reception will not be started. <3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low level is input to the SSI11 pin Transmission/reception or reception is started. <4> A high level is input to the SSI11 pin during transmission/reception or reception Transmission/reception or reception is suspended. After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0. Then the next communication is enabled. Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial communication). 2. When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 503 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) (a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 504 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) (b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 505 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (c) Type 3: CKP1n = 1, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (d) Type 4: CKP1n = 1, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n Remarks 1. n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products 2. The above figure illustrates a communication operation where data is transmitted with the MSB first. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 506 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11. Output Operation of First Bit (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch First bit SO1n 2nd bit (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 507 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-11. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch First bit SO1n 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 508 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( Next request is issued.) Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch Last bit SO1n (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Remark n = 0: Last bit 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 509 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-12. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Last bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Remark n = 0: Last bit 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 510 78K0/Kx2 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (see Figures 16-1 and 16-2) The status of the SO1n output is as follows depending on the setting of CSIE1n, TRMD1n, DAP1n, and DIR1n. Table 16-3. SO1n Output Status CSIE1n CSIE1n = 0 TRMD1n Note 2 TRMD1n = 0 Notes 2, 3 DIR1n - - Low level output - Low level output DAP1n = 0 TRMD1n = 1 DAP1n = 1 DIR1n = 0 DIR1n = 1 CSIE1n = 1 TRMD1n = 0 Note 3 TRMD1n = 1 Notes 1. Note 1 DAP1n SO1n Output Note 2 Value of bit 7 of SOTB1n Value of bit 0 of SOTB1n - - Low level output - - Transmission data Note 4 The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12 or PM02 and P02, as well as the SO1n output. 2. This is a status after reset. 3. To use the P12/SO10 or P02/SO11 pin as general-purpose port, set the serial clock selection register 1n (CSIC1n) in the default status (00H). 4. After transmission has been completed, the SO1n pin holds the output value of the last bit of transmission data. Caution If a value is written to CSIE1n, TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. Remark n = 0: 78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2, 78K0/KD2 products n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 511 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 17 SERIAL INTERFACE CSIA0 78K0/KB2 78K0/KC2 Serial interface 78K0/KD2 - 78K0/KE2 78K0/KF2 CSIA0 Remark : Mounted, -: Not mounted 17.1 Functions of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 17.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is to communicate data successively in 8-bit units, by using three lines: serial clock (SCKA0) and serial data (SIA0 and SOA0) lines. The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. For details, see 17.4.2 3-wire serial I/O mode. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB/LSB-first selectable) This mode is used to communicate data continuously in 8-bit units using three lines: a serial clock line (SCKA0) and two serial data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode with automatic transmit/receive function because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. Data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer RAM is incorporated. Also, the incorporation of handshake pins (STB0, BUSY0) used in the master mode has made connection to peripheral ICs easy. For details, see 17.4.3 3-wire serial I/O mode with automatic transmit/receive function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 512 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 The features of serial interface CSIA0 are as follows. * Master mode/slave mode selectable * Communication data length: 8 bits * MSB/LSB-first selectable for communication data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single communication/repeat communication selectable Internal 32-byte buffer RAM * On-chip dedicated baud rate generator (6/8/16/32 divisions) * 3-wire SOA0: SIA0: Serial data output Serial data input SCKA0: Serial clock I/O * Handshake function incorporated STB0: Strobe output BUSY0: Busy input * Detection of bit shift error due to BUSY0 signal * Transmission/reception completion interrupt: INTACSI 17.2 Configuration of Serial Interface CSIA0 Serial interface CSIA0 consists of the following hardware. Table 17-1. Configuration of Serial Interface CSIA0 Item Configuration Controller Serial transfer controller Registers Serial I/O shift register 0 (SIOA0) Control registers Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Automatic data transfer address count register 0 (ADTC0) Port mode register 14 (PM14) Port register 14 (P14) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 513 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 17-1. Block Diagram of Serial Interface CSIA0 Buffer RAM Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer address count register 0 (ADTC0) Internal bus ATE0 Serial trigger register 0 (CSIT0) DIR0 ATM0 Serial I/O shift register 0 (SIOA0) SIA0/P143 Divisor selection register 0 (BRGCA0) ATSTP0 ATSTA0 RXAE0 SOA0/P144 Serial status register 0 (CSIS0) P144 TXAE0 PM144 STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 2 STB0/P145 PM145 Serial clock counter P145 Interrupt generator INTACSI 4 Serial transfer controller BUSY0/P141 3 SCKA0/P142 Selector fW/6 to fW/32 Automatic data transfer interval specification register 0 (ADTI0) Baud rate generator fW Selector P142 MASTER0 CKS000 6-bit counter CSIAE0 ATE0 ATM0 MASTER0 TXEA0 RXEA0 DIR0 Serial operation mode specification register 0 (CSIMA0) Internal bus fPRS fPRS/2 514 CHAPTER 17 SERIAL INTERFACE CSIA0 PM142 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial I/O shift register 0 (SIOA0) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 0). Writing transmit data to SIOA0 starts the communication. In addition, after a communication completion interrupt request (INTACSI) is output (bit 0 (TSF0) of serial status register 0 (CSIS0) = 0), data can be received by reading data from SIOA0. This register can be written or read by an 8-bit memory manipulation instruction. However, writing to SIOA0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Reset signal generation clears this register to 00H. Cautions 1. A communication operation is started by writing to SIOA0. Consequently, when transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0 register to start the communication operation, and then perform a receive operation. 2. Do not write data to SIOA0 while the automatic transmit/receive function is operating. 17.3 Registers Controlling Serial Interface CSIA0 Serial interface CSIA0 is controlled by the following nine registers. * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Automatic data transfer address count register 0 (ADTC0) * Port mode register 14 (PM14) * Port register 14 (P14) (1) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 515 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-2. Format of Serial Operation Mode Specification Register 0 (CSIMA0) Address: FF90H After reset: 00H Symbol < > CSIMA0 CSIAE0 ATE0 R/W ATM0 CSIAE0 < > TXEA0 RXEA0 DIR0 0 Control of CSIA0 operation enable/disable 0 CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuitNote 1. 1 CSIA0 operation enabled ATE0 Control of automatic communication operation enable/disable 0 1-byte communication mode 1 Automatic communication mode ATM0 Automatic communication mode specification 0 Single transfer mode (stops at the address specified by the ADTP0 register) 1 Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer) MASTER0 CSIA0 master/slave mode specification 0 Slave mode (synchronous with SCKA0 input clock)Note 2 1 Master mode (synchronous with internal clock) Control of transmit operation enable/disable TXEA0 0 Transmit operation disabled (SOA0: Low level) 1 Transmit operation enabled Control of receive operation enable/disable RXEA0 0 Receive operation disabled 1 Receive operation enabled First bit specification DIR0 Notes 1. MASTER0 < > 0 MSB 1 LSB Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset. 2. Do not start communication with the external clock from the SCKA0 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed. 2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. 3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 516 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Serial status register 0 (CSIS0) This is an 8-bit register used to select the base clock, control the communication operation, and indicate the status of serial interface CSIA0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1. Reset signal generation clears this register to 00H. Figure 17-3. Format of Serial Status Register 0 (CSIS0) (1/2) Address: FF91H Symbol CSIS0 R/WNote 1 After reset: 00H 7 0 6 Note 2 CKS00 5 4 3 2 1 0 STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 Base clock (fW) selectionNote 3 CKS00 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 0 fPRSNote 4 2 MHz 5 MHz 10 MHz 20 MHzNote 5 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz STBE0Notes 6, 7 Notes 1. 2. Strobe output enable/disable 0 Strobe output disabled 1 Strobe output enabled Bits 0 and 1 are read-only. Make sure that bit 7 (CSIAE0) of the Serial Operation Mode Specification Register 0 (CSIMA0) = 0 when rewriting the CKS00 bit. 3. The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 4. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of CKS00 = 0 (base clock: fPRS) is prohibited. 5. This is settable only if 4.0 V VDD 5.5 V. 6. STBE0 is valid only in master mode. 7. When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks are used for 1-byte transfer if ADTI0 = 00H is set. Caution Be sure to clear bit 7 to 0. Remark fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 517 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-3. Format of Serial Status Register 0 (CSIS0) (2/2) BUSYE0 Busy signal detection enable/disable 0 Busy signal detection disabled (input via BUSY0 pin is ignored) 1 Busy signal detection enabled and communication wait by busy signal is executed BUSYLV0Note 1 Busy signal active level setting 0 Low level 1 High level ERRE0Note 2 Bit error detection enable/disable 0 Error detection disabled 1 Error detection enabled ERRF0 0 1 Bit error detection flag Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 At reset input When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1 or writing to SIOA0. Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer period is detected via BUSY0 pin input). TSF0 0 1 Notes 1. 2. Caution Transfer status detection flag Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 At reset input At the end of the specified transfer When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1 From the transfer start to the end of the specified transfer In bit error detection by busy input, the active level specified by BUSYLV0 is detected. The ERRE0 setting is valid even when BUSYE0 = 0. During transfer (TSF0 = 1), rewriting serial operation mode specification register 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 518 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (3) Serial trigger register 0 (CSIT0) This is an 8-bit register used to control execution/stop of automatic data transfer between buffer RAM and serial I/O shift register 0 (SIOA0). This register can be set by a 1-bit or 8-bit memory manipulation instruction. This register can be set when bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is 1. Reset signal generation clears this register to 00H. Figure 17-4. Format of Serial Trigger Register 0 (CSIT0) Address: FF92H After reset: 00H R/W Symbol 7 6 5 4 3 2 <1> <0> CSIT0 0 0 0 0 0 0 ATSTP0 ATSTA0 ATSTP0 Automatic data transfer stop 0 - 1 Automatic data transfer stopped ATSTA0 Automatic data transfer start - 0 1 Automatic data transfer started Cautions 1. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1-byte transfer is complete. 2. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. 3. After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by setting ATSTA0 to 1 after re-setting the registers. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 519 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Divisor selection register 0 (BRGCA0) This is an 8-bit register used to select the base clock divisor of CSIA0. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting BRGCA0 is prohibited. Reset signal generation sets this register to 03H. Figure 17-5. Format of Divisor Selection Register 0 (BRGCA0) Address: FF93H After reset: 03H R/W Symbol 7 6 5 4 3 2 1 0 BRGCA0 0 0 0 0 0 0 BRGCA01 BRGCA00 BRGCA01 BRGCA00 Selection of base clock (fW) divisor of CSIA0Note fW = 1 MHz fW = 2 MHz fW = 2.5 MHz fW = 5 MHz fW = 10 MHz fW = 20 MHz 0 0 fW/6 166.67 kHz 333.3 kHz 416.67 kHz 833.33 kHz 1.67 MHz Setting prohibited 0 1 fW/23 125 kHz 250 kHz 312.5 kHz 625 kHz Setting prohibited 0 fW/2 4 62.5 kHz 125 kHz 156.25 kHz 312.5 kHz 625 kHz fW/2 5 31.25 kHz 62.5 kHz 1 1 1 1.25 MHz 1.25 MHz 78.125 kHz 156.25 kHz 312.5 kHz 625 kHz Note Set the transfer clock so as to satisfy the following conditions. * When 4.0 V VDD 5.5 V: transfer clock 1.67 MHz * When 2.7 V VDD < 4.0 V: transfer clock 833.33 kHz * When 1.8 V VDD < 2.7 V: transfer clock 555.56 kHz (Standard products and (A) grade products only) Remark fW: Base clock frequency selected by CKS00 bit of CSIS0 register (fPRS or fPRS/2) fPRS: Peripheral hardware clock frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 520 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (5) Automatic data transfer address point specification register 0 (ADTP0) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 = 1). This register can be set by an 8-bit memory manipulation instruction. However, during transfer (TSF0 = 1), rewriting ADTP0 is prohibited. In the 78K0/KF2, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When ADTP0 is set to 07H 8 bytes of FA00H to FA07H are transferred. In repeat transfer mode (bit 5 (ATM0) of CSIMA0 = 1), transfer is performed repeatedly up to the address specified with ADTP0. Example When ADTP0 is set to 07H (repeat transfer mode) Transfer is repeated as FA00H to FA07H, FA00H to FA07H, ... . Figure 17-6. Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0) Address: FF94H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTP0 0 0 0 ADTP04 ADTP03 ADTP02 ADTP01 ADTP00 Caution Be sure to clear bits 7 to 5 to "0". The relationship between transfer end buffer RAM address values and ADTP0 setting values is shown below. Table 17-2. Relationship Between Transfer End Buffer RAM Address Values and ADTP0 Setting Values Transfer End Buffer RAM ADTP0 Setting Value Address Value FAxxH Remark R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 xxH xx: 00 to 1F 521 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (6) Automatic data transfer interval specification register 0 (ADTI0) This is an 8-bit register used to specify the interval time for byte data transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave mode). Setting in 1-byte communication mode (bit 6 (ATE0) of CSIMA0 = 0) is also valid. When the interval time specified by ADTI0 after the end of 1-byte communication has elapsed, an interrupt request signal (INTACSI) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTI0 is prohibited. Figure 17-7. Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0) Address: FF95H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTI0 0 0 ADTI05 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Caution Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. Example Interval time when ADTI0 = 00H and busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer. The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by an integer value. Example When ADTI0 = 03H SCKA0 Interval time of 3 clocks R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 522 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (7) Automatic data transfer address count register 0 (ADTC0) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTC0 register value. This register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. However, reading from ADTC0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Figure 17-8. Format of Automatic Data Transfer Address Count Register 0 (ADTC0) Address: FF97H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ADTC0 0 0 0 ADTC04 ADTC03 ADTC02 ADTC01 ADTP00 (8) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using P142/SCKA0 pin as the clock output of the serial interface, clear PM142 to 0 and set the output latch of P142 to 1. When using P144/SOA0 and P145/STB0 pins as the data output or strobe output of the serial interface, clear PM144, PM145, and the output latches of P144 and P145 to 0. When using P141/BUSY0, P142/SCKA0, and P143/SIA0 pins as the busy input, clock input, or data input of the serial interface, set PM141, PM142, and PM143 to 1. At this time, the output latches of P141, P142, and P143 may be 0 or 1. PM14 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 17-9. Format of Port Mode Register 14 (PM14) Address: FF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 PM14n P14n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 523 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4 Operation of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P142/SCKA0, P143/SIA0, and P144/SOA0 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode specification register 0 (CSIMA0). To set the operation stop mode, clear bit 7 (CSIAE0) of CSIMA0 to 0. (a) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FF90H After reset: 00H R/W < > CSIMA0 CSIAE0 CSIAE0 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 ATE0 ATM0 MASTER0 < > < > TXEA0 RXEA0 DIR0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuit 524 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is cleared to 0. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCKA0), serial output (SOA0), and serial input (SIA0) lines. (1) Registers used * Serial operation mode specification register 0 (CSIMA0)Note 1 * Serial status register 0 (CSIS0)Note 2 * Divisor selection register 0 (BRGCA0) * Port mode register 14 (PM14) * Port register 14 (P14) Notes 1. Bits 7, 6, and 4 to 1 (CSIAE0, ATE0, MASTER0, TXEA0, RXEA0, and DIR0) are used. Setting of bit 5 (ATM0) is invalid. 2. Only bit 0 (TSF0) and bit 6 (CKS00) are used. The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set bit 6 (CKS00) of the CSIS0 register (see Figure 17-3)Note 1. <2> Set the BRGCA0 register (see Figure 17-5) Note 1 . <3> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-2). <4> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0. <5> Write data to serial I/O shift register 0 (SIOA0). Data transmission/reception is startedNote 2. Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0). 2. Write dummy data to SIOA0 only for reception. Caution Take relationship with the other party of communication when setting the port mode register and port register. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 525 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between the register settings and pins is shown below. Table 17-3. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 PM143 0 x x xNote 1 P143 xNote 1 PM144 xNote 1 P144 xNote 1 PM142 xNote 1 P142 xNote 1 Serial I/O Serial Clock Shift Counter SIA0/ SOA0/ SCKA0/ Register 0 Operation P143 P144 P142 Operation Control Operation Pin Function Clear P143 P144 P142 Operation Count SIA0Note 2 SOA0Note 3 SCKA0 enabled operation stopped 1 0 0 1Note 2 xNote 2 0Note 3 0Note 3 1 0 1 x 1 (input) SCKA0 (output) Notes 1. Can be set as port function. 2. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. 3. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. Remark x: don't care CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ATE0: Bit 6 of CSIMA0 MASTER0: Bit 4 of CSIMA0 PM14x: Port mode register P14x: Port output latch R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 526 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1, 0, respectively, if communication data is written to serial I/O shift register 0 (SIOA0), the data is output via the SOA0 pin in synchronization with the SCKA0 falling edge, and stored in the SIOA0 register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, communication can only be started by writing a dummy value to the SIOA0 register. When communication of 1 byte is complete, an interrupt request signal (INTACSI) is generated. In 1-byte transmission/reception, the setting of bit 5 (ATM0) of CSIMA0 is invalid. Be sure to read data after confirming that bit 0 (TSF0) of serial status register 0 (CSIS0) = 0. Figure 17-10. 3-Wire Serial I/O Mode Timing SCKA0 1 2 3 4 5 6 7 8 SIA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SOA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 TSF0 ACSIIF Transfer starts at falling edge of SCKA0 End of transfer SIOA0 write Caution The SOA0 pin becomes low level by an SIOA0 write. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 527 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data communication direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-11. Format of Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SOA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SOA0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 528 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Switching MSB/LSB as start bit Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-12. Transfer Bit Order Switching Circuit 7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate SOA0 latch SIA0 Shift register 0 (SIOA0) D Q SOA0 SCKA0 Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (d) Communication start Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when the following two conditions are satisfied. * Serial interface CSIA0 operation control bit (CSIAE0) = 1 * Serial communication is not in progress Caution If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. Upon termination of 8-bit communication, serial communication automatically stops and the interrupt request flag (ACSIIF) is set. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 529 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. In addition, to transmit/receive data continuously when used as the master, handshake signals (STB0 and BUSY0) generated by hardware are supported. Therefore, connection to peripheral ICs such as OSD (On Screen Display) ICs and LCD controller/drivers can be easily realized. (1) Registers used * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Port mode register 14 (PM14) * Port register 14 (P14) The relationship between the register settings and pins is shown below. Caution A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 530 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Table 17-4. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 STBE0 BUSYE0 ERRE0 PM143 P143 PM144 P144 PM142 P142 PM145 P145 PM141 P141 0 x x x 1 1 0 xNote 1 xNote 1 0/1 1 0 0 0/1 1 1 0/1 Notes 1. x Note 1 x Note 1 x Note 1 x 1 Note 1 x x Note 1 0 x Note 1 x Note 1 0 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Serial I/O Shift Register 0 Operation Operation stopped Clear 1 x xNote 1 xNote 1 xNote 1 xNote 1 Operation enabled Count operation 0 1 xNote 1 xNote 1 xNote 1 xNote 1 0 0 1 x Pin Function SIA0/ SOA0/ SCKA0/ STB0/ BUSY0/ P143 P144 P142 P145 P141 P143 P144 P142 P145 P141 SCKA0 P145 SOA10 (input) P141 Note 2 SIA0 Note 3 SCKA0 P145 P141 (output) STB0 BUSY0 Can be set as port function. 2. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. 3. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. Remark Serial Clock Counter Operation Control x: don't care CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ATE0: Bit 6 of CSIMA0 MASTER0: Bit 4 of CSIMA0 Bit 5 of serial status register 0 (CSIS0) BUSYE0: Bit 4 of CSIS0 ERRE0: Bit 2 of CSIS0 PM14x: Port mode register P14x: Port output latch 531 CHAPTER 17 SERIAL INTERFACE CSIA0 STBE0: 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Automatic transmit/receive data setting Here is an example of the procedure for successively transmitting/receiving data as the master. <1> Enable CSIA0 to operate by setting bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) to 1 (the buffer RAM can now be accessed). <2> Select a serial clock by using serial status register 0 (CSIS0). <3> Set the division ratio of the serial clock by using division value selection register 0 (BRGCA0), and specify a communication rate. <4> Sequentially write data to be transmitted to the buffer RAM, starting from the least significant address FA00H, up to FA1FH. Data is transmitted from the lowest address, continuing on to higher addresses. <5> Set "number of data items to be transmitted - 1" to automatic data transfer address point specification register 0 (ADTP0). <6> Set bits 6 (ATE0) and 4 (MASTER0) of CSIMA0 to select a master operation in the automatic communication mode. <7> Set bits 3 (TXEA0) and 2 (RXEA0) of CSIMA0 to 1 to enable transmission/reception. <8> Set the transmission interval of data to the automatic data transfer interval specification register (ADTI0). <9> Automatic transmit/receive processing is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1. Caution Take the relationship with the other communicating party into consideration when setting the port mode register and port register. Operations <1> to <9> execute the following operation. * After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is transferred to SIOA0, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by ADTC0. * ADTC0 is incremented and the next data transmission/reception is carried out. Data transmission/reception continues until the ADTC0 incremental output matches the set value of automatic data transfer address point specification register 0 (ADTP0) (end of automatic transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, an interrupt request (INTACSI) is generated and bit 0 (TSF0) of CSIS0 is cleared. * To continue transmitting the next data, set the new data to the buffer RAM, and set "number of data to be transmitted - 1" to ADTP0. After setting the number of data, set ATSTA0 to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 532 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge by performing (2) Automatic transmit/receive data setting. The receive data is stored in the buffer RAM via the SIOA0 register in synchronization with the SCKA0 rising edge. Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following conditions is met. * Communication stop: Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0 * Communication suspension: Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register to 1 * Bit shift error: Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit 2 (ERRE0) = 1 * Transfer of the range specified by the ADTP0 register is complete At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been transferred and re-execute transfer by performing (2) Automatic transmit/receive data setting. In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and STB0/P145 pins can be used as ordinary I/O port pins. Figure 17-13 shows the example of the operation timing in automatic transmission/reception mode and Figure 17-14 shows the operation flowchart. Figures 17-15 and 17-16 show the operation of internal buffer RAM when 6 bytes of data are transmitted/received. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 533 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-13. Example of Automatic Transmission/Reception Mode Operation Timings Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 Cautions 1. Because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Bit 0 of serial status register 0 (CSIS0) 534 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-14. Automatic Transmission/Reception Mode Flowchart Start Set CSIAE0 to 1 Set the communication speed Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the automatic transmission/reception mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Transmission/reception operation Increment ADTC0 Hardware execution Write receive data from SIOA0 to internal buffer RAMNote ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 TSF0: Bit 0 of serial status register 0 (CSIS0) Note A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 535 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1, ATE0 = 1) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Starting automatic transmission/reception (see Figure 17-15) <1> When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0 and transmission/reception is started. <2> When transmission of the first byte is completed, the receive data 1 (R1) is transferred from SIOA0 to the buffer RAM, and automatic data transfer address count register 0 (ADTC0) is incremented. <3> Next, transmit data 2 (T2) is transferred from the internal buffer to SIOA0. Figure 17-15. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (Starting Transmission/Reception) (1/2) <1> Starting 1st byte transmission/reception FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) FA1FH Data transmission FA05H Transmit data 6 (T6) Transmit data 1 (T1) SIOA0 Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 2 (T2) FA00H Transmit data 1 (T1) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 536 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-15. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (Starting Transmission/Reception) (2/2) <2> End of 1st byte transmission/reception FA1FH Data reception FA05H Transmit data 6 (T6) Receive data 1 (R1) SIOA0 5 ADTP0 0 ADTC0 0 ACSIIF Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) FA00H +1 Transmit data 1 (T1) <3> Starting of 2nd byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Receive data 1 (R1) SIOA0 5 ADTP0 1 ADTC0 0 ACSIIF Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) FA00H Receive data 1 (R1) (ii) Completion of transmission/reception (see Figure 17-16) <1> When transmission/reception of the sixth byte is completed, receive data 6 (R6) is transferred from SIOA0 to the internal buffer RAM and ADTC0 is incremented. <2> When the value of ADPT0 and that of ADTC0 match, the automatic transmission/reception ends, and an interrupt request flag (ACSIIF) is set (INTACSI is generated). ADTC0 and bit 0 (TSF0) of serial status register 0 (CSIS0) are cleared to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 537 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-16. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (End of Transmission/Reception) <1> End of 6th byte transmission/reception FA1FH Data reception FA05H Transmit data 6 (T6) Receive data 6 (R6) SIOA0 5 ADTP0 4 ADTC0 0 ACSIIF Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) FA00H Receive data 1 (R1) +1 <2> End of automatic transmission/reception FA1FH FA05H Receive data 6 (R6) Receive data 6 (R6) SIOA0 5 ADTP0 Receive data 5 (R5) Receive data 4 (R4) Match Receive data 3 (R3) 5 ADTC0 Receive data 1 (R1) 0 ACSIIF Receive data 6 (R6) Receive data 6 (R6) SIOA0 5 ADTP0 5 ADTC0 1 ACSIIF Receive data 2 (R2) FA00H FA1FH FA05H Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) FA00H Receive data 1 (R1) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 538 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Automatic transmission mode In this mode, the specified data is transmitted in 8-bit unit. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. When the final byte has been transmitted, an interrupt request flag (ACSIIF) is set. The termination of automatic transmission can also be judged by bit 0 (TSF0) of serial status register 0 (CSIS0). If a receive operation, busy control and strobe control are not executed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as normal I/O port pins. Figure 17-17 shows the example of the automatic transmission mode operation timing, and Figure 17-18 shows the operation flowchart. Figure 17-17. Example of Automatic Transmission Mode Operation Timing Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Bit 0 of serial status register 0 (CSIS0) 539 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-18. Automatic Transmission Mode Flowchart Start Set CSIAE0 to 1 Set the communication rate Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the automatic transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment ADTC0 Transmission operation Hardware execution ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 TSF0: Bit 0 of serial status register 0 (CSIS0) Note A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 540 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. Unlike the automatic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0, and the internal buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins. The example of the repeat transmission mode operation timing is shown in Figure 17-19, and the operation flowchart in Figure 17-20. Figure 17-19. Example of Repeat Transmission Mode Operation Timing Interval Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 541 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-20. Repeat Transmission Mode Flowchart Start Set CSIAE0 to 1 Set the communication rate Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes Set the repeat transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment ADTC0 Transmission operation Hardware execution ADTP0 = ADTC0 No Yes Reset ADTC0 to 0 CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ADTP0: Automatic data transfer address point specification register 0 ADTI0: Automatic data transfer interval specification register 0 ATSTA0: Bit 0 of serial trigger register 0 (CSIT0) SIOA0: Serial I/O shift register 0 ADTC0: Automatic data transfer address count register 0 Note A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 542 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (d) Data format Data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-21. Format of CSIA0 Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SOA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SOA0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 543 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1. During 8-bit data communication, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data communication. When suspended, bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared to 0 after transfer of the 8th bit. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TSF0 = 1. Figure 17-22. Automatic Transmission/Reception Suspension and Restart Suspend command (ATSTP0 = 1) Suspend Restart command (after each register setting, ATSTA0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ATSTP0: Bit 1 of serial trigger register 0 (CSIT0) ATSTA0: Bit 0 of CSIT0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 544 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Synchronization control Busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1. Figure 17-23 shows the system configuration of the master device and slave device when the busy control option is used. Figure 17-23. System Configuration When Busy Control Option Is Used Master device (78K0/KF2) SCKA0 SOA0 SIA0 BUSY0 Slave device SCKA SIA SOA Busy output The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin. The master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0. BUSYLV0 = 1: Active-high BUSYLV0 = 0: Active-low When using the busy control option, select the master mode. Control with the busy signal cannot be implemented in the slave mode. Figure 17-24 shows the example of the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (ADTI0). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 545 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-24. Example of Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 Wait ACSIIF Busy input released Busy input valid TSF0 Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release the waiting, keep the busy signal inactive at the slave side, until SCKA0 falls. Figure 17-25 shows the example of the timing of the busy signal and releasing the waiting. This figure shows an example in which the busy signal is active as soon as transmission/reception has been started. Figure 17-25. Busy Signal and Wait Release (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 (active-high) 1.5 clocks (MAX.) If made inactive immediately after sampled Wait Busy input released Busy input valid R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 546 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Busy & strobe control option Strobe control is a function used to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB0/P145 pin when 8-bit transmission/reception has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied: * Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. Figure 17-26 shows the example of the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of transmission/reception is set after the strobe signal is output. Figure 17-26. Example of Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB0 BUSY0 ACSIIF Busy input released Busy input valid TSF0 Caution When TSF0 is cleared, the SOA0 pin goes low. Remark ACSIIF: Interrupt request flag TSF0: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Bit 0 of serial status register 0 (CSIS0) 547 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows: The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0 (CSIS0) to 1, and communication is suspended and an interrupt request signal (INTACSI) is output). Although communication is suspended after completion of 1-byte data communication, slave signal output, wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed. If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs. Figure 17-27 shows the example of the operation timing of the bit shift detection function by the busy signal. Figure 17-27. Example of Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 1) SCKA0 (Master) Bit shift due to noise SCKA0 (Slave) SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 ACSIIF CSIAE0 ERRF0 Busy not detected ACSIIF: Error interrupt request generated Error detected Interrupt request flag CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) ERRF0: Bit 1 of serial status register 0 (CSIS0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 548 78K0/Kx2 CHAPTER 17 SERIAL INTERFACE CSIA0 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 (STBE0) and 4 (BUSYE0) of serial status register 0 (CSIS0). When ADTI0 is cleared to 00H, an interval time based on the to STBE0 and BUSYE0 settings is inserted. If ADTI0 = 00H and STBE0 = BUSYE0 = 1, for example, then an interval time of two clocks is inserted, and the interval time can be further extended by using an external busy signal. If an interval time of two clocks or more is set by using ADTI0, then the interval time set by ADTI0 is inserted, regardless of the settings of STBE0 and BUSYE0. When BUSYE0 = 1, the interval time can be further extended by an external busy signal. Example Interval time when ADTI0 = 00H and busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Figure 17-28. Example of Interval Time for Automatic Transmission/Reception (When ADTI0 = 00H, STBE0 = 1, BUSYE0 = 0 (Two Clocks)) Interval SCKA0 SOA0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF ACSIIF: Interrupt request flag R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 549 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 CHAPTER 18 SERIAL INTERFACE IIC0 Caution Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface IIC0 and the multiplier/divider. Remark The multiplier/divider is mounted only onto the 78K0/Kx2 microcontroller products whose flash memory is at least 48 KB. 18.1 Functions of Serial Interface IIC0 Serial interface IIC0 are mounted onto all 78K0/Kx2 microcontroller products. Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial data bus (SDA0) line. This mode complies with the I2C bus format and the master device can generated "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received status and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line. Figure 18-1 shows a block diagram of serial interface IIC0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 550 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Slave address register 0 (SVA0) SDA0/ P61 IIC shift register 0 (IIC0) DFC0 D Q PM61 Stop condition generator SO latch CL01, CL00 Data hold time correction circuit TRC0 N-ch opendrain output Set Match signal Noise eliminator Start condition generator Clear ACK generator Output control Output latch (P61) Wake-up controller ACK detector Start condition detector Stop condition detector SCL0/ P60 Noise eliminator DFC0 Interrupt request signal generator Serial clock counter Serial clock controller Serial clock wait controller N-ch opendrain output PM60 Output latch (P60) INTIIC0 IICS0.MSTS0, EXC0, COI0 IIC shift register 0 (IIC0) IICC0.STT0, SPT0 IICS0.MSTS0, EXC0, COI0 fPRS EXSCL0/ P62 Bus status detector Prescaler CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC clock selection register 0 (IICCL0) CLX0 STCF IIC function expansion register 0 (IICX0) IICBSY STCEN IICRSV IIC flag register 0 (IICF0) Internal bus Remark The 78K0/KB2 products are not mounted with the EXSCL0 pin. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 551 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-2 shows a serial bus configuration example. Figure 18-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDA0 Slave CPU1 Address 0 SCL0 Serial data bus Serial clock SDA0 Slave CPU2 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Master CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N 552 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 18-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0) Port mode register 6 (PM6) Port register 6 (P6) (1) IIC shift register 0 (IIC0) IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. IIC0 can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing and reading operations to IIC0. Cancel the wait state and start data transfer by writing data to IIC0 during the wait period. IIC0 is set by an 8-bit memory manipulation instruction. Reset signal generation clears IIC0 to 00H. Figure 18-3. Format of IIC Shift Register 0 (IIC0) Address: FFA5H Symbol After reset: 00H 7 6 R/W 5 4 3 2 1 0 IIC0 Cautions 1. Do not write data to IIC0 during data transfer. 2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state other than during the wait period is prohibited. When the device serves as the master, however, IIC0 can be written only once after the communication trigger bit (STT0) is set to 1. <R> 3. When communication is reserved, write data to the IIC0 register after the interrupt triggered by a stop condition is detected. (2) Slave address register 0 (SVA0) <R> This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. This register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected). Reset signal generation clears SVA0 to 00H. Figure 18-4. Format of Slave Address Register 0 (SVA0) Address: FFA7H Symbol SVA0 7 After reset: 00H 6 R/W 5 4 3 2 1 0 0Note Note Bit 0 is fixed to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 553 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (3) SO latch The SO latch is used to retain the SDA0 pin's output level. (4) Wake-up controller This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0). An I2C interrupt request is generated by the following two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by SPIE0 bit) Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0) SPIE0 bit: Bit 4 of IIC control register 0 (IICC0) (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1. (13) Stop condition generator This circuit generates a stop condition when the SPT0 bit is set to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 554 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit. Remark STT0 bit: Bit 1 of IIC control register 0 (IICC0) SPT0 bit: Bit 0 of IIC control register 0 (IICC0) IICRSV bit: Bit 0 of IIC flag register 0 (IICF0) IICBSY bit: Bit 6 of IIC flag register 0 (IICF0) STCF bit: Bit 7 of IIC flag register 0 (IICF0) STCEN bit: Bit 1 of IIC flag register 0 (IICF0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 555 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.3 Registers to Control Serial Interface IIC0 Serial interface IIC0 is controlled by the following seven registers. * IIC control register 0 (IICC0) * IIC flag register 0 (IICF0) * IIC status register 0 (IICS0) * IIC clock selection register 0 (IICCL0) * IIC function expansion register 0 (IICX0) * Port mode register 6 (PM6) * Port register 6 (P6) (1) IIC control register 0 (IICC0) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. IICC0 register is set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from "0" to "1". Reset signal generation clears IICC0 to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 556 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFA6H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable 0 Stop operation. Reset IIC status register 0 (IICS0) 1 Enable operation. Note 1 . Stop internal operation. Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level. Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1) * Cleared by instruction * Set by instruction * Reset LREL0 Note s 2, 3 Exit from communications 0 Normal operation 1 This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0 and SDA0 lines are set to high impedance. The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0. * STT0 * SPT0 * MSTS0 * EXC0 * COI0 * TRC0 * ACKD0 * STD0 The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1) * Automatically cleared after execution * Reset * Set by instruction WREL0 Note s 2, 3 Wait cancellation 0 Do not cancel wait 1 Cancel wait. This setting is automatically cleared after wait is canceled. When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the SDA0 line goes into the high impedance state (TRC0 = 0). Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the <R> <R> IICCL0 register are reset. 2. The signals of these bits are invalid while the IICE0 bit is 0. 3. When the LREL0 and WREL0 bits are read, 0 is always read. Caution 2 If the operation of I C is enabled (IICE0 = 1) when the SCL0 line is high level, the SDA0 line is low level, and the digital filter is turned on (DFC0 of the IICCL0 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by using a 1-bit memory 2 manipulation instruction immediately after enabling operation of I C (IICE0 = 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 557 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-5. Format of IIC Control Register 0 (IICC0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) * Cleared by instruction * Reset * Set by instruction Note 1 WTIM0 0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1, 2 ACKE0 Acknowledgment control 0 Disable acknowledgment. 1 Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1. This flag's signal is invalid when IICE0 = 0. 2. The set value is invalid during address transfer and if the code is not an extension code. When the device serves as a slave and the addresses match, an acknowledge is generated regardless of the set value. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 558 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4) <R> STT0 Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: * When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSV = 1) Even if this bit is set (1), the STT0 is cleared and the STT0 clear flag (STCF) is set (1). No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as stop condition trigger (SPT0). * Setting the STT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1) * Cleared by setting SST0 bit to 1 while communication * Set by instruction reservation is prohibited. * Cleared by loss in arbitration * Cleared after start condition is generated by master device * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Note The signal of this bit is invalid while IICE0 is 0. Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting. 2. IICRSV: Bit 0 of IIC flag register (IICF0) STCF: Bit 7 of IIC flag register (IICF0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 559 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 <R> Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device's transfer). Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as start condition trigger (STT0). * SPT0 bit can be set to 1 only when in master mode. * When WTIM0 has been cleared to 0, if SPT0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 bit should be set to 1 during the wait period that follows the output of the ninth clock. * Setting SPT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Caution When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0) of the IICC0 register is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared (reception status) and the SDA0 line is set to high impedance. Release the wait performed while the TRC bit is 1 (transmission status) by writing to the IIC shift register. Remark Bit 0 (SPT0) becomes 0 when it is read after data setting. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 560 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (2) IIC status register 0 (IICS0) This register indicates the status of I2C. IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears IICS0 to 00H. Caution If data is read from IICS0 register, a wait cycle is generated. Do not read data from IICS0 register when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. Figure 18-6. Format of IIC Status Register 0 (IICS0) (1/3) Address: FFAAH After reset: 00H R Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 MSTS0 Master device status 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1) * When a stop condition is detected * When ALD0 = 1 (arbitration loss) * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset * When a start condition is generated ALD0 Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". MSTS0 bit is cleared. Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1) Note * Automatically cleared after IICS0 register is read * When IICE0 changes from 1 to 0 (operation stop) * Reset EXC0 * When the arbitration result is a "loss". Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than IICS0 register. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other bits. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 561 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses 0 Addresses do not match. 1 Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) * When a start condition is detected * When the received address matches the local address * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) (slave address register 0 (SVA0)) (set at the rising edge of the eighth clock). * When IICE0 changes from 1 to 0 (operation stop) * Reset TRC0 Detection of transmit/receive status 0 Receive status (other than transmit status). The SDA0 line is set for high impedance. 1 Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the falling edge of the first byte's ninth clock). <R> Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1) <Both master and slave> * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) Note * Cleared by WREL0 = 1 (wait cancel) * When the ALD0 bit changes from 0 to 1 (arbitration loss) * Reset * When not used for communication (MSTS0, EXC0, COI0 = 0) <Master> * When "1" is output to the first byte's LSB (transfer direction specification bit) <Slave> * When a start condition is detected * When "0" is input to the first byte's LSB (transfer direction specification bit) <Master> * When a start condition is generated * When 0 (master transmission) is output to the LSB (transfer direction specification bit) of the first byte (during address transfer) <Slave> * When 1 (slave transmission) is input to the LSB (transfer direction specification bit) of the first byte from the master (during address transfer) Note When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0) of the IIC control register 0 (IICC0) is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high impedance. Release the wait performed while TRC0 bit is 1 (transmission status) by writing to the IIC shift register. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 562 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-6. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) * When a stop condition is detected * After the SDA0 line is set to low level at the rising edge of ninth clock of SCL0 line * At the rising edge of the next byte's first clock * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset STD0 Detection of start condition 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect. Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset SPD0 Detection of stop condition 0 Stop condition was not detected. 1 Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When IICE0 changes from 1 to 0 (operation stop) * Reset Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) (3) IIC flag register 0 (IICF0) This register sets the operation mode of I2C and indicates the status of the I2C bus. This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF) 2 and I C bus status flag (IICBSY) are read-only. The IICRSV bit can be used to enable/disable the communication reservation function. The STCEN bit can be used to set the initial value of the IICBSY bit. The IICRSV and STCEN bits can be written only when the operation of I2C is disabled (bit 7 (IICE0) of the IIC control register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read. Reset signal generation clears this register to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 563 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-7. Format of IIC Flag Register 0 (IICF0) Address: FFABH After reset: 00H R/WNote Symbol <7> <6> 5 4 3 2 <1> <0> IICF0 STCF IICBSY 0 0 0 0 STCEN IICRSV STT0 clear flag STCF 0 Generate start condition 1 Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF = 0) Condition for setting (STCF = 1) * Cleared by STT0 = 1 * When IICE0 = 0 (operation stop) * Reset * Generating start condition unsuccessful and STT0 bit cleared to 0 when communication reservation is disabled (IICRSV = 1). I2C bus status flag IICBSY 0 Bus release status (communication initial status when STCEN = 1) 1 Bus communication status (communication initial status when STCEN = 0) Condition for clearing (IICBSY = 0) Condition for setting (IICBSY = 1) * Detection of stop condition * When IICE0 = 0 (operation stop) * Reset * Detection of start condition * Setting of IICE0 bit when STCEN = 0 STCEN Initial start enable trigger 0 After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of a stop condition. 1 After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting a stop condition. Condition for clearing (STCEN = 0) Condition for setting (STCEN = 1) * Detection of start condition * Reset * Set by instruction IICRSV Communication reservation function disable bit 0 Enable communication reservation 1 Disable communication reservation Condition for clearing (IICRSV = 0) Condition for setting (IICRSV = 1) * Cleared by instruction * Reset * Set by instruction Note Bits 6 and 7 are read-only. Cautions 1. Write to STCEN bit only when the operation is stopped (IICE0 = 0). 2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to IICRSV bit only when the operation is stopped (IICE0 = 0). Remark STT0: Bit 1 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 564 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (4) IIC clock selection register 0 (IICCL0) This register is used to set the transfer clock for the I2C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion register 0 (IICX0) (see 18.3 (6) I2C transfer clock setting method). Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation clears IICCL0 to 00H. Figure 18-8. Format of IIC Clock Selection Register 0 (IICCL0) Address: FFA8H After reset: 00H R/W Note Symbol 7 6 <5> <4> <3> <2> 1 0 IICCL0 0 0 CLD0 DAD0 SMC0 DFC0 CL01 CL00 CLD0 Detection of SCL0 pin level (valid only when IICE0 = 1) 0 The SCL0 pin was detected at low level. 1 The SCL0 pin was detected at high level. Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1) * When the SCL0 pin is at low level * When the SCL0 pin is at high level * When IICE0 = 0 (operation stop) * Reset DAD0 Detection of SDA0 pin level (valid only when IICE0 = 1) 0 The SDA0 pin was detected at low level. 1 The SDA0 pin was detected at high level. Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1) * When the SDA0 pin is at low level * When the SDA0 pin is at high level * When IICE0 = 0 (operation stop) * Reset SMC0 Operation mode switching 0 Operates in standard mode. 1 Operates in high-speed mode. DFC0 Digital filter operation control 0 Digital filter off. 1 Digital filter on. Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0). The digital filter is used for noise elimination in high-speed mode. Note Bits 4 and 5 are read-only. Remark IICE0: Bit 7 of IIC control register 0 (IICC0) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 565 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I2C. IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 18.3 (6) I2C transfer clock setting method). Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation clears IICX0 to 00H. Figure 18-9. Format of IIC Function Expansion Register 0 (IICX0) Address: FFA9H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> IICX0 0 0 0 0 0 0 0 CLX0 (6) I2C transfer clock setting method The I2C transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 12, 18, 24, 44, 66, 86 (see Table 18-2 Selection Clock Setting) T: 1/fW tR: SCL0 rise time tF: SCL0 fall time For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(88 x 238.7 ns + 200 ns + 50 ns) 48.1 kHz m x T + tR + tF tR m/2 x T tF m/2 x T SCL0 SCL0 inversion R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 SCL0 inversion SCL0 inversion 566 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0). Table 18-2. Selection Clock Setting IICX0 Selection Clock IICCL0 Transfer Clock Settable Selection Clock (fW/m) (fW) Range Notes 1, 2 (fW) Operation Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 0 0 0 0 fPRS/2 fW/44 2.00 to 4.19 MHz Normal mode 0 0 0 1 fPRS/2 fW/86 4.19 to 8.38 MHz (SMC0 bit = 0) 0 0 1 0 fPRS/4 fW/86 Notes 3, 4 0 0 1 1 fEXSCL0 fW/66 6.4 MHz 0 1 0 x fPRS/2 fW/24 4.00 to 8.38 MHz 0 1 1 0 fPRS/4 fW/24 0 1 1 1 fEXSCL0 1 0 x x Setting prohibited 1 1 0 x 1 1 1 1 1 1 Note 3, 4 High-speed mode (SMC0 bit = 1) fW/18 6.4 MHz fPRS/2 fW/12 4.00 to 4.19 MHz 0 fPRS/4 fW/12 1 Setting prohibited High-speed mode (SMC0 bit = 1) Notes 1. The frequency that can be used for the peripheral hardware clock (fPRS) differs depending on the power supply voltage and product specifications. Supply Voltage Conventional-specification Products Expanded-specification Products (PD78F05xx and 78F05xxD) (PD78F05xxA and 78F05xxDA) 4.0 V VDD 5.5 V fPRS 20 MHz 2.7 V VDD < 4.0 V fPRS 10 MHz 1.8 V VDD < 2.7 V fPRS 5 MHz fPRS 20 MHz fPRS 5 MHz (Standard products and (A) grade products only) (The values shown in the table above are those when fPRS = fXH (XSEL = 1).) 2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fXH) (XSEL = 0), set CLX0, SMC0, CL01 and CL00 as follows. IICX0 IICCL0 Selection Clock Transfer Clock Settable Selection (fW) (fW/m) Clock (fW) Range Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 0 0 0 0 fPRS/2 fW/44 3.8 MHz to 4.2 MHz Operation Mode Normal mode (SMC0 bit = 0) 0 1 0 x fPRS/2 fW/24 High-speed mode (SMC0 bit = 1) 3. This must not be set, because the 78K0/KB2 products are not mounted with the EXSCL0 pin. 4. Do not start communication with the external clock from the EXSCL0 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Caution Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 567 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Remarks 1. x: don't care 2. fPRS: Peripheral hardware clock frequency 3. fEXSCL0: External clock frequency from EXSCL0 pin (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0 and P61/SDA0 pins output a low level (fixed) when IICE0 is 0. PM6 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM6 to FFH. Figure 18-10. Format of Port Mode Register 6 (PM6) Address: FF26H Symbol PM6 R/W 7 6 5 4 3 2 1 0 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM6n Remark After reset: FFH P6n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) The figure shown above presents the format of port mode register 6 of 78K0/KF2 products. For the format of port mode register 6 of other products, see (1) Port mode registers (PMxx) in 5.3 Registers Controlling Port Function. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 568 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.4 I2C Bus Mode Functions 18.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0....... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDA0 ...... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 18-11. Pin Configuration Diagram Slave device VDD Master device SCL0 SCL0 Clock output (Clock output) VDD VSS VSS (Clock input) Clock input SDA0 SDA0 Data output Data output VSS Data input R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 VSS Data input 569 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 18-12 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus. Figure 18-12. I2C Bus Serial Data Transfer Timing SCL0 1-7 8 9 1-8 9 1-8 9 ACK Data ACK SDA0 Start condition Address R/W ACK Data Stop condition The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0's low level period can be extended and a wait can be inserted. 18.5.1 Start conditions A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected. Figure 18-13. Start Conditions SCL0 H SDA0 A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of IICS0 is set (to 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 570 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 register values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 18-14. Address SCL0 1 2 3 4 5 6 7 8 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Address Note INTIIC0 Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. The slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 Transfer direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received addresses are written to IIC0. The slave address is assigned to the higher 7 bits of IIC0 register. 18.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device. Figure 18-15. Transfer Direction Specification SCL0 1 2 3 4 5 6 7 8 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Transfer direction specification INTIIC0 Note Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 571 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows. <1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist. To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0) of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 bit to 1 for reception (TRC0 = 0). If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the slave must inform the master, by clearing ACKE0 bit to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 bit to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). Figure 18-16. ACK SCL0 1 2 3 4 5 6 7 8 9 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W ACK When the local address is received, ACK is automatically generated, regardless of the value of ACKE0 bit. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if ACKE0 bit is set to 1 in advance. How ACK is generated when data is received differs as follows depending on the setting of the wait timing. * When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0): By setting ACKE0 bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the SCL0 pin. * When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1): ACK is generated by setting ACKE0 bit to 1 in advance. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 572 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 18-17. Stop Condition SCL0 H SDA0 A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4 (SPIE0) of IICC0 register is set to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 573 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 18-18. Wait (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master returns to high impedance but slave is in wait state (low level). IIC0 Wait after output of ninth clock IIC0 data write (cancel wait) SCL0 6 7 8 9 1 2 3 Slave Wait after output of eighth clock FFH is written to IIC0 or WREL0 is set to 1 IIC0 SCL0 ACKE0 H Transfer lines Wait from slave SCL0 6 7 8 SDA0 D2 D1 D0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Wait from master 9 ACK 1 2 3 D7 D6 D5 574 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-18. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IIC0 data write (cancel wait) IIC0 6 SCL0 7 8 9 1 2 3 Slave FFH is written to IIC0 or WREL0 is set to 1 IIC0 SCL0 ACKE0 H Wait from master and slave Transfer lines SCL0 6 7 8 9 SDA0 D2 D1 D0 ACK Wait from slave 1 D7 2 3 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0: Bit 2 of IIC control register 0 (IICC0) WREL0: Bit 5 of IIC control register 0 (IICC0) A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0). Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 register is set to 1 or when FFH is written to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0 register. The master device can also cancel the wait state via either of the following methods. * By setting bit 1 (STT0) of IICC0 register to 1 * By setting bit 0 (SPT0) of IICC0 register to 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 575 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.7 Canceling wait The I2C usually cancels a wait state by the following processing. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note Note Master only When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed. To cancel a wait state and transmit data (including addresses), write the data to IIC0 register. To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control register 0 (IICC0) to 1. To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 register to 1. To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 register to 1. Execute the canceling processing only once for one wait state. If, for example, data is written to IIC0 register after canceling a wait state by setting WREL0 bit to 1, an incorrect value may be output to SDA0 line because the timing for changing the SDA0 line conflicts with the timing for writing IIC0 register. In addition to the above, communication is stopped if IICE0 bit is cleared to 0 when communication has been aborted, so that the wait state can be canceled. If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of IICC0 register, so that the wait state can be canceled. 18.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 18-3. Table 18-3. INTIIC0 Generation Timing and Wait Control WTIM0 During Slave Device Operation Address 0 1 9 Notes 1, 2 9 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 Notes 1. The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (SVA0). At this point, ACK is generated regardless of the value set to bit 2 (ACKE0) of the IICC0 register. For a slave device that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. If the received address does not match the contents of slave address register 0 (SVA0) and extension code is not received, neither INTIIC0 nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 576 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIM0 bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note Note Master only. When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be determined prior to wait cancellation. (5) Stop condition detection INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1). 18.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.10 Error detection In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0 (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 577 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.11 Extension code (1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected. (2) If "11110xx0" is set to SVA0 register by a 10-bit address transfer and "11110xx0" is transferred from the master device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXC0 = 1 * Seven bits of data match: Remark COI0 = 1 EXC0: Bit 5 of IIC status register 0 (IICS0) COI0: Bit 4 of IIC status register 0 (IICS0) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next communication operation. Table 18-4. Bit Definitions of Main Extension Code Slave Address R/W Bit Description 0000 000 0 General call address 1111 0xx 0 10-bit slave address specification (for address authentication) 1111 0xx 1 10-bit slave address specification (for read command issuance after address match) Remark For extension codes other than the above, refer to THE I2C-BUS SPECIFICATION published by NXP. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 578 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0) is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. For details of interrupt request timing, see 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence. Remark STD0: Bit 1 of IIC status register 0 (IICS0) STT0: Bit 1 of IIC control register 0 (IICC0) Figure 18-19. Arbitration Timing Example Master 1 SCL0 SDA0 Master 2 Hi-Z Hi-Z Master 1 loses arbitration SCL0 SDA0 Transfer lines SCL0 SDA0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 579 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Table 18-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data transmission When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1) When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transfer Note 1 condition When stop condition is detected while attempting to generate a Note 2 When stop condition is generated (when SPIE0 = 1) restart condition When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transfer Note 1 condition When SCL0 is at low level while attempting to generate a restart condition Notes 1. When WTIM0 bit (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM0 = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation. Remark SPIE0: Bit 4 of IIC control register 0 (IICC0) 18.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 580 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1). If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to IIC0 before the stop condition is detected is invalid. When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. * If the bus has been released ........................................ a start condition is generated * If the bus has not been released (standby mode)......... communication reservation Check whether the communication reservation operates or not by using MSTS0 bit (bit 7 of IIC status register 0 (IICS0)) after STT0 bit is set to 1 and the wait time elapses. The wait periods, which should be set via software, are listed in Table 18-6. Table 18-6. Wait Periods CLX0 SMC0 CL01 CL00 Wait Period 0 0 0 0 46 clocks 0 0 0 1 86 clocks 0 0 1 0 172 clocks 0 0 1 1 34 clocks 0 1 0 0 30 clocks 0 1 0 1 0 1 1 0 60 clocks 0 1 1 1 12 clocks 1 1 0 0 18 clocks 1 1 0 1 1 1 1 0 36 clocks Figure 18-20 shows the communication reservation timing. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 581 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-20. Communication Reservation Timing Program processing Write to IIC0 STT0 = 1 CommuniHardware processing cation reservation SCL0 1 2 3 4 Set SPD0 and INTIIC0 5 6 7 8 9 Set STD0 1 2 3 4 5 6 SDA0 Generate by master device with bus mastership Remark IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0) STD0: Bit 1 of IIC status register 0 (IICS0) SPD0: Bit 0 of IIC status register 0 (IICS0) Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0 (IICC0) to 1 before a stop condition is detected. Figure 18-21. Timing for Accepting Communication Reservations SCL0 SDA0 STD0 SPD0 Standby mode Figure 18-22 shows the communication reservation protocol. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 582 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-22. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note Yes MSTS0 = 0? Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait period set by software (see Table 18-6). Confirmation of communication reservation No (Generate start condition) Cancel communication reservation MOV IIC0, #xxH Clear user flag IIC0 write operation EI Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop condition interrupt request occurs. Remark STT0: Bit 1 of IIC control register 0 (IICC0) MSTS0: Bit 7 of IIC status register 0 (IICS0) IIC0: IIC shift register 0 (2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1) When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IICC0 register was set to 1) To confirm whether the start condition was generated or request was rejected, check STCF flag (bit 7 of IICF0). The time shown in Table 18-7 is required until STCF flag is set to 1 after setting STT0 = 1. Therefore, secure the time by software. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 583 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Table 18-7. Wait Periods CL01 CL00 Wait Period 0 0 6 clocks 0 1 6 clocks 1 0 12 clocks 1 1 3 clocks 18.5.15 Cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY flag (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. <1> Set IIC clock selection register 0 (IICCL0). <2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1. <3> Set bit 0 (SPT0) of IICC0 to 1. (2) When STCEN = 1 Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this interferes with other I2C communications. To avoid this, start I2C in the following sequence. <1> Clear bit 4 (SPIE0) of IICC0 register to 0 to disable generation of an interrupt request signal (INTIIC0) when the stop condition is detected. <2> Set bit 7 (IICE0) of IICC0 register to 1 to enable the operation of I2C. <3> Wait for detection of the start condition. <4> Set bit 6 (LREL0) of IICC0 register to 1 before ACK is returned (4 to 80 clocks after setting IICE0 bit to 1), to forcibly disable detection. (4) Determine the transfer clock frequency by using SMC0, CL01, CL00 bits (bits 3, 1, and 0 of IICL0 register), and CLX0 bit (bit 0 of IICX0 register) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 bit to 0 once. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 584 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (5) Setting STT0 and SPT0 bits (bits 1 and 0 of IICC0 register) again after they are set and before they are cleared to 0 is prohibited. (6) When transmission is reserved, set SPIE0 bit (bit 4 of IICL0 register) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to IIC status register 0 (IICS0) after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set SPIE0 bit to 1 when MSTS0 bit (bit 7 of IIC status register 0 (IICS0) is detected by software. 18.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the 78K0/Kx2 microcontrollers as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the 78K0/Kx2 microcontrollers takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the 78K0/Kx2 microcontrollers looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the 78K0/Kx2 microcontrollers is used as the I2C bus slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIIC0 interrupt occurrence (communication waiting). When an INTIIC0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 585 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (1) Master operation in single-master system Figure 18-23. Master Operation in Single-Master System START Initializing I2C busNote IICX0 0XH IICCL0 XXH Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN, IICRSV = 0 Sets a start condition. Initial setting IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 Setting port STCEN = 1? Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). Yes No SPT0 = 1 INTIIC0 Interrupt occurs? Prepares for starting communication (generates a stop condition). No Waits for detection of the stop condition. Yes STT0 = 1 Prepares for starting communication (generates a start condition). Writing IIC0 Starts communication (specifies an address and transfer direction). INTIIC0 interrupt occurs? No Waits for detection of acknowledge. Yes No ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Communication processing Yes Writing IIC0 Starts transmission. WREL0 = 1 INTIIC0 interrupt occurs? No Waits for data transmission. INTIIC0 interrupt occurs? Yes Yes ACKD0 = 1? No Starts reception. No Waits for data reception. Reading IIC0 Yes No End of transfer? No End of transfer? Yes Yes Restart? Yes ACKE0 = 0 WTIM0 = WREL0 = 1 No SPT0 = 1 INTIIC0 interrupt occurs? Yes No Waits for detection of acknowledge. END 2 Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level. Remark Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 586 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (2) Master operation in multi-master system Figure 18-24. Master Operation in Multi-Master System (1/3) START IICX0 0XH IICCL0 XXH Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN and IICRSV Sets a start condition. Initial setting IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 Setting port Checking bus statusNote Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). Releases the bus for a specific period. Bus status is being checked. No No STCEN = 1? INTIIC0 interrupt occurs? Prepares for starting communication (generates a stop condition). SPT0 = 1 Yes Yes SPD0 = 1? INTIIC0 interrupt occurs? No Yes Yes Slave operation SPD0 = 1? No Waits for detection of the stop condition. No Yes 1 Waits for a communication Slave operation * Waiting to be specified as a slave by other master * Waiting for a communication start request (depends on user program) Master operation starts? No (No communication start request) Yes (Communication start request) SPIE0 = 0 INTIIC0 interrupt occurs? SPIE0 = 1 No Waits for a communication request. Yes IICRSV = 0? No Slave operation Yes A B Enables reserving Disables reserving communication. communication. Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and SDA0 pins = high level) in conformance with the specifications of the product that is communicating. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 587 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-24. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Secure wait time by software (see Table 18-6). Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIIC0 interrupt occurs? Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function. EXC0 = 1 or COI0 =1? Yes C Slave operation B Disables reserving communication. IICBSY = 0? No Yes D Communication processing No Waits for bus release (communication being reserved). STT0 = 1 Wait STCF = 0? Yes Prepares for starting communication (generates a start condition). Secure wait time by software (see Table 18-7). No INTIIC0 interrupt occurs? No Waits for bus release Yes C EXC0 = 1 or COI0 =1? No Detects a stop condition. Yes Slave operation R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 D 588 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-24. Master Operation in Multi-Master System (3/3) C Writing IIC0 INTIIC0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IIC0 INTIIC0 interrupt occurs? INTIIC0 interrupt occurs? No Waits for data transmission. Yes MSTS0 = 1? No Waits for data reception. Yes MSTS0 = 1? No No Yes Yes ACKD0 = 1? Starts reception. Starts transmission. 2 2 Reading IIC0 No Transfer end? No Yes Yes No WTIM0 = WREL0 = 1 ACKE0 = 0 Transfer end? Yes Restart? INTIIC0 interrupt occurs? No No Waits for detection of ACK. Yes SPT0 = 1 Yes MSTS0 = 1? STT0 = 1 END Yes No 2 Communication processing C 2 EXC0 = 1 or COI0 = 1? Yes Slave operation No 1 Does not participate in communication. Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIIC0 has occurred to check the arbitration result. 3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0 registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed next. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 589 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication. It is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. INTIIC0 Flag Interrupt servicing Setting Main processing IIC0 Data Setting Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIIC0. <1> Communication mode flag This flag indicates the following two communication statuses. * Clear mode: Status in which data communication is not performed * Communication mode: Status in which data communication is performed (from valid address detection to stop condition detection, no detection of ACK from master, address mismatch) <2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> Communication direction flag This flag indicates the direction of communication. Its value is the same as TRC0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 590 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way. Figure 18-25. Slave Operation Flowchart (1) START IICX0 0XH Selects a transfer clock. IICCL0 XXH Initial setting SVA0 XXH Sets a local address. IICF0 0XH Sets a start condition. Setting IICRSV IICC0 XXH ACKE0 = WTIM0 = 1 SPIE0 = 0, IICE0 = 1 Setting port No Sets each pin to the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). Communication mode flag = 1? Yes Communication direction flag = 1? No Yes WREL0 = 1 Writing IIC0 Communication processing No Communication mode flag = 1? Communication mode flag = 1? No Yes Yes No Starts reception. Starts transmission. Communication direction flag = 0? Communication direction flag = 1? No Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes Reading IIC0 Clearing ready flag Yes Clearing ready flag ACKD0 = 1? No Clearing communication mode flag WREL0 = 1 Remark Conform to the specifications of the product that is in communication, regarding the transmission and reception formats. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 591 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state. Remark <1> to <3> above correspond to <1> to <3> in Figure 18-26 Slave Operation Flowchart (2). Figure 18-26. Slave Operation Flowchart (2) INTIIC0 generated Yes <1> Yes <2> SPD0 = 1? No STD0 = 1? No No <3> COI0 = 1? Yes Set ready flag Communication direction flag TRC0 Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 592 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below. Remark ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 593 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B 3: IICS0 = 1000x000B (Sets WTIM0 to 1Note) 4: IICS0 = 1000xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B 3: IICS0 = 1000xx00B (Sets SPT0 to 1) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 594 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1Note 1) 3: IICS0 = 1000xx00B (Clears WTIM0 to 0Note 2, sets STT0 to 1) 4: IICS0 = 1000x110B 5: IICS0 = 1000x000B (Sets WTIM0 to 1Note 3) 6: IICS0 = 1000xx00B (Sets SPT0 to 1) 7: IICS0 = 00000001B Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. 2. Clear WTIM0 to 0 to restore the original setting. 3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 SPT0 = 1 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 1000x110B 4: IICS0 = 1000xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 595 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1010x110B 2: IICS0 = 1010x000B 3: IICS0 = 1010x000B (Sets WTIM0 to 1Note) 4: IICS0 = 1010xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 1010x110B 2: IICS0 = 1010x100B 3: IICS0 = 1010xx00B (Sets SPT0 to 1) 4: IICS0 = 00001001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 596 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 597 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0001x110B 4: IICS0 = 0001xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 598 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 4 ACK SP 5 6 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0010x010B 4: IICS0 = 0010x110B 5: IICS0 = 0010xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 599 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 600 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 601 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0001x110B 5: IICS0 = 0001xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 602 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 5 ACK SP 6 7 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0010x010B 5: IICS0 = 0010x110B 6: IICS0 = 0010xx00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 603 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 00100010B 2: IICS0 = 00100000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 1: IICS0 = 00100010B 2: IICS0 = 00100110B 3: IICS0 = 00100x00B 4: IICS0 = 00000110B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 604 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 605 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0110x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 606 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0110x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK SP 2 1: IICS0 = 01000110B 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 607 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICS0 = 0110x010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 608 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01000110B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 609 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 610 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets STT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 611 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000xx00B (Sets STT0 to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 612 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets SPT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 613 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 18.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figures 18-27 and 18-28 show timing charts of the data communication. IIC shift register 0 (IIC0)'s shift operation is synchronized with the falling edge of the serial clock (SCL0). The transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin. Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 614 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 address IIC0 IIC0 data Note 1 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 STT0 SPT0 L WREL0 L INTIIC0 TRC0 Transmit Transfer lines 1 SCL0 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0 8 9 1 2 3 4 W ACK D7 D6 D5 D4 Start condition Processing by slave device IIC0 FFH Note 2 IIC0 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Note 2 WREL0 INTIIC0 TRC0 L Receive Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission. 2. To cancel slave wait, write "FFH" to IIC0 or set WREL0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 615 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 data Note 1 IIC0 IIC0 data Note 1 ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 H STT0 L SPT0 L WREL0 L INTIIC0 TRC0 H Transmit Transfer lines SCL0 8 9 1 2 3 4 5 6 7 8 9 SDA0 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 D7 D6 D5 Processing by slave device IIC0 FFH Note 2 IIC0 IIC0 FFH Note 2 ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Note 2 WREL0 Note 2 INTIIC0 TRC0 L Receive Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission. 2. To cancel slave wait, write "FFH" to IIC0 or set WREL0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 616 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 data Note 1 IIC0 IIC0 address ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 STT0 SPT0 WREL0 L INTIIC0 (When SPIE0 = 1) Transmit TRC0 Transfer lines SCL0 1 2 3 4 5 6 7 8 9 SDA0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Processing by slave device IIC0 FFH Note 2 IIC0 1 2 AD6 AD5 Stop condition Start condition IIC0 FFH Note 2 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 Note 2 Note 2 INTIIC0 TRC0 L Receive (When SPIE0 = 1) Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission. 2. To cancel slave wait, write "FFH" to IIC0 or set WREL0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 617 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 address IIC0 IIC0 FFH Note 1 ACKD0 STD0 SPD0 WTIM0 L ACKE0 H MSTS0 STT0 L SPT0 Note 1 WREL0 INTIIC0 TRC0 Receive Transmit Transfer lines 1 SCL0 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0 8 9 R ACK 1 D7 2 3 4 5 6 D6 D5 D4 D3 D2 Processing by slave device IIC0 data Note 2 IIC0 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 L INTIIC0 TRC0 Receive Transmit Notes 1. To cancel master wait, write "FFH" to IIC0 or set WREL0. 2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 618 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IIC0 FFH Note 1 IIC0 IIC0 FFH Note 1 ACKD0 STD0 L SPD0 L WTIM0 L ACKE0 H MSTS0 H STT0 L SPT0 L Note 1 WREL0 Note 1 INTIIC0 TRC0 Receive L Transfer lines SCL0 8 9 SDA0 D0 ACK 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK 1 2 3 D7 D6 D5 Processing by slave device IIC0 data Note 2 IIC0 IIC0 data Note 2 ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 L INTIIC0 TRC0 H Transmit Notes 1. To cancel master wait, write "FFH" to IIC0 or set WREL0. 2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 619 78K0/Kx2 CHAPTER 18 SERIAL INTERFACE IIC0 Figure 18-28. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device IIC0 address IIC0 FFH Note 1 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 Note 1 WREL0 INTIIC0 (When SPIE0 = 1) TRC0 Receive Transfer lines SCL0 1 2 3 4 5 6 7 8 SDA0 D7 D6 D5 D4 D3 D2 D1 D0 9 1 AD6 NACK Stop condition Start condition Processing by slave device IIC0 data Note 2 IIC0 IIC0 FFH Note 1 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Notes 1, 3 WREL0 INTIIC0 (When SPIE0 = 1) TRC0 Transmit Note 3 Receive Notes 1. To cancel wait, write "FFH" to IIC0 or set WREL0. 2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission. 3. If a wait state during slave transmission is canceled by setting WREL0, TRC0 will be cleared. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 620 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER CHAPTER 19 MULTIPLIER/DIVIDER 78K0/KB2 78K0/KC2 78K0/KE2 78K0/KF2 Products whose flash memory is less than 32 KB: - - Multiplier/divider 78K0/KD2 Products whose flash memory is at least 48 KB: Remark : Mounted, -: Not mounted Caution Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface IIC0 and the multiplier/divider. 19.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits, 16-bit remainder (division) 19.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 19-1. Configuration of Multiplier/Divider Item Registers Configuration Remainder data register 0 (SDR0) Multiplication/division data registers A0 (MDA0H, MDA0L) Multiplication/division data registers B0 (MDB0) Control register Multiplier/divider control register 0 (DMUC0) Figure 19-1 shows the block diagram of the multiplier/divider. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 621 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 19-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 (MDB0 (MDB0H + MDB0L) Remainder data register 0 (SDR0 (SDR0H + SDR0L) Multiplication/division data register A0 (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) DMUSEL0 DMUE Start MDA000 INTDMU Clear Controller Controller 6-bit counter fPRS 17-bit adder Controller CHAPTER 19 MULTIPLIER/DIVIDER 622 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears SDR0 to 0000H. Figure 19-2. Format of Remainder Data Register 0 (SDR0) Address: FF60H, FF61H After reset: 0000H Symbol R FF61H (SDR0H) SDR0 FF60H (SDR0L) SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. 2. SDR0 is reset when the operation is started (when DMUE is set to 1). (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 19-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) Address: FF62H, FF63H, FF64H, FF65H Symbol MDA0H R/W FF64H (MDA0HL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 031 030 029 Symbol MDA0L After reset: 0000H, 0000H FF65H (MDA0HH) 028 027 026 025 024 023 022 021 FF63H (MDA0LH) 020 019 018 017 016 FF62H (MDA0LL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). 2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 623 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 19-2. Functions of MDA0 During Operation Execution DMUSEL0 Remark Operation Mode Setting Operation Result 0 Division mode Dividend Division result (quotient) 1 Multiplication mode Higher 16 bits: 0, Lower Multiplication result 16 bits: Multiplier A (product) DMUSEL0: Bit 0 of multiplier/divider control register 0 (DMUC0) The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDA0 (bits 15 to 0) x MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) * Register configuration during division <Dividend> <Divisor> <Quotient> <Remainder> MDA0 (bits 31 to 0) / MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) ... SDR0 (bits 15 to 0) MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is set to 1. MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears MDA0H and MDA0L to 0000H. (3) Multiplication/division data register B0 (MDB0) MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the division mode. MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears MDB0 to 0000H. Figure 19-4. Format of Multiplication/Division Data Register B0 (MDB0) Address: FF66H, FF67H After reset: 0000H Symbol MDB0 R/W FF67H (MDB0H) FF66H (MDB0L) MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 624 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER 19.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears DMUC0 to 00H. Figure 19-5. Format of Multiplier/Divider Control Register 0 (DMUC0) Address: FF68H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 DMUC0 DMUE 0 0 0 0 0 0 DMUSEL0 DMUENote Operation start/stop 0 Stops operation 1 Starts operation DMUSEL0 Operation mode (multiplication/division) selection 0 Division mode 1 Multiplication mode Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is complete. Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). 3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 625 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER 19.4 Operations of Multiplier/Divider 19.4.1 Multiplication operation * Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. * During operation 3. The operation will be completed when 16 peripheral hardware clocks (fPRS) have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The operation result data is stored in the MDA0L and MDA0H registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 19.4.2 Division operation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 626 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 19-6. Timing Chart of Multiplication Operation (00DAH x 0093H) fPRS DMUE DMUSEL0 Internal clock 0 Counter XXXX SDR0 MDA0 XXXX XXXX MDB0 XXXX 2 3 4 5 6 7 8 9 A B C D E F 10 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00DA 0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000 006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E 0 0093 627 CHAPTER 19 MULTIPLIER/DIVIDER INTDMU XXXX 00DA 1 78K0/Kx2 CHAPTER 19 MULTIPLIER/DIVIDER 19.4.2 Division operation * Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start. * During operation 3. The operation will be completed when 32 peripheral hardware clocks (fPRS) have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 19.4.2 Division operation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 628 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 19-7. Timing Chart of Division Operation (DCBA2586H / 0018H) fPRS DMUE DMUSEL0 "0" Internal clock 0 Counter XXXX SDR0 0000 MDA0 XXXX XXXX DCBA 2586 MDB0 XXXX 0018 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 4B0C 0C12 64D8 72E8 9618 E5D1 CBA2 2C30 5860 9744 B0C1 2E89 6182 5D12 C304 BA25 8609 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D 0 0932 6C3A 629 CHAPTER 19 MULTIPLIER/DIVIDER INTDMU 1 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS CHAPTER 20 INTERRUPT FUNCTIONS 78K0/KB2 Maskable External 6 78K0/KC2 38/44 pins: 7 ch 48 pins: interrupts internal 14 78K0/KD2 78K0/KE2 78K0/KF2 Products Products whose flash whose flash memory is memory is at less than least 32 KB 48 KB 8 9 9 9 16 16 19 20 8 ch 16 20.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored interrupt servicing. For the priority order, see Table 20-1. A standby release signal is generated and STOP and HALT modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 20.2 Interrupt Sources and Configuration The interrupt sources consist of maskable interrupts and software interrupts. In addition, they also have up to four reset sources (see Table 20-1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 630 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Table 20-1. Interrupt Source List (1/2) Interrupt Internal/ Type Basic Default External Configuration Priority Note 1 Interrupt Source Note 2 Name Trigger Type Maskable Internal External Internal Note 3 Vector K K K K K Table B C D E F Address 2 2 2 2 2 0004H 0006H (A) 0 INTLVI Low-voltage detection (B) 1 INTP0 Pin input edge detection 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTP4 000EH 6 INTP5 0010H 7 INTSRE6 UART6 reception error generation 0012H 8 INTSR6 End of UART6 reception 0014H 9 INTST6 End of UART6 transmission 0016H 10 INTCSI10/ End of CSI10 communication/end of 0018H 001AH 001CH 001EH 0020H 0022H (A) INTST0 11 UART0 transmission INTTMH1 Match between TMH1 and CMP01 (when compare register is specified) 12 INTTMH0 Match between TMH0 and CMP00 (when compare register is specified) 13 INTTM50 Match between TM50 and CR50 (when compare register is specified) 14 INTTM000 Match between TM00 and CR000 (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 15 INTTM010 Match between TM00 and CR010 (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) 16 INTAD End of A/D conversion 0024H 17 INTSR0 End of UART0 reception or reception 0026H error generation 18 19 Notes 1. 2. INTWTI Watch timer reference time interval signal 0028H - INTTM51 Match between TM51 and CR51 002AH Note 4 (when compare register is specified) Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1. The default priority determines the sequence of processing vectored interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority. 3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0. 4. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 631 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Table 20-1. Interrupt Source List (2/2) Interrupt Internal/ Type Basic Default External Configuration Priority Interrupt Source Vector K K K K K Table B C D E F Address 2 2 2 2 2 Note 2 Note 1 Name Trigger Type (C) 20 INTKR Key interrupt detection 002CH - Internal (A) 21 INTWT Watch timer overflow 002EH - External (B) 22 INTP6 Pin input edge detection 0030H - - Maskable External Note 4 Internal (A) 23 INTP7 24 INTIIC0/ End of IIC0 communication/end of INTDMU multiply/divide operation 25 0032H INTCSI11 End of CSI11 communication 0034H 0036H - - Note 5 Note 5 Note 5 Note 5 - - - Note 6 26 INTTM001 Match between TM01 and CR001 0038H - - - Note 6 (when compare register is specified), TI011 pin valid edge detection (when capture register is specified) 27 INTTM011 Match between TM01 and CR011 003AH - - - Note 6 (when compare register is specified), TI001 pin valid edge detection (when capture register is specified) 28 INTACSI End of CSIA0 communication 003CH - - - - Software - (D) - BRK BRK instruction execution 003EH Reset - - - RESET Reset input 0000H POC Power-on clear LVI Low-voltage detection WDT WDT overflow Notes 1. 2. Note 3 Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1. The default priority determines the sequence of processing vectored interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority. 3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1. 4. 48-pin products only. 5. INTIIC0: products with the flash memory of 32 KB or less INTIIC0/INTDMU: products with the flash memory of 48 KB or more 6. Products with the flash memory of 48 KB or more only. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 632 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Priority controller IF Vector table address generator Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge enable register (EGP, EGN) Interrupt request Edge detector MK IE IF PR ISP Priority controller Vector table address generator Standby release signal Remark n = 0 to 5: 78K0/KB2, 38-pin and 44-pin products of 78K0/KC2 n = 0 to 6: 78K0/KD2, 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KE2, 78K0/KF2 IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 633 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-1. Basic Configuration of Interrupt Function (2/2) <R> (C) External maskable interrupt (INTKR) Internal bus Key return mode register (KRM) MK IE PR1 ISP1 KRMn Key interrupt detector KRn pin input Priority controller IF Vector table address generator Standby release signal Remark n = 0, 1: 38-pin products of 78K0/KC2 n = 0 to 3: 44-pin and 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KD2, 78K0/KE2, 78K0/KF2 (D) Software interrupt Internal bus Interrupt request IF: Priority controller Vector table address generator Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag KRM: Key return mode register R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 634 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS 20.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) * Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) * Priority specification flag register (PR0L, PR0H, PR1L, PR1H) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 20-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 20-2. Flags Corresponding to Interrupt Request Sources (1/2) K K K K Interrupt B C D E F Source 2 2 2 2 2 INTLVI LVIIF INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTSRE6 SREIF6 INTSR6 SRIF6 INTST6 STIF6 INTCSI10 K INTST0 Interrupt Request Flag Interrupt Mask Flag Register IF0L Register LVIMK MK0L SREMK6 IF0H Priority Specification Flag Register LVIPR SREPR6 SRMK6 MK0H STMK6 SRPR6 PR0H STPR6 CSIIF10 DUALIF0 CSIMK10 DUALMK0 CSIPR10 DUALPR0 Note 1 Note 1 Note 2 Note 3 Note 2 STIF0 STMK0 STPR0 Note 1 Note 2 Note 3 INTTMH1 TMIFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 TMMK010 TMPR010 Notes 1. PR0L Note 3 If either interrupt source INTCSI10 or INTST0 is generated, bit 2 of IF0H is set (1). 2. Bit 2 of MK0H supports both interrupt sources INTCSI10 and INTST0. 3. Bit 2 of PR0H supports both interrupt sources INTCSI10 and INTST0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 635 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Table 20-2. Flags Corresponding to Interrupt Request Sources (2/2) K K K K Interrupt B C D K E F Source 2 2 2 2 2 INTAD ADIF INTSR0 SRIF0 SRMK0 SRPR0 - INTWTI WTIIF WTIMK WTIPR INTTM51 TMIF51 TMMK51 TMPR51 Interrupt Request Flag Interrupt Mask Flag Register IF1L Priority Specification Flag Register ADMK MK1L Register ADPR PR1L Note 4 - INTKR KRIF KRMK KRPR - INTWT WTIF WTMK WTPR INTP6 PIF6 PMK6 PPR6 - Note 1 - INTP7 PIF7 INTIIC0 IICIF0 Note 2 Note 2 Note 2 Note 2 PMK7 Note 6 IF1H PPR7 Note 7 IICMK0 MK1H IICPR0 Note 8 PR1H Note 5 INTDMU Note 6 Note 7 Note 8 DMUIF DMUMK DMUPR CSIIF11 CSIMK11 CSIPR11 INTTM001 TMIF001 TMMK001 TMPR001 INTTM011 TMIF011 TMMK011 TMPR011 INTACSI ACSIMK ACSIPR Note 5 - - - INTCSI11 Note 3 - - - Note 3 - - - Note 3 - - - Notes 1. 2. - ACSIIF 48-pin products only. INTIIC0: products whose flash memory is less than 32 KB INTIIC0/INTDMU: products whose flash memory is at least 48 KB 3. Products whose flash memory is at least 48 KB only. 4. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon the 5. Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing). interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C compiler, do not select the check box of "Using Multiplier/Divider" on GUI of PM+. 6. If either interrupt source INTIIC0 or INTDMU is generated, bit 0 of IF1H is set (1). 7. Bit 0 of MK1H supports both interrupt sources INTIIC0 and INTDMU. 8. Bit 0 of PR1H supports both interrupt sources INTIIC0 and INTDMU. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 636 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 637 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KB2) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H After reset: 00H R/W Symbol 7 6 5 4 <3> 2 <1> <0> IF1L 0 0 0 0 TMIF51 0 SRIF0 ADIF Address: FFE3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> IF1H 0 0 0 0 0 0 0 IICIF0 XXIFX Caution Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Be sure to clear bits 2, 4 to 7 of IF1L and bits 1 to 7 of IF1H to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 638 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KC2) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H Symbol After reset: 00H 7 IF1L 0 Address: FFE3H R/W <6> PIF6 Note 1 After reset: 00H <5> <4> <3> <2> <1> <0> WTIF KRIF TMIF51 WTIIF SRIF0 ADIF <0> R/W Symbol 7 6 5 4 3 2 1 IF1H 0 0 0 0 0 0 0 IICIF0 DMUIF XXIFX Note 2 Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Notes 1. 48-pin products only. 2. Products whose flash memory is at least 48 KB only. Cautions 1. Be sure to clear bits 6 and 7 of IF1L to 0 in the 38-pin and 44-pin products. Be sure to clear bit 7 of IF1L to 0 in the 48-pin products. 2. Be sure to clear bits 1 to 7 of IF1H to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 639 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-4. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KD2) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H After reset: 00H R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> IF1L 0 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF <0> Address: FFE3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 IF1H 0 0 0 0 0 0 0 IICIF0 DMUIF XXIFX Note Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Note Products whose flash memory is at least 48 KB only. Caution Be sure to clear bit 7 of 1F1L and bits 1 to 7 of IF1H to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 640 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-5. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KE2) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF 5 4 <3> <2> <1> <0> Address: FFE3H Symbol IF1H After reset: 00H 7 0 6 0 R/W 0 0 TMIF011 Note TMIF001 Note Note CSIIF11 IICIF0 DMUIF XXIFX Note Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Note Products whose flash memory is at least 48 KB only. Caution Be sure to clear bits 1 to 7 of IF1H to 0 for the products whose flash memory is less than 32 KB. Be sure to clear bits 4 to 7 of IF1H to 0 for the products whose flash memory is at least 48 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 641 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-6. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KF2) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF <0> Address: FFE3H After reset: 00H R/W Symbol 7 6 5 <4> <3> <2> <1> IF1H 0 0 0 ACSIIF TMIF011 TMIF001 CSIIF11 IICIF0 DMUIF XXIFX Caution Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Be sure to clear bits 5 to 7 of IF1H to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 642 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 20-7. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KB2) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK10 STMK0 Address: FFE6H After reset: FFH R/W Symbol 7 6 5 4 <3> 2 <1> <0> MK1L 1 1 1 1 TMMK51 1 SRMK0 ADMK Address: FFE7H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 <0> MK1H 1 1 1 1 1 1 1 IICMK0 XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Caution Be sure to set bits 2, 4 to 7 of MK1L and bits 1 to 7 of MK1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 643 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-8. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KC2) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK10 STMK0 Address: FFE6H Symbol After reset: FFH 7 MK1L 1 Address: FFE7H R/W <6> PMK6 Note 1 After reset: FFH <5> <4> <3> <2> <1> <0> WTMK KRMK TMMK51 WTIMK SRMK0 ADMK <0> R/W Symbol 7 6 5 4 3 2 1 MK1H 1 1 1 1 1 1 1 IICMK0 DMUMK XXMKX Note 2 Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Notes 1. 48-pin products only. 2. Products whose flash memory is at least 48 KB only. Cautions 1. Be sure to set bits 6 and 7 of MK1L to 1 in the 38-pin and 44-pin products. Be sure to set bit 7 of MK1L to 1 in the 48-pin products. 2. Be sure to set bits 1 to 7 of MK1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 644 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-9. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KD2) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK10 STMK0 Address: FFE6H After reset: FFH R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> MK1L 1 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK <0> Address: FFE7H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 MK1H 1 1 1 1 1 1 1 IICMK0 DMUMK XXMKX Note Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note Products whose flash memory is at least 48 KB only. Caution Be sure to set bit 7 of MK1L and bits 1 to 7 of MK1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 645 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-10. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KE2) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK10 STMK0 Address: FFE6H Symbol MK1L MK1H R/W <6> <5> <4> <3> <2> <1> <0> PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK 4 <3> <2> <1> <0> Address: FFE7H Symbol After reset: FFH <7> After reset: FFH 7 1 6 1 R/W 5 1 1 TMMK011 Note TMMK001 Note CSIMK11 Note IICMK0 DMUMK XXMKX Note Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note Products whose flash memory is at least 48 KB only. Caution Be sure to set bits 1 to 7 of MK1H to 1 for the products whose flash memory is less than 32 KB. Be sure to set bits 4 to 7 of MK1H to 1 for the products whose flash memory is at least 48 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 646 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-11. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KF2) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK10 STMK0 Address: FFE6H Symbol MK1L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK <0> Address: FFE7H After reset: FFH R/W Symbol 7 6 5 <4> <3> <2> <1> MK1H 1 1 1 ACSIMK TMMK011 TMMK001 CSIMK11 IICMK0 DMUMK XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Caution Be sure to set bits 5 to 7 of MK1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 647 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 20-12. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KB2) Address: FFE8H Symbol PR0L R/W <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H Symbol PR0H After reset: FFH <7> After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH After reset: FFH R/W Symbol 7 6 5 4 <3> 2 <1> <0> PR1L 1 1 1 1 TMPR51 1 SRPR0 ADPR Address: FFEBH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 <0> PR1H 1 1 1 1 1 1 1 IICPR0 XXPRX Priority level selection 0 High priority level 1 Low priority level Caution Be sure to set bits 2, 4 to 7 of PR1L and bits 1 to 7 of PR1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 648 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-13. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KC2) Address: FFE8H Symbol PR0L R/W <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H Symbol PR0H After reset: FFH After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH Symbol After reset: FFH 7 PR1L 1 Address: FFEBH R/W <6> PPR6 Note 1 After reset: FFH <5> <4> <3> <2> <1> <0> WTPR KRPR TMPR51 WTIPR SRPR0 ADPR <0> R/W Symbol 7 6 5 4 3 2 1 PR1H 1 1 1 1 1 1 1 IICPR0 Note 2 DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Notes 1. 48-pin products only. 2. Products whose flash memory is at least 48 KB only. Cautions 1. Be sure to set bits 6 and 7 of PR1L to 1 in the 38-pin and 44-pin products. Be sure to set bit 7 of PR1L to 1 in the 48-pin products. 2. Be sure to set bits 1 to 7 of PR1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 649 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-14. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KD2) Address: FFE8H Symbol PR0L R/W <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H Symbol PR0H After reset: FFH After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH After reset: FFH R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> PR1L 1 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR <0> Address: FFEBH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 PR1H 1 1 1 1 1 1 1 IICPR0 Note DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Note Products whose flash memory is at least 48 KB only. Caution Be sure to set bit 7 of PR1L and bits 1 to 7 of PR1H to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 650 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-15. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KE2) Address: FFE8H After reset: FFH Symbol PR0L <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H After reset: FFH Symbol PR0H R/W R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH Symbol PR1L PR1H R/W <6> <5> <4> <3> <2> <1> <0> PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR 4 <3> <2> <1> <0> Address: FFEBH Symbol After reset: FFH <7> After reset: FFH 7 1 R/W 6 1 5 1 1 TMPR011 Note TMPR001 Note CSIPR11 Note IICPR0 Note DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Note Products whose flash memory is at least 48 KB only. Caution Be sure to set bits 1 to 7 of PR1H to 1 for the products whose flash memory is less than 32 KB. Be sure to set bits 4 to 7 of PR1H to 1 for the products whose flash memory is at least 48 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 651 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-16. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KF2) Address: FFE8H After reset: FFH Symbol PR0L <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H After reset: FFH Symbol PR0H R/W R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH Symbol PR1L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR <0> Address: FFEBH After reset: FFH R/W Symbol 7 6 5 <4> <3> <2> <1> PR1H 1 1 1 ACSIPR TMPR011 TMPR001 CSIPR11 IICPR0 DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Caution Be sure to set bits 5 to 7 of PR1H to 1. (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTPn. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Remark n = 0 to 5: 78K0/KB2, 38-pin and 44-pin products of 78K0/KC2 n = 0 to 6: 78K0/KD2, 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KE2, 78K0/KF2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 652 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-17. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) (1/2) (1) 78K0/KB2 Address: FF48H After reset: 00H Symbol 7 6 R/W 5 4 3 2 1 0 EGP 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 R/W (2) 38-pin and 44-pin products of 78K0/KC2 Address: FF48H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGP 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 R/W (3) 48-pin products of 78K0/KC2, 78K0/KD2 Address: FF48H After reset: 00H Symbol 7 6 R/W 5 4 3 2 1 0 EGP 0 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN 0 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges R/W INTPn pin valid edge selection Caution Be sure to clear bits 6 and 7 of EGP and EGN to 0 in 78K0/KB2, and 38-pin and 44-pin products of 78K0/KC2. Be sure to clear bit 7 of EGP and EGN to 0 in 78K0/KD2, and 48-pin products of 78K0/KC2. Remark n = 0 to 5: 78K0/KB2, 38-pin and 44-pin products of 78K0/KC2 n = 0 to 6: 78K0/KD2, 48-pin products of 78K0/KC2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 653 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-17. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) (2/2) (4) 78K0/KE2, 78K0/KF2 Address: FF48H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 EGP R/W Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges EGN Remark R/W INTPn pin valid edge selection n = 0 to 7: 78K0/KE2, 78K0/KF2 Table 20-3 shows the ports corresponding to EGPn and EGNn. Table 20-3. Ports Corresponding to EGPn and EGNn Detection Enable Register Note 1 Note 2 Edge Detection Interrupt Request Port Signal EGP0 EGN0 P120 INTP0 EGP1 EGN1 P30 INTP1 EGP2 EGN2 P31 INTP2 EGP3 EGN3 P32 INTP3 EGP4 EGN4 P33 INTP4 EGP5 EGN5 P16 INTP5 EGP6 EGN6 P140 INTP6 EGP7 EGN7 P141 INTP7 Note 3 Notes 1. 78K0/KB2, and 38-pin and 44-pin products of 78K0/KC2 2. 78K0/KD2, and 48-pin products of 78K0/KC2 3. 78K0/KE2 and 78K0/KF2 Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark n = 0 to 5: 78K0/KB2, 38-pin and 44-pin products of 78K0/KC2 n = 0 to 6: 78K0/KD2, 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KE2, 78K0/KF2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 654 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 20-18. Format of Program Status Word PSW <7> <6> <5> <4> <3> 2 <1> 0 After reset IE Z RBS1 AC RBS0 0 ISP CY 02H Used when normal instruction is executed ISP R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Priority of interrupt currently being serviced 0 High-priority interrupt servicing (low-priority interrupt disabled) 1 Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) IE Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled 655 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS 20.4 Interrupt Servicing Operations 20.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 20-4 below. For the interrupt request acknowledgment timing, see Figures 20-20 and 20-21. Table 20-4. Time from Generation of Maskable Interrupt Until Servicing Minimum Time Note Maximum Time When xxPR = 0 7 clocks 32 clocks When xxPR = 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 20-19 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 656 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-19. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending No No IE = 1? Yes Interrupt request held pending Any high-priority interrupt request among those simultaneously generated with xxPR = 0? No Vectored interrupt servicing Interrupt request held pending Any high-priority interrupt request among those simultaneously generated? No IE = 1? Yes ISP = 1? Yes Yes Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 657 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-20. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 20-21. Interrupt Request Acknowledgment Timing (Maximum Time) CPU processing Instruction 25 clocks 6 clocks Divide instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 20.4.2 Software interrupt request acknowledgment A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 658 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS 20.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-22 shows multiple interrupt servicing examples. Table 20-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request PR = 0 Software interrupt Remarks 1. Interrupt PR = 1 Request Interrupt Being Serviced Maskable interrupt Software Maskable Interrupt Request IE = 1 IE = 0 IE = 1 IE = 0 ISP = 0 { x x x { ISP = 1 { x { x { { x { x { : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled. 4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H. PR = 0: Higher priority level PR = 1: Lower priority level R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 659 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-22. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing EI INTxx servicing INTyy servicing IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 660 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-22. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 EI INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 661 78K0/Kx2 CHAPTER 20 INTERRUPT FUNCTIONS 20.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW. bit, CY * MOV1 CY, PSW. bit * AND1 CY, PSW. bit * OR1 CY, PSW. bit * XOR1 CY, PSW. bit * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW. bit, $addr16 * BF PSW. bit, $addr16 * BTCLR PSW. bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and PR1H registers. Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 20-23 shows the timing at which interrupt requests are held pending. Figure 20-23. Interrupt Request Hold CPU processing Instruction N Instruction M PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 662 78K0/Kx2 CHAPTER 21 KEY INTERRUPT FUNCTION CHAPTER 21 KEY INTERRUPT FUNCTION 78K0/KB2 Key interrupt 78K0/KC2 - 38 pins: 78K0/KD2 78K0/KE2 2 ch 78K0/KF2 8 ch 44/48 pins: 4 ch 21.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KRn). Table 21-1. Assignment of Key Interrupt Detection Pins Flag KRMn Remark n = 0, 1: Description Controls KRn signal in 1-bit units. 38-pin products of 78K0/KC2 n = 0 to 3: 44-pin and 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KD2, 78K0/KE2, 78K0/KF2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 663 78K0/Kx2 CHAPTER 21 KEY INTERRUPT FUNCTION 21.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 21-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) Figure 21-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) Remark KR0, KR1, KRM0, KRM1: 38-pin products of 78K0/KC2 KR0 to KR3, KRM0 to KRM3: 44-pin and 48-pin products of 78K0/KC2 KR0 to KR7, KRM0 to KRM7: 78K0/KD2, 78K0/KE2, 78K0/KF2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 664 78K0/Kx2 CHAPTER 21 KEY INTERRUPT FUNCTION 21.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRMn bit using the KRn signal. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears KRM to 00H. Figure 21-2. Format of Key Return Mode Register (KRM) (1) 38-pin products of 78K0/KC2 Address: FF6EH After reset: 00H R/W Symbol 7 6 5 4 3 2 KRM 0 0 0 0 0 0 0 KRM1 KRM0 KRM1 KRM0 KRM1 KRM0 (2) 44-pin and 48-pin products of 78K0/KC2 Address: FF6EH After reset: 00H R/W Symbol 7 6 5 4 3 2 KRM 0 0 0 0 KRM3 KRM2 0 (3) 78K0/KD2, 78K0/KE2, 78K0/KF2 Address: FF6EH R/W 7 6 5 4 3 2 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 Symbol KRM After reset: 00H KRMn 0 Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal Cautions 1. If any of the KRMn bits used is set to 1, set bit n (PU7n) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports. 4. For the 38-pin products of 78K0/KC2, be sure to set bits 2 to 7 of KRM to "0". For the 44-pin and 48-pin products of 78K0/KC2, be sure to set bits 4 to 7 of KRM to "0". Remark n = 0, 1: 38-pin products of 78K0/KC2 n = 0 to 3: 44-pin and 48-pin products of 78K0/KC2 n = 0 to 7: 78K0/KD2, 78K0/KE2, 78K0/KF2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 665 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION CHAPTER 22 STANDBY FUNCTION 22.1 Standby Function and Configuration 22.1.1 Standby function The standby function is mounted onto all 78K0/Kx2 microcontroller products. The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. Note The 78K0/KB2 is not provided with a subsystem clock oscillator. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with main system clock before executing STOP instruction. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 666 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION 22.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 667 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Figure 22-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 204.8 s min. 102.4 s min. 13 819.2 s min. 409.6 s min. 14 1.64 ms min. 819.2 s min. 15 3.27 ms min. 1.64 ms min. 16 6.55 ms min. 3.27 ms min. 1 0 0 0 0 2 /fX min. 1 1 0 0 0 2 /fX min. 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 fX = 20 MHz 11 2 /fX min. 2 /fX min. 2 /fX min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 668 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Figure 22-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 0 1 1 0 1 1 1 819.2 s 409.6 s 14 1.64 ms 819.2 s 15 3.27 ms 1.64 ms 16 6.55 ms 3.27 ms 2 /fX 0 0 102.4 s 2 /fX 1 0 204.8 s 13 2 /fX 0 2 /fX 1 2 /fX Other than above fX = 20 MHz 11 Setting prohibited Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency 22.2 Standby Function Operation 22.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clockNote. The operating statuses in the HALT mode are shown below. Note The 78K0/KB2 is not provided with a subsystem clock. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 669 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Table 22-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) Item System clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Clock supply to the CPU is stopped Main system clock Subsystem clock fRH Operation continues (cannot be stopped) Status before HALT mode was set is retained fX Status before HALT mode was set is retained Operation continues (cannot be stopped) fEXCLK Operates or stops by external clock input fXT Status before HALT mode was set is retained fEXCLKS fRL Status before HALT mode was set is retained Operation continues (cannot be stopped) Operates or stops by external clock input Status before HALT mode was set is retained Operation stopped CPU Flash memory Status before HALT mode was set is retained RAM Port (latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer H0 Operable 01 51 H1 Watch timer Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 CSIA0 IIC0 Multiplier/divider Power-on-clear function Low-voltage detection function External interrupt Remarks 1. 2. fRH: Internal high-speed oscillation clock, fX: X1 clock fEXCLK: External main system clock, fXT: XT1 clock fEXCLKS: External subsystem clock, fRL: Internal low-speed oscillation clock The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 670 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Table 22-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (fXT) When CPU Is Operating on External Subsystem Clock (fEXCLKS) Item System clock Clock supply to the CPU is stopped Main system clock Status before HALT mode was set is retained fRH fX Subsystem clock fEXCLK Operates or stops by external clock input fXT Operation continues (cannot be stopped) Status before HALT mode was set is retained Operates or stops by external clock input Operation continues (cannot be stopped) fEXCLKS fRL Status before HALT mode was set is retained Operation stopped CPU Flash memory Status before HALT mode was set is retained RAM Port (latch) 16-bit timer/event counter 00 Note 01 Note 8-bit timer/event counter 50 Note 51 Note 8-bit timer H0 Operable H1 Watch timer Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable Buzzer output Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped. A/D converter Serial interface UART0 Operable UART6 CSI10 Note CSI11 Note CSIA0 IIC0 Note Note Multiplier/divider Power-on-clear function Low-voltage detection function External interrupt Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock and high-speed system clock have been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. Remarks 1. 2. fRH: Internal high-speed oscillation clock, fX: X1 clock fEXCLK: External main system clock, fXT: XT1 clock fEXCLKS: External subsystem clock, fRL: Internal low-speed oscillation clock The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 671 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 22-3. HALT Mode Release by Interrupt Request Generation HALT instruction Interrupt request Standby release signal Status of CPU Normal operation WaitNote 1 HALT mode High-speed system clock, internal high-speed oscillation clock, or subsystem clockNote 2 Normal operation Oscillation Notes 1. The wait time is as follows: * When vectored interrupt servicing is carried out: 11 or 12 clocks * When vectored interrupt servicing is not carried out: 4 or 5 clocks 2. The 78K0/KB2 is not provided with a subsystem clock. Remark The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 672 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 22-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock HALT instruction Reset signal Status of CPU Normal operation (high-speed system clock) High-speed system clock (X1 oscillation) Reset Reset processing period (11 to 45 s) HALT mode Normal operation (internal high-speed oscillation clock) Oscillation Oscillation stopped stopped Oscillates Oscillates Oscillation stabilization time (211/fX to 216/fX) Starting X1 oscillation is specified by software. (2) When internal high-speed oscillation clock is used as CPU clock HALT instruction Reset signal Normal operation (internal high-speed oscillation clock) Status of CPU Internal high-speed oscillation clock Reset Reset processing period (11 to 45 s) HALT mode Oscillates Oscillation stopped Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) (3) When subsystem clock is used as CPU clockNote 1 HALT instruction Reset signal Status of CPU Normal operation (subsystem clock) Subsystem clock (XT1 oscillation) HALT mode Oscillates Reset period Reset Normal operation mode processing (internal high-speed (11 to 45 s) oscillation clock) Oscillation Oscillation stopped stopped Oscillates Starting XT1 oscillation is specified by software. <R> Oscillation stabilization time (measure by the user)Note 2 Notes 1. The 78K0/KB2 is not provided with a subsystem clock. 2. Oscillation stabilization time is not required when using the external subsystem clock (fEXCLKS) as the subsystem clock. Remark fX: X1 clock oscillation frequency R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 673 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Table 22-2. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x Interrupt servicing execution 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing execution Reset 1 x x x HALT mode held - - x x Reset processing x: don't care 22.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 674 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Table 22-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) Item System clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Clock supply to the CPU is stopped Main system clock Stopped fRH fX fEXCLK Subsystem clock Input invalid fXT Status before STOP mode was set is retained fEXCLKS Operates or stops by external clock input fRL Status before STOP mode was set is retained Operation stopped CPU Flash memory Status before STOP mode was set is retained RAM Port (latch) 16-bit timer/event counter 00 Note 1 01 Note 1 Operation stopped 8-bit timer/event counter 50 Note 1 Operable only when TI50 is selected as the count clock 51 Note 1 Operable only when TI51 is selected as the count clock 8-bit timer H0 Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation H1 Operable only when fRL, fRL/2 , fRL/2 is selected as the count clock 7 9 Watch timer Operable only when subsystem clock is selected as the count clock Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable only when subsystem clock is selected as the count clock Buzzer output Operation stopped A/D converter Serial interface UART0 UART6 CSI10 Note 1 CSI11 Note 1 CSIA0 IIC0 Note 1 Note 1 Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter 50 operation Operable only when external clock is selected as the serial clock Operation stopped Operable only when the external clock from EXSCL0/P62 pin is selected as the serial clock Multiplier/divider Operation stopped Power-on-clear function Operable Note 2 Low-voltage detection function External interrupt Notes 1. Do not start operation of these functions on the external clock input from peripheral hardware pins in the stop mode. 2. The operation of 78K0/KB2 products is stopped (The external clock from the EXSCL0/P62 pin cannot be selected, because the EXSCL0/P62 pin is not mounted.). Remarks 1. 2. Internal high-speed oscillation clock, fX: X1 clock fRH: fEXCLK: External main system clock, fXT: XT1 clock fRL: Internal low-speed oscillation clock fEXCLKS: External subsystem clock, The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 675 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. Even if "internal low-speed oscillator can be stopped by software" is selected by the option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode, stop it by software and then execute the STOP instruction. 3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), switch the CPU clock to the internal high-speed oscillation clock before the execution of the STOP instruction using the following procedure. <1> Set RSTOP to 0 (starting oscillation of the internal high-speed oscillator) <2> Set MCM0 to 0 (switching the CPU from X1 oscillation to internal high-speed oscillation) <3> Check that MCS is 0 (checking the CPU clock) <4> Check that RSTS is 1 (checking internal high-speed oscillation operation) <5> Execute the STOP instruction Before changing the CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). 4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal high-speed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. 5. Execute the STOP instruction after having confirmed that the internal high-speed oscillator is operating stably (RSTS = 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 676 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION (2) STOP mode release Figure 22-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock High-speed system clock (X1 oscillation) is selected as CPU clock when STOP instruction is executed Wait for oscillation accuracy stabilization (86 to 361 s) HALT status (oscillation stabilization time set by OSTS) High-speed system clock (external clock input) is selected as CPU clock when STOP instruction is executed Internal high-speed oscillation clock is selected as CPU clock when STOP instruction is executed High-speed system clock Clock switched by software High-speed system clock WaitNote2 Supply of the CPU clock is stopped (160 external clocks)Note1 Internal high-speed oscillation clock WaitNote2 High-speed system clock Clock switched by software Supply of the CPU clock is stopped (4.06 to 16.12 s)Note1 Notes 1. When AMPH = 1 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 17 or 18 clocks * When vectored interrupt servicing is not carried out: 11 or 12 clocks The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 677 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Figure 22-6. STOP Mode Release by Interrupt Request Generation (1/2) (1) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt request STOP instruction Standby release signal Status of CPU Wait (set by OSTS) Normal operation (high-speed system clock) STOP mode Oscillates Oscillation stopped High-speed system clock (X1 oscillation) Normal operation (high-speed system clock) Oscillation stabilization wait (HALT mode status) Oscillates Oscillation stabilization time (set by OSTS) (2) When high-speed system clock (external clock input) is used as CPU clock * When AMPH = 1 STOP instruction Interrupt request Standby release signal Status of CPU Normal operation (high-speed system clock) STOP mode Supply of the CPU clock is stopped Oscillates Oscillation stopped (160 external clocks) High-speed system clock (external clock input) WaitNote Normal operation (high-speed system clock) Oscillates * When AMPH = 0 STOP instruction Interrupt request Standby release signal Status of CPU Normal operation (high-speed system clock) STOP mode Oscillates Oscillation stopped High-speed system clock (external clock input) Note WaitNote Normal operation (high-speed system clock) Oscillates The wait time is as follows: * When vectored interrupt servicing is carried out: 17 or 18 clocks * When vectored interrupt servicing is not carried out: 11 or 12 clocks Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 678 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION Figure 22-6. STOP Mode Release by Interrupt Request Generation (2/2) (3) When internal high-speed oscillation clock is used as CPU clock * When AMPH = 1 STOP instruction Interrupt request Standby release signal Status of CPU Normal operation (internal high-speed oscillation clock) STOP mode Oscillates Oscillation stopped Supply of the CPU clock is stopped Note Wait Normal operation (internal high-speed oscillation clock) (4.06 to 16.12 s) Internal high-speed oscillation clock Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) * When AMPH = 0 STOP instruction Interrupt request Standby release signal Status of CPU Normal operation (internal high-speed oscillation clock) Internal high-speed oscillation clock Oscillates STOP mode Oscillation stopped Note Wait Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) Note The wait time is as follows: * When vectored interrupt servicing is carried out: 17 or 18 clocks * When vectored interrupt servicing is not carried out: 11 or 12 clocks Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 679 78K0/Kx2 CHAPTER 22 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 22-7. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Reset signal Status of CPU High-speed system clock (X1 oscillation) <R> Normal operation (high-speed system clock) STOP mode Oscillation stopped Oscillates Reset period Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) Oscillation Oscillation stopped stopped Oscillates Oscillation stabilization time (211/fX to 216/fX) Note Starting X1 oscillation is specified by software. Note Oscillation stabilization time is not required when using the external main system clock (fEXCLK) as the highspeed system clock. (2) When internal high-speed oscillation clock is used as CPU clock STOP instruction Reset signal Status of CPU Internal high-speed oscillation clock Normal operation (internal high-speed oscillation clock) Reset Reset processing period (11 to 45 s) STOP mode Oscillation Oscillation stopped stopped Oscillates Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) Remark fX: X1 clock oscillation frequency Table 22-4. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x Interrupt servicing execution 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing execution Reset 1 x x x STOP mode held - - x x Reset processing x: don't care R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 680 78K0/Kx2 CHAPTER 23 RESET FUNCTION CHAPTER 23 RESET FUNCTION The reset function is mounted onto all 78K0/Kx2 microcontroller products. The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Tables 23-1 and 23-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a reset release, except for P130, which is low-level output. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal highspeed oscillation clock (see Figures 23-2 to 23-4) after reset processing. Reset by POC and LVI circuit power supply detection is automatically released when VDD VPOC or VDD VLVI after the reset, and program execution starts using the internal high-speed oscillation clock (see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW- VOLTAGE DETECTOR) after reset processing. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset signal generation, the X1 clock, XT1 clockNote 1, internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating. External main system clock input and external subsystem clockNote 1 input become invalid. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130Note 2, which is set to lowlevel output. Notes 1. 2. The 78K0/KB2 is not provided with XT1 clock and external subsystem clock. P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 681 78K0/Kx2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Figure 23-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Set Set Watchdog timer reset signal Clear Clear RESF register read signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register Reset signal 682 CHAPTER 23 RESET FUNCTION Low-voltage detector reset signal 78K0/Kx2 CHAPTER 23 RESET FUNCTION Figure 23-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Reset period (oscillation stop) Normal operation Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) RESET Internal reset signal Delay Port pin (except P130) Delay (5 s (TYP.)) Hi-Z Port pin (P130Note 1) Notes 1. 2. Remark Note 2 P130 pin is not mounted onto 78K0/KB2, and 38-pin and 44-pin products of the 78K0/KC2. Set P130 to high-level output by software. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 683 78K0/Kx2 CHAPTER 23 RESET FUNCTION Figure 23-3. Timing of Reset Due to Watchdog Timer Overflow Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Normal operation Reset period (oscillation stop) Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) Watchdog timer overflow Internal reset signal Port pin (except P130) Hi-Z Port pin (P130Note 1) Notes 1. 2. Note 2 P130 pin is not mounted onto 78K0/KB2, and 38-pin and 44-pin products of the 78K0/KC2. Set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 684 78K0/Kx2 CHAPTER 23 RESET FUNCTION Figure 23-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization (86 to 361 s) STOP instruction execution Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Normal operation Stop status (oscillation stop) Reset period (oscillation stop) Reset processing Normal operation (internal high-speed oscillation clock) (11 to 45 s) RESET Internal reset signal Delay Port pin (except P130) Delay (5 s (TYP.)) Hi-Z Port pin (P130Note 1) Notes 1. 2. Note 2 P130 pin is not mounted onto 78K0/KB2, and 38-pin and 44-pin products of the 78K0/KC2. Set P130 to high-level output by software. Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. 2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWERON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 685 78K0/Kx2 CHAPTER 23 RESET FUNCTION Table 23-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Subsystem clock fRH Operation stopped fX Operation stopped (pin is I/O port mode) fEXCLK Clock input invalid (pin is I/O port mode) fXT Operation stopped (pin is I/O port mode) fEXCLKS Clock input invalid (pin is I/O port mode) fRL Operation stopped CPU Flash memory RAM Port (latch) 16-bit timer/event 00 counter 01 8-bit timer/event 50 counter 51 8-bit timer H0 H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 CSIA0 IIC0 Multiplier/divider Power-on-clear function Operable Low-voltage detection function Operation stopped External interrupt Remarks 1. 2. fRH: Internal high-speed oscillation clock, fX: X1 clock fEXCLK: External main system clock, fXT: XT1 clock fEXCLKS: External subsystem clock, fRL: Internal low-speed oscillation clock The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 686 78K0/Kx2 CHAPTER 23 RESET FUNCTION Table 23-2. Hardware Statuses After Reset Acknowledgment (1/4) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined Note 2 General-purpose registers Undefined Note 2 Port registers (P0 to P7, P12 to P14) (output latches) 00H Port mode registers (PM0 to PM7, PM12, PM14) FFH Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) 00H Internal expansion RAM size switching register (IXS) 0CH Internal memory size switching register (IMS) CFH Notes 1. 2. 3. 4. Remark Notes 3, 4 Notes 3, 4 During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. When a reset is executed in the standby mode, the pre-reset status is held even after reset. The initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all products of the 78K0/Kx2 microcontrollers, regardless of the internal memory capacity. Therefore, set the value corresponding to each product as indicated in Tables 3-1 and 3-2. The ROM and RAM capacities of the products with the on-chip debug function can be debugged by setting IMS and IXS, according to the debug target products. Set IMS and IXS according to the debug target products. The special function register (SFR) mounted depend on the product. See 3.2.3 Special function registers (SFRs). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 687 78K0/Kx2 CHAPTER 23 RESET FUNCTION Table 23-2. Hardware Statuses After Reset Acknowledgment (2/4) Hardware Status After Reset Acknowledgment Memory bank select register (BANK) 00H Clock operation mode select register (OSCCTL) 00H Processor clock control register (PCC) 01H Internal oscillation mode register (RCM) 80H Main OSC control register (MOC) 80H Main clock mode register (MCM) 00H Oscillation stabilization time counter status register (OSTC) 00H Oscillation stabilization time select register (OSTS) 05H 16-bit timer/event counters 00, 01 Timer counters 00, 01 (TM00, TM01) 0000H Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) 0000H 8-bit timer/event counters 50, 51 8-bit timers H0, H1 Mode control registers 00, 01 (TMC00, TMC01) 00H Prescaler mode registers 00, 01 (PRM00, PRM01) 00H Capture/compare control registers 00, 01 (CRC00, CRC01) 00H Timer output control registers 00, 01 (TOC00, TOC01) 00H Timer counters 50, 51 (TM50, TM51) 00H Compare registers 50, 51 (CR50, CR51) 00H Timer clock selection registers 50, 51 (TCL50, TCL51) 00H Mode control registers 50, 51 (TMC50, TMC51) 00H Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H Mode registers (TMHMD0, TMHMD1) 00H Note 2 Carrier control register 1 (TMCYC1) 00H Watch timer Operation mode register (WTM) 00H Clock output/buzzer output controller Clock output selection register (CKS) 00H Watchdog timer Enable register (WDTE) 1AH/9AH A/D converter 10-bit A/D conversion result register (ADCR) 0000H 8-bit A/D conversion result register (ADCRH) 00H Mode register (ADM) 00H Analog input channel specification register (ADS) 00H A/D port configuration register (ADPC) 00H Receive buffer register 0 (RXB0) FFH Serial interface UART0 Notes 1. Note 1 Transmit shift register 0 (TXS0) FFH Asynchronous serial interface operation mode register 0 (ASIM0) 01H Asynchronous serial interface reception error status register 0 (ASIS0) 00H Baud rate generator control register 0 (BRGC0) 1FH Note 3 During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. 8-bit timer H1 only. 3. The reset value of WDTE is determined by the option byte setting. Remark The special function register (SFR) mounted depend on the product. See 3.2.3 Special function registers (SFRs). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 688 78K0/Kx2 CHAPTER 23 RESET FUNCTION Table 23-2. Hardware Statuses After Reset Acknowledgment (3/4) Hardware Status After Reset Acknowledgment Serial interface UART6 Receive buffer register 6 (RXB6) FFH Transmit buffer register 6 (TXB6) FFH Asynchronous serial interface operation mode register 6 (ASIM6) 01H Asynchronous serial interface reception error status register 6 (ASIS6) 00H Asynchronous serial interface transmission status register 6 (ASIF6) 00H Clock selection register 6 (CKSR6) 00H Baud rate generator control register 6 (BRGC6) FFH Asynchronous serial interface control register 6 (ASICL6) 16H Input switch control register (ISC) 00H Serial interfaces CSI10, Transmit buffer registers 10, 11 (SOTB10, SOTB11) 00H CSI11 Serial I/O shift registers 10, 11 (SIO10, SIO11) 00H Serial operation mode registers 10, 11 (CSIM10, CSIM11) 00H Serial interface CSIA0 Serial interface IIC0 Multiplier/divider Key interrupt Note Serial clock selection registers 10, 11 (CSIC10, CSIC11) 00H Serial operation mode specification register 0 (CSIMA0) 00H Serial status register 0 (CSIS0) 00H Serial trigger register 0 (CSIT0) 00H Divisor value selection register 0 (BRGCA0) 03H Automatic data transfer address point specification register 0 (ADTP0) 00H Automatic data transfer interval specification register 0 (ADTI0) 00H Serial I/O shift register 0 (SIOA0) 00H Automatic data transfer address count register 0 (ADTC0) 00H Shift register 0 (IIC0) 00H Control register 0 (IICC0) 00H Slave address register 0 (SVA0) 00H Clock selection register 0 (IICCL0) 00H Function expansion register 0 (IICX0) 00H Status register 0 (IICS0) 00H Flag register 0 (IICF0) 00H Remainder data register 0 (SDR0) 0000H Multiplication/division data register A0 (MDA0H, MDA0L) 0000H Multiplication/division data register B0 (MDB0) 0000H Multiplier/divider control register 0 (DMUC0) 00H Key return mode register (KRM) 00H Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. Remark The special function register (SFR) mounted depend on the product. See 3.2.3 Special function registers (SFRs). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 689 78K0/Kx2 CHAPTER 23 RESET FUNCTION Table 23-2. Hardware Statuses After Reset Acknowledgment (4/4) Status After Reset Hardware Acknowledgment Note 2 Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level selection register (LVIS) 00H Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) 00H Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H) FFH Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, FFH Interrupt Note 1 Note 2 Note 2 PR1H) Notes 1. External interrupt rising edge enable register (EGP) 00H External interrupt falling edge enable register (EGN) 00H During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. These values vary depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register RESF WDTRF flag Cleared (0) Cleared (0) LVIRF flag LVIM Cleared (00H) Cleared (00H) Set (1) Held Held Set (1) Cleared (00H) Held LVIS Remark The special function register (SFR) mounted depend on the product. See 3.2.3 Special function registers (SFRs). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 690 78K0/Kx2 CHAPTER 23 RESET FUNCTION 23.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/Kx2 microcontrollers. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 23-5. Format of Reset Control Flag Register (RESF) Address: FFACH After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 23-3. Table 23-3. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Flag WDTRF LVIRF R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Cleared (0) Cleared (0) Set (1) Held Held Set (1) 691 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) is mounted onto all 78K0/Kx2 microcontroller products. The power-on-clear circuit has the following functions. * Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage (VDD) exceeds 1.59 V 0.15 V. In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply voltage (VDD) exceeds 2.7 V 0.2 V. * Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V), generates internal reset signal when VDD < VPOC. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark 78K0/Kx2 microcontrollers incorporate multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 23 RESET FUNCTION. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 692 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 24-1. Figure 24-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Reference voltage source 24.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPOC = 1.59 V 0.15 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VPOC. (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VDDPOC = 2.7 V 0.2 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VDDPOC. The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 693 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Supply voltage (VDD) VLVI 1.8 VNotes 1, 2, 3 VPOC = 1.59 V (TYP.) 0.5 V/ms (MIN.) Note 2, 3 0V Wait for oscillation accuracy stabilization (86 to 361 s) Note 4 Note 4 Internal high-speed oscillation clock (fRH) Starting oscillation is specified by software. High-speed system clock (fXH) (when X1 oscillation is selected) Operation CPU stops Wait for voltage stabilization (1.93 to 5.39 ms) Starting oscillation is specified by software. Normal operation Reset period (internal high-speed (oscillation oscillation clock)Note 5 stop) Reset processing (11 to 45 s) Starting oscillation is specified by software. Normal operation Reset period Wait for voltage (internal high-speed (oscillation stabilization Note 5 oscillation clock) stop) (1.93 to 5.39 ms) Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock)Note 5 Operation stops Reset processing (11 to 45 s) Internal reset signal Notes 1. The guaranteed operation range for the standard and (A) grade products is 1.8 V VDD 5.5 V, and 2.7 V VDD 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input a low level to the RESET pin. 2. With the standard and (A) grade products, if the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1). 3. With the (A2) grade products, if the voltage rises to 2.7 V at a rate slower than 0.75 V/ms (MIN.) on power application, input a low level to the RESET pin after power application and before the voltage reaches 2.7 V. 4. The oscillation accuracy stabilization time of the internal high-speed oscillation clock is included in the internal voltage stabilization time. 5. The CPU clock can be switched from the internal high-speed oscillation clock to the high-speed system clock or to the subsystem clockNote 6. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clockNote 6, use the timer function for confirmation of the lapse of the stabilization time. 6. The 78K0/KB2 is not provided with subsystem clock and XT1 clock. Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOWVOLTAGE DETECTOR). Remark VLVI: LVI detection voltage VPOC: POC detection voltage R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 694 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Wait for oscillation accuracy stabilization (86 to 361 s) Wait for oscillation accuracy stabilization (86 to 361 s) Supply voltage (VDD) VLVI VDDPOC = 2.7 V (TYP.) 1.8 VNote 1 VPOC = 1.59 V (TYP.) 0V Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock (fRH) Starting oscillation is specified by software. High-speed system clock (fXH) (when X1 oscillation is selected) Normal operation Reset period (internal high-speed (oscillation stop) oscillation clock)Note 2 Operation CPU stops Reset processing (11 to 45 s) Starting oscillation is specified by software. Normal operation (internal high-speed oscillation clock)Note 2 Reset period (oscillation stop) Reset processing (11 to 45 s) Starting oscillation is specified by software. Normal operation (internal high-speed oscillation clock)Note 2 Operation stops Reset processing (11 to 45 s) Internal reset signal Notes 1. The guaranteed operation range for the standard and (A) grade products is 1.8 V VDD 5.5 V, and 2.7 V VDD 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input a low level to the RESET pin. 2. The CPU clock can be switched from the internal high-speed oscillation clock to the high-speed system clock or subsystem clockNote 3. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clockNote 3, use the timer function for confirmation of the lapse of the stabilization time. 3. The 78K0/KB2 is not provided with subsystem clock and XT1 clock. Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-VOLTAGE DETECTOR). 2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. Remark VLVI: LVI detection voltage VPOC: POC detection voltage R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 695 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 24-3. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset Initialization processing <1> ; Check the reset sourceNote 2 Initialize the port. Power-on-clear Setting 8-bit timer H1 (to measure 50 ms) ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Clearing WDT Note 1 No 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Notes 1. 2. ; Setting of division ratio of system clock, such as setting of timer or A/D converter If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 696 78K0/Kx2 CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-3. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 697 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR CHAPTER 25 LOW-VOLTAGE DETECTOR 25.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) is mounted onto all 78K0/Kx2 microcontroller products. The low-voltage detector has the following functions. * The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.): fixed), and generates an internal reset or internal interrupt signal. * The supply voltage (VDD) or input voltage from an external input pin (EXLVI) can be selected by software. * Reset or interrupt function can be selected by software. * Detection levels (16 levels Note ) of supply voltage can be changed by software. * Operable in STOP mode. Note Standard products and (A) grade products: 16 levels (A2) grade products: 10 levels The reset and interrupt signals are generated as follows depending on selection by software. Selection of Level Detection of Supply Voltage (VDD) Selection Level Detection of Input Voltage from (LVISEL = 0) External Input Pin (EXLVI) (LVISEL = 1) Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0). Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0). Generates an internal reset Generates an internal interrupt Generates an internal reset Generates an internal interrupt signal when VDD < VLVI and signal when VDD drops lower signal when EXLVI < VEXLVI signal when EXLVI drops releases the reset signal when than VLVI (VDD < VLVI) or when and releases the reset signal lower than VEXLVI (EXLVI < VDD VLVI. VDD becomes VLVI or higher when EXLVI VEXLVI. (VDD VLVI). VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI). Remark LVISEL: Bit 2 of low-voltage detection register (LVIM) LVIMD: Bit 1 of LVIM While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM). When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 23 RESET FUNCTION. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 698 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 25-1. Figure 25-1. Block Diagram of Low-Voltage Detector VDD N-ch Internal reset signal Selector EXLVI/P120/ INTP0 + Selector Low-voltage detection level selector VDD - INTLVI Reference voltage source 4 LVION LVISEL LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) LVIF Low-voltage detection register (LVIM) Internal bus 25.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) * Port mode register 12 (PM12) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 699 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-2. Format of Low-Voltage Detection Register (LVIM) After reset: 00HNote 1 Address: FFBEH R/WNote 2 Symbol <7> 6 5 4 3 <2> <1> <0> LVIM LVION 0 0 0 0 LVISEL LVIMD LVIF Notes 3, 4 LVION Enables low-voltage detection operation 0 Disables operation 1 Enables operation Note 3 LVISEL Voltage detection selection 0 Detects level of supply voltage (VDD) 1 Detects level of input voltage from external input pin (EXLVI) Note 3 LVIMD 0 Low-voltage detection operation mode (interrupt/reset) selection * LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes VLVI or higher (VDD VLVI). * LVISEL = 1: Generates an interrupt signal when the input voltage from an external input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI). 1 * LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) < detection voltage (VLVI) and releases the reset signal when VDD VLVI. * LVISEL = 1: Generates an internal reset signal when the input voltage from an external input pin (EXLVI) < detection voltage (VEXLVI) and releases the reset signal when EXLVI VEXLVI. LVIF 0 Low-voltage detection flag * LVISEL = 0: Supply voltage (VDD) detection voltage (VLVI), or when operation is disabled * LVISEL = 1: Input voltage from external input pin (EXLVI) detection voltage (VEXLVI), or when operation is disabled 1 * LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI) * LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI) Notes 1. 2. 3. This bit is cleared to 00H upon a reset other than an LVI reset. Bit 0 is read-only. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. 4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for an operation stabilization time (10 s (MIN.)) from when LVION is set to 1 until operation is stabilized. After operation has stabilized, the external input of 200 s (MIN.) (Minimum pulse width: 200 s (MIN.)) is required from when a state below LVI detection voltage has been entered, until LVIF is set (1). Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 700 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Cautions 3. When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and LVIIF becomes 1. 4. With the conventional-specification products (PD78F05xx and 78F05xxD), after an LVI reset has been generated, do not write values to LVIS and LVIM when LVION = 1. (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS) After reset: 00HNote 1 Address: FFBFH R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 0 0 0 0 VLVI0 (4.24 V 0.1 V) 0 0 0 1 VLVI1 (4.09 V 0.1 V) 0 0 1 0 VLVI2 (3.93 V 0.1 V) 0 0 1 1 VLVI3 (3.78 V 0.1 V) 0 1 0 0 VLVI4 (3.62 V 0.1 V) 0 1 0 1 VLVI5 (3.47 V 0.1 V) 0 1 1 0 VLVI6 (3.32 V 0.1 V) 0 1 1 1 VLVI7 (3.16 V 0.1 V) 1 0 0 0 VLVI8 (3.01 V 0.1 V) 1 0 0 1 VLVI9 (2.85 V 0.1 V) 1 0 1 0 VLVI10 (2.70 V 0.1 V) Note 2 1 0 1 1 VLVI11 (2.55 V 0.1 V) Note 2 1 1 0 0 VLVI12 (2.39 V 0.1 V) Note 2 1 1 0 1 VLVI13 (2.24 V 0.1 V) Note 2 1 1 1 0 VLVI14 (2.08 V 0.1 V) Note 2 1 1 1 1 VLVI15 (1.93 V 0.1 V) Note 2 Detection level Notes 1. The value of LVIS is not reset but retained as is, upon a reset by LVI. It is cleared to 00H upon other resets. 2. Do not set VLVI10 to VLVI15 for (A2) grade products. Cautions 1. Be sure to clear bits 4 to 7 to "0". 2. Do not change the value of LVIS during LVI operation. 3. When an input voltage from the external input pin (EXLVI) is detected, the detection voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary. 4. With the conventional-specification products (PD78F05xx and 78F05xxD), after an LVI reset has been generated, do not write values to LVIS and LVIM when LVION = 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 701 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH. Figure 25-4. Format of Port Mode Register 12 (PM12) Address: FF2CH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 PM12n P12n pin I/O mode selection (n = 0 to 4) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Remark The format of port mode register 12 of 78K0/KB2 products is different from the above format. See 5.3 Registers Controlling Port Function (1) Port mode registers (PMxx). 25.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1) * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD VLVI. * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)), generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI VEXLVI. (2) Used as interrupt (LVIMD = 0) * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI). When VDD drops lower than VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD VLVI), generates an interrupt signal (INTLVI). * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)). When EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI), generates an interrupt signal (INTLVI). While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM). Remark LVIMD: Bit 1 of low-voltage detection register (LVIM) LVISEL: Bit 2 of LVIM R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 702 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.4.1 When used as reset (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MIN.)). <6> Wait until it is checked that (supply voltage (VDD) detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected). Figure 25-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <7> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <4>. 2. If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 703 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) H <1> LVISEL flag (set by software) L LVION flag (set by software) <3> <2> Not cleared Not cleared <4> Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Clear Note 2 Not cleared Not cleared <7> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of "When starting operation" in 25.4.1 (1) When detecting level of supply voltage (VDD). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 704 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V (TYP.) VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) HNote 1 LVISEL flag (set by software) L <1> <3> LVION flag (set by software) <2> Not cleared Not cleared <4> Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Clear Note 2 Not cleared Not cleared <7> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of "When starting operation" in 25.4.1 (1) When detecting level of supply voltage (VDD). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 705 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MIN.)). <5> Wait until it is checked that (input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.))) by bit 0 (LVIF) of LVIM. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected). Figure 25-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)) when LVIMD is set to 1, an internal reset signal is not generated. 3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 706 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage (VEXLVI) Time LVIMK flag (set by software) HNote 1 LVISEL flag (set by software) <1> Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared <2> LVION flag (set by software) <3> <4> Wait time LVIF flag <5> LVIMD flag (set by software) Note 2 Not cleared <6> LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <6> in Figure 25-6 above correspond to <1> to <6> in the description of "When starting operation" in 25.4.1 (2) When detecting level of input voltage from external input pin (EXLVI). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 707 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.4.2 When used as interrupt (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value). <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to wait for an operation stabilization time (10 s (MIN.)). <7> Confirm that "supply voltage (VDD) detection voltage (VLVI)" when detecting the falling edge of VDD, or "supply voltage (VDD) < detection voltage (VLVI)" when detecting the rising edge of VDD, at bit 0 (LVIF) of LVIM. <8> Clear the interrupt request flag of LVI (LVIIF) to 0. <9> Release the interrupt mask flag of LVI (LVIMK). <10> Execute the EI instruction (when vector interrupts are used). Figure 25-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 708 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 LVISEL flag (set by software) <9> Cleared by software <3> L LVION flag (set by software) <2> <5> <6> Wait time LVIF flag <7> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <8> Cleared by software <4> Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). 3. If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and LVIIF becomes 1. Remark <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of "When starting operation" in 25.4.2 (1) When detecting level of supply voltage (VDD). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 709 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V(TYP.) VPOC = 1.59 V (TYP.) Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 LVISEL flag (set by software) <9> Cleared by software <3> L <2> LVION flag (set by software) <5> <6> Wait time LVIF flag <7> Note 2 INTLVI Note 2 LVIIF flag LVIMD flag (set by software) Note 2 <8> Cleared by software L <4> Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). 3. If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and LVIIF becomes 1. Remark <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of "When starting operation" in 25.4.2 (1) When detecting level of supply voltage (VDD). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 710 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MIN.)). <6> Confirm that "input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)" when detecting the falling edge of EXLVI, or "input voltage from external input pin (EXLVI) < detection voltage (VEXLVI = 1.21 V (TYP.)" when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM. <7> Clear the interrupt request flag of LVI (LVIIF) to 0. <8> Release the interrupt mask flag of LVI (LVIMK). <9> Execute the EI instruction (when vector interrupts are used). Figure 25-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 711 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) VEXLVI Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 <8> Cleared by software LVISEL flag (set by software) LVION flag (set by software) <2> <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <7> Cleared by software <3> Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and LVIIF becomes 1. Remark <1> to <8> in Figure 25-8 above correspond to <1> to <8> in the description of "When starting operation" in 25.4.2 (2) When detecting level of input voltage from external input pin (EXLVI). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 712 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. <Action> (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see Figure 25-9). (2) When used as interrupt (a) Confirm that "supply voltage (VDD) detection voltage (VLVI)" when detecting the falling edge of VDD, or "supply voltage (VDD) < detection voltage (VLVI)" when detecting the rising edge of VDD, in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0. (b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, confirm that "supply voltage (VDD) detection voltage (VLVI)" when detecting the falling edge of VDD, or "supply voltage (VDD) < detection voltage (VLVI)" when detecting the rising edge of VDD, using the LVIF flag, and clear the LVIIF flag to 0. Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to "1", the meanings of the above words change as follows. * Supply voltage (VDD) Input voltage from external input pin (EXLVI) * Detection voltage (VLVI) Detection voltage (VEXLVI = 1.21 V) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 713 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-9. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check the reset sourceNote Initialize the port. Initialization processing <1> LVI reset ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, Where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Setting 8-bit timer H1 (to measure 50 ms) Clearing WDT Detection voltage or higher (LVIF = 0?) Yes No Restarting timer H1 (TMHE1 = 0 TMHE1 = 1) No ; The timer counter is cleared and the timer is started. 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> ; Setting of division ratio of system clock, such as setting of timer or A/D converter Note A flowchart is shown on the next page. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 714 78K0/Kx2 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-9. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source LVION of LVIM register = 1? Yes: Reset generation by LVI No: Reset generation other than by LVI Set LVI (Set LVIM and LVIS registers) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 715 78K0/Kx2 CHAPTER 26 OPTION BYTE CHAPTER 26 OPTION BYTE 26.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/Kx2 microcontrollers is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes. When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H. Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance. Caution Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap function is used). (1) 0080H/1080H { Internal low-speed oscillator operation * Can be stopped by software * Cannot be stopped { Watchdog timer overflow time setting { Watchdog timer counter operation * Enabled counter operation * Disabled counter operation { Watchdog timer window open period setting Caution Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. (2) 0081H/1081H { Selecting POC mode * During 2.7 V/1.59 V POC mode operation (POCMODE = 1) The device is in the reset state upon power application and until the supply voltage reaches 2.7 V (TYP.). It is released from the reset state when the voltage exceeds 2.7 V (TYP.). After that, POC is not detected at 2.7 V but is detected at 1.59 V (TYP.). With standard and (A) grade products, if the supply voltage rises to 1.8 V after power application at a rate slower than 0.5 V/ms (MIN.), use of the 2.7 V/1.59 V POC mode is recommended. * During 1.59 V POC mode operation (POCMODE = 0) The device is in the reset state upon power application and until the supply voltage reaches 1.59 V (TYP.). It is released from the reset state when the voltage exceeds 1.59 V (TYP.). After that, POC is detected at 1.59 V (TYP.), in the same manner as on power application. Caution POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming. However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 716 78K0/Kx2 CHAPTER 26 OPTION BYTE (3) 0084H/1084H { On-chip debug operation control * Disabling on-chip debug operation * Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the on-chip debug security ID fails * Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped with the on-chip debug function (PD78F05xx and 78F05xxA). Also set 00H to 1084H because 0084H and 1084H are switched during the boot operation. 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F05xxD and 78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot operation. 26.2 Format of Option Byte The format of the option byte is shown below. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 717 78K0/Kx2 CHAPTER 26 OPTION BYTE Figure 26-1. Format of Option Byte (1/2) Note Address: 0080H/1080H 7 6 5 4 3 2 1 0 0 WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 0 0 25% 0 1 50% 1 0 75% 1 1 100% WDTON Watchdog timer window open period Operation control of watchdog timer counter/illegal access detection 0 Counter operation disabled (counting stopped after reset), illegal access detection operation disabled 1 Counter operation enabled (counting started after reset), illegal access detection operation enabled WDCS2 WDCS1 WDCS0 Watchdog timer overflow time 10 0 0 0 2 /fRL (3.88 ms) 0 0 1 2 /fRL (7.76 ms) 0 1 0 2 /fRL (15.52 ms) 0 1 1 2 /fRL (31.03 ms) 1 0 0 2 /fRL (62.06 ms) 1 0 1 2 /fRL (124.12 ms) 1 1 0 2 /fRL (248.24 ms) 1 1 1 2 /fRL (496.48 ms) LSROSC 11 12 13 14 15 16 17 Internal low-speed oscillator operation 0 Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register) 1 Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit) Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V VDD < 2.7 V. 3. The watchdog timer continues its operation during self-programming and EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 4. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit timer H1 even in the HALT/STOP mode. 5. Be sure to clear bit 7 to 0. Remarks 1. 2. fRL: Internal low-speed oscillation clock frequency ( ): fRL = 264 kHz (MAX.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 718 78K0/Kx2 CHAPTER 26 OPTION BYTE Figure 26-1. Format of Option Byte (2/2) Notes 1, 2 Address: 0081H/1081H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POCMODE POCMODE Notes 1. POC mode selection 0 1.59 V POC mode (default) 1 2.7 V/1.59 V POC mode POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming. However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. 2. To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip erasure) of the flash memory. The setting cannot be changed after the memory of the specified block is erased. Caution Be sure to clear bits 7 to 1 to "0". Note Address: 0082H/1082H, 0083H/1083H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082H and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is used. Notes1, 2 Address: 0084H/1084H Notes 1. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 OCDEN1 OCDEN0 OCDEN1 OCDEN0 0 0 On-chip debug operation control Operation disabled 0 1 Setting prohibited 1 0 Operation enabled. Does not erase data of the flash memory in case authentication of the on-chip debug security ID fails. 1 1 Operation enabled. Erases data of the flash memory in case authentication of the on-chip debug security ID fails. Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the on-chip debug function (PD78F05xx and 78F05xxA). Also set 00H to 1084H because 0084H and 1084H are switched during the boot swap operation. 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F05xxD and 78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot swap operation. Remark For the on-chip debug security ID, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 719 78K0/Kx2 CHAPTER 26 OPTION BYTE Here is an example of description of the software for setting the option bytes. OPT CSEG OPTION: DB AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 210/fRL, ; Internal low-speed oscillator can be stopped by software. Remark DB 00H ; 1.59 V POC mode DB 00H ; Reserved area DB 00H ; Reserved area DB 00H ; On-chip debug operation disabled Referencing of the option byte is performed during reset processing. For the reset processing timing, see CHAPTER 23 RESET FUNCTION. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 720 78K0/Kx2 CHAPTER 27 FLASH MEMORY CHAPTER 27 FLASH MEMORY The 78K0/Kx2 microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 27.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH. Caution Be sure to set each product to the values shown in Table 27-1 after a reset release. Figure 27-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H After reset: CFH Symbol 7 6 5 4 3 2 1 0 RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 0 0 0 768 bytes 0 1 0 512 bytes 1 1 0 1024 bytes IMS R/W Other than above Internal high-speed RAM capacity selection Setting prohibited ROM3 ROM2 ROM1 ROM0 0 0 1 0 8 KB 0 1 0 0 16 KB 0 1 1 0 24 KB 1 0 0 0 32 KB 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above Internal ROM capacity selection Setting prohibited Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 721 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-1. Internal Memory Size Switching Register Settings 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 - - - - 42H - 04H - C6H - C8H PD78F0500, IMS Setting 78F0500A PD78F0501, PD78F0511, PD78F0521, PD78F0531, 78F0501A 78F0511A 78F0521A 78F0531A PD78F0502, PD78F0512, PD78F0522, PD78F0532, 78F0502A 78F0512A 78F0522A 78F0532A PD78F0503, PD78F0513, PD78F0523, PD78F0533, 78F0503A, Note 1 , 78F0503D 78F0513A, 78F0523A 78F0533A PD78F0514, PD78F0524, PD78F0534, PD78F0544, 78F0514A 78F0524A 78F0534A 78F0544A PD78F0515, PD78F0525, PD78F0535, PD78F0545, 78F0525A 78F0535A 78F0545A PD78F0526, PD78F0536, PD78F0546, 78F0526A 78F0536A 78F0546A PD78F0527, PD78F0537, PD78F0547, 78F0503DA Note 1 - - Note 1 , 78F0513D 78F0513DA Note 1 78F0515A, Note 1 78F0515D 78F0515DA - - - - CFH , Note 1 78F0527A, 78F0537A, Note 1 78F0527D 78F0527DA Notes 1. CCH , Note 1 78F0537DA CCH Note 2 78F0547A, Note 1 78F0537D Note 2 CCH , Note 1 Note 1 78F0547D 78F0547DA , Note 1 The internal ROM capacity and internal high-speed RAM capacity of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS according to the debug target products. 2. The PD78F05x6 and 78F05x6A (x = 2 to 4) have internal ROMs of 96 KB, and the PD78F05x7, 78F05x7A, 78F05x7D, and 78F05x7DA (x = 2 to 4) have those of 128 KB. However, the set value of IMS of these devices is the same as those of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.3 Memory Bank Select Register (BANK). 27.2 Internal Expansion RAM Size Switching Register Select the internal expansion RAM capacity using the internal expansion RAM size switching register (IXS). IXS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IXS to 0CH. Caution Be sure to set each product to the values shown in Table 27-2 after a reset release. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 722 78K0/Kx2 CHAPTER 27 FLASH MEMORY Figure 27-2. Format of Internal Expansion RAM Size Switching Register (IXS) Address: FFF4H After reset: 0CH R/W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 1 1 0 0 0 bytes 1 0 1 0 1024 bytes 1 0 0 0 2048 bytes 0 1 0 0 4096 bytes 0 0 0 0 6144 bytes Other than above Internal expansion RAM capacity selection Setting prohibited Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and internal expansion RAM area do not overlap. Table 27-2. Internal Expansion RAM Size Switching Register Settings 48-pin products 78K0/KD2 78K0/KE2 78K0/KF2 IXS Setting of 78K0/KC2 PD78F0511, PD78F0521, PD78F0531, 78F0511A 78F0521A 78F0531A PD78F0512, PD78F0522, PD78F0532, 78F0512A 78F0522A 78F0532A PD78F0513, PD78F0523, PD78F0533, - 0CH - 0CH - 0CH 78F0513A 78F0523A 78F0533A PD78F0514, PD78F0524, PD78F0534, PD78F0544, 78F0514A 78F0524A 78F0534A 78F0544A PD78F0515, PD78F0525, PD78F0535, PD78F0545, 78F0515A, 78F0525A 78F0535A 78F0545A PD78F0526, PD78F0536, PD78F0546, 78F0526A 78F0536A 78F0546A PD78F0527, PD78F0537, PD78F0547, 78F0527A, 78F0537A, 78F0547A, Note 78F0515D 78F0515DA - - 08H , Note Note 78F0527D 78F0527DA Note 0AH , Note Note 78F0537D 78F0537DA , Note Note 78F0547D 78F0547DA 04H 00H , Note The internal expansion RAM capacity of the products with the on-chip debug function can be debugged according to the debug target products. Set IXS according to the debug target products. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 723 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.3 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/Kx2 microcontrollers have been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/Kx2 microcontrollers are mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 27.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/Kx2 microcontrollers are illustrated below. Figure 27-3. Environment for Writing Program to Flash Memory FLMD0 POWER RS-232C VDD PASS BUSY NG VSS USB START PG-FP5 Host machine RESET CSI10/UART6 78K0/Kx2 microcontrollers Dedicated flash memory programmer A host machine that controls the dedicated flash memory programmer is necessary. To interface between the dedicated flash memory programmer and the 78K0/Kx2 microcontrollers, CSI10 or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 724 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.5 Communication Mode Communication between the dedicated flash memory programmer and the 78K0/Kx2 microcontrollers is established by serial communication via CSI10 or UART6 of the 78K0/Kx2 microcontrollers. (1) CSI10 Transfer rate: 2.4 kHz to 2.5 MHz Figure 27-4. Communication with Dedicated Flash memory programmer (CSI10) FLMD0 FLMD0 POWER VDD VDD/EVDD/AVREF NG BUSY PASS GND START PG-FP5 Dedicated flash memory programmer /RESET VSS/EVSS/AVSS RESET SI/RxD SO10 SO/TxD SI10 SCK SCK10 78K0/Kx2 microcontrollers (2) UART6 Transfer rate: 115200 bps Figure 27-5. Communication with Dedicated Flash memory programmer (UART6) FLMD0 FLMD0 POWER VDD BUSY PASS VDD/EVDD/AVREF NG GND /RESET VSS/EVSS/AVSS RESET START PG-FP5 Dedicated flash memory programmer R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 SI/RxD TxD6 SO/TxD RxD6 CLK EXCLK 78K0/Kx2 microcontrollers 725 78K0/Kx2 CHAPTER 27 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the 78K0/Kx2 microcontrollers. For details, refer to the user's manual for the PG-FP5, FL-PR5, PG-FP4, or FL-PR4. Table 27-3. Pin Connection Dedicated Flash memory programmer 78K0/Kx2 Connection microcontrollers Signal Name I/O Pin Function Pin Name FLMD0 Output Mode signal FLMD0 VDD I/O VDD voltage generation/power monitoring VDD, EVDD, AVREF - GND Ground VSS, EVSS, AVSS CLK Output Clock output to 78K0/Kx2 microcontrollers EXCLK/X2/P122 /RESET Output Reset signal RESET SI/RxD Input Receive signal SO10/TxD6 SO/TxD Output Transmit signal SI10/RxD6 SCK Output Transfer clock SCK10 Notes 1. 2. Remark CSI10 x Note 1 UART6 { Note 2 x Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. : Be sure to connect the pin. {: The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 726 78K0/Kx2 CHAPTER 27 FLASH MEMORY For the pins not to be used when the dedicated program adapter (FA series) is used, perform the processing described under the recommended connection of unused pins shown in Table 2-3 Pin I/O Circuit Types, or those described in Table 27-4 Processing of Unused Pins When the Flash Memory Write Adapter Is Connected (Required). Table 27-4. Processing of Unused Pins When the Flash Memory Write Adapter Is Connected (Required) Pin name Pin processing P00, P01 Independently connect to EVSS via a resistor. Notes 1, 5 P03 to P06 Independently connect to EVSS via a resistor. Notes 2, 5 P10, P11 Independently connect to EVSS via a resistor. Notes 3, 5 P14 Independently connect to EVSS via a resistor. Notes 4, 5 P16, P17 Independently connect to EVSS via a resistor. Notes 1, 5 P30 to P33 P60 to P63 Independently connect to EVSS via a resistor, or connect directly to Note 5 EVSS. P70 to P77 Independently connect to EVSS via a resistor. Notes 1, 5 P120 P140 to P143 Notes 1. These pins may be directly connected to EVSS, without using a resistor, when design is performed so that operation is not switched to the normal operation mode on the flash memory write adapter board during flash memory programming. 2. These pins may be left open with the PD78F053n and 78F053nA (n = 1 to 3) of the 78K0/KE2 as well as the 78K0/KD2. 3. Connect these pins with the programmer when communicating with the dedicated flash memory programmer via serial communication by CSI10. 4. Connect this pin with the programmer when communicating with the dedicated flash memory programmer via serial communication by UART6. 5. With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect them to VDD. 27.6 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 727 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.6.1 FLMD0 pin In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below. Figure 27-6. FLMD0 Pin Connection Example 78K0/Kx2 microcontrollers Dedicated flash memory programmer connection pin FLMD0 10 k (recommended) 27.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 27-5. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 UART6 TxD6, RxD6 To connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 728 78K0/Kx2 CHAPTER 27 FLASH MEMORY (1) Signal collision If the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 27-7. Signal Collision (Input Pin of Serial Interface) 78K0/Kx2 microcontrollers Signal collision Input pin Dedicated flash memory programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. (2) Malfunction of other device If the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 27-8. Malfunction of Other Device 78K0/Kx2 microcontrollers Dedicated flash memory programmer connection pin Pin Other device Input pin If the signal output by the 78K0/Kx2 microcontrollers in the flash memory programming mode affects the other device, isolate the signal of the other device. 78K0/Kx2 microcontrollers Pin Dedicated flash memory programmer connection pin Other device Input pin If the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 729 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash memory programmer. Figure 27-9. Signal Collision (RESET Pin) 78K0/Kx2 microcontrollers Signal collision RESET Dedicated flash memory programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of the reset signal generator. 27.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to EVDDNote or EVSSNote via a resistor. Note With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect them to VDD. <R> 27.6.5 REGC pin Connect the REGC pin to VSS via a capacitor (0.47 to 1 F) in the same manner as during normal operation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 730 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.6.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the dedicated flash memory programmer, however, connect CLK of the programmer to EXCLK/X2/P122. Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. 2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. 3. For the product with an on-chip debug function (PD78F05xxD and 78F05xxDA), connect P31/INTP2/OCD1A and P121/X1/OCD0A as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1A: Connect to EVSSNote via a resistor. * P121/X1/OCD0A: Connect to VSSNote via a resistor. Note With products without an EVSS pin, connect them to VSS. 27.6.7 Power supply To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. However, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power monitor function with the flash memory programmer, even when using the on-board supply voltage. Supply the same other power supplies (EVDD, EVSS, AVREF, and AVSS) as those in the normal operation mode. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 731 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.7 Programming Method 27.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 27-10. Flash Memory Manipulation Procedure Start Flash memory programming mode is set FLMD0 pulse supply Selecting communication mode Manipulate flash memory No End? Yes End 27.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/Kx2 microcontrollers in the flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 27-11. Flash Memory Programming Mode VDD 5.5 V 0V VDD RESET 0V FLMD0 pulse VDD FLMD0 0V Flash memory programming mode Table 27-6. Relationship Between FLMD0 Pin and Operation Mode After Reset Release FLMD0 0 VDD R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Operation Mode Normal operation mode Flash memory programming mode 732 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.7.3 Selecting communication mode In the 78K0/Kx2 microcontrollers, a communication mode is selected by inputting pulses to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash memory programmer. The following table shows the relationship between the number of pulses and communication modes. Table 27-7. Communication Modes Communication Mode Standard Setting Port UART (UART6) UART-Ext-Osc 3-wire serial I/O (CSI10) CSI-Internal-OSC Speed Note 1 Pins Used Frequency Note 3 115,200 bps Note 2 2 to 20 MHz Multiply Rate 1.0 TxD6, RxD6 UART-Ext-FP5CK 2.4 kHz to 2.5 MHz - SO10, SI10, SCK10 Peripheral Number of Clock FLMD0 Pulses fX 0 fEXCLK 3 fRH 8 Notes 1. Selection items for Standard settings on GUI of the flash memory programmer. 2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash memory programmer after the FLMD0 pulse has been received. Remark fX : X1 clock fEXCLK: External main system clock fRH: Internal high-speed oscillation clock R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 733 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.7.4 Communication commands The 78K0/Kx2 microcontrollers communicate with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0/Kx2 microcontrollers are called commands, and the signals sent from the 78K0/Kx2 microcontrollers to the dedicated flash memory programmer are called response. Figure 27-12. Communication Commands POWER PASS BUSY Command NG Response START PG-FP5 78K0/Kx2 microcontrollers Dedicated flash memory programmer The flash memory control commands of the 78K0/Kx2 microcontrollers are listed in the table below. All these commands are issued from the programmer and the 78K0/Kx2 microcontrollers perform processing corresponding to the respective commands. Table 27-8. Flash Memory Control Commands Classification Verify Command Name Function Compares the contents of a specified area of the flash memory with Verify data transmitted from the programmer. Erase Blank check Chip Erase Erases the entire flash memory. Block Erase Erases a specified area in the flash memory. Block Blank Check Checks if a specified block in the flash memory has been correctly erased. Write Programming Writes data to a specified area in the flash memory. Getting information Status Gets the current operating status (status data). Silicon Signature Gets 78K0/Kx2 information (such as the part number and flash memory configuration). Version Get Gets the 78K0/Kx2 version and firmware version. Checksum Gets the checksum data for a specified area. Security Security Set Sets security information. Others Reset Used to detect synchronization status of communication. Oscillating Frequency Set Specifies an oscillation frequency. The 78K0/Kx2 microcontrollers return a response for the command issued by the dedicated flash memory programmer. The response names sent from the 78K0/Kx2 microcontrollers are listed below. Table 27-9. Response Names Response Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 734 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.8 Security Settings The 78K0/Kx2 microcontrollers support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next. * Disabling batch erase (chip erase) Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board programming. Once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. Caution After the security setting for the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written, because the erase command is disabled. * Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-board programming. However, blocks can be erased by means of self programming. * Disabling write Execution of the write and block erase commands for entire blocks in the flash memory is prohibited during onboard/off-board programming. However, blocks can be written by means of self programming. * Disabling rewriting boot cluster 0 Execution of the block erase command and write command on boot cluster 0 (0000H to 0FFFH) in the flash memory is prohibited by this setting. Execution of the batch erase (chip erase) command is also prohibited by this setting. Caution If a security setting that rewrites boot cluster 0 has been applied, the rewriting of boot cluster 0 and the batch erase (chip erase) will not be executed for the device. The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. Security can be set by on-board/off-board programming and self programming. Each security setting can be used in combination. Prohibition of erasing blocks and writing is cleared by executing the batch erase (chip erase) command. Table 27-10 shows the relationship between the erase and write commands when the 78K0/Kx2 microcontroller security function is enabled. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 735 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-10. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Prohibition of batch erase (chip erase) Prohibition of block erase Block Erase Write Note Cannot be erased in batch Blocks cannot be Can be performed Can be erased in batch. erased. Can be performed. Prohibition of writing . Cannot be performed. Prohibition of rewriting boot cluster 0 Cannot be erased in batch Boot cluster 0 cannot be Boot cluster 0 cannot be erased. written. Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase (chip erase) is prohibited, do not write data if the data has not been erased. (2) During self programming Valid Security Executed Command Block Erase Prohibition of batch erase (chip erase) Write Blocks can be erased. Can be performed. Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Prohibition of block erase Prohibition of writing Prohibition of rewriting boot cluster 0 Table 27-11 shows how to perform security settings in each programming mode. Table 27-11. Setting Security in Each Programming Mode (1) On-board/off-board programming Security Security Setting How to Disable Security Setting Prohibition of batch erase (chip erase) Set via GUI of dedicated flash memory Cannot be disabled after set. Prohibition of block erase programmer, etc. Execute batch erase (chip erase) Prohibition of writing command Prohibition of rewriting boot cluster 0 Cannot be disabled after set. (2) Self programming Security Prohibition of batch erase (chip erase) Security Setting Set by using information library. How to Disable Security Setting Cannot be disabled after set. Prohibition of block erase Execute batch erase (chip erase) Prohibition of writing command during on-board/off-board programming (cannot be disabled during self programming) Prohibition of rewriting boot cluster 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Cannot be disabled after set. 736 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.9 Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP4 or PG-FP5 is used as a dedicated flash memory programmer. Table 27-12. Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) (1/2) (1) Products with internal ROMs of the 32 KB Command of Port: CSI-Internal-OSC Port: UART-Ext-FP4CK (External main system clock (fEXCLK)), PG-FP4 (Internal high-speed oscillation Speed: 115,200 bps clock (fRH)), Frequency: 2.0 MHz Speed: 2.5 MHz Frequency: 20 MHz Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Blankcheck 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Erase 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Program 2.5 s (TYP.) 5 s (TYP.) 5 s (TYP.) Verify 1.5 s (TYP.) 4 s (TYP.) 3.5 s (TYP.) E.P.V 3.5 s (TYP.) 6 s (TYP.) 6 s (TYP.) Checksum 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) (2) Products with internal ROMs of the 60 KB Command of Port: CSI-Internal-OSC PG-FP4 (Internal high-speed oscillation clock (fRH)), Speed: 2.5 MHz Port: UART-Ext-FP4CK (External main system clock (fEXCLK)), Speed: 115,200 bps Frequency: 2.0 MHz Frequency: 20 MHz Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Blankcheck 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) Erase 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) Program 5 s (TYP.) 9 s (TYP.) 9 s (TYP.) Verify 2 s (TYP.) 6.5 s (TYP.) 6.5 s (TYP.) E.P.V 6 s (TYP.) 10.5 s (TYP.) 10.5 s (TYP.) Checksum 0.5 s (TYP.) 1 s (TYP.) 1 s (TYP.) Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Caution When executing boot swapping, do not use the E.P.V. command with the dedicated flash memory programmer. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 737 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-12. Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) (2/2) (3) Products with internal ROMs of the 128 KB Command of Port: CSI-Internal-OSC Port: UART-Ext-FP4CK (External main system clock (fEXCLK)), PG-FP4 (Internal high-speed oscillation Speed: 115,200 bps clock (fRH)), Speed: 2.5 MHz Frequency: 2.0 MHz Frequency: 20 MHz Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Blankcheck 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) Erase 1.5 s (TYP.) 1.5 s (TYP.) 1.5 s (TYP.) Program 9.5 s (TYP.) 18 s (TYP.) 18 s (TYP.) Verify 4.5 s (TYP.) 13.5 s (TYP.) 13.5 s (TYP.) E.P.V 11 s (TYP.) 19.5 s (TYP.) 19.5 s (TYP.) Checksum 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) Caution When executing boot swapping, do not use the E.P.V. command with the dedicated flash memory programmer. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 738 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.10 Flash Memory Programming by Self-Programming The 78K0/Kx2 microcontrollers support a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using a self-programming library, it can be used to upgrade the program in the field. If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt servicing can be executed. To execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute the EI instruction. After the self-programming mode is later restored, self-programming can be resumed. Remark For details of the self-programming function and the self-programming library, refer to 78K0 Microcontrollers Self Programming Library Type01 User's Manual (U18274E). Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2. Oscillation of the internal high-speed oscillator is started during self programming, regardless of the setting of the RSTOP flag (bit 0 of the internal oscillation mode register (RCM)). Oscillation of the internal high-speed oscillator cannot be stopped even if the STOP instruction is executed. 3. Input a high level to the FLMD0 pin during self-programming. 4. Be sure to execute the DI instruction before starting self-programming. The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H). If an interrupt request is generated, self-programming is stopped. 5. Self-programming is also stopped by an interrupt request that is not masked even in the DI status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L, MK0H, MK1L, and MK1H). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 739 78K0/Kx2 CHAPTER 27 FLASH MEMORY Caution 6. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. Figure 27-13. Operation Mode and Memory Map for Self-Programming (PD78F0547 and 78F0547A) FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH Reserved Buffer RAM Reserved Memory bank 4 Memory bank 2 Internal expansion RAM E000H DFFFH C000H BFFFH FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH SFR Internal highspeed RAM Reserved Flash memory control firmware ROM Flash memory (memory bank 0) Disable accessing 8000H 7FFFH Memory bank 5 SFR Internal highspeed RAM Reserved Buffer RAM Reserved Memory bank 2 Internal expansion RAM E000H DFFFH C000H BFFFH Reserved Flash memory control firmware ROM Disable accessing Enable accessing 8000H 7FFFH Memory bank 5 Memory bank 3 Flash memory (common area) Memory bank 1 0000H Normal mode R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Memory bank 4 Instructions can be fetched from common area and selected memory bank. 0000H Flash memory (common area) Memory bank 3 Memory bank 1 Instructions can be fetched from common area and firmware ROM. Self-programming mode 740 78K0/Kx2 CHAPTER 27 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self-programming library. Figure 27-14. Flow of Self Programming (Rewriting Flash Memory) Start of self programming FlashStart Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Normal completion? No Yes FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? No Yes FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? No Yes Normal completion Error FlashEnd End of self programming Remark For details of the self-programming library, refer to 78K0 Microcontrollers Self Programming Library Type01 User's Manual (U18274E). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 741 78K0/Kx2 CHAPTER 27 FLASH MEMORY The following table shows the processing time and interrupt response time for the self-programming library. Table 27-13. Processing Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (1/4) (1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 4.25 Initialize library 977.75 Mode check library Block blank check library 753.875 753.125 12770.875 12765.875 Block erase library 36909.5 356318 36904.5 356296.25 Word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375) Block verify library 25618.875 25613.875 Self programming end library Get information library 4.25 Option value: 03H 871.25 (871.375) 866 (866.125) Option value: 04H 863.375 (863.5) 858.125 (858.25) Option value: 05H 1024.75 (1043.625) 1037.5 (1038.375) Set information library 105524.75 790809.375 105523.75 EEPROM write library 1496.5 2691.5 1489.5 790808.375 2684.5 (1496.875) (2691.875) (1489.875) (2684.875) Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 742 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-13. Processing Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (2/4) (2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 4.25 Initialize library 443.5 Mode check library Block blank check library 219.625 218.875 12236.625 12231.625 Block erase library 36363.25 355771.75 36358.25 355750 Word write library 679.75 1874.75 672.75 1867.75 (1875.125) (673.125) (680.125) Block verify library 25072.625 Self programming end library Get information library (1868.125) 25067.625 4.25 Option value: 03H 337 (337.125) 331.75 (331.875) Option value: 04H 329.125 (239.25) 323.875 (324) Option value: 05H 502.25 (503.125) Set information library EEPROM write library 104978.5 541143.125 497 (497.875) 104977.5 541142.125 962.25 2157.25 955.25 2150.25 (962.625) (2157.625) (955.625) (2150.625) Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 743 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-13. Processing Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (3/4) (3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 34/fCPU Initialize library 49/fCPU + 485.8125 Mode check library Block blank check library Block erase library Word write library Block verify library 35/fCPU + 374.75 29/fCPU + 374.75 174/fCPU + 6382.0625 134/fCPU + 6382.0625 174/fCPU + 174/fCPU + 134/fCPU + 134/fCPU + 31093.875 298948.125 31093.875 298948.125 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 644.125 1491.625 644.125 1491.625 174/fCPU + 13448.5625 Self programming end library Get information library 134/fCPU + 13448.5625 34/fCPU Option value: 03H 171 (172 )/fCPU + 432.4375 129 (130)/fCPU + 432.4375 Option value: 04H 181 (182)/fCPU + 427.875 139 (140)/fCPU + 427.875 Option value: 05H 404 (411)/fCPU + 496.125 Set information library 75/fCPU + 75/fCPU + 652400 79157.6875 EEPROM write library 362 (369)/fCPU + 496.125 67fCPU + 67fCPU + 652400 79157.6875 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 799.875 1647.375 799.875 1647.375 Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. fCPU: CPU operation clock frequency 4. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 744 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-13. Processing Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (4/4) (4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Self programming start library Min. Max. 34/fCPU Initialize library 49/fCPU + 224.6875 Mode check library Block blank check library Block erase library Word write library Block verify library 35/fCPU + 113.625 29/fCPU + 113.625 174/fCPU + 6120.9375 134/fCPU + 6120.9375 174/fCPU + 174/fCPU + 134/fCPU + 30820.75 298675 30820.75 298675 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 383 1230.5 383 1230.5 174/fCPU + 13175.4375 Self programming end library Get information library 134/fCPU + 134/fCPU + 13175.4375 34/fCPU Option value: 03H 171 (172)/fCPU + 171.3125 Option value: 04H 181 (182)/fCPU + 166.75 139 (140)/fCPU + 166.75 Option value: 05H 404 (411)/fCPU + 231.875 362 (369)/fCPU + 231.875 Set information library EEPROM write library 129 (130)/fCPU + 171.3125 75/fCPU + 75/fCPU + 67fCPU + 67fCPU + 78884.5625 527566.875 78884.5625 527566.875 318 (321)/fCPU + 318 (321)/fCPU + 262 (265)/fCPU + 262 (265)/fCPU + 538.75 1386.25 538.75 1386.25 Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the internal high-speed RAM. 2. The above processing times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 3. fCPU: CPU operation clock frequency 4. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 745 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-14. Processing Time for Self Programming Library (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (1/3) (1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Self programming start library Initialize library Mode check library Block blank check library Static Model of C Compiler/Assembler Min. Max. Min. 4.0 4.5 4.0 Max. 4.5 1105.9 1106.6 1105.9 1106.6 905.7 906.1 904.9 905.3 12776.1 12778.3 12770.9 12772.6 Block erase library 26050.4 349971.3 26045.3 349965.6 Word write library 1180.1 + 203 x w 1184.3 + 2241 x w 1172.9 + 203 x w 1176.3 + 2241 x w Block verify library 25337.9 25340.2 25332.8 25334.5 4.0 4.5 4.0 4.5 1072.9 1075.2 1067.5 1069.1 Self programming end library Get information library Option value: 03H Option value: 04H 1060.2 1062.6 1054.8 1056.6 Option value: 05H 1023.8 1028.2 1018.3 1022.1 Set information library 70265.9 759995.0 70264.9 759994.0 EEPROM write library 1316.8 + 347 x w 1320.9 + 2385 x w 1309.0 + 347 x w 1312.4 + 2385 x w (2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Self programming start library Initialize library Mode check library Static Model of C Compiler/Assembler Min. Max. Min. 4.0 4.5 4.0 Max. 4.5 449.5 450.2 449.5 450.2 249.3 249.7 248.6 248.9 Block blank check library 12119.7 12121.9 12114.6 12116.3 Block erase library 25344.7 349266.4 25339.6 349260.8 Word write library 445.8 + 203 x w 449.9 + 2241 x w 438.5 + 203 x w 441.9 + 2241 x w Block verify library 24682.7 24684.9 24677.6 24679.3 4.0 4.5 4.0 4.5 417.6 419.8 412.1 413.8 Self programming end library Get information library Option value: 03H Option value: 04H 405.0 407.4 399.5 401.3 Option value: 05H 367.4 371.8 361.9 365.8 Set information library 69569.3 759297.3 69568.3 759296.2 EEPROM write library 795.1 + 347 x w 799.3 + 2385 x w 787.4 + 347 x w 790.8 + 2385 x w Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 746 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-14. Processing Time for Self Programming Library (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (2/3) (3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Min. Self programming start library Max. 34/fCPU Initialize library 55/fCPU + 594 Mode check library Block blank check library 36/fCPU + 495 30/fCPU + 495 179/fCPU + 6429 136/fCPU + 6429 Block erase library 179/fCPU + 19713 179/fCPU + 268079 136/fCPU + 19713 136/fCPU + 268079 Word write library 333/fCPU + 647 + 333/fCPU + 647 + 272/fCPU + 647 + 272/fCPU + 647 + 136 x w 1647 x w 136 x w 1647 x w Block verify library 179/fCPU + 13284 Self programming end library Get information library 136/fCPU + 13284 34/fCPU Option value: 03H 180/fCPU + 581 134/fCPU + 581 Option value: 04H 190/fCPU + 574 144/fCPU + 574 Option value: 05H 350/fCPU + 535 304/fCPU + 535 Set information library 80/fCPU + 43181 80/fCPU + 572934 72/fCPU + 43181 72/fCPU + 572934 EEPROM write library 333/fCPU + 729 + 333/fCPU + 729 + 268/fCPU + 729 + 268/fCPU + 729 + 209 x w 1722 x w 209 x w 1722 x w Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. fCPU: CPU operation clock frequency 4. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 747 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-14. Processing Time for Self Programming Library (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (3/3) (4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range Processing Time (s) Library Name Normal Model of C Compiler Min. Static Model of C Compiler/Assembler Max. Min. Self programming start library Max. 34/fCPU Initialize library 55/fCPU + 272 Mode check library Block blank check library 36/fCPU + 173 30/fCPU + 173 179/fCPU + 6108 136/fCPU + 6108 Block erase library 179/fCPU + 19371 179/fCPU + 267738 136/fCPU + 19371 136/fCPU + 267738 Word write library 333/fCPU + 247 + 333/fCPU + 247 + 272/fCPU + 247 + 272/fCPU + 247 + 136 x w 1647 x w 136 x w 1647 x w Block verify library 179/fCPU+12964 Self programming end library Get information library 136/fCPU+12964 34/fCPU Option value: 03H 180/fCPU + 261 134/fCPU + 261 Option value: 04H 190/fCPU + 254 144/fCPU + 254 Option value: 05H 350/fCPU + 213 304/fCPU + 213 Set information library 80/fCPU + 42839 80/fCPU + 572592 72/fCPU + 42839 72/fCPU + 572592 EEPROM write library 333/fCPU + 516 + 333/fCPU + 516 + 268/fCPU + 516 + 268/fCPU + 516 + 209 x w 1722 x w 209 x w 1722 x w Remarks 1. The above processing times are those when a write start address structure is located in the internal highspeed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) 3. fCPU: CPU operation clock frequency 4. w: Number of words in write data (1 word = 4 bytes) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 748 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-15. Interrupt Response Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (1/2) (1) When internal high-speed oscillation clock is used Interrupt Response Time (s (Max.)) Library Name Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 933.6 668.6 927.9 Block erase library 1026.6 763.6 1020.9 662.9 757.9 Word write library 2505.8 1942.8 2497.8 1934.8 Block verify library 958.6 693.6 952.9 687.9 Set information library 476.5 211.5 475.5 210.5 EEPROM write library 2760.8 2168.8 2759.5 2167.5 Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) (2) When high-speed system clock is used (normal model of C compiler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 179/fCPU + 507 179/fCPU + 407 179/fCPU + 1650 Block erase library 179/fCPU + 559 179/fCPU + 460 179/fCPU + 1702 179/fCPU + 767 Word write library 333/fCPU + 1589 333/fCPU + 1298 333/fCPU + 2732 333/fCPU + 1605 Block verify library 179/fCPU + 518 179/fCPU + 418 179/fCPU + 1661 179/fCPU + 725 Set information library 80/fCPU + 370 80/fCPU + 165 80/fCPU + 1513 80/fCPU + 472 29/fCPU + 1759 29/fCPU + 1468 29/fCPU + 1759 29/fCPU + 1468 333/fCPU + 834 333/fCPU + 512 333/fCPU + 2061 333/fCPU + 873 Note EEPROM write library 179/fCPU + 714 Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 749 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-15. Interrupt Response Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) (2/2) (3) When high-speed system clock is used (static model of C compiler/assembler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 136/fCPU + 507 136/fCPU + 407 136/fCPU + 1650 Block erase library 136/fCPU + 559 136/fCPU + 460 136/fCPU + 1702 136/fCPU + 767 Word write library 272/fCPU + 1589 272/fCPU + 1298 272/fCPU + 2732 272/fCPU + 1605 Block verify library 136/fCPU + 518 136/fCPU + 418 136/fCPU + 1661 136/fCPU + 725 Set information library 72/fCPU + 370 72/fCPU + 165 72/fCPU + 1513 72/fCPU + 472 19/fCPU + 1759 19/fCPU + 1468 19/fCPU + 1759 19/fCPU + 1468 268/fCPU + 834 268/fCPU + 512 268/fCPU + 2061 268/fCPU + 873 Note EEPROM write library 136/fCPU + 714 Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 750 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-16. Interrupt Response Time for Self Programming Library (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (1/2) (1) When internal high-speed oscillation clock is used Interrupt Response Time (s (Max.)) Library Name Normal Model of C Compiler Static Model of C Compiler/Assembler Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 1100.9 431.9 1095.3 426.3 Block erase library 1452.9 783.9 1447.3 778.3 Word write library 1247.2 579.2 1239.2 571.2 Block verify library 1125.9 455.9 1120.3 450.3 Set information library 906.9 312.0 905.8 311.0 EEPROM write library 1215.2 547.2 1213.9 545.9 Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed oscillator (RSTS = 1). 2. RSTS: Bit 7 of the internal oscillation mode register (RCM) (2) When high-speed system clock is used (normal model of C compiler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 179/fCPU + 567 179/fCPU + 246 179/fCPU + 1708 179/fCPU + 569 Block erase library 179/fCPU + 780 179/fCPU + 459 179/fCPU + 1921 179/fCPU + 782 Word write library 333/fCPU + 763 333/fCPU + 443 333/fCPU + 1871 333/fCPU + 767 Block verify library 179/fCPU + 580 179/fCPU + 259 179/fCPU + 1721 179/fCPU + 582 80/fCPU + 456 80/fCPU + 200 80/fCPU + 1598 80/fCPU + 459 29/fCPU + 767 29/fCPU + 447 29/fCPU + 767 29/fCPU + 447 333/fCPU + 696 333/fCPU + 376 333/fCPU + 1838 333/fCPU + 700 Set information library Note EEPROM write library Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 751 78K0/Kx2 CHAPTER 27 FLASH MEMORY Table 27-16. Interrupt Response Time for Self Programming Library (Expanded-specification Products (PD78F05xxA and 78F05xxDA)) (2/2) (3) When high-speed system clock is used (static model of C compiler/assembler) Interrupt Response Time (s (Max.)) Library Name RSTOP = 0, RSTS = 1 RSTOP = 1 Entry RAM location Entry RAM location Entry RAM location is outside short is in short direct is outside short is in short direct direct addressing addressing range direct addressing addressing range range Entry RAM location range Block blank check library 136/fCPU + 567 136/fCPU + 246 136/fCPU + 1708 136/fCPU + 569 Block erase library 136/fCPU + 780 136/fCPU + 459 136/fCPU + 1921 136/fCPU + 782 Word write library 272/fCPU + 763 272/fCPU + 443 272/fCPU + 1871 272/fCPU + 767 Block verify library 136/fCPU + 580 136/fCPU + 259 136/fCPU + 1721 136/fCPU + 582 Set information library 72/fCPU + 456 72/fCPU + 200 72/fCPU + 1598 72/fCPU + 459 19/fCPU + 767 19/fCPU + 447 19/fCPU + 767 19/fCPU + 447 268/fCPU + 696 268/fCPU + 376 268/fCPU + 1838 268/fCPU + 700 Note EEPROM write library Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on the value of fCPU. Remarks 1. fCPU: CPU operation clock frequency 2. RSTOP: Bit 0 of the internal oscillation mode register (RCM) 3. RSTS: Bit 7 of the internal oscillation mode register (RCM) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 752 78K0/Kx2 CHAPTER 27 FLASH MEMORY 27.10.1 Boot swap function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78K0/Kx2 microcontrollers, so that boot cluster 1 is used as a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. If the program has been correctly written to boot cluster 0, restore the original boot area by using the set information function of the firmware of the 78K0/Kx2 microcontrollers. Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function. Boot cluster 0 (0000H to 0FFFH): Original boot program area Boot cluster 1 (1000H to 1FFFH): Area subject to boot swap function Caution When executing boot swapping, do not use the E.P.V command with the dedicated flash memory programmer. Figure 27-15. Boot Swap Function XXXXH User program Self programming to boot cluster 1 User program Executing boot swapping by firmware User program 2000H User program New boot program (boot cluster 1) New boot program (boot cluster 1) Boot program (boot cluster 0) Boot program (boot cluster 0) Boot program (boot cluster 0) 1000H 0000H Boot Boot Boot XXXXH Self programming to boot cluster 0 User program Executing boot swapping by firmware User program 2000H 1000H 0000H Remark New boot program (boot cluster 1) New boot program (boot cluster 1) Boot New boot program (boot cluster 0) New boot program (boot cluster 0) Boot Boot cluster 1 becomes 0000H to 0FFFH when a reset is generated after the boot flag has been set. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 753 78K0/Kx2 CHAPTER 27 FLASH MEMORY Figure 27-16. Example of Executing Boot Swapping Block number Boot cluster 1 Boot cluster 0 7 6 5 4 3 2 1 0 Program Program Program Program Boot program Boot program Boot program Boot program 1000H 0000H Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Program Program Program Boot program Boot program Boot program Boot program Program Program Boot program Boot program Boot program Boot program Program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Booted by boot cluster 0 Writing blocks 5 to 7 7 New boot program 6 New boot program 5 New boot program 4 New boot program 3 Boot program 2 Boot program 1 Boot program 0 Boot program Boot swap 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program Boot program 0000H 1000H Erasing block 0 Erasing block 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program New boot program New boot program New boot program New boot program Boot program Boot program Booted by boot cluster 1 Erasing block 2 Erasing block 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program New boot program New boot program New boot program New boot program Writing blocks 0 to 3 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program New boot program New boot program New boot program New boot program Boot swap 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program 1 0 0 0 H New boot program New boot program New boot program New boot program 0 0 0 0 H Booted by boot cluster 0 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 754 78K0/Kx2 CHAPTER 27 FLASH MEMORY <R> 27.11 Creating ROM Code to Place Order for Previously Written Product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). The HCU is a software tool that includes functions required for creating ROM code. The HCU can be downloaded at the Renesas Electronics website. (1) Website http:www2.renesas.com/micro/en/ods Click Version-up Service. (2) Downloading the HCU To download the HCU, click Software for previously written flash products and then HCU_GUI. Remark For details about how to install and use the HCU, see the materials (the user's manual) that comes with the HCU at the above website. 27.11.1 Procedure for using ROM code to place an order Use the HCU to create the ROM code by following the procedure below, and then place your order with Renesas Electronics. For details, see the ROM Code Ordering Method Information (C10302J). Renesas Electronics Customer Decide which product to order. Send the order information. Renesas Electronics processes the product name and number and creates a record of the transaction. Create the ROM code Note Check the ROM order details and generate the required data. Renesas Electronics sends the order number and other order-related information. Send the data required for the ROM order. Note Use the HCU to create the ROM code for the order. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Renesas Electronics processes the ROM code. 755 78K0/Kx2 CHAPTER 28 ON-CHIP DEBUG FUNCTION CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxD and 78F05xxDA ONLY) 28.1 Connecting QB-MINI2 to PD78F05xxD and 78F05xxDA The PD78F05xxD and 78F05xxDA use the VDD, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). Whether OCD0A/X1 and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected. Caution The PD78F05xxD and 78F05xxDA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Remark PD78F05xxD: PD78F0503D, 78F0513D, 78F0515D, 78F0527D, 78F0537D, 78F0547D PD78F05xxDA: PD78F0503DA, 78F0513DA, 78F0515DA, 78F0527DA, 78F0537DA, 78F0547DA Figure 28-1. Connection Example of QB-MINI2 and PD78F05xxD and 78F05xxDA (When OCD0A/X1 and OCD0B/X2 Are Used) Target connector (10-pin) VDD VDD VDD 1 k (Recommended) Reset circuit Reset signal RESET_INNote 1 10 k (Recommended) Target device RESET RESET_OUT FLMD0 FLMD0 Note 2 VDD VDD DATA X2/OCD0B GND CLK X1/OCD0A P31 GND GND R.F.U. (Open) R.F.U. (Open) Note 2 Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer (output resistance: 100 or less). For details, refer to QB-MINI2 User's Manual (U18371E). 2. Make pull-down resistor 470 or more (10 k: recommended). Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging. 2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin or by using an external circuit using the P130 pin (that outputs a low level when the device is reset). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 756 78K0/Kx2 CHAPTER 28 ON-CHIP DEBUG FUNCTION Figure 28-2. Connection Example of QB-MINI2 and PD78F05xxD and 78F05xxDA (When OCD1A/P31 and OCD1B/P32 Are Used) Target connector (10-pin) VDD VDD VDD 3 to 10 k (Recommended) Note 2 VDD Reset circuit 1 k Reset signal (Recommended) RESET_INNote 1 10 k Target device (Recommended) RESET RESET_OUT FLMD0 FLMD0 Note 3 VDD VDD DATA OCD1B/P32 GND CLK OCD1A/P31 GND GND R.F.U. (Open) R.F.U. Note 3 (Open) Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer (output resistance: 100 or less). For details, refer to QB-MINI2 User's Manual (U18371E). 2. This is the processing of the pin when OCD1B/P32 is set as the input port (to prevent the pin from being left opened when not connected to QB-MINI2). 3. Make pull-down resistor 470 or more (10 k: recommended). Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging. Figure 28-3. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging Target connector Target device Port 1 k (recommended) FLMD0 FLMD0 10 k (recommended) Caution When using the port that controls the FLMD0 pin, make sure that it satisfies the values of the highlevel output current and FLMD0 supply voltage (minimum value: 0.8VDD) stated in CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 757 78K0/Kx2 CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.2 Reserved Area Used by QB-MINI2 QB-MINI2 uses the reserved areas shown in Figure 28-4 below to implement communication with the PD78F05xxD and 78F05xxDA, or each debug function. The shaded reserved areas are used for the respective debug functions to be used, and the other areas are always used for debugging. These reserved areas can be secured by using user programs and compiler options. When using a boot swap operation during self programming, set the same value to boot cluster 1 beforehand. For details on reserved area, refer to QB-MINI2 User's Manual (U18371E). Figure 28-4. Reserved Area Used by QB-MINI2 Internal ROM space Internal RAM space Stack area for debugging (Max. 16 bytes) 28FH Pseudo RRM area (256 bytes) 190H 18FH FF7FH Debug monitor area (257 bytes) 8FH 8EH 85H 84H F7F0H Pseudo RRM area (16 bytes)Note Security ID area (10 bytes) Option byte area (1 byte) 7 F H Software break area (2 bytes) 7EH 03H 02H Debug monitor area (2 bytes) 00H Note With products not incorporated the internal expansion RAM (PD78F0503D, 78F0503DA, 78F0513D, and 78F0513DA), it is not necessary to secure this area. Remark Shaded reserved areas: Area used for the respective debug functions to be used Other reserved areas: R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Areas always used for debugging 758 78K0/Kx2 CHAPTER 29 INSTRUCTION SET CHAPTER 29 INSTRUCTION SET This chapter lists each instruction set of the 78K0/Kx2 microcontrollers in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 29-1. Operand Identifiers and Specification Methods Identifier Specification Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special function register symbol sfrp Special function register symbol (16-bit manipulatable register even addresses only) saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even address only) addr16 0000H to FFFFH Immediate data or labels Note Note (Only even addresses for 16-bit data transfer instructions) addr11 0800H to 0FFFH Immediate data or labels addr5 0040H to 007FH Immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label RBn RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, see Table 3-8 Special Function Register List. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 759 78K0/Kx2 CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag RBS: Register bank select flag IE: Interrupt request enable flag ( ): Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 29.1.3 Description of flag operation column (Blank): Not affected 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 760 78K0/Kx2 CHAPTER 29 INSTRUCTION SET 29.2 Operation List Instruction Group Mnemonic Operands Clocks Bytes Note 1 8-bit data MOV transfer 2 4 - r byte saddr, #byte 3 6 7 (saddr) byte 3 - 7 sfr byte A, r Note 3 1 2 - Ar r, A Note 3 1 2 - rA A, saddr 2 4 5 A (saddr) saddr, A 2 4 5 (saddr) A A, sfr 2 - 5 A sfr sfr, A 2 - 5 sfr A A, !addr16 3 8 9 A (addr16) !addr16, A 3 8 9 (addr16) A PSW, #byte 3 - 7 PSW byte A, PSW 2 - 5 A PSW PSW, A 2 - 5 PSW A A, [DE] 1 4 5 A (DE) [DE], A 1 4 5 (DE) A A, [HL] 1 4 5 A (HL) [HL], A 1 4 5 (HL) A A, [HL + byte] 2 8 9 A (HL + byte) [HL + byte], A 2 8 9 (HL + byte) A A, [HL + B] 1 6 7 A (HL + B) [HL + B], A 1 6 7 (HL + B) A A, [HL + C] 1 6 7 A (HL + C) 1 6 7 (HL + C) A [HL + C], A XCH Notes 1. Z AC CY Note 2 r, #byte sfr, #byte 1 2 - Ar A, saddr 2 4 6 A (saddr) A, sfr 2 - 6 A (sfr) A, r Note 3 Flag Operation A, !addr16 3 8 10 A (addr16) A, [DE] 1 4 6 A (DE) A, [HL] 1 4 6 A (HL) A, [HL + byte] 2 8 10 A (HL + byte) A, [HL + B] 2 8 10 A (HL + B) A, [HL + C] 2 8 10 A (HL + C) x x x x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 761 78K0/Kx2 Instruction Group 16-bit data CHAPTER 29 INSTRUCTION SET Mnemonic MOVW transfer Operands Note 1 Note 2 6 - rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 - 10 sfrp word AX, saddrp 2 6 8 AX (saddrp) saddrp, AX 2 6 8 (saddrp) AX AX, sfrp 2 - 8 AX sfrp 2 - 8 sfrp AX AX, rp Note 3 1 4 - AX rp rp, AX Note 3 1 4 - rp AX AX, !addr16 3 10 12 AX (addr16) !addr16, AX 3 10 12 (addr16) AX 1 4 - AX rp XCHW AX, rp ADD A, #byte 2 4 - A, CY A + byte x x x saddr, #byte 3 6 8 (saddr), CY (saddr) + byte x x x 2 4 - A, CY A + r x x x r, A 2 4 - r, CY r + A x x x A, saddr 2 4 5 A, CY A + (saddr) x x x operation A, r ADDC Note 4 A, !addr16 3 8 9 A, CY A + (addr16) x x x A, [HL] 1 4 5 A, CY A + (HL) x x x A, [HL + byte] 2 8 9 A, CY A + (HL + byte) x x x A, [HL + B] 2 8 9 A, CY A + (HL + B) x x x A, [HL + C] 2 8 9 A, CY A + (HL + C) x x x A, #byte 2 4 - A, CY A + byte + CY x x x 3 6 8 (saddr), CY (saddr) + byte + CY x x x 2 4 - A, CY A + r + CY x x x r, A 2 4 - r, CY r + A + CY x x x A, saddr 2 4 5 A, CY A + (saddr) + CY x x x A, !addr16 3 8 9 A, CY A + (addr16) + C x x x A, [HL] 1 4 5 A, CY A + (HL) + CY x x x A, [HL + byte] 2 8 9 A, CY A + (HL + byte) + CY x x x A, [HL + B] 2 8 9 A, CY A + (HL + B) + CY x x x A, [HL + C] 2 8 9 A, CY A + (HL + C) + CY x x x saddr, #byte A, r Notes 1. Z AC CY 3 Note 3 Flag Operation rp, #word sfrp, AX 8-bit Clocks Bytes Note 4 When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 762 78K0/Kx2 Instruction Group 8-bit CHAPTER 29 INSTRUCTION SET Mnemonic SUB operation Operands A, #byte saddr, #byte A, r Note 3 r, A SUBC Z AC CY Note 1 Note 2 2 4 - A, CY A - byte x x x 3 6 8 (saddr), CY (saddr) - byte x x x 2 4 - A, CY A - r x x x 2 4 - r, CY r - A x x x 2 4 5 A, CY A - (saddr) x x x A, !addr16 3 8 9 A, CY A - (addr16) x x x A, [HL] 1 4 5 A, CY A - (HL) x x x A, [HL + byte] 2 8 9 A, CY A - (HL + byte) x x x A, [HL + B] 2 8 9 A, CY A - (HL + B) x x x A, [HL + C] 2 8 9 A, CY A - (HL + C) x x x A, #byte 2 4 - A, CY A - byte - CY x x x 3 6 8 (saddr), CY (saddr) - byte - CY x x x 2 4 - A, CY A - r - CY x x x r, A 2 4 - r, CY r - A - CY x x x A, saddr 2 4 5 A, CY A - (saddr) - CY x x x A, r Note 3 A, !addr16 3 8 9 A, CY A - (addr16) - CY x x x A, [HL] 1 4 5 A, CY A - (HL) - CY x x x A, [HL + byte] 2 8 9 A, CY A - (HL + byte) - CY x x x A, [HL + B] 2 8 9 A, CY A - (HL + B) - CY x x x A, [HL + C] 2 8 9 A, CY A - (HL + C) - CY x x x A, #byte 2 4 - A A byte x saddr, #byte 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x r, A 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x A, r Notes 1. Flag Operation A, saddr saddr, #byte AND Clocks Bytes Note 3 A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 763 78K0/Kx2 Instruction Group 8-bit CHAPTER 29 INSTRUCTION SET Mnemonic OR Operands A, #byte operation saddr, #byte A, r Note 3 r, A XOR Z AC CY Note 1 Note 2 2 4 - A A byte 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x 2 4 - rrA x x 2 4 5 A A (saddr) x A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x A, #byte 2 4 - A A byte x 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x r, A 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x A, r Note 3 A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x A, #byte 2 4 - A - byte x x x saddr, #byte 3 6 8 (saddr) - byte x x x 2 4 - A-r x x x r, A 2 4 - r-A x x x A, saddr 2 4 5 A - (saddr) x x x A, r Notes 1. Flag Operation A, saddr saddr, #byte CMP Clocks Bytes Note 3 A, !addr16 3 8 9 A - (addr16) x x x A, [HL] 1 4 5 A - (HL) x x x A, [HL + byte] 2 8 9 A - (HL + byte) x x x A, [HL + B] 2 8 9 A - (HL + B) x x x A, [HL + C] 2 8 9 A - (HL + C) x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 764 78K0/Kx2 Instruction Group CHAPTER 29 INSTRUCTION SET Mnemonic Operands Clocks Bytes Flag Operation Z AC CY Note 1 Note 2 16-bit ADDW AX, #word 3 6 - AX, CY AX + word x x x operation SUBW AX, #word 3 6 - AX, CY AX - word x x x CMPW AX, #word 3 6 - AX - word x x x MULU X 2 16 - AX A x X divide DIVUW C 2 25 - AX (Quotient), C (Remainder) AX / C Increment/ INC r 1 2 - rr+1 x x saddr 2 4 6 (saddr) (saddr) + 1 x x Multiply/ decrement r 1 2 - rr-1 x x saddr 2 4 6 (saddr) (saddr) - 1 x x INCW rp 1 4 - rp rp + 1 DECW rp 1 4 - rp rp - 1 ROR A, 1 1 2 - (CY, A7 A0, Am - 1 Am) x 1 time ROL A, 1 1 2 - (CY, A0 A7, Am + 1 Am) x 1 time x RORC A, 1 1 2 - (CY A0, A7 CY, Am - 1 Am) x 1 time x ROLC A, 1 1 2 - (CY A7, A0 CY, Am + 1 Am) x 1 time x ROR4 [HL] 2 10 12 DEC Rotate x A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 ROL4 [HL] 2 10 12 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 BCD ADJBA 2 4 - Decimal Adjust Accumulator after Addition x x x adjustment ADJBS 2 4 - Decimal Adjust Accumulator after Subtract x x x Bit MOV1 3 6 7 CY (saddr.bit) x manipulate Notes 1. 2. CY, saddr.bit CY, sfr.bit 3 - 7 CY sfr.bit x CY, A.bit 2 4 - CY A.bit x CY, PSW.bit 3 - 7 CY PSW.bit x x CY, [HL].bit 2 6 7 CY (HL).bit saddr.bit, CY 3 6 8 (saddr.bit) CY sfr.bit, CY 3 - 8 sfr.bit CY A.bit, CY 2 4 - A.bit CY PSW.bit, CY 3 - 8 PSW.bit CY [HL].bit, CY 2 6 8 (HL).bit CY x x When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 765 78K0/Kx2 Instruction Group Bit CHAPTER 29 INSTRUCTION SET Mnemonic AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Operands CY, saddr.bit Clocks Bytes 3 Flag Operation Z AC CY Note 1 Note 2 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW. bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 - 8 sfr.bit 1 A.bit 2 4 - A.bit 1 PSW.bit 2 - 6 PSW.bit 1 [HL].bit 2 6 8 (HL).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 - 8 sfr.bit 0 A.bit 2 4 - A.bit 0 x x x x x x PSW.bit 2 - 6 PSW.bit 0 [HL].bit 2 6 8 (HL).bit 0 SET1 CY 1 2 - CY 1 1 CLR1 CY 1 2 - CY 0 0 NOT1 CY 1 2 - CY CY x When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 766 78K0/Kx2 Instruction Group Call/return CHAPTER 29 INSTRUCTION SET Mnemonic CALL Operands !addr16 Clocks Bytes 3 Operation Note 1 Note 2 7 - Flag Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLF !addr11 2 5 - (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (addr5 + 1), PCL (addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET 1 6 - PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 6 - PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 RETB 1 6 - PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 Stack PUSH manipulate PSW 1 2 - (SP - 1) PSW, SP SP - 1 rp 1 4 - (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 POP PSW 1 2 - PSW (SP), SP SP + 1 rp 1 4 - rpH (SP + 1), rpL (SP), R R R SP SP + 2 SP, #word 4 - 10 SP word SP, AX 2 - 8 SP AX AX, SP 2 - 8 AX SP !addr16 3 6 - PC addr16 $addr16 2 6 - PC PC + 2 + jdisp8 AX 2 8 - PCH A, PCL X Conditional BC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 1 branch BNC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 0 MOVW Unconditional BR branch Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 767 78K0/Kx2 Instruction Group CHAPTER 29 INSTRUCTION SET Mnemonic Operands Note 2 8 9 PC PC + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 - 9 PC PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 0 branch BTCLR Z AC CY Note 1 saddr.bit, $addr16 Flag Operation 3 Conditional BT BF Clocks Bytes A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if PSW. bit = 0 [HL].bit, $addr16 3 10 11 PC PC + 3 + jdisp8 if (HL).bit = 0 saddr.bit, $addr16 4 10 12 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 - 12 PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 - 12 PC PC + 4 + jdisp8 if PSW.bit = 1 then reset A.bit x x x then reset PSW.bit [HL].bit, $addr16 3 10 12 PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit DBNZ B, $addr16 2 6 - C, $addr16 2 6 - B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 10 (saddr) (saddr) - 1, then RBn 2 4 - RBS1, 0 n PC PC + 3 + jdisp8 if (saddr) 0 CPU SEL control NOP 1 2 - No Operation EI 2 - 6 IE 1 (Enable Interrupt) DI 2 - 6 IE 0 (Disable Interrupt) HALT 2 6 - Set HALT Mode STOP 2 6 - Set STOP Mode Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 768 78K0/Kx2 CHAPTER 29 INSTRUCTION SET 29.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None [HL + B] First Operand A r [HL + C] ADD MOV MOV MOV MOV ADDC XCH XCH XCH XCH SUB ADD ADD ADD SUBC ADDC ADDC ADDC ADDC ADDC AND SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV SUB MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD RORC ROLC SUB MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV saddr MOV MOV ADD DBNZ INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note Except "r = A" R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 769 78K0/Kx2 CHAPTER 29 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None First Operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1 BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 770 78K0/Kx2 CHAPTER 29 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 771 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Target Products 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Conventional-specification Products Expanded-specification Products PD78F0500, 78F0501, 78F0502, 78F0503, PD78F0500A, 78F0501A, 78F0502A, 78F0503A, 78F0503D 78F0503DA PD78F0511, 78F0512, 78F0513, 78F0514, PD78F0511A, 78F0512A, 78F0513A, 78F0514A, 78F0515, 78F0513D, 78F0515D 78F0515A, 78F0513DA, 78F0515DA PD78F0521, 78F0522, 78F0523, 78F0524, PD78F0521A, 78F0522A, 78F0523A, 78F0524A, 78F0525, 78F0526, 78F0527, 78F0527D 78F0525A, 78F0526A, 78F0527A, 78F0527DA PD78F0531, 78F0532, 78F0533, 78F0534, PD78F0531A, 78F0532A, 78F0533A, 78F0534A, 78F0535, 78F0536, 78F0537, 78F0537D 78F0535A, 78F0536A, 78F0537A, 78F0537DA PD78F0544, 78F0545, 78F0546, 78F0547, PD78F0544A, 78F0545A, 78F0546A, 78F0547A, 78F0547D 78F0547DA The following items are described separately for conventional-specification products (PD78F05xx, 78F05xxD) and expanded-specification products (PD78F05xxA, 78F05xxDA). * X1 clock oscillation frequency (X1 oscillator characteristics) * Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width ( (1) Basic operation AC characteristics) * A/D conversion time (A/D Converter Characteristics) * Number of rewrites per chip (Flash Memory Programming Characteristics) in Cautions 1. The PD78F05xxD and 78F05xxDA have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product as follows. (1) Port functions Port 78K0/KB2 78K0/KC2 30/36 Pins Port 0 P00, P01 Port 1 P10 to P17 Port 2 P20 to P23 Port 3 P30 to P33 38 Pins P20 to P25 - Port 4 48 Pins 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins P00 to P03 P00 to P06 P20 to P27 P40, P41 - Port 5 Port 6 44 Pins 78K0/KD2 P60, P61 Port 7 - Port 12 P120 to P122 P40 to P43 P40 to P47 P50 to P53 P50 to P57 P60 to P63 P70, P71 P60 to P67 P70 to P73 P70 to P75 P70 to P77 P120 to P124 Port 13 - P130 Port 14 - P140 P140, P141 P140 to P145 (The remaining table is on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 772 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) (2) Non-port functions Port 78K0/KB2 78K0/KC2 30/36 Pins 38 Pins 44 Pins 48 Pins 78K0/KD2 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins Note 1 , VDD, AVREF, VSS, AVSS VDD, EVDD, VSS, EVSS, AVREF, Note 1 , AVSS Power supply, VDD, EVDD ground VSS, EVSS AVREF, AVSS Regulator REGC Reset RESET Clock X1, X2, oscillation EXCLK Writing to FLMD0 X1, X2, XT1, XT2, EXCLK, EXCLKS flash memory Interrupt INTP0 to INTP5 - Key interrupt TM00 INTP0 to INTP6 KR0, KR1 KR0 to KR3 Timer KR0 to KR7 TI000, TI010, TO00 TM01 Serial interface INTP0 to INTP7 TM50 TI50, TO50 TM51 TI51, TO51 TMH0 TOH0 TMH1 TOH1 UART0 RxD0, TxD0 UART6 RxD6, TxD6 IIC0 SCL0, SDA0 CSI10 SCK10, SI10, SO10 - TI001 - SCK11 Note 2 , TI011 Note 2 Note 2 , TO01 SCL0, SDA0, EXSCL0 CSI11 SO11 Note 2 , SI11 Note 2 , SSI11 - CSIA0 Note 2 , Note 2 SCKA0, SIA0, SOA0, BUSY0, STB0 A/D converter ANI0 to ANI3 ANI0 to ANI5 - Clock output PCL - Buzzer output Low-voltage ANI0 to ANI7 BUZ EXLVI detector (LVI) On-chip debug OCD0A, OCD1A, OCD0B, OCD1B (mounted only onto PD78F05xxD and 78F05xxDA (products with on-chip function debug function)) Notes 1. This is not mounted onto 30-pin products. 2. This is not mounted onto the 78K0/KE2 products whose flash memory is less than 32 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 773 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 -0.5 to VDD + 0.3 AVREF REGC pin input voltage Input voltage V Note AVSS -0.5 to +0.3 VIREGC -0.5 to +3.6 and -0.5 to VDD VI1 P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V V Note V V to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET, FLMD0 VI2 Output voltage Analog input voltage P60 to P63 (N-ch open drain) -0.3 to +6.5 V VO -0.3 to VDD + 0.3 VAN -0.3 to AVREF + 0.3 ANI0 to ANI7 Note Note V V and -0.3 to VDD + 0.3 Note Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 774 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbol Ratings Unit -10 mA -25 mA -55 mA -0.5 mA -2 mA -1 mA -4 mA 30 mA 60 mA 140 mA 1 mA 5 mA 4 mA 10 mA TA -40 to +85 C Tstg -65 to +150 C IOH Conditions Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Output current, low IOL Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Operating ambient temperature Storage temperature Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. The value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 775 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. X1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Parameter Conditions Ceramic X1 clock Conventional- resonator, oscillation specification Note 1 Crystal resonator frequency (fX) VSS X1 X2 Products (PD78F05xx, MIN. 4.0 V VDD 5.5 V 1.0 Note 2 2.7 V VDD < 4.0 V 1.0 Note 2 TYP. MAX. Unit 20.0 MHz 10.0 78F05xxD) 1.8 V VDD < 2.7 V C1 C2 Expanded- 2.7 V VDD 5.5 V specification 1.8 V VDD < 2.7 V 1.0 1.0 Note 2 1.0 5.0 20.0 5.0 Products (PD78F05xxA, 78F05xxDA) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 776 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Internal Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Parameter 8 MHz internal oscillator Conditions Internal high-speed oscillation RSTS = 1 Note clock frequency (fRH) TYP. MAX. Unit 2.7 V VDD 5.5 V 7.6 8.0 8.4 MHz 1.8 V VDD < 2.7 V 7.6 8.0 10.4 MHz 2.48 5.6 9.86 MHz RSTS = 0 240 kHz internal oscillator MIN. Internal low-speed oscillation 2.7 V VDD 5.5 V 216 240 264 kHz clock frequency (fRL) 1.8 V VDD < 2.7 V 192 240 264 kHz Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM) XT1 Oscillator CharacteristicsNote 1 (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Conditions XT1 clock oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz Note 2 frequency (fXT) Rd C4 Parameter C3 Notes 1. The 78K0/KB2 is not provided with the XT1 oscillator. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 777 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Recommended Oscillator Constants (1/2) (1) X1 oscillation: Ceramic resonator (TA = -40 to +85C) (1/2) Manufacturer Part Number SMD/ Frequency Recommended Circuit Lead (MHz) Constants C1 (pF) C2 (pF) Oscillation Voltage Range MIN. (V) Murata Mfg. Co., CSTCC2M00G56-R0 SMD 2.00 Internal (47) Internal (47) Ltd. CSTLS4M00G56-B0 Lead 4.00 Internal (47) Internal (47) Internal (39) Internal (39) 4.194 Internal (47) Internal (47) Internal (39) Internal (39) Internal (47) Internal (47) Internal (39) Internal (39) Internal (47) Internal (47) 1.9 Internal (39) Internal (39) 1.8 6.00 Internal (47) Internal (47) 2.4 Internal (39) Internal (39) 1.8 8.00 Internal (47) Internal (47) 2.3 Internal (33) Internal (33) 1.9 Internal (47) Internal (47) 2.3 Internal (33) Internal (33) 1.9 Internal (47) Internal (47) 2.5 Internal (33) Internal (33) 2.3 Internal (33) Internal (33) 2.3 CSTCR4M00G55-R0 SMD CSTLS4M19G56-B0 Lead CSTCR4M19G55-R0 SMD CSTLS4M91G56-B0 Lead CSTCR4M91G55-R0 SMD CSTLS5M00G56-B0 Lead CSTCR5M00G55-R0 SMD CSTLS6M00G56-B0 Lead CSTCR6M00G55-R0 SMD CSTLS8M00G56-B0 Lead CSTCE8M00G55-R0 SMD CSTLS8M38G56-B0 Lead CSTCE8M38G55-R0 SMD CSTLS10M0G56-B0 Lead CSTCE10M0G55-R0 SMD CSTCE12M0G55-R0 SMD 4.915 5.00 8.388 10.0 12.0 1.8 CSTCE16M0V53-R0 SMD 16.0 Internal (15) Internal (15) 2.3 CSTCE20M0V53-R0 SMD 20.0 Internal (15) Internal (15) 2.6 Murata Mfg. Co., CSTLS6M00G53-B0 Lead 6.00 Internal (15) Internal (15) 1.8 Ltd. CSTLS8M00G53-B0 Lead 8.00 Internal (15) Internal (15) 1.8 CSTLS8M38G53-B0 Lead 8.388 Internal (15) Internal (15) 1.8 CSTLS10M0G53-B0 Lead 10.0 Internal (15) Internal (15) 1.8 CSTCE12M0G52-R0 SMD 12.0 Internal (10) Internal (10) 1.8 CSTCE16M0V51-R0 SMD 16.0 Internal (5) Internal (5) 1.8 CSTCE20M0V51-R0 SMD 20.0 Internal (5) Internal (5) 1.9 (low-capacitance MAX. (V) 5.5 5.5 products) Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/Kx2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 778 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Recommended Oscillator Constants (2/2) (1) X1 oscillation: Ceramic resonator (TA = -40 to +85C) (2/2) Manufacturer TDK Corporation Part Number SMD/ Frequency Recommended Circuit Lead (MHz) Constants CCR4.0MUC8 SMD FCR4.0MC5 Lead CCR8.0MXC8 SMD FCR8.0MC5 Lead 4.00 8.00 Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) Internal (27) Internal (27) Internal (30) Internal (30) Internal (18) Internal (30) Internal (20) Internal (20) MAX. (V) 1.8 5.5 Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/Kx2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. (2) XT1 oscillation: Crystal resonator (TA = -40 to +85C) Manufacturer Part SMD/ Frequency Load Number Lead (MHz) Capacitance Voltage Range CL (pF) Seiko VT-200 Lead Instruments Inc. 32.768 Oscillation Recommended Circuit Constants VDD = 3.3 V VDD = 5.0 V MIN. MAX. (V) (V) C3 C4 Rd C3 C4 Rd (pF) (pF) (k) (pF) (pF) (k) 6.0 4 3 100 6 5 100 12.5 15 15 100 18 15 100 1.8 5.5 Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KE2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 779 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (1/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 Conditions IOL1 -3.0 mA -2.5 mA 1.8 V VDD < 2.7 V -1.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V -20.0 mA 2.7 V VDD < 4.0 V -10.0 mA 1.8 V VDD < 2.7 V -5.0 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 4.0 V VDD 5.5 V -30.0 mA 2.7 V VDD < 4.0 V -19.0 mA 1.8 V VDD < 2.7 V -10.0 mA 4.0 V VDD 5.5 V -50.0 mA 2.7 V VDD < 4.0 V -29.0 mA 1.8 V VDD < 2.7 V -15.0 mA AVREF = VDD -0.1 mA -0.1 mA Per pin for P20 to P27 Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V 8.5 mA 2.7 V VDD < 4.0 V 5.0 mA 1.8 V VDD < 2.7 V 2.0 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 15.0 mA 2.7 V VDD < 4.0 V 5.0 mA 1.8 V VDD < 2.7 V 2.0 mA 4.0 V VDD 5.5 V 20.0 mA 2.7 V VDD < 4.0 V 15.0 mA 1.8 V VDD < 2.7 V 9.0 mA 4.0 V VDD 5.5 V 45.0 mA 2.7 V VDD < 4.0 V 35.0 mA 1.8 V VDD < 2.7 V 20.0 mA 4.0 V VDD 5.5 V 65.0 mA 2.7 V VDD < 4.0 V 50.0 mA 1.8 V VDD < 2.7 V 29.0 mA AVREF = VDD 0.4 mA 0.4 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 Note 3 Total of all the pins above IOL2 Unit 2.7 V VDD < 4.0 V Per pin for P121 to P124 Note 2 MAX. 4.0 V VDD 5.5 V Note 3 Output current, low TYP. Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all the pins above IOH2 MIN. Per pin for P20 to P27 Per pin for P121 to P124 Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where the duty factor is 50%, IOH = -20.0 mA Total output current of pins = (-20.0 x 0.7)/(50 x 0.01) = -28.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 780 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (2/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high (products whose flash memory is at least Note 1 48 KB) Conditions MIN. MAX. Unit VIH1 Symbol P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145, EXCLK, EXCLKS 0.7VDD VDD V VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD TYP. VIH4 P60 to P63 0.7VDD 6.0 V VIH1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P121 to P124, EXCLK, EXCLKS 0.7VDD VDD V VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V VIH4 P60 to P63 0.7VDD 6.0 V Input voltage, low (products whose flash memory is at least Note 1 48 KB) VIL1 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145, EXCLK, EXCLKS 0 0.3VDD V VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET 0 0.2VDD V VIL3 P20 to P27 0 0.3AVREF V Input voltage, low (products whose flash memory is less than Note 2 32 KB) VIL1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P60 to P63, P121 to P124, EXCLK, EXCLKS 0 0.3VDD V VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, RESET 0 0.2VDD V VIL3 P20 to P27 AVREF = VDD 0 0.3AVREF V VOH1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V, IOH1 = -3.0 mA VDD - 0.7 V 2.7 V VDD < 4.0 V, IOH1 = -2.5 mA VDD - 0.5 V 1.8 V VDD < 2.7 V, IOH1 = -1.0 mA VDD - 0.5 V P20 to P27 AVREF = VDD, IOH2 = -100 A VDD - 0.5 V P121 to P124 IOH2 = -100 A VDD - 0.5 V Input voltage, high (products whose flash memory is less than Note 2 32 KB) Output voltage, high VOH2 AVREF = VDD AVREF = VDD Notes 1. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB, and 78K0/KF2 2. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is less than 32 KB, 78K0/KB2, and 78K0/KC2 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 781 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 VOL2 VOL3 Input leakage current, ILIH1 Conditions MAX. Unit 4.0 V VDD 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 0.7 V 1.8 V VDD < 2.7 V, IOH1 = 2.0 mA 0.5 V 1.8 V VDD < 2.7 V, IOL1 = 0.5 mA 0.4 V P20 to P27 AVREF = VDD, IOL2 = 0.4 mA 0.4 V P121 to P124 IOL2 = 0.4 mA 0.4 V P60 to P63 4.0 V VDD 5.5 V, IOL1 = 15.0 mA 2.0 V 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 0.4 V 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 0.6 V 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 0.4 V 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA 0.4 V VI = VDD 1 A P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P00 to P06, P10 to P17, MIN. TYP. P30 to P33, P40 to P47, high P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIH2 P20 to P27 VI = AVREF = VDD 1 A ILIH3 P121 to 124 VI = VDD I/O port mode 1 A OSC mode 20 A -1 A (X1, X2, XT1, XT2) Input leakage current, low ILIL1 P00 to P06, P10 to P17, VI = VSS P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIL2 P20 to P27 VI = VSS, AVREF = VDD -1 A ILIL3 P121 to 124 VI = VSS I/O port mode -1 A OSC mode -20 A 100 k (X1, X2, XT1, XT2) Pull-up resistor RU VI = VSS 10 FLMD0 supply voltage VIL In normal operation mode 0 0.2VDD V VIH In self-programming mode 0.8VDD VDD V Remark 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 782 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 Conditions Operating IDD1 mode fXH = 20 MHz, VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 10 MHz, VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 2.0 V Notes 2, 3 MIN. TYP. MAX. Unit Square wave input 3.2 5.5 mA Resonator connection 4.5 6.9 mA Square wave input 1.6 2.8 mA Resonator connection 2.3 3.9 mA Square wave input 1.5 2.7 mA Resonator connection 2.2 3.2 mA Square wave input 0.9 1.6 mA Resonator connection 1.3 2.0 mA Square wave input 0.7 1.4 mA Resonator connection 1.0 1.6 mA 1.4 2.5 mA 6 25 A fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V IDD2 Note 5 HALT fXH = 20 MHz, mode VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 Square wave input Resonator connection 15 30 A Square wave input 0.8 2.6 mA Resonator connection 2.0 4.4 mA Square wave input 0.4 1.3 mA Resonator connection 1.0 2.4 mA Square wave input 0.2 0.65 mA Resonator connection 0.5 1.1 mA 0.4 1.2 mA fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V Note 6 IDD3 Note 5 Note 4 Note 4 Square wave input 3.0 22 A Resonator connection 12 25 A 1 20 A 1 10 A 0.86 1.9 mA 5 10 A 9 18 A STOP mode TA = -40 to +70 C A/D converter IADC Note 7 2.3 V AVREF VDD, ADCS = 1 Note 8 During 240 kHz internal low-speed oscillation clock operating current Watchdog timer IWDT operation operating current Note 9 LVI operating current Remarks 1. fXH: ILVI High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 783 78K0/Kx2 Notes 1. 2. CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the current flowing into the pull-up resistors and the output current of the port are not included. Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1 oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. 4. Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 5. Not including the operating current of the X1 oscillator, 8 MHz internal oscillator, and 240 kHz internal 6. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current 7. Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is the 8. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator). oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. flowing into the A/D converter, watchdog timer and LVI circuit. sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 9. Current flowing only to the LVI circuit. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 784 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Characteristics (1) Basic operation (1/2) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main Conventionalsystem specification clock (fXP) Products operation (PD78F05xx, MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 0.1 32 s 2.7 V VDD < 4.0 V 0.2 32 s 32 s 32 s 32 s 125 s 1.8 V V DD < 2.7 V 0.4 Note 1 78F05xxD) Expanded- 2.7 V VDD 5.5 V specification 1.8 V VDD < 2.7 V 0.4 0.1 Note 1 Products (PD78F05xxA, 78F05xxDA) Subsystem clock (fSUB) operation Peripheral hardware clock fPRS frequency Note 2 114 122 fPRS = fXH (XSEL = Conventional- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 10 MHz 1) Products 1.8 V VDD < 2.7 V 5 MHz Expanded- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 20 MHz Products Note 3 5 MHz (PD78F05xx, 78F05xxD) (PD78F05xxA, 1.8 V VDD < 2.7 V 78F05xxDA) fPRS = fRH (XSEL = 0) 2.7 V VDD 5.5 V 7.6 8.4 MHz 1.8 V VDD < 2.7 V 7.6 10.4 MHz Note 4 External main system clock frequency fEXCLK Conventional-specification Products (PD78F05xx, 78F05xxD) 4.0 V VDD 5.5 V 1.0 Note 5 20.0 MHz 2.7 V VDD < 4.0 V 1.0 Note 5 10.0 MHz 1.0 5.0 MHz 2.7 V VDD 5.5 V 1.0 Expanded-specification Products 1.8 V VDD < 2.7 V 1.0 (PD78F05xxA, 78F05xxDA) 20.0 MHz 5.0 MHz 1.8 V VDD < 2.7 V Note 5 External main system clock input high-level width, low-level width Notes 1. 2. 3. 4. 5. tEXCLKH, tEXCLKL 4.0 V VDD 5.5 V 24 ns 2.7 V VDD < 4.0 V 48 ns 1.8 V VDD < 2.7 V 96 ns 2.7 V VDD 5.5 V Expanded-specification Products 1.8 V VDD < 2.7 V (PD78F05xxA, 78F05xxDA) 24 ns 96 ns Conventional-specification Products (PD78F05xx, 78F05xxD) 0.38 s when operating with the 8 MHz internal oscillator. The 78K0/KB2 is not provided with a subsystem clock. Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fXH/2 (10 MHz) or less. The multiplier/divider, however, can operate on fXH (20 MHz). Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fRH/2 or less. 2.0 MHz (MIN.) when using UART6 during on-board programming. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 785 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (1) Basic operation (2/2) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) MIN. TYP. MAX. Unit External subsystem clock Note 1 frequency Parameter fEXCLKS 32 32.768 35 kHz External subsystem clock input high-level width, low-level Note 1 width tEXCLKSH, tEXCLKSL 12 s TI000, TI010, TI001, TI011 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 2/fsam + Note 2 0.1 s 2.7 V VDD < 4.0 V 2/fsam + Note 2 0.2 s 1.8 V VDD < 2.7 V 2/fsam + Note 2 0.5 s TI50, TI51 input frequency Symbol fTI5 Conditions 4.0 V VDD 5.5 V 10 MHz 2.7 V VDD < 4.0 V 10 MHz 5 MHz 1.8 V VDD < 2.7 V TI50, TI51 input high-level width, low-level width Interrupt input high-level width, low-level width tTIH5, tTIL5 tINTH, tINTL 4.0 V VDD 5.5 V 50 ns 2.7 V VDD < 4.0 V 50 ns 1.8 V VDD < 2.7 V 100 ns 1 s Key interrupt input low-level width tKR 250 ns RESET low-level width 10 s Notes 1. 2. tRSL The 78K0/KB2 is not provided with a subsystem clock. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 786 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation) <1> Conventional-specification Products (PD78F05xx, 78F05xxD) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 1.8 Supply voltage VDD [V] <2> Expanded-specification Products (PD78F05xxA, 78F05xxDA) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 787 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Timing Test Points VIH VIH Test points VIL VIL External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLK 1/fEXCLKS tEXCLKSL tEXCLKSH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLKS TI Timing tTIH0 tTIL0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 788 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 789 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Serial interface (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 625 kbps MAX. Unit 625 kbps (b) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) IIC0 Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz SCL0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 - 0.6 - s tHD: STA 4.0 - 0.6 - s Internal clock operation 4.7 - 1.3 - s EXSCL0 clock (6.4 MHz) 4.7 - 1.25 - s 4.0 - 0.6 - s 250 - 100 0 3.45 0 Hold time Note 1 Hold time when SCL0 = "L" tLOW operation Hold time when SCL0 = "H" tHIGH Data setup time (reception) tSU: DAT Note 2 Data hold time (transmission) tHD: DAT N fW = fXH/2 or fW = fEXSCL0 selected - 0.9 Note 4 Note 3 1.00 N fW = fRH/2 selected Note 3 ns s Note 5 0 3.45 0 1.05 s Setup time of stop condition tSU: STO 4.0 - 0.6 - s Bus free time tBUF 4.7 - 1.3 - s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. 3. fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers. 4. When fW 4.4 MHz is selected 5. When fW < 4.4 MHz is selected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 790 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 tKH1, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 160 ns 2.7 V VDD < 4.0 V 250 ns 1.8 V VDD < 2.7 V 500 ns 4.0 V VDD 5.5 V tKCY1/2 - ns Note 1 tKL1 15 2.7 V VDD < 4.0 V tKCY1/2 - ns Note 1 25 1.8 V VDD < 2.7 V tKCY1/2 - ns Note 1 50 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to tSIK1 4.0 V VDD 5.5 V ns 2.7 V VDD < 4.0 V 80 ns 1.8 V VDD < 2.7 V 170 ns 30 ns tKSI1 tKSO1 55 Note 2 C = 50 pF 40 ns MAX. Unit SO1n output Notes 1. 2. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns 80 ns 50 ns tKL2 SI1n setup time (to SCK1n) tSIK2 SI1n hold time (from SCK1n) tKSI2 Delay time from SCK1n to tKSO2 Note C = 50 pF SO1n output 4.0 V VDD 5.5 V 120 ns 2.7 V VDD < 4.0 V 120 ns 1.8 V VDD < 2.7 V 165 ns Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 791 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tKH3, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 1.8 V VDD < 2.7 V 1800 ns 4.0 V VDD 5.5 V tKCY3/2 - ns tKL3 50 2.7 V VDD < 4.0 V tKCY3/2 - ns 100 1.8 V VDD < 2.7 V tKCY3/2 - ns 200 SIA0 setup time (to SCKA0) tSIK3 2.7 V VDD 5.5 V 100 ns 1.8 V VDD < 2.7 V 200 ns 300 ns SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to tKSO3 SOA0 output Time from SCKA0 to STB0 Note C = 100 pF 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns 1.8 V VDD < 2.7 V 400 ns tKCY3/2 - tSBD ns 100 Strobe signal high-level width tSBW 4.0 V VDD 5.5 V tKCY3 - ns 30 2.7 V VDD < 4.0 V tKCY3 - ns 60 1.8 V VDD < 2.7 V tKCY3 - ns 120 Busy signal setup time (to tBYS busy signal detection timing) Busy signal hold time (from 2.7 V VDD 5.5 V 100 ns 1.8 V VDD < 2.7 V 200 ns 100 ns tBYH busy signal detection timing) Time from busy inactive to tSPS 4.0 V VDD 5.5 V SCKA0 2tKCY3 + ns 100 2.7 V VDD < 4.0 V 2tKCY3 + ns 150 1.8 V VDD < 2.7 V 2tKCY3 + ns 200 Note C is the load capacitance of the SCKA0 and SOA0 output lines. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 792 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width SIA0 setup time (to SCKA0) Symbol Conditions MIN. MAX. 600 ns 2.7 V VDD < 4.0 V 1200 ns 1.8 V VDD < 2.7 V 1800 ns tKH4, 4.0 V VDD 5.5 V 300 ns tKL4 2.7 V VDD < 4.0 V 600 ns 1.8 V VDD < 2.7 V 900 ns 100 ns 2/fW + ns tSIK4 100 tKSO4 Note 2 C = 100 pF 4.0 V VDD 5.5 V SOA0 output Note 1 2/fW + 100 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Notes 1. 2. tR4, tF4 ns Note 1 2/fW + 300 ns Note 1 2/fW + 200 SCKA0 rise/fall time Unit 4.0 V VDD 5.5 V tKCY4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to TYP. ns Note 1 1000 ns fW is the CSIA0 base clock selected by the CSIS0 register. C is the load capacitance of the SOA0 output line. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 793 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD: DAT tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT tHD: STA SDA0 tBUF Stop Start condition condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 794 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing (2/2) CSIA0: D2 SOA0 SIA0 D1 D2 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 CSIA0 (busy processing): SCKA0 7 8 9Note 10Note tBYS 10 + nNote tBYH 1 tSPS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 795 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. A/D Converter Characteristics (TA = -40 to +85C, 2.3 V AVREF VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Resolution Conditions MIN. RES Notes 1, 2 Overall error AINL tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 EFS Note 1 Integral non-linearity error Differential non-linearity error ILE Note 1 DLE Notes 1. 2. Unit 10 bit 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 1.2 %FSR Conventionalspecification Products (PD78F05xx, 78F05xxD) 4.0 V AVREF 5.5 V 6.1 36.7 s 2.7 V AVREF < 4.0 V 12.2 36.7 s 2.3 V AVREF < 2.7 V 27 66.6 s Expandedspecification Products (PD78F05xxA, 78F05xxDA) 4.0 V AVREF 5.5 V 6.1 66.6 s 2.7 V AVREF < 4.0 V 12.2 66.6 s 2.3 V AVREF < 2.7 V 27 66.6 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 2.3 V AVREF < 2.7 V 6.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB 2.0 LSB AVREF V 2.3 V AVREF < 2.7 V Analog input voltage MAX. 4.0 V AVREF 5.5 V 2.3 V AVREF < 2.7 V Conversion time TYP. VAIN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 796 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 1.59 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage VPOC Power supply voltage rise inclination tPTH Minimum pulse width tPW Conditions MIN. TYP. MAX. 1.44 1.59 1.74 VDD: 0 V change inclination of VPOC Unit V 0.5 V/ms 200 s 1.59 V POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time Supply Voltage Rise Time (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 1.8 V (VDD (MIN.)) Symbol tPUP1 (VDD: 0 V 1.8 V) Maximum time to rise to 1.8 V (VDD (MIN.)) (releasing RESET input VDD: 1.8 V) Conditions MIN. POCMODE (option byte) = 0, TYP. MAX. Unit 3.6 ms 1.9 ms when RESET input is not used tPUP2 POCMODE (option byte) = 0, when RESET input is used Supply Voltage Rise Time Timing * When RESET pin input is not used * When RESET pin input is used Supply voltage (VDD) Supply voltage (VDD) 1.8 V 1.8 V VPOC Time Time tPUP1 RESET pin tPUP2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 797 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. 2.7 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage on application of supply VDDPOC Conditions POCMODE (option bye) = 1 MIN. TYP. MAX. Unit 2.50 2.70 2.90 V voltage Remark The operations of the POC circuit are as described below, depending on the POCMODE (option byte) setting. Option Byte Setting POCMODE = 0 POC Mode 1.59 V mode operation Operation A reset state is retained until VPOC = 1.59 V (TYP.) is reached after the power is turned on, and the reset is released when VPOC is exceeded. After that, POC detection is performed at VPOC, similarly as when the power was turned on. The power supply voltage must be raised at a time of tPUP1 or tPUP2 when POCMODE is 0. POCMODE = 1 2.7 V/1.59 V mode operation A reset state is retained until VDDPOC = 2.7 V (TYP.) is reached after the power is turned on, and the reset is released when VDDPOC is exceeded. After that, POC detection is performed at VPOC = 1.59 V (TYP.) and not at VDDPOC. The use of the 2.7 V/1.59 V POC mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 V, is more relaxed than tPTH. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 798 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. LVI Circuit Characteristics (TA = -40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection Symbol Supply voltage level voltage Conditions MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.26 V VLVI8 2.91 3.01 3.11 V VLVI9 2.75 2.85 2.95 V VLVI10 2.60 2.70 2.80 V VLVI11 2.45 2.55 2.65 V VLVI12 2.29 2.39 2.49 V VLVI13 2.14 2.24 2.34 V VLVI14 1.98 2.08 2.18 V 1.83 1.93 2.03 V 1.11 1.21 1.31 V VLVI15 External input pin Note 1 Minimum pulse width Operation stabilization wait time Note 2 EXLVI EXLVI < VDD, 1.8 V VDD 5.5 V tLW 200 s tLWAIT 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 15 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Time 799 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Operation mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 800 78K0/Kx2 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter Symbol Conditions MIN. MAX. Unit 4.5 11.0 mA VDD supply current IDD Erase time All block Teraca 20 200 ms Block unit Terasa 20 200 ms 10 100 s Notes 1, 2 Write time (in 8-bit fXP = 10 MHz (TYP.), 20 MHz (MAX.) TYP. Twrwa Note 1 units) Number of rewrites per chip Cerwr 1 erase + Expanded- * When a flash memory Retention: 1000 programmer is used, 15 years 1 write specification after Products and the libraries erase = (PD78F05xxA, provided by Renesas 1 rewrite 78F05xxDA) Note 3 Times Note 4 Electronics are used * For program update * When the EEPROM Note 5 emulation libraries Retention: 10000 Times 5 years provided by Renesas Electronics are used * The rewritable ROM size: 4 KB * For data update Expanded- Conditions other than specification the above Note 6 Retention: 100 Times 10 years Products (PD78F05xxA, 78F05xxDA) Conventionalspecification Products (PD78F05xx, 78F05xxD) Notes 1. 2. 3. 4. 5. 6. Remarks Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or PGFP5, is used and the rewrite time during self programming, see Tables 27-12 to 27-14. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) is excluded. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) is excluded. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) are used. 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (Document No.: U17739E). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 801 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Target Products 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Conventional-specification Products Expanded-specification Products PD78F0500(A), 78F0501(A), 78F0502(A), PD78F0500A(A), 78F0501A(A), 78F0502A(A), 78F0503(A) 78F0503A(A) PD78F0511(A), 78F0512(A), 78F0513(A), PD78F0511A(A), 78F0512A(A), 78F0513A(A), 78F0514(A), 78F0515(A) 78F0514A(A), 78F0515A(A) PD78F0521(A), 78F0522(A), 78F0523(A), PD78F0521A(A), 78F0522A(A), 78F0523A(A), 78F0524(A), 78F0525(A), 78F0526(A), 78F0524A(A), 78F0525A(A), 78F0526A(A), 78F0527(A) 78F0527A(A) PD78F0531(A), 78F0532(A), 78F0533(A), PD78F0531A(A), 78F0532A(A), 78F0533A(A), 78F0534(A), 78F0535(A), 78F0536(A), 78F0534A(A), 78F0535A(A), 78F0536A(A), 78F0537(A) 78F0537A(A) PD78F0544(A), 78F0545(A), 78F0546(A), PD78F0544A(A), 78F0545A(A), 78F0546A(A), 78F0547(A) 78F0547A(A) The following items are described separately for conventional-specification products (PD78F05xx(A)) and expandedspecification products (PD78F05xxA(A)). * X1 clock oscillation frequency (X1 oscillator characteristics) * Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width ( (1) Basic operation AC characteristics) * A/D conversion time (A/D Converter Characteristics) * Number of rewrites per chip (Flash Memory Programming Characteristics) Caution in The pins mounted depend on the product as follows. (1) Port functions Port 78K0/KB2 78K0/KC2 30/36 Pins Port 0 P00, P01 Port 1 P10 to P17 Port 2 P20 to P23 Port 3 P30 to P33 38 Pins P20 to P25 - Port 4 48 Pins 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins P00 to P03 P00 to P06 P20 to P27 P40, P41 - Port 5 Port 6 44 Pins 78K0/KD2 P60, P61 Port 7 - Port 12 P120 to P122 P40 to P43 P40 to P47 P50 to P53 P50 to P57 P60 to P63 P70, P71 P60 to P67 P70 to P73 P70 to P75 P70 to P77 P120 to P124 Port 13 - P130 Port 14 - P140 P140, P141 P140 to P145 (The remaining table is on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 802 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (2) Non-port functions Port 78K0/KB2 78K0/KC2 30/36 Pins 38 Pins 44 Pins 48 Pins 78K0/KD2 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins Note 1 , VDD, AVREF, VSS, AVSS VDD, EVDD, VSS, EVSS, AVREF, Note 1 , AVSS Power supply, VDD, EVDD ground VSS, EVSS AVREF, AVSS Regulator REGC Reset RESET Clock X1, X2, oscillation EXCLK Writing to FLMD0 X1, X2, XT1, XT2, EXCLK, EXCLKS flash memory Interrupt INTP0 to INTP5 - Key interrupt TM00 INTP0 to INTP6 KR0, KR1 Timer KR0 to KR7 TI000, TI010, TO00 - TM01 Serial interface KR0 to KR3 INTP0 to INTP7 TM50 TI50, TO50 TM51 TI51, TO51 TMH0 TOH0 TMH1 TOH1 UART0 RxD0, TxD0 UART6 RxD6, TxD6 IIC0 SCL0, SDA0 CSI10 SCK10, SI10, SO10 Note 2 TI001 , TI011 Note 2 Note 2 , TO01 SCL0, SDA0, EXSCL0 - CSI11 Note 2 , SI11 SCK11 SO11 Note 2 , SSI11 - CSIA0 Note 2 , Note 2 SCKA0, SIA0, SOA0, BUSY0, STB0 A/D converter ANI0 to ANI3 ANI0 to ANI7 - Clock output PCL - Buzzer output Low-voltage ANI0 to ANI5 BUZ EXLVI detector (LVI) Notes 1. This is not mounted onto 30-pin products. 2. This is not mounted onto the 78K0/KE2 products whose flash memory is less than 32 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 803 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 -0.5 to VDD + 0.3 AVREF REGC pin input voltage Input voltage V Note AVSS -0.5 to +0.3 VIREGC -0.5 to +3.6 and -0.5 to VDD VI1 P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V V Note V V to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET, FLMD0 VI2 Output voltage Analog input voltage P60 to P63 (N-ch open drain) -0.3 to +6.5 V VO -0.3 to VDD + 0.3 VAN -0.3 to AVREF + 0.3 ANI0 to ANI7 Note Note V V and -0.3 to VDD + 0.3 Note Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 804 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbol Ratings Unit -10 mA -25 mA -55 mA -0.5 mA -2 mA -1 mA -4 mA 30 mA 60 mA 140 mA 1 mA 5 mA 4 mA 10 mA TA -40 to +85 C Tstg -65 to +150 C IOH Conditions Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Output current, low IOL Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Operating ambient temperature Storage temperature Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. The value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 805 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. X1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Parameter Conditions Ceramic X1 clock Conventional- 4.0 V VDD 5.5 V resonator, oscillation specification 2.7 V VDD < 4.0 V Crystal Note 1 VSS X1 X2 frequency (fX) resonator Products (PD78F05xx 1.8 V VDD < 2.7 V MIN. MAX. Unit 1.0 Note 2 20.0 MHz 1.0 Note 2 10.0 1.0 TYP. 5.0 (A)) C1 C2 Expanded- 2.7 V VDD 5.5 V specification 1.8 V VDD < 2.7 V 1.0 Note 2 1.0 20.0 MHz 5.0 Products (PD78F05xxA (A)) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 806 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Internal Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Parameter 8 MHz internal oscillator Conditions Internal high-speed oscillation RSTS = 1 Note clock frequency (fRH) TYP. MAX. Unit 2.7 V VDD 5.5 V 7.6 8.0 8.4 MHz 1.8 V VDD < 2.7 V 7.6 8.0 10.4 MHz 2.48 5.6 9.86 MHz RSTS = 0 240 kHz internal oscillator MIN. Internal low-speed oscillation 2.7 V VDD 5.5 V 216 240 264 kHz clock frequency (fRL) 1.8 V VDD < 2.7 V 192 240 264 kHz Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM) XT1 Oscillator CharacteristicsNote 1 (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Conditions XT1 clock oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz Note 2 frequency (fXT) Rd C4 Parameter C3 Notes 1. The 78K0/KB2 is not provided with the XT1 oscillator. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 807 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (1/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 Conditions IOL1 -3.0 mA -2.5 mA 1.8 V VDD < 2.7 V -1.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V -12.0 mA 2.7 V VDD < 4.0 V -7.0 mA 1.8 V VDD < 2.7 V -5.0 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 4.0 V VDD 5.5 V -18.0 mA 2.7 V VDD < 4.0 V -15.0 mA 1.8 V VDD < 2.7 V -10.0 mA 4.0 V VDD 5.5 V -23.0 mA 2.7 V VDD < 4.0 V -20.0 mA 1.8 V VDD < 2.7 V -15.0 mA AVREF = VDD -0.1 mA -0.1 mA Per pin for P20 to P27 Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V 8.5 mA 2.7 V VDD < 4.0 V 5.0 mA 1.8 V VDD < 2.7 V 2.0 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 15.0 mA 2.7 V VDD < 4.0 V 5.0 mA 1.8 V VDD < 2.7 V 2.0 mA 4.0 V VDD 5.5 V 20.0 mA 2.7 V VDD < 4.0 V 15.0 mA 1.8 V VDD < 2.7 V 9.0 mA 4.0 V VDD 5.5 V 45.0 mA 2.7 V VDD < 4.0 V 35.0 mA 1.8 V VDD < 2.7 V 20.0 mA 4.0 V VDD 5.5 V 65.0 mA 2.7 V VDD < 4.0 V 50.0 mA 1.8 V VDD < 2.7 V 29.0 mA AVREF = VDD 0.4 mA 0.4 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 Note 3 Total of all the pins above IOL2 Unit 2.7 V VDD < 4.0 V Per pin for P121 to P124 Note 2 MAX. 4.0 V VDD 5.5 V Note 3 Output current, low TYP. Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all the pins above IOH2 MIN. Per pin for P20 to P27 Per pin for P121 to P124 Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where the duty factor is 50%, IOH = -20.0 mA Total output current of pins = (-20.0 x 0.7)/(50 x 0.01) = -28.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 808 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (2/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high (products whose flash memory is at least Note 1 48 KB) Input voltage, high (products whose flash memory is less than Note 2 32 KB) Conditions MIN. MAX. Unit VIH1 Symbol P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145 0.7VDD VDD V VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD TYP. VIH4 P60 to P63 0.7VDD 6.0 V VIH1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P121 to P124 0.7VDD VDD V VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD VIH4 P60 to P63 0.7VDD 6.0 V VIL1 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145 0 0.3VDD V VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 0 0.3AVREF V Input voltage, low (products whose flash memory is less than Note 2 32 KB) VIL1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P60 to P63, P121 to P124 0 0.3VDD V VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 AVREF = VDD 0 0.3AVREF V Output voltage, high VOH1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V, IOH1 = -3.0 mA VDD - 0.7 V 2.7 V VDD < 4.0 V, IOH1 = -2.5 mA VDD - 0.5 V 1.8 V VDD < 2.7 V, IOH1 = -1.0 mA VDD - 0.5 V P20 to P27 AVREF = VDD, IOH2 = -100 A VDD - 0.5 V P121 to P124 IOH2 = -100 A VDD - 0.5 V Input voltage, low (products whose flash memory is at least Note 1 48 KB) VOH2 AVREF = VDD Notes 1. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB, and 78K0/KF2 2. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is less than 32 KB, 78K0/KB2, and 78K0/KC2 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 809 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (3/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 VOL2 VOL3 Input leakage current, ILIH1 Conditions MAX. Unit 4.0 V VDD 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 0.7 V 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA 0.5 V 1.8 V VDD < 2.7 V, IOL1 = 0.5 mA 0.4 V P20 to P27 AVREF = VDD, IOL2 = 0.4 mA 0.4 V P121 to P124 IOL2 = 0.4 mA 0.4 V P60 to P63 4.0 V VDD 5.5 V, IOL1 = 15.0 mA 2.0 V 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 0.4 V 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 0.6 V 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 0.4 V 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA 0.4 V VI = VDD 1 A VI = AVREF = VDD 1 A P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P00 to P06, P10 to P17, MIN. TYP. P30 to P33, P40 to P47, high P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIH2 P20 to P27 ILIH3 P121 to 124 VI = I/O port mode 1 A (X1, X2, XT1, XT2) VDD OSC mode 20 A P00 to P06, P10 to P17, VI = VSS -1 A Input leakage current, low ILIL1 P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIL2 P20 to P27 VI = VSS, AVREF = VDD -1 A ILIL3 P121 to 124 VI = I/O port mode -1 A (X1, X2, XT1, XT2) VSS OSC mode -20 A 100 k Pull-up resistor RU VI = VSS 10 FLMD0 supply voltage VIL In normal operation mode 0 0.2VDD V VIH In self-programming mode 0.8VDD VDD V Remark 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 810 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (4/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 Conditions Operating IDD1 mode fXH = 20 MHz, VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 10 MHz VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 2.0 V Notes 2, 3 MIN. TYP. MAX. Unit Square wave input 3.2 5.5 mA Resonator connection 4.5 6.9 mA Square wave input 1.6 2.8 mA Resonator connection 2.3 3.9 mA Square wave input 1.5 2.7 mA Resonator connection 2.2 3.2 mA Square wave input 0.9 1.6 mA Resonator connection 1.3 2.0 mA Square wave input 0.7 1.4 mA Resonator connection 1.0 1.6 mA 1.4 2.5 mA 6 30 A fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V IDD2 Note 5 HALT fXH = 20 MHz, mode VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 Square wave input Resonator connection 15 35 A Square wave input 0.8 2.6 mA Resonator connection 2.0 4.4 mA Square wave input 0.4 1.3 mA Resonator connection 1.0 2.4 mA Square wave input 0.2 0.65 mA Resonator connection 0.5 1.1 mA 0.4 1.2 mA fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V Note 6 IDD3 Note 5 Note 4 Note 4 Square wave input 3.0 27 A Resonator connection 12 32 A 1 20 A 1 10 A 0.86 1.9 mA 5 10 A 9 18 A STOP mode TA = -40 to +70 C A/D converter IADC Note 7 2.3 V AVREF VDD, ADCS = 1 Note 8 During 240 kHz internal low-speed oscillation clock operating current Watchdog timer IWDT operation operating current Note 9 LVI operating current Remarks 1. fXH: ILVI High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 811 78K0/Kx2 Notes 1. 2. CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the current flowing into the pull-up resistors and the output current of the port are not included. Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1 oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. 4. Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and the 5. Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal 6. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current 7. Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is the 8. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator). current flowing into the A/D converter, watchdog timer and LVI circuit. oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. flowing into the A/D converter, watchdog timer and LVI circuit. sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 9. Current flowing only to the LVI circuit. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 812 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Characteristics (1) Basic operation (1/2) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main Conventionalsystem specification clock (fXP) Products operation (PD78F05xx MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 0.1 32 s 2.7 V VDD < 4.0 V 0.2 32 s 32 s 32 s 32 s 125 s 1.8 V V DD < 2.7 V 0.4 Note 1 (A)) Expanded- 2.7 V VDD 5.5 V specification 1.8 V VDD < 2.7 V 0.4 0.1 Note 1 Products (PD78F05xxA (A)) Subsystem clock (fSUB) operation Peripheral hardware clock fPRS frequency Note 2 114 122 fPRS = fXH (XSEL = Conventional- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 10 MHz 1) Products 1.8 V VDD < 2.7 V 5 MHz Expanded- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 20 MHz Products Note 3 5 MHz (PD78F05xx (A)) (PD78F05xxA 1.8 V VDD < 2.7 V (A)) fPRS = fRH (XSEL = 0) 2.7 V VDD 5.5 V 7.6 8.4 MHz 1.8 V VDD < 2.7 V 7.6 10.4 MHz Note 4 External main system clock frequency fEXCLK Conventional-specification 4.0 V VDD 5.5 V 1.0 Note 5 20.0 MHz Products 2.7 V VDD < 4.0 V 1.0 Note 5 10.0 MHz (PD78F05xx(A)) 1.8 V VDD < 2.7 V 5.0 MHz Expanded-specification 2.7 V VDD 5.5 V 1.0 20.0 MHz Products 1.8 V VDD < 2.7 V 1.0 5.0 MHz Conventional-specification 4.0 V VDD 5.5 V 24 ns Products 2.7 V VDD < 4.0 V 48 ns (PD78F05xx(A)) 1.8 V VDD < 2.7 V 96 ns Expanded-specification 2.7 V VDD 5.5 V 24 ns Products 1.8 V VDD < 2.7 V 96 ns 1.0 Note 5 (PD78F05xxA(A)) External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL (PD78F05xxA(A)) Notes 1. 2. 3. 4. 5. 0.38 s when operating with the 8 MHz internal oscillator. The 78K0/KB2 is not provided with a subsystem clock. Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fXH/2 (10 MHz) or less. The multiplier/divider, however, can operate on fXH (20 MHz). Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fRH/2 or less. 2.0 MHz (MIN.) when using UART6 during on-board programming. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 813 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (1) Basic operation (2/2) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) MIN. TYP. MAX. Unit External subsystem clock Note 1 frequency Parameter fEXCLKS 32 32.768 35 kHz External subsystem clock input high-level width, low-level Note 1 width tEXCLKSH, tEXCLKSL 12 s TI000, TI010, TI001, TI011 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 2/fsam + Note 2 0.1 s 2.7 V VDD < 4.0 V 2/fsam + Note 2 0.2 s 1.8 V VDD < 2.7 V 2/fsam + Note 2 0.5 s TI50, TI51 input frequency Symbol fTI5 Conditions 4.0 V VDD 5.5 V 10 MHz 2.7 V VDD < 4.0 V 10 MHz 5 MHz 1.8 V VDD < 2.7 V TI50, TI51 input high-level width, low-level width Interrupt input high-level width, low-level width tTIH5, tTIL5 tINTH, tINTL 4.0 V VDD 5.5 V 50 ns 2.7 V VDD < 4.0 V 50 ns 1.8 V VDD < 2.7 V 100 ns 1 s Key interrupt input low-level width tKR 250 ns RESET low-level width 10 s Notes 1. 2. tRSL The 78K0/KB2 is not provided with a subsystem clock. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 814 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation) <1> Conventional-specification Products (PD78F05xx(A)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 1.8 Supply voltage VDD [V] <2> Expanded-specification Products (PD78F05xxA(A)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 815 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Timing Test Points VIH VIH Test points VIL VIL External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.) 1/fEXCLKS tEXCLKSL EXCLKS R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 tEXCLKSH 0.8VDD (MIN.) 0.2VDD (MAX.) 816 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TI Timing tTIH0 tTIL0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 817 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (2) Serial interface (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 625 kbps MAX. Unit 625 kbps (b) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) IIC0 Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz SCL0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 - 0.6 - s tHD: STA 4.0 - 0.6 - s Internal clock operation 4.7 - 1.3 - s EXSCL0 clock (6.4 MHz) 4.7 - 1.25 - s 4.0 - 0.6 - s 250 - 100 0 3.45 0 Hold time Note 1 Hold time when SCL0 = "L" tLOW operation Hold time when SCL0 = "H" tHIGH Data setup time (reception) tSU: DAT Note 2 Data hold time (transmission) tHD: DAT N fW = fXH/2 or fW = fEXSCL0 selected - 0.9 Note 4 Note 3 1.00 N fW = fRH/2 selected Note 3 ns s Note 5 0 3.45 0 1.05 s Setup time of stop condition tSU: STO 4.0 - 0.6 - s Bus free time tBUF 4.7 - 1.3 - s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. 3. fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers. 4. When fW 4.4 MHz is selected 5. When fW < 4.4 MHz is selected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 818 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 tKH1, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 400 ns 1.8 V VDD < 2.7 V 600 ns 4.0 V VDD 5.5 V tKCY1/2 - ns Note 1 tKL1 20 2.7 V VDD < 4.0 V tKCY1/2 - ns Note 1 30 1.8 V VDD < 2.7 V tKCY1/2 - ns Note 1 60 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to tSIK1 4.0 V VDD 5.5 V 70 ns 2.7 V VDD < 4.0 V 100 ns 1.8 V VDD < 2.7 V 190 ns 30 ns tKSI1 tKSO1 Note 2 C = 50 pF 40 ns MAX. Unit SO1n output Notes 1. 2. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns tKL2 SI1n setup time (to SCK1n) tSIK2 80 ns SI1n hold time (from SCK1n) tKSI2 50 ns Delay time from SCK1n to tKSO2 SO1n output C = 50 Note pF 4.0 V VDD 5.5 V 120 ns 2.7 V VDD < 4.0 V 120 ns 1.8 V VDD < 2.7 V 180 ns Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 819 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tKH3, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 1.8 V VDD < 2.7 V 1800 ns 4.0 V VDD 5.5 V tKCY3/2 - ns tKL3 50 2.7 V VDD < 4.0 V tKCY3/2 - ns 100 1.8 V VDD < 2.7 V tKCY3/2 - ns 200 SIA0 setup time (to SCKA0) tSIK3 2.7 V VDD 5.5 V 100 ns 1.8 V VDD < 2.7 V 200 ns SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to tKSO3 SOA0 output Time from SCKA0 to STB0 300 Note C = 100 pF ns 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns 1.8 V VDD < 2.7 V 400 ns tKCY3/2 - tSBD ns 100 Strobe signal high-level width tSBW 4.0 V VDD 5.5 V tKCY3 - ns 30 2.7 V VDD < 4.0 V tKCY3 - ns 60 1.8 V VDD < 2.7 V tKCY3 - ns 120 Busy signal setup time (to tBYS busy signal detection timing) Busy signal hold time (from 2.7 V VDD 5.5 V 100 ns 1.8 V VDD < 2.7 V 200 ns 100 ns tBYH busy signal detection timing) Time from busy inactive to tSPS 4.0 V VDD 5.5 V SCKA0 2tKCY3 + ns 100 2.7 V VDD < 4.0 V 2tKCY3 - ns 150 1.8 V VDD < 2.7 V 2tKCY3 - ns 200 Note C is the load capacitance of the SCKA0 and SOA0 output lines. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 820 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width SIA0 setup time (to SCKA0) Symbol Conditions MIN. MAX. 600 ns 2.7 V VDD < 4.0 V 1200 ns 1.8 V VDD < 2.7 V 1800 ns tKH4, 4.0 V VDD 5.5 V 300 ns tKL4 2.7 V VDD < 4.0 V 600 ns 1.8 V VDD < 2.7 V 900 ns 100 ns 2/fW + ns tSIK4 100 tKSO4 Note 2 C = 100 pF 4.0 V VDD 5.5 V SOA0 output Note 1 2/fW + 100 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Notes 1. 2. tR4, tF4 ns Note 1 2/fW + 300 ns Note 1 2/fW + 200 SCKA0 rise/fall time Unit 4.0 V VDD 5.5 V tKCY4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to TYP. ns Note 1 1000 ns fW is the CSIA0 base clock selected by the CSIS0 register. C is the load capacitance of the SOA0 output line. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 821 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD:DAT tHIGH tHD:STA tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop Start condition condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 822 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (2/2) CSIA0: D2 SOA0 SIA0 D1 D2 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 CSIA0 (busy processing): SCKA0 7 8 9Note 10Note tBYS 10 + nNote tBYH 1 tSPS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 823 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. A/D Converter Characteristics (TA = -40 to +85C, 2.3 V AVREF VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Resolution Conditions MIN. RES Notes 1, 2 Overall error AINL tCONV Notes 1, 2 Full-scale error EZS Notes 1, 2 EFS Note 1 Integral non-linearity error Differential non-linearity error ILE Note 1 Analog input voltage Notes 1. 2. DLE Unit 10 bit 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR Conventionalspecification Products (PD78F05xx(A)) 1.2 %FSR 4.0 V AVREF 5.5 V 6.1 36.7 s 2.7 V AVREF < 4.0 V 12.2 36.7 s 2.3 V AVREF < 2.7 V 27 66.6 s 4.0 V AVREF 5.5 V Expandedspecification 2.7 V AVREF < 4.0 V Products 2.3 V AVREF < 2.7 V (PD78F05xxA(A)) Zero-scale error MAX. 4.0 V AVREF 5.5 V 2.3 V AVREF < 2.7 V Conversion time TYP. 6.1 66.6 s 12.2 66.6 s 27 66.6 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 2.3 V AVREF < 2.7 V 6.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB 2.3 V AVREF < 2.7 V 2.0 LSB AVREF V VAIN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 824 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. 1.59 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage VPOC Power supply voltage rise inclination tPTH Minimum pulse width tPW Conditions MIN. TYP. MAX. 1.44 1.59 1.74 VDD: 0 V change inclination of VPOC Unit V 0.5 V/ms 200 s 1.59 V POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 825 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Supply Voltage Rise Time (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Maximum time to rise to 1.8 V (VDD (MIN.)) tPUP1 (VDD: 0 V 1.8 V) Conditions MIN. TYP. POCMODE (option byte) = 0, MAX. Unit 3.6 ms 1.9 ms when RESET input is not used Maximum time to rise to 1.8 V (VDD (MIN.)) tPUP2 (releasing RESET input VDD: 1.8 V) POCMODE (option byte) = 0, when RESET input is used Supply Voltage Rise Time Timing * When RESET pin input is not used * When RESET pin input is used Supply voltage (VDD) Supply voltage (VDD) 1.8 V 1.8 V VPOC Time Time tPUP1 RESET pin tPUP2 2.7 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage on application of supply VDDPOC Conditions POCMODE (option bye) = 1 MIN. TYP. MAX. Unit 2.50 2.70 2.90 V voltage Remark The operations of the POC circuit are as described below, depending on the POCMODE (option byte) setting. Option Byte Setting POCMODE = 0 POC Mode 1.59 V mode operation Operation A reset state is retained until VPOC = 1.59 V (TYP.) is reached after the power is turned on, and the reset is released when VPOC is exceeded. After that, POC detection is performed at VPOC, similarly as when the power was turned on. The power supply voltage must be raised at a time of tPUP1 or tPUP2 when POCMODE is 0. POCMODE = 1 2.7 V/1.59 V mode operation A reset state is retained until VDDPOC = 2.7 V (TYP.) is reached after the power is turned on, and the reset is released when VDDPOC is exceeded. After that, POC detection is performed at VPOC = 1.59 V (TYP.) and not at VDDPOC. The use of the 2.7 V/1.59 V POC mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 V, is more relaxed than tPTH. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 826 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. LVI Circuit Characteristics (TA = -40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection Symbol Supply voltage level voltage Conditions MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.26 V VLVI8 2.91 3.01 3.11 V VLVI9 2.75 2.85 2.95 V VLVI10 2.60 2.70 2.80 V VLVI11 2.45 2.55 2.65 V VLVI12 2.29 2.39 2.49 V VLVI13 2.14 2.24 2.34 V VLVI14 1.98 2.08 2.18 V 1.83 1.93 2.03 V 1.11 1.21 1.31 V VLVI15 External input pin Note 1 Minimum pulse width Operation stabilization wait time Note 2 EXLVI EXLVI < VDD, 1.8 V VDD 5.5 V tLW 200 s tLWAIT 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 15 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Time 827 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Operation mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 828 78K0/Kx2 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter Symbol Conditions MIN. MAX. Unit 4.5 11.0 mA VDD supply current IDD Erase time All block Teraca 20 200 ms Block unit Terasa 20 200 ms 10 100 s Notes 1, 2 Write time (in 8-bit fXP = 10 MHz (TYP.), 20 MHz (MAX.) TYP. Twrwa Note 1 units) Number of rewrites per chip Cerwr 1 erase + Expanded- * When a flash memory Retention: 1000 programmer is used, 15 years 1 write specification after Products and the libraries erase = (PD78F05xxA provided by Renesas 1 rewrite (A)) Note 3 Times Note 4 Electronics are used * For program update * When the EEPROM Note 5 emulation libraries Retention: 10000 Times 5 years provided by Renesas Electronics are used * The rewritable ROM size: 4 KB * For data update Expanded- Conditions other than specification the above Note 6 Retention: 100 Times 10 years Products (PD78F05xxA (A)) Conventionalspecification Products (PD78F05xx (A)) Notes 1. 2. 3. 4. 5. 6. Remarks Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or PGFP5, is used and the rewrite time during self programming, see Tables 27-12 to 27-14. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) is excluded. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) is excluded. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) are used. 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (Document No.: U17739E). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 829 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +110C) Target Products 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Conventional-specification Products Expanded-specification Products PD78F0500(A2), 78F0501(A2), 78F0502(A2), PD78F0500A(A2), 78F0501A(A2), 78F0502A(A2), 78F0503(A2) 78F0503A(A2) PD78F0511(A2), 78F0512(A2), 78F0513(A2), PD78F0511A(A2), 78F0512A(A2), 78F0513A(A2), 78F0514(A2), 78F0515(A2) 78F0514A(A2), 78F0515A(A2) PD78F0521(A2), 78F0522(A2), 78F0523(A2), PD78F0521A(A2), 78F0522A(A2), 78F0523A(A2), 78F0524(A2), 78F0525(A2), 78F0526(A2), 78F0524A(A2), 78F0525A(A2), 78F0526A(A2), 78F0527(A2) 78F0527A(A2) PD78F0531(A2), 78F0532(A2), 78F0533(A2), PD78F0531A(A2), 78F0532A(A2), 78F0533A(A2), 78F0534(A2), 78F0535(A2), 78F0536(A2), 78F0534A(A2), 78F0535A(A2), 78F0536A(A2), 78F0537(A2) 78F0537A(A2) PD78F0544(A2), 78F0545(A2), 78F0546(A2), PD78F0544A(A2), 78F0545A(A2), 78F0546A(A2), 78F0547(A2) 78F0547A(A2) The following items are described separately for conventional-specification products (PD78F05xx(A2)) and expandedspecification products (PD78F05xxA(A2)). * X1 clock oscillation frequency (X1 oscillator characteristics) * Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width ( (1) Basic operation AC characteristics) * A/D conversion time (A/D Converter Characteristics) * Number of rewrites per chip (Flash Memory Programming Characteristics) Caution in The pins mounted depend on the product as follows. (1) Port functions Port 78K0/KB2 78K0/KC2 30/36 Pins Port 0 P00, P01 Port 1 P10 to P17 Port 2 P20 to P23 Port 3 P30 to P33 38 Pins P20 to P25 - Port 4 48 Pins 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins P00 to P03 P00 to P06 P20 to P27 P40, P41 - Port 5 Port 6 44 Pins 78K0/KD2 P60, P61 Port 7 - Port 12 P120 to P122 P40 to P43 P40 to P47 P50 to P53 P50 to P57 P60 to P63 P70, P71 P60 to P67 P70 to P73 P70 to P75 P70 to P77 P120 to P124 Port 13 - P130 Port 14 - P140 P140, P141 P140 to P145 (The remaining table is on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 830 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS (2) Non-port functions Port 78K0/KB2 78K0/KC2 30/36 Pins 38 Pins 44 Pins 48 Pins 78K0/KD2 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins Note 1 , VDD, AVREF, VSS, AVSS VDD, EVDD, VSS, EVSS, AVREF, Note 1 , AVSS Power supply, VDD, EVDD ground VSS, EVSS AVREF, AVSS Regulator REGC Reset RESET Clock X1, X2, oscillation EXCLK Writing to FLMD0 X1, X2, XT1, XT2, EXCLK, EXCLKS flash memory Interrupt INTP0 to INTP5 - Key interrupt TM00 INTP0 to INTP6 KR0, KR1 Timer KR0 to KR7 TI000, TI010, TO00 - TM01 Serial interface KR0 to KR3 INTP0 to INTP7 TM50 TI50, TO50 TM51 TI51, TO51 TMH0 TOH0 TMH1 TOH1 UART0 RxD0, TxD0 UART6 RxD6, TxD6 IIC0 SCL0, SDA0 CSI10 SCK10, SI10, SO10 Note 2 TI001 , TI011 Note 2 Note 2 , TO01 SCL0, SDA0, EXSCL0 - CSI11 Note 2 , SI11 SCK11 SO11 Note 2 , SSI11 - CSIA0 Note 2 , Note 2 SCKA0, SIA0, SOA0, BUSY0, STB0 A/D converter ANI0 to ANI3 ANI0 to ANI7 - Clock output PCL - Buzzer output Low-voltage ANI0 to ANI5 BUZ EXLVI detector (LVI) Notes 1. This is not mounted onto 30-pin products. 2. This is not mounted onto the 78K0/KE2 products whose flash memory is less than 32 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 831 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 -0.5 to VDD + 0.3 AVREF REGC pin input voltage Input voltage V Note AVSS -0.5 to +0.3 VIREGC -0.5 to +3.6 and -0.5 to VDD VI1 P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V V Note V V to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET, FLMD0 VI2 Output voltage Analog input voltage P60 to P63 (N-ch open drain) -0.3 to +6.5 V VO -0.3 to VDD + 0.3 VAN -0.3 to AVREF + 0.3 ANI0 to ANI7 Note Note V V and -0.3 to VDD + 0.3 Note Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 832 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbol Ratings Unit -10 mA -25 mA -55 mA -0.5 mA -2 mA -1 mA -4 mA 30 mA 60 mA 140 mA 1 mA 5 mA 4 mA 10 mA TA -40 to +110 C Tstg -65 to +150 C IOH Conditions Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Output current, low IOL Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Operating ambient temperature Storage temperature Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. The value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 833 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. X1 Oscillator Characteristics (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator, VSS X1 X2 Parameter X1 clock Conventional- 4.0 V VDD 5.5 V oscillation specification 2.7 V VDD < 4.0 V Note 1 Crystal frequency (fX) resonator C1 Conditions C2 MIN. MAX. Unit 1.0 Note 2 TYP. 20.0 MHz 1.0 Note 2 10.0 1.0 Note 2 20.0 Products (PD78F05xx (A2)) Expanded-specification Products MHz (PD78F05xxA(A2)) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 834 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Internal Oscillator Characteristics (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Parameter 8 MHz internal oscillator Conditions Internal high-speed oscillation MIN. TYP. MAX. Unit RSTS = 1 7.6 RSTS = 0 2.48 8.0 8.4 MHz 5.6 9.86 MHz 216 240 264 kHz Note clock frequency (fRH) 240 kHz internal oscillator Internal low-speed oscillation clock frequency (fRL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM) XT1 Oscillator CharacteristicsNote 1 (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Conditions XT1 clock oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz Note 2 frequency (fXT) Rd C4 Parameter C3 Notes 1. The 78K0/KB2 is not provided with the XT1 oscillator. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 835 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (1/4) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 Conditions IOL1 -2.5 mA -2.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V -7.5 mA 2.7 V VDD < 4.0 V -6.0 mA 4.0 V VDD 5.5 V -12.5 mA 2.7 V VDD < 4.0 V -10.0 mA Total of all the pins above 4.0 V VDD 5.5 V -16.0 mA 2.7 V VDD < 4.0 V -14.0 mA Per pin for P20 to P27 AVREF = VDD -0.1 mA -0.1 mA Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V 5.0 mA 2.7 V VDD < 4.0 V 3.0 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 10.0 mA 2.7 V VDD < 4.0 V 3.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 13.0 mA 2.7 V VDD < 4.0 V 10.0 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 4.0 V VDD 5.5 V 25.0 mA 2.7 V VDD < 4.0 V 20.0 mA 4.0 V VDD 5.5 V 38.0 mA 2.7 V VDD < 4.0 V 30.0 mA AVREF = VDD 0.4 mA 0.4 mA Note 3 Total of all the pins above IOL2 Unit 2.7 V VDD < 4.0 V Per pin for P121 to P124 Note 2 MAX. 4.0 V VDD 5.5 V Note 3 Output current, low TYP. Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 IOH2 MIN. Per pin for P20 to P27 Per pin for P121 to P124 Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where the duty factor is 50%, IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(50 x 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 836 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (2/4) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high (products whose flash memory is at least Note 1 48 KB) Input voltage, high (products whose flash memory is less than Note 2 32 KB) Conditions MIN. MAX. Unit VIH1 Symbol P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145 0.7VDD VDD V VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD TYP. VIH4 P60 to P63 0.7VDD 6.0 V VIH1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P121 to P124 0.7VDD VDD V VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD VIH4 P60 to P63 0.7VDD 6.0 V VIL1 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145 0 0.3VDD V VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 0 0.3AVREF V Input voltage, low (products whose flash memory is less than Note 2 32 KB) VIL1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P60 to P63, P121 to P124 0 0.3VDD V VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 AVREF = VDD 0 0.3AVREF V Output voltage, high VOH1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V, IOH1 = -2.5 mA VDD - 0.7 V 2.7 V VDD < 4.0 V, IOH1 = -2.0 mA VDD - 0.5 V P20 to P27 AVREF = VDD, IOH2 = -100 A VDD - 0.5 V P121 to P124 IOH2 = -100 A VDD - 0.5 V Input voltage, low (products whose flash memory is at least Note 1 48 KB) VOH2 AVREF = VDD Notes 1. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB, and 78K0/KF2 2. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is less than 32 KB, 78K0/KB2, and 78K0/KC2 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 837 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (3/4) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 VOL2 VOL3 Input leakage current, ILIH1 Conditions MAX. Unit 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 0.7 V 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 0.7 V P20 to P27 AVREF = VDD, IOL2 = 0.4 mA 0.4 V P121 to P124 IOL2 = 0.4 mA 0.4 V P60 to P63 4.0 V VDD 5.5 V, IOL1 = 10.0 mA 2.0 V 4.0 V VDD 5.5 V, IOL1 = 3.0 mA 0.4 V 2.7 V VDD < 4.0 V, IOL1 =3.0 mA 0.6 V VI = VDD 3 A VI = AVREF = VDD 3 A P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P00 to P06, P10 to P17, MIN. TYP. P30 to P33, P40 to P47, high P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIH2 P20 to P27 ILIH3 P121 to 124 VI = I/O port mode 3 A (X1, X2, XT1, XT2) VDD OSC mode 20 A P00 to P06, P10 to P17, VI = VSS -3 A Input leakage current, low ILIL1 P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIL2 P20 to P27 VI = VSS, AVREF = VDD -3 A ILIL3 P121 to 124 VI = I/O port mode -3 A (X1, X2, XT1, XT2) VSS OSC mode -20 A Pull-up resistor RU VI = VSS 10 100 k FLMD0 supply voltage VIL In normal operation mode 0 0.2VDD V VIH In self-programming mode 0.8VDD VDD V Remark 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 838 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (4/4) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 Conditions Operating IDD1 mode fXH = 20 MHz, VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 10 MHz VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 MIN. TYP. MAX. Unit Square wave input 3.2 7.2 mA Resonator connection 4.5 9.0 mA Square wave input 1.6 3.7 mA Resonator connection 2.3 5.1 mA Square wave input 1.5 3.6 mA Resonator connection 2.2 4.2 mA Square wave input 0.9 2.1 mA Resonator connection 1.3 2.6 mA 1.4 3.3 mA Square wave input 6 93 A Resonator connection 15 100 A Square wave input 0.8 3.4 mA Resonator connection 2.0 5.8 mA Square wave input 0.4 1.7 mA Resonator connection 1.0 3.2 mA Square wave input 0.2 0.85 mA Resonator connection 0.5 1.5 mA 0.4 1.6 mA Square wave input 3.0 89 A Resonator connection 12 93 A 1 60 A 1 10 A 0.86 2.5 mA 5 13 A 9 24 A fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V IDD2 Note 5 HALT fXH = 20 MHz, mode VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V Note 6 IDD3 Note 5 Note 4 Note 4 STOP mode TA = -40 to +70 C A/D converter IADC Note 7 2.7 V AVREF VDD, ADCS = 1 Note 8 During 240 kHz internal low-speed oscillation clock operating current Watchdog timer IWDT operation operating current Note 9 LVI operating current Remarks 1. fXH: ILVI High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 839 78K0/Kx2 Notes 1. 2. CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the current flowing into the pull-up resistors and the output current of the port are not included. Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1 oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. 4. Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and the 5. Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal 6. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current 7. Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is the 8. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator). current flowing into the A/D converter, watchdog timer and LVI circuit. oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. flowing into the A/D converter, watchdog timer and LVI circuit. sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 9. Current flowing only to the LVI circuit. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 840 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Characteristics (1) Basic operation (1/2) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main Conventionalsystem specification clock (fXP) Products operation (PD78F05xx MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 0.1 32 s 2.7 V VDD < 4.0 V 0.2 32 s 2.7 V VDD 5.5 V 0.1 32 s 125 s (A2)) Expandedspecification Products (PD78F05xxA (A2)) Subsystem clock (fSUB) operation Peripheral hardware clock fPRS frequency Note 1 114 122 fPRS = fXH (XSEL = Conventional- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 10 MHz 1) Products Expanded- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 20 MHz Products Note 2 8.4 MHz (PD78F05xx (A2)) (PD78F05xxA (A2)) External main system clock frequency fEXCLK fPRS = fRH (XSEL = 0) 2.7 V VDD 5.5 V Conventional-specification 4.0 V VDD 5.5 V 1.0 Note 3 20.0 MHz Products 2.7 V VDD < 4.0 V 1.0 Note 3 10.0 MHz 2.7 V VDD 5.5 V 1.0 Note 3 20.0 MHz 7.6 (PD78F05xx(A2)) Expanded-specification Products (PD78F05xxA(A2)) External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL Conventional-specification 4.0 V VDD 5.5 V 24 ns Products 2.7 V V < 4.0 V 48 ns 2.7 V VDD 5.5 V 24 ns DD (PD78F05xx(A2)) Expanded-specification Products (PD78F05xxA(A2)) Notes 1. 2. 3. The 78K0/KB2 is not provided with a subsystem clock. Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fXH/2 (10 MHz) or less. The multiplier/divider, however, can operate on fXH (20 MHz). 2.0 MHz (MIN.) when using UART6 during on-board programming. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 841 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (1) Basic operation (2/2) (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) MIN. TYP. MAX. Unit External subsystem clock Note 1 frequency Parameter fEXCLKS 32 32.768 35 kHz External subsystem clock input high-level width, low-level Note 1 width tEXCLKSH, tEXCLKSL 12 s TI000, TI010, TI001, TI011 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 2/fsam + Note 2 0.1 s 2.7 V VDD < 4.0 V 2/fsam + Note 2 0.2 s TI50, TI51 input frequency fTI5 TI50, TI51 input high-level width, low-level width tTIH5, tTIL5 50 ns Interrupt input high-level width, low-level width tINTH, tINTL 1 s Key interrupt input low-level width tKR 250 ns RESET low-level width 10 s Notes 1. 2. Symbol tRSL Conditions 10 MHz The 78K0/KB2 is not provided with a subsystem clock. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 842 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation) <1> Conventional-specification Products (PD78F05xx(A2)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] <2> Expanded-specification Products (PD78F05xxA(A2)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 843 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Timing Test Points VIH VIH Test points VIL VIL External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.) 1/fEXCLKS tEXCLKSL EXCLKS R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 tEXCLKSH 0.8VDD (MIN.) 0.2VDD (MAX.) 844 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TI Timing tTIH0 tTIL0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 845 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (2) Serial interface (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 625 kbps MAX. Unit 625 kbps (b) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) IIC0 Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz SCL0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 - 0.6 - s tHD: STA 4.0 - 0.6 - s Internal clock operation 4.7 - 1.3 - s EXSCL0 clock (6.4 MHz) 4.7 - 1.25 - s 4.0 - 0.6 - s 250 - 100 0 3.45 0 Hold time Note 1 Hold time when SCL0 = "L" tLOW operation Hold time when SCL0 = "H" tHIGH Data setup time (reception) tSU: DAT Note 2 Data hold time (transmission) tHD: DAT N fW = fXH/2 or fW = fEXSCL0 selected - 0.9 Note 4 Note 3 1.00 N fW = fRH/2 selected Note 3 ns s Note 5 0 3.45 0 1.05 s Setup time of stop condition tSU: STO 4.0 - 0.6 - s Bus free time tBUF 4.7 - 1.3 - s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. 3. fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers. 4. When fW 4.4 MHz is selected 5. When fW < 4.4 MHz is selected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 846 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 tKH1, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 400 ns 4.0 V VDD 5.5 V tKCY1/2 - ns Note 1 tKL1 20 2.7 V VDD < 4.0 V tKCY1/2 - ns Note 1 30 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to tSIK1 4.0 V VDD 5.5 V 70 ns 2.7 V VDD < 4.0 V 100 ns 30 ns tKSI1 tKSO1 Note 2 C = 50 pF 40 ns MAX. Unit SO1n output Notes 1. 2. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns tKL2 SI1n setup time (to SCK1n) tSIK2 80 ns SI1n hold time (from SCK1n) tKSI2 50 ns Delay time from SCK1n to tKSO2 Note C = 50 pF 120 ns SO1n output Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 847 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tKH3, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 4.0 V VDD 5.5 V tKCY3/2 - ns tKL3 50 2.7 V VDD < 4.0 V tKCY3/2 - ns 100 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to tKSO3 SOA0 output Time from SCKA0 to STB0 Note C = 100 pF 100 ns 300 ns 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns tKCY3/2 - tSBD ns 100 Strobe signal high-level width tSBW 4.0 V VDD 5.5 V tKCY3 - ns 30 2.7 V VDD < 4.0 V tKCY3 - ns 60 Busy signal setup time (to tBYS 100 ns tBYH 100 ns busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to tSPS 4.0 V VDD 5.5 V SCKA0 2tKCY3 + ns 100 2.7 V VDD < 4.0 V 2tKCY3 - ns 150 Note C is the load capacitance of the SCKA0 and SOA0 output lines. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 848 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width SIA0 setup time (to SCKA0) Symbol Conditions MIN. MAX. 600 ns 2.7 V VDD < 4.0 V 1200 ns tKH4, 4.0 V VDD 5.5 V 300 ns tKL4 2.7 V VDD < 4.0 V 600 ns 100 ns 2/fW + ns tSIK4 100 tKSO4 Note 2 C = 100 pF 4.0 V VDD 5.5 V SOA0 output Note 1 2/fW + 100 2.7 V VDD < 4.0 V Notes 1. 2. tR4, tF4 ns Note 1 2/fW + 200 SCKA0 rise/fall time Unit 4.0 V VDD 5.5 V tKCY4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to TYP. ns Note 1 1000 ns fW is the CSIA0 base clock selected by the CSIS0 register. C is the load capacitance of the SOA0 output line. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 849 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD:DAT tHIGH tHD:STA tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop Start condition condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 850 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (2/2) CSIA0: D2 SOA0 SIA0 D1 D2 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 CSIA0 (busy processing): SCKA0 7 8 9Note 10Note tBYS 10 + nNote tBYH 1 tSPS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 851 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. A/D Converter Characteristics (TA = -40 to +110C, 2.7 V AVREF VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Resolution Conditions RES Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 EFS Note 1 Integral non-linearity error Differential non-linearity error Note 1 Analog input voltage TYP. MAX. Unit 10 bit 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR Conventional4.0 V AVREF 5.5 V specification 2.7 V AVREF < 4.0 V Products (PD78F05xx(A2)) 6.1 36.7 s 12.2 36.7 s 4.0 V AVREF 5.5 V 6.1 66.6 s 2.7 V AVREF < 4.0 V 12.2 66.6 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR Expandedspecification Products (PD78F05xxA (A2)) Notes 1. 2. MIN. 2.7 V AVREF < 4.0 V 0.6 %FSR ILE 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB DLE 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB AVREF V VAIN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 852 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. 1.59 V POC Circuit Characteristics (TA = -40 to +110C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage VPOC Power supply voltage rise inclination tPTH Minimum pulse width tPW Conditions MIN. TYP. MAX. 1.44 1.59 1.74 VDD: 0 V change inclination of VPOC Unit V 0.5 V/ms 200 s 1.59 V POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 853 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Supply Voltage Rise Time (TA = -40 to +110C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 2.7 V (VDD (MIN.)) Symbol tPUP1 (VDD: 0 V 2.7 V) Maximum time to rise to 2.7 V (VDD (MIN.)) (releasing RESET input VDD: 2.7 V) Conditions MIN. POCMODE (option byte) = 0, TYP. MAX. Unit 3.6 ms 1.9 ms when RESET input is not used tPUP2 POCMODE (option byte) = 0, when RESET input is used Supply Voltage Rise Time Timing * When RESET pin input is not used * When RESET pin input is used Supply voltage (VDD) Supply voltage (VDD) 2.7 V 2.7 V VPOC Time Time tPUP1 RESET pin tPUP2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 854 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. 2.7 V POC Circuit Characteristics (TA = -40 to +110C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage on application of supply VDDPOC Conditions POCMODE (option bye) = 1 MIN. TYP. MAX. Unit 2.50 2.70 2.90 V voltage Remark The operations of the POC circuit are as described below, depending on the POCMODE (option byte) setting. Option Byte Setting POCMODE = 0 POC Mode 1.59 V mode operation Operation A reset state is retained until VPOC = 1.59 V (TYP.) is reached after the power is turned on, and the reset is released when VPOC is exceeded. After that, POC detection is performed at VPOC, similarly as when the power was turned on. The power supply voltage must be raised at a time of tPUP1 or tPUP2 when POCMODE is 0. POCMODE = 1 2.7 V/1.59 V mode operation A reset state is retained until VDDPOC = 2.7 V (TYP.) is reached after the power is turned on, and the reset is released when VDDPOC is exceeded. After that, POC detection is performed at VPOC = 1.59 V (TYP.) and not at VDDPOC. The use of the 2.7 V/1.59 V POC mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 V, is more relaxed than tPTH. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 855 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. LVI Circuit Characteristics (TA = -40 to +110C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection Symbol Supply voltage level voltage External input pin Note 1 Minimum pulse width Operation stabilization wait time Note 2 MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.26 V VLVI8 2.91 3.01 3.11 V VLVI9 2.75 2.85 2.95 V 1.11 1.21 1.31 V EXLVI Conditions EXLVI < VDD, 2.7 V VDD 5.5 V tLW 200 s tLWAIT 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 9 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Time 856 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Operation mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 857 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Flash Memory Programming Characteristics (TA = -40 to +110C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter Symbol Conditions MIN. MAX. Unit 4.5 14.0 mA VDD supply current IDD Erase time All block Teraca 20 200 ms Block unit Terasa 20 200 ms 10 100 s Notes 1, 2 Write time (in 8-bit fXP = 10 MHz (TYP.), 20 MHz (MAX.) TYP. Twrwa Note 1 units) Number of rewrites per chip Cerwr 1 erase + Expanded- * When a flash memory Retention: 1000 programmer is used, 15 years 1 write specification after Products and the libraries erase = (PD78F05xxA provided by Renesas 1 rewrite (A2)) Note 3 Times Note 4 Electronics are used * For program update * When the EEPROM Note 5 emulation libraries Retention: 10000 Times 5 years provided by Renesas Electronics are used * The rewritable ROM size: 4 KB * For data update Expanded- Conditions other than specification the above Note 6 Retention: 100 Times 10 years Products (PD78F05xxA (A2)) Conventionalspecification Products (PD78F05xx (A2)) Notes 1. 2. 3. 4. 5. 6. Remarks Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or PGFP5, is used and the rewrite time during self programming, see Tables 27-12 to 27-14. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) is excluded. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) is excluded. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) are used. 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (Document No.: U17739E). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 858 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C) Target Products 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 Conventional-specification Products Expanded-specification Products PD78F0500(A2), 78F0501(A2), 78F0502(A2), PD78F0500A(A2), 78F0501A(A2), 78F0502A(A2), 78F0503(A2) 78F0503A(A2) PD78F0511(A2), 78F0512(A2), 78F0513(A2), PD78F0511A(A2), 78F0512A(A2), 78F0513A(A2), 78F0514(A2), 78F0515(A2) 78F0514A(A2), 78F0515A(A2) PD78F0521(A2), 78F0522(A2), 78F0523(A2), PD78F0521A(A2), 78F0522A(A2), 78F0523A(A2), 78F0524(A2), 78F0525(A2), 78F0526(A2), 78F0524A(A2), 78F0525A(A2), 78F0526A(A2), 78F0527(A2) 78F0527A(A2) PD78F0531(A2), 78F0532(A2), 78F0533(A2), PD78F0531A(A2), 78F0532A(A2), 78F0533A(A2), 78F0534(A2), 78F0535(A2), 78F0536(A2), 78F0534A(A2), 78F0535A(A2), 78F0536A(A2), 78F0537(A2) 78F0537A(A2) PD78F0544(A2), 78F0545(A2), 78F0546(A2), PD78F0544A(A2), 78F0545A(A2), 78F0546A(A2), 78F0547(A2) 78F0547A(A2) The following items are described separately for conventional-specification products (PD78F05xx(A2)) and expandedspecification products (PD78F05xxA(A2)). * X1 clock oscillation frequency (X1 oscillator characteristics) * Instruction cycle, peripheral hardware clock frequency, external main system clock frequency, external main system clock input high-level width, and external main system clock input low-level width ( (1) Basic operation AC characteristics) * A/D conversion time (A/D Converter Characteristics) * Number of rewrites per chip (Flash Memory Programming Characteristics) Caution in The pins mounted depend on the product as follows. (1) Port functions Port 78K0/KB2 78K0/KC2 30/36 Pins Port 0 P00, P01 Port 1 P10 to P17 Port 2 P20 to P23 Port 3 P30 to P33 38 Pins P20 to P25 - Port 4 48 Pins 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins P00 to P03 P00 to P06 P20 to P27 P40, P41 - Port 5 Port 6 44 Pins 78K0/KD2 P60, P61 Port 7 - Port 12 P120 to P122 P40 to P43 P40 to P47 P50 to P53 P50 to P57 P60 to P63 P70, P71 P60 to P67 P70 to P73 P70 to P75 P70 to P77 P120 to P124 Port 13 - P130 Port 14 - P140 P140, P141 P140 to P145 (The remaining table is on the next page.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 859 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS (2) Non-port functions Port 78K0/KB2 78K0/KC2 30/36 Pins 38 Pins 44 Pins 48 Pins 78K0/KD2 78K0/KE2 78K0/KF2 52 Pins 64 Pins 80 Pins Note 1 , VDD, AVREF, VSS, AVSS VDD, EVDD, VSS, EVSS, AVREF, Note 1 , AVSS Power supply, VDD, EVDD ground VSS, EVSS AVREF, AVSS Regulator REGC Reset RESET Clock X1, X2, oscillation EXCLK Writing to FLMD0 X1, X2, XT1, XT2, EXCLK, EXCLKS flash memory Interrupt INTP0 to INTP5 - Key interrupt TM00 INTP0 to INTP6 KR0, KR1 Timer KR0 to KR7 TI000, TI010, TO00 - TM01 Serial interface KR0 to KR3 INTP0 to INTP7 TM50 TI50, TO50 TM51 TI51, TO51 TMH0 TOH0 TMH1 TOH1 UART0 RxD0, TxD0 UART6 RxD6, TxD6 IIC0 SCL0, SDA0 CSI10 SCK10, SI10, SO10 Note 2 TI001 , TI011 Note 2 Note 2 , TO01 SCL0, SDA0, EXSCL0 - CSI11 Note 2 , SI11 SCK11 SO11 Note 2 , SSI11 - CSIA0 Note 2 , Note 2 SCKA0, SIA0, SOA0, BUSY0, STB0 A/D converter ANI0 to ANI3 ANI0 to ANI7 - Clock output PCL - Buzzer output Low-voltage ANI0 to ANI5 BUZ EXLVI detector (LVI) Notes 1. This is not mounted onto 30-pin products. 2. This is not mounted onto the 78K0/KE2 products whose flash memory is less than 32 KB. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 860 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 -0.5 to VDD + 0.3 AVREF REGC pin input voltage Input voltage V Note AVSS -0.5 to +0.3 VIREGC -0.5 to +3.6 and -0.5 to VDD VI1 P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V V Note V V to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET, FLMD0 VI2 Output voltage Analog input voltage P60 to P63 (N-ch open drain) -0.3 to +6.5 V VO -0.3 to VDD + 0.3 VAN -0.3 to AVREF + 0.3 ANI0 to ANI7 Note Note V V and -0.3 to VDD + 0.3 Note Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 861 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbol Ratings Unit -10 mA -25 mA -55 mA -0.5 mA -2 mA -1 mA -4 mA 30 mA 60 mA 140 mA 1 mA 5 mA 4 mA 10 mA TA -40 to +125 C Tstg -65 to +150 C IOH Conditions Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Output current, low IOL Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin P20 to P27 Total of all pins Per pin P121 to P124 Total of all pins Operating ambient temperature Storage temperature Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. The value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 862 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. X1 Oscillator Characteristics (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator, VSS X1 X2 Parameter X1 clock Conventional- 4.0 V VDD 5.5 V oscillation specification 2.7 V VDD < 4.0 V Note 1 Crystal frequency (fX) resonator C1 Conditions C2 MIN. MAX. Unit 1.0 Note 2 TYP. 20.0 MHz 1.0 Note 2 10.0 1.0 Note 2 20.0 Products (PD78F05xx (A2)) Expanded-specification Products MHz (PD78F05xxA(A2)) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 863 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Internal Oscillator Characteristics (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Parameter 8 MHz internal oscillator Conditions Internal high-speed oscillation MIN. TYP. MAX. Unit RSTS = 1 7.6 8.0 8.46 MHz RSTS = 0 2.48 5.6 9.86 MHz 216 240 264 kHz Note clock frequency (fRH) 240 kHz internal oscillator Internal low-speed oscillation clock frequency (fRL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM) XT1 Oscillator CharacteristicsNote 1 (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Conditions XT1 clock oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz Note 2 frequency (fXT) Rd C4 Parameter C3 Notes 1. The 78K0/KB2 is not provided with the XT1 oscillator. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 864 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (1/4) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 Conditions IOL1 -1.5 mA -1.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V -6.0 mA 2.7 V VDD < 4.0 V -4.0 mA 4.0 V VDD 5.5 V -10.0 mA 2.7 V VDD < 4.0 V -8.0 mA Total of all the pins above 4.0 V VDD 5.5 V -14.0 mA 2.7 V VDD < 4.0 V -12.0 mA Per pin for P20 to P27 AVREF = VDD -0.1 mA -0.1 mA Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V 4.0 mA 2.7 V VDD < 4.0 V 2.0 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 8.0 mA 2.7 V VDD < 4.0 V 2.0 mA Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 10.0 mA 2.7 V VDD < 4.0 V 8.0 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 4.0 V VDD 5.5 V 20.0 mA 2.7 V VDD < 4.0 V 16.0 mA 4.0 V VDD 5.5 V 30.0 mA 2.7 V VDD < 4.0 V 24.0 mA AVREF = VDD 0.4 mA 0.4 mA Note 3 Total of all the pins above IOL2 Unit 2.7 V VDD < 4.0 V Per pin for P121 to P124 Note 2 MAX. 4.0 V VDD 5.5 V Note 3 Output current, low TYP. Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 IOH2 MIN. Per pin for P20 to P27 Per pin for P121 to P124 Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where the duty factor is 50%, IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(50 x 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 865 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (2/4) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high (products whose flash memory is at least Note 1 48 KB) Input voltage, high (products whose flash memory is less than Note 2 32 KB) Conditions MIN. MAX. Unit VIH1 Symbol P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145 0.7VDD VDD V VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD TYP. VIH4 P60 to P63 0.7VDD 6.0 V VIH1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P121 to P124 0.7VDD VDD V VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V AVREF = VDD VIH4 P60 to P63 0.7VDD 6.0 V VIL1 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145 0 0.3VDD V VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 0 0.3AVREF V Input voltage, low (products whose flash memory is less than Note 2 32 KB) VIL1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P60 to P63, P121 to P124 0 0.3VDD V VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140, P141, EXCLK, EXCLKS, RESET 0 0.2VDD V VIL3 P20 to P27 AVREF = VDD 0 0.3AVREF V Output voltage, high VOH1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 4.0 V VDD 5.5 V, IOH1 = -1.5 mA VDD - 0.7 V 2.7 V VDD < 4.0 V, IOH1 = -1.0 mA VDD - 0.5 V P20 to P27 AVREF = VDD, IOH2 = -100 A VDD - 0.5 V P121 to P124 IOH2 = -100 A VDD - 0.5 V Input voltage, low (products whose flash memory is at least Note 1 48 KB) VOH2 AVREF = VDD Notes 1. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB, and 78K0/KF2 2. Supported products: 78K0/KD2 and 78K0/KE2 whose flash memory is less than 32 KB, 78K0/KB2, and 78K0/KC2 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 866 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (3/4) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 VOL2 VOL3 Input leakage current, ILIH1 Conditions MAX. Unit 4.0 V VDD 5.5 V, IOL1 = 4.0 mA 0.7 V 2.7 V VDD < 4.0 V, IOL1 = 2.0 mA 0.7 V P20 to P27 AVREF = VDD, IOL2 = 0.4 mA 0.4 V P121 to P124 IOL2 = 0.4 mA 0.4 V P60 to P63 4.0 V VDD 5.5 V, IOL1 = 8.0 mA 2.0 V 4.0 V VDD 5.5 V, IOL1 = 2.0 mA 0.6 V 2.7 V VDD < 4.0 V, IOL1 = 2.0 mA 0.6 V VI = VDD 5 A VI = AVREF = VDD 5 A P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P00 to P06, P10 to P17, MIN. TYP. P30 to P33, P40 to P47, high P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIH2 P20 to P27 ILIH3 P121 to 124 VI = I/O port mode 5 A (X1, X2, XT1, XT2) VDD OSC mode 20 A P00 to P06, P10 to P17, VI = VSS -5 A Input leakage current, low ILIL1 P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P140 to P145, FLMD0, RESET ILIL2 P20 to P27 VI = VSS, AVREF = VDD -5 A ILIL3 P121 to 124 VI = I/O port mode -5 A (X1, X2, XT1, XT2) VSS OSC mode -20 A Pull-up resistor RU VI = VSS 10 100 k FLMD0 supply voltage VIL In normal operation mode 0 0.2VDD V VIH In self-programming mode 0.8VDD VDD V Remark 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 867 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. DC Characteristics (4/4) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 Conditions Operating IDD1 mode fXH = 20 MHz, VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 10 MHz VDD = 3.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 MIN. TYP. MAX. Unit Square wave input 3.2 8.3 mA Resonator connection 4.5 10.5 mA Square wave input 1.6 4.2 mA Resonator connection 2.3 5.9 mA Square wave input 1.5 4.1 mA Resonator connection 2.2 4.8 mA Square wave input 0.9 2.4 mA Resonator connection 1.3 3.0 mA 1.4 3.8 mA Square wave input 6 138 A Resonator connection 15 145 A Square wave input 0.8 3.9 mA Resonator connection 2.0 6.6 mA Square wave input 0.4 2.0 mA Resonator connection 1.0 3.6 mA Square wave input 0.2 1.0 mA Resonator connection 0.5 1.7 mA 0.4 1.8 mA Square wave input 3.0 133 A Resonator connection 12 138 A 1 100 A 1 10 A 0.86 2.9 mA 5 15 A 9 27 A fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V IDD2 Note 5 HALT fXH = 20 MHz, mode VDD = 5.0 V Note 2 fXH = 10 MHz, VDD = 5.0 V Notes 2, 3 fXH = 5 MHz, VDD = 3.0 V Notes 2, 3 fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz, VDD = 5.0 V Note 6 IDD3 Note 5 Note 4 Note 4 STOP mode TA = -40 to +70 C A/D converter IADC Note 7 2.7 V AVREF VDD, ADCS = 1 Note 8 During 240 kHz internal low-speed oscillation clock operating current Watchdog timer IWDT operation operating current Note 9 LVI operating current Remarks 1. fXH: ILVI High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 868 78K0/Kx2 Notes 1. 2. CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the current flowing into the pull-up resistors and the output current of the port are not included. Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1 oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. 4. Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and the 5. Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal 6. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current 7. Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is the 8. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator). current flowing into the A/D converter, watchdog timer and LVI circuit. oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. flowing into the A/D converter, watchdog timer and LVI circuit. sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 9. Current flowing only to the LVI circuit. The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 869 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Characteristics (1) Basic operation (1/2) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main Conventionalsystem specification clock (fXP) Products operation (PD78F05xx MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 0.1 32 s 2.7 V VDD < 4.0 V 0.2 32 s 2.7 V VDD 5.5 V 0.1 32 s 125 s (A2)) Expandedspecification Products (PD78F05xxA (A2)) Subsystem clock (fSUB) operation Peripheral hardware clock fPRS frequency Note 1 114 122 fPRS = fXH (XSEL = Conventional- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 10 MHz 1) Products Expanded- 4.0 V VDD 5.5 V 20 MHz specification 2.7 V VDD < 4.0 V 20 MHz Products Note 2 8.4 MHz (PD78F05xx (A2)) (PD78F05xxA (A2)) External main system clock frequency fEXCLK fPRS = fRH (XSEL = 0) 2.7 V VDD 5.5 V Conventional-specification 4.0 V VDD 5.5 V 1.0 Note 3 20.0 MHz Products 2.7 V VDD < 4.0 V 1.0 Note 3 10.0 MHz 2.7 V VDD 5.5 V 1.0 Note 3 20.0 MHz 7.6 (PD78F05xx(A2)) Expanded-specification Products (PD78F05xxA(A2)) External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL Conventional-specification 4.0 V VDD 5.5 V 24 ns Products 2.7 V VDD < 4.0 V 48 ns 2.7 V VDD 5.5 V 24 ns (PD78F05xx(A2)) Expanded-specification Products (PD78F05xxA(A2)) Notes 1. 2. 3. The 78K0/KB2 is not provided with a subsystem clock. Characteristics of the main system clock frequency. Set the division clock to be set by a peripheral function to fXH/2 (10 MHz) or less. The multiplier/divider, however, can operate on fXH (20 MHz). 2.0 MHz (MIN.) when using UART6 during on-board programming. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 870 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (1) Basic operation (2/2) (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) MIN. TYP. MAX. Unit External subsystem clock Note 1 frequency Parameter fEXCLKS 32 32.768 35 kHz External subsystem clock input high-level width, low-level Note 1 width tEXCLKSH, tEXCLKSL 12 s TI000, TI010, TI001, TI011 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 2/fsam + Note 2 0.1 s 2.7 V VDD < 4.0 V 2/fsam + Note 2 0.2 s TI50, TI51 input frequency fTI5 TI50, TI51 input high-level width, low-level width tTIH5, tTIL5 50 ns Interrupt input high-level width, low-level width tINTH, tINTL 1 s Key interrupt input low-level width tKR 250 ns RESET low-level width 10 s Notes 1. 2. Symbol tRSL Conditions 10 MHz The 78K0/KB2 is not provided with a subsystem clock. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 871 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation) <1> Conventional-specification Products (PD78F05xx(A2)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] <2> Expanded-specification Products (PD78F05xxA(A2)) 100 32 10 Cycle time TCY [ s] 5.0 Guaranteed operation range (The gray portion is applicable only if AMPH = 1 is set.) 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 872 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. AC Timing Test Points VIH VIH Test points VIL VIL External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.) 1/fEXCLKS tEXCLKSL EXCLKS R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 tEXCLKSH 0.8VDD (MIN.) 0.2VDD (MAX.) 873 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. TI Timing tTIH0 tTIL0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 874 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (2) Serial interface (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 625 kbps MAX. Unit 625 kbps (b) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) IIC0 Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz SCL0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 - 0.6 - s tHD: STA 4.0 - 0.6 - s Internal clock operation 4.7 - 1.3 - s EXSCL0 clock (6.4 MHz) 4.7 - 1.25 - s 4.0 - 0.6 - s 250 - 100 0 3.45 0 Hold time Note 1 Hold time when SCL0 = "L" tLOW operation Hold time when SCL0 = "H" tHIGH Data setup time (reception) tSU: DAT Note 2 Data hold time (transmission) tHD: DAT N fW = fXH/2 or fW = fEXSCL0 selected - 0.9 Note 4 Note 3 1.00 N fW = fRH/2 selected Note 3 ns s Note 5 0 3.45 0 1.05 s Setup time of stop condition tSU: STO 4.0 - 0.6 - s Bus free time tBUF 4.7 - 1.3 - s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. 3. fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers. 4. When fW 4.4 MHz is selected 5. When fW < 4.4 MHz is selected R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 875 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 tKH1, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 400 ns 4.0 V VDD 5.5 V tKCY1/2 - ns Note 1 tKL1 20 2.7 V VDD < 4.0 V tKCY1/2 - ns Note 1 30 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to tSIK1 4.0 V VDD 5.5 V 70 ns 2.7 V VDD < 4.0 V 100 ns 30 ns tKSI1 tKSO1 Note 2 C = 50 pF 40 ns MAX. Unit SO1n output Notes 1. 2. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. tKCY2 400 ns tKH2, tKCY2/2 ns tKL2 SI1n setup time (to SCK1n) tSIK2 80 ns SI1n hold time (from SCK1n) tKSI2 50 ns Delay time from SCK1n to tKSO2 Note C = 50 pF 120 ns SO1n output Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 876 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width Symbol tKCY3 tKH3, Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V 600 ns 2.7 V VDD < 4.0 V 1200 ns 4.0 V VDD 5.5 V tKCY3/2 - ns tKL3 50 2.7 V VDD < 4.0 V tKCY3/2 - ns 100 SIA0 setup time (to SCKA0) tSIK3 SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to tKSO3 SOA0 output Time from SCKA0 to STB0 Note C = 100 pF 100 ns 300 ns 4.0 V VDD 5.5 V 200 ns 2.7 V VDD < 4.0 V 300 ns tKCY3/2 - tSBD ns 100 Strobe signal high-level width tSBW 4.0 V VDD 5.5 V tKCY3 - ns 30 2.7 V VDD < 4.0 V tKCY3 - ns 60 Busy signal setup time (to tBYS 100 ns tBYH 100 ns busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to tSPS 4.0 V VDD 5.5 V SCKA0 2tKCY3 + ns 100 2.7 V VDD < 4.0 V 2tKCY3 - ns 150 Note C is the load capacitance of the SCKA0 and SOA0 output lines. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 877 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width SIA0 setup time (to SCKA0) Symbol Conditions MIN. MAX. 600 ns 2.7 V VDD < 4.0 V 1200 ns tKH4, 4.0 V VDD 5.5 V 300 ns tKL4 2.7 V VDD < 4.0 V 600 ns 100 ns 2/fW + ns tSIK4 100 tKSO4 Note 2 C = 100 pF 4.0 V VDD 5.5 V SOA0 output Note 1 2/fW + 100 2.7 V VDD < 4.0 V Notes 1. 2. tR4, tF4 ns Note 1 2/fW + 200 SCKA0 rise/fall time Unit 4.0 V VDD 5.5 V tKCY4 SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to TYP. ns Note 1 1000 ns fW is the CSIA0 base clock selected by the CSIS0 register. C is the load capacitance of the SOA0 output line. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 878 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD:DAT tHIGH tHD:STA tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop Start condition condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0, 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 879 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Serial Transfer Timing (2/2) CSIA0: D2 SOA0 SIA0 D1 D2 D0 D1 D7 D0 D7 tKSI3, 4 tSIK3, 4 tKH3, 4 tKSO3, 4 tF4 SCKA0 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW STB0 CSIA0 (busy processing): SCKA0 7 8 9Note 10Note tBYS 10 + nNote tBYH 1 tSPS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 880 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. A/D Converter Characteristics (TA = -40 to +125C, 2.7 V AVREF VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Resolution Conditions RES Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 EFS Note 1 Integral non-linearity error Differential non-linearity error Note 1 Analog input voltage TYP. MAX. Unit 10 bit 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR Conventional4.0 V AVREF 5.5 V specification 2.7 V AVREF < 4.0 V Products (PD78F05xx(A2)) 6.1 36.7 s 12.2 36.7 s 4.0 V AVREF 5.5 V 6.1 66.6 s 2.7 V AVREF < 4.0 V 12.2 66.6 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR Expandedspecification Products (PD78F05xxA (A2)) Notes 1. 2. MIN. 2.7 V AVREF < 4.0 V 0.6 %FSR ILE 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB DLE 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB AVREF V VAIN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 881 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. 1.59 V POC Circuit Characteristics (TA = -40 to +125C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage VPOC Power supply voltage rise inclination tPTH Minimum pulse width tPW Conditions MIN. TYP. MAX. 1.44 1.59 1.74 VDD: 0 V change inclination of VPOC Unit V 0.5 V/ms 200 s 1.59 V POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 882 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Supply Voltage Rise Time (TA = -40 to +125C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 2.7 V (VDD (MIN.)) Symbol tPUP1 (VDD: 0 V 2.7 V) Maximum time to rise to 2.7 V (VDD (MIN.)) (releasing RESET input VDD: 2.7 V) Conditions MIN. POCMODE (option byte) = 0, TYP. MAX. Unit 3.6 ms 1.9 ms when RESET input is not used tPUP2 POCMODE (option byte) = 0, when RESET input is used Supply Voltage Rise Time Timing * When RESET pin input is not used * When RESET pin input is used Supply voltage (VDD) Supply voltage (VDD) 2.7 V 2.7 V VPOC Time Time tPUP1 RESET pin tPUP2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 883 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. 2.7 V POC Circuit Characteristics (TA = -40 to +125C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage on application of supply VDDPOC Conditions POCMODE (option bye) = 1 MIN. TYP. MAX. Unit 2.50 2.70 2.90 V voltage Remark The operations of the POC circuit are as described below, depending on the POCMODE (option byte) setting. Option Byte Setting POCMODE = 0 POC Mode 1.59 V mode operation Operation A reset state is retained until VPOC = 1.59 V (TYP.) is reached after the power is turned on, and the reset is released when VPOC is exceeded. After that, POC detection is performed at VPOC, similarly as when the power was turned on. The power supply voltage must be raised at a time of tPUP1 or tPUP2 when POCMODE is 0. POCMODE = 1 2.7 V/1.59 V mode operation A reset state is retained until VDDPOC = 2.7 V (TYP.) is reached after the power is turned on, and the reset is released when VDDPOC is exceeded. After that, POC detection is performed at VPOC = 1.59 V (TYP.) and not at VDDPOC. The use of the 2.7 V/1.59 V POC mode is recommended when the rise of the voltage, after the power is turned on and until the voltage reaches 1.8 V, is more relaxed than tPTH. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 884 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. LVI Circuit Characteristics (TA = -40 to +125C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection Symbol Supply voltage level voltage External input pin Note 1 Minimum pulse width Operation stabilization wait time Note 2 MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.26 V VLVI8 2.91 3.01 3.11 V VLVI9 2.75 2.85 2.95 V 1.11 1.21 1.31 V EXLVI Conditions EXLVI < VDD, 2.7 V VDD 5.5 V tLW 200 s tLWAIT 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 9 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Time 885 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +125C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Operation mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 886 78K0/Kx2 CHAPTER 33 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter. Flash Memory Programming Characteristics (TA = -40 to +125C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter Symbol Conditions MIN. MAX. Unit 4.5 16.0 mA VDD supply current IDD Erase time All block Teraca 20 200 ms Block unit Terasa 20 200 ms 10 100 s Notes 1, 2 Write time (in 8-bit fXP = 10 MHz (TYP.), 20 MHz (MAX.) TYP. Twrwa Note 1 units) Number of rewrites per chip Cerwr 1 erase + Expanded- * When a flash memory Retention: 1000 programmer is used, 15 years 1 write specification after Products and the libraries erase = (PD78F05xxA provided by Renesas 1 rewrite (A2)) Note 3 Times Note 4 Electronics are used * For program update * When the EEPROM Note 5 emulation libraries Retention: 10000 Times 5 years provided by Renesas Electronics are used * The rewritable ROM size: 4 KB * For data update Expanded- Conditions other than specification the above Note 6 Retention: 100 Times 10 years Products (PD78F05xxA (A2)) Conventionalspecification Products (PD78F05xx (A2)) Notes 1. 2. 3. 4. 5. 6. Remarks Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or PGFP5, is used and the rewrite time during self programming, see Tables 27-12 to 27-14. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) is excluded. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) is excluded. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming User's Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.: U17517E) are used. 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (Document No.: U17739E). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 887 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS CHAPTER 34 PACKAGE DRAWINGS 34.1 78K0/KB2 * PD78F0500MC-5A4-A, 78F0501MC-5A4-A, 78F0502MC-5A4-A, 78F0503MC-5A4-A, 78F0503DMC-5A4-A 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. K ITEM A MILLIMETERS 9.850.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 S30MC-65-5A4-2 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 888 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0500MC(A)-CAB-AX, 78F0501MC(A)-CAB-AX, 78F0502MC(A)-CAB-AX, 78F0503MC(A)-CAB-AX * PD78F0500MC(A2)-CAB-AX, 78F0501MC(A2)-CAB-AX, 78F0502MC(A2)-CAB-AX, 78F0503MC(A2)-CAB-AX * PD78F0500AMC-CAB-AX, 78F0501AMC-CAB-AX, 78F0502AMC-CAB-AX, 78F0503AMC-CAB-AX, 78F0503DAMCCAB-AX * PD78F0500AMCA-CAB-G, 78F0501AMCA-CAB-G, 78F0502AMCA-CAB-G, 78F0503AMCA-CAB-G * PD78F0500AMCA2-CAB-G, 78F0501AMCA2-CAB-G, 78F0502AMCA2-CAB-G, 78F0503AMCA2-CAB-G 30-PIN PLASTIC SSOP (7.62mm (300)) 30 V 16 detail of lead end T I P 1 U V 15 W L W A H F G J S C E D N S B M M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. K (UNIT:mm) ITEM A B 9.700.10 0.30 C 0.65 (T.P.) D 0.22 +0.10 -0.05 E 0.100.05 F 1.300.10 G 1.20 H 8.100.20 I 6.100.10 J 1.000.20 0.15 +0.05 -0.01 K L 0.50 M 0.13 N 0.10 P 3 +5 -3 T 0.25(T.P.) U 0.600.15 V W R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 DIMENSIONS 0.25 MAX. 0.15 MAX. P30MC-65-CAB 889 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0500FC-AA3-A, 78F0501FC-AA3-A, 78F0502FC-AA3-A, 78F0503FC-AA3-A, 78F0503DFC-AA3-A * PD78F0500AFC-AA3-A, 78F0501AFC-AA3-A, 78F0502AFC-AA3-A, 78F0503AFC-AA3-A, 78F0503DAFC-AA3-A 36-PIN PLASTIC FLGA (4x4) x 32x b M S AB A ZE w S A D e ZD 6 5 B 4 E 3 2.90 2 C 1 D F E y1 S E 2.90 w S B INDEX MARK D C B A A S y S DETAIL OF C PART DETAIL OF D PART DETAIL OF E PART R0.170.05 0.700.05 0.550.05 R0.120.05 0.75 0.55 R0.170.05 0.700.05 R0.120.05 0.550.05 0.75 0.55 (UNIT:mm) ITEM D DIMENSIONS 4.000.10 E 4.000.10 w 0.20 e 0.50 A 0.910.07 b (Land pad) b 0.240.05 x 0.05 0.340.05 (Aperture of solder resist) y 0.08 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.55 0.75 0.550.05 0.700.05 0.55 0.75 0.550.05 0.700.05 R0.2750.05 R0.350.05 y1 0.20 ZD 0.75 ZE 0.75 P36FC-50-AA3-2 890 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS 34.2 78K0/KC2 * PD78F0511AMC-GAA-AX, 78F0512AMC-GAA-AX, 78F0513AMC-GAA-AX, 78F0513DAMC-GAA-AX * PD78F0511AMCA-GAA-G, 78F0512AMCA-GAA-G, 78F0513AMCA-GAA-G * PD78F0511AMCA2-GAA-G, 78F0512AMCA2-GAA-G, 78F0513AMCA2-GAA-G 38-PIN PLASTIC SSOP (7.62mm (300)) 38 V 20 detail of lead end T I P 1 U V 19 W L W A H F G J S C E D N S M M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. B K (UNIT:mm) ITEM A B 12.300.10 0.30 C 0.65 (T.P.) D 0.30 +0.10 -0.05 E 0.1250.075 F 2.00 MAX. G 1.700.10 H 8.100.20 I 6.100.10 J 1.000.20 0.15 +0.10 -0.05 K L 0.50 M 0.10 N 0.10 P 3 +5 -3 T 0.25(T.P.) U 0.600.15 V W R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 DIMENSIONS 0.25 MAX. 0.15 MAX. P38MC-65-GAA 891 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0511GB-UES-A, 78F0512GB-UES-A, 78F0513GB-UES-A, 78F0513DGB-UES-A 44-PIN PLASTIC LQFP(10x10) HD D detail of lead end A3 23 22 33 34 c E L Lp HE L1 12 11 44 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 S y S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. A1 0.37 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 b 1.00 P44GB-80-UES-1 892 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0511GB(A)-GAF-AX, 78F0512GB(A)-GAF-AX, 78F0513GB(A)-GAF-AX * PD78F0511GB(A2)-GAF-AX, 78F0512GB(A2)-GAF-AX, 78F0513GB(A2)-GAF-AX * PD78F0511AGB-GAF-AX, 78F0512AGB-GAF-AX, 78F0513AGB-GAF-AX, 78F0513DAGB-GAF-AX * PD78F0511AGBA-GAF-G, 78F0512AGBA-GAF-G, 78F0513AGBA-GAF-G * PD78F0511AGBA2-GAF-G, 78F0512AGBA2-GAF-G, 78F0513AGBA2-GAF-G 44-PIN PLASTIC LQFP (10x10) HD detail of lead end D L1 33 A3 23 c 22 34 L Lp E HE (UNIT:mm) 44 12 11 1 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.35 +0.08 -0.04 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE 1.00 P44GB-80-GAF 893 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0511GA-8EU-A, 78F0512GA-8EU-A, 78F0513GA-8EU-A, 78F0514GA-8EU-A, 78F0515GA-8EU-A, 78F0515DGA-8EU-A 48-PIN PLASTIC LQFP (FINE PITCH)(7x7) HD D detail of lead end 36 25 37 A3 24 c E L Lp HE L1 13 48 12 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b S c L y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 0.220.05 0.145 +0.055 -0.045 0.50 0.75 P48GA-50-8EU 894 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0511GA(A)-GAM-AX, 78F0512GA(A)-GAM-AX, 78F0513GA(A)-GAM-AX, 78F0514GA(A)-GAM-AX, 78F0515GA(A)-GAM-AX * PD78F0511GA(A2)-GAM-AX, 78F0512GA(A2)-GAM-AX, 78F0513GA(A2)-GAM-AX, 78F0514GA(A2)-GAM-AX, 78F0515GA(A2)-GAM-AX * PD78F0511AGA-GAM-AX, 78F0512AGA-GAM-AX, 78F0513AGA-GAM-AX, 78F0514AGA-GAM-AX, 78F0515AGAGAM-AX, 78F0515DAGA-GAM-AX * PD78F0511AGAA-GAM-G, 78F0512AGAA-GAM-G, 78F0513AGAA-GAM-G, 78F0514AGAA-GAM-G, 78F0515AGAAGAM-G * PD78F0511AGAA2-GAM-G, 78F0512AGAA2-GAM-G, 78F0513AGAA2-GAM-G, 78F0514AGAA2-GAM-G, 78F0515AGAA2-GAM-G 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) HD D detail of lead end 36 A3 25 37 c 24 L Lp E L1 HE (UNIT:mm) 13 48 1 12 ZE e ZD b x M S A S A2 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 +0.07 0.20 -0.03 b S y ITEM D c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 P48GA-50-GAM 895 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS 34.3 78K0/KD2 * PD78F0521GB-UET-A, 78F0522GB-UET-A, 78F0523GB-UET-A, 78F0524GB-UET-A, 78F0525GB-UET-A, 78F0526GB-UET-A, 78F0527GB-UET-A, 78F0527DGB-UET-A 52-PIN PLASTIC LQFP(10x10) HD D detail of lead end 27 39 40 A3 26 c E L Lp HE L1 14 52 1 (UNIT:mm) 13 ZE e ZD b x M S A A2 ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 S y S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. A1 0.32 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD 1.10 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 b 1.10 P52GB-65-UET-1 896 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0521GB(A)-GAG-AX, 78F0522GB(A)-GAG-AX, 78F0523GB(A)-GAG-AX, 78F0524GB(A)-GAG-AX, 78F0525GB(A)-GAG-AX, 78F0526GB(A)-GAG-AX, 78F0527GB(A)-GAG-AX * PD78F0521GB(A2)-GAG-AX, 78F0522GB(A2)-GAG-AX, 78F0523GB(A2)-GAG-AX, 78F0524GB(A2)-GAG-AX, 78F0525GB(A2)-GAG-AX, 78F0526GB(A2)-GAG-AX, 78F0527GB(A2)-GAG-AX * PD78F0521AGB-GAG-AX, 78F0522AGB-GAG-AX, 78F0523AGB-GAG-AX, 78F0524AGB-GAG-AX, 78F0525AGBGAG-AX, 78F0526AGB-GAG-AX, 78F0527AGB-GAG-AX, 78F0527DAGB-GAG-AX * PD78F0521AGBA-GAG-G, 78F0522AGBA-GAG-G, 78F0523AGBA-GAG-G, 78F0524AGBA-GAG-G, 78F0525AGBA-GAG-G, 78F0526AGBA-GAG-G, 78F0527AGBA-GAG-G * PD78F0521AGBA2-GAG-G, 78F0522AGBA2-GAG-G, 78F0523AGBA2-GAG-G, 78F0524AGBA2-GAG-G, 78F0525AGBA2-GAG-G, 78F0526AGBA2-GAG-G, 78F0527AGBA2-GAG-G 52-PIN PLASTIC LQFP (10x10) HD detail of lead end D L1 39 40 27 26 A3 c E L HE Lp (UNIT:mm) 52 14 13 1 ZE e b ZD x M S A2 S S NOTE Each lead centerline is located within 0.13mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A y ITEM D A1 0.25 b 0.30 +0.08 -0.04 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD 1.10 ZE 1.10 P52GB-65-GAG 897 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS 34.4 78K0/KE2 * PD78F0531GB-UEU-A, 78F0532GB-UEU-A, 78F0533GB-UEU-A, 78F0534GB-UEU-A, 78F0535GB-UEU-A, 78F0536GB-UEU-A, 78F0537GB-UEU-A, 78F0537DGB-UEU-A 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 33 49 A3 32 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 L 0.25 0.220.05 0.145 +0.55 -0.45 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-UEU 898 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GB(A)-GAH-AX, 78F0532GB(A)-GAH-AX, 78F0533GB(A)-GAH-AX, 78F0534GB(A)-GAH-AX, 78F0535GB(A)-GAH-AX, 78F0536GB(A)-GAH-AX, 78F0537GB(A)-GAH-AX * PD78F0531GB(A2)-GAH-AX, 78F0532GB(A2)-GAH-AX, 78F0533GB(A2)-GAH-AX, 78F0534GB(A2)-GAH-AX, 78F0535GB(A2)-GAH-AX, 78F0536GB(A2)-GAH-AX, 78F0537GB(A2)-GAH-AX * PD78F0531AGB-GAH-AX, 78F0532AGB-GAH-AX, 78F0533AGB-GAH-AX, 78F0534AGB-GAH-AX, 78F0535AGBGAH-AX, 78F0536AGB-GAH-AX, 78F0537AGB-GAH-AX, 78F0537DAGB-GAH-AX * PD78F0531AGBA-GAH-G, 78F0532AGBA-GAH-G, 78F0533AGBA-GAH-G, 78F0534AGBA-GAH-G, 78F0535AGBAGAH-G, 78F0536AGBA-GAH-G, 78F0537AGBA-GAH-G * PD78F0531AGBA2-GAH-G, 78F0532AGBA2-GAH-G, 78F0533AGBA2-GAH-G, 78F0534AGBA2-GAH-G, 78F0535AGBA2-GAH-G, 78F0536AGBA2-GAH-G, 78F0537AGBA2-GAH-G 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 A3 33 49 c 32 L Lp E L1 HE (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A A2 S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 b +0.07 0.20 -0.03 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-GAH 899 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GC-UBS-A, 78F0532GC-UBS-A, 78F0533GC-UBS-A, 78F0534GC-UBS-A, 78F0535GC-UBS-A, 78F0536GC-UBS-A, 78F0537GC-UBS-A, 78F0537DGC-UBS-A 64-PIN PLASTIC LQFP(14x14) HD D detail of lead end 48 49 A3 33 32 c E L Lp HE L1 64 17 16 1 (UNIT:mm) ZE e ZD b x M S A A2 S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. A1 DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 S y ITEM D 0.37 +0.08 -0.07 c 0.17 +0.03 -0.06 L 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 b 1.00 P64GC-80-UBS 900 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GC(A)-GAL-AX, 78F0532GC(A)-GAL-AX, 78F0533GC(A)-GAL-AX, 78F0534GC(A)-GAL-AX, 78F0535GC(A)-GAL-AX, 78F0536GC(A)-GAL-AX, 78F0537GC(A)-GAL-AX * PD78F0531GC(A2)-GAL-AX, 78F0532GC(A2)-GAL-AX, 78F0533GC(A2)-GAL-AX, 78F0534GC(A2)-GAL-AX, 78F0535GC(A2)-GAL-AX, 78F0536GC(A2)-GAL-AX, 78F0537GC(A2)-GAL-AX * PD78F0531AGC-GAL-AX, 78F0532AGC-GAL-AX, 78F0533AGC-GAL-AX, 78F0534AGC-GAL-AX, 78F0535AGC-GAL-AX, 78F0536AGC-GAL-AX, 78F0537AGC-GAL-AX, 78F0537DAGC-GAL-AX * PD78F0531AGCA-GAL-G, 78F0532AGCA-GAL-G, 78F0533AGCA-GAL-G, 78F0534AGCA-GAL-G, 78F0535AGCA-GAL-G, 78F0536AGCA-GAL-G, 78F0537AGCA-GAL-G * PD78F0531AGCA2-GAL-G, 78F0532AGCA2-GAL-G, 78F0533AGCA2-GAL-G, 78F0534AGCA2-GAL-G, 78F0535AGCA2-GAL-G, 78F0536AGCA2-GAL-G, 78F0537AGCA2-GAL-G 64-PIN PLASTIC LQFP (14x14) HD detail of lead end D A3 48 49 33 32 c L Lp E HE L1 (UNIT:mm) 64 17 16 1 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.35 +0.08 -0.04 c 0.125 +0.075 -0.025 L 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE 1.00 P64GC-80-GAL 901 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GK-UET-A, 78F0532GK-UET-A, 78F0533GK-UET-A, 78F0534GK-UET-A, 78F0535GK-UET-A, 78F0536GK-UET-A, 78F0537GK-UET-A, 78F0537DGK-UET-A 64-PIN PLASTIC LQFP(12x12) HD D detail of lead end 48 33 49 32 A3 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.32 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD ZE 1.125 1.125 P64GK-65-UET-1 902 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GK(A)-GAJ-AX, 78F0532GK(A)-GAJ-AX, 78F0533GK(A)-GAJ-AX, 78F0534GK(A)-GAJ-AX, 78F0535GK(A)-GAJ-AX, 78F0536GK(A)-GAJ-AX, 78F0537GK(A)-GAJ-AX * PD78F0531GK(A2)-GAJ-AX, 78F0532GK(A2)-GAJ-AX, 78F0533GK(A2)-GAJ-AX, 78F0534GK(A2)-GAJ-AX, 78F0535GK(A2)-GAJ-AX, 78F0536GK(A2)-GAJ-AX, 78F0537GK(A2)-GAJ-AX * PD78F0531AGK-GAJ-AX, 78F0532AGK-GAJ-AX, 78F0533AGK-GAJ-AX, 78F0534AGK-GAJ-AX, 78F0535AGK-GAJ-AX, 78F0536AGK-GAJ-AX, 78F0537AGK-GAJ-AX, 78F0537DAGK-GAJ-AX * PD78F0531AGKA-GAJ-G, 78F0532AGKA-GAJ-G, 78F0533AGKA-GAJ-G, 78F0534AGKA-GAJ-G, 78F0535AGKAGAJ-G, 78F0536AGKA-GAJ-G, 78F0537AGKA-GAJ-G * PD78F0531AGKA2-GAJ-G, 78F0532AGKA2-GAJ-G, 78F0533AGKA2-GAJ-G, 78F0534AGKA2-GAJ-G, 78F0535AGKA2-GAJ-G, 78F0536AGKA2-GAJ-G, 78F0537AGKA2-GAJ-G 64-PIN PLASTIC LQFP (12x12) HD D detail of lead end 48 33 49 32 A3 c E L Lp HE L1 (UNIT:mm) 64 17 1 16 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.30 +0.08 -0.04 c 0.125 +0.75 -0.25 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD ZE 1.125 1.125 P64GK-65-GAJ 903 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531GA-9EV-A, 78F0532GA-9EV-A, 78F0533GA-9EV-A, 78F0534GA-9EV-A, 78F0535GA-9EV-A, 78F0536GA-9EV-A, 78F0537GA-9EV-A, 78F0537DGA-9EV-A 64-PIN PLASTIC TQFP (FINE PITCH) (7x7) HD D detail of lead end 33 32 48 49 A3 c E L HE Lp L1 64 17 16 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.20 MAX. A1 0.100.05 A2 1.000.05 A3 b S c L y S NOTE Each lead centerline is located within 0.07 mm of its true position at maximum material condition. A1 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.40 x 0.07 y 0.08 ZD 0.50 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 0.180.05 0.145 +0.055 -0.045 0.50 0.50 P64GA-40-9EV-1 904 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531AGA-HAB-AX, 78F0532AGA-HAB-AX, 78F0533AGA-HAB-AX, 78F0534AGA-HAB-AX, 78F0535AGA-HAB-AX, 78F0536AGA-HAB-AX, 78F0537AGA-HAB-AX, 78F0537DAGA-HAB-AX 64-PIN PLASTIC TQFP (FINE PITCH) (7x7) HD D detail of lead end 48 A3 33 49 c 32 L Lp E L1 HE (UNIT:mm) 64 17 1 16 ZE e ZD b x M A S A2 S y S NOTE Each lead centerline is located within 0.07mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.20 MAX. A1 0.100.05 A2 1.000.05 A3 0.25 b +0.07 0.16 -0.03 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.40 x 0.07 y 0.08 ZD 0.50 ZE 0.50 P64GA-40-HAB 905 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531FC-AA1-A, 78F0532FC-AA1-A, 78F0533FC-AA1-A, 78F0534FC-AA1-A, 78F0535FC-AA1-A, 78F0536FCAA1-A, 78F0537FC-AA1-A, 78F0537DFC-AA1-A * PD78F0531AFC-AA1-A, 78F0532AFC-AA1-A, 78F0533AFC-AA1-A, 78F0534AFC-AA1-A, 78F0535AFC-AA1-A, 78F0536AFC-AA1-A, 78F0537AFC-AA1-A, 78F0537DAFC-AA1-A 64-PIN PLASTIC FLGA(5x5) x 60x b M S AB A ZE w S A D e ZD 8 7 6 5 3.90 4 3 2 1 B E C D H G F E D C B A y1 S E 3.90 w S B INDEX MARK A S y DETAIL OF C PART S DETAIL OF D PART DETAIL OF E PART R0.170.05 0.700.05 0.550.05 R0.120.05 0.75 0.55 R0.170.05 0.700.05 R0.120.05 0.550.05 0.75 0.55 b (Land pad) 0.340.05 (Aperture of solder resist) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.55 0.75 0.550.05 0.700.05 0.55 0.75 0.550.05 0.700.05 R0.2750.05 R0.350.05 (UNIT:mm) ITEM D DIMENSIONS 5.000.10 E 5.000.10 w 0.20 e 0.50 A 0.910.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 P64FC-50-AA1-1 906 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0531AF1-AA2-A, 78F0532AF1-AA2-A, 78F0533AF1-AA2-A, 78F0534AF1-AA2-A, 78F0535AF1-AA2-A, 78F0536AF1-AA2-A, 78F0537AF1-AA2-A, 78F0537DAF1-AA2-A 64-PIN PLASTIC FBGA (4x4) w D S A ZE ZD A 8 7 6 B 5 4 E 3 2 1 H G F E D C B A INDEX MARK w S B INDEX MARK A y1 A2 S (UNIT:mm) S y e S b x M A1 S A B ITEM D DIMENSIONS E 4.000.10 w 0.15 A 0.890.10 A1 0.20 0.05 A2 0.69 e 0.40 b 0.25 0.05 x 0.05 y 0.08 y1 0.20 ZD 0.60 ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 4.000.10 0.60 P64F1-40-AA2 907 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS 34.5 78K0/KF2 * PD78F0544GC-UBT-A, 78F0545GC-UBT-A, 78F0546GC-UBT-A, 78F0547GC-UBT-A, 78F0547DGC-UBT-A 80-PIN PLASTIC LQFP(14x14) HD D detail of lead end 60 61 A3 41 40 c E L Lp HE L1 80 1 21 20 (UNIT:mm) ZE e ZD b x M S A A2 S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. A1 DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 S y ITEM D 0.320.06 c 0.17 +0.03 -0.06 L 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD ZE R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 0.25 b 0.825 0.825 P80GC-65-UBT 908 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0544GC(A)-GAD-AX, 78F0545GC(A)-GAD-AX, 78F0546GC(A)-GAD-AX, 78F0547GC(A)-GAD-AX * PD78F0544GC(A2)-GAD-AX, 78F0545GC(A2)-GAD-AX, 78F0546GC(A2)-GAD-AX, 78F0547GC(A2)-GAD-AX * PD78F0544AGC-GAD-AX, 78F0545AGC-GAD-AX, 78F0546AGC-GAD-AX, 78F0547AGC-GAD-AX, 78F0547DAGCGAD-AX * PD78F0544AGCA-GAD-G, 78F0545AGCA-GAD-G, 78F0546AGCA-GAD-G, 78F0547AGCA-GAD-G * PD78F0544AGCA2-GAD-G, 78F0545AGCA2-GAD-G, 78F0546AGCA2-GAD-G, 78F0547AGCA2-GAD-G 80-PIN PLASTIC LQFP(14x14) HD D detail of lead end 60 61 A3 41 40 c E L Lp HE L1 (UNIT:mm) 80 1 21 20 ZE e ZD b x M S ITEM D DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 A b A2 c S y S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 L 0.25 +0.08 0.30 -0.04 0.125 +0.075 -0.025 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD ZE 0.825 0.825 P80GC-65-GAD 909 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0544GK-8EU-A, 78F0545GK-8EU-A, 78F0546GK-8EU-A, 78F0547GK-8EU-A, 78F0547DGK-8EU-A 80-PIN PLASTIC LQFP(FINE PITCH)(12x12) HD D detail of lead end 41 60 61 A3 40 c E L Lp HE L1 (UNIT:mm) 21 80 1 20 ZE e ZD b x M S A ITEM D DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 A1 L 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P80GK-50-8EU-1 910 78K0/Kx2 CHAPTER 34 PACKAGE DRAWINGS * PD78F0544GK(A)-GAK-AX, 78F0545GK(A)-GAK-AX, 78F0546GK(A)-GAK-AX, 78F0547GK(A)-GAK-AX * PD78F0544GK(A2)-GAK-AX, 78F0545GK(A2)-GAK-AX, 78F0546GK(A2)-GAK-AX, 78F0547GK(A2)-GAK-AX * PD78F0544AGK-GAK-AX, 78F0545AGK-GAK-AX, 78F0546AGK-GAK-AX, 78F0547AGK-GAK-AX, 78F0547DAGK-GAK-AX * PD78F0544AGKA-GAK-G, 78F0545AGKA-GAK-G, 78F0546AGKA-GAK-G, 78F0547AGKA-GAK-G * PD78F0544AGKA2-GAK-G, 78F0545AGKA2-GAK-G, 78F0546AGKA2-GAK-G, 78F0547AGKA2-GAK-G 80-PIN PLASTIC LQFP(FINE PITCH)(12x12) HD detail of lead end D 60 A3 41 c 61 40 L Lp E L1 HE (UNIT:mm) 21 80 1 20 ZE e ZD b x M S A2 S S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 +0.07 0.20 -0.03 b A y ITEM D A1 c 0.125 +0.075 -0.025 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P80GK-50-GAK 911 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www2.renesas.com/pkg/en/mount/index.html) Table 35-1. Soldering Conditions of Conventional-specification Products (PD78F05xx and 78F05xxD) (1/3) (1) 36-pin plastic FLGA (4x4) PD78F050xFC-AA3-A (x = 0 to 3), 78F0503DFC-AA3-A 64-pin plastic FLGA (5x5) PD78F053xFC-AA1-A (x = 1 to 7), 78F0537DFC-AA1-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 20 to 72 hours) Note IR60-207-3 (after that, prebake at 125C for After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution The PD78F05xxD has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 912 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Table 35-1. Soldering Conditions of Conventional-specification Products (PD78F05xx and 78F05xxD) (2/3) (2) 30-pin plastic SSOP (7.62 mm (300)) PD78F050xMC-5A4-A (x = 0 to 3), 78F0503DMC-5A4-A 44-pin plastic LQFP (10x10) PD78F051xGB-UES-A (x = 1 to 3), 78F0513DGB-UES-A 48-pin plastic LQFP (fine pitch) (7x7) PD78F051xGA-8EU-A (x = 1 to 5), 78F0515DGA-8EU-A PD78F051xGA(A)-GAM-AX (x = 1 to 5), 78F051xGA(A2)-GAM-AX (x = 1 to 5) 52-pin plastic LQFP (10x10) PD78F052xGB-UET-A (x = 1 to 7), 78F0527DGB-UET-A 64-pin plastic LQFP (fine pitch) (10x10) PD78F053xGB-UEU-A (x = 1 to 7), 78F0537DGB-UEU-A PD78F053xGB(A)-GAH-AX (x = 1 to 7), 78F053xGB(A2)-GAH-AX (x = 1 to 7) 64-pin plastic LQFP (14x14) PD78F053xGC-UBS-A (x = 1 to 7), 78F0537DGC-UBS-A 64-pin plastic LQFP (12x12) PD78F053xGK-UET-A (x = 1 to 7), 78F0537DGK-UET-A 64-pin plastic TQFP (fine pitch) (7x7) PD78F053xGA-9EV-A (x = 1 to 7), 78F0537DGA-9EV-A 80-pin plastic LQFP (14x14) PD78F054xGC-UBT-A (x = 4 to 7), 78F0547DGC-UBT-A 80-pin plastic LQFP (fine pitch) (12x12) PD78F054xGK-8EU-A (x = 4 to 7), 78F0547DGK-8EU-A PD78F054xGK(A)-GAK-AX (x = 4 to 7), 78F054xGK(A2)-GAK-AX (x = 4 to 7) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 20 to 72 hours) Partial heating Note Recommended Condition Symbol IR60-207-3 (after that, prebake at 125C for Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution The PD78F05xxD has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 913 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Table 35-1. Soldering Conditions of Conventional-specification Products (PD78F05xx and 78F05xxD) (3/3) (3) 30-pin plastic SSOP (7.62 mm (300)) PD78F050xMC(A)-CAB-AX (x = 0 to 3), 78F050xMC(A2)-CAB-AX (x = 0 to 3) 44-pin plastic LQFP (10x10) PD78F051xGB(A)-GAF-AX (x = 1 to 3), 78F051xGB(A2)-GAF-AX (x = 1 to 3) 52-pin plastic LQFP (10x10) PD78F052xGB(A)-GAG-AX (x = 1 to 7), 78F052xGB(A2)-GAG-AX (x = 1 to 7) 64-pin plastic LQFP (14x14) PD78F053xGC(A)-GAL-AX (x = 1 to 7), 78F053xGC(A2)-GAL-AX (x = 1 to 7) 64-pin plastic LQFP (12x12) PD78F053xGK(A)-GAJ-AX (x = 1 to 7), 78F053xGK(A2)-GAJ-AX (x = 1 to 7) 80-pin plastic LQFP (14x14) PD78F054xGC(A)-GAD-AX (x = 4 to 7), 78F054xGC(A2)-GAD-AX (x = 4 to 7) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 20 to 72 hours) Wave soldering IR60-207-3 (after that, prebake at 125C for Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-207-1 Preheating temperature: 120C max. (package surface temperature), Note Exposure limit: 7 days (after that, prebake at 125C for 20 to 72 hours) Partial heating Note Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 914 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Table 35-2. Soldering Conditions of Expanded-specification products (PD78F05xxA and 78F05xxDA) (1/2) (1) 36-pin plastic FLGA (4x4) PD78F050xAFC-AA3-A (x = 0 to 3), 78F0503DAFC-AA3-A 64-pin plastic FLGA (5x5) PD78F053xAFC-AA1-A (x = 1 to 7), 78F0537DAFC-AA1-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 10 to 72 hours) IR60-107-3 (after that, prebake at 125C for (2) 48-pin plastic LQFP (fine pitch) (7x7) PD78F051xAGA-GAM-AX (x = 1 to 5), 78F0515DAGA-GAM-AX PD78F051xAGAA-GAM-G (x = 1 to 5), 78F051xAGAA2-GAM-G (x = 1 to 5) 64-pin plastic LQFP (fine pitch) (10x10) PD78F053xAGB-GAH-AX (x = 1 to 7), 78F0537DAGB-GAH-AX PD78F053xAGBA-GAH-G (x = 1 to 7), 78F053xAGBA2-GAH-G (x = 1 to 7) 80-pin plastic LQFP (fine pitch) (12x12) PD78F054xAGK-GAK-AX (x = 4 to 7), 78F0547DAGK-GAK-AX PD78F054xAGKA-GAK-G (x = 4 to 7), 78F054xAGKA2-GAK-G (x = 4 to 7) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 10 to 72 hours) Partial heating Note IR60-107-3 (after that, prebake at 125C for Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution The PD78F05xxDA has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 915 78K0/Kx2 CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS Table 35-2. Soldering Conditions of Expanded-specification products (PD78F05xxA and 78F05xxDA) (2/2) (3) 30-pin plastic SSOP (7.62 mm (300)) PD78F050xAMC-CAB-AX (x = 0 to 3), 78F0503DAMC-CAB-AX PD78F050xAMCA-CAB-G (x = 0 to 3), 78F050xAMCA2-CAB-G (x = 0 to 3) 38-pin plastic SSOP (7.62 mm (300)) PD78F051xAMC-GAA-AX (x = 1 to 3), 78F0513DAMC-GAA-AX PD78F051xAMCA-GAA-G (x = 1 to 3), 78F051xAMCA2-GAA-G (x = 1 to 3) 44-pin plastic LQFP (10x10) PD78F051xAGB-GAF-AX (x = 1 to 3), 78F0513DAGB-GAF-AX PD78F05x1AGBA-GAF-G (x = 1 to 3), 78F051xAGBA2-GAF-G (x = 1 to 3) 52-pin plastic LQFP (10x10) PD78F052xAGB-GAG-AX (x = 1 to 7), 78F0527DAGB-GAG-AX PD78F052xAGBA-GAG-G (x = 1 to 7), 78F052xAGBA2-GAG-G (x = 1 to 7) 64-pin plastic LQFP (14x14) PD78F053xAGC-GAL-AX (x = 1 to 7), 78F0537DAGC-GAL-AX PD78F053xAGCA-GAL-G (x = 1 to 7), 78F053xAGCA2-GAL-G (x = 1 to 7) 64-pin plastic LQFP (12x12) PD78F053xAGK-GAJ-AX (x = 1 to 7), 78F0537DAGK-GAJ-AX PD78F053xAGKA-GAJ-G (x = 1 to 7), 78F053xAGKA2-GAJ-G (x = 1 to 7) 80-pin plastic LQFP (14x14) PD78F054xAGC-GAD-G (x = 4 to 7), 78F0547DAGC-GAD-AX PD78F054xAGCA-GAD-G (x = 4 to 7), 78F054xAGCA2-GAD-G (x = 4 to 7) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 10 to 72 hours) Wave soldering IR60-107-3 (after that, prebake at 125C for Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-107-1 Preheating temperature: 120C max. (package surface temperature), Note Exposure limit: 7 days (after that, prebake at 125C for 10 to 72 hours) Partial heating Note Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Cautions 1. Do not use different soldering methods together (except for partial heating). 2. The PD78F05xxDA has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 916 78K0/Kx2 CHAPTER 36 CAUTIONS FOR WAIT CHAPTER 36 CAUTIONS FOR WAIT 36.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Tables 36-1 and 36-2). This must be noted when real-time processing is performed. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 917 78K0/Kx2 CHAPTER 36 CAUTIONS FOR WAIT 36.2 Peripheral Hardware That Generates Wait Table 36-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks and Table 36-2 lists the RAM accesses that issue a wait request and the number of CPU wait clocks. Table 36-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access Number of Wait Clocks Hardware Serial interface ASIS0 Read 1 clock (fixed) ASIS6 Read 1 clock (fixed) IICS0 Read 1 clock (fixed) ADM Write 1 to 5 clocks (when fAD = fPRS/2 is selected) ADS Write 1 to 7 clocks (when fAD = fPRS/3 is selected) ADPC Write ADCR Read UART0 Serial interface UART6 Serial interface IIC0 A/D converter 1 to 9 clocks (when fAD = fPRS/4 is selected) 2 to 13 clocks (when fAD = fPRS/6 is selected) 2 to 17 clocks (when fAD = fPRS/8 is selected) 2 to 25 clocks (when fAD = fPRS/12 is selected) The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait clocks can be calculated by the following expression and under the following conditions. <Calculating number of wait clocks> 2 fCPU +1 * Number of wait clocks = fAD * Fraction is truncated if the number of wait clocks 0.5 and rounded up if the number of wait clocks > 0.5. fAD: A/D conversion clock frequency (fPRS/2 to fPRS/12) fCPU: CPU clock frequency fPRS: Peripheral hardware clock frequency fXP: Main system clock frequency <Conditions for maximum/minimum number of wait clocks> * Maximum number of times: Maximum speed of CPU (fXP), lowest speed of A/D conversion clock (fPRS/12) * Minimum number of times: Minimum speed of CPU (fSUB/2), highest speed of A/D conversion clock (fPRS/2) Caution When the peripheral hardware clock (fPRS) is stopped, do not access the registers listed above using an access method in which a wait request is issued. Remark The clock is the CPU clock (fCPU). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 918 78K0/Kx2 CHAPTER 36 CAUTIONS FOR WAIT Table 36-2. RAM Accesses That Generate Wait and Number of CPU Wait Clocks (78K0/KF2 only) Area Buffer RAM Access Write Number of Wait Clocks Note 1 to 81 clocks <Calculating maximum number of wait clocks> * Maximum number of wait clocks = 5 fCPU +1 fW * Fraction is truncated if the number of wait clocks multiplied by (1/fCPU) is equal or lower than tCPUL and rounded up if higher than tCPUL. fW: Frequency of base clock selected by CKS00 bit of CSIS0 register (CKS00 = 0: fPRS, CKS00 = 1: fPRS/2) fCPU: CPU clock frequency tCPUL: CPU clock low-level width fPRS: Peripheral hardware clock frequency Note No waits are generated when five CSIA0 operating clocks or more are inserted between writing to the RAM from the CSIA0 and writing to the buffer RAM from the CPU. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 919 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/Kx2 microcontrollers. Figure A-1 shows the development tool configuration. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 920 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator QB-78K0KX2 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 Power supply unit QB-78K0KX2Note 4 < Flash memory write environment > Flash memory programmerNote 4 Off-board programming Emulation probe On-board programming Conversion adapter Flash memory write adapter 78K0/Kx2 microcontroller Target connector Target system Notes 1. Download the device file for 78K0/Kx2 microcontrollers (DF780547) and the integrated debugger ID78K0QB from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). 2. SM+ for 78K0 (instruction simulation version) is included in the software package. SM+ for 78K0/Kx2 (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. PM+ cannot be used other than with WindowsTM. 4. QB-78K0KX2 is supplied with the integrated debugger ID78K0-QB, a USB interface cable, the on-chip debug emulator with programming function QB-MINI2, connection cables (10-pin and 16-pin cables), and the 78K0-OCD board. Any other products are sold separately. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 921 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the on-chip debug emulator with programming function QB-MINI2 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 <When using QB-MINI2 as a flash memory programmer> <When using QB-MINI2 as an on-chip degug emulator> QB-MINI2Note 4 QB-MINI2Note 4 Connection cable 78K0-OCD boardNote 4 (16-pin cable)Note 4 Connection cable (10-pin/16-pin cable)Note 4 Target connector Target system Notes 1. Download the device file for 78K0/Kx2 microcontrollers (DF780547) and the integrated debugger ID78K0QB from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). 2. SM+ for 78K0 (instruction simulation version) is included in the software package. SM+ for 78K0/Kx2 (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. PM+ cannot be used other than with Windows. 4. QB-MINI2 is supplied with USB interface cable, connection cables (10-pin cable and 16-pin cable), and 78K0-OCD board. Any other products are sold separately. In addition, download the software for operating the QB-MINI2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 922 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K0 microcontrollers are combined in this 78K0 microcontroller software package. package A.2 Language Processing Software RA78K0 Note 1 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780547). <Precaution when using RA78K0 in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. CC78K0 Note 1 This compiler converts programs written in C language into object codes executable with C compiler package a microcontroller. This compiler should be used in combination with an assembler package and device file. <Precaution when using CC78K0 in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. Note 2 DF780547 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (RA78K0, CC78K0, ID78K0QB, and the system simulator). The corresponding OS and host machine differ depending on the tool to be used. Notes 1. If the versions of RA78K0 and CC78K0 are Ver.4.00 or later, different versions of RA78K0 and CC78K0 can be installed on the same machine. 2. The DF780547 can be used in common with the RA78K0, CC78K0, ID78K0-QB, and the system simulator. Download the DF780547 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 923 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Programming Tools A.3.1 When using flash memory programmer FG-FP5, FL-PR5, FG-FP4, and FL-PR4 FG-FP5, FL-PR5, PG-FP4 Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Note 1 , FL-PR4 Flash memory programmer FA-xxxx Note 2 Flash memory programming adapter used connected to the flash memory programmer Flash memory programming adapter Notes 1. 2. for use. Phase-out The part numbers of the flash memory programming adapter and the packages of the target device are described below. Package Flash Memory Programming Adapter 78K0/KB2 30-pin plastic SSOP (MC-5A4 and MC-CAB types) FA-30MC-CAB-B, FA-78F0503MC-5A4-RX 36-pin plastic FLGA (FC-AA3 type) FA-36FC-AA3-B, FA-78F0503FC-AA3-RX 78K0/KC2 38-pin plastic SSOP (MC-GAA type) FA-38MC-GAA-B 44-pin plastic LQFP (GB-UES and GB-GAF types) FA-44GB-GAF-B, FA-78F0513GB-UES-RX 48-pin plastic LQFP (GA-8EU and GA-GAM types) FA-48GA-GAM-B, FA-78F0515GA-8EU-RX 78K0/KD2 52-pin plastic LQFP (GB-UET and GB-GAG types) FA-52GB-GAG-B, FA-78F0527GB-UET-RX 78K0/KE2 64-pin plastic LQFP (GB-UEU and GB-GAH types) FA-64GB-GAH-B, FA-78F0537GB-UEU-RX 64-pin plastic LQFP (GC-UBS and GC-GAL types) FA-64GC-GAL-B, FA-78F0537GC-UBS-RX 64-pin plastic LQFP (GK-UET and GK-GAJ types) FA-64GK-GAJ-B, FA-78F0537GK-UET-RX 64-pin plastic TQFP (GA-9EV and GA-HAB types) FA-64GA-8EV-B, FA-64GA-HAB-B, FA-78F0537GA-9EV-RX 78K0/KF2 64-pin plastic FLGA (FC-AA1 type) FA-78F0537FC-AA1-RX 80-pin plastic LQFP (GC-UBT and GC-GAD types) FA-80GC-GAD-B, FA-78F0547GC-UBT-RX 80-pin plastic LQFP (GK-8EU and GK-GAK types) FA-80GK-GAK-B, FA-78F0547GK-8EU-RX Remarks 1. FL-PR5, FL-PR4, and FA-xxxx are products of Naito Densei Machida Mfg. Co., Ltd (http://www.ndk-m.co.jp/, TEL: +81-42-750-4172). 2. Use the latest version of the flash memory programming adapter. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 924 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS A.3.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This is a flash memory programmer dedicated to microcontrollers with on-chip flash On-chip debug emulator with memory. It is available also as on-chip debug emulator which serves to debug hardware programming function and software when developing application systems using the 78K0/Kx2 microcontrollers. When using this as flash memory programmer, it should be used in combination with a connection cable (16-pin cable) and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16-pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board are used only when using the on-chip debug function. 2. Download the software for operating the QB-MINI2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0KX2 QB-78K0KX2 In-circuit emulator This in-circuit emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2 microcontrollers. It supports to the integrated debugger (ID78K0QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. QB-144-CA-01 Check pin adapter This check pin adapter is used in waveform monitoring using the oscilloscope, etc. QB-80-EP-01T Emulation probe This emulation probe is flexible type and used to connect the in-circuit emulator and target system. Note This exchange adapter is used to perform pin conversion from the in-circuit emulator to target connector. Note This space adapter is used to adjust the height between the target system and in-circuit emulator. Note This YQ connector is used to connect the target connector and exchange adapter. Note This mount adapter is used to mount the target device with socket. Note This target connector is used to mount on the target system. QB-xxxx-EA-xxx Exchange adapter QB-xxxx-YS-xxx Space adapter QB-xxxx-YQ-xxx YQ connector QB-xxxx-HQ-xxx Mount adapter QB-xxxx-NQ-xxx , Target connector (Note and Remarks are listed on the next page or later.) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 925 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS Note The part numbers of the exchange adapter, space adapter, YQ connector, mount adapter, and target connector and the packages of the target device are described below. Package Exchange Space Adapter YQ Connector Mount Adapter 78K0/KB2 Target Connector Adapter 30-pin plastic SSOP QB-30MC- QB-30MC- QB-30MC- QB-30MC- QB-30MC- (MC-5A4 and EA-02T YS-01T YQ-01T HQ-01T NQ-01T 36-pin plastic FLGA QB-36FC- None None None QB-36FC- (FC-AA3 type) EA-01T MC-CAB types) 78K0/KC2 NQ-01T 38-pin plastic SSOP QB-38MC- QB-38MC- QB-38MC- QB-38MC- QB-38MC- (MC-GAA type) EA-01T YQ-01T YQ-01T HQ-01T NQ-01T 44-pin plastic LQFP QB-44GB- QB-44GB- QB-44GB- QB-44GB- QB-44GB- (GB-UES and GB- EA-03T YS-01T YQ-01T HQ-01T NQ-01T 48-pin plastic LQFP QB-48GA- QB-48GA- QB-48GA- QB-48GA- QB-48GA- (GA-8EU and GA- EA-02T YS-01T YQ-01T HQ-01T NQ-01T 52-pin plastic LQFP QB-52GB- QB-52GB- QB-52GB- QB-52GB- QB-52GB- (GB-UET and GB- EA-02T YS-01T YQ-01T HQ-01T NQ-01T 64-pin plastic LQFP QB-64GB- QB-64GB- QB-64GB- QB-64GB- QB-64GB- (GB-UEU and GB- EA-04T YS-01T YQ-01T HQ-01T NQ-01T 64-pin plastic LQFP QB-64GC- QB-64GC- QB-64GC- QB-64GC- QB-64GC- (GC-UBS and GC- EA-03T YS-01T YQ-01T HQ-01T NQ-01T 64-pin plastic LQFP QB-64GK- QB-64GK- QB-64GK- QB-64GK- QB-64GK- (GK-UET and GK- EA-04T YS-01T YQ-01T HQ-01T NQ-01T 64-pin plastic TQFP QB-64GA- QB-64GA- QB-64GA- QB-64GA- QB-64GA- (GA-9EV and GA- EA-01T YS-01T YQ-01T HQ-01T NQ-01T 64-pin plastic FLGA QB-64FC- None None None QB-64FC- (FC-AA1 type) EA-01T 80-pin plastic LQFP QB-80GC- QB-80GC- QB-80GC- QB-80GC- QB-80GC- (GC-UBT and GC- EA-01T YS-01T YQ-01T HQ-01T NQ-01T 80-pin plastic LQFP QB-80GK- QB-80GK- QB-80GK- QB-80GK- QB-80GK- (GK-8EU and GK- EA-01T YS-01T YQ-01T HQ-01T NQ-01T GAF types) GAM types) 78K0/KD2 GAG types) 78K0/KE2 GAH types) GAL types) GAJ types) HAB types) 78K0/KF2 NQ-01T GAD types) GAK type) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 926 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS Remarks 1. The QB-78K0KX2 is supplied with the integrated debugger ID78K0-QB, a USB interface cable, the onchip debug emulator QB-MINI2, connection cables (10-pin and 16-pin cables), and the 78K0-OCD board. Download the software for operating the QB-MINI2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html) when using the QB-MINI2. 2. The packed contents of QB-78K0KX2 differ depending on the part number, as follows. Packed Contents In-Circuit Emulator Emulation Probe Exchange Adapter YQ Connector Target Connector QB-30MC-EA-02T QB-30MC-YQ-01T QB-30MC-NQ-01T QB-78K0KX2-T36FC QB-36FC-EA-01T None QB-36FC-NQ-01T QB-78K0KX2-T38MC QB-38MC-EA-01T QB-38MC-YQ-01T QB-38MC-NQ-01T QB-78K0KX2-T44GB QB-44GB-EA-03T QB-44GB-YQ-01T QB-44GB-NQ-01T QB-78K0KX2-T48GA QB-48GA-EA-02T QB-48GA-YQ-01T QB-48GA-NQ-01T QB-78K0KX2-T52GB QB-52GB-EA-02T QB-52GB-YQ-01T QB-52GB-NQ-01T Part Number QB-78K0KX2-ZZZ QB-78K0KX2 QB-78K0KX2-T30MC None QB-80-EP-01T QB-78K0KX2-T64GB QB-64GB-EA-04T QB-64GB-YQ-01T QB-64GB-NQ-01T QB-78K0KX2-T64GC QB-64GC-EA-03T QB-64GC-YQ-01T QB-64GC-NQ-01T QB-78K0KX2-T64GK QB-64GK-EA-04T QB-64GK-YQ-01T QB-64GK-NQ-01T QB-78K0KX2-T64GA QB-64GA-EA-01T QB-64GA-YQ-01T QB-64GA-NQ-01T QB-78K0KX2-T64FC QB-64FC-EA-01T None QB-64FC-NQ-01T QB-78K0KX2-T80GC QB-80GC-EA-01T QB-80GC-YQ-01T QB-80GC-NQ-01T QB-78K0KX2-T80GK QB-80GK-EA-01T QB-80GK-YQ-01T QB-80GK-NQ-01T Note Under development A.4.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This on-chip debug emulator serves to debug hardware and software when developing On-chip debug emulator with application systems using the 78K0/Kx2. It is available also as flash memory programming function programmer dedicated to microcontrollers with on-chip flash memory. When using this as on-chip debug emulator, it should be used in combination with a connection cable (10pin cable or 16-pin cable), a USB interface cable that is used to connect the host machine, and the 78K0-OCD board. Target connector specifications 10-pin general-purpose connector (2.54 mm pitch) or 16-pin general-purpose connector (2.54 mm pitch) Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16-pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board are used only when using the on-chip debug function. 2. Download the software for operating the QB-MINI2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 927 78K0/Kx2 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) ID78K0-QB Note Integrated debugger This debugger supports the in-circuit emulators for the 78K0 microcontrollers. The ID78K0-QB is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (DF780547). SM+ for 78K0 System simulator is Windows-based software. SM+ for 78K0/Kx2 It is used to perform debugging at the C source level or assembler level while simulating System simulator the operation of the target system on a host machine. Use of system simulator allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. System simulator should be used in combination with the device file (DF780547). The following two types of system simulators supporting the 78K0/Kx2 microcontrollers are available. * SM+ for 78K0 (instruction simulation version) This can only simulate a CPU. It is included in the software package. * SM+ for 78K0/ Kx2 (instruction + peripheral simulation version) This can simulate a CPU and peripheral hardware (ports, timers, serial interfaces, etc.). It is sold separately from the software package. Note Download the ID78K0-QB from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 928 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX B NOTES ON TARGET SYSTEM DESIGN This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0KX2 is used. 12.5 13.375 11.5 10 11.5 10 Figure B-1. For 30-Pin MC Package 12.5 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 929 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 3.5 3.5 Figure B-2. For 36-Pin FC Package 3 4 21.8 : Exchange adapter area: Components up to 2.5 mm in height can be mounted : Emulation probe tip area: Components up to 4.5 mm in height can be mounted 15 13.375 9.85 10 10 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mounted Note Note 9.85 Figure B-3. For 44-Pin GB Package Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 930 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 15 10 15 13.375 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mounted Note Note 10 9.5 9.5 Figure B-4. For 48-Pin GA Package Height can be adjusted by using space adapters (each adds 2.4 mm) 15 13.375 9.85 10 9.85 10 Figure B-5. For 52-Pin GB Package 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 931 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 3.5 3.5 Figure B-6. For 64-Pin FC Package 3 4 21.8 : Exchange adapter area (connector part): Components up to 2.45 mm in height can be mounted : Exchange adapter area (probe part): Components up to 4.5 mm in height can be mounted 15 13.375 9.5 10 9.5 10 Figure B-7. For 64-Pin GA Package 15 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 932 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 15 10 15 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 10 10.5 10.5 Figure B-8. For 64-Pin GB Package Height can be adjusted by using space adapters (each adds 2.4 mm) 15 13.375 11.85 10 10 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 11.85 Figure B-9. For 64-Pin GC Package Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 933 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 15 10.5 10 10 15 13.375 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 10.5 Figure B-10. For 64-Pin GK Package Height can be adjusted by using space adapters (each adds 2.4 mm) 15 13.375 12.05 10 10 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 12.05 Figure B-11. For 80-Pin GC Package Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 934 78K0/Kx2 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 15 13.375 10.5 10 10 15 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 10.5 Figure B-12. For 80-Pin GK Package Height can be adjusted by using space adapters (each adds 2.4 mm) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 935 78K0/Kx2 APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D converter mode register (ADM) ........................................................................................................................... 412 A/D port configuration register (ADPC) .............................................................................................................. 219, 419 Analog input channel specification register (ADS)...................................................................................................... 418 Asynchronous serial interface control register 6 (ASICL6) ......................................................................................... 466 Asynchronous serial interface operation mode register 0 (ASIM0)............................................................................. 436 Asynchronous serial interface operation mode register 6 (ASIM6)............................................................................. 460 Asynchronous serial interface reception error status register 0 (ASIS0) .................................................................... 438 Asynchronous serial interface reception error status register 6 (ASIS6) .................................................................... 462 Asynchronous serial interface transmission status register 6 (ASIF6)........................................................................ 463 Automatic data transfer address count register 0 (ADTC0)........................................................................................ 523 Automatic data transfer address point specification register 0 (ADTP0) .................................................................... 521 Automatic data transfer interval specification register 0 (ADTI0)................................................................................ 522 [B] Baud rate generator control register 0 (BRGC0) ........................................................................................................ 439 Baud rate generator control register 6 (BRGC6) ........................................................................................................ 465 [C] Capture/compare control register 00 (CRC00) ........................................................................................................... 280 Capture/compare control register 01 (CRC01) ........................................................................................................... 280 Clock operation mode select register (OSCCTL) ....................................................................................................... 229 Clock output selection register (CKS)......................................................................................................................... 404 Clock selection register 6 (CKSR6) ............................................................................................................................ 463 [D] Divisor selection register 0 (BRGCA0) ....................................................................................................................... 520 [E] 8-bit A/D conversion result register (ADCRH) ............................................................................................................ 417 8-bit timer compare register 50 (CR50) ...................................................................................................................... 347 8-bit timer compare register 51 (CR51) ...................................................................................................................... 347 8-bit timer counter 50 (TM50) ..................................................................................................................................... 347 8-bit timer counter 51 (TM51) ..................................................................................................................................... 347 8-bit timer H carrier control register 1 (TMCYC1) ....................................................................................................... 371 8-bit timer H compare register 00 (CMP00)................................................................................................................ 366 8-bit timer H compare register 01 (CMP01)................................................................................................................ 366 8-bit timer H compare register 10 (CMP10)................................................................................................................ 366 8-bit timer H compare register 11 (CMP11)................................................................................................................ 366 8-bit timer H mode register 0 (TMHMD0) ................................................................................................................... 367 8-bit timer H mode register 1 (TMHMD1) ................................................................................................................... 367 8-bit timer mode control register 50 (TMC50)............................................................................................................. 351 8-bit timer mode control register 51 (TMC51)............................................................................................................. 351 External interrupt falling edge enable register (EGN) ................................................................................................. 652 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 936 78K0/Kx2 APPENDIX C REGISTER INDEX External interrupt rising edge enable register (EGP) .................................................................................................. 652 [I] IIC clock selection register 0 (IICCL0) ........................................................................................................................ 565 IIC control register 0 (IICC0) ...................................................................................................................................... 556 IIC flag register 0 (IICF0)............................................................................................................................................ 563 IIC function expansion register 0 (IICX0).................................................................................................................... 566 IIC shift register 0 (IIC0) ............................................................................................................................................. 553 IIC status register 0 (IICS0)........................................................................................................................................ 561 Input switch control register (ISC) .............................................................................................................................. 468 Internal expansion RAM size switching register (IXS) ................................................................................................ 722 Internal memory size switching register (IMS)............................................................................................................ 721 Internal oscillation mode register (RCM) .................................................................................................................... 235 Interrupt mask flag register 0H (MK0H)...................................................................................................................... 643 Interrupt mask flag register 0L (MK0L) ....................................................................................................................... 643 Interrupt mask flag register 1H (MK1H)...................................................................................................................... 643 Interrupt mask flag register 1L (MK1L) ....................................................................................................................... 643 Interrupt request flag register 0H (IF0H)..................................................................................................................... 637 Interrupt request flag register 0L (IF0L)...................................................................................................................... 637 Interrupt request flag register 1H (IF1H)..................................................................................................................... 637 Interrupt request flag register 1L (IF1L)...................................................................................................................... 637 [K] Key return mode register (KRM)................................................................................................................................. 665 [L] Low-voltage detection level selection register (LVIS) ................................................................................................. 701 Low-voltage detection register (LVIM)........................................................................................................................ 699 [M] Main clock mode register (MCM)................................................................................................................................ 237 Main OSC control register (MOC) .............................................................................................................................. 236 Memory Bank Select Register (BANK)....................................................................................................................... 150 Multiplication/division data register A0 (MDA0H, MDA0L).......................................................................................... 623 Multiplication/division data register B0 (MDB0) .......................................................................................................... 624 Multiplier/divider control register 0 (DMUC0).............................................................................................................. 625 [O] Oscillation stabilization time counter status register (OSTC).............................................................................. 238, 667 Oscillation stabilization time select register (OSTS) ........................................................................................... 239, 668 [P] Port mode register 0 (PM0) ........................................................................................................................ 205, 288, 498 Port mode register 1 (PM1) .................................................................................................205, 353, 372, 440, 468, 498 Port mode register 2 (PM2) ................................................................................................................................ 205, 420 Port mode register 3 (PM3) ................................................................................................................................ 205, 353 Port mode register 4 (PM4) ........................................................................................................................................ 205 Port mode register 5 (PM5) ........................................................................................................................................ 205 Port mode register 6 (PM6) ................................................................................................................................ 205, 568 Port mode register 7 (PM7) ........................................................................................................................................ 205 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 937 78K0/Kx2 APPENDIX C REGISTER INDEX Port mode register 12 (PM12) ............................................................................................................................ 205, 702 Port mode register 14 (PM14) .................................................................................................................... 205, 407, 523 Port register 0 (P0) ..................................................................................................................................................... 210 Port register 1 (P1) ..................................................................................................................................................... 210 Port register 2 (P2) ..................................................................................................................................................... 210 Port register 3 (P3) ..................................................................................................................................................... 210 Port register 4 (P4) ..................................................................................................................................................... 210 Port register 5 (P5) ..................................................................................................................................................... 210 Port register 6 (P6) ..................................................................................................................................................... 210 Port register 7 (P7) ..................................................................................................................................................... 210 Port register 12 (P12) ................................................................................................................................................. 210 Port register 13 (P13) ................................................................................................................................................. 210 Port register 14 (P14) ................................................................................................................................................. 210 Prescaler mode register 00 (PRM00) ......................................................................................................................... 285 Prescaler mode register 01 (PRM01) ......................................................................................................................... 285 Priority specification flag register 0H (PR0H) ............................................................................................................. 648 Priority specification flag register 0L (PR0L) .............................................................................................................. 648 Priority specification flag register 1H (PR1H) ............................................................................................................. 648 Priority specification flag register 1L (PR1L) .............................................................................................................. 648 Processor clock control register (PCC) ...................................................................................................................... 232 Pull-up resistor option register 0 (PU0) ...................................................................................................................... 215 Pull-up resistor option register 1 (PU1) ...................................................................................................................... 215 Pull-up resistor option register 3 (PU3) ...................................................................................................................... 215 Pull-up resistor option register 4 (PU4) ...................................................................................................................... 215 Pull-up resistor option register 5 (PU5) ...................................................................................................................... 215 Pull-up resistor option register 6 (PU6) ...................................................................................................................... 215 Pull-up resistor option register 7 (PU7) ...................................................................................................................... 215 Pull-up resistor option register 12 (PU12) .................................................................................................................. 215 Pull-up resistor option register 14 (PU14) .................................................................................................................. 215 [R] Receive buffer register 0 (RXB0)................................................................................................................................ 435 Receive buffer register 6 (RXB6)................................................................................................................................ 459 Receive shift register 0 (RXS0) .................................................................................................................................. 435 Receive shift register 6 (RXS6) .................................................................................................................................. 459 Remainder data register 0 (SDR0) ............................................................................................................................. 623 Reset control flag register (RESF).............................................................................................................................. 691 [S] Serial clock selection register 10 (CSIC10) ................................................................................................................ 495 Serial clock selection register 11 (CSIC11) ................................................................................................................ 495 Serial I/O shift register 0 (SIOA0) ............................................................................................................................... 515 Serial I/O shift register 10 (SIO10) ............................................................................................................................. 492 Serial I/O shift register 11 (SIO11) ............................................................................................................................. 492 Serial operation mode register 10 (CSIM10) .............................................................................................................. 493 Serial operation mode register 11 (CSIM11) .............................................................................................................. 493 Serial operation mode specification register 0 (CSIMA0) ........................................................................................... 515 Serial status register 0 (CSIS0) .................................................................................................................................. 517 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 938 78K0/Kx2 APPENDIX C REGISTER INDEX Serial trigger register 0 (CSIT0).................................................................................................................................. 519 Slave address register 0 (SVA0) ................................................................................................................................ 553 16-bit timer capture/compare register 000 (CR000) ................................................................................................... 273 16-bit timer capture/compare register 001 (CR001) ................................................................................................... 273 16-bit timer capture/compare register 010 (CR010) ................................................................................................... 273 16-bit timer capture/compare register 011 (CR011) ................................................................................................... 273 16-bit timer counter 00 (TM00) ................................................................................................................................... 272 16-bit timer counter 01 (TM00) ................................................................................................................................... 272 16-bit timer mode control register 00 (TMC00)........................................................................................................... 277 16-bit timer mode control register 01 (TMC01)........................................................................................................... 277 16-bit timer output control register 00 (TOC00) .......................................................................................................... 282 16-bit timer output control register 01 (TOC01) .......................................................................................................... 282 [T] Timer clock selection register 50 (TCL50).................................................................................................................. 348 Timer clock selection register 51 (TCL51).................................................................................................................. 348 10-bit A/D conversion result register (ADCR) ............................................................................................................. 416 Transmit buffer register 10 (SOTB10) ........................................................................................................................ 492 Transmit buffer register 11 (SOTB11) ........................................................................................................................ 492 Transmit buffer register 6 (TXB6) ............................................................................................................................... 459 Transmit shift register 0 (TXS0).................................................................................................................................. 435 Transmit shift register 6 (TXS6).................................................................................................................................. 459 [W] Watch timer operation mode register (WTM) ............................................................................................................. 391 Watchdog timer enable register (WDTE).................................................................................................................... 398 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 939 78K0/Kx2 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: 10-bit A/D conversion result register....................................................................................................... 416 ADCRH: 8-bit A/D conversion result register......................................................................................................... 417 ADM: A/D converter mode register................................................................................................................... 412 ADPC: A/D port configuration register ........................................................................................................ 219, 419 ADS: Analog input channel specification register............................................................................................. 418 ADTC0: Automatic data transfer address count register 0 ................................................................................... 523 ADTI0: Automatic data transfer interval specification register 0 ......................................................................... 522 ADTP0: Automatic data transfer address point specification register 0................................................................ 521 ASICL6: Asynchronous serial interface control register 6 ..................................................................................... 466 ASIF6: Asynchronous serial interface transmission status register 6 ................................................................. 463 ASIM0: Asynchronous serial interface operation mode register 0 ....................................................................... 436 ASIM6: Asynchronous serial interface operation mode register 6 ....................................................................... 460 ASIS0: Asynchronous serial interface reception error status register 0 .............................................................. 438 ASIS6: Asynchronous serial interface reception error status register 6 .............................................................. 462 [B] BANK: Memory Bank Select Register ................................................................................................................ 150 BRGC0: Baud rate generator control register 0 .................................................................................................... 439 BRGC6: Baud rate generator control register 6 .................................................................................................... 465 BRGCA0: Divisor selection register 0...................................................................................................................... 520 [C] CKS: Clock output selection register................................................................................................................ 404 CKSR6: Clock selection register 6........................................................................................................................ 463 CMP00: 8-bit timer H compare register 00 ........................................................................................................... 366 CMP01: 8-bit timer H compare register 01 ........................................................................................................... 366 CMP10: 8-bit timer H compare register 10 ........................................................................................................... 366 CMP11: 8-bit timer H compare register 11 ........................................................................................................... 366 CR000: 16-bit timer capture/compare register 000 .............................................................................................. 273 CR001: 16-bit timer capture/compare register 000 .............................................................................................. 273 CR010: 16-bit timer capture/compare register 010 .............................................................................................. 273 CR011: 16-bit timer capture/compare register 011 .............................................................................................. 273 CR50: 8-bit timer compare register 50............................................................................................................... 347 CR51: 8-bit timer compare register 51............................................................................................................... 347 CRC00: Capture/compare control register 00 ...................................................................................................... 280 CRC01: Capture/compare control register 01 ...................................................................................................... 280 CSIC10: Serial clock selection register 10 ............................................................................................................ 495 CSIC11: Serial clock selection register 11 ............................................................................................................ 495 CSIM10: Serial operation mode register 10........................................................................................................... 493 CSIM11: Serial operation mode register 11........................................................................................................... 493 CSIMA0: Serial operation mode specification register 0 ........................................................................................ 515 CSIS0: Serial status register 0 ............................................................................................................................ 517 CSIT0: Serial trigger register 0 ........................................................................................................................... 519 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 940 78K0/Kx2 APPENDIX C REGISTER INDEX [D] DMUC0: Multiplier/divider control register 0 .......................................................................................................... 625 [E] EGN: External interrupt falling edge enable register ........................................................................................ 652 EGP: External interrupt rising edge enable register ......................................................................................... 652 [I] IF0H: Interrupt request flag register 0H ............................................................................................................ 637 IF0L: Interrupt request flag register 0L............................................................................................................. 637 IF1H: Interrupt request flag register 1H ............................................................................................................ 637 IF1L: Interrupt request flag register 1L............................................................................................................. 637 IIC0: IIC shift register 0 ................................................................................................................................... 553 IICC0: IIC control register 0 ............................................................................................................................... 556 IICCL0: IIC clock selection register 0................................................................................................................... 565 IICF0: IIC flag register 0 .................................................................................................................................... 563 IICS0: IIC status register 0 ................................................................................................................................ 561 IICX0: IIC function expansion register 0 ............................................................................................................ 566 IMS: Internal memory size switching register.................................................................................................. 721 ISC: Input switch control register .................................................................................................................... 468 IXS: Internal expansion RAM size switching register ..................................................................................... 722 [K] KRM: Key return mode register ........................................................................................................................ 665 [L] LVIM: Low-voltage detection register................................................................................................................ 699 LVIS: Low-voltage detection level selection register ........................................................................................ 701 [M] MCM: Main clock mode register........................................................................................................................ 237 MDA0H: Multiplication/division data register A0.................................................................................................... 623 MDA0L: Multiplication/division data register A0.................................................................................................... 623 MDB0: Multiplication/division data register B0.................................................................................................... 624 MK0H: Interrupt mask flag register 0H ............................................................................................................... 643 MK0L: Interrupt mask flag register 0L ................................................................................................................ 643 MK1H: Interrupt mask flag register 1H ............................................................................................................... 643 MK1L: Interrupt mask flag register 1L ................................................................................................................ 643 MOC: Main OSC control register ...................................................................................................................... 236 [O] OSCCTL: Clock operation mode select register ..................................................................................................... 229 OSTC: Oscillation stabilization time counter status register ....................................................................... 238, 667 OSTS: Oscillation stabilization time select register .................................................................................... 239, 668 [P] P0: Port register 0 ......................................................................................................................................... 210 P1: Port register 1 ......................................................................................................................................... 210 P2: Port register 2 ......................................................................................................................................... 210 P3: Port register 3 ......................................................................................................................................... 210 P4: Port register 4 ......................................................................................................................................... 210 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 941 78K0/Kx2 APPENDIX C REGISTER INDEX P5: Port register 5 ......................................................................................................................................... 210 P6: Port register 6 ......................................................................................................................................... 210 P7: Port register 7 ......................................................................................................................................... 210 P12: Port register 12 ....................................................................................................................................... 210 P13: Port register 13 ....................................................................................................................................... 210 P14: Port register 14 ....................................................................................................................................... 210 PCC: Processor clock control register.............................................................................................................. 232 PM0: Port mode register 0 ............................................................................................................... 205, 288, 498 PM1: Port mode register 1 ........................................................................................205, 353, 372, 440, 468, 498 PM2: Port mode register 2 ....................................................................................................................... 205, 420 PM3: Port mode register 3 ....................................................................................................................... 205, 353 PM4: Port mode register 4 ............................................................................................................................... 205 PM5: Port mode register 5 ............................................................................................................................... 205 PM6: Port mode register 6 ....................................................................................................................... 205, 568 PM7: Port mode register 7 ............................................................................................................................... 205 PM12: Port mode register 12 ..................................................................................................................... 205, 702 PM14: Port mode register 14 ............................................................................................................. 205, 407, 523 PR0H: Priority specification flag register 0H ...................................................................................................... 648 PR0L: Priority specification flag register 0L ....................................................................................................... 648 PR1H: Priority specification flag register 1H ...................................................................................................... 648 PR1L: Priority specification flag register 1L ....................................................................................................... 648 PRM00: Prescaler mode register 00..................................................................................................................... 285 PRM01: Prescaler mode register 01..................................................................................................................... 285 PU0: Pull-up resistor option register 0 ............................................................................................................. 215 PU1: Pull-up resistor option register 1 ............................................................................................................. 215 PU3: Pull-up resistor option register 3 ............................................................................................................. 215 PU4: Pull-up resistor option register 4 ............................................................................................................. 215 PU5: Pull-up resistor option register 5 ............................................................................................................. 215 PU6: Pull-up resistor option register 6 ............................................................................................................. 215 PU7: Pull-up resistor option register 7 ............................................................................................................. 215 PU12: Pull-up resistor option register 12 ........................................................................................................... 215 PU14: Pull-up resistor option register 14 ........................................................................................................... 215 [R] RCM: Internal oscillation mode register ............................................................................................................ 235 RESF: Reset control flag register....................................................................................................................... 691 RXB0: Receive buffer register 0......................................................................................................................... 435 RXB6: Receive buffer register 6......................................................................................................................... 459 RXS0: Receive shift register 0 ........................................................................................................................... 435 RXS6: Receive shift register 6 ........................................................................................................................... 459 [S] SDR0: Remainder data register 0 ...................................................................................................................... 623 SIO10: Serial I/O shift register 10 ....................................................................................................................... 492 SIO11: Serial I/O shift register 11 ....................................................................................................................... 492 SIOA0: Serial I/O shift register 0 ......................................................................................................................... 515 SOTB10: Transmit buffer register 10...................................................................................................................... 492 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 942 78K0/Kx2 APPENDIX C REGISTER INDEX SOTB11: Transmit buffer register 11...................................................................................................................... 492 SVA0: Slave address register 0 ......................................................................................................................... 553 [T] TCL50: Timer clock selection register 50 ............................................................................................................ 348 TCL51: Timer clock selection register 51 ............................................................................................................ 348 TM00: 16-bit timer counter 00............................................................................................................................ 272 TM01: 16-bit timer counter 01............................................................................................................................ 272 TM50: 8-bit timer counter 50.............................................................................................................................. 347 TM51: 8-bit timer counter 51.............................................................................................................................. 347 TMC00: 16-bit timer mode control register 00 ...................................................................................................... 277 TMC01: 16-bit timer mode control register 01 ...................................................................................................... 277 TMC50: 8-bit timer mode control register 50 ........................................................................................................ 351 TMC51: 8-bit timer mode control register 51 ........................................................................................................ 351 TMCYC1: 8-bit timer H carrier control register 1 ..................................................................................................... 371 TMHMD0: 8-bit timer H mode register 0 .................................................................................................................. 367 TMHMD1: 8-bit timer H mode register 1 .................................................................................................................. 367 TOC00: 16-bit timer output control register 00 ..................................................................................................... 282 TOC01: 16-bit timer output control register 01 ..................................................................................................... 282 TXB6: Transmit buffer register 6........................................................................................................................ 459 TXS0: Transmit shift register 0 .......................................................................................................................... 435 TXS6: Transmit shift register 6 .......................................................................................................................... 459 [W] WDTE: Watchdog timer enable register.............................................................................................................. 398 WTM: Watch timer operation mode register...................................................................................................... 391 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 943 78K0/Kx2 APPENDIX D LIST OF CAUTIONS APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. "Classification (hard/soft)" in table is as follows. Hard: Soft: Cautions for microcontroller internal/external hardware Cautions for software such as register settings or programs Hard Classification Hard Chapter 2 Chapter 1 Chapter (1/30) Function Details of Function Pin function AVSS Cautions Page Make AVSS the same potential as VSS. pp. 42, 44 to 47 AVSS, EVSS Make AVSS and EVSS the same potential as VSS. pp. 43, 48 to 50 EVDD Make EVDD the same potential as VDD. pp. 43, 48 to 50 REGC Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). pp. 42 to 50 ANI0/P20 to ANIn/P2n ANI0/P20 to ANIn/P2n are set in the analog input mode after release of reset. pp. 42 to 50 Pin function ANI0/P20 to ANI7/P27 ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. p. 81 In the product with an on-chip debug function (PD78F05xxD and 78F05xxDA), be sure to pull the P31/INTP2/OCD1A pin down before a reset, release to prevent malfunction. p. 82 P31/INTP2/ OCD1A Soft Chapter 3 Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug p. 83 function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator (see the table on p.83). Memory space P121/X1/OCD0A Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator (see the table on p.87). p. 87 REGC pin Keep the wiring length as short as possible for the broken-line part in the above figure. p. 90 IMS, IXS: Internal memory size switching register, internal expansion RAM size switching register Regardless of the internal memory capacity, the initial values of the internal memory p. 96 size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Kx2 microcontrollers are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. p. 96 Memory bank Instructions cannot be fetched between different memory banks. p. 113 Branch and access cannot be directly executed between different memory banks. Execute branch or access between different memory banks via the common area. p. 113 SFR: Special function register Allocate interrupt servicing in the common area. p. 113 An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. p. 113 Do not access addresses to which SFRs are not assigned. p. 116 SP: Stack pointer Since reset signal generation makes the SP contents undefined, be sure to initialize p. 126 the SP before using the stack. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 944 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Port function Soft Classification Cautions Page BANK: Memory bank select register Be sure to change the value of the BANK register in the common area (0000H to p. 150 7FFFH). If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never change the value of the BANK register in the bank area. Memory bank Instructions cannot be fetched between different memory banks. p. 151 Branching and accessing cannot be directly executed between different memory banks. Execute branching or accessing between different memory banks via the common area. p. 151 P02/SO11, P04/SCK11 Allocate interrupt servicing in the common area. p. 151 An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. p. 151 To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H). p. 164 P10/SCK10/TxD0, To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode register 10 (CSIM10) and serial clock selection register 10 P12/SO10 (CSIC10) to the default status (00H) p. 175 P13/TxD6 To use P13/TxD6 as general-purpose port, clear bit 0 (TXDLV6) of synchronous serial interface control register 6 (ASICL6) to 0 (normal output of TxD6). p. 175 Soft Hard Soft Memory bank switching function (products whose flash memory is at least 96 KB only) Details of Function Port 2 Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. p. 181 For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". p. 182 Hard Chapter 5 Chapter 4 Chapter (2/30) Function P31/INTP2/ OCD1A In the product with an on-chip debug function (PD78F05xxD and 78F05xxDA), be sure to pull the P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction. p. 183 Soft For the 38-pin products of 78K0/KC2, be sure to set bits 0 and 1 of PM4 and P4 to "0". p. 187 P60, P61 A through current flows through P60 and P61 if an intermediate potential is input to these pins, because the input buffer is also turned on when P60 and P61 are in output mode. Consequently, do not input an intermediate potential when P60 and P61 are in output mode. p. 190 P62 A through current flows through P62 if an intermediate potential is input to this pin, because the input buffer is also turned on when P62 is in output mode. Consequently, do not input an intermediate potential when P62 is in output mode. p. 191 Port 7 For the 38-pin products of 78K0/KC2, be sure to set bits 2 and 3 of PM7 and P7 to "0". p. 195 Soft Port 4 Hard Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug p. 183 function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator (see the table on p.183). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 945 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Chapter Chapter 5 Soft Classification (3/30) Function Port function Details of Function P121/X1/OCD0A, P122/X2/EXCLK/O CD0B, P123/XT1, P124/XT2/EXCLKS Cautions When using the P121 to P124 pins to connect a resonator for the main system clock p. 196 (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary. Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function (PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash memory programmer or an on-chip debug emulator (see the table on p.197). Port mode registers Page p. 197 Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of p. 205 PM6, bits 3 to 7 of PM12 to 1. (78K0/KB2) For the 38-pin products, be sure to set bits 2 to 7 of PM0, bits 6 and 7 of PM2, bits 4 p. 206 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to "1". Also, be sure to set bits 0 and 1 of PM4, and bits 2 and 3 of PM7 to "0". For the 44-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to "1". For the 48-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 6 and 7 of PM7, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to "1". (78K0/KC2) Be sure to set bits 4 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of p. 207 PM6, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to 1. (78K0/KD2) Soft Chapter 6 Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of PM5, p. 208 bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to "1". (78K0/KE2) Clock generator Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and 7 of PM14 to "1". (78K0/KF2) p. 209 Port register (78K0/KC2) For the 38-pin products, be sure to set bits 6 and 7 of P2, bits 0 and 1 of P4, and bits 2 and 3 of P7 to "0". p. 211 ADPC: A/D port configuration register Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). p. 220 If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the peripheral hardware clock is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 220 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input p. 224 and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. OSCCTL: Clock operation mode select register Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. pp. 230, 231 Set AMPH before setting the main clock mode register (MCM). pp. 230, 231 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 946 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Chapter Chapter 6 Soft Classification (4/30) Function Clock generator Details of Function OSCCTL: Clock operation mode select register Cautions Page Set AMPH before setting the peripheral functions after a reset release. The value of pp. 230, 231 AMPH can be changed only once after a reset release. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the high-speed system clock (external clock input) is selected as the CPU clock, supply of the CPU clock is stopped for the duration of 160 external clocks after AMPH is set to 1. pp. 230, If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal high- 231 speed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, the oscillation stabilization time is counted after the STOP mode is released. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) pp. 230, of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external 231 clock from the EXCLK pin is disabled). Be sure to clear bits 1 to 5 to 0. (78K0/KB2) PCC: Processor clock control register RCM: Internal oscillation mode register pp. 230, 231 Be sure to clear bits 1 to 3 to 0. (78K0/KC2 to 78K0/KF2) p. 232 Be sure to clear bits 3 and 7 to "0". (78K0/KC2 to 78K0/KF2) p. 233 The peripheral hardware clock (fPRS) is not divided when the division ratio of the PCC pp. 232, is set. 233 Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating with main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS. p. 234 When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. <1> 78K0/KB2 * When MCS = 1 (when CPU operates with the high-speed system clock) <2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. p. 235 p. 236 MOC: Main OSC When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock control register other than the high-speed system clock. Specifically, set under either of the following conditions. <1> 78K0/KB2 * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) <2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2 * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select register (OSCCTL) is 0 (I/O port mode). p. 236 The peripheral hardware cannot operate when the peripheral hardware clock is stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. p. 236 947 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Chapter Classification Soft Chapter 6 Clock generator Details of Function MCM: Main clock mode register Hard Soft (5/30) Function Soft Hard OSTC: Oscillation stabilization time counter status register Cautions Page XSEL can be changed only once after a reset release. p. 237 Do not rewrite MCM0 when the CPU clock operates with the subsystem clock. p. 237 A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0. * Watchdog timer (operates with internal low-speed oscillation clock) 7 9 * When "fRL", "fRL/2 ", or "fRL/2 " is selected as the count clock for 8-bit timer H1 (operates with internal low-speed oscillation clock) * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) p. 237 After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 238 The oscillation stabilization time counter counts up to the oscillation stabilization time p. 238 set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). OSTS: Oscillation To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS stabilization time before executing the STOP instruction. select register Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. p. 238 p. 239 p. 239 Hard The oscillation stabilization time counter counts up to the oscillation stabilization time p. 239 set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). X1/XT1 oscillator - When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed p. 241 by the broken lines in the Figures 6-12 and 6-13 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 239 p. 242 948 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Chapter Classification Chapter 6 Clock generator operation when power supply voltage is turned on - Soft Details of Function Hard (6/30) Function Cautions Page It is not necessary to wait for the oscillation stabilization time when an external clock pp. 246, input from the EXCLK and EXCLKS pins is used. 247 A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the power p. 247 supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. Controlling X1/P121 and The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset high-speed X2/EXCLK/P122 release. system clock X1 clock Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. p. 248 p. 249 Set the X1 clock after the supply voltage has reached the operable voltage of the p. 249 clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS : TA = * 40 to +125C)). External main system clock Do not change the value of EXCLK and OSCSEL while the external main systerm clock is operating. p. 249 Set the external main system clock after the supply voltage has reached the operable p. 249 voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS : TA = * 40 to +125C)). Main system clock If the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. p. 250 High-speed system clock Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop p. 251 peripheral hardware that is operating on the high-speed system clock. Internal highBe sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, speed oscillation stop peripheral hardware that is operating on the internal high-speed oscillation clock clock. p. 253 XT1/P123, XT2/EXCLKS/ P124 The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release. p. 254 External clock from peripheral hardware pins Do not start the peripheral hardware operation with the external clock from peripheral p. 254 hardware pins when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. XT1 clock, Do not change the value of XTSTART, EXCLKS, and OSCSELS while the external subsystem clock is operating. subsystem clock p. 254 Subsystem clock Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. p. 255 The subsystem clock oscillation cannot be stopped using the STOP instruction. Controlling Internal lowIf "Internal low-speed oscillator cannot be stopped" is selected by the option byte, internal low- speed oscillation oscillation of the internal low-speed oscillation clock cannot be controlled. speed clock oscillation clock R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 255 p. 256 949 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Chapter Classification Chapter 6 Soft (7/30) Function CPU clock Details of Function - Cautions Page Set the clock after the supply voltage has reached the operable voltage of the clock pp. 260, to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD 261, 263 PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS : TA = * 40 to +125C)). p. 266 Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). When switching the internal high-speed oscillation clock to the high-speed system p. 267 clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Hard Soft Chapter 7 Do not rewrite MCM0 when the CPU clock operates with the subsystem clock. 16-bit timer/event counters 00, 01 - p. 267 The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at p. 272 the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. p. 272 To change the mode from the capture mode to the comparison mode, first clear the p. 272 TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has been once captured remains stored in CR00n unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value. TM0n: 16-bit timer Even if TM0n is read, the value is not captured by CR01n. counter 0n p. 273 CR00n, CR01n: 16-bit timer capture/compare registers 00n, 01n CR00n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. p. 274 CR01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. p. 274 To capture the count value of the TM0n register to the CR00n register by using the p. 276 phase reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated after the value has been captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM00n signal. Hard CRC0n: Capture/ To ensure that the capture operation is performed properly, the capture trigger pp. 280, compare control requires a pulse two cycles longer than the count clock selected by prescaler mode 281 register 0n register 0n (PRM0n). Soft TMC0n: 16-bit 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3 p. 277 timer mode are set to values other than 00 (operation stop mode), respectively. Set TMC0n2 control register 0n and TMC0n3 to 00 to stop the operation. Be sure to set TOC0n using the following procedure. TOC0n: 16-bit timer output <1> Set TOC0n4 and TOC0n1 to 1. control register 0n <2> Set only TOE0n to 1. <3> Set either of LVS0n or LVR0n to 1. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 282 950 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Chapter Chapter 7 Classification (8/30) Function Details of Function 16-bit PRM0n: Prescaler timer/event mode register 0n counters 00, 01 Cautions Page Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11 p. 285 (to specify the valid edge of the TI00n pin as a count clock). * Clear & start mode entered by the TI00n pin valid edge * Setting the TI00n pin as a capture trigger Soft Hard p. 285 If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at p. 285 the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. Clear & start mode entered by TI00n pin valid edge input Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n may be cleared. p. 299 PPG output To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during TM0n operation. p. 321 Set values to CR00n and CR01n such that the condition 0000H CR01n < CR00n p. 323 FFFFH is satisfied. One-shot pulse output LVS0n, LVRn0 p. 325 To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do not change the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be unexpectedly output. p. 325 p. 327 p. 339 Table 7-3 shows the restrictions for each channel. p. 340 Hard Do not set the same value to CR00n and CR01n. Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. Soft - Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. CR00n, CR01n: 16-bit timer capture/compare registers 00n, 01n Set a value other than 0000H to CR00n and CR01n in clear & start mode entered p. 340 upon a match between TM0n and CR00n (TM0n cannot count one pulse when it is used as an external event counter). p. 341 When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is detected (the interrupt signal is not generated when the reversephase edge of the TI00n pin is detected). When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated. The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 340 p. 341 951 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Classification Soft Chapter 7 Chapter (9/30) Function Details of Function 16-bit ES0n0, ES0n1 timer/event counters Re-triggering 00, 01 one-shot pulse OVF0n Cautions Page Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and p. 341 TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1. Make sure that the trigger is not generated while an active level is being output in the p. 341 one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H p. 342 One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. p. 342 TI00n When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly. p. 343 TI00n, TI01n To accurately capture the count value, the pulse input to the TI00n and TI01n pins as p. 343 a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 7-9). INTTM00n, INTTM01n The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9). p. 343 Soft CRC0n1 = 1 When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal when the external interrupt is not used. p. 343 Specifying valid edge after reset p. 343 If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge p. 343 of TI00n is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM0n is used for sampling. When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9). TI00n/TI01n The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. Hard One-shot pulse output Hard Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count p. 342 clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. p. 343 Soft Chapter 8 Reading of TM0n TM0n can be read without stopping the actual counter, because the count values p. 344 captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. 8-bit CR5n: 8-bit timer timer/event compare register counters 5n 50, 51 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = p. 347 0), do not write other values to CR5n during operation. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock p. 347 selected by TCL5n) or more. 952 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 8 Chapter (10/30) Function Details of Function 8-bit TCL50: Timer clock timer/event selection register 50 counters TCL51: Timer clock 50, 51 selection register 51 Cautions When rewriting TCL50 to other data, stop the timer operation beforehand. Soft Chapter 9 p. 349 Be sure to clear bits 3 to 7 to "0". p. 349 When rewriting TCL51 to other data, stop the timer operation beforehand. p. 350 Be sure to clear bits 3 to 7 to "0". TMC5n: 8-bit timer The settings of LVS5n and LVR5n are valid in other than PWM mode. mode control Perform <1> to <4> below in the following order, not at the same time. register 5n (TMC5n) <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n Interval timer Page p. 350 p. 352 p. 352 When TCE5n = 1, setting the other bits of TMC5n is prohibited. p. 352 The actual TO50/TI50/P17 and TO51/TI51/P33/INTP4 pin outputs are determined depending on PM17 and P17, and PM33 and P33, besides TO5n output. p. 352 Do not write other values to CR5n during operation. p. 354 Square-wave output Do not write other values to CR5n during operation. p. 357 PWM output In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. p. 358 When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). p. 361 Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. p. 362 Reading of TM5n TM5n can be read without stopping the actual counter, because the count values p. 362 captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. 8-bit timers CMP0n: 8-bit timer H CMP0n cannot be rewritten during timer count operation. CMP0n can be H0, H1 comparer register 0n refreshed (the same value is written) during timer count operation. (CMP0n) p. 366 CMP1n: 8-bit timer H In the PWM output mode and carrier generator mode, be sure to set CMP1n compare register 1n when starting the timer count operation (TMHEn = 1) after the timer count (CMP1n) operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). p. 366 TMHMD0: 8-bit timer When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, H mode register 0 TMHMD0 can be refreshed (the same value is written). p. 369 In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). p. 369 The actual TOH0/P15 pin output is determined depending on PM15 and P15, besides TOH0 output. p. 369 TMHMD1: 8-bit timer When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). H mode register 1 In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). p. 371 p. 371 When the carrier generator mode is used, set so that the count clock frequency of p. 371 TMH1 becomes more than 6 times the count clock frequency of TM51. The actual TOH1/INTP5/P16 pin output is determined depending on PM16 and P16, besides TOH1 output. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 371 953 78K0/Kx2 APPENDIX D LIST OF CAUTIONS 8-bit timers TMCYC1: 8-bit H0, H1 timer H carrier register 1 Classification Hard Soft Details of Function PWM output Soft Chapter 9 Chapter (11/30) Function Cautions Page Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same p. 371 value is written). The set value of the CMP1n register can be changed while the timer counter is operating. However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed until the value is transferred to the register. p. 377 Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) p. 377 after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). Carrier generator (8-bit timer H1 only) Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH p. 377 Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. p. 383 When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt p. 383 is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. Soft Hard Soft Chapter 11 Chapter 10 Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) p. 385 after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Watch timer WTM: Watch timer operation mode register Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. p. 385 Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. p. 385 The set value of the CMP11 register can be changed while the timer counter is operating. However, it takes the duration of three operating clocks (signal selected by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11 register has been changed until the value is transferred to the register. p. 385 Be sure to set the RMC1 bit before the count operation is started. p. 385 Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) p. 393 of WTM) during watch timer operation. Interrupt request When operation of the watch timer and 5-bit counter is enabled by the watch timer mode p. 395 control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Watchdog WDTE: If a value other than ACH is written to WDTE, an internal reset signal is generated. If timer Watchdog timer the source clock to the watchdog timer is stopped, however, an internal reset signal is enable register generated when the source clock to the watchdog timer resumes operation. p. 398 If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal p. 398 is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. Operation control The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). p. 398 The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. p. 399 If the watchdog timer is cleared by writing "ACH" to WDTE, the actual overflow time may p. 399 be different from the overflow time set by the option byte by up to 2/fRL seconds. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 954 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Watchdog timer Details of Function Cautions Operation control The watchdog timer can be cleared immediately before the count value overflows (FFFFH). Page p. 399 Chapter 12 Soft Soft p. 400 The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte (see Table on p. 402). If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops operating. At this time, the counter is not cleared to 0. Chapter 13 Chapter 11 Chapter (12/30) Function Setting overflow time of watchdog timer, Setting window open period of watchdog time The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. Setting window open period of watchdog timer Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V VDD < 2.7 V. p. 401 The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. p. 401 Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). pp. 405, 407 Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). p. 407 Clock output/ CKS: clock buzzer output output select controller register pp. 400, 401 The watchdog timer continues its operation during self-programming and EEPROM pp. 400, emulation of the flash memory. During processing, the interrupt acknowledge time 401 is delayed. Set the overflow time and window size taking this delay into consideration. When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read p. 411 A/D converter ADCR: 10-bit A/D conversion data from ADCR and ADCRH when the peripheral hardware clock (fPRS) is stopped. register, ADCRH: For details, see CHAPTER 36 CAUTIONS FOR WAIT. 8-bit A/D conversion register ADM: A/D converter mode register A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to p. 413 values other than the identical data. A/D conversion timer selection Set the conversion times with the following conditions. (see pp.414, 415) When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. pp. 414, 415 Change LV0 from the default value, when 2.3 V AVREF < 2.7 V. pp. 414, 415 The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. pp. 414, 415 ADCR: 10-bit A/D conversion register If data is written to ADM, a wait cycle is generated. Do not write data to ADM when p. 413 the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. pp. 414, 415 When writing to the A/D converter mode register (ADM), analog input channel p. 416 specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR p. 416 when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 955 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 13 Chapter (13/30) Function A/D converter Details of Function Cautions Page ADCRH: 8-bit A/D When writing to the A/D converter mode register (ADM), analog input channel p. 417 conversion specification register (ADS), and A/D port configuration register (ADPC), the contents register of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. ADS: Analog input channel specification register If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 417 Be sure to clear bits 3 to 7 to "0". p. 418 If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 418 ADS: Analog input Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). channel specification register, ADPC: A/D port configuration register (ADPC) pp. 418, 419 ADPC: A/D port configuration register (ADPC) If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when p. 419 the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. Port mode register 2 (PM2) For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to "1", and bits 6 and 7 of P2 to "0". p. 420 Basic operations of A/D converter Make sure the period of <1> to <5> is 1 s or more. p. 421 A/D conversion operation Make sure the period of <1> to <5> is 1 s or more. p. 425 <1> may be done between <2> and <4>. p. 425 <1> can be omitted. However, ignore data of the first conversion after <5> in this case. p. 425 The period from <6> to <9> differs from the conversion time set using bits 5 to 1 (FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time set using FR2 to FR0, LV1, and LV0. p. 425 Hard p. 428 Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or p. 428 higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. Soft Operating current The A/D converter stops operating in the STOP mode. At this time, the operating in STOP mode current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. Conflicting operations If conflict occurs between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by instruction upon the end of conversion, ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or ADCRH. p. 428 If conflict occurs between ADCR or ADCRH write and A/D converter mode register p. 428 (ADM) write, analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion, ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 956 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 13 Chapter (14/30) Function Details of Function A/D converter Page p. 428 Noise To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF countermeasures pin and pins ANI0 to ANI7. * Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. * The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 13-20 is recommended. * Do not switch these pins with other pins during conversion. * The accuracy is improved if the HALT mode is set immediately after the start of conversion. ANI0/P20 to ANI7/P27 Soft Cautions The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). p. 429 When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. p. 429 Input impedance of ANI0 to ANI7 pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 13-20). p. 429 AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and p. 429 AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel p. 430 specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Conversion results The first A/D conversion value immediately after A/D conversion starts may not fall p. 430 just after A/D within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was conversion start set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. A/D conversion result register (ADCR, ADCRH) read operation p. 430 When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. Internal equivalent The equivalent circuit of the analog input block is shown below. (see Figure 13-22) circuit R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 431 957 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 14 Chapter (15/30) Function Serial interface UART0 Details of Function UART mode Cautions Page p. 432 If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. p. 432 TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. p. 432 Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. pp. 432, 435 TXS0: Transmit shift register 0 Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. p. 435 ASIM0: Asynchronous serial interface operation mode register 0 To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission, clear TXE0 to 0, and then clear POWER0 to 0. p. 437 To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear RXE0 to 0, and then clear POWER0 to 0. p. 437 Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. p. 437 If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. ASIS0: Asynchronous serial interface reception error status register 0 p. 437 Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. p. 437 Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. p. 437 Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. p. 437 Be sure to set bit 0 to 1. p. 437 The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0) p. 438 Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p. 438 If an overrun error occurs, the next receive data is not written to receive buffer register p. 438 0 (RXB0) but discarded. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 438 Hard Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting p. 440 BRGC0: Baud the MDL04 to MDL00 bits. rate generator control register 0 Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the TPS01 p. 440 and TPS00 bits. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 The baud rate value is the output clock of the 5-bit counter divided by 2. p. 440 958 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 14 Chapter (16/30) Function Serial interface UART0 Details of Function Cautions Page POWER0, TXE0, Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop RXE0: Bits 7, 6, mode. 5 of ASIM0 To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1. p. 441 UART mode Take relationship with the other party of communication when setting the port mode register and port register. p. 442 UART transmission After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. p. 445 UART reception If a reception error occurs, read asynchronous serial interface reception error status register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p. 446 Reception is always performed with the "number of stop bits = 1". The second stop bit p. 446 is ignored. Error of baud rate Keep the baud rate error during transmission to within the permissible error range at the reception destination. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Soft Chapter 15 Permissible baud Make sure that the baud rate error during reception is within the permissible error rate range during range, by using the calculation expression shown below. reception Serial interface UART6 UART mode p. 450 p. 450 p. 451 The TXD6 output inversion function inverts only the transmission side and not the p. 453 reception side. To use this function, the reception side must be ready for reception of inverted data. p. 453 If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. TXB6: Transmit buffer register 6 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. p. 453 TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. p. 453 Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. p. 453 If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is used in LIN communication operation. p. 453 Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. p. 459 Do not refresh (write the same value to) TXB6 by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6) of ASIM6 are 1). p. 459 Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. p. 459 959 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 15 Chapter (17/30) Function Serial interface UART6 Details of Function ASIM6: Asynchronous serial interface operation mode register 6 Cautions Page To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission, clear TXE6 to 0, and then clear POWER6 to 0. p. 461 To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear RXE6 to 0, and then clear POWER6 to 0. p. 461 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If p. 461 POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To p. 461 enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. ASIS6: Asynchronous serial interface reception error status register 6 ASIF6: Asynchronous serial interface transmission status register 6 Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. p. 461 Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. p. 461 Fix the PS61 and PS60 bits to 0 when used in LIN communication operation. p. 461 Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. p. 461 Make sure that RXE6 = 0 when rewriting the ISRM6 bit. p. 461 The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 p. 462 bits of asynchronous serial interface operation mode register 6 (ASIM6). For the stop bit of the receive data, only the first bit is checked regardless of the number of stop bits. p. 462 If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. p. 462 If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 462 To transmit data continuously, write the first transmit data (first byte) to the TXB6 p. 463 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. To initialize the transmission unit upon completion of continuous transmission, be sure p. 463 to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. Soft Hard CKSR6: Clock Make sure POWER6 = 0 when rewriting TPS63 to TPS60. selection register 6 p. 465 BRGC6: Baud Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting p. 465 rate generator the MDL67 to MDL60 bits. control register 6 The baud rate is the output clock of the 8-bit counter divided by 2. p. 465 ASICL6: Asynchronous serial interface control register 6 p. 466 ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF reception or SBF transmission. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF6 flag is held (1). p. 467 Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of p. 467 ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 960 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 15 Chapter (18/30) Function Details of Function Serial ASICL6: interface Asynchronous serial UART6 interface control register 6 Cautions The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. Page p. 467 Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of p. 467 ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission p. 467 Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during transmission. p. 467 When the TXDLV6 bit is set to 1 (inverted TxD6 output), the TxD6/SCLA0/P60 pin p. 467 cannot be used as a general-purpose port, regardless of the settings of POWER6 and TXE6. When using the TxD6/SCLA0/P60 pin as a general-purpose port, clear the TXDLV6 bit to 0 (normal TxD6 output). Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 467 POWER6, TXE6, Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation. RXE6: Bits 7, 6, 5 of To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1. ASIM6 p. 469 UART mode Take relationship with the other party of communication when setting the port mode register and port register. p. 470 Parity types and operation Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation. p. 473 Continuous transmission The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to p. 475 "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. When the device is use in LIN communication operation, the continuous transmission p. 475 function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. p. 475 To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. p. 475 During continuous transmission, the next transmission may complete before p. 475 execution of INTST6 interrupt servicing after transmission of one data frame. As a countermeasure, detection can be performed by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. Normal reception Error of baud rate Permissible baud rate range during reception R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p. 479 Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. p. 479 Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. p. 479 Keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 486 Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. p. 486 Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. p. 487 961 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Classification Soft Chapter 16 Chapter (19/30) Function Serial interface CSI10, CSI11 Details of Function Cautions Page SOTB1n: Transmit buffer register 1n Do not access SOTB1n when CSOT1n = 1 (during serial communication). p. 492 In the slave mode, transmission/reception is started when data is written to SOTB11 with a low level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2) Communication operation. p. 492 CSIM10: Serial operation mode register 10 Be sure to clear bit 5 to 0. p. 493 CSIC10: Serial clock selection register 10 Do not write to CSIC10 while CSIE10 = 1 (operation enabled). p. 496 CSIC11: Serial clock selection register 11 To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in p. 496 the default status (00H). The phase type of the data clock is type 1 after reset. p. 496 Do not write to CSIC11 while CSIE11 = 1 (operation enabled). p. 498 To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status (00H). p. 498 The phase type of the data clock is type 1 after reset. p. 498 3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode register and port register. p. 500 Communication operation p. 503 Do not access the control register and data register when CSOT1n = 1 (during serial communication). When using serial interface CSI11, wait for the duration of at least one clock before p. 503 the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. Soft Chapter 17 SO1n output Serial interface CSIA0 If a value is written to CSIE1n, TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. p. 511 SIOA0: Serial I/O shift A communication operation is started by writing to SIOA0. Consequently, when register 0 transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0 register to start the communication operation, and then perform a receive operation. p. 515 Do not write data to SIOA0 while the automatic transmit/receive function is operating. CSIMA0: When CSIAE0 = 0, the buffer RAM cannot be accessed. Serial operation mode When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note specification register 0 above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. p. 515 p. 516 p. 516 When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. p. 516 CSIS0: Serial status register 0 Be sure to clear bit 7 to 0. p. 517 CSIT0: Serial trigger register 0 Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1-byte transfer is complete. During transfer (TSF0 = 1), rewriting serial operation mode specification register 0 p. 518 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. p. 519 ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI p. 519 is generated. p. 519 After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by setting ATSTA0 to 1 after re-setting the registers. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 962 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 17 Chapter (20/30) Function Serial interface CSIA0 Details of Function Cautions Page ADTP0: Automatic Be sure to clear bits 7 to 5 to "0". data transfer address point specification register 0 p. 521 ADTI0: Automatic data transfer interval specification register 0 p. 522 Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. 3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode p. 525 register and port register. 1-byte transmission/ reception The SOA0 pin becomes low level by an SIOA0 write. Communication start If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. p. 529 3-wire serial I/O mode with automatic transmit/receive function A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 36 CAUTIONS FOR WAIT. p. 530 Take the relationship with the other communicating party into consideration when setting the port mode register and port register. p. 532 Automatic transmission/ reception mode p. 527 Because, in the automatic transmission/reception mode, the automatic p. 534 transmit/receive function writes/reads data to/from the internal buffer RAM after 1byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 534 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Automatic transmission Because, in the automatic transmission mode, the automatic transmit/receive p. 539 function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 539 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Repeat transmission mode Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). p. 541 If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 541 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 963 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 17 Chapter (21/30) Function Serial interface CSIA0 Details of Function Automatic transmission/ reception suspension and restart Cautions If the HALT instruction is executed during automatic transmission/reception, p. 544 communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TSF0 = 1. Busy control option Soft Chapter 18 - p. 544 Busy control cannot be used simultaneously with the interval time control function of p. 545 automatic data transfer interval specification register 0 (ADTI0). Busy & strobe control When TSF0 is cleared, the SOA0 pin goes low. option Serial interface IIC0 Page Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface IIC0 and the multiplier/divider. p. 547 p. 550 IIC0: IIC shift register Do not write data to IIC0 during data transfer. p. 553 0 Write or read IIC0 only during the wait period. Accessing IIC0 in a communication p. 553 state other than during the wait period is prohibited. When the device serves as the master, however, IIC0 can be written only once after the communication trigger bit (STT0) is set to 1. When communication is reserved, write data to the IIC0 register after the interrupt triggered by a stop condition is detected. IICC0: IIC control register 0 p. 553 2 If the operation of I C is enabled (IICE0 = 1) when the SCL0 line is high level, the p. 557 SDA0 line is low level, and the digital filter is turned on (DFC0 of the IICCL0 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by using a 1-bit memory manipulation instruction immediately after 2 enabling operation of I C (IICE0 = 1). When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission p. 560 status), bit 5 (WREL0) of the IICC0 register is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high impedance. Release the wait performed while the TRC bit is 1 (transmission status) by writing to the IIC shift register. IICS0: IIC status register 0 If data is read from IICS0 register, a wait cycle is generated. Do not read data from p. 561 IICS0 register when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT. IICF0: IIC flag register Write to STCEN bit only when the operation is stopped (IICE0 = 0). 0 As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. Write to IICRSV bit only when the operation is stopped (IICE0 = 0). 2 Selection clock setting Determine the transfer clock frequency of I C by using CLX0, SMC0, CL01, and CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0. p. 564 p. 564 p. 564 p. 567 2 When STCEN = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication p. 584 status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. * Set IIC clock selection register 0 (IICCL0). * Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1. * Set bit 0 (SPT0) of IICC0 to 1. When STCEN = 1 Immediately after I C operation is enabled (IICE0 = 1), the bus released status p. 584 (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 2 964 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Soft Chapter 19 Chapter 18 Chapter (22/30) Function Serial interface IIC0 Multiplier/ divider Details of Function 2 Cautions 2 Page If other I C communications are already in progress If I C operation is enabled and the device participates in communication already in 2 progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I C recognizes that the SDA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, 2 2 but this interferes with other I C communications. To avoid this, start I C in the following sequence. * Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the stop condition is detected. 2 * Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I C. * Wait for detection of the start condition. * Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly disable detection. p. 584 Transfer clock frequency setting Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 p. 584 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0 once. STT0, SPT0: Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before Bits 1, 0 of IIC control they are cleared to 0 is prohibited. register 0 (IICC0) p. 585 Transmission reserve When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software. p. 585 - SDR0: Remainder data register 0 MDA0H, MDA0L: Multiplication/ division data register A0 Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags corresponding to interrupt request sources are shared among serial interface IIC0 and the multiplier/divider. p. 621 The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. p. 623 SDR0 is reset when the operation is started (when DMUE is set to 1). p. 623 MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). p. 623 Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. p. 623 The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. p. 623 MDB0: Multiplication/ Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) division data register of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the B0 operation is executed, but the result is undefined. DMUC0: Multiplier/divider control register 0 p. 624 Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. p. 624 If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. p. 625 Do not change the value of DMUSEL0 during operation processing (while DMUE is p. 625 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 625 965 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 20 Chapter (23/30) Function Interrupt function Details of Function 1F0L, 1F0L, 1F1L, 1F1H: Interrupt request flag registers Cautions When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. Page p. 637 When manipulating a flag of the interrupt request flag register, use a 1-bit memory p. 637 manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. Be sure to clear bits 2, 4 to 7 of IF1L and bits 1 to 7 of IF1H to 0. (78K0/KB2) p. 638 Be sure to clear bits 6 and 7 of IF1L to 0 in the 38-pin and 44-pin products. Be sure to clear bit 7 of IF1L to 0 in the 48-pin products. p. 639 Be sure to clear bits 1 to 7 of IF1H to 0. (78K0/KC2) p. 639 Be sure to clear bit 7 of 1F1L and bits 1 to 7 of IF1H to 0. (78K0/KD2) p. 640 Be sure to clear bits 1 to 7 of IF1H to 0 for the products whose flash memory is less p. 641 than 32 KB. Be sure to clear bits 4 to 7 of IF1H to 0 for the products whose flash memory is at least 48 KB. (78K0/KE2) MK0L, MK0H, MK1L, MK1H: Interrupt mask flag registers Be sure to clear bits 5 to 7 of IF1H to 0. (78K0/KF2) p. 642 Be sure to set bits 2, 4 to 7 of MK1L and bits 1 to 7 of MK1H to 1. (78K0/KB2) p. 643 Be sure to set bits 6 and 7 of MK1L to 1 in the 38-pin and 44-pin products. Be sure to set bit 7 of MK1L to 1 in the 48-pin products. Be sure to set bits 1 to 7 of MK1H to 1. (78K0/KC2) p. 644 Be sure to set bit 7 of MK1L and bits 1 to 7 of MK1H to 1. (78K0/KD2) p. 645 Be sure to set bits 1 to 7 of MK1H to 1 for the products whose flash memory is less p. 646 than 32 KB. Be sure to set bits 4 to 7 of MK1H to 1 for the products whose flash memory is at least 48 KB. (78K0/KE2) PR0L, PR0H, PR1L, PR1H: Priority specification flag registers R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Be sure to set bits 5 to 7 of MK1H to 1. (78K0/KF2) p. 647 Be sure to set bits 2, 4 to 7 of PR1L and bits 1 to 7 of PR1H to 1. (78K0/KB2) p. 648 Be sure to set bits 6 and 7 of PR1L to 1 in the 38-pin and 44-pin products. Be sure to set bit 7 of PR1L to 1 in the 48-pin products. Be sure to set bits 1 to 7 of PR1H to 1. (78K0/KC2) p. 649 Be sure to set bit 7 of PR1L and bits 1 to 7 of PR1H to 1. (78K0/KD2) p. 650 Be sure to set bits 1 to 7 of PR1H to 1 for the products whose flash memory is less than 32 KB. Be sure to set bits 4 to 7 of PR1H to 1 for the products whose flash memory is at least 48 KB. (78K0/KE2) p. 651 Be sure to set bits 5 to 7 of PR1H to 1. (78K0/KF2) p. 652 966 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 20 Chapter (24/30) Function Interrupt function Details of Function EGP, EGN: External interrupt rising edge, falling edge enable registers Cautions Be sure to clear bits 6 and 7 of EGP and EGN to 0 in 78K0/KB2, and the 38-pin and 44-pin products of 78K0/KC2. Be sure to clear bit 7 of EGP and EGN to 0 in 78K0/KD2, and the 48-pin products of 78K0/KC2. p. 653 Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. p. 654 Soft Soft Chapter 22 Chapter 21 Software interrupt Do not use the RETI instruction for restoring from the software interrupt. request Key interrupt function Standby function Page p. 658 BRK instruction The BRK instruction is not one of the above-listed interrupt request hold instructions. p. 662 However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. KRM: Key return mode register If any of the KRMn bits used is set to 1, set bit n (PU7n) of the corresponding pull-up resistor register 7 (PU7) to 1. p. 665 If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts p. 665 and then change the KRM register. Clear the interrupt request flag and enable interrupts. Standby function The bits not used in the key interrupt mode can be used as normal ports. p. 665 For the 38-pin products of 78K0/KC2, be sure to set bits 2 to 7 of KRM to "0". For the 44-pin and 48-pin products of 78K0/KC2, be sure to set bits 4 to 7 of KRM to "0". p. 665 The STOP mode can be used only when the CPU is operating on the main system clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. p. 666 When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with main system clock before executing STOP instruction. p. 666 The following sequence is recommended for operating current reduction of the A/D p. 666 converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. Soft Hard OSTC: Oscillation stabilization time counter status register After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 668 p. 668 The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal highspeed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). p. 668 OSTS: Oscillation To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before p. 669 stabilization time executing the STOP instruction. select register Do not change the value of the OSTS register during the X1 clock oscillation p. 669 stabilization time. p. 669 The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal highspeed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 967 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Hard Classification Standby function Soft Chapter 22 Chapter (25/30) Function Details of Function Cautions OSTS: The X1 clock oscillation stabilization wait time does not include the time until clock Oscillation oscillation starts ("a" below). stabilization time select register STOP mode Page p. 669 Because the interrupt request signal is used to clear the standby mode, if there is an p. 674 interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. To use the peripheral hardware that stops operation in the STOP mode, and the p. 676 peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. Even if "internal low-speed oscillator can be stopped by software" is selected by the option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode, stop it by software and then execute the STOP instruction. p. 676 p. 676 To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), switch the CPU clock to the internal highspeed oscillation clock before the execution of the STOP instruction using the following procedure. <1> Set RSTOP to 0 (starting oscillation of the internal high-speed oscillator) <2> Set MCM0 to 0 (switching the CPU from X1 oscillation to internal high-speed oscillation) <3> Check that MCS is 0 (checking the CPU clock) <4> Check that RSTS is 1 (checking internal high-speed oscillation operation) <5> Execute the STOP instruction Before changing the CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). Hard Chapter 23 If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is p. 676 stopped for 4.06 to 16.12 s after the STOP mode is released when the internal highspeed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. Reset function - Execute the STOP instruction after having confirmed that the internal high-speed oscillator is operating stably (RSTS = 1). p. 676 For an external reset, input a low level for 10 s or more to the RESET pin. p. 681 During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and p. 681 internal low-speed oscillation clock stop oscillating. External main system clock input and external subsystem clock input become invalid. Soft Chapter 24 Soft When the STOP mode is released by a reset, the STOP mode contents are held p. 681 during reset input. However, the port pins become high-impedance, except for P130, which is set to low-level output. Power-onclear circuit Block diagram of An LVI circuit internal reset does not reset the LVI circuit. reset function p. 682 Watchdog timer overflow A watchdog timer internal reset resets the watchdog timer. p. 684 RESF: Reset control flag register Do not read data by a 1-bit memory manipulation instruction. p. 691 - R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 If an internal reset signal is generated in the POC circuit, the reset control flag register p. 692 (RESF) is cleared to 00H. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-VOLTAGE DETECTOR). pp. 694, 695 968 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Chapter Chapter 24 Details of Function Cautions Page Power-on- In 2.7 V/1.59 V clear POC mode circuit A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply p. 695 voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. Cautions for power-on-clear circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity p. 696 of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. Lowvoltage detector LVIM: LowTo stop LVI, follow either of the procedures below. voltage detection * When using 8-bit memory manipulation instruction: Write 00H to LVIM. register * When using 1-bit memory manipulation instruction: Clear LVION to 0. Soft Hard Chapter 25 Soft Classification (26/30) Function LVIM and LVIS p. 700 Input voltage from external input pin (EXLVI) must be EXLVI < VDD. p. 700 When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and LVIIF becomes 1. p. 701 With the conventional-specification products (PD78F05xx and 78F05xxD), after an p. 701 LVI reset has been generated, do not write values to LVIS and LVIM when LVION = 1. LVIS: LowBe sure to clear bits 4 to 7 to "0". voltage detection Do not change the value of LVIS during LVI operation. level selection When an input voltage from the external input pin (EXLVI) is detected, the detection register voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary. p. 701 p. 701 p. 701 p. 701 With the conventional-specification products (PD78F05xx and 78F05xxD), after an LVI reset has been generated, do not write values to LVIS and LVIM when LVION = 1. When used as reset (When detecting level of supply voltage (VDD)) Soft Chapter 26 Soft Hard When used as reset (When detecting level of input voltage from external input pin (EXLVI)) <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately p. 703 after the processing in <4>. If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. p. 703 <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately p. 706 after the processing in <3>. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)) when LVIMD is set to 1, an internal reset signal is not generated. p. 706 Input voltage from external input pin (EXLVI) must be EXLVI < VDD. p. 706 Input voltage from external input pin (EXLVI) must be EXLVI < VDD. When used as interrupt (When detecting level of input voltage from external input pin (EXLVI)) p. 711 Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity p. 713 voltage detector of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. Option byte 0082H, 0083H/ 1082H, 1083H Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap function is used). p. 716 0080H/1080H Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. p. 716 R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 969 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 26 Chapter (27/30) Function Option byte Details of Function Cautions Page 0081H/1081H POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during selfprogramming. However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. p. 716 0084H/1084H Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not p. 717 equipped with the on-chip debug function (PD78F05xx and 78F05xxA). Also set 00H to 1084H because 0084H and 1084H are switched during the boot swap operation. To use the on-chip debug function with a product equipped with the on-chip debug p. 717 function (PD78F05xxD and 78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot swap operation. 0080H/1080H The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 p. 718 is prohibited. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V VDD < 2.7 V. p. 718 The watchdog timer continues its operation during self-programming and EEPROM p. 718 emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied p. 718 to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit timer H1 even in the HALT/STOP mode Be sure to clear bit 7 to 0. Soft Chapter 27 0081H/1081H Flash IMS: Internal memory memory size switching register, IXS: internal expansion RAM size switching register Operation clock p. 718 Be sure to clear bits 7 to 1 to "0". p. 719 Be sure to set each product to the values shown in Table 27-1 after a reset release. p. 721 Be sure to set each product to the values shown in Table 27-2 after a reset release. p. 722 To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. pp. 721, 723 Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. p. 731 Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 p. 731 is used. Hard Processing of X1, For the product with an on-chip debug function (PD78F05xxD and 78F05xxDA), P31 pins connect P31/INTP2/OCD1A and P121/X1/OCD0A as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1A: Connect to EVSS via a resistor. * P121/X1/OCD0A: Connect to VSS via a resistor. p. 731 Selecting communication mode When UART6 is selected, the receive clock is calculated based on the reset command p. 733 sent from the dedicated flash memory programmer after the FLMD0 pulse has been received. Security Settings After the security setting for the batch erase is set, erasure cannot be performed for the p. 735 device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written, because the erase command is disabled. If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device will not be rewritten, and the device will not be erased in batch. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 p. 735 970 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Hard Classification Flash memory Details of Function Cautions Page E.P.V. command usage When executing boot swapping, do not use the E.P.V. command with the dedicated flash memory programmer. pp. 737, 738, 753 Flash memory programming by selfprogramming The self-programming function cannot be used when the CPU operates with the subsystem clock. p. 739 Oscillation of the internal high-speed oscillator is started during self programming, regardless of the setting of the RSTOP flag (bit 0 of the internal oscillation mode register (RCM)). Oscillation of the internal high-speed oscillator cannot be stopped even if the STOP instruction is executed. p. 739 Input a high level to the FLMD0 pin during self-programming. p. 739 Soft Chapter 27 Chapter (28/30) Function Be sure to execute the DI instruction before starting self-programming. p. 739 The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H). If an interrupt request is generated, self-programming is stopped. Self-programming is also stopped by an interrupt request that is not masked even in the p. 739 DI status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L, MK0H, MK1L, and MK1H). Hard Hard Chapters 30, 31, 32, 33 Chapter 28 Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. On-chip debug function (PD78F 05xxD and 78F05xx DA only) p. 740 PD78F05xxD The PD78F05xxD and 78F05xxDA have an on-chip debug function, which is provided p. 756 and 78F05xxDA for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. When OCD0A/X1 and OCD0B/X2 are used Input the clock from the OCD0A/X1 pin during on-chip debugging. p. 756 When using the port that controls the FLMD0 pin When using the port that controls the FLMD0 pin, make sure that it satisfies the values p. 757 of the high-level output current and FLMD0 supply voltage (minimum value: 0.8VDD) stated in CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C). Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 p. 756 pin or by using an external circuit using the P130 pin (that outputs a low level when the device is reset). Electrical PD78F05xxD The PD78F05xxD and 78F05xxDA have an on-chip debug function, which is provided p. 772 specificati and 78F05xxDA for development and evaluation. Do not use the on-chip debug function in products ons designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. - The pins mounted depend on the product. pp. 772, 774 to 777, 780 to 783, 785 to 802, 804 to 811, 813 to 830, 832 to 839, 841 to 859, 861 to 868, 870 to 887 Absolute maximum ratings R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. pp. 774, 775, 804, 805, 832, 833, 861, 862 971 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Hard Classification Chapters 30, 31, 32, 33 Chapter (29/30) Function Electrical specifications Details of Function Cautions Page Value of the current The value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. pp. 775, 805, 833, 862 X1 oscillator characteristics When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. pp. 776, 806, 834, 863 Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. pp. 776, 806, 834, 863 When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. pp. 777, 807, 835, 864 XT1 oscillator characteristics The XT1 oscillator is designed as a low-amplitude circuit for reducing power pp. 777, consumption, and is more prone to malfunction due to noise than the X1 oscillator. 807, 835, Particular care is therefore required with the wiring method when the XT1 clock is 864 used. Recommended The oscillator constants shown above are reference values based on evaluation in pp. 778, oscillator a specific environment by the resonator manufacturer. If it is necessary to optimize 779 constants the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/Kx2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 972 78K0/Kx2 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 35 Chapter (30/30) Function Details of Function Recommended PD78F05xxD soldering conditions - Cautions The PD78F05xxD has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. pp. 912, 913 Do not use different soldering methods together (except for partial heating). pp. 914, 916 PD78F05xxDA The PD78F05xxDA has an on-chip debug function, which is provided for Soft Chapter 36 development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Wait - R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 Page When the peripheral hardware clock (fPRS) is stopped, do not access the registers listed above using an access method in which a wait request is issued. pp. 915, 916 p. 918 973 78K0/Kx2 APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Description Classification R01UH0008EJ0400 R01UH0008EJ0401 pp. 97, 396, 399, 722, 723 Deletion of Note (c) p. 93 Change of Recommended Connection of Unused Pins of FLMD0 pin in Table 2-3. Pin I/O Circuit Types (a) p. 135 Change of Note 2 of Table 3-8. Special Function Register List (5/5) (c) U18598JJ3V0UD00 R01UH0008EJ0400 Throughout Deletion of "recommended" from Caution "Connect the REGC pin to VSS via a capacitor (0.47 to 1 F: recommended)." (c) CHAPTER 1 OUTLINE p. 41 Change of status of 64-pin plastic FBGA (4x4) of 78K0/KE2 from under development to mass production (b) CHAPTER 2 PIN FUNCTIONS (c) p. 69 Change of 2. 1. 3 78K0/KD2 (2) Non-port functions: 78K0/KD2 pp. 72, 73 Change of 2. 1. 4 78K0/KE2 (2) Non-port functions: 78K0/KE2 (c) Change of Table 2-3. Pin I/O Circuit Types (3/3) (c) p. 93 CHAPTER 6 CLOCK GENERATOR p. 230 Change of Caution 2 in Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KB2) (a) p. 231 Change of Caution 2 in Figure 6-4. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) (a) p. 259 Change of Figure 6-18. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) (c) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 p. 299 Change of Caution in 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input (c) CHAPTER 18 SERIAL INTERFACE IIC0 Addition of Caution to Figure 18-3. Format of IIC Shift Register 0 (IIC0) (c) p. 553 Change of description of 18.2 (2) Slave address register 0 (SVA0) (c) p. 557 Addition of Note to Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4) and change of Caution (c) p. 559 Change of Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4) (c) p. 560 Change of Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4) (c) p. 562 Change of Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3) (c) p. 553 CHAPTER 20 INTERRUPT FUNCTIONS p. 634 Change of (C) External maskable interrupt (INTKR) in Figure 20-1 Basic Configuration of Interrupt Function (c) CHAPTER 22 STANDBY FUNCTION p. 673 Addition of Note to Figure 22-4. HALT Mode Release by Reset (c) p. 680 Addition of Note to Figure 22-7. STOP Mode Release by Reset (c) CHAPTER 27 FLASH MEMORY p. 730 Change of description of 27.6.5 REGC pin (c) p. 755 Addition of 27.11 Creating ROM Code to Place Order for Previously Written Product (c) APPENDIX E REVISION HISTORY p. 975 Remark Addition of C.2 Revision History of Preceding Editions (c) "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 974 78K0/Kx2 APPENDIX E REVISION HISTORY <R> E.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/4) Edition 3nd Edition Description Addition of the conventional-specification products (PD78F05xx, 78F05xx(A), Chapter Throughout 78F05xx(A2)) Addition of the (A2) grade products of expanded-specification products (PD78F05xxA(A2)) Addition of the 64-pin plastic FBGA (4x4) package Addition of SM+ tor 78K0 Deletion of QB-78K0MINI, PG-FPL3, and FP-LITE3 (because of discontinued products) Addition of Differences Between Conventional-specification Products and Expanded-specification Products INTRODUCTION Modification of Related Documents Addition of 1.1 Differences Between Conventional-specification Products (PD78F05xx and 78F05xxD) and Expanded-specification Products (PD78F05xxA and 78F05xxDA) CHAPTER 1 OUTLINE Modification of 1.4 Ordering Information Modification of 1.8 Outline of Functions Modification of Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) (78K0/KB2, and 38-pin products and 44-pin products of the 78K0/KC2) and Table 3-2 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) (48-pin products of the 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) CHAPTER 3 CPU ARCHITECTURE Addition of description in 3.2.1 (2) Program status word (PSW) Modification of Notes 2 to 4 in Table 3-8 Special Function Register List (5/5) Addition of Caution 2 to 5.2.2 Port 1 CHAPTER 5 PORT Modification of Caution in Figure 5-17 Block Diagram of P60 and P61 and Figure FUNCTIONS 5-18 Block Diagram of P62 Addition of Caution 2 to Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KB2) and Figure 6-4 Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) CHAPTER 6 CLOCK GENERATOR Modification of Note 1 in and addition of Note 2 to Figure 6-15 Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Addition of Note to Figure 6-17 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KB2) and Figure 6-18 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) Modification of Note 1 in and addition of Note 3 to Figure 7-13 Format of Prescaler Mode Register 00 (PRM00) and Figure 7-14 Format of Prescaler Mode Register 01 (PRM01) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Modification of description in (f) 16-bit capture/compare register 00n (CR00n) in Figure 7-46 Example of Register Settings for PPG Output Operation (2/2) R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 975 78K0/Kx2 APPENDIX E REVISION HISTORY (2/4) Edition 3nd Edition Description Chapter Modification of Note 1 in and addition of Note 4 to Figure 8-5 Format of Timer CHAPTER 8 8-BIT Clock Selection Register 50 (TCL50) and Figure 8-6 Format of Timer Clock Selection Register 51 (TCL51) TIMER/EVENT COUNTERS 50 AND 51 Modification of Note 1 in and addition of Note 3 to Figure 9-5 Format of 8-Bit Timer CHAPTER 9 8-BIT H Mode Register 0 (TMHMD0) and Figure 9-6 Format of 8-Bit Timer H Mode TIMERS H0 AND H1 Register 1 (TMHMD1) Addition of Note to Figure 10-2 Format of Watch Timer Operation Mode Register (WTM) Modification of Note and description in 11.1 Functions of Watchdog Timer Modification of Note and description in 11.4.1 Controlling operation of watchdog timer CHAPTER 10 WATCH TIMER CHAPTER 11 WATCHDOG TIMER Modification of Remark in 11.4.3 Setting window open period of watchdog timer Modification of Note 1 in Figure 12-3 Format of Clock Output Selection Register (CKS) (78K0/KD2, 48-pin Products of 78K0/KC2) and Figure 12-4 Format of Clock Output Selection Register (CKS) (78K0/KE2, 78K0/KF2) CHAPTER 12 CLOCK Addition of Table 13-2 A/D Conversion Time Selection (Conventionalspecification Products CHAPTER 13 A/D OUTPUT/BUZZER OUTPUT CONTROLLER CONVERTER (PD78F05xx and 78F05xxD)) Modification of Table 13-3 A/D Conversion Time Selection (Expandedspecification Products (PD78F05xxA and 78F05xxDA)) Modification of Figure 13-6 Format of 10-Bit A/D Conversion Result Register (ADCR) Modification of Note 1 in Figure 14-4 Format of Baud Rate Generator Control Register 0 (BRGC0) CHAPTER 14 SERIAL INTERFACE UART0 Modification of Note 1 in Table 14-4 Set Value of TPS01 and TPS00 Modification of Table 14-5 Set Data of Baud Rate Generator Modification of Note 1 in Figure 15-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) CHAPTER 15 SERIAL INTERFACE UART6 Modification of Note 1 in and addition of Note 3 to Figure 15-8 Format of Clock Selection Register 6 (CKSR6) Addition of Caution 8 to Figure 15-10 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) Modification of Note 1 in 15.4.1 (1) Register used Modification of Note 1 in and addition of Note 3 to Table 15-4 Set Value of TPS63 to TPS60 Modification of Notes 1 and 2 in Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10) and Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11) CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Addition of Note 2 in and modification of Table 16-2 Relationship Between Register Settings and Pins Modification of 16.4.2 (5) SO1n output R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 976 78K0/Kx2 APPENDIX E REVISION HISTORY (3/4) Edition 3rd Edition Description Addition of Notes 2 and 5 to and modification of Note 3 in Figure 17-3 Format of Serial Status Register 0 (CSIS0) (1/2) Chapter CHAPTER 17 SERIAL INTERFACE CSIA0 Modification of Note in Figure 17-5 Format of Divisor Selection Register 0 (BRGCA0) Addition of Note 1 to Table 18-2 Selection Clock Setting CHAPTER 18 SERIAL Modification of Table 18-4 Bit Definitions of Main Extension Code INTERFACE IIC0 Modification of Figure 18-27 Example of Master to Slave Communication and Figure 18-28 Example of Slave to Master Communication Modification of Note 1 in Figure 22-3 HALT Mode Release by Interrupt Request Generation CHAPTER 22 STANDBY FUNCTION Addition of Caution 5 to Table 22-3 Operating Statuses in STOP Mode Modification of Note 2 in Figure 22-5 Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) Modification of Note in Figure 22-6 STOP Mode Release by Interrupt Request Generation Modification of Figure 23-1 Block Diagram of Reset Function CHAPTER 23 RESET Modification of Notes 3 and 4 in Table 23-2 Hardware Statuses After Reset Acknowledgment (1/4) FUNCTION Modification of Figure 24-1 Block Diagram of Power-on-Clear Circuit CHAPTER 24 POWER- Modification of Notes 1 and 2 in and addition of Note 3 to Figure 24-2 Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) ON-CLEAR CIRCUIT Modification of Note 1 in Figure 24-2 Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) Addition of Note to 25.1 Functions of Low-Voltage Detector CHAPTER 25 LOW- Modification of Note 4 in and addition of Caution 4 in Figure 25-2 Format of LowVoltage Detection Register (LVIM) VOLTAGE DETECTOR Addition of Note 2 and Caution 4 to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Modification of Figure 25-9 Example of Software Processing After Reset Release Modification of caution in 26.1 (2) 0081H/1081H CHAPTER 26 OPTION Modification of Note 1 in "Address: 0081H/1081H" in Figure 26-1 Format of Option Byte (2/2) BYTE Modification of Table 27-1 Internal Memory Size Switching Register Settings CHAPTER 27 FLASH Modification of Caution 2 in 27.2 Internal Expansion RAM Size Switching Register MEMORY Modification of Table 27-2 Internal Expansion RAM Size Switching Register Settings Modification of caution in 27.8 Security Settings Addition of Table 27-13 Processing Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) Addition of Table 27-15. Interrupt Response Time for Self Programming Library (Conventional-specification Products (PD78F05xx and 78F05xxD)) Modification of Caution in 28.1 Connecting QB-MINI2 to PD78F0503D and 78F0503DA CHAPTER 28 ON- Addition of Caution in Figure 28-3 Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging FUNCTION R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 CHIP DEBUG (PD78F0503D and 78F0503DA ONLY) 977 78K0/Kx2 APPENDIX E REVISION HISTORY (4/4) Edition 3rd Edition Description Revision of this chapter Chapter CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Revision of this chapter CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Addition of this chapter CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +110C) Addition of this chapter CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: TA = -40 to +125C) Revision of this chapter CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS Revision of this chapter APPENDIX A DEVELOPMENT TOOLS Addition of this chapter APPENDIX E REVISION HISTORY R01UH0008EJ0401 Rev.4.01 Jul 15, 2010 978 [MEMO] 78K0/Kx2 User's Manual: Hardware Publication Date: Rev.0.01 Rev.4.01 January 10, 2008 July 15, 2010 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632 Tel: +65-6213-0200, Fax: +65-6278-8001 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2010 Renesas Electronics Corporation. All rights reserved. Colophon 1.0 78K0/Kx2 R01UH0008EJ0401 (Previous Number: U18598EJ3V0UD00)