LTC2606/LTC2616/LTC2626 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface FEATURES DESCRIPTION n The LTC(R)2606/LTC2616/LTC2626 are single 16-, 14- and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic. n n n n n n n n n n n n Smallest Pin-Compatible Single DACs: LTC2606: 16 Bits LTC2616: 14 Bits LTC2626: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature 27 Selectable Addresses 400kHz I2C Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 270A at 3V Power Down to 1A, Max High Rail-to-Rail Output Drive ( 15mA, Min) Double-Buffered Data Latches Asynchronous DAC Update Pin LTC2606/LTC2616/LTC2626: Power-On Reset to Zero Scale LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset to Mid-Scale Tiny (3mm x 3mm) 10-Lead DFN Package APPLICATIONS n n n n Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and load regulation in single-supply, voltage-output DACs. The parts use a 2-wire, I2C compatible serial interface. The LTC2606/LTC2616/LTC2626 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). An asynchronous DAC update pin (LDAC) is also included. The LTC2606/LTC2616/LTC2626 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2606-1/LTC2616-1/ LTC2626-1 to mid-scale. The voltage outputs stay at midscale until a valid write and update take place. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 9 6 VCC REF Differential Nonlinearity (LTC2606) 1.0 3 SCL INPUT REGISTER DAC REGISTER 16-BIT DAC VOUT VCC = 5V VREF = 4.096V 0.8 7 0.6 0.4 DNL (LSB) I2C INTERFACE SDA 2 CONTROL LOGIC 0.2 0 -0.2 -0.4 -0.6 4 5 1 -0.8 CA0 CA1 CA2 I2C ADDRESS DECODE -1.0 LDAC GND 10 8 0 16384 32768 CODE 49152 65535 2606 G02 2606 BD 26061626fb 1 LTC2606/LTC2616/LTC2626 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Any Pin to GND ............................................- 0.3V to 6V Any Pin to VCC ............................................ -6V to 0.3V Maximum Junction Temperature...........................125C Storage Temperature Range...................-65C to 125C Lead Temperature (Soldering, 10 sec) ..................300C Operating Temperature Range: LTC2606C/LTC2616C/LTC2626C LTC2606-1C/LTC2616-1C/LTC2626-1C ...... 0C to 70C LTC2606I/LTC2616I/LTC2626I LTC2606-1I/LTC2616-1I/LTC2626-1I ......- 40C to 85C TOP VIEW 10 LDAC CA2 1 SDA 2 SCL 3 CA0 4 7 VOUT CA1 5 6 REF 9 VCC 11 8 GND DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2606CDD#PBF LTC2606CDD#TRPBF LAJX 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2606IDD#PBF LTC2606IDD#TRPBF LAJX 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2606CDD-1#PBF LTC2606CDD-1#TRPBF LAJW 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2606IDD-1#PBF LTC2606IDD-1#TRPBF LAJW 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2616CDD#PBF LTC2616CDD#TRPBF LBPQ 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2616IDD#PBF LTC2616IDD#TRPBF LBPQ 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2616CDD-1#PBF LTC2626CDD-1#TRPBF LBPR 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2616IDD-1#PBF LTC2626IDD-1#TRPBF LBPR 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2626CDD#PBF LTC2626CDD#TRPBF LBPS 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2626IDD#PBF LTC2626IDD#TRPBF LBPS 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2626CDD-1#PBF LTC2626CDD-1#TRPBF LBPT 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2626IDD-1#PBF LTC2626IDD-1#TRPBF LBPT 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2606CDD LTC2606CDD#TR LAJX 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2606IDD LTC2606IDD#TR LAJX 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2606CDD-1 LTC2606CDD-1#TR LAJW 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2606IDD-1 LTC2606IDD-1#TR LAJW 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2616CDD LTC2616CDD#TR LBPQ 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2616IDD LTC2616IDD#TR LBPQ 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2616CDD-1 LTC2616CDD-1#TR LBPR 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2616IDD-1 LTC2616IDD-1#TR LBPR 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2626CDD LTC2626CDD#TR LBPS 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2626IDD LTC2626IDD#TR LBPS 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC2626CDD-1 LTC2626CDD-1#TR LBPT 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC2626IDD-1 LTC2626IDD-1#TR LBPT 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C 26061626fb 2 LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 MIN MIN MIN TYP MAX TYP MAX TYP MAX UNITS DC Performance 12 14 16 Bits (Note 2) 12 14 16 Bits DNL Differential Nonlinearity (Note 2) INL Integral Nonlinearity (Note 2) Load Regulation VREF = VCC = 5V, Mid-Scale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.7V, Mid-Scale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking Resolution Monotonicity 0.5 1 LSB 4 16 14 64 LSB 0.025 0.125 0.05 0.125 0.1 0.2 0.5 0.5 0.5 0.7 2 2 LSB/mA LSB/mA 0.05 0.1 0.25 0.25 0.2 0.4 1 1 0.9 1.5 4 4 LSB/mA LSB/mA 1 4 1 ZSE Zero-Scale Error Code = 0 1 9 1 9 1 9 mV VOS Offset Error (Note 5) 1 9 1 9 1 9 mV VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient 5 0.1 8.5 5 0.7 0.1 8.5 5 0.7 0.1 8.5 V/C 0.7 %FSR ppm/C 26061626fb 3 LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. (Note 11) SYMBOL PARAMETER CONDITIONS MIN PSR Power Supply Rejection VCC = 10% ROUT DC Output Impedance VREF = VCC = 5V, Mid-Scale; -15mA IOUT 15mA VREF = VCC = 2.7V, Mid-Scale; -7.5mA IOUT ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND VCC = 2.7V, VREF = 2.7V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND TYP MAX UNITS -81 dB 0.05 0.06 0.15 0.15 15 15 34 36 60 60 mA mA 7.5 7.5 22 29 50 50 mA mA 0 VCC V 88 160 k Reference Input Input Voltage Range Resistance Normal Mode Capacitance IREF Reference Current, Power Down Mode 124 15 DAC Powered Down 0.001 pF 1 A 5.5 V 0.5 0.4 1 1 mA mA A A Power Supply VCC Positive Supply Voltage For Specified Performance ICC Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) DAC Powered Down (Note 3) VCC = 5V DAC Powered Down (Note 3) VCC = 3V 2.7 0.340 0.27 0.35 0.10 Digital I/O (Note 11) -0.5 (Note 8) 0.7VCC VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VIL Low Level Input Voltage (SDA and SCL) VIH High Level Input Voltage (SDA and SCL) VIL(LDAC) Low Level Input Voltage (LDAC) VIH(LDAC) High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V 0.3VCC V 0.8 0.6 V V V 2.4 2.0 V V VIL(CAn) Low Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 VIH(CAn) High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 RINH Resistance from CAn (n = 0, 1, 2) to VCC to Set CAn = VCC See Test Circuit 2 10 k RINL Resistance from CAn (n = 0, 1, 2) to GND to Set CAn = GND See Test Circuit 2 10 k RINF Resistance from CAn (n = 0, 1, 2) to VCC or GND to Set CAn = Float See Test Circuit 2 2 VOL Low Level Output Voltage Sink Current = 3mA 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 9) 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter 0 50 ns IIN Input Leakage 0.15VCC 0.85VCC V V M 0.1VCC VIN 0.9VCC 1 A (Note 4) CIN I/O Pin Capacitance 10 pF CB Capacitive Load for Each Bus Line 400 pF CCAX External Capacitive Load on Address Pins CAn (n = 0, 1, 2) 10 pF 26061626fb 4 LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 MIN MIN MIN TYP MAX TYP MAX TYP MAX UNITS AC Performance tS Settling Time (Note 6) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 7 7 9 7 9 10 s s s Settling Time for 1LSB Step (Note 7) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 2.7 2.7 4.8 2.7 4.8 5.2 s s s 0.75 0.75 0.75 V/s Voltage Output Slew Rate Capacitive Load Driving 1000 1000 1000 At Mid-Scale Transition 12 12 12 180 180 180 kHz Output Voltage Noise Density At f = 1kHz At f = 10kHz 120 100 120 100 120 100 nV/Hz nV/Hz Output Voltage Noise 0.1Hz to 10Hz 15 15 15 VP-P Glitch Impulse Multiplying Bandwidth en pF nV*s TIMING CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Notes 10, 11) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz VCC = 2.7V to 5.5V fSCL SCL Clock Frequency 0 tHD(STA) Hold Time (Repeated) Start Condition 0.6 s tLOW Low Period of the SCL Clock Pin 1.3 s tHIGH High Period of the SCL Clock Pin 0.6 s tSU(STA) Set-Up Time for a Repeated Start Condition 0.6 s tHD(DAT) Data Hold Time 0 tSU(DAT) Data Set-Up Time 100 tr Rise Time of Both SDA and SCL Signals (Note 9) 20 + 0.1CB 300 (Note 9) 20 + 0.1CB 300 0.6 0.9 s ns ns tf Fall Time of Both SDA and SCL Signals tSU(STO) Set-Up Time for Stop Condition tBUF Bus Free Time Between a Stop and Start Condition 1.3 s t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition 400 ns t2 LDAC Low Pulse Width 20 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: Guaranteed by design and not production tested. Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1), ns s code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at full-scale. Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND. Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale and half scale - 1. Load is 2k in parallel with 200pF to GND. Note 8: Maximum VIH = VCC(MAX) + 0.5V Note 9: CB = capacitance of one bus line in pF. Note 10: All values refer to VIH(MIN) and VIL(MAX) levels. Note 11: These specifications apply to LTC2606/LTC2606-1, LTC2616/ LTC2616-1, LTC2626/LTC2626-1. 26061626fb 5 LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 0.6 16 VCC = 5V VREF = 4.096V 24 16 0.4 0 -8 0.2 0 -0.2 0 -8 -0.4 -16 INL (POS) 8 INL (LSB) DNL (LSB) INL (LSB) 8 INL (NEG) -16 -0.6 -24 -32 -24 -0.8 16384 0 32768 CODE 49152 65535 -1.0 0 16384 32768 CODE 49152 2606 G01 1.5 VCC = 5.5V 24 0.6 90 VCC = 5.5V 1.0 16 0.4 DNL (POS) 0.2 0 -0.2 0 -8 DNL (NEG) -0.4 0.5 INL (POS) 8 INL (LSB) DNL (LSB) 70 DNL vs VREF INL vs VREF 32 VCC = 5V VREF = 4.096V DNL (POS) INL (NEG) 0 DNL (NEG) -0.5 -16 -0.6 -1.0 -24 -0.8 -1.0 -50 -10 10 30 50 TEMPERATURE (C) 2606 G03 DNL (LSB) 0.8 -30 2606 G02 DNL vs Temperature 1.0 -32 -50 65535 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -32 0 1 2 3 VREF (V) 2606 G04 VOUT 100V/DIV 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS -1.5 0 1 2 3 VREF (V) 4 5 2606 G06 Settling of Full-Scale Step VOUT 100V/DIV SCL 2V/DIV 5 2606 G05 Settling to 1LSB 9TH CLOCK OF 3RD DATA BYTE 4 9.7s SCR 2V/DIV 2606 G07 12.3s 9TH CLOCK OF 3RD DATA BYTE 5s/DIV 2606 G08 SETTLING TO 1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS 26061626fb 6 LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2616 Integral Nonlinearity (INL) 8 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 6 0.6 0.4 2 DNL (LSB) INL (LSB) VCC = 5V VREF = 4.096V 0.8 4 0 -2 VOUT 100V/DIV 0.2 0 9TH CLOCK OF 3RD DATA BYTE SCL 2V/DIV -0.2 -0.4 -4 -0.6 -6 -8 Settling to 1LSB 4096 8192 CODE 12288 -1.0 16383 2606 G11 2s/DIV -0.8 0 8.9s 0 4096 8192 CODE 12288 2606 G09 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 16383 2606 G10 LTC2626 Integral Nonlinearity (INL) 2.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 1.5 0.6 6.8s 0.4 0.5 DNL (LSB) INL (LSB) VCC = 5V VREF = 4.096V 0.8 1.0 0 -0.5 VOUT 1mV/DIV 0.2 0 9TH CLOCK OF 3RD DATA BYTE SCL 2V/DIV -0.2 -0.4 -1.0 -0.6 -1.5 -2.0 Settling to 1LSB 0 1024 2048 CODE 3072 -1.0 4095 2606 G14 2s/DIV -0.8 0 1024 2048 CODE 3072 2606 G12 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 4095 2606 G13 LTC2606/LTC2616/LTC2626 Current Limiting 0.06 VOUT (V) 0.04 CODE = MIDSCALE -0.06 0.4 VREF = VCC = 3V 0.2 0 -0.2 VREF = VCC = 5V -0.4 VREF = VCC = 5V VREF = VCC = 3V -0.6 -0.08 -0.10 -40 -30 -20 -10 0 10 IOUT (mA) 2 0.6 VREF = VCC = 3V 0 -0.04 CODE = MIDSCALE 0.8 VREF = VCC = 5V 0.02 -0.02 Offset Error vs Temperature 3 OFFSET ERROR (mV) 0.08 Load Regulation 1.0 VOUT (mV) 0.10 30 40 2606 G17 -1.0 -35 0 -1 -2 -0.8 20 1 -25 -15 -5 5 IOUT (mA) 15 25 35 2606 G18 -3 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 2606 G19 26061626fb 7 LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Zero-Scale Error vs Temperature Gain Error vs Temperature 3 3 0.3 2.0 1.5 1.0 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 2.5 ZERO-SCALE ERROR (mV) Offset Error vs VCC 0.4 0.1 0 -0.1 0 -1 -0.2 0.5 -2 -0.3 0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 2606 G20 0.4 -3 2.5 90 3.5 3 4 VCC (V) 4.5 5 2606 G21 Gain Error vs VCC 5.5 2606 G22 ICC Shutdown vs VCC Large-Signal Response 450 0.3 400 0.2 350 0.1 300 ICC (nA) GAIN ERROR (%FSR) 1 0 -0.1 VOUT 0.5V/DIV 250 200 VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 150 -0.2 100 -0.3 2.5s/DIV 50 -0.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 2606 G25 5.5 2606 G24 2606 G23 Mid-Scale Glitch Impulse Headroom at Rails vs Output Current Power-On Reset Glitch 5.0 5V SOURCING 4.5 TRANSITION FROM MS-1 TO MS SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE TRANSITION FROM MS TO MS-1 4.0 3.5 VCC 1V/DIV VOUT (V) VOUT 10mV/DIV 4mV PEAK VOUT 10mV/DIV 2.5s/DIV 2606 G26 3V SOURCING 3.0 2.5 2.0 1.5 5V SINKING 1.0 250s/DIV 3V SINKING 2606 G27 0.5 0 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 10 2606 G28 26061626fb 8 LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Power-On Reset to Mid-Scale Supply Current vs Logic Voltage Supply Current vs Logic Voltage 650 VREF = VCC 1.2 VCC = 5V SWEEP LDAC 0V TO VCC 600 VCC = 5V SWEEP SCL AND SDA 0V TO VCC AND VCC TO 0V 1.1 1.0 550 0.9 1V/DIV ICC (A) ICC (A) 500 450 400 VCC 350 VOUT 300 HYSTERESIS 370mV 0.8 0.7 0.6 0.5 0.4 500s/DIV 2606 G29 0.3 - 250 0 0.5 1 4 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4.5 0.2 5 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 2606 G30 4 4.5 5 2606 G31 Output Voltage Noise, 0.1Hz to 10Hz Multiplying Bandwidth 0 -3 -6 -9 -12 VOUT 10V/DIV dB -15 -18 -21 -24 -27 -30 -33 -36 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 1k 0 1 2 3 4 5 6 SECONDS 8 9 10 2606 G33 1M 10k 100k FREQUENCY (Hz) 7 2606 G32 Short-Circuit Output Current vs VOUT (Sourcing) Short-Circuit Output Current vs VOUT (Sinking) 10mA/DIV 10mA/DIV 0mA 0mA VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV 2606 G18 1V/DIV 2606 G19 26061626fb 9 LTC2606/LTC2616/LTC2626 PIN FUNCTIONS CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open-drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. SCL (Pin 3): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. CA0 (Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). REF (Pin 6): Reference Voltage Input. 0V VREF VCC. VOUT (Pin 7): DAC Analog Voltage Output. The output range is 0V to VREF. GND (Pin 8): Analog Ground. VCC (Pin 9): Supply Voltage Input. 2.7V VCC 5.5V. LDAC (Pin 10): Asynchronous DAC Update. A falling edge on this input after four bytes have been written into the part immediately updates the DAC register with the contents of the input register. A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. Software power-down is disabled when LDAC is low. Exposed Pad (Pin 11): Ground. Must be soldered to PCB ground. CA1 (Pin 5): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). 26061626fb 10 LTC2606/LTC2616/LTC2626 BLOCK DIAGRAM 3 9 6 VCC REF SCL INPUT REGISTER DAC REGISTER VOUT 16-BIT DAC 7 I2C INTERFACE SDA 2 CONTROL LOGIC 4 5 1 CA0 I2C ADDRESS DECODE CA1 CA2 LDAC GND 10 8 2606 BD TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD RINH/RINL/RINF 100 CAn CAn VIH(CAn)/VIL(CAn) GND 2606 TC 26061626fb 11 12 2 1 SCL 3 A4 4 A3 5 A2 SLAVE ADDRESS 6 A1 7 A0 8 tf tHD(STA) tr tHD(DAT) tHIGH tSU(DAT) tf tSU(STA) 9 ACK 1 C3 2 C2 3 C1 4 C0 5 X 1ST DATA BYTE LDAC SCL 6 X 7 X 1 2 Figure 2b t1 Figure 2a 9 ACK 9TH CLOCK OF 3RD DATA BYTE 8 X S Figure 1 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS S tLOW 3 2606 F02b 4 5 2ND DATA BYTE tHD(STA) 6 7 tSU(STO) tSP 8 tr 9 ACK P 1 tBUF S 2 3 2606 F01 4 5 3RD DATA BYTE 6 7 8 9 ACK t1 t2 2606 F02A TIMING DIAGRAMS LDAC A5 A6 SDA START SCL SDA LTC2606/LTC2616/LTC2626 26061626fb LTC2606/LTC2616/LTC2626 OPERATION Power-On Reset The LTC2606/LTC2616/LTC2626 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. The LTC2606-1/ LTC2616-1/LTC2626-1 set the voltage outputs to mid-scale when power is first applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2606/ LTC2616/LTC2626 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range - 0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 9) is in transition. Transfer Function The digital-to-analog transfer function is: k VOUT(IDEAL) = N VREF 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Digital Interface The LTC2606/LTC2616/LTC2626 communicate with a host using the standard 2-wire I2C interface. The Timing Diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The VCC power should not be removed from the LTC2606/LTC2616/LTC2626 when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. The LTC2606/LTC2616/LTC2626 are receive-only (slave) devices. The master can write to the LTC2606/LTC2616/ LTC2626. The LTC2606/LTC2616/LTC2626 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2606/LTC2616/LTC2626 respond to a write by a master in this manner. The LTC2606/LTC2616/LTC2626 do not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). 26061626fb 13 LTC2606/LTC2616/LTC2626 OPERATION Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC, GND or float. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 1. Table 1. Slave Address Map CA2 CA1 CA0 GND GND GND GND GND FLOAT GND GND VCC GND FLOAT GND GND FLOAT FLOAT GND FLOAT VCC GND GND VCC FLOAT GND VCC VCC GND VCC FLOAT GND GND FLOAT GND FLOAT FLOAT GND VCC FLOAT FLOAT GND FLOAT FLOAT FLOAT FLOAT FLOAT VCC GND FLOAT VCC FLOAT FLOAT VCC VCC FLOAT VCC GND GND VCC GND FLOAT VCC GND VCC VCC FLOAT GND VCC FLOAT FLOAT VCC FLOAT VCC VCC VCC GND VCC VCC FLOAT VCC VCC VCC VCC GLOBAL ADDRESS A6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2606, LTC2616 and LTC2626 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit on-chip hardwired address and is not selectable by CA0, CA1 and CA2. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 1. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. Write Word Protocol The master initiates communication with the LTC2606/ LTC2616/LTC2626 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2606/ LTC2616/LTC2626 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of data. The LTC2606/LTC2616/LTC2626 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2606/LTC2616/LTC2626 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2606/LTC2616/LTC2626 do not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command and four don't care bits. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, followed by 0, 2 or 4 don't care bits (LTC2606, LTC2616 and LTC2626 respectively). A typical LTC2606 write transaction is shown in Figure 4. The command assignments (C3-C0) are shown in Table 2. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. 26061626fb 14 LTC2606/LTC2616/LTC2626 OPERATION Write Word Protocol for LTC2606/LTC2616/LTC1626 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE C2 C1 C0 X X 3RD DATA BYTE A P INPUT WORD Input Word (LTC2606) C3 A X X 1ST DATA BYTE D15 D14 D13 D12 D11 D10 D9 2ND DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 D0 3RD DATA BYTE Input Word (LTC2616) C3 C2 C1 C0 X X X X 1ST DATA BYTE D13 D12 D11 D10 D9 D8 D7 2ND DATA BYTE D6 D5 D4 D3 D2 D1 D0 X X X X 3RD DATA BYTE Input Word (LTC2626) C3 C2 C1 C0 X X X 1ST DATA BYTE X D11 D10 D9 D8 D7 D6 2ND DATA BYTE D5 D4 D3 D2 D1 D0 X X 3RD DATA BYTE 2606 F03 Figure 3 Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever the DAC output is not needed. When in power-down, the buffer amplifier, bias circuit and reference input is disabled and draws essentially zero current. The DAC output is put into a high impedance state, and the output pin is passively pulled to ground through 90k resistors. Input- and DAC-register contents are not disturbed during power-down. performing an asychronous update (LDAC) as described in the next section. The DAC is powered up as its voltage output is updated. When the DAC in powered-down state is powered up and updated, normal settling is delayed. The main bias generation circuit block has been automatically shut down in addition to the DAC amplifier and reference input and so the power-up delay time is: 12s (for VCC = 5V) or 30s (for VCC = 3V) Asynchronous DAC Update Using LDAC Table 2 COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register 0 0 0 1 Update (Power Up) DAC Register 0 0 1 1 Write to and Update (Power Up) 0 1 0 0 Power Down 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. The DAC channel can be put into power-down mode by using command 0100b. The 16-bit data word is ignored. The supply and reference currents are reduced to almost zero when the DAC is powered down; the effective resistance at REF becomes a high impedance input (typically >1G). Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 2 or In addition to the update commands shown in Table 2, the LDAC pin asynchronously updates the DAC register with the contents of the input register. Asynchronous update is disabled when the input word is being clocked into the part. If a complete input word has been written to the part, a low on the LDAC pin causes the DAC register to be updated with the contents of the input register. If the input word is being written to the part, a low going pulse on the LDAC pin before the completion of three bytes of data powers up the DAC but does not cause the output to be updated. If LDAC remains low after a complete input word has been written to the part, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC output is updated. 26061626fb 15 LTC2606/LTC2616/LTC2626 OPERATION The DAC is powered up when LDAC is taken low, independent of any activity on the I2C bus. If LDAC is low at the falling edge of the 9th clock of the 3rd byte of data, it inhibits any software power-down command that was specified in the input word. Voltage Output The rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.050 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation performance is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.050). Note that the LTC2606/ LTC2616/LTC2626 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 26061626fb 16 X = DON'T CARE 2 1 SCL VOUT A5 A6 SDA A5 0V OUTPUT VOLTAGE 4 NEGATIVE OFFSET 3 A3 A3 6 A1 A1 7 A0 A0 1 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 X X COMMAND 6 X X 7 X X 8 X X 9 ACK 1 D15 2 D14 3 D13 4 5 D11 MS DATA D12 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 (b) OUTPUT VOLTAGE 0 (a) 32, 768 INPUT CODE VREF = VCC 65, 535 3 D5 4 INPUT CODE (c) 5 D3 LS DATA D4 VREF = VCC Figure 4. Typical LTC2606 Input Waveform--Programming DAC Output for Full Scale 9 ACK C3 INPUT CODE 8 WR Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale 5 A2 A2 SLAVE ADDRESS A4 A4 6 D2 7 D1 POSITIVE FSE 9 ACK 2606 F05 OUTPUT VOLTAGE 8 D0 ZERO-SCALE VOLTAGE 2606 F05 FULL-SCALE VOLTAGE STOP OPERATION START A6 LTC2606/LTC2616/LTC2626 26061626fb 17 LTC2606/LTC2616/LTC2626 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev B) 0.70 p0.05 3.55 p0.05 1.65 p0.05 2.15 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p0.10 (4 SIDES) R = 0.125 TYP 6 0.40 p 0.10 10 1.65 p 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN REV B 0309 5 0.200 REF 1 0.25 p 0.05 0.50 BSC 0.75 p0.05 0.00 - 0.05 2.38 p0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 26061626fb 18 LTC2606/LTC2616/LTC2626 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 11/09 Insert Text in Serial Digital Interface Section 13 26061626fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2606/LTC2616/LTC2626 TYPICAL APPLICATION Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters 5V 5V VREF 1V TO 5V 0.1F CA0 I 2C BUS CA1 CA2 10 4 2 3 5 1 9 6 LDAC VCC VREF CA0 SDA LTC2606 VOUT SCL CA1 GND CA2 8 0.1F 2 FSSET 7 100 7.5k 3 VIN 1 VCC LTC2421 100pF DAC OUTPUT 9 SCK 8 SDO 7 CS 10 FO SPI BUS ZSSET GND 5 6 2606 TA01 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5s/750A, 8s/450A LTC1655/LTC1655L Single 16-Bit VOUT DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched LTC1657/LTC1657L Parallel 5V/3V 16-Bit VOUT DACs Low Power, Deglitched, Rail-to-Rail VOUT LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2s for 10V Step LTC2600/LTC2610 LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2601/LTC2611 LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2602/LTC2612 LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2604/LTC2614 LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 26061626fb 20 Linear Technology Corporation LT 1109 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2004