LTC2606/LTC2616/LTC2626
1
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TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
16-/14-/12-Bit Rail-to-Rail DACs
with I2C Interface
The LTC
®
2606/LTC2616/LTC2626 are single 16-, 14- and
12-bit,
2.7V-to-5.5V rail-to-rail voltage output DACs in a
10-lead DFN package. They have built-in high performance
output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply, volt-
age-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
The LTC2606/LTC2616/LTC2626 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update take place.
Differential Nonlinearity
(LTC2606)
n Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits
n
Guaranteed 16-Bit Monotonic Over Temperature
n 27 Selectable Addresses
n 400kHz I2C Interface
n
Wide 2.7V to 5.5V Supply Range
n
Low Power Operation: 270μA at 3V
n
Power Down to 1μA, Max
n
High Rail-to-Rail Output Drive (±15mA, Min)
n
Double-Buffered Data Latches
n
Asynchronous DAC Update Pin
n
LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale
n
LTC2606-1/LTC2616-1/LTC2626-1: Power-On
Reset to Mid-Scale
n Tiny (3mm × 3mm) 10-Lead DFN Package
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
7
10
4
5
1
DAC
REGISTER
INPUT
REGISTER
I2C
INTERFACE
16-BIT DAC VOUT
CONTROL
LOGIC
I2C
ADDRESS
DECODE
LDAC
SCL
SDA
CA0
CA1
CA2
2606 BD
8
GND
9 6
VCC REF
3
2
CODE
0 16384 32768 49152 65535
DNL (LSB)
2606 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2606/LTC2616/LTC2626
2
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Any Pin to GND ............................................–0.3V to 6V
Any Pin to VCC ............................................ –6V to 0.3V
Maximum Junction Temperature...........................125°C
Storage Temperature Range ...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec) ..................300°C
Operating Temperature Range:
LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ...... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I ......–40°C to 85°C
(Note 1)
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1LDAC
VCC
GND
VOUT
REF
CA2
SDA
SCL
CA0
CA1
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2606CDD#PBF LTC2606CDD#TRPBF LAJX 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2606IDD#PBF LTC2606IDD#TRPBF LAJX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2606CDD-1#PBF LTC2606CDD-1#TRPBF LAJW 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2606IDD-1#PBF LTC2606IDD-1#TRPBF LAJW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2616CDD#PBF LTC2616CDD#TRPBF LBPQ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2616IDD#PBF LTC2616IDD#TRPBF LBPQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2616CDD-1#PBF LTC2626CDD-1#TRPBF LBPR 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2616IDD-1#PBF LTC2626IDD-1#TRPBF LBPR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2626CDD#PBF LTC2626CDD#TRPBF LBPS 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2626IDD#PBF LTC2626IDD#TRPBF LBPS 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2626CDD-1#PBF LTC2626CDD-1#TRPBF LBPT 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2626IDD-1#PBF LTC2626IDD-1#TRPBF LBPT 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2606CDD LTC2606CDD#TR LAJX 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2606IDD LTC2606IDD#TR LAJX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2606CDD-1 LTC2606CDD-1#TR LAJW 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2606IDD-1 LTC2606IDD-1#TR LAJW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2616CDD LTC2616CDD#TR LBPQ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2616IDD LTC2616IDD#TR LBPQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2616CDD-1 LTC2616CDD-1#TR LBPR 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2616IDD-1 LTC2616IDD-1#TR LBPR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2626CDD LTC2626CDD#TR LBPS 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2626IDD LTC2626IDD#TR LBPS 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2626CDD-1 LTC2626CDD-1#TR LBPT 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2626IDD-1 LTC2626IDD-1#TR LBPT 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2606/LTC2616/LTC2626
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ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution ●12 14 16 Bits
Monotonicity (Note 2) ●12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ●±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) ●± 1 ±4 ±4 ±16 ±14 ±64 LSB
Load Regulation VREF = VCC = 5V, Mid-Scale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
●
●
0.025
0.05
0.125
0.125
0.1
0.2
0.5
0.5
0.5
0.7
2
2
LSB/mA
LSB/mA
VREF = VCC = 2.7V, Mid-Scale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
●
●
0.05
0.1
0.25
0.25
0.2
0.4
1
1
0.9
1.5
4
4
LSB/mA
LSB/mA
ZSE Zero-Scale Error Code = 0 ●19 19 19 mV
VOS Offset Error (Note 5) ●±1 ±9 ±1 ±9 ±1 ±9 mV
VOS Temperature
Coeffi cient
±5 ±5 ±5 μV/°C
GE Gain Error ●±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR
Gain Temperature
Coeffi cient
±8.5 ±8.5 ±8.5 ppm/°C
LTC2606/LTC2616/LTC2626
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ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted. (Note 11)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC = ±10% –81 dB
ROUT DC Output Impedance VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.7V, Mid-Scale; –7.5mA ≤ IOUT ≤
●
●
0.05
0.06 0.15
0.15 Ω
Ω
ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
●
●
15
15 34
36 60
60 mA
mA
VCC = 2.7V, VREF = 2.7V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
●
●
7.5
7.5 22
29 50
50 mA
mA
Reference Input
Input Voltage Range ●0V
CC V
Resistance Normal Mode ●88 124 160 kΩ
Capacitance 15 pF
IREF Reference Current, Power Down Mode DAC Powered Down ●0.001 1 μA
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance ●2.7 5.5 V
ICC Supply Current VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
●
●
●
●
0.340
0.27
0.35
0.10
0.5
0.4
1
1
mA
mA
μA
μA
Digital I/O (Note 11)
VIL Low Level Input Voltage (SDA and SCL) ●–0.5 0.3VCC V
VIH High Level Input Voltage (SDA and SCL) (Note 8) ●0.7VCC V
VIL(LDAC)Low Level Input Voltage (LDAC)V
CC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
●
●
0.8
0.6 V
V
VIH(LDAC)High Level Input Voltage (LDAC)V
CC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
●
●
2.4
2.0 V
V
VIL(CA
n
)Low Level Input Voltage on CA
n
(
n
= 0, 1, 2) See Test Circuit 1 ●0.15VCC V
VIH(CA
n
)High Level Input Voltage on CA
n
(
n
= 0, 1, 2) See Test Circuit 1 ●0.85VCC V
RINH Resistance from CA
n
(
n
= 0, 1, 2)
to VCC to Set CA
n
= VCC
See Test Circuit 2 ●10 kΩ
RINL Resistance from CA
n
(
n
= 0, 1, 2)
to GND to Set CA
n
= GND See Test Circuit 2 ●10 kΩ
RINF Resistance from CA
n
(
n
= 0, 1, 2)
to VCC or GND to Set CA
n
= Float See Test Circuit 2 ●2MΩ
VOL Low Level Output Voltage Sink Current = 3mA ●0 0.4 V
tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 9)
●20 + 0.1CB250 ns
tSP Pulse Width of Spikes Suppressed
by Input Filter
●050ns
IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC ●1μA
CIN I/O Pin Capacitance (Note 4) ●10 pF
CBCapacitive Load for Each Bus Line ●400 pF
CCAX External Capacitive Load on Address
Pins CA
n
(
n
= 0, 1, 2)
●10 pF
LTC2606/LTC2616/LTC2626
5
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TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
fSCL SCL Clock Frequency ●0 400 kHz
tHD(STA) Hold Time (Repeated) Start Condition ●0.6 μs
tLOW Low Period of the SCL Clock Pin ●1.3 μs
tHIGH High Period of the SCL Clock Pin ●0.6 μs
tSU(STA) Set-Up Time for a Repeated Start Condition ●0.6 μs
tHD(DAT) Data Hold Time ●0 0.9 μs
tSU(DAT) Data Set-Up Time ●100 ns
trRise Time of Both SDA and SCL Signals (Note 9) ●20 + 0.1CB300 ns
tfFall Time of Both SDA and SCL Signals (Note 9) ●20 + 0.1CB300 ns
tSU(STO) Set-Up Time for Stop Condition ●0.6 μs
tBUF Bus Free Time Between a Stop and Start Condition ●1.3 μs
t1Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
●400 ns
t2LDAC Low Pulse Width ●20 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defi ned from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defi ned from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full-scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and
3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 8: Maximum VIH = VCC(MAX) + 0.5V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifi cations apply to LTC2606/LTC2606-1, LTC2616/
LTC2616-1, LTC2626/LTC2626-1.
The ● denotes specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (See Figure 1) (Notes 10, 11)
ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tSSettling Time (Note 6) ±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
77
9
7
9
10
μs
μs
μs
Settling Time for 1LSB Step
(Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7 2.7
4.8
2.7
4.8
5.2
μs
μs
μs
Voltage Output Slew Rate 0.75 0.75 0.75 V/μs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Mid-Scale Transition 12 12 12 nV•s
Multiplying Bandwidth 180 180 180 kHz
enOutput Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 μVP-P
LTC2606/LTC2616/LTC2626
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
DNL vs Temperature INL vs VREF DNL vs VREF
Settling to ±1LSB Settling of Full-Scale Step
LTC2606
CODE
016384 32768 49152 65535
INL (LSB)
2606 G01
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
CODE
0 16384 32768 49152 65535
DNL (LSB)
2606 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
INL (LSB)
2606 G03
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
DNL (LSB)
2606 G04
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
DNL (POS)
DNL (NEG)
VREF (V)
012345
INL (LSB)
2606 G05
32
24
16
8
0
–8
–16
–24
–32
VCC = 5.5V
INL (POS)
INL (NEG)
VREF (V)
012345
DNL (LSB)
2606 G06
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5.5V
DNL (POS)
DNL (NEG)
2μs/DIV 2606 G07
VOUT
100μV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
9.7μs
9TH CLOCK
OF 3RD DATA
BYTE
5μs/DIV 2606 G08
VOUT
100μV/DIV
SCR
2V/DIV
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
12.3μs
9TH CLOCK OF
3RD DATA BYTE
LTC2606/LTC2616/LTC2626
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Current Limiting Load Regulation Offset Error vs Temperature
LTC2616
LTC2626
LTC2606/LTC2616/LTC2626
CODE
04096 8192 12288 16383
INL (LSB)
2606 G09
8
6
4
2
0
–2
–4
–6
–8
VCC = 5V
VREF = 4.096V
CODE
0 4096 8192 12288 16383
DNL (LSB)
2606 G10
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
2μs/DIV 2606 G11
VOUT
100μV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
8.9μs
9TH CLOCK
OF 3RD DATA
BYTE
CODE
01024 2048 3072 4095
INL (LSB)
2606 G12
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
VCC = 5V
VREF = 4.096V
CODE
0 1024 2048 3072 4095
DNL (LSB)
2606 G13
VCC = 5V
VREF = 4.096V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2μs/DIV 2606 G14
VOUT
1mV/DIV
SCL
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
6.8μs
9TH CLOCK
OF 3RD DATA
BYTE
IOUT (mA)
–40 –30 –20 –10 0 10 20 30 40
ΔVOUT (V)
2606 G17
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
VREF = VCC = 5V
VREF = VCC = 3V
VREF = VCC = 5V
VREF = VCC = 3V
CODE = MIDSCALE
IOUT (mA)
–35 –25 –15 –5 5 15 25 35
ΔVOUT (mV)
2606 G18
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VREF = VCC = 5V
CODE = MIDSCALE
VREF = VCC = 3V
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
OFFSET ERROR (mV)
2606 G19
3
2
1
0
–1
–2
–3
LTC2606/LTC2616/LTC2626
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TYPICAL PERFORMANCE CHARACTERISTICS
Zero-Scale Error vs Temperature Gain Error vs Temperature Offset Error vs VCC
Gain Error vs VCC ICC Shutdown vs VCC Large-Signal Response
Mid-Scale Glitch Impulse Power-On Reset Glitch
Headroom at Rails
vs Output Current
LTC2606/LTC2616/LTC2626
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
ZERO-SCALE ERROR (mV)
2606 G20
3
2.5
2.0
1.5
1.0
0.5
0
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
GAIN ERROR (%FSR)
2606 G21
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
OFFSET ERROR (mV)
2606 G22
3
2
1
0
–1
–2
–3
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
GAIN ERROR (%FSR)
2606 G23
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
ICC (nA)
2606 G24
450
400
350
300
250
200
150
100
50
0
2.5μs/DIV
VOUT
0.5V/DIV
2606 G25
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
VOUT
10mV/DIV
SCL
2V/DIV
2.5μs/DIV 2606 G26
TRANSITION FROM
MS-1 TO MS
TRANSITION FROM
MS TO MS-1
9TH CLOCK
OF 3RD DATA
BYTE
VOUT
10mV/DIV
250μs/DIV 2606 G27
VCC
1V/DIV
4mV PEAK
IOUT (mA)
012345678910
VOUT (V)
2606 G28
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
3V SOURCING
3V SINKING
5V SINKING
LTC2606/LTC2616/LTC2626
9
26061626fb
TYPICAL PERFORMANCE CHARACTERISTICS
Power-On Reset to Mid-Scale Supply Current vs Logic Voltage Supply Current vs Logic Voltage
Multiplying Bandwidth
Output Voltage Noise,
0.1Hz to 10Hz
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
LTC2606/LTC2616/LTC2626
1V/DIV
500μs/DIV 2606 G29
VCC
VOUT
VREF = VCC
LOGIC VOLTAGE (V)
0
ICC (μA)
650
600
550
500
450
400
350
300
– 250 4
2606 G30
123 53.50.5 1.5 2.5 4.5
VCC = 5V
SWEEP LDAC
0V TO VCC
LOGIC VOLTAGE (V)
0
ICC (μA)
0.8
1.0
1.2
4
2606 G31
0.6
0.4
0.7
0.9
1.1
0.5
0.3
0.2 10.5 21.5 3 3.5 4.5
2.5 5
HYSTERESIS
370mV
VCC = 5V
SWEEP SCL AND
SDA 0V TO VCC
AND VCC TO 0V
FREQUENCY (Hz)
1k
dB
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36 1M
2606 G32
10k 100k
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
VOUT
10μV/DIV
SECONDS
012345678910
2606 G33
1V/DIV
10mA/DIV
0mA
2606 G18
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
1V/DIV
10mA/DIV
0mA
2606 G19
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
LTC2606/LTC2616/LTC2626
10
26061626fb
PIN FUNCTIONS
CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it fl oating to select an I2C slave address for the
part (Table 1).
SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open-drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to VCC.
SCL (Pin 3): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
CA0 (Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it fl oating to select an I2C slave address for the
part (Table 1).
CA1 (Pin 5): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it fl oating to select an I2C slave address for the
part (Table 1).
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT (Pin 7): DAC Analog Voltage Output. The output
range is 0V to VREF
.
GND (Pin 8): Analog Ground.
VCC (Pin 9): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
LDAC (Pin 10): Asynchronous DAC Update. A falling edge
on this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part does not update the DAC output. Soft-
ware power-down is disabled when LDAC is low.
Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.
LTC2606/LTC2616/LTC2626
11
26061626fb
BLOCK DIAGRAM
TEST CIRCUITS
7
10
4
5
1
DAC
REGISTER
INPUT
REGISTER
I2C
INTERFACE
16-BIT DAC VOUT
CONTROL
LOGIC
I2C
ADDRESS
DECODE
LDAC
SCL
SDA
CA0
CA1
CA2
2606 BD
8
GND
9 6
VCC REF
3
2
100ΩRINH/RINL/RINF
VIH(CAn)/VIL(CAn)
CAn
GND
2606 TC
VDD
Test Circuit 2Test Circuit 1
CAn
LTC2606/LTC2616/LTC2626
12
26061626fb
TIMING DIAGRAMS
Figure 1
Figure 2b
Figure 2a
SDA
tf
S
tr
tLOW
tHD(STA)
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
tHD(DAT)
tSU(DAT)
tSU(STA)
tHD(STA)
tSU(STO)
tSP tBUF
tr
tf
tHIGH
SCL
S P S 2606 F01
ACK ACK
123456789123456789123456789123456789
2606 F02A
ACK
t1
START
SDA A6 A5 A4 A3
SLAVE ADDRESS
A2 A1 A0
SCL
LDAC
C2C3 C1 C0 X X X X ACK
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
t2
9TH CLOCK
OF 3RD
DATA BYTE
t1
SCL
LDAC
2606 F02b
LTC2606/LTC2616/LTC2626
13
26061626fb
OPERATION
Power-On Reset
The LTC2606/LTC2616/LTC2626 clear the outputs to
zero-scale when power is fi rst applied, making system
initialization consistent and repeatable. The LTC2606-1/
LTC2616-1/LTC2626-1 set the voltage outputs to mid-scale
when power is fi rst applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2606/
LTC2616/LTC2626 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 9) is in transition.
Transfer Function
The digital-to-analog transfer function is:
VOUT(IDEAL) =k
2N
⎛
⎝
⎜⎞
⎠
⎟VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Digital Interface
The LTC2606/LTC2616/LTC2626 communicate with a
host using the standard 2-wire I2C interface. The Timing
Diagrams (Figures 1 and 2) show the timing relationship
of the signals on the bus. The two bus lines, SDA and
SCL, must be high when the bus is not in use. External
pull-up resistors or current sources are required on these
lines. The value of these pull-up resistors is dependent
on the power supply and can be obtained from the I2C
specifi cations. For an I2C bus operating in the fast mode,
an active pull-up will be necessary if the bus capacitance is
greater than 200pF. The VCC power should not be removed
from the LTC2606/LTC2616/LTC2626 when the I2C bus
is active to avoid loading the I2C bus lines through the
internal ESD protection diodes.
The LTC2606/LTC2616/LTC2626 are receive-only (slave)
devices. The master can write to the LTC2606/LTC2616/
LTC2626. The LTC2606/LTC2616/LTC2626 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has fi nished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2606/LTC2616/LTC2626 respond to a write by a
master in this manner. The LTC2606/LTC2616/LTC2626
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
LTC2606/LTC2616/LTC2626
14
26061626fb
OPERATION
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: VCC, GND or fl oat. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Table 1. Slave Address Map
CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND VCC 0010010
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT VCC 0100001
GND VCC GND 0 1 0 0 0 1 0
GND VCC FLOAT 0 1 0 0 0 1 1
GND VCC VCC 01100 00
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND VCC 0110011
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT VCC 1000010
FLOAT VCC GND 1 0 0 0 0 1 1
FLOAT VCC FLOAT 1 0 1 0 0 0 0
FLOAT VCC VCC 1010001
VCC GND GND 1 0 1 0 0 1 0
VCC GND FLOAT 1 0 1 0 0 1 1
VCC GND VCC 11000 00
VCC FLOAT GND 1 1 0 0 0 0 1
VCC FLOAT FLOAT 1 1 0 0 0 1 0
VCC FLOAT VCC 1100011
VCC VCC GND 1 1 1 0 0 0 0
VCC VCC FLOAT 1 1 1 0 0 0 1
VCC VCC VCC 11100 10
GLOBAL ADDRESS 1 1 1 0 0 1 1
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are fl oating.
Write Word Protocol
The master initiates communication with the LTC2606/
LTC2616/LTC2626 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data. The LTC2606/LTC2616/LTC2626 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete
bytes of data, the LTC2606/LTC2616/LTC2626 executes the
command specifi ed in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do not
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
The format of the three data bytes is shown in Figure 3.
The fi rst byte of the input word consists of the 4-bit com-
mand and four don’t care bits. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626
respectively).
A typical LTC2606 write transaction is shown
in Figure 4.
The command assignments (C3-C0) are shown in Table 2.
The fi rst four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an
analog voltage at the DAC output. The update operation
also powers up the DAC if it had been in power-down
mode. The data path and registers are shown in the Block
Diagram.
LTC2606/LTC2616/LTC2626
15
26061626fb
OPERATION
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifi er, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into a
high impedance state, and the output pin is passively pulled
to ground through 90k resistors. Input- and DAC-register
contents are not disturbed during power-down.
Table 2
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
*Command codes not shown are reserved and should not be used.
The DAC channel can be put into power-down mode by
using command 0100b. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective resis-
tance at REF becomes a high impedance input (typically
>1GΩ).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2 or
performing an asychronous update (LDAC) as described
in the next section. The DAC is powered up as its voltage
output is updated. When the DAC in powered-down state
is powered up and updated, normal settling is delayed. The
main bias generation circuit block has been automatically
shut down in addition to the DAC amplifi er and reference
input and so the power-up delay time is:
12μs (for VCC = 5V) or 30μs (for VCC = 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2,
the LDAC pin asynchronously updates the DAC register
with the contents of the input register. Asynchronous
update is disabled when the input word is being clocked
into the part.
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recognized,
the command specifi ed in the 24-bit word just transferred
is executed and the DAC output is updated.
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2606)
Write Word Protocol for LTC2606/LTC2616/LTC1626
C2 C1 C0 XXXXD13D14D15
SWA
SLAVE ADDRESS 1ST DATA BYTE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A 2ND DATA BYTE A 3RD DATA BYTE A P
2606 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2616)
C2 C1 C0 XXXXD11D12D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
2ND DATA BYTE 3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2626)
C2 C1 C0 XXXXD9D10D11 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
2ND DATA BYTE 3RD DATA BYTE
LTC2606/LTC2616/LTC2626
16
26061626fb
OPERATION
The DAC is powered up when LDAC is taken low, inde-
pendent of any activity on the I2C bus.
If LDAC is low at the falling edge of the 9th clock of the
3rd byte of data, it inhibits any software power-down
command that was specifi ed in the input word.
Voltage Output
The rail-to-rail amplifi er has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
3V).
Load regulation is a measure of the amplifi er’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifi ers’ DC output
impedance is 0.050Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails
vs Output Current in the Typical Performance Charac-
teristics section.
The amplifi er is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation performance is achieved in
part by keeping “signal” and “power” grounds separated
internally and by reducing shared internal resistance.
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here
will add directly to the effective DC output impedance
of the device (typically 0.050Ω). Note that the LTC2606/
LTC2616/LTC2626 are no more susceptible to these ef-
fects than other parts of their type; on the contrary, they
allow layout-based performance improvements to shine
rather than limiting attainable performance with excessive
internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 5c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting
can occur.
LTC2606/LTC2616/LTC2626
17
26061626fb
OPERATION
Figure 4. Typical LTC2606 Input Waveform—Programming DAC Output for Full Scale
ACK ACK
123456789123456789123456789123456789
2606 F05
ACK
START
X = DON’T CARE
STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA A6 A5 A4 A3 A2 A1 A0
SCL
VOUT
C2C3
C3 C2 C1 C0 X X X X
C1 C0 X X X X ACK
COMMAND
D15 D14 D13 D12 D11 D10 D9 D8
MS DATA
D7 D6 D5 D4 D3 D2 D1 D0
LS DATA
A6 A5 A4 A3 A2 A1 A0 WR
SLAVE ADDRESS
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2606 F05
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 7680 65, 535
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC2606/LTC2616/LTC2626
18
26061626fb
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
2.38 p0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV B 0309
0.25 p 0.05
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)2.15 p0.05
0.50
BSC
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
LTC2606/LTC2616/LTC2626
19
26061626fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 11/09 Insert Text in Serial Digital Interface Section 13
(Revision history begins at Rev B)
LTC2606/LTC2616/LTC2626
20
26061626fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 1109 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters
LDAC
CA0
SDA
SCL
CA1
CA2
SCK
SDO
CS
FO
9
8
7
10
10
4
2
3
5
1
7
56
296 1
2606 TA01
3
100Ω7.5k
0.1μF
8
VOUT
CA0
CA1
CA2
I2C BUS
VCC
LTC2606
GND
5V
VREF
1V TO 5V
DAC
OUTPUT
VREF VCC
GND
VIN LTC2421
FSSET
ZSSET
0.1μF
SPI BUS
5V
100pF
PART NUMBER DESCRIPTION COMMENTS
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA
LTC1655/LTC1655L Single 16-Bit VOUT DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parallel 5V/3V 16-Bit VOUT DACs Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step
LTC2600/LTC2610
LTC2620
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2601/LTC2611
LTC2621
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2602/LTC2612
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2604/LTC2614
LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
