PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83905 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. * 6 LVCMOS / LVTTL outputs The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905 ideal for high performance, single ended applications that also require a limited output voltage. * Operating supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3Vcore/2.5V or1.8V operating supply, and mixed 2.5V core/1.8V operating supply ICS * Crystal oscillator interface * Output frequency range: 10MHz to 50MHz * Crystal input frequency range: 10MHz to 50MHz * Output skew: 10ps (typical) * 5V tolerant enable inputs * Synchronous output enables * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant * Pin compatible to MPC905 * Industrial version available upon request BLOCK DIAGRAM PIN ASSIGNMENT BCLK0 BCLK1 XTAL_IN BCLK2 XTAL_OUT 1 2 3 4 5 6 7 8 XTAL_OUT ENABLE 2 GND BCLK0 VDD o BCLK1 GND BCLK2 16 15 14 13 12 11 10 9 XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD ICS83905 BCLK3 BCLK4 ICS83905 nc ENABLE1 20 19 18 17 16 ICS83905 15 GND 1 GND 2 20-Lead VFQFN 14 4mm x 4mm x 0.9mm body package 13 4 K Package 12 VDDO BCLK0 3 BCLK4 Top View GND 6 7 8 GND BCLK2 5 GND VDDO BCLK1 11 BCLK5 GND 9 10 BCLK3 SYNCHRONIZE ENABLE2 ENABLE 2 XTAL_IN BCLK5 16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm body package G Pacakge Top View VDD SYNCHRONIZE XTAL_OUT ENABLE 1 16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package M Pacakge Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 83905AM http://www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Name Type Description XTAL_OUT Output XTAL_IN Input Cr ystal oscillator interface. XTAL_IN is the input. Cr ystal oscillator interface. XTAL_OUT is the output. ENABLE 1, ENABLE2 BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 GND Input Output enable. LVCMOS / LVTTL interface levels. Output Clock outputs. LVCMOS / LVTTL interface levels. Power Power supply ground. VDD Power Core supply pin. VDDO Power Output supply pin. n/c Unused No connect. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance C PD Power Dissipation Capacitance (per output) Minimum Typical 4 TABLE 3. OUTPUT ENABLE AND 19 pF 18 pF 16 pF 12 5 7 VDDO = 2.5V 5% 7 VDDO = 1.8V 0.2V 10 CLOCK ENABLE FUNCTION TABLE Control Inputs Outputs ENABLE 1 ENABLE 2 BCLK0:BCLK4 BCLK5 0 0 LOW LOW 0 1 LOW Toggling 1 0 Toggling LOW 1 1 Toggling Toggling 83905AM pF VDDO = 3.465V VDDO = 2V Output Impedance Units VDDO = 2.625V VDDO = 3.3V 5% ROUT Maximum http://www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VDD + 0.5 V Maximum Ratings may cause permanent damage to the Outputs, VO -0.5V to VDDO + 0.5V device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- Package Thermal Impedance, JA 16 Lead SOIC package 16 Lead TSSOP package 20 Lead VFQFN package 78.8C/W (0 mps) 89C/W (0 lfpm) 38.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDO Output Supply Voltage IDD Power Supply Current TBD A V IDDO Output Supply Current TBD A TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current TBD A IDDO Output Supply Current TBD A TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current TBD A IDDO Output Supply Current TBD A TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current TBD A IDDO Output Supply Current TBD A 83905AM http://www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.8 2.0 VDDO Output Supply Voltage IDD Power Supply Current 1.6 TBD A V IDDO Output Supply Current TBD A TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 1.8 2.0 VDDO Output Supply Voltage IDD Power Supply Current 1.6 TBD A V IDDO Output Supply Current TBD A TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0C TO 70C Symbol VIH VIL VOH Parameter Input High Voltage Input Low Voltage Output High Voltage ENABLE1, ENABLE2 ENABLE1, ENABLE2 Test Conditions Minimum VDD = 3.3V 5% 2 Output Low Voltage Maximum Units VDD + 0.3 V VDD = 2.5V 5% 1.7 VDD + 0.3 V VDD = 1.8V 0.2V 0.65*VDD VDD + 0.3 V VDD = 3.3V 5% -0.3 1.3 V VDD = 2.5V 5% -0.3 0.7 V VDD = 1.8V 0.2V -0.3 0.35*VDD V VDDO = 3.3V 5%; NOTE 1 2.6 V VDDO = 2.5V 5%; IOH = -1mA 2 V VDDO = 2.5V 5%; NOTE 1 1.8 V VDDO = 1.8V 0.2V; NOTE 1 VDD - 0.3 VDDO = 3.3V 5%; NOTE 1 VOL Typical V 0.5 V VDDO = 2.5V 5%; IOL = 1mA 0.4 V VDDO = 2.5V 5%; NOTE 1 0.45 V VDDO = 1.8V 0.2V; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. 83905AM http://www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz HIGH (above 2V); NOTE 1 t PW Output Pulse Width 0.5T LOW (below 0.8V), NOTE 2 0.5T T = Periods HIGH (above 2V); NOTE 1 0.5T LOW (below 0.8V), NOTE 2 0.5T tPER Output Period T = desired Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; NOTE 4 TBD 10 ps 500 ps E NA B LE 1 TBD ms E NA B LE 2 TBD ms tDIS Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 TBD ms TBD ms A OSC XTAL_IN to XTAL_OUT Oscillator Gain TBD db Phase Loop Phase Shift Modulo 360+ TBD 20% to 80% All parameters measured at fMAX unless noted otherwise. NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met. NOTE 2: Assuming external crystal or 50% duty cycle external reference is used. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz fMAX Output Frequency odc Output Duty Cycle t PER Output Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 tDIS Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 A OSC Phase 50 % TBD 10 ps 500 ps TBD ms TBD ms TBD ms TBD ms XTAL_IN to XTAL_OUT Oscillator Gain TBD db Loop Phase Shift Modulo 360+ TBD 20% to 80% See notes from Table 5A. 83905AM http://www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz fMAX Output Frequency odc Output Duty Cycle tPER Output Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 tDIS Output Disable Time; ENABLE 1 NOTE 4 E NA B LE 2 A OSC Phase 50 % TBD 10 ps 550 ps TBD ms TBD ms TBD ms TBD ms XTAL_IN to XTAL_OUT Oscillator Gain TBD db Loop Phase Shift Modulo 360+ TBD 20% to 80% See notes from Table 5A. TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz fMAX Output Frequency odc Output Duty Cycle t PER Output Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 tDIS Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 A OSC Phase 50 % TBD 10 ps 500 ps TBD ms TBD ms TBD ms TBD ms XTAL_IN to XTAL_OUT Oscillator Gain TBD db Loop Phase Shift Modulo 360+ TBD 20% to 80% See notes from Table 5A. 83905AM http://www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 5E. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz fMAX Output Frequency tPW Output Pulse Width tPER Output Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 tDIS Output Disable Time; ENABLE 1 NOTE 4 E NA B LE 2 A OSC Phase 50 % TBD 10 ps 550 ps TBD ms TBD ms TBD ms TBD ms XTAL_IN to XTAL_OUT Oscillator Gain TBD db Loop Phase Shift Modulo 360+ TBD 20% to 80% See notes from Table 5A. TABLE 5F. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 50 MHz Using External Clock Source DC 100 MHz fMAX Output Frequency odc Output Duty Cycle tPER Output Period tsk(o) Output Skew; NOTE 3, 5 tR/tF Output Rise/Fall Time t EN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 A OSC Phase 50 % TBD 10 ps 550 ps ENABLE 1 TBD ms E NA B LE 2 TBD ms ENABLE 1 TBD ms ENABLE 2 TBD ms XTAL_IN to XTAL_OUT Oscillator Gain TBD db Loop Phase Shift Modulo 360+ TBD 20% to 80% See notes from Table 5A. 83905AM http://www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.25V5% 1.65V5% SCOPE VDD, VDDO Qx LVCMOS LVCMOS GND Qx GND -1.165V5% 3.3V SCOPE VDD, VDDO CORE/3.3V -1.25V5% OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V5% 0.9V0.1V SCOPE VDD, VDDO 1.25V5% SCOPE VDD VDDO LVCMOS Qx LVCMOS Qx GND GND -0.9V 0.1V -1.25V5% 1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.40.9V 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V0.025% 0.9V0.1V 0.9V0.1V SCOPE V DD VDDO LVCMOS VDDO Qx LVCMOS Qx GND GND -0.9V0.1V -0.9V0.1V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 83905AM SCOPE V DD 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT http://www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER V DD V DDO Qx 2 BCLKx 2 Pulse Width t V PERIOD DDO Qy 2 t sk(o) odc = t PW t PERIOD OUTPUT SKEW Clock Outputs OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% tR tF 20% 20% OUTPUT RISE/FALL TIME 83905AM http://www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION CRYSTAL INPUT INTERFACE, FUNDAMENTAL racy ppm. The optimum C1 and C2 values can be adjusted to improve the frequency accuracy for stray capacitance of different board layout. Figure 1A shows an example of ICS83905 crystal interface with parallel resonance crystal using fundamental frequency. The C1, C2 and R1 values are suggested for the best frequency accu- XTAL_IN C1 10p X1 R1 XTAL_OUT C2 16p 100 FIGURE 1A. CRYSTAL OSCILLATOR INTERFACE, (FUNDAMENTAL) CRYSTAL INPUT INTERFACE, 3RD OVERTONE Figure 1B shows an example of ICS83905 crystal interface with parallel resonance crystal using 3rd overtone frequency. The C1, C2 values are suggested for the best frequency accuracy ppm. The optimum C1 and C2 values can be adjusted to improve the frequency accuracy for stray capacitance of different board layout. The C3 and L1 can be calculated from the given equation. F _ fund = XTAL_IN C1 10p 1 2 L1 * C 3 X1 XTAL_OUT C2 16p C3 L1 FIGURE 1B. CRYSTAL OSCILLATOR INTERFACE (3RD OVERTONE) 83905AM http://www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6A. JAVS. AIR FLOW TABLE 16 LEAD SOIC FOR JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards TABLE 6B. JAVS. AIR FLOW TABLE FOR 0 1 2 78.8C/W 71.1C/W 66.2C/W 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1C/W 89.0C/W 118.2C/W 81.8C/W 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6C. JAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN JA by Velocity (Meters per Second) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 141.7C/W 38.5C/W 126C/W 35C/W 116.9C/W 33.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83905 is: 339 83905AM http://www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER FOR FOR 16 LEAD SOIC MINIMUM FOR TABLE 7B. PACKAGE DIMENSIONS Millimeters N A PACKAGE OUTLINE - G SUFFIX 16 LEAD SOIC TABLE 7A. PACKAGE DIMENSIONS SYMBOL ICS83905 SYMBOL MAXIMUM 16 16 LEAD TSSOP FOR TSSOP Millimeters Minimum N Maximum 16 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 b D 9.80 10.00 c 0.09 0.20 E 3.80 4.00 D 4.90 5.10 e A 1.27 BASIC -- 1.20 A1 0.05 0.15 A2 0.80 1.05 0.19 0.30 E 6.40 BASIC H 5.80 6.20 E1 h 0.25 0.50 e L 0.40 1.27 L 0.45 0.75 0 8 Reference Document: JEDEC Publication 95, MS-012 0 8 aaa -- 0.10 4.30 4.50 0.65 BASIC Reference Document: JEDEC Publication 95, MO-153 83905AM http://www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER 20 LEAD VFQFN TABLE 7C. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM A 0.80 A1 0 1.0 0.05 0.25 Reference A3 b MAXIMUM 20 N 0.18 0.30 e 0.50 BASIC ND 5 NE 5 D 4.0 D2 0.75 2.80 4.0 E E2 0.75 2.80 L 0.35 0.75 Reference Document: JEDEC Publication 95, MO-220 83905AM http://www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83905 LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83905AM 83905AM 16 Lead SOIC tube 0C to 70C ICS83905AMT 83905AM 16 Lead SOIC 2500 tape & reel 0C to 70C ICS83905AMLF 83905AML 16 Lead "Lead-Free" SOIC tube 0C to 70C ICS83905AMLFT 83905AML 16 Lead "Lead-Free" SOIC 2500 tape & reel 0C to 70C ICS83905AG TBD 16 Lead TSSOP tube 0C to 70C ICS83905AGT TBD 16 Lead TSSOP 2500 tape & reel 0C to 70C ICS83905AK 83905A 20 Lead VFQFN tube 0C to 70C ICS83905AKT 83905A 20 Lead VFQFN 2500 tape & reel 0C to 70C The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83905AM http://www.icst.com/products/hiperclocks.html 14 REV. A JANUARY 20, 2005