User Guide 1.0 IRAC11662-100W +16V Low-side Smart Rectification 100W Flyback Demo Board User's Guide by HELEN DING, ISRAEL SERRANO 19 April 2010 Rev.1A 19 April 2010 UG #1.0 Page 1 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Table of Contents 1.0 INTRODUCTION 2.0 GENERAL DESCRIPTION 2.1 IRAC11662-100W +16V Demo Board Schematic Diagram 2.2 IRAC11662-100W +16V Demo Board Pictures 2.3 IRAC11662-100W +16V Demo Board PCB Layout 3.0 Circuit Description 4.0 Test Connection and Set up Pictures 5.0 Circuit Features 5.1 OVT Setting 5.2 ENABLE Setting 5.3 MOT Setting 5.4 Mosfet Selection Design Tips 6.0 Test Waveforms 6.1.1 Transient Load Test 6.1.2 Static Load Test 6.1.3 Ripple And Noise Measurement 6.1.4 Dynamic load Test 7.0 Line / Load Regulation Test 7.1 IR11662 Demo Board V-I Characteristics Curve 7.2 System Efficiency Test 7.3 Thermal Verification 8.0 Summary 9.0 Appendix 9.1 Transformer turns ratio, Duty Cycle and Secondary Current Relationship Chart 9.2 IR11662 100W +16V SR Demo Board Power Transformer Specs 10.0 IRAC11662-100W +16V Demo Board Bill of Materials (BOM) Rev.1A 19 April 2010 UG #1.0 Page 2 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Page(s) 2 3 3 4 5 6 7 8 9 9 9 9 10 11-17 11-13 14-15 16 17 18 18 19 20 21 21-25 21 22 23-24 1.0 INTRODUCTION Generally, Schottky diodes are traditional devices use in passive rectification in order to have low conduction loss in secondary side for switching power supplies. The proliferations of synchronous rectification (SR) idea - which is mostly use in buck-derive topologies - have reached the domain of flyback application in recent years. The use of low-voltage-low-Rdson mosfet has become so attractive to replace the Schottky rectifiers in high current applications because it offers several system advantages such as dramatic decrease in conduction loss and better thermal management of the whole system by reducing the cost investment in heat sink and PCB space. A number of techniques in the implementation of SR in flyback converters are continuously growing from a simple self-driven (secondary winding voltage detection) to a more complex solution using "current transformer sensing" or combinations of both to improve the existing technology. The idea has become quite complicated though and additional discrete devices have made the cost and part counts issue even worse. Moreover, the issue of reverse current conduction (-due to the delay in sensing the sharp drop of secondary current during turn-off phase of the SR) still lingers on in different input line/ output load conditions. The use of a simple fast-rate-direct-sensing of voltage drop across the mosfet (Vsd) using integrated solution has pave the way for a much simpler and effective means of controlling the SR mosfets as well as alleviating the reverse current and multiple-pulse gate turn-ON issues. The objective of this user guide is to show the advantages of SR application using integrated IC approach and study the practical limits of the efficiency improvements vs. the normal rectification method. 2.0 GENERAL DESCRIPTION The IRAC11662-100W demo board is a universal-input flyback converter with single DC output capable of delivering continuous 100W (@ +16V x 6.25A) during active rectification mode. This demo board is primarily designed to study synchronous rectification using IR11662 in low-side configuration to take advantage of simpler derivation of Vcc supply from converter's output. It is equipped with necessary jumpers to ease exploring the conduction behavior of synchronous rectifiers SRs in quasi-resonant mode, so discussion would be confined to variable frequency switching in Critical Conduction Mode. It features the fast Vsd sensing of the IR11662 Smart Rectifier Control IC with gate output drive capability of +1A/-4A. It drives 2 pcs. of SRs in parallel (100V N-ch mosfet IRF7853 in SO-8 package with very low Rdson in its class : 18 m max). This had greatly simplified the overall mechanical design for not having those bulky and heavy heat sinks normally seen in high current flyback design using passive rectification. Rev.1A 19 April 2010 UG #1.0 Page 3 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6 5 4 3 2 1 2 4 CON1 - + 2 + 2 4 8 7 6 5 J2 Vout-tp Rs14 $ 3 2 1 SR2 4 1 optoK Cs21 10nF $ Rs23 470R 16Vout Vd-P Vd1-P Cs24 100nF + U1 IR1166 5 16Vout Vd 6 LGND EN 7 optoK Vs Vs1 8 VdTP Cs25 2 1 4 - + 32 1 10nf of GND MOT J4 Rev 1A 4 1 Document Number 1950-0808 JUMPER1 1 IRAC1166-100W Schematic Diagram 2 1 Title Rs18 33K OVT Rs20 0 0 Page 4 of 24 3 Checked : ISRAEL SERRANO 10K 2 Vgate LED 2 Vcc Rs21 10K 1 J3 Cs22 *10nF Cs20 47nF Vs 1 0R1 3W 1 2 CS18 100NF 3 Note: * Optional $ Unstuffed # Trimming 1 GNDS Rs22 1K Rp9 1K Sheet Vcc-P 1 1 FB 2 GND 3 COMP 2 J5 5 2 470pF 1kV Q1 IRFP22N60K 3 1k 100nF 100UF/35V Rp12 22R Tuesday, November 28, 2006 U4 AS4305 or AQ105 TP 1 220nf Rp10 CS17 22UF/35V CS 4 2 Rs17 10R Cp7 1 Cp8 VCC G-TP 2 2 Rs24 5.6K Ds5 Ls4148 Rp8 Date: Rs26 Dp5 LS4148 1 Gatedr Rs15 10R VCC 2 16Vout 1 8 7 6 5 Rp9A 12K Cp12 22pf SR1 IRF7853 1 TEA1507 Size Rs25 30m Rp6 910K SR1 2 Rp7 5K1 1 Cp11 4n7 3 2 1 1 Rs16 4K7 Vout-TP VCC DRAIN GND HVS CTRL DRIVER DEM Isns Cp6 4 2 Rp5 0R Rp11 280k U3 SFH615A2 optoK UG #1.0 1 2 3 4 8 7 6 5 J1 1 U2 SR2 IRF7853 2 2 1 3 1 Dp3 Ls4148 1 2 L2 40uH 0 optoA 2 Cp9 22pf Cp5 + Cs19 $ 2 Dp2 BAV103/200V 1 1 2 10uH Cp10 10nf 2 Cp13 1n 5 Cs23 1000UF/25V 1000UF/25V 1 0 Rp4 3K3 Rp3 22R 1500UF/25V 1500UF/25V 2 10 11 12 Cs16 Cs14 Cs15 + + + PQ3535 Dp1 1N5407 L3 Vouttp TP + Rs13 2K2 10R NTC Thermistor 2 1 L1 1uH 8A OptoA 7 8 9 1 Cp3 330UF/400V 1 2 Cp4 4N7/1kV 2 Rp1 19 April 2010 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Cp2 4N7/1kV Rp2 47K 2W 3 FUSE 1 6GBU06 DB1 1 F1 3 T1 1 Cp1 220NF/275V 1 2 3 4 CON2 FIGURE 1. IRAC11662-100W SCHEMATIC DIAGRAM Rev.1A IRAC1166-100W +16V Demo Board Schematic Diagram 2.1 IRAC11662-100W Demo Board Pictures Figure 2A. Top side of the IRAC11662-100W Demo Board Figure 2B. Bottom side of the IRAC11662-100W Demo Board - - ++ AC Input Rev.1A 19 April 2010 +16 V x 6.25A Output UG #1.0 Page 5 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 2.2 PCB Layout for IRAC11662-100W Figure 3A. Top layer etch with silkscreen print Figure 3B. Bottom layer etch with silkscreen print. Rev.1A 19 April 2010 UG #1.0 Page 6 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3.0 CIRCUIT DESCRIPTION The PCB design is basically optimized as a test platform to evaluate of active rectification using Smart synchronous rectification and as well as basic features of flyback converter operating in quasi-resonant mode. This demo board has 2-pin connector ( CON1 ) for AC input and a time-lag type 3.5A fuse for input current overload protection. Minimum input filtering is provided (Cp1-Xcap) before AC input voltage (90-264VAC) is routed to a 6Amp-bridge rectifier (DB1). Primary side controller (U2) basically drives the primary Mosfet Q1 to operate in CriticalConduction mode to eliminate turn-ON switching loss thru ZVS (zero voltage switching only occurs when NVsec > Vdcin ) or thru LVS ( low-voltage switching when nVsec< Vdcin) to reduce capacitive losses of Q1 especially at high line condition. The switching frequency Fsw at full load varies from ~38 to ~84kHz typically from low to high input condition and falls back to minimum value (fixed ~ 6 -10kHz) to reduce input power during light load condition. Auxiliary winding is loosely monitored by demagnetization pin4 of U2 through Dp3, Rp5 and Rp11 network that sets the OVP limit with Rp6 and Rp11 sets the over power limit of the converter. Optocoupler U3 provides isolated output voltage feedback to the primary side. The output voltage level across load connector CON2 (+16Vo) is monitored and regulated by the V/I Secondary error amplifier U4 (AQ105 or AS4305) that also manages the output current limiting function by monitoring the voltage across the RS25-26 current sense resistors. The power stage of the secondary is using 2-SO8 low IRF7853 synch-fets (SR) in parallel to implement the low-side synchronous rectification. In this configuration, it is simpler to derive the Vcc supply for the U1 (IR11662 SO8-IC) controller directly from the DC output Vout. Jumper J5 is used to isolate U1's Vcc from Vout so that user may easily evaluate IC's power consumption especially during standby load condition. In the absence of a sensitive low current probe, the quiescent current Icc through Dp4 can be calculated from the differential voltage across the Rs17. The decoupling capacitor Cs17 and Cs18 provides additional filtering which is necessary to clean high frequency noise especially when U1 is driving several mosfets (SR1 // SR2) with high Qg parameters normally associated with high currentlow voltage mosfets. The Vd and Vs sense pins monitor the voltage (Vsd) across the sync rect mosfets and proper attention was taken during PCB routing to ensure the integrity of differential voltage Vsd. This is done by directly taking the signal Vd from the drain pins of SR1//SR2 using a dedicated trace. Probe points as well as redundant test hook points are provided to facilitate easy probing of essential test waveforms. Rev.1A 19 April 2010 UG #1.0 Page 7 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 4.0 TEST CONNECTION AND SETUP DIAGRAM 4.1 Recommended setup for Voltage and Current probing Fig. 4A Direct gate voltage probing using tip & gnd spring. Fig. 4B Recommended probing of secondary current waveform. Rev.1A 19 April 2010 Fig. 4C Connecting O-scope probe to hook Gate drive test points. Fig. 4D Recommended probing of Vout's Ripple & Noise voltage. UG #1.0 Page 8 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 5.0 CIRCUIT FEATURES 5.1 OVT setting: The Offset Voltage Threshold can be easily selected by changing the position of jumper J3 according to system mode of operation as shown on Table 1 below. Since the demo board is practically designed to operate in Critical conduction mode, OVT pin can be left floating or grounded to prolong the MOSFET's channel conduction period a bit compared to connecting it to Vcc. As a result, this would give the advantage of further reducing the conduction period of the MOSFET's (SR1 & SR2) body diode, thus achieving more efficient operation. Reducing the chance of having reverse current during the fast turn-off phase of the sync-fets is another strong reason for having this feature available. Table 1 System mode of operation OVT connected to DCM or CrCM Ground, VTH1= -3.5mV Boundary CCM Floating, VTH1= -10.5mV CCM VCC, VTH1= -19.0 mV The general observation during light load condition (~10-20% full load) is that a ~0.5 to ~1.2% efficiency improvement was seen for OVT=Gnd compared to OVT=floating. This small difference is no longer significant when the load becomes heavy for CrCM operation. 5.2 Enable setting: The IC is enabled by default knowing that EN pin is tied internally to VCC through a resistor. Having a jumper on J4 location will connect EN pin to Gnd and will immediately disable the internal gate drive circuit of the IR11662 IC. By putting a jumper J4 in/out would help the user to quickly evaluate the effect in efficiency by investigating the change in input power as a result of having SR fets working compared to just having an ordinary passive rectification offered by the body diode(s) when the gate drive is disabled. CAUTION : This demo board is basically designed for evaluation of functionality of IR11662 IC. The users may disable the IC by shorting J4 EN to GND for quick testing at full load but with care should be taken. It is strongly advise not to load more than 4.6 - 6Amp with IR11662 disabled for a prolong period of time (>1min). This is to prevent damaging the MOSFET's body diode due to overheating when the load current passes through the mosfets' body diode while SRs are turned-OFF. Never power-up the unit without shorting J5. 5.3 Minimum ON Time (MOT) setting: MOT setting is used to de-sensitize the IC from multiple change in Vsd during the turn-ON phase of SRs which is cause by the ringing of the secondary winding voltage (Vsec). MOT can be adjusted through Rs18 (according to AN1087 simplified equation RMOT =2.5x1010*tmot ) and is chosen to be 1.2us which is usually enough to ignore the parasitic noises at Vsd in a quasi-resonant switching converters such as this demo board. Rev.1A 19 April 2010 UG #1.0 Page 9 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 5.4 Mosfet Selection Design Tips Application note AN1087 has made it easy to understand the calculations required in flyback sync-rect driving circuits using IR116x series ICs. Choosing the right mosfet(s) to satisfy the performance-cost requirement of any sync rect design should be simple as well. Voltage rating: SRs should also follow similar equation in most flyback design as shown below: Vsd > k*[Vo +(VDCinmax /(Npri/Nsec) )] where k =1.1 to 1.4 as a guard band for startup stress due to leakage spike. RdsON rating: Generally, it is easy to meet >1% system efficiency improvement if the conduction loss of the SRs becomes twice smaller than normal passive rectification approach. This is to achieve better thermal performance especially if the designer wishes to consider not having too bulky and heavy heatsink in the design, but take note that it would still be largely dependent on the size PCB copper area allotted to the SRs. We should also consider the estimated Rdson at 25C (normally shown in the datasheet) would be approximately ~1.8 times higher at Tj=125C. As a rule of thumb, we will base our calculation on these assumptions to simplify the mosfet selection criteria. For typical 100V Schottky rectifiers, Vf is around ~ 600 mV ( @Tj=125C), so in this case we should find a 100-V mosfet(s) with lower Rdson which will have a ~150mV max Vsd at rated full load current (Ioave). For quick estimation of Isecrms, designer might find Fig. 9.1 useful to quickly estimate Isecrms since Ioave is normally given as standard design specs. Calculating the rms value of secondary current is easier for CrCM mode where D = N*Vsec/ (N*Vsec + Vdcinmin) N=Npri / Nsec , N = 31/5 eqn. 1 Let Vsec =16.1, Vdcmin=100, D= ~50% h = Vf (Schottkydiode) / Vsd(mosfet ) eqn.2 Pdis SR < 1/h* Vfdiode* Ioave eqn.3 With h > 2, Target VSD(@Tj=125C) 600mV / 2 300mV 2 I secrms*RdsON (@Tj=125C) 300 mV*Ioave eqn.4 RdsON (@Tj=125C) = ~1.8*RdsON (@Tj=25C) I sec rms = Rev.1A 2 Ioave (1 - D ) / 3 (1 - D ) 19 April 2010 eqn.5 eqn.6 Combining equations 4, 5, and 6 RDSON @ Tj = 25C RDSON 166mV [ 3(1 - D )] 4 Ioave eqn.7 0.125 * (50%) 0.125 * 0.5 = = 0.010 6.25 Ioave RdsON @Tj=25C 10 m We can use 2-SO8 mosfets (IRF7853) in parallel having equivalent RdsON (@Tj=25C) of ~9 m. Note : Vsd(@Tj=125C)<100mV would yield lower Rdson and can be achieve better thermal performance but it would mean raising the parts count and cost. UG #1.0 Page 10 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6.0 TEST WAVEFORMS 6.1.1 Transient Test Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Vsd of sync rects are quite clean. IR11662 starts operation when Vcc exceeds Vcc turn on threshold. Prior to the activation of the IC, the body diodes of the sync rect mosfets act as the passive rectifiers. The VD (fsw : ~10kHz) pulses became so narrow after the output voltage stabilizes and reached the regulation at no load condition. After the output voltage getting stable, IR11662 detects the light load situation and disables gate output. (-see Fig. 6G for more details). Fig 6A - 90 Vacin startup @ no load. Ch2 : Vsd of sync rect (SR) Ch3 : Vgate, Ch4 : Isd Vsd of sync-rects is uniform and switching regularly. Gate drive pulses become narrow at light load condition and the switching frequency decreases after the output voltage reached its regulation level. The zoom view shows no reverse current during startup at no load. The gate voltage of IR11662 is clamped at ~10V. The clamping circuit kicks in when Vcc voltage is approximate 13V. Fig 6B - 265 Vacin -startup @ no load. Rev.1A 19 April 2010 UG #1.0 Page 11 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd IR11662 gate drive started ~10ms after power-up. The zoom view shows no reverse current during startup at full load. Fig 6C - 90 Vacin 100W full load startup. Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd IR11662 gate drive started ~15ms after power-up. The zoom view shows no reverse current during startup at full load. Fig 6D - 265 Vacin 100W full load startup. Rev.1A 19 April 2010 UG #1.0 Page 12 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Vsd of sync-rects switching freq. drops to ~15kHz at power shutdown. The zoom view shows no reverse current during power-off. Fig 6E - Power down @ 90Vacin @ 100W full load Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd No reverse current during power-off. Fig 6F - Power down @ 265Vacin @ 100W full load Rev.1A 19 April 2010 UG #1.0 Page 13 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6.1.2 Static Load Test Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Vsd of sync-rects are switching at ~foldback freq (~12kHz DCM oper'n) at no output load condition. Vgate became a narrow (~1.4us) pulses during no load standby operation. As the secondary current conduction time is very close to the set MOT time, IR11662 disables gate output every other cycle (cycle skipping). The standby power at 90Vac is 0.98W with 28mA/ 460mW dummy load. Fig. 6G - 90Vac in, 16Vout / no load Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Fsw falls back to a fix low frequency around ~6kHz with gate pulse width reduce to a narrow ~1.4usec. IR11662 has cycle skipping at high line - no load condition. This helps to reduce the gate driver losses. The standby power at 265Vac is 1.1W. This is under 28mA/ 460mW dummy load (Rs23 and the Green LED) condition. Fig. 6H - 265Vac in, 16Vout / no load Rev.1A 19 April 2010 UG #1.0 Page 14 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Fsw : ~40 kHz Fig. 6I - 90Vacin, 16Vout / 6.25A full 100W load Ch2 : Vsd of sync rect (SR) Ch3 : Vgate of SR1 & SR2 Ch4 :Isd Fsw : ~84 kHz Fig. 6J - 265Vacin, 16Vout / 6.25A full 100W Rev.1A 19 April 2010 UG #1.0 Page 15 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6.2 Ripple & Noise Measurement Vout R&N : ~337mVpp Vout R&N : ~312mVpp Iout ( 5A/div) : 6.25A Iout ( 5A/div) : 6.25A Fig. 6K 90Vacin, Ripple & Noise 16Vout / 6.25A full 100W load Fig. 6M 240Vacin, Ripple & Noise 16Vout / 6.25A full 100W load Ch2 : Output R&N (100mV/div) Ch4 (x10A/V): Iout ( 5A/div) Ch2 : Output R&N (100mV/div) Ch4 (x10A/V): Iout ( 5A/div) Vout R&N : ~312mVpp Vout R&N : ~312mVpp Iout ( 5A/div) : 6.25A Fig. 6L 115Vacin, Ripple & Noise 16Vout / 6.25A full 100W load Rev.1A 19 April 2010 Iout ( 5A/div) : 6.25A Fig. 6N 265Vacin, Ripple & Noise 16Vout / 6.25A full 100W load UG #1.0 Page 16 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6.3 Dynamic Load Test (0 - 100% rated load, +/- 2.5A/usec) Iout ( 5A/div) Vout R&N : 1.25Vpp Fig. 6O 90Vacin, Ripple & Noise +16Vout , 6.25A 5msec, 0A 5msec Vout R&N : 1.22Vpp Fig. 5Q 240Vacin, Ripple & Noise +16Vout , 6.25A 5msec, 0A 5msec Vout R&N : 1.12Vpp Fig. 5P 115Vacin, Ripple & Noise +16Vout , 6.25A 5msec, 0A 5msec Rev.1A 19 April 2010 Vout R&N : 1.25Vpp Fig. 5R 265Vacin, Ripple & Noise +16Vout, 6.25A 5msec, 0A 5msec UG #1.0 Page 17 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 7.0 LINE/ LOAD REGULATION TEST 7.1 IR11662 Demo Board V-I Characteristics Vin Iout (A) 0 1 2 3 4 5 6 6.25 6.5 6.75 7 7.25 90 Vout (V) 115 Vout (V) 230 Vout (V) 265 Vout (V) 16.049 16.052 16.054 16.053 16.054 16.054 16.055 16.046 16.02 14.2 10.29 16.049 16.053 16.055 16.054 16.055 16.056 16.057 16.051 16.03 14.27 10.34 16.049 16.058 16.063 16.061 16.058 16.059 16.062 16.062 16.05 14.33 10.4 16.052 16.063 16.068 16.07 16.066 16.064 16.064 16.064 16.06 14.1 10.36 Bounce Bounce Bounce Table 2. V-I Characteristics Bounce Figure 7.1. Output Voltage vs. Load Current Characteristic Curve Rev.1A 19 April 2010 UG #1.0 Page 18 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 7.2 System Efficiency Test Table 3 VinAC Vout V) Iout (A) Pout (W) Pin (W) Efficiency 90 16.046 6.244 100.2 117.3 85.41% 115 16.051 6.244 100.2 115.5 86.77% 230 16.062 6.244 100.3 115 87.21% 265 16.064 6.244 100.3 116 86.47% System Efficiency with OVT=GND 90% 88% 86% Efficiency 84% 82% 90Vac 80% 115Vac 78% 76% 230Vac 74% 265Vac 72% 70% 0 1 2 3 4 5 6 7 Output Load Current (A) Fig. 7.2A System Efficiency with OVT = Gnd Rev.1A 19 April 2010 UG #1.0 Page 19 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 7.3 Thermal Verification Table 4 IRAC11662-100W 90VACin 265VACin Ambient Temp 26 26 IR11662 (SO-8 IC) 73 70 SR1 (IRF7853 SO8 FET) SR2 (IRF7853 SO8 FET) 95 96 84 85 Q1 (IRF22N60K) 58 65 DP1 (UF5407) Snubber diode 330uF/400V MXR Bulk Ecap 62.5 50 69.5 50 Power transformer (PQ3535) 75.5 76 67 49 117.3 16.05 116 16.06 Input bridge rectifier Pin (W) Vout (A) Iout (A) Efficiency 6.25 6.25 85.5% 86.5% Note : All case temperature in C. Rev.1A 19 April 2010 UG #1.0 Page 20 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 8.0 Summary : This demo board showcases the performance of IR11662 SmartRectifier Control IC to drive mosfets (as synchronous rectifiers) by simple fast-rate direct-voltage-sensing technique. It also featured the flexibility of the IC to cope with different current conduction modes of flyback converter designs. The low-side synchronous rectification is fully demonstrated in this demo board, which operates in variable frequency critical conduction mode (VF-CrCM). This configuration has lead to achieve better efficiency and a much simpler overall system design normally required in single output flyback high current applications such those use in laptop power adaptors. This 100W demo board has shown the efficiency improvement using low voltage SO8 mosfets - replacing the traditional Schottky rectifiers - has brought a string of advantages such as avoiding the use of heavy heat sinks and simple gate drive circuit for the synchronous mosfets. This design simplification has resulted to saving in PCB area due to reduction of part counts and elimination of bulky heat sink. IR11662 automatically disables or skips gate output at no load condition thus minimizes the standby power losses. 9.1 Transformer turns ratio, Duty Cycle and Secondary Current Relationship Dmax xfmr vs. Isec rms / Io ave ratio, @ Different Operational Duty cycle 3.30 Dmax cntrlr=40%, Vdcmin=100, Vsec=16.1 3.10 Dmax cntrlr=50%, Vdcmin=100, Vsec=16.1 2.90 Isecrms / Ioave ratio Dmax cntrlr=60%, Vdcmin=100, Vsec=16.1 2.70 Dmax cntrlr=70%, Vdcmin=100, Vsec=16.1 2.50 Dmax cntrlr=50%, Vdcmin=200,Vsec=16.1 2.30 Dmax cntrlr=50%, Vdcmin=100,Vsec=12.1 Dmax cntrlr=50%, Vdcmin=200,Vsec=12.1 2.10 Dmax cntrlr=50%,Vdcmin=100, Vsec=20 1.90 Dmax cntrlr=50%,Vdcmin=200, Vsec=20 1.70 1.50 1.30 1.10 0.90 0.70 0.50 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 Dmax Xfmr = NVsec / (NVsec + Vdcmin) where Vdcmin=100, 200 and Vsec = 16V1, 12V1, 20V 0.60 0.65 Fig. 9.1 Graphical estimation chart for Isec rms / Ioave Rev.1A 19 April 2010 UG #1.0 Page 21 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 9.2 IRAC11662-100W +16V SR Demo Board Power Transformer Specification Winding W1 : 15 turns 2 x AWG#20 Winding W2 : 5 turns 3 x TIW (0.55 mm) Winding W3 : 5 turns 3 x TIW (0.55 mm) Winding W4 : 5 turns AWG#30 Winding W5 : 5 turns 3 x TIW (0.55 mm) Winding W6 : 16 turns 2 x AWG#20 Core type : PQ3535 Ferrite material : PC44 TDK / Nicera equivalent Lpri : 250uH +/-15% (pin 6-4) Finishing : Dip varnish / vacuum BOTTOM VIEW Pin 6 W5 Pin 7 W1 31 turns total W3 Pin 8 Pin 5 W2 Pin 9 5 turns 5 turns 5 turns W6 Pin 4 Pin 3 5 turns total Pin 10 Pin 2 W4 Pin 11 Pin 1 Pin 12 PQ3535 Fig. 9.2 Power transformer Winding Termination Diagram Note : TIW = triple insulated wire Rev.1A 19 April 2010 UG #1.0 Page 22 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 10.0 IRAC11662-100W +16V Demo Board Bill of Material (BOM) Note: TH = Through-hole Item # Qty. 1 1 2-PIN CON1 2 way connector (TH) PN: 5417 or List No. : 39-26-3030 2 1 4-PIN CON2 4 way connector (TH) PN: 5417 or List No. : 39-26-3040 3 1 220NF/275V CP1 KNB1560 0.22UF 10% 275 L30 R15 (TH) KNB1560 0.22UF 10% 275 L30 R15 4 1 4NF7/1KV CP2 CAPACITOR, 4.7NF 1000V (TH) DEBF33A472ZC1B(Murata) 5 1 330UF/400V CP3 CAPACITOR, 330UF 400V (TH) 400MXR330M35X35 (Rubycon) or EET-ED2G331EA - (Panasonic) 6 1 4NF7/1KV CP4 CAPACITOR, 4.7NF 1kV (TH) DEBF33A472ZC1B (Murata) 7 1 100UF/35V CP5 CAPACITOR, 100UF 35V (TH) UPL1V101MPH NICHICON 8 1 0.1UF CP6 CAPACITOR, 1206 100 NF 50V 12065C104KAT00J UNSTUFFED 9 Date : Value 8-Mar-2010 Part Ref. Manuf. PN. Description UNSTUFFED CP7 10 1 0.22UF CP8 CAPACITOR, 1206 220NF 50V 12065G224ZAT2A ( AVX ) 11 1 22PF CP9 CAPACITOR, 1206 22PF 50V 12061A220JAT2A ( AVX ) 12 1 10NF CP10 CAPACITOR, 1206 10NF 50V 12065G103ZAT2A ( AVX ) 13 1 4N7F CP11 CAPACITOR, 1206 4.7NF 50V 12065C471KAT2A ( AVX ) 12061A220JAT2A ( AVX ) DE1E3KX152MA5B ( Murata ) 14 1 22PF CP12 CAPACITOR, 1206 22PF 50V 15 1 1N5 CP13 CAPACITOR, X1/Y1 1.5NF (TH) CS14, CS15 CAPACITOR, 1000UF 25V (TH) 25ZL1000M12.5X20 (Rubycon) (TH) 25ZL1500M12.5X25 (Rubycon) 16 1 1000UF/25V 17 1 1500UF/25V CS16 CAPACITOR, 1500UF 25V 18 1 22UF/35V CS17 CAPACITOR, 22UF 50V (TH) 50ZL22M5X11 (Rubycon) 100NF CS18, CS24 CAPACITOR, 1206 100NF 50V 12065C104KAT00J ( AVX ) UNSTUFFED CS19 UNSTUFFED CAPACITOR, 1206 47NF 50V 12065C473KAT2A ( AVX ) CAPACITOR, 1206 10NF 50V 12065C103KAT2A ( AVX ) 19 1 20 21 1 47NF 22 2 10NF CS20 CS21, CS22, CS25 23 1 820UF/25V CS23 CAPACITOR 820UF, 25V (TH) EEUFC1E821. 24 1 6GBU06 DB1 6-Amp 800V Bridge rectifier diode (TH) 6GBU06 -(General Semiconductor) 25 1 1n5407 DP1 DIODE, 3A 800V (TH) 1N5407 (General Semiconductor) Philips BAV103 26 1 BAV103/200V DP2 DIODE, SWITCHING SOD-80C 27 3 LS4148 DP3, DP4, DS5 DIODE, QUADRO-MELF LS4148 (VISHAY) 19372K 3.15A. 28 1 T3.15A/250V F1 FUSE, TR5 ANTISURGE 3.15A, (TH) 29 1 Test hook point GND,G TERMINAL, PCB Raised Loop Black (TH) 200-203 (W HUGHES ) 30 1 Test hook point Gate Drv TERMINAL, PCB Raised Loop White (TH) 200-201 (W HUGHES ) 31 1 Wire Jumper J1 Jumper wire 0.7 diameter, 19 mm (TH) 32 1 Wire Jumper J2 Jumper wire 0.7 diameter, 11mm (TH) 33 1 JUMPER1 J3 Three way jumper (TH) M22F2010305 ( HARWIN ) 34 2 JUMPER1 J4, J5 Two-way jumper (TH) M22-2010205 (HARWIN) M22-1910005 (HARWIN) 35 1 for J3 Jumper Head (blue) 36 1 for J4 Jumper Head (Black) M22-1900005 (HARWIN) 37 1 for J5 Jumper Head (Red) M22F19200005 (HARWIN) 38 1 1uH L1 High current Ferrite Rod Inductor- (TH) prime PG0203 -Pulse Electronics or 019-4698-00R - Precision Inc. 39 1 40uH L2 Common mode choke -TH 019-4685-00R - Precision Inc. 40 1 10uH L3 Ferrite core inductor, axial (TH) B78108-S1103-K Rev.1A 19 April 2010 UG #1.0 - EPCOS Page 23 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 41 1 LED LED1 LED Green - TH L-1413GDT 42 1 IRFP22N60K Q1 TO-247 600V 22Amp N-ch Mosfet 43 1 10R RP1 NTC Thermistor 10ohm 3Amp (TH) (TH) B57235S100M IRFP22N60KPBF- VISHAY 44 1 47K 2W RP2 RESISTOR, 2W 5% 47K - (TH) MCF 2W 47K 45 1 22R RP3 RESISTOR, 0.25W 5% 22R (TH) MCF 0.25W 22R. 46 1 3k3 RP4 RESISTOR, 1206 3K3 MC 0.125W 1206 1% 3K3 MC 0.125W 1206 0R - EPCOS 47 1 0R RP5 RESISTOR, 1206 0R 5% 48 1 910K RP6 RESISTOR, 1206 910K MC 0.125W 1206 5% 910K 49 1 5.1k RP7 RESISTOR, 1206 5.1K; MC 0.125W 1206 1% 5.1K RESISTOR, 1206 22R MC 0.125W 1206 5% 22R RESISTOR, 1206 1K MC 0.125W 1206 1% 1K 50 1 22R 51 3 1K RP8 RP9, RP12, RS22 52 1 12K RP9A RESISTOR, 1206 12K MC 0.125W 1206 5% 12K 53 1 0R1 RP10 RESISTOR, WW 3W 5% 0R1 (TH) WELWYN MC 0.125W 1206 5% 280K MC 0.125W 1206 5% 2K2. 54 1 280K RP11 RESISTOR, RC12H 1206 280K 55 1 2K2 RS13 RESISTOR, 1206 2K2 RS14, RS26 UNSTUFFED RESISTOR, 1206 10R 56 W210R1J1 MC 0.125W 1206 5% 10R 57 2 10R RS15, RS17 58 1 4K7 RS16 RESISTOR, 1206 4K7 MC 0.125W 1206 5% 4K7 MC 0.125W 1206 5% 33K 59 1 33K RS18 RESISTOR, 1206 33K 60 1 47K RS20 RESISTOR, 1206 47K MC 0.125W 1206 1% 47K 61 1 10K RS21 RESISTOR, 1206 10K MC 0.125W 1206 1% 10K RESISTOR, RC02H 1206 470R RC-02H-470R-1P5. 62 1 470R RS23 63 1 5.6k RS24 RESISTOR, 1206 5.6K; MC 0.125W 1206 1% 5.6K OARS1 - R030FI. 64 1 30m RS25 RESISTOR, SMD 1% 0R030 65 2 IRF7853 SR1, SR2 66 1 PQ3535 T1 67 1 IR11662 U1 68 1 TEA1507 U2 SO-8 N-ch 100V 18mohm MOSFET PQ3535 100W Flyback Power Transformer (TH) SO-8 Flyback Sync Rectifier Smart Controller GreenChipTM II SMPS control IC DIP8 (TH) 69 1 SFH615A2 U3 70 1 AS4305 or AQ105 U4 SOT23-5 Secondary V-I Error amplifier Siliconlink or Acutechnology 71 1 Test hook point TERMINAL, PCB Raised Loop - Red (TH) 200-207 - W HUGHES 72 2 Test hook point VCC-HP VD-HP, VD1-HP TERMINAL, PCB Raised Loop- Yellow (TH) 200-202 - W HUGHES 73 1 Test hook point VS, VS1 200-203 - W HUGHES 74 1 Pri - Heatsink TERMINAL, PCB Raised Loop BLACK (TH) 10.4DegC/W, Black anodized extruded heat sink - radial fins & notched base and solderable pins 531102B02500G -Aavid Thermalloy HS191-ND -DIGI-KEY 75 4 Screw + washer SCREW with washer M3X6 P=.5 SEM02030006FA (NETTLEFOLDS ) 76 1 Screw M3x12 mm , For Primary heat sink MB04030012007FA (NETTLEFOLDS) 77 2 Spring Washers M3 1mm thick, For Primary heat sink WS21030081FA (unbranded) 78 1 Nut NC01030081FA (unbranded) 79 1 Insulator for Q1 (TO247) TRANSIPILLA R, HEX STYLE 3 M3X38; HEX NUT M3X0.5X1.8 Silpad K-10 or K-4, 25.5mm x 19.1mm (0.2 0.4 degCin2/W) Depth, thread:4.5mm; Diameter, External:7mm; Head type:Hexagonal; Height, spacer:38mm; Length / Height, external:38mm; Thread size:M3 80 4 Nylon Standoff 81 1 PCB Rev.1A SFH615A2 DIP 4 option G Optocoupler (TH) IR 019-4563-00 Rev 01 IR TEA1507 - NXP SFH615A-2 -Vishay (Infineon) 0900 000 5350 (HARTING Bergquist) SCHURTER- 9633.83 1.6mm thick 2-sided 2 oz, UL rated 94V-0 PCB 19 April 2010 UG #1.0 -Precision Inc. Page 24 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice.