844011AGILF - Integrated Device Technology

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS844011I is a Fibre Channel Clock

Generator and a member of the HiPerClocksTM

family of high performance devices from ICS.

The ICS844011I uses an 18pF parallel resonant

crystal over the range of 20.4MHz - 28.3MHz. For

Fibre Channel applications, a 26.5625MHz crystal is used.

The ICS844011I has excellent <1ps phase jitter per-

formance, over the 637kHz - 10MHz integration range. The

ICS844011I is packaged in a small 8-pin TSSOP, making it

ideal for use in systems with limited board space.

FEATURES

•One differential LVDS output

•Crystal oscillator interface, 18pF parallel resonant crystal

(20.4MHz - 28.3MHz)

•Output frequency range: 81.66MHz - 113.33MHz

•VCO range: 490MHz - 680MHz

•RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal

(637kHz - 10MHz): 0.75ps (typical)

•3.3V or 2.5V operating supply

•-40°C to 85°C ambient operating temperature

•Available in both standard and lead-free RoHS compliant

packages

HiPerClockS™

ICS

ICS844011I

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VDDA

GND

XTAL_OUT

XTAL_IN

VDD

BLOCK DIAGRAM

OSC Phase

Detector

VCO

490MHz - 680MHz

M = ÷24

(fixed)

N = ÷6

(fixed)

XTAL_IN

XTAL_OUT

COMMON CONFIGURATION TABLE - FIBRE CHANNEL

PIN ASSIGNMENT

stupnI ycneuqerFtuptuO

)zHM(

)zHM(ycneuqerFlatsyrCMN

noitacilpitluM

N/MeulaV

5265.62426 4 52.601

52426 4 001

Pullup

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

ADD

rewoP.nipylppusgolanA

2DNGrewoP.dnuorgylppusrewoP

4,3 ,TUO_LATX

NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotal

licsolatsyrC

.tuptuoehtsiTUO_LATX

5EOtupnIpulluP Qn/Qeht,WOLnehW.evitcasituptuoQn/Q,HGIHnehW.nipelbanetuptu

.slevelecafretniLTTVL/SOMCVL.etatsecnadepmihgihanisituptuo

7,6Q,QntuptuO.slevelecafretniSDVL.stuptuokcol

claitnereffiD

rewoP.nipylppuseroC

:ETON pulluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniots

refer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

tnerruCylppuSrewoP DBTAm

ADD

tnerruCylppuSgolanA DBTAm

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, IO (LVDS)

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θJA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V

V3.3=2V

3.0+V

V5.2=7.1V

3.0+V

egatloVwoLtupnI V

V3.3=3.0-8.0V

V5.2=3.0-7.0V

tnerruChgiHtupnIEOV

V526.2roV564.3=5Aµ

tnerruCwoLtupnIEOV

V,V526.2roV564.3=

V0=051-Aµ

TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ADD

egatloVylppuSgolanA 573.25.2526.2V

tnerruCylppuSrewoP DBTAm

ADD

tnerruCylppuSgolanA DBTAm

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 4. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 4.023.82zHM

)RSE(ecnats

iseRseireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 1Wm

TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 66.1833.311zHM

t)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

:egnaRnoitargetnI@zHM52.601

zHM01-zHk736 DBTsp

:egnaRnoitargetnI@zHM001

zHM01-zHk736 57.0sp

emiTllaF/esiRtuptuO%08ot%02572sp

cdoelcyCytuDtuptuO 05%

.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:

1ETON

TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 66.1833.311zHM

t)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

:egnaRnoitargetnI@zHM52.601

zHM01-zHk736 DBTsp

:egnaRnoitargetnI@zHM001

zHM01-zHk736 39.0sp

emiTllaF/esiRtuptuO%08ot%02592sp

cdoelcyCytuDtuptuO 05%

.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:

1ETON

TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 053Vm

ΔV

egnahCedutingaM 05Vm

egatloVtesffO 2.1V

ΔV

egnahCedutingaM 04Vm

.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON

TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 053Vm

ΔV

egnahCedutingaM 04Vm

egatloVtesffO 52.1V

ΔV

egnahCedutingaM 05Vm

.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP

LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT

RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

SCOPE

nQx

LVDS

3.3V±5%

POWER SUPPLY

Float GND

➤

100

out

LVDS

DC Input VOD/Δ VOD

VDD

out

LVDS

DC Input

➤

/Δ V

VDD

Clock

Outputs 20%

80% 80%

20%

SWING

DIFFERENTIAL OUTPUT VOLTAGE SETUP

SCOPE

nQx

LVDS

2.5V±5%

POWER SUPPLY

Float GND

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

PERIOD

odc = x 100%

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS844011I has been characterized with 18pF paral-

lel resonant crystals. The capacitor values, C1 and C2,

shown in Figure 2 below were determined using a

26.5625MHz, 18pF parallel resonant crystal and were cho-

sen to minimize the ppm error. The optimum C1 and C2

values can be slightly adjusted for different board layouts.

33p

18pF Parallel Crystal

27p

XTAL_OUT

XTAL_IN

POWER SUPPLY FILTERING T ECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS844011I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VDD and VDDA should

be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING

10Ω

VDDA

10μF

.01μF

3.3V or 2.5V

.01μF

VDD

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

FIGURE 4. TYPICAL LVDS DRIVER T ERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

2.5V or 3.3V

VDD

100 Ohm Differential Transmission Line

100

LVDS_Driv er

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram

is shown in Figure 3. The XTAL_OUT pin can be left floating.

The input edge rate can be as slow as 10ns. For LVCMOS

inputs, it is recommended that the amplitude be reduced from

full swing to half swing in order to prevent signal interference

with the power rail and to reduce noise. This configuration

requires that the output impedance of the driver (Ro) plus the

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

series resistance (Rs) equals the transmission line

impedance. In addition, matched termination at the crystal

input will attenuate the signal in half. This can be done in one

of two ways. First, R1 and R2 in parallel should equal the

transmission line impedance. For most 50Ω applications, R1

and R2 can be 100Ω. This can also be accomplished by

removing R1 and making R2 50Ω.

Zo = 50

VDD

Zo = Ro + Rs

VDD

XTA L_ I N

XTA L_ O U T

.1uf

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS844011I is: 2533

TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.201.3

ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

844011AGI www.icst.com/products/hiperclocks.html REV. A APRIL 18, 2006

Integrated

Circuit

Systems, Inc.

ICS844011I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 8. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

IGA110448SCIIA104POSSTdael8ebutC°58otC°04-

TIGA11044

8SCIIA104POSSTdael8leer&epat0052C°58otC°04-

FLIGA110448SCIDBTPOSST"eerF-daeL"dael8ebutC°58otC°04-

TFLIGA110448S

CIDBTPOSST"eerF-daeL"dael8leer&epat0052C°58otC°04-

.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntra

pehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON