Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
1 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
2.0
2.1
2.2
2.3
Initial issue with new naming rule
Revise 1. page 2 & 4: page address inputs
2.
A
dd Vcc absolute max. in page 5
Modify Deep Power Down Mode & Page Mode
Revise DC/AC Char.
Mar. 01, 2005
Nov. 23, 2005
Jun. 15, 2006
Oct. 29, 2007
2.4 Change wafer process from 0.13um to 90nm Aug. 26, 2008
2.5 Add 48BGA-6*8mm package Jan. 06, 2010
2.6 Delete Die form information Apr.12,2010
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
2 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Product Description
The CS26LV32163 is a 32M-bit PSRAM organized as 2M words by 16 bits. It provides high
density, high speed and low power. The device operates single power supply. The device also
features SRAM-like W/R timing whereby the device is controlled by /CE, /OE and /WE on
asynchronous. The device has the page access operation. Page size is 16 words. The device also
supports deep power-down mode, realizing low-power standby. The CS26LV32163 is available die
form and 48-Ball BGA package.
Features
¾ Single power supply voltage of 2.6 to 3.3V
¾ Direct TTL compativility for all inputs and outputs.
¾ Deep power-down mode : Memory cell data invalid.
¾ Page operation mode
Page read operation by 16 words.
¾ Logic compatible with SRAM R/W pin.
¾ Standby Current
Standby 120 uA(Max)
Deep power-down standby 10 uA(Max)
¾ Access Time
/CE1 Access Time: 70ns
/OE Access Time: 25ns
Page Access Time: 20ns
Product Family
Product Family Operating Temp Vcc. Range Speed(ns) Standby(Max.) Package Type
0~70oC
CS26LV32163
-40~85oC
2.6~3.3 70 120 uA
Dice
48BGA-6*7mm
48BGA-6*8mm
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
3 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Pin Configuration
<48BGA>
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
4 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Functional Block Diagram
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
5 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Pin Descriptions
Name Type Function
A0~A20 input Address input
A0~A3 input Page Address input
/CE1 input Chip Enable Input1, Low : Enable
CE2 input Chip Enable Input2, High:Enable, Low:Enter Power Down mode
/WE input Write Enable input, Low :Enable
/OE input Output Enable input, Low :Enable
/LB input Lower byte write control
/UB input Upper byte write control
DQ0~DQ15 I/O Data inputs/outputs
VDD Power Device Power supply
VSS Power VSS must be connected ground
VDDQ Power I/O Power supply
VSSQ Power VSSQ must be connected ground
NC Not Connection
Truth Table
MODE /CE1 CE2 /OE /WE /LB /UB DQ0~7 DQ8~15 VDD Current
Deep power down X L X X X X High Z High Z
Standby H H X X X X High Z High Z ICCSB, ICCSB1
Output Disabled L H H H X X High Z High Z ICC
Read L L DOUT D
OUT I
CC
Upper Byte Read L H DOUT High Z ICC
Lower Byte Read
L H L H
H L High Z DOUT I
CC
Write L L DIN D
IN I
CC
Upper Byte Write L H DIN Invalid ICC
Lower Byte Write
L H X L
H L Invalid DIN I
CC
Note: X means don’t care. (Must be low or high state)
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
6 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Absolute Maximum Ratings(1)
Symbol Parameter Rating Unit
VIN Input Voltage -1.0 to 3.6 V
VOUT Output Voltage -1.0 to 3.6
VDD Device Power Supply Voltage -1.0 to 3.6 V
TSTG Storage Temperature -55 to +150 OC
TA Operating Temperature -40 to +85 OC
PD Power Dissipation 0.6 W
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to
the device. Functional operation should be restricted to recommended operating condition. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics ( TA = 0 to + 70oC , VDD= 3.0V )
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VIL Input Low Voltage (2) -0.3 0.6 V
VIH Input High Voltage (2) 2.4 VDD + 0.3 V
IIL Input Leakage Current VIN=0 to VDD -1 1 uA
IOL Output Leakage Current Output disable, VOUT= 0V to VDD -1 1 uA
VOL Output Low Voltage IOL = 0.5mA, VDD=VDDmin 0.6 V
VOH Output High Voltage IOH = -0.5mA 2.4 V
ICC1 Operating Current tRC= Min, /CE1=VIL , CE2=VIH ,
IOUT=0mA
25 mA
ICC2 Page Access Operating
current
tPC = Min, /CE1=VIL, CE2=VIH ,
IOUT=0mA, Page add. cycling.
15 mA
ICCSB1 Standby Current -CMOS /CE1≧VDD-0.2V, CE2=VDD -0.2V 120 uA
ICCSB2 Deep Power-down
Standby Current
CE2 = 0.2V 10 uA
1. Typical characteristics are at TA = 25oC.
2. VIH(Max) VDD+1.0V with 10ns pulse width, VIL(Min)-1.0V with 10ns pulse width
Capacitance (1) (TA = 25oC, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance VIN=0V 10 pF
COUT Output Capacitance VOUT=0V 10 pF
1. This parameter is sampled periodically and is not 100% tested
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
7 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
AC Test Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.2V to VDDQ-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : VDDQ /2
Output Load (See right) : CL1) = 30pF
1. Including scope and Jig capacitance
Key To Switching Waveforms
Waveform Inputs Outputs
Must be standby Must be standby
May change for H to L Will be change from H to L
May change for L to H May change for L to H
Don’t care any change permitted Change state unknown
Does not apply Center line is high impedance “OFF” state
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
8 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
AC Characteristics <Read cycle & Write Cycle>
70
Parameter Name Name
Min Max
Unit
Read cycle time tRC 70 10,000 ns
Page mode cycle time tMRC 20 10,000 ns
Address access time tACC - 70 ns
Page Address Access Time tAA 20 ns
Chip enable access time (/CE1) tCO - 70 ns
Output enable to output valid (/OE) tOE - 25 ns
Byte enable access time tBA - 25 ns
Output data hold time tOH 5 - ns
Page mode output data hold time tAOH 5 - ns
Chip enable to output in low Z (/CE1) tCOE 10 - ns
Output enable to output in low Z (/OE) tOEE 0 - ns
Byte enable to output in low Z tBE 0 - ns
Chip disable to output in High Z (/CE1) tOD - 20 ns
Output disable to output in High Z (OE) tODO - 20 ns
Byte disable to output in High Z tBD - 20 ns
Write cycle time tWC 70 10,000 ns
Byte enable to end of write tBW 60 - ns
Address valid to end of write tAW 60 - ns
Chip select to end of write tCW 65 - ns
Data set up time tDS 30 - ns
Data hold time tDH 0 - ns
Write pulse width tWP 50 - ns
Address set up time tAS 0 - ns
Write recovery time(/WE) tWR 0 - ns
/WE high to output low Z tOEW 0 - ns
/WE low to output high Z tODW - 20 ns
Chip enable high pulse width tCEH 10 ns
Write enable high pulse width tWEH 6 - ns
CE2 set –up time tCS 0 - ns
CE2 hold time tCH 300 - ns
CE2 pulse width tDPD 10 - ns
CE2 hold from /CE1 tCHC 0 - ns
CE2 hold from power on tCHP 30 - ns
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
9 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAMS <READ CYCLE>
PAGE READ CYCLE (16 words access)
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
10 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
WRITE CYCLE (1) (/WE controlled)
WRITE CYCLE (2) (/CE1 controlled)
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
11 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
NOTES
1. AC measurement are assumed tR, tF = 5ns.
1. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and
are not output voltage reference levels.
2. Data cannot be retained at deep power-down stand-by mode.
3. If /OE is high during the write cycle, the outputs will remain at high impedence.
4. During the output state of DQ signals, input signals of reverse polarity must not be applied.
5. If /CE1 or /LB&/UB goes LOW coincident with or after /WE goes LOW, the outputs will remain at high
impedence.
6. If /CE1 or /LB&/UB goes HIGH coincident with or before /WE goes HIGH, the outputs will remain at high
impedence.
DEEP POWER-DOWN TIMING
POWER_ON TIMING
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
12 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
PROVISIONS OF ADDRESS SKEW
Read
In case, multiple invalid address cycles shorter than tRC_min sustain over 10us in a active status, as least one
valid address cycle over tRC_min must be needed during 10us.
Write
In case, multiple invalid address cycles shorter than tWC_min sustain over 10us in a active status, as least one
valid address cycle over tRC_min with tWP_min must be needed during 10us.
Low Power Pseudo SRAM
2 M Word x 16 bit CS26LV32163
13 Rev 2.6
Chiplus reserves the right to change product or specification without notice.
Order information
Note: Package material code “P” meets RoHS
