General Description
The MAX5550 dual, 10-bit, digital-to-analog converter
(DAC) features high-output-current capability. The
MAX5550 sources up to 30mA per DAC, making it ideal
for PIN diode biasing applications. Outputs can also be
paralleled for high-current applications (up to 60mA
typ). Operating from a single +2.7V to +5.25V supply,
the MAX5550 typically consumes 1.5mA per DAC in
normal operation and less than 1µA (max) in shutdown
mode. The MAX5550 also features low output leakage
current in shutdown mode (±1µA max) that is essential
to ensure that the external PIN diodes are off.
Additional features include an integrated +1.25V
bandgap reference, and a control amplifier to ensure
high accuracy and low-noise performance. A separate
reference input (REFIN) allows for the use of an external
reference source, such as the MAX6126, for improved
gain accuracy. A pin-selectable I2C*-/SPI™-compatible
serial interface provides optimum flexibility for the
MAX5550. The maximum programmable output current
value is set using software and an adjustment resistor.
The MAX5550 is available in a (3mm x 3mm) 16-pin thin
QFN package, and is specified over the extended
(-40°C to +85°C) temperature range.
Applications
PIN Diode Biasing
RF Attenuator Control
VCO Tuning
Features
♦Pin-Selectable I2C- or SPI-Compatible Interface
♦Guaranteed Low Output Leakage Current in
Shutdown (±1µA max)
♦Guaranteed Monotonic over Extended
Temperature Range
♦Dual Outputs for Balanced Systems
♦Current Outputs Source Up to 30mA per DAC
♦Parallelable Outputs for 60mA Applications
♦Output Stable with RF Filters
♦Internal or External Reference Capability
♦Digital Output (DOUT) Available for Daisy
Chaining in SPI Mode
♦+2.7V to +5.25V Single-Supply Operation
♦16-Pin (3mm x 3mm) Thin QFN Package
♦Programmable Output Current Range Set by
Software and Adjustment Resistor
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3871; Rev 0; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP
RANGE
PIN-
PACKAGE
PKG
CODE
TOP
MARK
MAX5550ETE -40°C to
+85°C 16 Thin QFN T1633F-3 ACZ
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
SPI is a trademark of Motorola, Inc.
+1.25V
REF
REFIN
BUFFER
10-BIT CURRENT-STEERING
DAC A
P
OUTA
VDD
FSADJA
VDD
OUTB
FSADJB
GND
DOUT/A1
CS/A0
DIN/SDASCLK/SCL
SPI/I2C 16-BIT INPUT REGISTER
DAC REGISTER A DAC REGISTER B
10-BIT CURRENT-STEERING
DAC B
MAX5550
P
Functional Diagram
Pin Configuration appears at end of data sheet.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND .............................................................-0.3V to +6V
OUTA, OUTB to GND.................................-0.3V to (VDD + 0.3V)
REFIN, CS/AO, DOUT/AI, SPI/I2C, FSADJA,
FSADJB to GND ......................................-0.3V to (VDD + 0.3V)
SCLK/SCL, DIN/SDA ................................................-0.3V to +6V
Continuous Power Dissipation (TA= +85°C)
16-Pin Thin QFN (derate 17.5mW/°C above +70°C) ..1398.6mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ; compliance voltage = (VDD - 0.6V),
VSCLK/SCL = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution 10 Bits
Integral Nonlinearity INL IOUT_ = 1mA to 30mA (Note 2) ±2 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
Offset IOS -50 -16 LSB
Zero-Scale Error IOUT_ = 1mA to 30mA, code = 0x000 1 µA
Full-Scale Error IOUT_ = 1mA to 30mA, code = 0x3FF,
includes offset -16 LSB
REFERENCE
Internal Reference Range 1.21 1.25 1.29 V
Internal Reference Tempco 30 ppm/°C
External Reference Range 0.5 1.5 V
External Reference Input Current 108 225 µA
DAC OUTPUTS
Full-Scale Current (Note 3) 1 30 mA
Output Current Leakage in
Shutdown ±1 µA
Output Capacitance 10 pF
IOUT_ = 30mA 1
TA = +25°C 0.55
Current Source Dropout Voltage
(VDD - VOUT_) IOUT_ = 20mA TA = -40°C to +85°C 0.6
V
Output Impedance at Full-Scale
Current 100 kΩ
Capacitive Load to Ground CLOAD 10 nF
Series Inductive Load LLOAD 100 nH
Maximum FSADJ_ Capacitive
Load CFSADJ_ 75 pF
DYNAMIC PERFORMANCE
Settling Time tSCLOAD = 24pF, LLOAD = 27nH (Note 4) 30 µs
Digital Feedthrough 2 nVs
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ; compliance voltage = (VDD - 0.6V),
VSCLK/SCL = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital-to-Analog Glitch Impulse 40 nVs
DAC-to-DAC Current Matching 2%
VDD = +3V 400
Wake-Up Time VDD = +5V 10 µs
POWER SUPPLIES
Supply Voltage VDD +2.70 +5.25 V
Supply Current IDD VDD = +5.25V, no load 3 6 mA
Shutdown Current 1.2 µA
LOGIC AND CONTROL INPUTS
+2.7V ≤ VDD ≤ +3.4V 0.7 x
VDD
Input High Voltage (Note 5) VIH
+3.4V < VDD ≤ +5.25V 2.4
V
Input Low Voltage VIL (Note 5) 0.8 V
Input Hysteresis VHYS 0.1 x
VDD V
Input Capacitance CIN 10 pF
Input Leakage Current IIN ±1 µA
Output Low Voltage VOL ISINK = 3mA 0.6 V
Output High Voltage VOH ISOURCE = 2mA VDD -
0.5 V
I2C TIMING CHARACTERISTICS (Figure 2)
SCL Clock Frequency fSCL 400 kHz
Setup Time for START Condition tSU:STA 600 ns
Hold Time for START Condition tHD:STA 600 ns
SCL Pulse-Width Low tLOW 130 ns
SCL Pulse-Width High tHIGH 600 ns
Data Setup Time tSU:DAT 100 ns
Data Hold Time tHD:DAT 070ns
SCL Rise Time tRCL 20 + 0.1
x CB300 ns
SCL Fall Time tFCL 20 + 0.1
x CB300 ns
SDA Rise Time tRDA 20 + 0.1
x CB300 ns
SDA Fall Time tFDA 20 + 0.1
x CB300 ns
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ; compliance voltage = (VDD - 0.6V),
VSCLK/SCL = 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Free Time Between a STOP
and START Condition tBUF 1.3 µs
Setup Time for STOP Condition tSU:STO 160 ns
Maximum Capacitive Load for
Each Bus Line CB400 pF
SPI TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period tCP 100 ns
SCLK Pulse-Width High tCH 40 ns
SCLK Pulse-Width Low tCL 40 ns
CS Fall to SCLK Rise Setup Time tCSS 25 ns
SCLK Rise to CS Rise Hold Time tCSH 50 ns
DIN Setup Time tDS 40 ns
DIN Hold Time tDH 0ns
SCLK Fall to DOUT Transition tDO1 CLOAD = 30pF 40 ns
CS Fall to DOUT Enable tCSE CLOAD = 30pF 40 ns
CS Rise to DOUT Disable tCSD CLOAD = 30pF 40 ns
SCLK Rise to CS Fall Delay tCS0 50 ns
CS Rise to SCLK Rise Hold Time tCS1 40 ns
CS Pulse-Width High tCSW 100 ns
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
SCLK Clock Period tCP 200 ns
SCLK Pulse-Width High tCH 80 ns
SCLK Pulse-Width Low tCL 80 ns
CS Fall to SCLK Rise Setup Time tCSS 25 ns
SCLK Rise to CS Rise Hold Time tCSH 50 ns
DIN Setup Time tDS 40 ns
DIN Hold Time tDH 0ns
SCLK Fall to DOUT Transition tDO1 CLOAD = 30pF 40 ns
CS Fall to DOUT Enable tCSE CLOAD = 30pF 40 ns
CS Rise to DOUT Disable tCSD CLOAD = 30pF 40 ns
SCLK Rise to CS Fall Delay tCS0 50 ns
CS Rise to SCLK Rise Hold Time tCS1 40 ns
CS Pulse-Width High tCSW 100 ns
Note 1: 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2: INL linearity is guaranteed from code 60 to code 1024.
Note 3: Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section.
Note 4: Settling time is measured from (0.25 x full scale) to (0.75 x full scale).
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +
0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 5
INL vs. CODE
CODE
INL (LSB)
MAX5550 toc01
0 128 384 640256 512 768 896 1024
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
DNL vs. CODE
CODE
DNL (LSB)
MAX5550 toc02
0 128 384 640256 512 768 896 1024
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
INL vs. TEMPERATURE
TEMPERATURE (°C)
INL (LSB)
MAX5550 toc03
-40 -15 10 35 60 85
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
DNL vs. TEMPERATURE
TEMPERATURE (°C)
DNL (LSB)
MAX5550 toc04
-40 -15 10 35 60 85
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
MAXIMUM INL ERROR vs.
OUTPUT CURRENT RANGES
OUTPUT CURRENT RANGE (mA)
INL (LSB)
MAX5550 toc05
1–2 1.5–3 4.5–9 8–162–5 15–30
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1.0
0.5
2.5
2.0
1.5
4.0
3.5
3.0
4.5
-40 10-15 35 60 85
ZERO-SCALE OUTPUT CURRENT
vs. TEMPERATURE
MAX5550 toc06
TEMPERATURE (°C)
ZERO-SCALE CURRENT (nA)
VDD = 5V
VDD = 3V
FULL-SCALE CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
FULL-SCALE CURRENT (mA)
MAX5550 toc07
-40 -15 10 35 60 85
29.72
29.74
29.76
29.78
29.80
29.82
29.84
29.86
29.88
VDD = 3V
VDD = 5V
SETTLING TIME
(FULL-SCALE POSITIVE STEP)
MAX5550 toc08
VOUT_
1V/div
10µs/div
CS
2V/div
RLOAD = 65Ω
CLOAD = 24pF
SETTLING TIME
(FULL-SCALE NEGATIVE STEP)
MAX5550 toc09
VOUT_
1V/div
10µs/div
CS
2V/div
RLOAD = 65Ω
CLOAD = 24pF
Typical Operating Characteristics
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ, TA= +25°C. unless otherwise noted).
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ, TA= +25°C. unless otherwise noted).
GLITCH IMPULSE
MAX5548 toc10
VOUT_
AC-COUPLED
40ns/div
CS
1V/div
10mV/div
RLOAD = 65Ω
CLOAD = 24pF
620
520
420
320
220
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX5550 toc11
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (nA)
NO LOAD, CODE = 0x00
620
520
420
320
220
-40 10-15 35 60 85
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5550 toc12
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
NO LOAD, CODE = 0x00
VDD = 5V
VDD = 3V
1.246
1.248
1.247
1.250
1.249
1.251
1.252
-40 10-15 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5550 toc14
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
NO LOAD, CODE = 0x00
1.25100
1.25075
1.25050
1.25025
1.25000
2.5 4.03.0 3.5 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX5550 toc13
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
NO LOAD, CODE = 0x00
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ, TA= +25°C. unless otherwise noted).
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
DIGITAL INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX5550 toc19
012345
1
10
NO LOAD, CODE = 0x00
VDD = 5V
VDD = 3V
2.80
2.75
2.70
2.65
2.60
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5550 toc15
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
NO LOAD, CODE = 0x00
INTERNAL REFERENCE
EXTERNAL REFERENCE
2.730
2.740
2.735
2.750
2.745
2.755
2.760
-40 10-15 35 60 85
SUPPLY CURRENT
vs. TEMPERATURE
MAX5550 toc16
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
NO LOAD, CODE = 0x00
VDD = 5V
VDD = 3V
WAKE-UP TIME
MAX5550 toc17
VOUT_
1V/div
400µs/div
CS
2V/div
RLOAD = 65Ω
CLOAD = 24pF
IOUT vs. VOUT
VOUT (V)
IOUT (mA)
MAX5550 toc18
012345
0
5
10
15
20
25
30
35
VDD = 3V VDD = 5V
DIGITAL FEEDTHROUGH
MAX5550 toc20
VOUT_
AC-COUPLED
10mV/div
400µs/div
SCLK
2V/div
RLOAD = 65Ω
CLOAD = 24pF
MAX5550
Detailed Description
Architecture
The MAX5550 10-bit, dual current-steering DAC (see
the Functional Diagram) operates with DAC update
rates up to 10Msps in SPI mode and 400ksps in I2C
mode. The converter consists of a 16-bit shift register
and input DAC registers, followed by a current-steering
array. The current-steering array generates full-scale
currents up to 30mA per DAC. An integrated +1.25V
bandgap reference, control amplifier, and an external
resistor determine each data converter’s full-scale out-
put range.
Reference Architecture and Operation
The MAX5550 provides an internal +1.25V bandgap ref-
erence or accepts an external reference voltage source
between +0.5V and +1.5V. REFIN serves as the input for
an external low-impedance reference source. Leave
REFIN unconnected in internal reference mode. Internal
or external reference mode is software selectable
through the SPI/I2C serial interface.
The MAX5550’s reference circuit (Figure 1) employs a
control amplifier to regulate the full-scale current (IFS)
for the current outputs of the DAC. This device has a
software-selectable full-scale current range (see the
command summary in Table 4). After selecting a cur-
rent range, an external resistor (RFSADJ_) sets the full-
scale current. See Table 1 for a matrix of IFS and
RFSADJ selections.
During startup, when the power is first applied, the
MAX5550 defaults to the external reference mode, and
to the 1mA–2mA full-scale current-range mode.
DAC Data
The 10-bit DAC data is decoded as offset binary, MSB
first, with 1 LSB = IFS / 1024, and converted into the cor-
responding current as shown in Table 2.
Serial Interface
The MAX5550 features a pin-selectable SPI/I2C serial
interface. Connect SPI/I2C to GND to select I2C mode, or
connect SPI/I2C to VDD to select SPI mode. SDA and
SCL (I2C mode) and DIN, SCLK, and CS (SPI mode)
facilitate communication between the MAX5550 and the
master. The serial interface remains active in shutdown.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1SCLK/SC Serial Clock Input. Connect SCL to VDD through a 2.4kΩ resistor in I2C mode.
2 DIN/SDA Serial Data Input. Connect SDA to VDD through a 2.4kΩ resistor in I2C mode.
3CS/A0 Chip-Select Input in SPI Mode/Address Select 0 in I2C Mode. CS is an active-low input. Connect A0 to VDD
or GND to set the device address in I2C mode.
4 SPI/I2C SPI/I2C Select Input. Connect SPI/I2C to VDD to select SPI mode, or connect SPI/I2C to GND to select I2C
mode.
5 DOUT/A1
Serial Data Output in SPI Mode/Address Select 1 in I2C Mode. Use DOUT to daisy chain the MAX5550 to
other devices or to read back in SPI mode. The digital data is clocked out on SCLK’s falling edge. Connect
A1 to VDD or GND to set the device address in I2C mode.
6, 13, 15 N.C. No Connection. Leave unconnected or connect to GND.
7 REFIN Refer ence Inp ut. D r i ve RE FIN w i th an exter nal r efer ence sour ce b etw een + 0.5V and + 1.5V . Leave RE FIN
unconnected i n i nter nal r efer ence m od e. Byp ass w i th a 0.1µF cap aci tor to GN D as cl ose to the d evi ce as p ossi b l e.
8, 16 GND Ground
9 OUTB DACB Output. OUTB provides up to 30mA of output current.
10 FSADJB D AC B Ful l - S cal e Ad j ust Inp ut. For m axi m um ful l - scal e outp ut cur r ent, connect a 20kΩ r esi stor b etw een FS AD JB
and GN D . For m i ni m um ful l - scal e cur r ent, connect a 40kΩ r esi stor b etw een FS AD JB and GN D .
11 FSADJA D AC A Ful l - S cal e Ad j ust Inp ut. For m axi m um ful l - scal e outp ut cur r ent, connect a 20kΩ r esi stor b etw een FS AD JA
and GN D . For m i ni m um ful l - scal e cur r ent, connect a 40kΩ r esi stor b etw een FS AD JA and GN D .
12 OUTA DACA Output. OUTA provides up to 30mA of output current.
14 VDD Power Supply Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1µF
capacitor as close to the device as possible.
I2C Compatibility (SPI/
I2C
= GND)
The MAX5550 is compatible with existing I2C systems
(Figure 2). SCL and SDA are high-impedance inputs;
SDA has an open-drain output that pulls the data line
low during the ninth clock pulse. SDA and SCL require
pullup resistors (2.4kΩor greater) to VDD. Optional
resistors (24Ω) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals. The communication protocol sup-
ports standard I2C 8-bit communications. The device’s
address is compatible with 7-bit I2C addressing proto-
col only. Ten-bit address formats are not supported.
Only write commands are accepted by the MAX5550.
Note: I2C readback is not supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
The MAX5550 requires nine clock cycles to transfer
data into or out of the DAC register. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), (a high-to-low transition on SDA with SCL high).
The master terminates a transmission with a STOP con-
dition (P), (a low-to-high transition on SDA while SCL is
high) (Figure 3). A START condition from the master
signals the beginning of a transmission to the
MAX5550. The master terminates transmission by issu-
ing a STOP condition. The STOP condition frees the
bus. If a repeated START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 9
+1.25V
REFERENCE
IFSADJ
RFSADJ
FSADJ_ OUT_
VDD
GND
CURRENT-SOURCE
ARRAY DAC
Figure 1. Reference Architecture and Output Current Adjustment
*Negative output current values = 0
FULL-SCALE OUTPUT CURRENT (mA)* RFSADJ (kΩ)
1mA–2mA 1.5mA–3mA 2.5mA–5mA 4.5mA–9mA 8mA–16mA 15mA–30mA Calculated 1% EIA Std
1.00 1.500 2.500 4.500 8.00 15.00 40 40.2
1.25 1.875 3.125 5.625 10.00 18.75 35 34.8
1.50 2.250 3.750 6.750 12.00 22.50 30 30.1
1.75 2.625 4.375 7.875 14.00 26.25 25 24.9
2.00 3.000 5.000 9.000 16.00 30.00 20 20.0
Table 1. Full-Scale Output Current and RFSADJ_ Selection Based on a +1.25V (typ)
Reference Voltage
*See the command summary in Table 4.
DAC CODE IOUT_
11 1111 1111
10 0000 0000
00 0000 0001*
00 0000 0000 0
Table 2. DAC Output Code Table
1023 1024
×−
II
I
FS OS
||
1023 1024
×−
II
FS OS
||
1023 1024
×−
II
FS OS
||
MAX5550
Early STOP Conditions
The MAX5550 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (Figure 4).
This condition is not allowed in the I2C format.
Repeated START Conditions
A repeated START (Sr) condition is used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5550’s
serial interface supports continuous write operations
with an Srcondition separating them.
Acknowledge Bit (ACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5550 (slave) generate acknowledge bits. To gen-
erate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
10 ______________________________________________________________________________________
SPSr
SCL
SDA
Figure 3. START and STOP Conditions
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 4. Early STOP Conditions
SCL
SDA
S
PSr
tSU:DAT
tHD:DAT
tRDA
tRCL
tFCL
tHIGH tLOW tHIGH
tLOW
tFCL
tRCL
tSU:STO
tHD:STA
tFDA
tSU:STA
Figure 2. I2C Serial-Interface Timing Diagram
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition fol-
lowed by its slave address. When the device recog-
nizes its slave address, it acquires the data and
executes the command. The first 5 bits (MSBs) of the
slave address have been factory programmed and are
always 01100. Connect A1 and A0 to VDD or GND to
program the remaining 2 bits of the slave address. Set
the least significant bit (LSB) of the address byte (R/W)
to zero to write to the MAX5550. After receiving the
address, the MAX5550 (slave) issues an acknowledge
by pulling SDA low for one clock cycle. I2C read com-
mands (R/W= 1) are not acknowledged by the
MAX5550.
Write Cycle
The write command requires 27 clock cycles. In write
mode (R/W= 0), the command/data byte that follows
the address byte controls the MAX5550 (Table 3). The
registers update on the rising edge of the 26th SCL
pulse. Prematurely aborting the write cycle does not
update the DAC. See Table 4 for a command summary.
SPI Compatibility (SPI/
I2C
= VDD)
The MAX5550 is compatible with the 3-wire SPI serial
interface (Figure 6). This interface mode requires three
inputs: chip-select (CS), data clock (SCLK), and data in
(DIN). Drive CS low to enable the serial interface and
clock data synchronously into the shift register on each
SCLK rising edge.
The MAX5550 requires 16 clock cycles to clock in 6
command bits (C5–C0) and 10 data bits (D9–D0)
(Figure 7). After loading data into the shift register,
drive CS high to latch the data into the appropriate
DAC register and disable the serial interface. Keep CS
low during the entire serial data stream to avoid corrup-
tion of the data. See Table 4 for a command summary.
Shutdown Mode
The MAX5550 has a software shutdown mode that
reduces the supply current to less than 1µA. Shutdown
mode disables the DAC outputs. The serial interface
remains active in shutdown. This provides the flexibilty to
update the registers while in shut down. Recycling the
power supply resets the device to the default settings.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
______________________________________________________________________________________ 11
12 8 9
ACKNOWLEDGE
SCL
S
SDA
Figure 5. Acknowledge Condition
S
T
A
R
T
ADDRESS
BYTE
R/ W*
COMMAND/DATA BYTE DATA BYTE
S
T
O
P
Master
SDA S0 1 10 0A1A00 C5C4C3C2C1C0D9 D8 D7D6D5D4D3D2D1D0 P
Slave
SDA
A
C
K
A
C
K
A
C
K
Table 3. Write Operation
*Read operation not supported.
MAX5550
Applications Information
Daisy Chaining (SPI/
I2C
= VDD)
In standard SPI-/QSPI™-/MICROWIRE™-compatible
systems, a microcontroller (µC) communicates with its
slave devices through a 3- or 4-wire serial interface.
The typical interface includes a chip-select signal (CS),
a serial clock (SCLK), a data input signal (DIN), and
sometimes a data signal output (DOUT). In this system,
the µC allots an independent slave-select signal (SS_)
to each slave device so that they can be addressed
individually. Only the slaves with their CS inputs assert-
ed low acknowledge and respond to the activity on the
serial clock and data lines. This is simple to implement
when there are very few slave devices in the system.
An alternative method is daisy chaining. Daisy
chaining, in serial-interface applications, is the method
of propagating commands through devices connected
in series (see Figure 8).
Daisy chain devices by connecting the DOUT of one
device to the DIN of the next. Connect the SCLK of all
devices to a common clock and connect the CS of all
devices to a common slave-select line. Data shifts out of
DOUT 16.5 clock cycles after it is shifted into DIN on the
falling edge of SCLK. In this configuration, the µC only
needs three signals (SS, SCK, and MOSI) to control all of
the slaves in the network. The SPI-/QSPI-/MICROWIRE-
compatible serial interface normally works at up to
10MHz, but must be slowed to 5MHz if daisy chaining.
DOUT is high impedance when CS is high.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
12 ______________________________________________________________________________________
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 D2 D1 D0C3 C2
SCLK
DIN
CS
C5 C4 C1 C0 D9 D8
Figure 7. SPI-Interface Format
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
tCSW
tCS1
tCSD
tCSH
LSB
tDO1
tCL
tCP
tCH
tDH
tDS
MSB
MSB
tCSS
tCSO
CS
SCLK
DIN
DOUT
tCSE
Figure 6. SPI-Interface Timing Diagram
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
______________________________________________________________________________________ 13
SERIAL DATA INPUT
C5 C4 C3 C2 C1 C0 D9–D0 FUNCTIONS
000000 XXXXXXXXXX No operation.
000001 10-bit DAC data Load DAC data to both DAC registers and both input registers from the
shift register.
000010 10-bit DAC data Load DAC register A and input register A from the shift register.
000011 10-bit DAC data Load DAC register B and input register B from the shift register.
000100 10-bit DAC data Load both channel input registers from the shift register, both DAC
registers are unchanged.
000101 10-bit DAC data Load input register A from the shift register; DAC register A is
unchanged.
000110 10-bit DAC data Load input register B from the shift register; DAC register B is
unchanged.
000111 XXXXXXXXXX Update both DAC registers from their corresponding input registers.
001001 XXXXXXXXXX Update DAC register A from input register A.
001010 XXXXXXXXXX Update DAC register B from input register B.
001011 XXXXXXXXXX Internal reference mode.
001100 XXXXXXXXXX External reference mode (default mode at power-up).
001101 XXXXXXXXXX Shut down both DACs.
001110 XXXXXXXXXX Shut down DACA.
001111 XXXXXXXXXX Shut down DACB.
010000 XXXXXXXXXX DACA 1mA–2mA full-scale current range mode (default mode at
power-up)
010001 XXXXXXXXXX DACA 1.5mA–3mA full-scale current range mode.
010010 XXXXXXXXXX DACA 2.5mA–5mA full-scale current range mode.
010011 XXXXXXXXXX DACA 4.5mA–9mA full-scale current range mode.
010100 XXXXXXXXXX DACA 8mA–16mA full-scale current range mode.
010101 XXXXXXXXXX DACA 15mA–30mA full-scale current range mode.
101101 XXXXXXXXXX Power up both DACs.
101110 XXXXXXXXXX Power up DACA.
101111 XXXXXXXXXX Power up DACB.
110000 XXXXXXXXXX DACB 1mA–2mA full-scale current range mode (default mode at
power-up)
110001 XXXXXXXXXX DACB 1.5mA–3mA full-scale current range mode.
110010 XXXXXXXXXX DACB 2.5mA–5mA full-scale current range mode.
110011 XXXXXXXXXX DACB 4.5mA–9mA full-scale current range mode.
110100 XXXXXXXXXX DACB 8mA–16mA full-scale current range mode.
110101 XXXXXXXXXX DACB 15mA–30mA full-scale current range mode.
Table 4. Command Summary
MAX5550
Power Sequencing
Ensure that the voltage applied to REFIN does not
exceed VDD at any time. If proper power sequencing is
not possible, connect an external Schottky diode
between REFIN and VDD to ensure compliance with the
absolute maximum ratings.
Power-Supply Bypassing and Ground
Management
Digital or AC transient signals on GND create noise at
the analog output. Return GND to the highest quality
ground plane available. For extremely noisy environ-
ments, bypass REFIN and VDD to GND with 1µF and
0.1µF capacitors with the 0.1µF capacitor as close to
the device as possible. Careful PC board ground layout
minimizes crosstalk between the DAC outputs and
digital inputs.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
14 ______________________________________________________________________________________
CONTROLLER
DEVICE
DIN(0)
DOUT(0)
SCLK
CS
MAX5550
DIN(1)
DOUT(1)
SCLK
CS
MAX5550
DIN(2)
DOUT(2)
SCLK
CS
MAX5550
Figure 8. Daisy-Chain Configuration
15
16
14
13
5
6
7
CS/AO
SPI/I2C
8
SCLK/SCL
FSADJB
OUTB
OUTA
13
VDD
4
12 10 9
N.C.
GND
GND
REFIN
N.C.
DOUT/A1
MAX5550
DIN/SDA FSADJA
2
11
N.C.
THIN QFN (3mm x 3mm)
TOP VIEW
Pin Configuration
Chip Information
PROCESS: BiCMOS
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
0.10 C0.08 C
0.10 M C A B
D
D/2
E/2
E
A1
A2
A
E2
E2/2
L
k
e
(ND - 1) X e
(NE - 1) X e
D2
D2/2
b
L
e
L
C
L
e
C
L
L
C
L
C
PACKAGE OUTLINE
21-0136
2
1
F
12, 16L THIN QFN, 3x3x0.8mm
MARKING
AAAA
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
EXPOSED PAD VARIATIONS
1.10T1633-1 0.95
CODES
PKG.
T1233-1 MIN.
0.95
NOM.
1.10
D2
1.251.100.951.25
NOM.
1.10
MAX.
1.25 MIN.
0.95 MAX.
1.25
E2
12
N
k
A2
0.25
NE
A1
ND
00.20 REF
--
3
0.02
3
0.05
L
e
E
0.45
2.90
b
D
A
0.20
2.90
0.70
0.50 BSC.
0.55
3.00
0.65
3.10
0.25
3.00
0.75
0.30
3.10
0.80
16
0.20 REF
0.25 -
0
4
0.02
4
-
0.05
0.50 BSC.
0.30
2.90
0.40
3.00
0.20
2.90
0.70
0.25
3.00
0.75
3.10
0.50
0.80
3.10
0.30
PKG
REF. MIN.
12L 3x3
NOM. MAX. NOM.
16L 3x3
MIN. MAX.
0.35 x 45°
PIN ID JEDEC
WEED-1
0.35 x 45° WEED-2
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
NOTES:
T1233-3 1.10 1.25 0.95 1.10 0.35 x 45°1.25 WEED-10.95
T1633F-3 0.65
T1633-4 0.95
0.80 0.95 0.65 0.80
1.10 1.25 0.95 1.10
0.225 x 45°
0.95 WEED-2
0.35 x 45°
1.25 WEED-2
T1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45°
1.25 WEED-2
NO
DOWN
BONDS
ALLOWED
YES
NO
YES
N/A
NO
PACKAGE OUTLINE
21-0136 2
2
F
12, 16L THIN QFN, 3x3x0.8
YESWEED-11.251.100.95 0.35 x 45°1.251.100.95T1233-4
T1633FH-3 0.65 0.80 0.95 0.225 x 45°0.65 0.80 0.95 WEED-2 N/A
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
Freed 7/13/05
