MC100LVEP05 - ON Semiconductor

© Semiconductor Components Industries, LLC, 2007

May, 2007 - Rev. 0

1Publication Order Number:

MC100LVEP05/D

MC100LVEP05

2.5V / 3.3V ECL 2-Input

Differential AND/NAND

Description

The MC100LVEP05 is a 2-input differential AND/NAND gate.

The MC100LVEP05 is the low voltage version of the MC100EP05

and is functionally equivalent to the EL05 and LVEL05 devices. With

AC performance much faster than the LVEL05 device, the

MC100LVEP05 is ideal for low voltage applications requiring the

fastest AC performance available.

The 100 Series contains temperature compensation.

Features

•220 ps Typical Propagation Delay

•Input Clock Frequency > 3 GHz

•0.2 ps Typical RMS Random Clock Period Jitter

•LVPECL Mode Operating Range: VCC = 2.375 V to 3.6 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = -2.375 V to -3.6 V

•Open Input Default State

•Q Output Will Default LOW with Inputs Open

•These are Pb-Free Devices*

*For additional information on our Pb-Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Y = Year

W = Work Week

G= Pb-Free Package

K = MC100

M = Date Code

A = Assembly Location

L = Wafer Lot

MARKING DIAGRAMS*

TSSOP-8

DT SUFFIX

CASE 948R

ALYWG

KU05

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*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

DFN8

MN SUFFIX

CASE 506AA

(Note: Microdot may be in either location)

6N MG

MC100LVEP05

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igure 1. 8-Lead Pinout (Top View) and Logic

Diagram

VEE

VCC

QD1

Table 1. PIN DESCRIPTION

Pin Function

D0*, D1*, D0**, D1** ECL Data Inputs

Q, Q ECL Data Outputs

VCC Positive Supply

VEE Negative Supply

EP Exposed pad must be connected to a

sufficient thermal conduit. Electrically

connect to the most negative supply

or leave floating open.

* Pins will default LOW when left open.

**Pins will default to VCC/2when left open.

Table 2. TRUTH TABLE

D0 D1 D0 D1 Q Q

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor 37.5 kW

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

TSSOP-8

DFN8

Pb Pkg

Level 1

Pb-Free Pkg

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in

Transistor Count 167 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V -6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

-6

Iout Output Current Continuous

Surge

100

TAOperating Temperature Range -40 to +85 °C

Tstg Storage Temperature Range -65 to +150 °C

qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

TSSOP-8

185

140

°C/W

qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP-8 41 to 44 °C/W

qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder 3 sec @ 260°C 265 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2)

-40 °C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 15 25 32 17 27 36 19 28 38 mA

VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

VOL Output LOW Voltage (Note 3) 555 730 900 555 730 900 555 730 900 mV

VIH Input HIGH Voltage (Single-Ended) 1355 1620 1355 1620 1355 1620 mV

VIL Input LOW Voltage (Single-Ended) 555 900 555 900 555 900 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Notes 4, 5)

1.2 2.5 1.2 2.5 1.2 2.5 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.

3. All loading with 50 W to VCC - 2.0 V.

4. Single-ended input CLK pin operation is limited to VCC  3.0 V in PECL mode.

5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6)

-40 °C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 15 25 32 17 27 36 19 28 38 mA

VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 7) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV

VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 8)

1.2 3.3 1.2 3.3 1.2 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.

7. All loading with 50 W to VCC - 2.0 V.

8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -2.375 V to -3.6 V (Note 9)

-40 °C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 15 25 32 17 27 36 19 28 38 mA

VOH Output HIGH Voltage (Note 10) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mV

VOL Output LOW Voltage (Note 10) -1945 -1770 -1600 -1945 -1770 -1600 -1945 -1770 -1600 mV

VIH Input HIGH Voltage (Single-Ended) -1 165 -880 -1 165 -880 -1 165 -880 mV

VIL Input LOW Voltage (Single-Ended) -1945 -1600 -1945 -1600 -1945 -1600 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 11)

VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. Input and output parameters vary 1:1 with VCC.

10.All loading with 50 W to VCC - 2.0 V.

11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.6 V or VCC = 2.375 V to 3.6 V; VEE = 0 V (Note 12)

Symbol Characteristic

-40 °C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency

(Figure 2)

3.0 3.0 3.0 GHz

tPLH,

tPHL

Propagation Delay to

Output Differential

160 210 260 170 220 270 210 260 320 ps

tJITTER RMS Random Clock Jitter fin  3.0 GHz

(Figure 2)

0.2 1 0.2 1 0.2 1.5 ps

VPP Input Voltage Swing

(Differential Configuration)

150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times Q

(20% - 80%)

70 120 170 80 130 180 100 150 200 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

12.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V.

MC100LVEP05

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Figure 2. Fmax @ 255C

FREQUENCY (GHz)

3.3 V

VOUTamplitude (mVpp)

850

750

650

550

450

350

250

1.0 1.5 2.0 2.5 3.0

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D - Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC - 2.0 V

MC100LVEP05

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ORDERING INFORMATION

Device Package Shipping†

MC100LVEP05DTG TSSOP-8

(Pb-Free)

100 Units / Rail

MC100LVEP05DTR2G TSSOP-8

(Pb-Free)

2500 / Tape & Reel

MC100LVEP05MNTXG DFN8

(Pb-Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D - ECL Clock Distribution Techniques

AN1406/D - Designing with PECL (ECL at +5.0 V)

AN1503/D -ECLinPSt I/O SPiCE Modeling Kit

AN1504/D - Metastability and the ECLinPS Family

AN1568/D - Interfacing Between LVDS and ECL

AN1672/D - The ECL Translator Guide

AND8001/D - Odd Number Counters Design

AND8002/D - Marking and Date Codes

AND8020/D - Termination of ECL Logic Devices

AND8066/D - Interfacing with ECLinPS

AND8090/D - AC Characteristics of ECL Devices

MC100LVEP05

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

-U-

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

-T-

-V-

-W-

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP-8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R-02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

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PACKAGE DIMENSIONS

DFN8

CASE 506AA-01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION:

MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED

BETWEEN 0.25 AND 0.30 MM FROM

TERMINAL.

4. COPLANARITY APPLIES TO THE

EXPOSED PAD AS WELL AS THE

TERMINALS.

ÇÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 ---

L0.25 0.35

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

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MC100LVEP05/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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