54F181LMQB. - NATIONAL SEMICONDUCTOR

54F181,74F181

54F181 74F181 4-Bit Arithmetic Logic Unit

Literature Number: SNOS164A

TL/F/9491

54F/74F181 4-Bit Arithmetic Logic Unit

August 1995

54F/74F181

4-Bit Arithmetic Logic Unit

General Description

The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can

perform all the possible 16 logic operations on two variables

and a variety of arithmetic operations. It is 40% faster than

the Schottky ALU and only consumes 30% as much power.

Features

YFull lookahead for high-speed arithmetic operation on

long words

YGuaranteed 4000V minimum ESD protection

Commercial Military Package Package Description

Number

74F181PC N24A 24-Lead (0.600×Wide) Molded Dual-In-Line

74F181SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line

54F181DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line

54F181SDM (Note 2) J24F 24-Lead (0.300×) Ceramic Dual-In-Line

74F181SC (Note 1) M24B 24-Lead (0.300×) Molded Small Outline, JEDEC

54F181FM (Note 2) W24C 24-Lead Cerpack

54F181LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier,Type C

Note 1: Devices also available in 13×reel. Use suffix eSCX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.

Connection Diagrams

Pin Assignment

for DIP, SOIC and Flatpak

TL/F/9491–1

Pin Assignment

for LCC

TL/F/9491–2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Obsolete

Logic Symbols

Active-HIGH Operands

TL/F/9491–3

Active-LOW Operands

TL/F/9491–4

IEEE/IEC

TL/F/9491–10

Unit Loading/Fan Out

54F/74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

A0–A3A Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA

B0–B3B Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA

S0–S3Function Select Inputs 1.0/4.0 20 mA/b2.4 mA

M Mode Control Input 1.0/1.0 20 mA/b0.6 mA

CnCarry Input 1.0/5.0 20 mA/b3.0 mA

F0–F3Function Outputs (Active LOW) 50/33.3 b1 mA/20 mA

AeB Comparator Output OC*/33.3 */20 mA

GCarry Generate Output (Active LOW) 50/33.3 b1 mA/20 mA

PCarry Propagate Output (Active LOW) 50/33.3 b1 mA/20 mA

Cna4Carry Output 50/33.3 b1 mA/20 mA

*OC-Open Collector

Functional Description

The ’F181 is a 4-bit high-speed parallel Arithmetic Logic

Unit (ALU). Controlled by the four Function Select inputs

(S0–S3) and the Mode Control input (M), it can perform all

the 16 possible logic operations or 16 different arithmetic

operations on Active HIGH or Active LOW operands. The

Function Table lists these operations.

When the Mode Control input (M) is HIGH, all internal car-

ries are inhibited and the device performs logic operations

on the individual bits as listed. When the Mode Control input

is LOW, the carries are enabled and the device performs

arithmetic operations on the two 4-bit words. The device

incorporates full internal carry lookahead and provides for

either ripple carry between devices using the Cna4output,

or for carry lookahead between packages using the signals

P(Carry Propagate) and G (Carry Generate). In the Add

mode, P indicates that F is 15 or more, while G indicates

that F is 16 or more. In the Subtract mode P indicates that F

is zero or less, while G indicates that F is less than zero. P

and G are not affected by carry in. When speed require-

ments are not stringent, the ’F181 can be used in a simple

Ripple Carry mode by connecting the Carry output (Cna4)

signal to the Carry input (Cn) of the next unit. For high speed

operation the device is used in conjunction with a carry look-

ahead circuit. One carry lookahead package is required for

each group of four ’F181 devices. Carry lookahead can be

provided at various levels and offers high speed capability

over extremely long word lengths.

The AeB output from the device goes HIGH when all four F

outputs are HIGH and can be used to indicate logic equiva-

lence over four bits when the unit is in the Subtract mode.

The AeB output is open collector and can be wired AND

with other AeB outputs to give a comparison for more than

four bits. The AeB signal can also be used with the Cna4

signal to indicate AlB and AkB.

The Function Table lists the arithmetic operations that are

performed without a carry in. An incoming carry adds a one

to each operation. Thus, select code LHHL generates A

minus B minus 1 (2s complement notation) without a carry

in and generates A minus B when a carry is applied. Be-

cause subtraction is actually performed by complementary

addition (1s complement), a carry out means borrow; thus a

carry is generated when there is no underflow and no carry

is generated when there is underflow. As indicated, this de-

vice can be used with either active LOW inputs producing

active LOW outputs or with active HIGH inputs producing

active HIGH outputs. For either case the table lists the oper-

ations that are performed to the operands labeled inside the

logic symbol.

Obsolete

’F181 Operation Table

Logic Arithmetic Arithmetic

S0S1S2S3(MeH) (MeL, C0eInactive) (MeL, C0eActive)

LLLL A A minus 1 A

HLLL A

B A

B minus 1 A #B

LHLL A

Bminus 1 A #B

H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero

LLHL A

BA plus (A aB) A plus (A aB) plus 1

HLHL B A

B plus (A aB)A

B plus (A aB) plus 1

LHHL A

BA minus B minus 1 A minus B

HHHL A

B A

Bplus 1

LLLH A

B A plus (A aB) A plus (A aB plus 1

HLLH A

B A plus B A plus B plus 1

LHLH B A

Bplus (A aB) A #B plus (A aB) plus 1

HHLH A

B plus 1

L L H H Logic ‘‘0’’ A plus A (2 cA) A plus A (2 cA) plus 1

HLHH A

BA plus A #B A plus A #B plus 1

LHHH A

B A plus A #B A plus A #B plus 1

H H H H A A A plus 1

LLLL A A A plus 1

HLLL A

B A

B plus 1

LHLL A

B A

Bplus 1

H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero

LLHL A

BA plus (A #B) A plus A #B plus 1

HLHL B A

Bplus (A aB) A #B plus (A aB) plus 1

LHHL A

B A minus B minus 1 A minus B

HHHL A

B A

Bminus 1 A #B

LLLH A

B A plus A #B A plus A #B plus 1

HLLH A

BA plus B A plus B plus 1

LHLH B A

B plus (A aB)A

B plus (A aB) plus 1

HHLH A

B minus 1 A #B

L L H H Logic ‘‘1’’ A plus A (2 cA) A plus A (2 cA) plus 1

HLHH A

BA plus (A aB) A plus (AaB) plus 1

LHHH A

B A plus (A aB) A plus (AaB) plus 1

H H H H A A minus 1 A

LLLL A A minus 1 A

HLLL A

Bminus 1 A #B

LHLL A

B A

B minus 1 A #B

H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero

LLHL A

B A plus (A aB) A plus (A aB) plus 1

HLHL B A

Bplus (A aB) A #B plus (A aB) plus 1

LHHL A

B A plus B A plus B plus 1

HHHL A

B plus 1

LLLH A

BA plus (A aB) A plus (A aB) plus 1

HLLH A

BA minus B minus 1 A minus B

LHLH B A

B plus (A aB)A

B plus (A aB) plus 1

HHLH A

B A

Bplus 1

L L H H Logic ‘‘0’’ A plus A (2 cA) A plus A (2 cA) plus 1

HLHH A

B A plus A #B A plus A #B plus 1

LHHH A

BA plus A #B A plus A #B plus 1

H H H H A A A plus 1

LLLL A A A plus 1

HLLL A

B A

Bplus 1

LHLL A

B A

B plus 1

H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero

LLHL A

B A plus A #B A plus A #B plus 1

HLHL B A

B plus (A aB)A

Bplus (A aB) plus 1

LHHL A

BA plus B A plus B plus 1

HHHL A

B minus 1 A #B

LLLH A

BA plus A #B A plus A #B plus 1

HLLH A

B A minus B minus 1 A minus B

LHLH B A

Bplus (A aB) A #B plus (A aB) plus 1

HHLH A

B A

Bminus 1 A #B

L L H H Logic ‘‘1’’ A plus A (2 cA) A plus A (2 cA) plus 1

HLHH A

B A plus (A aB) A plus (AaB) plus 1

LHHH A

BA plus (A aB) A plus (AaB) plus 1

H H H H A A minus 1 A

a. All Input Data Inverted

b. All Input Data True

c. A Input Data Inverted;

B Input Data True

d. A Input Data True;

B Input Date Inverted

Obsolete

Logic Diagram

TL/F/9491–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Obsolete

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATEÉOutput b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

ESD Last Passing Voltage (Min) 4000V

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 54F/74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.2 V Min IIN eb

18 mA

VOH Output HIGH 54F 10% VCC 2.5 IOH eb

1mA

Voltage 74F 10% VCC 2.5 V Min IOH eb

1mA

74F 5% VCC 2.7 IOH eb

1mA

OL Output LOW 54F 10% VCC 0.5 V Min IOL e20 mA

Voltage 74F 10% VCC 0.5 IOL e20 mA

IIH Input HIGH 54F 20.0

mA Max VIN e2.7V

Current 74F 5.0

IBVI Input HIGH Current 54F 100

mA Max VIN e7.0V

Breakdown Test 74F 7.0

ICEX Output HIGH 54F 250

mA Max VOUT eVCC (Fn,G,P,C

)

Leakage Current 74F 50

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.6 VIN e0.5V (M)

b1.8 mA Max VIN e0.5V (A0,A

)

2.4 VIN e0.5V (Sn,A

)

3.0 VIN e0.5V (Cn)

IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V (Fn,G,P,C

)

OHC Open Collector, Output 250 mA Min VOeVCC (A eB)

OFF Leakage Test

ICCH Power Supply Current 43 65.0 mA Max VOeHIGH

ICCL Power Supply Current 43 65.0 mA Max VOeLOW

Obsolete

AC Electrical Characteristics

74F 54F 74F

TAea

25§CTA,V

CC eMil TA,V

CC eCom

Symbol Parameter VCC ea

5.0V CLe50 pF CLe50 pF Units

CLe50 pF

Path Mode Min Typ Max Min Max Min Max

tPLH Propagation Delay 3.0 6.4 8.5 3.0 10.0 3.0 9.5 ns

tPHL Cnto Cna43.0 6.1 8.0 3.0 9.5 3.0 9.0

tPLH Propagation Delay 5.0 10.0 13.0 5.0 15.5 5.0 14.0 ns

tPHL A or B to Cna4Sum 4.0 9.4 12.0 3.5 16.5 4.0 13.0

tPLH Propagation Delay 5.0 10.8 14.0 5.0 17.0 5.0 15.0 ns

tPHL A or B to Cna4Dif 5.0 10.0 13.0 4.0 15.0 5.0 14.0

tPLH Propagation Delay 3.0 6.7 8.5 2.5 16.0 3.0 9.5 ns

tPHL Cnto F Any 3.0 6.5 8.5 2.5 12.0 3.0 9.5

tPLH Propagation Delay 3.0 5.7 7.5 2.5 9.0 3.0 8.5 ns

tPHL A or B or G Sum 3.0 5.8 7.5 2.5 9.5 3.0 8.5

tPLH Propagation Delay 3.0 6.5 8.5 2.5 11.5 3.0 9.5 ns

tPHL A or B to G Dif 3.0 7.3 9.5 2.5 11.0 3.0 10.5

tPLH Propagation Delay 3.0 5.0 7.0 2.5 8.5 3.0 8.0 ns

tPHL A or B to P Sum 3.0 5.5 7.5 3.0 9.5 3.0 8.5

tPLH Propagation Delay 3.0 5.8 7.5 2.5 11.0 3.0 8.5 ns

tPHL A or B to P Dif 4.0 6.5 8.5 3.0 11.0 4.0 9.5

tPLH Propagation Delay 3.0 7.0 9.0 3.0 14.5 3.0 10.0 ns

tPHL Aior Bito FiSum 3.0 7.2 10.0 3.0 14.5 3.0 10.0

tPLH Propagation Delay 3.0 8.2 11.0 3.0 17.5 3.0 12.0 ns

tPHL Aior Bito FiDif 3.0 5.0 11.0 3.0 14.5 3.0 12.0

tPLH Propagation Delay 4.0 8.0 10.5 3.5 16.5 4.0 11.5 ns

tPHL Any A or B to Any F Sum 4.0 7.8 10.0 4.0 13.5 4.0 11.0

tPLH Propagation Delay 4.5 9.4 12.0 3.5 17.5 4.5 13.0 ns

tPHL Any A or B to Any F Dif 3.5 9.4 12.0 3.0 14.0 3.5 13.0

tPLH Propagation Delay 4.0 6.0 9.0 3.5 14.5 4.0 10.0 ns

tPHL A or B to F Logic 4.0 6.0 10.0 3.0 15.5 4.0 11.0

tPLH Propagation Delay 11.0 18.5 27.0 8.0 35.0 11.0 29.0 ns

tPHL A or B to A eB Dif 6.0 9.8 12.5 5.5 21.0 6.0 13.5

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 181 P C

Temperature Range Family Special Variations

74F eCommercial QB eMilitary grade device with

54F eMilitary environmental and burn-in

processing

Device Type

Temperature Range

Package Code CeCommercial (0§Ctoa

70§C)

PePlastic DIP MeMilitary (b55§Ctoa

125§C)

SP eSlim Plastic DIP

DeCeramic DIP

SD eSlim Ceramic DIP

FeFlatpak

LeLeadless Chip Carrier (LCC)

SeSmall Outline SOIC JEDEC

Obsolete

Physical Dimensions inches (millimeters)

28-Lead Ceramic Leadless Chip Carrier (L)

NS Package Number E28A

24-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J24A

Obsolete

Physical Dimensions inches (millimeters) (Continued)

24-Lead (0.300×Wide) Ceramic Dual-In-Line Package (SD)

NS Package Number J24F

24-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)

NS Package Number M24B

Obsolete

Physical Dimensions inches (millimeters) (Continued)

24-Lead (0.600×Wide) Molded Dual-In-Line Package (P)

NS Package Number N24A

24-Lead (0.300×Wide) Molded Dual-In-Line Package (SP)

NS Package Number N24C

Obsolete

54F/74F181 4-Bit Arithmetic Logic Unit

Physical Dimensions inches (millimeters) (Continued)

24-Lead Ceramic Flatpak (F)

NS Package Number W24C

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Obsolete

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