LTC3111EMSE#PBF - LINEAR TECHNOLOGY

LTC3111

3111fa

For more information www.linear.com/LTC3111

LOAD CURRENT (A)

0.0001

EFFICIENCY (%)

100

0.001 1 100.01 0.1

3111 TA01b

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

TYPICAL APPLICATION

FEATURES DESCRIPTION

15V, 1.5A Synchronous

Buck-Boost DC/DC

Converter

The LT C

3111 is a fixed frequency, synchronous buck-

boost DC/DC converter with an extended input and output

range. The unique 4-switch, single inductor architecture

provides low noise and seamless operation from input

voltages above, below or equal to the output voltage.

With an input and output range of 2.5V to 15V, the LTC3111

is well suited for a wide variety of single or multiple-cell

batteries, back-up capacitor or wall adapter source applica-

tions. Low RDS(ON) internal N-channel MOSFET switches

and selectable PWM or Burst Mode operation produce

high efficiency over a wide range of operating conditions.

An accurate RUN pin allows the user to program the

turn-on threshold voltage of the converter. Other features

include: short-circuit protection, internal soft-start and

thermal shutdown.

The LTC3111 is offered in both thermally enhanced

14-lead (3mm × 4mm × 0.75mm) DFN and 16-lead MSOP

packages.

5V, 800kHz Wide Input Voltage Buck-Boost Regulator

APPLICATIONS

n Regulated Output with VIN Above, Below

or Equal to VOUT

n 2.5V to 15V Input and Output Voltage Range

n 1.5A Continuous Output Current: VIN ≥ 5V,

VOUT = 5V, PWM Mode

n Single Inductor

n Accurate RUN Threshold

n Up to 95% Efficiency

n 800kHz Switching Frequency, Synchronizable

Between 600kHz and 1.5MHz

n 49µA No-Load Quiescent Current in Burst Mode

Operation

n Output Disconnect in Shutdown

n Shutdown Current < 1µA

n Internal Soft-Start

n Small, Thermally Enhanced 14-Lead (3mm × 4mm ×

0.75mm) DFN and 16-Lead MSOP Packages

n 3.3V or 5V from 1, 2 or 3 Li-Ion, Multiple-Cell

Alkaline/NiMH Batteries

n RF Transmitters

n Military, Industrial Power Systems

L, LT , LT C , LT M , Linear Technology, the Linear logo, Burst Mode, LTspice are registered

trademarks and No RSENSE and PowerPath are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 6404251, 6166527, 5481178, 6304066, 6580258.

SW1 0.1µF

27pF

1µF

33pF

191k

3111 TA01a

20k

680pF 26.1k

0.1µF

VIN

2.5V TO 15V

4.7µH

SW2

BST1 BST2

VIN

LTC3111

PGNDSGND

VOUT

22µF

VOUT

1.5A

(VIN > 5V)

10µF

PWM/SYNC

BURST PWM

RUN FB

VCC

SNSGND

COMP

OFF ON

Efficiency at 5VOUT

LTC3111

3111fa

For more information www.linear.com/LTC3111

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

VIN Voltage ................................................. –0.3V to 16V

VOUT Voltage .............................................. –0.3V to 16V

SW1 Voltage (Note 4) ................... –0.3V to (VIN + 0.3V)

SW2 Voltage (Note 4) .................–0.3V to (VOUT + 0.3V)

BST1 Voltage ...................(VSW1 – 0.3V) to (VSW1 + 6V)

BST2 Voltage ...................(VSW2 – 0.3V) to (VSW2 + 6V)

RUN Voltage............................................... –0.3V to 16V

PWM/SYNC, VCC Voltage ............................. –0.3V to 6V

FB, COMP, Voltage ....................................... –0.3V to 6V

(Notes 1, 3)

SGND

PWM/SYNC

VCC

VOUT

SW2

BST2

COMP

SNSGND

RUN

VIN

SW1

BST1

TOP VIEW

PGND

DE PACKAGE

14-LEAD (4mm × 3mm) PLASTIC DFN

TJMAX = 150°C, θJA = 43°C/W, θJC = 5°C/W

EXPOSED PAD (PIN 15) IS PGND, MUST BE SOLDERED TO PCB

COMP

SNSGND

RUN

VIN

SW1

BST1

PGND

SGND

PWM/SYNC

VCC

VOUT

SW2

BST2

PGND

TOP VIEW

PGND

MSE PACKAGE

16-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3111EDE#PBF LTC3111EDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C

LTC3111IDE#PBF LTC3111IDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C

LTC3111HDE#PBF LTC3111HDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 150°C

LTC3111MPDE#PBF LTC3111MPDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –55°C to 150°C

LTC3111EMSE#PBF LTC3111EMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C

LTC3111IMSE#PBF LTC3111IMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C

LTC3111HMSE#PBF LTC3111HMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 150°C

LTC3111MPMSE#PBF LTC3111MPMSE#TRPBF 3111 16-Lead Plastic MSOP –55°C to 150°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Operating Junction Temperature Range (Notes 2, 5)

LTC3111E, LTC3111I ........................... –40°C to 125°C

LTC3111H ........................................... –40°C to 150°C

LTC3111MP ........................................ –55°C to 150°C

Maximum Junction Temperature (Note 3)............. 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10sec)

MSOP ............................................................... 300°C

LTC3111

3111fa

For more information www.linear.com/LTC3111

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = PWM/SYNC = RUN = 5V unless otherwise

noted.

PARAMETER CONDITION MIN TYP MAX UNITS

Input Operating Range l 2.5 15 V

VIN UVLO Threshold Rising l1.9 2.1 2.3 V

VIN UVLO Hysteresis 200 mV

VCC UVLO Threshold Rising l2.2 2.35 2.5 V

VCC UVLO Hysteresis 190 mV

Output Voltage Adjust Range l2.5 15 V

INTVCC Clamp Voltage VIN = 5V or 15V l 3.9 4.2 4.5 V

Quiescent Current—Burst Mode Operation FB = 1V, PWM/SYNC = 0V 55 80 µA

Quiescent Current—Shutdown RUN = VOUT = VCC = 0V, Not Including Switch Leakage 0 1 µA

Feedback Voltage PWM Operation l0.78 0.8 0.82 V

Feedback Leakage FB = 0.8V 0 50 nA

NMOS Switch Leakage Switches A, B, C, D, VIN = VOUT = 15V 0.5 5 µA

NMOS Switch On-Resistance Switch A 90 mΩ

Switch B, C, D 105 mΩ

Input Current Limit l2.3 3 3.7 A

Peak Current Limit 5.8 A

Burst Current Limit PWM/SYNC = 0V 0.8 A

Burst Zero Current Threshold PWM/SYNC = 0V 0.1 A

Reverse Current Limit –1 A

Maximum Duty Cycle Percentage of the Period SW2 is Low in Boost Mode

(Note 7)

l85 90 %

Minimum Duty Cycle Percentage of the Period SW1 is Low in Buck Mode

(Note 7)

l0 %

SW1, SW2 Minimum Low Time (Note 7) 160 ns

Frequency PWM/SYNC = 5V l700 800 900 kHz

SYNC Frequency Range (Note 6) l600 1500 kHz

PWM/SYNC Threshold l0.5 0.9 1.5 V

RUN Threshold to Enable VCC Rising l0.35 0.8 1.15 V

RUN Threshold to Disable VCC Falling l0.3 V

RUN Threshold to Enable Switching Rising l1.15 1.18 1.23 V

RUN Hysteresis 120 mV

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetimes.

Note 2: The LTC3111 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3111E is guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3111I is guaranteed to meet performance specifications from –40°C

to 125°C junction temperature, the LTC3111H is guaranteed to meet

performance specifications from –40°C to 150°C junction temperature

and the LTC3111MP is guaranteed and tested to meet performance

specifications from –55°C to 150°C junction temperature. High junction

temperatures degrade operating lifetimes: operating lifetime is derated

for junction temperatures greater than 125°C. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal resistance and other environmental factors.

LTC3111

3111fa

For more information www.linear.com/LTC3111

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Output Current

in PWM Mode vs VIN

Maximum Load Current in Burst

Mode Operation vs VIN Wide VIN to 5VOUT Efficiency

Wide VIN to 5VOUT Power Loss Wide VIN to 3.3VOUT Efficiency Wide VIN to 3.3VOUT Power Loss

ELECTRICAL CHARACTERISTICS

Note 3: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 150°C when overtemperature protection is

active. Continuous operation above the specified maximum operating

junction temperature may impair device reliability.

Note 4: Voltage transients on the switch pins beyond the DC limit specified

in the Absolute Maximum Ratings, are non-disruptive to normal operation

when using good layout practices, as shown on the demo board or

described in the data sheet and application notes.

Note 5: The junction temperature (TJ in °C) is calculated from the ambient

temperature (TA in °C) and power dissipation (PD in Watts) according to

the formula:

TJ = TA + (PD • θJA)

where θJA (in °C/W) is the package thermal impedance.

Note 6: SYNC frequency range is tested with a square wave. Operation

with 100ns minimum high or low time is assured by design.

Note 7: Switch timing measurements are made in an open-loop test

configuration. Timing in the application may vary somewhat from these

values due to differences in the switch pin voltage during the non-overlap

durations when the switch pin voltage is influenced by the magnitude and

direction of the inductor current.

TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified

VIN (V)

MAXIMUM OUTPUT CURRENT (A)

0.2

0.6

0.8

1.0

8 9 10 1211 1413

2.0

1.8

3111 G01

0.4

34567 15

1.2

1.4

1.6

VOUT = 3.3V, L = 4.7µH

VOUT = 5V, L = 6.8µH

VOUT = 12V, L = 10µH

INPUT CURRENT LIMIT = 2.3A

VIN (V)

234

MAXIMUM OUTPUT CURRENT (mA)

400

600

3111 G02

200

05678910 11 12 13 14 15

800

300

500

100

700

VOUT = 3.3V

VOUT = 5V

VOUT = 12V

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.0001 0.01 0.1 1 10

3111 G03

0.001

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

LOAD CURRENT (A)

0.0001 0.001

0.0001

0.001

POWER LOSS (W)

0.1

0.01 0.1 1 10

3111 G04

0.01

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

LOAD CURRENT (A)

0.0001 0.001

EFFICIENCY (%)

100

0.01 10.1

3111 G05

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

LOAD CURRENT (A)

0.01

POWER LOSS (W)

0.1

0.01 0.1 1

3111 G06

0.0001

0.001

0.0001 0.001

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

LTC3111

3111fa

For more information www.linear.com/LTC3111

TYPICAL PERFORMANCE CHARACTERISTICS

800kHz PWM Mode No-Load Input

Current

Burst Mode No-Load Current with

VCC from VIN or Back-Fed from

VOUT with an Optional Diode

VCC Voltage vs VIN PWM Mode

No Load

VCC Voltage vs VCC Current

Normalized N-Channel MOSFET

Resistance vs VCC

Wide VIN to 12VOUT Efficiency

TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified

Wide VIN to 12VOUT Power Loss

12VIN to 12VOUT Efficiency at

f = 600kHz, 800kHz, 1MHz and

1.5MHz with L = 10µH

LOAD CURRENT (A)

0.0001 0.001

EFFICIENCY (%)

100

0.01 10.1

3111 G07

VIN = 2.7V

VIN = 5V

VIN = 12V

PWM

BURST

LOAD CURRENT (A)

0.0001 0.001

0.0001

0.001

POWER LOSS (W)

0.1

0.01 0.1 1 10

3111 G08

0.01

VIN = 2.7V

VIN = 5V

VIN = 12V

BURST

PWM

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.01 10.1

3111 G09

f = 600kHz

f = 800kHz

f = 1MHz

f = 1.5MHz

VIN (V)

VIN CURRENT (mA)

31111 G10

04 6 83 135 7 11109 14 15

VIN (V)

VIN CURRENT (µA)

150

200

250

9 10 11 12 13 14

450

3111 G11

100

43 5 6 7 8 15

300

350

400

VCC FROM VIN

VCC FROM VOUT

VOUT = 5V

VIN (V)

VCC VOLTAGE (V)

3.7

4.1

4.5

73 84 95 106 11

3111 G12

3.3

2.9

3.5

3.9

4.3

3.1

2.7

2.5 12 13 14 15

CURRENT FROM VCC (mA)

VCC (V)

3.9

4.0

4.1

60 7030 40 50

3111 G13

3.8

3.7

10 20 80

3.6

3.5

4.2

VCC (V)

2.5

NORMALIZED MOSFET RESISTANCE

1.05

1.10

1.15

4.0 5.0

3111 G14

1.00

0.95

0.90 3.0 3.5 4.5

1.20

1.25

1.30

Normalized N-Channel MOSFET

Resistance vs Temperature

TEMPERATURE (°C)

–50

0.6

NORMALIZED MOSFET RESISTANCE

0.7

0.9

1.0

1.1

1.6

1.3

050

3111 G15

0.8

1.4

1.5

1.2

100 150

LTC3111

3111fa

For more information www.linear.com/LTC3111

TYPICAL PERFORMANCE CHARACTERISTICS

RUN Threshold to Enable/Disable

VCC vs VIN

PWM Mode Input, Peak and

Reverse Current Limits vs

Temperature

Burst Mode Peak Current, IZERO

Limits vs Temperature

Feedback Pin Program Voltage

vs Temperature

RUN Threshold to Enable/Disable

VCC vs Temperature

VCC and VIN UVLO Voltage

Thresholds vs Temperature

RUN Threshold to Enable/Disable

Switching vs VIN

TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified

TEMPERATURE (°C)

–50

FEEDBACK PIN PROGRAM VOLTAGE (mV)

798.5

799.0

799.5

150

3111 G16

798.0

797.5

796.5 050 100

797.0

800.5

800.0

TEMPERATURE (°C)

–50

VCC AND VIN UVLO THRESHOLDS (V)

2.0

2.1

2.2

150

3111 G17

1.9

1.8

1.7

1.5 050 100

1.6

2.4

2.3 VCC UVLO RISING

VIN UVLO RISING

VCC UVLO FALLING

VIN UVLO FALLING

VIN (V)

RUN THRESHOLD TO ENABLE VCC (V)

0.80

0.90

1.00

3111 G18

0.70

0.60

0.75

0.85

0.95

0.65

0.55

0.50 46812

3 11

57913 14 15

RISING

FALLING

TEMPERATURE (°C)

–50

0.50

RUN THRESHOLDS TO ENABLE VCC (V)

0.55

0.65

0.70

0.75

1.00

0.85

050

3111 G19

0.60

0.90

0.95

0.80

100 150

RISING

FALLING

VIN (V)

RUN THRESHOLD TO ENABLE SWITCHING (V)

1.10

1.05

1.30

1.25

3111 G20

1.20

1.15

1.00 46812

3 11

57913 14 15

RISING

FALLING

TEMPERATURE (°C)

–50

RUN PIN THRESHOLD TO ENABLE SWITCHING (V)

1.10

1.05

1.20

1.30

100

3111 G21

1.15

1.25

1.00 050 150

RISING

FALLING

TEMPERATURE (°C)

–50

ILIMIT, IPEAK AND IREVERSE (A)

150

3111 G22

–2 050 100

–1

PEAK CURRENT LIMIT

INPUT CURRENT LIMIT

REVERSE CURRENT LIMIT

TEMPERATURE (°C)

–50 0 50 100 150

ILMIT, IPEAK, AND IREVERSE (A)

0.6

0.8

1.0

3111 G23

0.4

0.2

0.5

0.7

0.9

0.3

0.1

IZERO

PEAK CURRENT LIMIT

RUN Threshold to Enable/Disable

Switching vs Temperature

LTC3111

3111fa

For more information www.linear.com/LTC3111

TYPICAL PERFORMANCE CHARACTERISTICS

5VIN to 5VOUT Burst to PWM

Response

12VIN to 5VOUT Burst Mode VOUT

Ripple 12VIN to 5VOUT PWM VOUT Ripple

7.5VIN to 5VOUT Start-Up

Response

1.5MHz SYNC Signal Capture and

Release

12VIN to 5VOUT SW1 and SW2

Waveforms

3VIN to 5VOUT 0.05A to 0.25A

Load Response

5VIN to 5VOUT 0.05A to 0.5A

Load Response

12VIN to 5VOUT 0.05A to 0.5A

Load Response

TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified

VOUT

200mV/DIV

INDUCTOR

CURRENT

500mA/DIV

LOAD

CURRENT

200mA/DIV

500µs/DIV

FRONT PAGE APPLICATION

3111 G24

VOUT

200mV/DIV

INDUCTOR

CURRENT

500mA/DIV

LOAD

CURRENT

500mA/DIV

500µs/DIV

FRONT PAGE APPLICATION

3111 G25

VOUT

500mV/DIV

INDUCTOR

CURRENT

1A/DIV

LOAD

CURRENT

500mA/DIV

500µs/DIV

FRONT PAGE APPLICATION

3111 G26

VOUT

200mV/DIV

PWM/SYNC

5V/DIV

INDUCTOR

CURRENT

500mA/DIV 500µs/DIVILOAD = 10mA

L = 4.7µH

COUT = 22µF

3111 G27

VOUT

200mV/DIV

INDUCTOR

CURRENT

500mA/DIV

20µs/DIVILOAD = 50mA

L = 4.7µH

COUT = 22µF

3111 G28

VOUT

50mV/DIV

INDUCTOR

CURRENT

500mA/DIV

1µs/DIVILOAD = 500mA

L = 4.7µH

COUT = 22µF

3111 G29

VOUT

2V/DIV

INDUCTOR

CURRENT

1A/DIV

RUN

5V/DIV

500µs/DIVILOAD = 500mA

L = 4.7µH

COUT = 22µF

3111 G30

INDUCTOR

CURRENT

500mA/DIV

PWM/SYNC

5V/DIV

VOUT

200mV/DIV

100µs/DIV 3111 G31

INDUCTOR

CURRENT

500mA/DIV

SW1

10V/DIV

SW2

5V/DIV

1µs/DIV 3111 G32

LTC3111

3111fa

For more information www.linear.com/LTC3111

TYPICAL PERFORMANCE CHARACTERISTICS

3.3VOUT Die Temperature Rise vs

Continuous Load Current 4-Layer

Demo Board at 25°C

5VOUT Die Temperature Rise vs

Continuous Load Current 4-Layer

Demo Board at 25°C

12VOUT Die Temperature Rise vs

Continuous Load Current 4-Layer

Demo Board at 25°C

SW1, SW2 Minimum Low Time

vs VCC

SW1, SW2 Minimum Low Time

vs Temperature

VOUT Short-Circuit Response and

Recovery

VCC Short-Circuit Response and

Recovery

TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified

INDUCTOR

CURRENT

1A/DIV

VOUT

2V/DIV

1ms/DIV 3111 G33

INDUCTOR

CURRENT

1A/DIV

VCC

5V/DIV

VOUT

2V/DIV

1ms/DIV 3111 G34

SOFT-START

LOAD CURRENT (A)

DIE TEMPERATURE RISE (°C)

1.6

3111 G35

00.4 0.8 1.2

0.2 1.8

0.6 1.0 1.4 2.0

VIN = 2.7V

VIN = 12V

VIN = 5V

LOAD CURRENT (A)

DIE TEMPERATURE (°C)

0.4 0.8 1.2 1.6

3111 G36

2.00.20 0.6 1.0 1.4 1.8

VIN = 2.7V

VIN = 12V

VIN = 5V

LOAD CURRENT (A)

DIE TEMPERATURE RISE (°C)

1.81.6

3111 G37

00.4 0.8 1.2

0.2 2.0

0.6 1.0 1.4

VIN = 2.7V

VIN = 12V

VIN = 5V

VCC (V)

SW1, SW2 MINIMUM LOW TIME (ns)

100

150

200

300

2.5 3 3.5 4

3111 G38

4.5 5

250

ILOAD = 300mA

SW1, VIN = 4V

SW2, VIN = 6V

TEMPERATURE (°C)

–50

SW1, SW2 MINIMUM LOW TIME (ns)

110

130

150

250

190

050

3111 G39

210

230

170

100 150

ILOAD = 300mA

SW1, VIN = 4V

SW2, VIN = 6V

LTC3111

3111fa

For more information www.linear.com/LTC3111

PIN FUNCTIONS

(DFN/MSOP)

COMP (Pin 1/Pin 1): Error Amp Output. An R-C network

connected from this pin to FB sets the loop compensa-

tion for the voltage converter. Refer to the Applications

Information section for component selection details.

FB (Pin 2/Pin 2): Feedback Voltage Input. Connect the

VOUT resistor divider tap to this pin. The output voltage can

be adjusted from 2.5V to 15V by the following equation:

VOUT =0.8V • 1+R1











where R1 is the resistor between VOUT and FB and R2 is

the resistor between FB and GND

SNSGND (Pin 3/Pin 3): This pin must be connected to

ground.

RUN (Pin 4/Pin 4): Input to Enable or Disable the IC and Set

Custom Input Undervoltage Lockout (UVLO) Thresholds.

The RUN pin can be driven by an external logic signal to

enable and disable the IC. In addition, the voltage on this

pin can be set by a resistive voltage divider connected to

the input supply in order to provide accurate turn-on and

turn-off (UVLO) thresholds determined by:

VIN(RUN) =1.2V • 1+











The IC is enabled if RUN exceeds 1.2V nominally. Once

enabled, the UVLO threshold has a built-in hysteresis of

approximately 120mV, turn-off will occur when the voltage

on RUN drops to below 1.08V nominally. To continuously

enable the IC, RUN can be tied directly to the input voltage

up to the absolute maximum rating. This pin should not

be left unconnected.

VIN (Pin 5/Pin 5): Input Supply Voltage. This pin should

be bypassed to the ground plane with at least 10µF of low

ESR, low ESL ceramic capacitance. Place this capacitor as

close to the pin as possible and provide as short a return

path to the ground plane as possible.

SW1 (Pin 6/Pin 6): The external inductor and internal

switches A and B are connected here.

BST1 (Pin 7/Pin 7): Boosted Floating Driver Supply for

A-Switch Driver. Connect a 0.1µF capacitor from this pin

to SW1.

BST2 (Pin 8/Pin 10): Boosted Floating Driver Supply for

D-Switch Driver. Connect a 0.1µF capacitor from this pin

to SW2.

SW2 (Pin 9/Pin 11): The external inductor and internal

switches C and D are connected here.

VOUT (Pin 10/Pin 12): Regulated Output Voltage. This pin

should be connected to a low ESR ceramic capacitor. The

capacitor should be placed as close to the pin as possible

and have a short return to the ground plane.

NC (Pin 11/Pin 13): Not Connected. This pin should be

connected to ground.

VCC (Pin 12/Pin 14): External Capacitor Connection for

the Regulated VCC Supply. This supply is used to operate

internal circuitry and switch drivers. VCC will track VIN up

to 4.2V typical, but will maintain this voltage when VIN >

4.2V. Connect a 1µF ceramic capacitor from this pin to

GND. This pin can be tied to an external supply up to 5.5V.

Refer to the Operation section of this data sheet under

Power VCC from an External Source for more details.

PWM/SYNC (Pin 13/Pin 15): Burst Mode Control and

Synchronization Input. A DC voltage < 0.5V commands

Burst Mode operation independent of load current, >1.5V

commands 800kHz fixed frequency mode. A digital pulse

train between 600kHz and 1.5MHz applied to this pin will

override the internal oscillator and set the operating fre-

quency. The pulse train should have a minimum high time

or low time greater than 100ns (Note6). Note the LTC3111

has reduced power capability when operating in Burst

Mode operation. This pin should not be left unconnected.

SGND (Pin 14/Pin 16): Signal Ground. Terminate the RUN

input voltage divider and output voltage divider to SGND.

PGND (Exposed Pad Pin 15/Pin 8, 9, Exposed Pad Pin17)

Power Ground. The exposed pad must be soldered to

the PCB and electrically connected to ground through

the shortest and lowest impedance connection possible.

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SIMPLIFIED BLOCK DIAGRAM

–

ERROR AMP

PWM/SYNC

COMP

GND

0.8V

VIN

VCC

–1A

VOUT

SOFT-START

RAMP

3111 BD

800k

OSCILLATOR

4.2V

REGULATOR/

CLAMP

REFERENCE

Burst Mode

OPERATION

PLL

–

ILIMIT

IPEAK

IZERO

ADRV BDRV

VCC

CDRV DDRV

LOGIC

REVERSE

ILIM

DRIVERS

–

VCC

START

VIN UVLO

VCC UVLO

RUN

STOP

BST1 BST2

VIN VOUT

SW1 SW2

4.7µH

VCC

0.8V

1.2V

5.8A

0.1A

–

2.1V

START

1.2V

VIN +

–

2.35V

–

BDRV

ADRV

VCC VCC

COUT

VCC

CDRV

DDRV

GND

CIN

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OPERATION

INTRODUCTION

The LTC3111 is an extended input and output range, syn-

chronous 1.5A buck-boost DC/DC converter optimized for

a variety of applications. The LTC3111 utilizes a proprietary

switching algorithm, which allows its output voltage to be

regulated above, below or equal to the input voltage. The

error amplifier output on COMP determines the output duty

cycle of the switches. The low RDS(ON), low gate charge

synchronous switches provide high efficiency pulse width

modulation control. High efficiency is achieved at light

loads when Burst Mode operation is commanded.

LOW NOISE FIXED FREQUENCY OPERATION

Oscillator, Phase Lock Loop

An internal oscillator circuit sets the normal frequency of

operation to 800kHz. A pulse train applied to the PWM/

SYNC pin allows the operating frequency to be programmed

between 600kHz to 1.5MHz via an internal phase-lock-loop

circuit. The pulse train must have a minimum high or low

state of at least 100ns to guarantee operation (see Note6

of the Electrical Characteristics).

Error Amplifier

The LTC3111 contains a high gain operational amplifier

which provides frequency compensation of the control

loop to maintain output voltage regulation. To ensure

loop stability, an external compensation network must be

installed in the application circuit. A Type III compensation

network, as shown in Figure 1, is recommended for most

applications since it provides the flexibility to optimize

the converter’s transient response while simultaneously

minimizing any DC error in the output voltage.

As shown in Figure 1, the error amplifier is followed by

an internal analog divider which adjusts the loop gain by

the reciprocal of the input voltage when the converter is in

buck mode and by the output voltage when the converter

is in boost mode which minimizes loop-gain variation

over changes in the input voltage. This simplifies design

of the compensation network and optimizes the transient

response over the entire range of input voltages. Details

VIN

0.8V

3111 F01

LTC3111

CFB

CFF

RFF

CPOLE

RFB

VOUT

COMP

VOUT

SGND

SW1

SW2

–

PWM

COMPARATORS

Figure 1. Error Amplifier and Compensation Network

on designing the compensation network for the LTC3111

applications can be found in the Applications Information

section of this data sheet.

Current Limit Operation

The buck-boost converter has two current limit circuits.

The input current limit sources current into the feedback

divider network whenever the current in switch A exceeds

3A typical. Due to the high gain of the feedback loop, the

injected current forces the error amplifier output to decrease

until the average current through switch A decreases ap-

proximately to the current limit value. The input current

limit utilizes the error amplifier in an active state and

thereby provides a smooth recovery with little overshoot

once the current limit fault condition is removed. Since

the current limit is based on the average current through

switch A, the peak inductor current in current limit will

have a dependency on the duty cycle (i.e., on the input

and output voltages) in the overcurrent condition. For this

current limit feature to be most effective, the Thevenin

resistance from the FB to ground should exceed 100kΩ.

The speed of the input current limit circuit is limited by the

dynamics of the converter loop. On a hard output short, it

is possible for the inductor current to increase substantially

beyond the input current limit before the input current limit

circuit can react. For this reason, there is a peak current

limit circuit which turns off switch A if the current in switch

A exceeds approximately 190% of the input current limit

value. This provides additional protection in the case of

an instantaneous hard output short.

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OPERATION

Should the output voltage become shorted, the input

current limit is reduced to approximately one half of the

normal operating current limit.

Reverse Current Limit

During fixed frequency operation, a reverse current com-

parator on switch D monitors the current entering the VOUT

pin. When this current exceeds 1A (typical) switch D will

be turned off for the remainder of the switching cycle. This

feature protects the buck-boost converter from excessive

reverse current if the buck-boost output is held above the

regulation voltage.

Internal Soft-Start

The LTC3111 buck-boost converter has an independent

internal soft-start circuit with a nominal duration of 2ms.

The converter remains in regulation during soft-start and

will therefore respond to output load transients which

occur during this time. In addition, the output voltage rise

time has minimal dependency on the size of the output

capacitor or load current during start-up. Soft-start is reset

during a thermal shutdown.

THERMAL CONSIDERATIONS

For the LTC3111 to provide maximum output power, it is

imperative that a good thermal path be provided to dis-

sipate the heat generated within the package. This can be

accomplished by taking advantage of the large thermal

pad on the underside of the IC. It is recommended that

multiple vias in the printed circuit board be used to conduct

the heat away from the IC and into a copper plane with as

much area as possible.

The efficiency and maximum output current capability of

the LTC3111 will be reduced if the converter is required

to continuously deliver large amounts of power or oper-

ate at high temperatures. The amount of output current

derated is dependent upon factors such as board ground

plane or heat sink area, ambient operating temperature

and the input/output voltages of the application. A poor

thermal design can cause excessive heating, resulting in

impaired performance or reliability.

The temperature rise curves given in the Typical Perfor-

mance Characteristics section can be used as a guide to

predict junction temperature rise from ambient. These

curves were generated by mounting the LTC3111 to the

4-layer FR-4 demo printed circuit board layout shown in

Figure 4. The curves were taken at room temperature,

elevated ambient temperature will result in greater ther-

mal rise rates due to increased RDS(ON) of the N-channel

MOSFETs with temperature. The die temperature of the

LTC3111 should be kept below the maximum junction

rating of 125°C for E- and I-grades and 150°C for H- and

MP-grades.

In the event that the junction temperature gets too high

(approximately 170°C), the input current limit will be

linearly decreased from its typical value. If the junction

temperature continues to rise and exceeds approximately

175°C the LTC3111 will be disabled. All power devices

are turned off and all switch nodes put to a high imped-

ance state. The soft-start circuit for the converter is reset

during thermal shutdown to provide a smooth recovery

once the overtemperature condition is eliminated. When

the die temperature drops to approximately 170°C the

LTC3111 will restart.

UNDERVOLTAGE LOCKOUTS

The LTC3111 buck-boost converter is disabled and all

power devices are turned off until the VCC supply reaches

2.35V (typical). The soft-start circuit is reset during under-

voltage lockout to provide a smooth restart once the input

voltage rises above the undervoltage lockout threshold. A

second UVLO circuit disables all power devices if VIN is

below 2.1V rising, 1.9V falling (typical). This can provide

a lower VIN operating range in applications where VCC is

powered from an alternate source or VOUT after start-up.

INDUCTOR DAMPING

When the LTC3111 is disabled (RUN = 0V) or sleeping

during Burst Mode operation (PWM/SYNC = 0V), active

circuits “damp” the inductor voltage through 1kΩ (typical)

impedance between SW1 and SW2 and GND to reduce

ringing and EMI.

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OPERATION

PWM MODE OPERATION

When the PWM/SYNC pin is held high, the LTC3111 buck-

boost converter operates in a fixed-frequency pulse-width

modulation (PWM) mode using voltage mode control. Full

output current is only available in PWM mode. A proprietary

switching algorithm allows the converter to transition

between buck, buck-boost, and boost modes without

discontinuity in inductor current. The switch topology for

the buck-boost converter is shown in Figure 2.

This switching algorithm provides a seamless transition

between operating modes and eliminates discontinuities

in average inductor current, inductor current ripple, and

loop transfer function throughout the operational modes.

These advantages result in increased efficiency and stabil-

ity in comparison to the traditional 4-switch buck-boost

converter.

OUTPUT VOL

TAGE PROGRAMMING

The output voltage is set via the external resistor divider

comprised of resistors R1 and R2 as show in Figures 1.

The resistor divider values determine the output regulation

voltage according to:

VOUT =0.8V • 1+











In addition to setting the output voltage, the value of R1 is

instrumental in controlling the dynamics of the compensa-

tion network. When changing the value of this resistor,

care must be taken to understand the impact this will have

on the compensation network.

In addition, the Thevenin equivalent resistance of the resis-

tor divider controls the gain of the input current limit. To

maintain sufficient gain in this loop, it is recommended

that the Thevenin resistance be greater than 100kΩ.

RUN Comparator

In addition to serving as a logic-level input to enable the IC,

the RUN pin includes an accurate internal comparator that

allows it to be used to set custom rising and falling on/off

thresholds with the addition of an external resistor divider.

When RUN is driven above its logic threshold (0.8V typi-

cal), the LDO regulator is enabled, which provides power

to the internal control circuitry of the IC. If the voltage

on RUN is increased further so that it exceeds the RUN

comparator accurate analog threshold (1.2V typical), all

functions of the buck-boost converter will be enabled and

a start-up sequence will ensue.

If RUN is brought below the accurate comparator threshold,

the buck-boost converter will inhibit switching, but the

VIN VOUT

3111 F02

Figure 2. Buck-Boost Switch Topology

When the input voltage is significantly greater than the

output voltage, the buck-boost converter operates in buck

mode. Switch D turns on at maximum duty cycle and

switchC turns on just long enough to refresh the voltage

on the BST2 capacitor used to drive switch D. Switches A

and B are pulse-width modulated to produce the required

duty cycle to support the output regulation voltage.

As the input voltage nears the output voltage, switchesA

and D are on for a greater portion of the switching pe-

riod, providing a direct current path from VIN to VOUT.

SwitchesB and C are turned on only enough to ensure

proper regulation and/or provide charging of the BST1

and BST2 capacitors. The internal control circuitry will

determine the proper duty cycle in all modes of operation,

which will vary with load current.

As the input voltage drops well below the output voltage,

the converter operates solely in boost mode. Switch A

turns on at maximum duty cycle and switch B turns on

just long enough to refresh the voltage on the BST1 ca-

pacitor used to drive A. Switches C and D are pulse-width

modulated to produce the required duty cycle to regulate

the output voltage.

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OPERATION

LDO regulator and control circuitry will remain powered

unless RUN is brought below its logic threshold. Therefore,

in order to completely shut down the IC, it is necessary

to ensure that RUN is brought below its worst-case low

logic threshold of 0.3V. RUN is a high voltage input and

can be tied directly to VIN to continuously enable the IC

when the input supply is present. The RUN pin can be

driven above VIN or VOUT as long as it stays within the

operating range of 15V.

With the addition of an optional resistor divider as shown

in Figure 3, the RUN pin can be used to establish a user-

programmable turn on and turn off threshold.

Powering VCC from an External Source

The LTC3111’s VCC regulator can be powered or back-fed

from an external source up to 5.5V. The advantage of back

feeding VCC from a voltage above 4.2V is higher efficiency.

For 5VOUT applications, VCC can be easily powered from

VOUT using an external low current Schottky as shown in

several applications circuits in the Typical Applications

section.

Back feeding VCC also improves a light load PWM mode

output voltage ripple that occurs when the inductor passes

through zero current by reducing the switch pin anti-cross

conduction times. A disadvantage of powering VCC from

VOUT is that no-load quiescent current increases at lower

input voltage in Burst Mode operation as shown in the

Typical Performance Characteristics (compared to VCC

powered from VIN).

Burst Mode OPERATION

When the PWM/SYNC pin is held low, the buck-boost

converter operates utilizing a variable frequency switch-

ing algorithm designed to improve efficiency at light load

and reduce the standby current at zero load. In Burst

Mode operation, the inductor is charged with fixed peak

amplitude current pulses and as a result only a fraction

of the maximum output current can be delivered when in

Burst Mode operation.

These current pulses are repeated as often as necessary

to maintain the output regulation voltage. The maximum

output current, IMAX, which can be supplied in Burst Mode

operation is dependent upon the input and output voltage

as approximated by the following formula:

IMAX =IPK

2•η•VIN

VIN +VOUT









A

where IPK is the Burst Mode peak current limit (0.8A typi-

cal) in amps and η is the efficiency.

If the buck-boost load exceeds the maximum Burst Mode

current capability, the output rail will lose regulation. In

Burst Mode operation, the error amplifier is configured for

low power operation and used to hold the compensation

pin, COMP, to reduce transients that may occur during

transitions from and to burst and PWM mode operation.

–

ENABLE SWITCHING

1.2V LTC3111

3111 F03

VIN

RUN

R6 ACCURATE

THRESHOLD

–

ENABLE SWITCHING LDO

AND CONTROL CIRCUITS

0.8V

LOGIC

THRESHOLD

Figure 3. Accurate RUN Comparator

The buck-boost converter is enabled when the voltage

on RUN reaches 1.2V (nominal). Therefore, the turn-on

voltage threshold on VIN is given by:

VIN(RUN) =1.2V • 1+











Once the converter is enabled, the RUN comparator in-

cludes a built-in hysteresis of approximately 120mV, so

that the turn-off threshold will be approximately 10% lower

than the turn-on threshold. Put another way, the internal

threshold level for the RUN comparator looks like 1.08V

after the IC is enabled.

The RUN comparator is relatively noise insensitive, but

there may be cases due to PCB layout, very large value

resistors for R5 and R6 or proximity to noisy components

where noise pickup is unavoidable and may cause the

turn-on or turn-off of the IC to be intermittent. In these

cases, a filter capacitor can be added across R6 to ensure

proper operation.

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APPLICATIONS INFORMATION

The basic LTC3111 application circuit is shown on the front

page of this data sheet. The external component selection

is dependent upon the required performance of the IC in

each particular application given trade-offs such as PCB

area, output voltages, output currents, ripple voltages,

and efficiency. This section of the data sheet provides

some basic guidelines and considerations to aid in the

selection of external components and the design of the

application circuit.

Inductor Selection

To achieve high efficiency, a low ESR inductor should be

utilized for the buck-boost converter. In addition, the buck-

boost inductor must have a saturation current rating that

is greater than the worst-case average inductor current

plus half the ripple current. The peak-to-peak inductor

current ripple for buck or boost mode operation can be

calculated from the following formulas:

∆IL(P-P_BUCK) =VOUT

L•VIN – VOUT

VIN









•1

f– tLOW











∆IL(P-P_BOOST) =VIN

L•VOUT – VIN

VOUT









•1

f– tLOW











where f is the frequency in Hz and L is the inductance in

Henries and tLOW is the switch pin minimum low time in

seconds, which is typically 160ns.

In addition to affecting output current ripple, the inductor

value can also impact the stability of the feedback loop. In

boost mode, the converter transfer function has a right-

half-plane zero at a frequency that is inversely proportional

to the value of the inductor. As a result, a large inductance

can move this zero to a frequency that is low enough to

degrade the phase margin of the feedback loop. It is rec-

ommended that the inductor value be chosen less than

15μH if the converter is to be used in the boost region.

For 800kHz operation, a 4.7μH inductor is recommended

for 5VOUT and 10μH for 12VOUT.

The inductor DC resistance can impact the efficiency of

the buck-boost converter as well as the maximum output

current capability at low input voltage. In buck mode,

the output current is limited only by the inductor current

reaching the current limit value. However, in boost mode,

especially at large step-up ratios, the output current capa-

bility can also be limited by the total resistive losses in the

power stage. These include switch resistances, inductor

resistance, and PCB trace resistance. Use of an inductor

with high DC resistance can degrade the output current

capability from that shown in the graph in the Typical

Performance Characteristics section of this data sheet.

Different inductor core materials and styles have an impact

on the size and price of an inductor at any given current

rating. Shielded construction is generally preferred as it

minimizes the chances of interference with other circuitry.

The choice of inductor style depends upon the price,

sizing, and EMI requirements of a particular application.

Table 1 provides a small sampling of inductors that are

well suited to many LTC3111 buck-boost converter ap-

plications. Within each family (i.e., at a fixed size), the DC

resistance generally increases and the maximum current

generally decreases with increased inductance.

Table 1. Representative Buck-Boost Surface Mount Inductors

PART NUMBER

VALUE

(μH)

DCR

(mΩ)

MAX DC

CURRENT

(A)

SIZE (mm)

W × L × H

Coilcraft

LPS6225

LPS6235

4.7

6.8

3.2

2.8

6.2 × 6.2 × 2.5

6.2 × 6.2 × 3.5

Cooper-Bussmann

FP3-8R2-R

CD1-150-R

8.2

3.4

3.6

7.3 × 6.7 × 3.0

10.5 × 10.4 × 4.0

Sumida

CDRH8D28/HP

CDRH8D28NP

4.7

24.7

3.0

3.4

8.3 × 8.3 × 3.0

TOKO

B1047AS-6R8N

B1179BS-150M

6.8

2.9

2.7

7.6 × 7.6 × 5.0

12.0 × 12.0 × 6.0

Würth

7447789004

744311470

4.7

19.5

2.9

7.3 × 7.3 × 3.2

6.9 × 6.9 × 3.8

Output Capacitor Selection

A low ESR output capacitor should be utilized at the

buck-boost converter output in order to minimize output

voltage ripple. Multilayer X5R and X7R dielectric ceramic

capacitors are an excellent choice as they have low ESR and

are available in small footprints. The capacitor should be

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APPLICATIONS INFORMATION

chosen large enough to reduce the output voltage ripple to

acceptable levels. The minimum output capacitor needed

for a given output voltage ripple (neglecting the capacitor

ESR and ESL) can be calculated by the following formulas:

∆VP-P BUCK

( )

LOAD

• t

LOW

COUT

∆VP-P BOOST

( )

=ILOAD

f •COUT

•VOUT – VIN +tLOW • f • VIN

VOUT











where f is the frequency in Hz, COUT is the output capaci-

tance in μF, ILOAD is the output current in amps and tLOW

is the switch pin minimum low time in seconds, which is

typically 160ns.

In addition to output ripple generated across the output

capacitor, there is also output ripple produced across

the internal resistance of the output capacitor. The ESR-

generated output voltage ripple is proportional to the

series resistance of the output capacitor and is given by

the following expression:

∆VP-P BUCK

( )

LOAD

•R

ESR

1– tLOW • f ≅ILOAD •RESR

∆VP-P BOOST

( )

=ILOAD •RESR • VOUT

VIN 1– tLOW • f

( )

≅ILOAD •RESR • VOUT

VIN

where RESR is the series resistor of the output capacitor

and all other terms are as previously defined.

Input Capacitor Selection

It is recommended that a low ESR ceramic capacitor with

a value of at least 10μF be located as close to the VIN pin

as possible. In addition, the return trace from the pin to

the ground plane should be made as short as possible.

It is important to minimize any stray resistance from the

converter to the battery or power source. If cabling is

required to connect the LTC3111 to the battery or power

supply, a higher ESR capacitor or a series resistor with a

low ESR capacitor in parallel with the low ESR capacitor

may be required to damp out ringing caused by the cable

inductance.

Capacitor Vendor Information

Both the input bypass capacitors and output capacitors

used with the LTC3111 must be low ESR and designed

to handle the large AC currents generated by switching

converters. This is important to maintain proper functioning

of the IC and to reduce input/output ripple. Many modern

low voltage ceramic capacitors experience significant

loss in capacitance from their rated value with increased

DC bias voltages. For example, it is not uncommon for a

small surface mount ceramic capacitor to lose more than

50% of its rated capacitance when operated near its rated

voltage. As a result, it is sometimes necessary to use a

larger value capacitance or a capacitor with a larger case

size than required in order to actually realize the intended

capacitance at the full operating voltage. For details, con-

sult the capacitor vendor’s curve of capacitance versus

DC bias voltage.

The capacitors listed in Table 2 provide a sampling of small

surface mount ceramic capacitors that are well suited to

LTC3111 application circuits. All listed capacitors are either

X5R or X7R dielectric in order to ensure that capacitance

loss over temperature is minimized.

Table 2. Representative Bypass and Output Capacitors

PART NUMBER

VALUE

(μF)

VOLTAGE

(V)

SIZE (mm) L × W × H

(FOOTPRINT)

AVX

12103D226MAT2A

3.2 × 2.5 × 2.79

X5R Ceramic

Kemet

C220X226K3RACTU

A700D226M016ATE030

5.7 × 5.0 × 2.4

X7R Ceramic

7.3 × 4.3 × 2.8

Al Poly, 25mΩ

Murata

GRM32ER71E226KE15L

3.2 × 2.5 × 2.5

X7R Ceramic

Panasonic

ECJ-4YB1E226M

3.2 × 2.5 × 2.5

X5R Ceramic

Sanyo

25SVPF47M

6.6 × 6.6 × 5.9

OS-CON, 30mΩ

Vishay

94SVPD476X0035F12

10.3 × 10.3 × 12.6

OS-CON, 30mΩ

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APPLICATIONS INFORMATION

PCB Layout Considerations

The LTC3111 switches large currents at high frequencies.

Special attention should be paid to the PCB layout to en-

sure a stable, noise-free and efficient application circuit.

Figure 4 presents a representative PCB layout to outline

some of the primary considerations. A few key guidelines

are outlined below:

1. All circulating high current paths should be kept as short

as possible. This can be accomplished by keeping the

routes to all circled components in the figure below

as short and as wide as possible. Capacitor ground

connections should via down to the ground plane in

the shortest route possible. The bypass capacitors on

VIN should be placed as close to the IC as possible and

should have the shortest possible paths to ground.

2. The exposed pad is the power ground connection for

the LTC3111. Multiple vias should connect the back

pad directly to the ground plane. In addition maximi-

zation of the metallization connected to the back pad

will improve the thermal environment and improve the

power handling capabilities of the IC.

3. The circled components and their connections should

all be placed over a complete ground plane to minimize

loop cross-sectional areas. This minimizes EMI and

reduces inductive drops.

4. Connections to all of the circled components should be

made as wide as possible to reduce the series resistance.

This will improve efficiency and maximize the output

current capability of the buck-boost converter.

THERMAL AND

PGND VIAS

Figure 4a. Top and Fabrication Layer of Example PCB Figure 4b. Bottom and Fabrication Layer of Example PCB

COUT

CBST1 CBST2

CIN

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5. To prevent large circulating currents from disrupting

the output voltage sensing, the ground for each resistor

divider should be returned to the ground plane using

a via placed close to the IC and away from the power

connections.

6. Keep the connection from the resistor dividers to the

feedback pins (FB pin) as short as possible and away

from the switch pin connections.

7. Crossover connections should be made on inner copper

layers if available. If it is necessary to place these on

the ground plane, make the trace on the ground plane

as short as possible to minimize the disruption to the

ground plane.

Buck Mode Small-Signal Model

The LTC3111 uses a voltage mode control loop to maintain

regulation of the output voltage. An externally compen-

sated error amplifier drives the COMP pin to generate the

appropriate duty cycle of the power switches. Use of an

external compensation network provides the flexibility for

optimization of closed-loop performance over the wide

variety of output voltages, switching frequencies, and

external component values supported by the LTC3111.

The small-signal transfer function of the buck-boost con-

verter is different in the buck and boost modes of operation

and care must be taken to ensure stability in both operating

regions. When stepping down from a higher input voltage

to a lower output voltage, the converter will operate in

buck mode and the small-signal transfer function from

the error amplifier output COMP, to the converter output

voltage is given by the following equation:

VCOMP BUCK =GBUCK

2 • π• fZ

1+s

2 • π• fO•Q +s

2 • π• fO











The gain term, GBUCK, is comprised of three different

components: the gain of the analog divider, the gain of the

pulse-width modulator, and the gain of the power stage as

given by the following expressions where VIN is the input

voltage to the converter, f is the switching frequency, R

is the load resistance, and tLOW is the switch pin mini-

mum low time, which is typically 160ns. The parameter

RS represents the average series resistance of the power

stage and can be approximated as twice the average power

switch resistance plus the DC resistance of the inductor.

BUCK

DIVIDER

•G

PWM

•G

POWER

GDIVIDER =18

VIN

GPWM =2.5• 1– tLOW • f

( )

GPOWER =VIN •R

1– tLOW • f

( )

• R+RS

( )

Notice that the gain of the analog divider cancels the input

voltage dependence of the power stage. As a result, the

buck mode gain is approximated by a constant as given

by the following equation:

GBUCK =45 •

R+RS

≅45 =33dB

The buck mode transfer function has a single zero which

is generated by the ESR of the output capacitor. The zero

frequency, fZ, is given by the following expression where

RC and CO are the ESR and value of the output filter ca-

pacitor respectively.

fZ=

2• π•R

•C

In most applications, an output capacitor with a very low

ESR is utilized in order to reduce the output voltage ripple

to acceptable levels. Such low values of capacitor ESR

result in a very high frequency zero and as a result the zero

is commonly too high in frequency to significantly impact

compensation of the feedback loop. The denominator of

the buck mode transfer function exhibits a pair of resonant

poles generated by the LC filtering of the power stage. The

resonant frequency of the power stage, fO, is given by the

following expression where L is the value of the inductor:

fO=1

2• π•R+RS

L •COR+RC

( )

≅1

2• π• L •CO

APPLICATIONS INFORMATION

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The quality factor, Q, has a significant impact on compen-

sation of the voltage loop since a higher Q factor produces

a sharper loss of phase near the resonant frequency. The

quality factor is inversely related to the amount of damping

in the power stage and is substantially influenced by the

average series resistance of the power stage, RS. Lower

values of RS will increase the Q and result in a sharper

loss of phase near the resonant frequency and will require

more phase boost or lower bandwidth to maintain an

adequate phase margin.

Q=L •COR+RC

( )

• R+RS

( )

R•RC•CO+L+CO•RS• R+RC

( )

≅L •CO

+CO•RS

Boost Mode Small-Signal Model

When stepping up from a lower input voltage to a higher

output voltage, the buck-boost converter will operate in

boost mode where the small-signal transfer function from

control voltage, VCOMP, to the output voltage is given by

the following expression:

VCOMP BOOST =GBOOST

1+s

2 • π• fZ









• 1– s

2 • π• fRHPZ











1+s

2 • π• fO•Q +s

2 • π• fO











In boost mode operation, the transfer function is character-

ized by a pair of resonant poles and a zero generated by the

ESR of the output capacitor as in buck mode. However, in

addition there is a right-half-plane zero which generates

increasing gain and decreasing phase at higher frequen-

cies. As a result, the crossover frequency in boost mode

operation generally must be set lower than in buck mode

in order to maintain sufficient phase margin.

The boost mode gain, GBOOST, is comprised of three

components: the analog divider, the pulse width modula-

tor and the power stage. The gain of the PWM remains

the same as in buck mode operation, but the gain of the

analog divider and power stage in boost mode are given

by the following equation:

GDIVIDER =

VOUT

GPOWER =VOUT2

1– tLOW • f

( )

• VIN

By combining the individual terms, the total gain in boost

mode can be reduced to the following expression. Notice

that unlike in buck mode, the gain in boost mode is a

function of both the input and output voltage:

GBOOST =45•

OUT

In boost mode operation, the frequency of the right-half-

plane zero, fRHPZ, is given by the following expression.

The frequency of the right-half-plane zero decreases at

higher loads and with larger inductors:

fRHPZ −R• 1– tLOW • f

( )

2• VIN

2 • π•L • VOUT2

In boost mode, the resonant frequency of the power stage

has a dependence on the input and outputvoltage as shown

by the following equation:

fO=1

2 • π•

RS+R• VIN2

VOUT2

L •CO• R+RC

( )

≅1

2 • π•VIN

VOUT

•1

L •CO

Finally, the magnitude of the quality factor of the power

stage in boost mode operation is given by the following

expression:

L •CO•R• RS+R • VIN2

VOUT2











L+C

•R

APPLICATIONS INFORMATION

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3111fa

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APPLICATIONS INFORMATION

Compensation Of The Voltage Loop

The small-signal models of the LTC3111 reveal that the

transfer function from the error amplifier output, COMP,

to the output voltage is characterized by a set of resonant

poles and a possible zero generated by the ESR of the

output capacitor as shown in the Bode plot of Figure 5.

In boost mode operation, there is an additional right-half-

plane zero that produces phase lag and increasing gain at

higher frequencies. Typically, the compensation network

is designed to ensure that the loop crossover frequency is

low enough that the phase loss from the right-half-plane

zero is minimized. The low frequency gain in buck mode

is a constant, but varies with both VIN and VOUT in boost

mode.

For charging or other applications that do not require an

optimized output voltage transient response, a simple

TypeI compensation network as shown in Figure 6 can

be used to stabilize the voltage loop. To ensure sufficient

phase margin, the gain of the error amplifier must be low

enough that the resultant crossover frequency of the control

loop is well below the resonant frequency.

In most applications, the low bandwidth of the Type I com-

pensated loop will not provide sufficient transient response

performance. To obtain a wider bandwidth feedback loop,

optimize the transient response, and minimize the size of

the output capacitor, a Type III compensation network as

shown in Figure 7 is required.

A Bode plot of the typical Type III compensation network

is shown in Figure 8. The Type III compensation network

provides a pole near the origin which produces a very high

loop gain at DC to minimize any steady-state error in the

regulation voltage. Tw o zeros located at fZERO1 and fZERO2

provide sufficient phase boost to allow the loop crossover

frequency to be set above the resonant frequency, fO, of

the power stage. The Type III compensation network also

introduces a second and third pole. The second pole, at

frequency fPOLE2, reduces the error amplifier gain to a

zero slope to prevent the loop crossover from extending

0.8V

3111 F06

LTC3111

VOUT

COMP

SGND

–

Figure 6: Error Amplifier with Type I Compensation

0.8V

3111 F07

LTC3111

CFB

CFF

RFF

CPOLE

RFB

VOUT

COMP

SGND

–

Figure 7: Error Amplifier with Type III Compensation

Figure 5: Buck-Boost Converter Bode Plot

GAIN

PHASE

BOOST MODE

BUCK MODE

–20dB/DEC

–40dB/DEC

fO3111 F05

fRHPZ

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APPLICATIONS INFORMATION

too high in frequency. The third pole at frequency fPOLE3

provides attenuation of high frequency switching noise.

The transfer function of the compensated Type III error

amplifier from the input of the resistor divider to the output

of the error amplifier, COMP, is:

VCOMP

=GCOMP •

1+s

2 • π• fZERO1









• 1+s

2 • π• fZERO2











s• 1+s

2 • π• fPOLE2









• 1+s

2 • π• fPOLE3











The compensation gain is given by the following equation.

The simpler approximate value is sufficiently accurate in

most cases since CFB is typically much larger in value

than CPOLE.

GCOMP ≅

R1• CFB +CPOLE

( )

≅

R1•CFB

The pole and zero frequencies of the Type III compensation

network can be calculated from the following equations

where all frequencies are in Hz, resistances are in ohms,

and capacitances are in farads.

fZERO1=

2 • π•RFB •CFB

fZERO2 =1

2 • πR1+RFF

( )

•CFF

≅1

2 • π•R1•CFF

fPOLE2 =1

2 • π•CFB •CPOLE

CFB +CPOLE

•RFB

≅1

2 • π•RFB •CPOLE

fPOLE3 =1

2 • π•R

•C

In most applications the compensation network is designed

so that the loop crossover frequency is above the resonant

frequency of the power stage, but sufficiently below the

boost mode right-half-plane zero to minimize the additional

phase loss. Once the crossover frequency is decided upon,

the phase boost provided by the compensation network

is centered at that point in order to maximize the phase

margin. A larger separation in frequency between the

zeros and higher order poles will provide a higher peak

phase boost but may also increase the gain of the error

amplifier which can push out the loop crossover to a

higher frequency.

The Q of the power stage can have a significant influence

on the design of the compensation network because it

determines how rapidly the 180° of phase loss in the power

stage occurs. For very low values of series resistance, RS,

the Q will be higher and the phase loss will occur sharply.

In such cases, the phase of the power stage will fall rapidly

to –180° above the resonant frequency and the total phase

margin must be provided by the compensation network.

fZERO1

PHASE

GAIN

–20dB/DEC

fZERO2

3111 F08

fPOLE2 fPOLE3

Figure 8: Type III Compensation Bode Plot

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APPLICATIONS INFORMATION

However, with higher losses in the power stage (larger

RS) the Q factor will be lower and the phase loss will occur

more gradually. As a result, the power stage phase will

not be as close to –180° at the crossover frequency and

less phase boost is required of the compensation network.

The LTC3111 error amplifier is designed to have a fixed

maximum bandwidth in order to provide rejection of

switching noise to prevent it from interfering with the

control loop. From a frequency domain perspective, this

can be viewed as an additional single pole as illustrated

in Figure 9. The nominal frequency of this pole is 400kHz.

For typical loop crossover frequencies below about 60kHz

the phase contributed by this additional pole is negligible.

However, for loops with higher crossover frequencies this

additional phase loss should be taken into account when

designing the compensation network.

the worst-case inductor current ripple to less than 1A peak

to peak. A low ESR output capacitor with a value of 22µF

is specified to yield a worst-case output voltage ripple

(occurring at the worst-case step-up ratio and maximum

load current) of approximately 20mV. In summary, the

key power stage specifications for this LTC3111 example

application are given below.

f = 0.8MHz, tLOW = 160ns

VIN = 3.5V to 15V

VOUT = 5V at R = 10Ω

COUT = 22µF, RC = 10mΩ

L = 4.7µH, RL = 25mΩ

RS = 200mΩ

With the power stage parameters specified, the compen-

sation network can be designed. In most applications,

the most challenging compensation corner is boost

mode operation at the greatest step-up ratio and highest

load current since this generates the lowest frequency

right-half-plane zero and results in the greatest phase

loss. Therefore, a reasonable approach is to design the

compensation network at this worst-case corner and then

verify that sufficient phase margin exists across all other

operating conditions. In this example application, at VIN =

3.5V and the full 500mA load current, the right-half-plane

zero will be located at 136kHz and this will be a dominant

factor in determining the bandwidth of the control loop.

The first step in designing the compensation network is

to determine the target crossover frequency for the com-

pensated loop. A reasonable starting point is to assume

that the compensation network will generate a peak phase

boost of approximately 60°. Therefore, in order to obtain

a phase margin of 60°, the loop crossover frequency, fC,

should be selected as the frequency at which the phase

0.8V RFILT

CFILT

3111 F09

LTC3111

COMP

–

Figure 9. Internal Loop Filter

Loop Compensation Example

This section provides an example illustrating the design of

a compensation network for a typical LTC3111 application

circuit. In this example a 5V regulated output voltage is

generated with the ability to supply a 500mA load from an

input power source ranging from 3.5V to 15V. To reduce

switching losses a 800kHz switching frequency has been

chosen for this example. In this application the maximum

inductor current ripple will occur at the highest input volt-

age. An inductor value of 4.7µH has been chosen to limit

LTC3111

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Figure 10. Converter Bode Plot VIN = 3.5V, VOUT = 5V, R = 10Ω

(Hz)

–20

(dB)

(DEG)

–10

10 1k 10k 1M

3111 F10

–30

100 100k

0 –90

–40

–180

–135

–45

GAIN

PHASE

–255

–270

fC = 40kHz

APPLICATIONS INFORMATION

of the buck-boost converter reaches –180°. As a result, at

the loop crossover frequency the total phase will be simply

the 60° of phase provided by the error amplifier as shown:

Phase Margin = ϕBUCK-BOOST + ϕERRORAMPLIFIER + 180°

= –180° + 60° + 180° = 60°

Similarly, if a phase margin of 45° is required, the target

crossover frequency should be picked as the frequency

at which the buck-boost converter phase reaches –195°

so that the combined phase at the crossover frequency

yields the desired 45° of phase margin.

This example will be designed for a 60° phase margin to

ensure adequate performance over parametric variations

and varying operating conditions. As a result, the target

crossover frequency, fC, will be the point at which the

phase of the buck-boost converter reaches –180°. It is

generally difficult to determine this frequency analytically

given that it is significantly impacted by the Q factor of

the resonance in the power stage. As a result, it is best

determined from a Bode plot of the buck-boost converter

as shown in Figure 10. This Bode plot is for the LTC3111

buck-boost converter using the previously specified power

stage parameters and was generated from the small-signal

model equations using LTspice

software. In this case,

the phase reaches –180° at 40kHz making fC = 40kHz the

target crossover frequency for the compensated loop.

From the Bode plot of Figure 10 the gain of the power stage

at the target crossover frequency is 13.5dB. Therefore, in

order to make this frequency the crossover frequency in

the compensated loop, the total loop gain at fC must be

adjusted to 0dB. To achieve this, the gain of the compen-

sation network must be designed to be –13.5dB at the

crossover frequency.

At this point in the design process, there are three con-

straints that have been established for the compensation

network. It must have –13.5dB of gain at fC = 40kHz, a peak

phase boost of 60° that is centered at fC = 40kHz. One way

to design a compensation network to meet these targets

is to simulate the compensation error amplifier Bode plot

in LTspice for the typical compensation network shown

on the front page of this data sheet. Then, the gain, pole

and zero frequencies can be iteratively adjusted until the

required constraints are met. Alternatively, an analytical

approach can be used to design a compensation network

with the desired phase boost, center frequency and gain.

In general, this procedure can be cumbersome due to the

large number of degrees of freedom in the Type III com-

pensation network. However the design process can be

simplified by assuming that both the compensation zeros

occur at the same frequency, fZ, and both higher order

poles (fPOLE2 and fPOLE3) occur at the common frequency,

fP. In most cases this is a reasonable assumption since

the zeros are typically located between 1kHz and 10kHz

and the poles are typically located near each other at much

higher frequencies. Given this assumption, the maximum

phase boost, provided by the compensation error amplifier

is determined simply by the amount of separation between

the poles and zeros as shown by the following equation:

φMAX =4 • arctan fP









– 270°

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APPLICATIONS INFORMATION

A reasonable choice is to pick the frequency of the poles,

fP, to be 50 times higher than the frequency of the zeros,

fZ, which provides a peak phase boost of approximately

60° as was assumed previously. Next, the phase boost

must be centered so that the peak phase occurs at the

target crossover frequency. The frequency of the maximum

phase boost, fCENTER, is the geometric mean of the pole

and zero frequency as:

fCENTER =fP• fZ=50 • fZ≅7 • fZ

Therefore, in order to center the phase boost given a factor

of 50 separation between the pole and zero frequencies,

the zero should be located at one-seventh of the crossover

frequency and the poles should be located at seventh times

the crossover frequency as given by the following equation:

fZ=

40kHz

7=5.71kHz

=7 • f

=7 • 40kHz =280kHz

This placement of the poles and zeros will yield a peak phase

boost of 60° that is centered at the crossover frequency,

fC. Next, in order to produce the desired target crossover

frequency, the gain of the compensation network at the

point of maximum phase boost, GCENTER, must be set to

–13.5dB. The gain of the compensated error amplifier at

the point of the phase gain is given by:

GCENTER =10 •log 2 • π• fP

2• π• fZ

( )

3• R1•CFB

( )













dB

Assuming a multiple of 50 separation between the pole

and zero frequencies this can be simplified to the follow-

ing expression:

GCENTER =20 •log 50

2• π• fC•R1•CFB









dB

This equation completes the set of constraints needed to

determine the compensation component values. Specifi-

cally, the two zeros, fZERO1 and fZERO2, should be located

near 5.71kHz. The two poles, fPOLE2 and fPOLE3, should be

located near 280kHz and the gain should be set to provide

a gain at the crossover frequency of GCENTER = –13.5dB.

The first step in defining the compensation component

values is to pick a value for R1 that provides an acceptably

low quiescent current through the resistor divider. A value

of R1 = 1MΩ is a reasonable choice. Next, the value of CFB

can be found in order to set the error amplifier gain at the

crossover frequency to –13.5dB as follows:

GCENTER =–13.5dB =20 •log 50

2 • π• 40kHz •1MΩ•CFB











CFB =50

2 • π• 40kHz •1MΩ•10

–13.5

≅1000pF

The compensation poles can be set at 280kHz and the

zeros at 5.71kHz by using the expressions for the pole and

zero frequencies given in the previous sections. Setting

the frequency of the first zero, fZERO1, to 5.71kHz results

in the following value for RFB:

RFB =

2• π•5.71kHz•1000pF ≅28.0kΩ

This leaves the free parameter, CPOLE, to set frequency

fPOLE1 to the common pole frequency of 280kHz as given:

CPOLE =

2• π•280kHz •28kΩ

≅22pF

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Figure 11: Compensation Error Amplifier Bode Plot

Figure 12: Complete Loop Bode Plot

(Hz)

–20

(dB)

(DEG)

–10

10 1k 10k 1M

3111 F11

–30

100 100k

0 0

–40

–45

–90

40kHz, 57°

40kHz, –14dB

GAIN

PHASE

(Hz)

0 –90

(dB)

(DEG)

100 1k 10k 100k 1M

3111 F12

–10

–20

–30

–40

–45

–135

–180

–225

–270

135

180

40kHz, 59°

GAIN

PHASE

APPLICATIONS INFORMATION

Next, CFF can be chosen to set the second zero, fZERO2, to

the common zero frequency of 5.71kHz.

CFF =

2• π•5.71kHz•1MΩ

≅27pF

Finally, the resistor value RFF can be chosen to place the

second pole at 280kHz.

RFF =

2• π•280kHz •27pF ≅20kΩ

Now that the pole frequencies, zero frequencies and gain

of the compensation network have been established, the

next step is to generate a Bode plot for the compensated

error amplifier to confirm its gain and phase properties.

A Bode plot of the error amplifier with the designed com-

pensation component values is shown in Figure 11. The

Bode plot confirms that the peak phase occurs at 40kHz

and the phase boost at that point is 57°. In addition, the

gain at the peak phase frequency is –14dB which is close

to the design target.

The final step in the design process is to compute the

Bode plot for the entire designed compensation network

and confirm its phase margin and crossover frequency.

The complete loop Bode plot for this example is shown

in Figure 12. The loop crossover frequency is 40kHz and

the phase margin is approximately 59°.

The Bode plot for the complete loop should be checked over

all operating conditions and for variations in component

values to ensure that sufficient phase margin exist in all

cases. The stability of the loop should also be confirmed

via time domain simulation and by the transient response

of the converter in the actual circuit.

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TYPICAL APPLICATIONS

1, 2, 3 Li-Ion to 5V

Wide VIN to 5VOUT Efficiency

SW1 0.1µF

27pF

1µF

33pF

191k

154k

3111 TA02a

20k

680pF 26.1k

0.1µF

VIN

3V TO 12.6V

4.7µH

SW2

BST1 BST2

VIN

LTC3111

PGND

VOUT

22µF

VOUT

750mA

VIN > 4V

10µF

1 TO 3-CELL

Li-Ion

PWM/SYNC

BURST PWM

RUN FB

VCC

SNSGND

SGND

COMP

NUMBER

OF CELLS

274k

698k

1.13M

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.0001 0.001 0.1 1 10

3111 TA02b

0.01

40 VIN = 3.6V

VIN = 7.2V

VIN = 10.8V

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TYPICAL APPLICATIONS

LTC3111 Synchronized to a 1.5MHz Clock, 5V/1A Output

3.3V Backup from a High Voltage Capacitor Bank Runs Down to VIN = 2V with 500mA Load

SW1 0.1µF

15pF MBR0520L

OPTIONAL

191k

3111 TA03a

270pF 57.6k

0.1µF

VIN

2.5V TO 15V

2.2µH

SW2

BST1 BST2

VIN

LTC3111

SGND PGND

VOUT

1.5MHz CLOCK

22µF

1µF

VOUT

VIN > 5V

10µF

PWM/SYNC

RUN FB

VCC

SNSGND

COMP

OFF ON

SW1 0.1µF

33pF 36pF MBR0520L

OPTIONAL

316k

3111 TA04a

20k

1600pF24.3k

0.1µF

2V TO 15V

4.7µH

SW2

BST1 BST2

LTC3111

OUT

33µF

1µF

OUT

3.3V

500mA

100µF

214mF

PWM/SYNC

RUN FB

SNSGND

COMP

SGND PGND

VIN

5V/DIV

VOUT

2V/DIV

IOUT

500mA/DIV

2 SEC/DIV 3111 TA04b

POWER SUPPLY REMOVED

PWM/SYNC

5V/DIV

SW1

10V/DIV

INDUCTOR

CURRENT

1A/DIV

SW2

5V/DIV

500ns/DIV 3111 TA03b

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TYPICAL APPLICATIONS

Stepped Response from 1 or 2 Li-Ion to 12V Adapter Source VOUT = 5V

SW1 0.1µF

27pF

1µF

33pF

191k

3111 TA05a

20k

680pF 26.1k

0.1µF

12V

ADAPTER

4.7µH

SW2

BST1 BST2

VIN

LTC3111

VOUT

VCC

1- OR 2-SERIES

Li-Ion CELLS

22µF

VOUT

1.5A

VIN > 5V

47µF

PWM/SYNC

RUN FB

SNSGND

COMP

OFF ON

B520C

BURST PWM

LT ®4352

IDEAL

DIODE

SGND PGND

VIN

2V/DIV

TWO Li-Ion CELLS

VOUT

500mV/DIV

INDUCTOR

CURRENT

1A/DIV

1ms/DIVIOUT = 500mA 3111 TA05b

Custom Input Undervoltage Lockout Thresholds

SW1 0.1µF

27pF

1µF

33pF

191k

316k

3111 TA08a

20k

680pF 26.1k

0.1µF

VIN

5V TO 15V

ENABLED WHEN

VIN REACHED 5V

DISABLED WHEN VIN

FALLS BELOW 4.5V

4.7µH

SW2

BST1 BST2

VIN

LTC3111

VOUT

VCC

22µF

VOUT

1.5A

10µF

PWM/SYNC

RUN FB

SNSGND

COMP

SGND PGND

VIN

10V/DIV

VOUT

5V/DIV

INDUCTOR

CURRENT

1A/DIV

2ms/DIVRLOAD = 3.3Ω 3111 TA08b

VIN

10V/DIV

VOUT

5V/DIV

INDUCTOR

CURRENT

1A/DIV

2ms/DIVRLOAD = 3.3Ω 3111 TA08c

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PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

3.00 ±0.10

(2 SIDES)

4.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.70 ±0.10

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

3.00 REF

1.70 ±0.05

148

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DE14) DFN 0806 REV B

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

3.00 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 ±0.05

0.70 ±0.05

3.60 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

3.30 ±0.05

3.30 ±0.10

0.50 BSC

DE Package

14-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1708 Rev B)

LTC3111

3111fa

For more information www.linear.com/LTC3111

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MSE16) 0213 REV F

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL

NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ±0.102

(.112 ±.004)

2.845 ±0.102

(.112 ±.004)

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

1.651 ±0.102

(.065 ±.004)

1.651 ±0.102

(.065 ±.004)

0.1016 ±0.0508

(.004 ±.002)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.280 ±0.076

(.011 ±.003)

REF

4.90 ±0.152

(.193 ±.006)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.12 REF

0.35

REF

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev F)

LTC3111

3111fa

For more information www.linear.com/LTC3111

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 1/14 Clarified graphs 1, 4, 5, 6

LTC3111

3111fa

For more information www.linear.com/LTC3111

 LINEAR TECHNOLOGY CORPORATION 2013

LT 0114 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3111

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TYPICAL APPLICATION

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Converter

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LTC3115-1/

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Converter

VIN: 2.7V to 40V, VOUT = 2.7V to 40V, IQ = 30μA, ISD < 1μA, DFN and TSSOP

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Packages

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Converter with Output Disconnect

VIN:1.8V to 5.5V, VOUT: 2.2V to 15V. IQ = 25µA, ISD < 1µA, DFN and MSOP

Packages

Regulated 12V Output from Wide Range Input Supply Wide VIN to 12VOUT Efficiency

SW1 0.1µF

39pF

1µF

18pF

2.21M

158k

3111 TA06a

20k

1000pF44.2k

0.1µF

VIN

2.5V TO 15V

10µH

SW2

BST1 BST2

VIN

LTC3111

VOUT

VCC

22µF

VOUT

12V

0.5A, VIN > 5V

1.0A, VIN > 9V

10µF

PWM/SYNC

BURST PWM

RUN FB

SNSGND

COMP

OFF ON

SGND PGND

LOAD CURRENT (A)

0.0001

EFFICIENCY (%)

100

0.001 0.01 0.1 1 10

3111 TA06b

VIN = 5V

VIN = 12V

BURST

PWM