General Description
The MAX17014 multiple-output power-supply controller
generates all the supply rails for thin-film transistor
(TFT) liquid-crystal display (LCD) panels in TVs and
monitors operating from a regulated 12V input. It
includes a step-down and a step-up regulator, a posi-
tive and a negative charge pump, two operational
amplifiers, and a Dual Mode™ logic-controlled high-
voltage switch control block. The MAX17014 can oper-
ate from 8V to 16.5V input voltages and is optimized for
LCD TV panel and LCD monitor applications running
directly from 12V supplies.
The step-up and step-down regulators feature internal
power MOSFETs and high-frequency operation allow-
ing the use of small inductors and capacitors, resulting
in a compact solution. Both switching regulators use
fixed-frequency current-mode control architectures,
providing fast load-transient response and easy com-
pensation. A current-limit function for internal switches
and output-fault shutdown protect the step-up and
step-down power supplies against fault conditions. The
MAX17014 provides soft-start functions to limit inrush
current during startup. The MAX17014 provides
adjustable power-up timing.
The positive and negative charge-pump regulators pro-
vide TFT gate driver supply voltages. Both output volt-
ages can be adjusted with external resistive
voltage-dividers. The switch control block allows the
manipulation of the positive TFT gate driver voltage.
The MAX17014 includes two high-current operational
amplifiers designed to drive the LCD backplane
(VCOM). The amplifier features high output current
(±150mA), fast slew rate (100V/µs), wide bandwidth
(20MHz), and rail-to-rail inputs and outputs. A series
p-channel MOSFET is integrated to sequence power to
AVDD after the MAX17014 has proceeded through
normal startup, and provides True Shutdown™.
The MAX17014 is available in a small (7mm x 7mm),
low-profile (0.8mm), 48-pin thin QFN package and
operates over a -40°C to +85°C temperature range.
Applications
LCD TV Panels
LCD Monitor Panels
Features
oOptimized for 10.8V to 13.2V Input Supply
o8V to 16.5V Input Supply Range
oSelectable Frequency (600kHz/1.2MHz)
oCurrent-Mode Step-Up Regulator
Built-In 20V, 3.3A, 110mΩn-Channel MOSFET
High-Accuracy Output Voltage (1%)
True Shutdown
Fast Load-Transient Response
High Efficiency
3ms Internal Soft-Start
oCurrent-Mode Step-Down Regulator
Built-In 20V, 2.5A, 120mΩn-Channel MOSFET
Fast Load-Transient Response
Adjustable Output Voltage Down to 1.25V
Skip Mode at Light Load
High Efficiency
3ms Internal Soft-Start
oAdjustable Positive and Negative Charge-Pump
Regulators
oSoft-Start and Timer-Delay Fault Latch for All
Outputs
oLogic-Controlled High-Voltage Integrated
Switches with Adjustable Delay
oTwo High-Speed Operational Amplifiers
±150mA Short-Circuit Current
100V/µs Slew Rate
20MHz, -3dB Bandwidth
o120mΩp-Channel FET for AVDD Sequencing
oInput Undervoltage Lockout and Thermal-
Overload Protection
o48-Pin, 7mm x 7mm Thin QFN Package
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-1045; Rev 0; 10/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free package.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX17014ETM+
-40°C to +85°C
48 Thin QFN
7mm x 7mm
T4877+3
Dual Mode is a trademark of Maxim Integrated Products, Inc.
True Shutdown is a trademark of Maxim Integrated Products, Inc.
Simplified Operating Circuit and Pin Configuration appear
at end of data sheet.
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VIN, IN2, OVIN, SUP, EN1, EN2, FSEL to GND ......-0.3V to +22V
GND1, OGND, CPGND to GND .........................................±0.3V
MODE, DLP, CTL, THR, DEL1, DEL2, VL to GND ...-0.3V to +7.5V
REF, FBP, FBN, FB1, FB2, COMP,
OUT to GND ...........................................-0.3V to (VVL + 0.3V)
SWI, SWO to GND ..................................................-0.3V to +22V
LX1 to GND1 ..........................................................-0.3V to +22V
SWI to SWO ............................................................-0.3V to +22V
SWI to SUI .............................................................-0.3V to +7.5V
POS1, NEG1, OUT1, POS2, NEG2,
OUT2 to OGND...................................-0.3V to (VOVIN + 0.3V)
DRVN, DRVP to CPGND ...........................-0.3V to (VSUP + 0.3V)
LX2 to CPGND ...........................................-0.3V to (VIN2 + 0.3V)
BST to VL................................................................-0.3V to +22V
SRC to GND ...........................................................-0.3V to +48V
GON, DRN to GND ...................................-0.3V to (VSRC + 0.3V)
GON to DRN...........................................................-0.3V to +48V
POS_ to NEG_ RMS Current ...................................5mA (Note 1)
REF Short Circuit to GND ...........................................Continuous
RMS LX1 Current (total for both pins) ...................................3.2A
RMS GND1 Current (total for both pins) ...............................3.2A
RMS IN2 Current (total for both pins)....................................3.2A
RMS LX2 Current (total for both pins) ...................................3.2A
RMS CPGND Current............................................................0.8A
RMS SWI Current ..................................................................2.4A
RMS SWO Current ................................................................2.4A
RMS DRVN, DRVP Current ...................................................0.8A
RMS VL Current ..................................................................50mA
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN
(derate 38.5mW/°C above +70°C) .........................3076.9mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+160°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
VIN, IN2 Input Voltage Range 8.0 16.5 V
VIN + IN2 Quiescent Current Only LX2 switching (VFB1 = VFBP = 1.5V, VFBN = 0);
EN1 = EN2 = VL, VFSEL= 0 8 mA
VIN + IN2 Standby Current LX2 not switching (VFB1 = VFB2 = VFBP = 1.5V,
VFBN = 0); EN1 = EN2 = VL, VFSEL= 0 2 mA
VIN + IN2 Shutdown Current EN1 = EN2 = GND (shutdown) 300 μA
SUP + OVIN Shutdown Current EN1 = EN2 = GND (shutdown) 10 μA
FSEL = VIN 1020 1200 1380
SMPS Operating Frequency FSEL = GND 510 600 690 kHz
Phase Difference Between Step-
Down/Positive and Step-Up/Negative
Regulators
180 Degrees
VIN Undervoltage Lockout Threshold VIN rising edge, 100mV typical hysteresis 5.75 6.50 7.25 V
VL REGULATOR
VL Output Voltage IVL = 25mA, VFB1 = VFB2 = VFBP = 1.1V, VFBN =
0.4V (all regulators switching) 4.9 5.0 5.1 V
VL Undervoltage Lockout Threshold VL rising edge, 100mV typical hysteresis 3.5 3.9 4.3 V
Note 1: See Figure 6 for the op amp clamp structures.
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCE
REF Output Voltage No external load 1.235 1.250 1.265 V
REF Load Regulation 0 < ILOAD < 50μA 10 mV
REF Sink Current In regulation 10 μA
REF Undervoltage Lockout Threshold Rising edge; 20mV typical hysteresis 1.0 1.2 V
STEP-DOWN REGULATOR
0°C < TA< +85°C 3.25 3.30 3.35
OUT Voltage in Fixed Mode FB2 = GND, no load
(Note 2) TA = +25°C 3.267 3.333 V
0°C < TA< +85°C 1.23 1.25 1.27
FB2 Voltage in Adjustable Mode VOUT = 2.5V, no load
(Note 2) TA = +25°C 1.2375 1.2625 V
FB2 Adjustable-Mode Threshold
Voltage Dual-mode comparator 0.10 0.15 0.20 V
Output Voltage Adjust Range Step-down output 1.5 5.0 V
FB2 Fault Trip Level Falling edge 0.96 1.00 1.04 V
FB2 Input Leakage Current VFB2 = 1.5V 50 125 200 nA
DC Load Regulation 0A < ILOAD < 2A 0.5 %
DC Line Regulation No load, 10.8V < VIN2 < 13.2V 0.1 %/V
LX2-to-IN2 nMOS Switch
On-Resistance 120 240 m
LX2-to-CPGND nMOS Switch
On-Resistance 6 10 23
BST-to-VL PMOS Switch
On-Resistance 7 12 20
Low-Frequency Operation
OUT Threshold Step-down only 0.8 V
FSEL = VIN 217
Low-Frequency Operation
Switching Frequency FSEL = GND 108 kHz
LX2 Positive Current Limit 2.50 3 3.50 A
Soft-Start Period 3 ms
Soft-Start Step Size VREF /
128 V
Maximum Duty Factor 70 80 90 %
STEP-UP REGULATOR
Output Voltage Range VVIN 20 V
Oscillator Maximum Duty Cycle 69 75 81 %
Minimum tON 70 ns
0°C < TA< +85°C 1.235 1.25 1.265
FB1 Regulation Voltage FB1 = COMP,
CCOMP = 1nF TA = +25°C 1.2375 1.2625 V
FB1 Fault Trip Level Falling edge 0.96 1.00 1.04 V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise
noted.)
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FB1 Load Regulation 0 < ILOAD < full, transient only -1 %
FB1 Line Regulation 10.8V < VVIN < 13.2V 0.08 0.15 %/V
FB1 Input Bias Current VFB1 = 1.25V 25 125 200 nA
FB1 Transconductance I = ±2.5μA at COMP, FB1 = COMP 150 320 560 μS
FB1 Voltage Gain FB1 to COMP 1400 V/V
LX1 Leakage Current VFB1 = 1.5V, VLX1 = 20V 4 40 μA
LX1 Current Limit VFB1 = 1.1V, duty cycle = 25% 3.2 3.7 4.2 A
Current-Sense Transresistance 0.16 0.23 0.30 V/A
LX1 On-Resistance 110 220 m
Soft-Start Period 3 ms
Soft-Start Step Size ILIM /
128 A
POSITIVE AND NEGATIVE CHARGE-PUMP REGULATORS
SUP Input Supply Range 8.0 18.0 V
SUP Input Supply Current VFBP = 1.5V, VFBN = 0.15V (not switching) 0.2 0.4 mA
SUP Overvoltage Threshold SUP rising edge, 250mV typical hysteresis (Note 3) 18 19 20 V
0°C < TA< +85°C 1.23 1.25 1.27
FBP Regulation Voltage TA= +25°C 1.2375 1.2625 V
FBP Line-Regulation Error 11V < VSUP < 16V, not in dropout 0.2 %/V
FBP Input Bias Current VFBP = 1.5V -50 +50 nA
DRVP p-Channel MOSFET
On-Resistance 1.0 3.0
DRVP n-Channel MOSFET
On-Resistance 0.5 1.0
FBP Fault Trip Level Falling edge 0.96 1.00 1.04 V
Positive Charge-Pump Soft-Start Period 3 ms
Positive Charge-Pump Soft-Start
Step Size
VREF /
128 V
0°C < TA< +85°C 0.988 1.000 1.012
FBN Regulation Voltage VREF - VFBN TA = +25°C 0.99 1.00 1.01 V
FBN Input Bias Current VFBN = 0mV -50 +50 nA
FBN Line Regulation Error 11V < VSUP < 16V, not in dropout 0.2 %/V
DRVN p-Channel On-Resistance 1.0 3.0
DRVN n-Channel On-Resistance 0.5 1.0
FBN Fault Trip Level Rising edge 450 500 550 mV
Negative Charge-Pump Soft-Start 3 ms
Negative Charge-Pump Soft-Start
Step Size
(VREF -
VFBN) /
128
V
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless other-
wise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
AVDD SWITCH
SWI Supply Range 8.0 18.5 V
SWI Overvoltage Fault Threshold SWI rising edge, 250mV typical hysteresis (Note 3) 18.50 19.25 20.00 V
SWI-SWO Switch Resistance 120 240 m
SUI-SWI Pullup Resistance EN2 = GND 30
SUI Output Sink Current EN2 = DEL2 = VL 24 30 36 μA
SWI-SUI Done Threshold EN2 = DEL2 = VL 4.4 5.0 5.6 V
OPERATIONAL AMPLIFIERS
OVIN Supply Range 8 18 V
OVIN Overvoltage Fault Threshold OVIN rising edge, 250mV typical hysteresis (Note 3) 18 19 20 V
OVIN Supply Current Buffer configuration, VPOSx = VOVIN / 2, no load 4.2 6 mA
Input Offset Voltage 2V < (VNEGx, VPOSx) < (VOVIN - 2V), TA = +25°C -10 +10 mV
Input Bias Current 2V < (VNEGx, VPOSx) < (VOVIN - 2V) -1 +1 μA
Input Common-Mode Voltage Range 0 VOVIN V
Input Common-Mode Rejection 2V < (VNEGx, VPOSx) < (VOVIN - 2V) 100 dB
Output Voltage Swing High IOUTx = 25mA VOVIN -
300
VOVIN -
150 mV
Output Voltage Swing Low IOUTx = -25mA 150 300 mV
Large-Signal Voltage Gain 2V < (VNEGx, VPOSx)< (V
OVIN - 2V) 80 dB
Slew Rate 2V < (VNEGx, VPOSx) < (VOVIN - 2V) 100 V/μs
-3dB Bandwidth 2V < (VNEGx, VPOSx) < (VOVIN - 2V) 20 MHz
Short to VOVIN / 2, sourcing 150
Short-Circuit Current Short to VOVIN / 2, sinking 250 mA
HIGH-VOLTAGE SWITCH ARRAY
SRC Supply Range 44 V
SRC Supply Current 200 500 μA
GON-to-SRC Switch On-Resistance VDLP = 2V, CTL = VL 10 20
GON-to-SRC Switch Saturation Current (VSRC - VGON) > 5V 150 390 mA
GON-to-DRN Switch On-Resistance VDLP = 2V, CTL = GND 20 50
GON-to-DRN Switch Saturation Current (VGON - VDRN) > 5V 75 180 mA
GON-to-GND Switch On-Resistance DLP = GND, VGON = 5V 2.5 6.0 12.5 k
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 1.6 V
CTL Input Current CTL = GND or VL -1 +1 μA
CTL-to-GON Rising Propagation Delay 1k from DRN to GND, CTL = GND to VL step, no load
on GON, measured from VCTL = 2V to GON = 20% 100 ns
CTL-to-GON Falling Propagation Delay 1k from DRN to GND, CTL = VL to GND step, no load
on GON, measured from VCTL = 0.6V to GON = 80% 100 ns
MODE Switch On-Resistance 1250
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise
noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Mode 1 Voltage Threshold VMODE rising edge 4.5 V
MODE Capacitor Charge Current
(Mode 2) VMODE < MODE current-source stop voltage threshold 40 50 60 μA
MODE Voltage Threshold for
Enabling DRN Switch Control
in Mode 2
GON connects to DRN 1.20 1.25 1.30 V
MODE Current-Source Stop
Voltage Threshold MODE rising edge 2 3 V
THR-to-GON Voltage Gain 9.4 10.0 10.6 V/V
SEQUENCE CONTROL
EN1, EN2, Input Low Voltage 0.6 V
EN1, EN2 Input High Voltage 1.6 V
EN1, EN2 Pulldown Resistance 1 M
DEL1, DEL2, DLP Charge Current VDEL1 = VDEL2 = VDLP = 1V 6 8 10 μA
DEL1, DEL2, DLP Turn-On Threshold 1.19 1.25 1.31 kV
DEL1, DEL2, DLP Discharge
Switch On-Resistance EN1 = GND or fault tripped 10
FBN Discharge Switch On-Resistance EN2 = GND or fault tripped 3 k
FAULT DETECTION
Duration to Trigger Fault 50 ms
Duration to Restart After Fault 160 ms
Number of Restart Attempts
Before Shutdown 3 Times
Thermal-Shutdown Threshold 15°C typical hysteresis +160 °C
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 600kHz 0.6 V
FSEL Input High Voltage 1.2MHz 1.6 V
FSEL Pulldown Resistance 1 M
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless oth-
erwise noted.) (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
VIN, IN2 Input Voltage Range 8.0 16.5 V
FSEL = VIN 1020 1380
SMPS Operating Frequency FSEL = GND 510 690 kHz
VIN Undervoltage Lockout Threshold VIN rising edge, 100mV typical hysteresis 5.75 7.25 V
VL REGULATOR
VL Output Voltage IVL = 25mA, VFB1 = VFB2 = VFBP = 1.1V,
VFBN = 0.4V (all regulators switching) 4.9 5.1 V
VL Undervoltage Lockout Threshold VL rising edge, 100mV typical hysteresis 3.5 4.3 V
REFERENCE
REF Output Voltage No external load 1.235 1.265 V
REF Load Regulation 0 < ILOAD < 50μA 10 mV
REF Undervoltage Lockout Threshold Rising edge; 20mV typical hysteresis 1.2 V
STEP-DOWN REGULATOR
OUT Voltage in Fixed Mode FB2 = GND, no load (Note 2) 3.25 3.35 V
FB2 Voltage in Adjustable Mode VOUT = 2.5V, no load (Note 2) 1.23 1.27 V
FB2 Adjustable-Mode
Threshold Voltage Dual-mode comparator 0.10 0.20 V
Output Voltage Adjust Range Step-down output 1.5 5.0 V
LX2-to-IN2 nMOS Switch
On-Resistance 240 m
LX2-to-CPGND nMOS Switch
On-Resistance 6 23
BST-to-VL pMOS Switch
On-Resistance 7 20
LX2 Positive Current Limit 2.50 3.50 A
Maximum Duty Factor 70 90 %
STEP-UP REGULATOR
Output Voltage Range VVIN 20 V
Oscillator Maximum Duty Cycle 69 81 %
FB1 Regulation Voltage FB1 = COMP, CCOMP = 1nF 1.23 1.27 V
LX1 Current Limit VFB1 = 1.1V, duty cycle = 25% 3.2 4.2 A
Current-Sense Transresistance 0.16 0.30 V/A
LX1 On-Resistance 220 m
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless oth-
erwise noted.) (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
POSITIVE AND NEGATIVE CHARGE-PUMP REGULATORS
VSUP Input Supply Range 8 18 V
VSUP Overvoltage Threshold SUP rising edge, 250mV typical hysteresis (Note 3) 18 20 V
FBP Regulation Voltage 1.23 1.27 V
DRVP p-Channel MOSFET
On-Resistance 3
DRVP n-Channel MOSFET
On-Resistance 1
FBN Regulation Voltage VREF - VFBN 0.985 1.015 V
DRVN p-Channel On-Resistance 3
DRVN n-Channel On-Resistance 1
AVDD SWITCH
SWI Supply Range 8.0 18.5 V
SWI Overvoltage Fault Threshold VOVIN = rising, 250mV typical hysteresis (Note 3) 18.5 20.0 V
SWI-SWO Switch Resistance 240 m
SUI Output Sink Current EN2 = DEL2 = VL 24 36 μA
SWI-SUI Done Threshold EN2 = DEL2 = VL 4.4 5.6 V
OPERATIONAL AMPLIFIERS
OVIN Supply Range 8 18 V
OVIN Overvoltage Fault Threshold SWI rising edge, 250mV typical hysteresis (Note 2) 18 20 V
Input Common-Mode Voltage Range 0 VOVIN V
Output Voltage Swing High IOUTx = 25mA VOVIN -
300 mV
Output Voltage Swing Low IOUTx = -25mA 300 mV
HIGH-VOLTAGE SWITCH ARRAY
SRC Supply Range 44 V
GON-to-SRC Switch On-Resistance VDLP = 2V, CTL = VL 20
GON-to-DRN Switch On-Resistance VDLP = 2V, CTL = GND 50
GON-to-GND Switch On-Resistance DLP = GND, VGON = 5V 2.5 12.5 k
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 1.6 V
Mode 1 Voltage Threshold VMODE rising edge 4.5 V
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
_______________________________________________________________________________________ 9
Note 2: When the inductor is in continuous conduction (EN2 = VL or heavy load), the output voltage has a DC regulation level lower than
the error comparator threshold by 50% of the output voltage ripple. In discontinuous conduction (EN2 = GND with light load), the
output voltage has a DC regulation level higher than the error comparator threshold by 50% of the output voltage ripple.
Note 3: Disables boost switching if either SUP, SWI, or OVIN exceeds the threshold. Switching resumes when no threshold is exceeded.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = IN2 = 12V, AVDD = OVIN = SUP = 15V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless oth-
erwise noted.) (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MODE Voltage Threshold for Enabling
DRN Switch Control in Mode 2 GON connects to DRN 1.2 1.3 V
MODE Current-Source Stop Voltage
Threshold MODE rising edge 2 3 V
THR-to-GON Voltage Gain 9.4 10.6 V/V
SEQUENCE CONTROL
EN1, EN2 Input Low Voltage 0.6 V
EN1, EN2 Input High Voltage 1.6 V
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 600kHz 0.6 V
FSEL Input High Voltage 1.2MHz 1.6 V
Typical Operating Characteristics
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA= +25°C, unless other-
wise noted.)
STEP-DOWN REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17014 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
55
60
65
70
75
80
85
50
0.01 10
EN1 = VL, EN2 = GND
EN1 = VL, EN2 = VL
STEP-DOWN REGULATOR
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17014 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
1.60 2.001.200.800.40
3.225
3.250
3.275
3.300
3.325
3.350
3.200
0 2.40
EN1 = VL, EN2 = GND
EN1 = VL, EN2 = VL
STEP-DOWN REGULATOR
LOAD TRANSIENT RESPONSE
MAX17014 toc03
10µs/div
A: VOUT, 100mV/div
B: LOAD CURRENT, 2A/div
C: INDUCTOR CURRENT, 1A/div
A
B
C
0A
3.3V
2A
0.1A
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA= +25°C, unless other-
wise noted.)
STEP-DOWN REGULATOR
SOFT-START (HEAVY LOAD)
MAX17014 toc04
4.00ms/div
A: VIN, 5V/div
B: VOUT, 1V/div
C: INDUCTOR CURRENT,
500mA/div
D: VLX2, 10V/div
A
B
C
D
0V
0A
0V
0V
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17014 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
50
60
70
80
90
45
55
65
75
85
100
95
40
0.001 10
STEP-UP REGULATOR
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17014 toc06
LOAD CURRENT (A)
AVDD (V)
2.01.0 1.50.5
16.02
16.04
16.06
16.08
16.10
16.00
02.5
STEP-UP REGULATOR
SOFT-START (HEAVY LOAD)
MAX17014 toc07
10.00ms/div
A: EN2, 5V/div
B: DEL2, 5V/div
C: AVDD, 5V/div
D: VSUI, 5V/div
E: INDUCTOR CURRENT,
1.00A/div
A
B
C
D
E
STEP-UP REGULATOR
LOAD-TRANSIENT RESPONSE
MAX17014 toc08
20.0µs/div
A: LOAD CURRENT,
1A/div
B: AVDD, 200mV/div
C: INDUCTOR CURRENT,
2A/div
A
50mA
B
16V
C
0A
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE
MAX17014 toc09
10.0µs/div
A: LOAD CURRENT,
1A/div
B: AVDD, 200mV/div
C: INDUCTOR CURRENT,
2A/div
A
0.2A
B
16V
C
0A
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________
11
STEP-UP REGULATOR CURRENT LIMIT
vs. INPUT VOLTAGE
MAX17014 toc10
INPUT VOLTAGE (V)
STEP-UP CURRENT LIMIT (A)
151410 11 12 139
3.0
4.0
3.5
4.5
5.0
5.5
6.0
2.5
816
AVDD = 16V
AVDD = 18V
L1 = 4.7µH
(CDEP134NP-4R8M, ISAT = 9.3A)
TIME-DELAY LATCH
RESPONSE TO OVERLOAD
MAX17014 toc11
200ms/div
A: VOUT, 5V/div
B: VAVDD, 10V/div
C: VGON, 50V/div
D: VGOFF, 5V/div
E: L1 INDUCTOR CURRENT,
5A/div
A
B
C
D
E
0V
0V
0V
0V
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
MAX17014 toc12
VIN (V)
SWITCHING FREQUENCY (MHz)
1310 11 129
1.192
1.194
1.196
1.198
1.200
1.190
814
VL LOAD REGULATION
MAX17014 toc13
LOAD CURRENT (mA)
VL (V)
8020 40 60
4.96
4.99
5.00
4.98
4.97
5.01
5.02
5.03
5.04
5.05
4.95
0100
EN1 = EN2 = VL
EN1 = EN2 = GND
REFERENCE VOLTAGE
LOAD REGULATION
MAX17014 toc14
LOAD CURRENT (
µ
A)
REFERENCE VOLTAGE (V)
15050 100
1.248
1.247
1.246
1.249
1.250
1.251
1.245
0200
EN1 = EN2 = VL
EN1 = EN2 = GND
POSITIVE CHARGE-PUMP REGULATOR
NORMALIZED LINE REGULATION
MAX17014 toc15
VIN (V)
VSRC (%)
1612 14
-0.04
-0.07
-0.01
0.02
0.05
-0.10
10 181511 13 17
ISRC = 0A
ISRC = 25mA
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA= +25°C, unless other-
wise noted.)
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA= +25°C, unless other-
wise noted.)
POSITIVE CHARGE-PUMP REGULATOR
NORMALIZED LOAD REGULATION
MAX17014 toc16
LOAD CURRENT (mA)
OUTPUT VOLTAGE ERROR (%)
75
-0.8
-1.2
-1.6
-0.4
0
0.4
-2.0
015010025 50 125
POSITIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE
MAX17014 toc17
40.0µs/div
A: VSRC, 100mV/div
B: LOAD CURRENT, 20mA/div
A
70mA
10mA
34.8V
B
NEGATIVE CHARGE-PUMP REGULATOR
NORMALIZED LINE REGULATION
MAX17014 toc18
VIN (V)
OUTPUT VOLTAGE ERROR (%)
1511 13
-0.35
-0.55
-0.15
0.05
0.25
-0.75
9161410 12
NEGATIVE CHARGE-PUMP REGULATOR
NORMALIZED LOAD REGULATION
MAX17014 toc19
LOAD CURRENT (mA)
OUTPUT VOLTAGE ERROR (%)
100 200
-0.4
-0.6
-0.8
-1.0
-0.2
0
0.2
-1.2
025050 150
NEGATIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE
MAX17014 toc20
20.0µs/div
A: VGOFF, 100mV/div
B: LOAD CURRENT, 65mA/div
A
110mA
10mA
-6V
B
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 13
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA= +25°C, unless other-
wise noted.)
OPERATIONAL AMPLIFIER RAIL-TO-RAIL
INPUT/OUTPUT
MAX17014 toc22
4.0µs/div
A: INPUT SIGNAL, 5V/div
B: OUTPUT SIGNAL, 5V/div
A
0V
0V
B
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX17014 toc23
200ns/div
A: OUTPUT CURRENT, 50mA/div
B: OUTPUT VOLTAGE, 500mV/div
A
50mA
0mA
-50mA
8V
B
OPERATIONAL AMPLIFIER
LARGE-SIGNAL RESPONSE
MAX17014 toc24
400ns/div
A: INPUT SIGNAL, 5V/div
B: OUTPUT SIGNAL, 5V/div
A
0V
0V
B
OPERATIONAL AMPLIFIER
SMALL-SIGNAL RESPONSE
MAX17014 toc25
100ns/div
A: INPUT SIGNAL, 200mV/div
B: OUTPUT SIGNAL, 200mV/div
A
0V
0V
B
VIN SUPPLY CURRENT vs. VIN VOLTAGE
MAX17014 toc26
VIN VOLTAGE (V)
VIN SUPPLY CURRENT (mA)
10 12 13 14 15
3
2
1
4
5
6
0
816911
EN1 = EN2 = VL
EN1 = EN2 = GND
INL SUPPLY CURRENT vs. TEMPERATURE
MAX17014 toc27
TEMPERATURE (°C)
INL SUPPLY CURRENT (mA)
-15 35 60
1.5
1.0
0.5
2.0
3.0
2.5
3.5
0
-40 8510
EN1 = VL, EN2 = GND
EN1 = EN2 = GND
HIGH-VOLTAGE SWITCH
CONTROL FUNCTION (MODE 1)
MAX17014 toc28
4.00µs/div
A: VCTL, 5V/div
B: VMODE, 5V/div
C: VGON, 10V/div
A
B
0V
0V
0V
C
CGON = 2.2nF
HIGH-VOLTAGE SWITCH
CONTROL FUNCTION (MODE 2)
MAX17014 toc29
4.00µs/div
A: VCTL, 5V/div
B: VMODE, 2V/div
C: VGON, 10V/div
A
B
0V
0V
0V
C
CGON = 2.2nF
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 POS1 Operational Amplifier 1 Noninverting Input
2 OUT1 Operational Amplifier 1 Output
3 THR
GON Low-Level Regulation Set-Point Input. Connect THR to the center of a resistive voltage-divider
between AVDD and GND to set the VGON falling regulation level. The regulation level is 10 x VTHR.
See the High-Voltage Switch Control section for details.
4 MODE
High-Voltage Switch-Control Block Mode Selection Input and Timing-Adjustment Input. See the
High-Voltage Switch Control section for details. MODE is high impedance when it is connected to
VL. MODE is internally pulled to GND by a 10 resistor for 0.1μs typical when the high-voltage
switch-control block is enabled.
5 CTL
High-Voltage Switch-Control Block Timing Control Input. See the High-Voltage Switch Control
section for details.
6 DLP GON Output Enable. See the High-Voltage Switch Control section for details.
7 DRN Switch Input. Drain of the internal high-voltage p-channel MOSFET between DRN and GON.
8 GON
Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the high-voltage
switch-control block.
9 SRC Switch Input. Source of the internal high-voltage p-channel MOSFET between SRC and GON.
10 FBP
Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-
divider between the positive charge-pump regulator output and GND to set the positive charge-
pump regulator output voltage. Place the resistive voltage-divider within 5mm to FBP.
11 CPGND Charge Pump and Step-Down Regulator Power Ground
12 DRVP Positive Charge-Pump Driver Output. Connect DRVP to the positive charge-pump flying capacitor(s).
13 SUP
Supply Input for the Charge-Pump Drivers. Connect this pin to the output of the boost regulator SWI
and bypass to CPGND with a 0.1μF capacitor.
14 DRVN Negative Charge-Pump Driver Output. Connect DRVN to the negative charge-pump flying capacitor(s).
15, 34 GND Analog Ground
16 FBN
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive
voltage-divider between the negative output and REF to set the negative charge-pump regulator
output voltage. Place the resistive voltage-divider within 5mm of FBN.
17 REF
Reference Output. Connect a 0.22μF capacitor from REF to GND. All power outputs are disabled
until REF exceeds its UVLO threshold. REF is active whenever VIN is above VIN UVLO threshold.
18 DEL1
Negative Charge-Pump Delay Input. Connect a capacitor from DEL1 and GND to set the delay time
between the step-down output and the negative output. An 8μA current source charges CDEL1.
DEL1 is internally pulled to GND through 10 resistance when EN1 is low or VL is below its UVLO.
19 N.C. No Connection. Not internally connected.
20 OUT Step-Down Regulator Output-Voltage Sense. Connect OUT to the step-down regulator output.
21 FB2
Step-Down Regulator Feedback Input. Connect FB2 to GND to select the step-down converter’s
3.3V fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider
between the step-down regulator output and GND to set the step-down regulator output voltage.
Place the resistive voltage-divider within 5mm of FB2.
22 BST
Step-Down Regulator Bootstrap Capacitor Connection for High-Side Gate Driver. Connect a 0.1μF
ceramic capacitor from BST to LX2.
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 15
Pin Description (continued)
PIN NAME FUNCTION
23, 24 LX2
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET
connected between IN2 and LX2. Connect the inductor and Schottky catch diode close to both LX2
pins to minimize the trace area for low EMI.
25, 26 IN2 Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between IN2
and LX2.
27 VIN Input of the Internal 5V Linear Regulator and the Startup Circuitry. Bypass VIN to GND with 0.22μF
close to the IC.
28 FSEL
Frequency-Select Pin. Connect FSEL to GND for 600kHz operation. Connect to VL or VIN for 1.2MHz
operation.
29 DEL2
Step-Up Regulator and Positive Charge-Pump Delay Input. Connect a capacitor from DEL2 and
GND to set the delay time between EN2 and the startup of these regulators, or between the step-
down startup and the startup of these regulators if EN1 is high before the step-down starts. An 8μA
current source charges CDEL2. DEL2 is internally pulled to GND through 10 resistance when EN1
or EN2 is low or when VL is below its UVLO threshold.
30 VL
5V Internal Linear Regulator Output. Bypass VL to GND with 1μF minimum. Provides power for the
internal MOSFET driving circuit, the PWM controllers, charge-pump regulators, logic, and reference
and other analog circuitry. Provides 25mA load current when all switching regulators are enabled.
VL is active whenever VIN is above VIN UVLO threshold.
31 COMP
Compensation Pin for the Step-Up Error Amplifier. Connect a series resistor and capacitor from
COMP to ground.
32 EN2
Step-Up and Positive Charge-Pump Regulator Enable Input. Input HIGH also enables DEL2 pullup
current. EN2 is inactive when EN1 is low. See the Power-Up Sequence section for details.
33 EN1
Step-Down and Negative Charge-Pump Regulator Enable Input. Input HIGH also enables DEL1
pullup current.
35, 36 GND1 Step-Up Regulator Power Ground. Source of the internal power n-channel MOSFET.
37, 38 LX1 Step-Up Regulator Power MOSFET n-Channel Drain and Switching Node. Connect the inductor and
Schottky catch diode to both LX1 pins and minimize the trace area for lowest EMI.
39 SWI
Step-Up Regulator Internal p-Channel MOSFET Pass Switch Source Input. Connect to the cathode of
the step-up regulator Schottky catch diode.
40 SUI
Step-Up Regulator Internal p-Channel MOSFET Pass Switch Gate Input. Connect a capacitor from
SUI to SWI to set the delay time. A 30μA current source pulls down on CSUI when DEL2 is high.
41 FB1
Boost Regulator Feedback Input. Connect FB1 to the center of a resistive voltage-divider between
the boost regulator output and GND to set the boost regulator output voltage. Place the resistive
voltage-divider within 5mm of FB1.
42 SWO Step-Up Regulator Internal p-Channel MOSFET Pass Switch Drain Output
43 OVIN Operational Amplifier Power Input
44 NEG2 Operational Amplifier 2 Inverting Input
45 POS2 Operational Amplifier 2 Noninverting Input
46 OUT2 Operational Amplifier Output 2
47 OGND Operational Amplifier Power Ground
48 NEG1 Operational Amplifier 1 Inverting Input
EP GND Exposed Paddle = GND
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
16 ______________________________________________________________________________________
LX2
REF
FB1
LX1 LX1
GND
COMP
VIN
12V
OUT
3.3V
2A
AVDD
16V
1.5A
FSEL
FB2
OUT
STEP-DOWN,
NEGATIVE CHARGE
PUMP ON/OFF
VL
VIN VIN
GON
35V
50mA
OVIN
OGND
VL
REF
BST
GON
DRN
CTL
SWI
GON CONTROL
DRVN
FBN
REF
DRVP
FBP
SUP
CPGND
SRC
GND1 GND1
NEG2
OUT2
VCOM1
L1
4.7μH
C3
10μF
0.1μF
L2
2.6μH
C12
1μF
C13
0.1μF
C6
0.1μF
DEL2
DEL1
EN1
EN2
N.C.
NEG1
OUT1
SWI
SWO
SUI
POS1
C14
0.1μF
THR
POS2
DLP
MODE
C1
10μF
C2
10μF
D1
35 36 37 38
39
40
42
41
31
AVDD
43
47
VCOM2
45
1
3
48
2
44
46
5
R9
1kΩ
7
SWI
8
13
9
SRC
12
C20
0.1μF
C21
0.1μFC22
0.1μF
AVDD
10
11 49
16
14
D3
IN2 IN2
26
25
C4
0.1μF
D2
LX2
22
23
24
20
21
27
30
28
4
17
15
29
18
33
32
6
19
STEP-UP, POSITIVE
CHARGE PUMP ON/OFF
GOFF
-6V
100mA
MAX17014
C7
1μF
C8
0.22μF
C9
0.1μF
C10
0.15μF
C11
0.15μF
C5
22μF
C23
1μF
C18
0.1μF
C17
330pF
R5
82kΩ
R7
13.3kΩ
R6
20kΩ
R8
2.2kΩ
R16
367kΩ
R17
13.3kΩ
R3
158kΩ
R4
13.3kΩ
R1
150kΩ
R2
23kΩ
D4
D5
EP
C19
0.1μF
C16
10μF
C15
10μF
C24
10μF
Figure 1. Typical Operating Circuit
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 17
Typical Operating Circuit
The typical operating circuit (Figure 1) of the
MAX17014 is a complete power-supply system for TFT
LCD panels in monitors and TVs. The circuit generates
a +3.3V logic supply, a +16V source driver supply, a
+34.5V positive gate driver supply, and a -6V negative
gate driver supply from a 12V ±10% input supply.
Table 1 lists some selected components and Table 2
lists the contact information for component suppliers.
Detailed Description
The MAX17014 is a multiple-output power supply
designed primarily for TFT LCD panels used in moni-
tors and TVs. It contains a step-down switching regula-
tor to generate the logic supply rail, a step-up switching
regulator to generate the source driver supply, and two
charge-pump regulators to generate the gate driver
supplies. Each regulator features adjustable output
voltage, digital soft-start, and timer-delayed fault pro-
tection. Both the step-down and step-up regulators use
a fixed-frequency current-mode control architecture.
The two switching regulators are 180° out-of-phase to
minimize the input ripple. The internal oscillator offers
two pin-selectable frequency options (600kHz/1.2MHz),
allowing users to optimize their designs based on the
specific application requirements. The MAX17014
includes two high-performance operational amplifiers
designed to drive the LCD backplane (VCOM). The
amplifiers feature high output current (±150mA), fast
slew rate (100V/µs), wide bandwidth (20MHz), and rail-
to-rail inputs and outputs. In addition, the MAX17014
features a high-voltage switch-control block, an internal
5V linear regulator, a 1.25V reference output, well-
defined power-up and power-down sequences, and
thermal-overload protection. Figure 2 shows the
MAX17014 functional diagram.
Step-Down Regulator
The step-down regulator consists of an internal n-chan-
nel MOSFET with gate driver, a lossless current-sense
network, a current-limit comparator, and a PWM con-
troller block. The external power stage consists of a
Schottky diode rectifier, an inductor, and output capac-
itors. The output voltage is regulated by changing the
duty cycle of the n-channel MOSFET. A bootstrap cir-
cuit that uses a 0.1µF flying capacitor between LX2 and
BST provides the supply voltage for the high-side gate
driver. Although the MAX17014 also includes a 10Ω
(typ) low-side MOSFET, this switch is used to charge
the bootstrap capacitor during startup and maintains
fixed-frequency operation at light load and cannot be
used as a synchronous rectifier. An external Schottky
diode (D2 in Figure 1) is always required.
Table 1. Component List
DESIGNATION DESCRIPTION
C1, C2, C3
10μF ±20%, 16V X5R ceramic capacitors
(1206)
Taiyo Yuden EMK325BJ106MD
TDK C3225X7R1C106M
C5
22μF ±10%, 6.3V X5R ceramic capacitor
(1206)
Taiyo Yuden JMK316BJ226KL
Murata GRM31CR60J226M
C15, C16, C24
10μF ±20%, 25V X5R ceramic capacitors
(1210)
TDK C3225X5R1E106M
D1, D2
3A, 30V Schottky diodes (M-Flat)
Toshiba CMS02 (TE12L,Q)
Central Semiconductor
D3, D4, D5
200mA, 100V dual ultra-fast diodes
(SOT23)
Fairchild MMBD4148SE (top mark D4)
Central Semiconductor CMPD1001S lead
free (top mark L21)
L1
Low-profile 4.7μH, 3.5A inductor
(2mm height)
TOKO FDV0620-4R7M
L2
Low-profile 2.4μH, 2.6A inductor
(1.8mm height)
TOKO 1124BS-2R4M (2.4μH)
Wurth 744052002 (2.5μH)
Table 2. Component Suppliers
SUPPLIER PHONE FAX WEBSITE
Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida 847-545-6700 847-545-6720 www.sumida.com
TDK 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
18 ______________________________________________________________________________________
STEP-DOWN OSC
VL
LX2
CPGND
OUT
FB2
VIN
REF
GND
DEL1
VL VL
VIN
VIN (12V)
3.3V
2A
150mV
STEP-UP
POWER-UP
SEQUENCE HV
SWITCH
BLOCK
NEGATIVE
REG POSITIVE
REG
IN2
LX1
GND1
FB1
COMP
FSEL
SWI
SWO
SUI
OVIN
POS1
NEG1
OUT1
VL
BST
VGOFF
-6V
100mA
REF
VL
AVDD
16V
1.5A
REF
DEL2
DLP
DRVN
FBN FBP
REF
SUP
CPGND
50% OSC
EN1
STEP-DOWN,
NEGATIVE CHARGE
PUMP ON/OFF
EN2
STEP-UP,
POSITIVE CHARGE
PUMP ON/OFF
P
VGON
35V
50mA
POS2
NEG2
OUT2
OGND
DRN
THR
MODE
CTL GON
CONTROL
GON
AVDD
SRC
SUP
DRVP
CPGND
SWI
OP AMPs
Figure 2. Functional Diagram
PWM Controller Block
The heart of the PWM control block is a multi-input,
open-loop comparator that sums three signals: the out-
put voltage signal with respect to the reference voltage,
the current-sense signal, and the slope compensation.
The PWM controller is a direct-summing type, lacking a
traditional error amplifier and the phase shift associated
with it. This direct-summing configuration approaches
ideal cycle-by-cycle control over the output voltage.
When EN1 and EN2 are high, the controller always
operates in fixed-frequency PWM mode. Each pulse
from the oscillator sets the main PWM latch that turns
on the high-side switch until the PWM comparator
changes state.
When EN1 is high and EN2 is low, the controller oper-
ates in skip mode. The skip mode dramatically
improves light-load efficiency by reducing the effective
frequency, which reduces switching losses. It keeps
the peak inductor current at about 0.9A (typ) in an
active cycle, allowing subsequent cycles to be
skipped. Skip mode transitions seamlessly to fixed-
frequency PWM operation as load current increases.
Current Limiting and Lossless Current Sensing
The current-limit circuit turns off the high-side MOSFET
switch whenever the voltage across the high-side
MOSFET exceeds an internal threshold. The actual
current limit is 3A (typ).
For current-mode control, an internal lossless sense
network derives a current-sense signal from the induc-
tor DCR. The time constant of the current-sense net-
work is not required to match the time constant of the
inductor and has been chosen to provide sufficient cur-
rent ramp signal for stable operation at both operating
frequencies. The current-sense signal is AC-coupled
into the PWM comparator, eliminating most DC output-
voltage variation with load current.
Low-Frequency Operation
The step-down regulator of the MAX17014 enters into
low-frequency operating mode if the voltage on OUT is
below 0.8V. In the low-frequency mode, the switching
frequency of the step-down regulator is 1/6 the oscilla-
tor frequency. This feature prevents potentially uncon-
trolled inductor current if OUT is overloaded or shorted
to ground.
Dual-Mode Feedback
The step-down regulator of the MAX17014 supports
both fixed and adjustable output voltages. Connect
FB2 to GND to enable the 3.3V fixed output voltage.
Connect a resistive voltage-divider between OUT and
GND with the center tap connected to FB2 to adjust the
output voltage. Choose RB (resistance from FB2 to
GND) to be between 5kΩand 50kΩ, and solve for RA
(resistance from OUT1 to FB1) using the equation:
where VFB2 = 1.25V, and VOUT can vary from 1.25V to 5V.
Because of FB2’s (pin 21) close proximity to the noisy
BST (pin 22), a noise filter is required for FB2
adjustable-mode operation. Place a 100pF capacitor
from FB2 to GND to prevent unstable operation. No fil-
ter is required for 3.3V fixed-mode operation.
Soft-Start
The step-down regulator includes a 7-bit soft-start DAC
that steps its internal reference voltage from 0 to 1.25V in
128 steps. The soft-start period is 3ms (typ) and FB1 fault
detection is disabled during this period. The soft-start fea-
ture effectively limits the inrush current during startup (see
the Step-Down Regulator Soft-Start (Heavy Load) wave-
forms in the
Typical Operating Characteristics
).
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-
frequency PWM architecture to maximize loop band-
width and provide fast-transient response to pulsed
loads typical of TFT LCD panel source drivers. The inte-
grated MOSFET and the built-in digital soft-start func-
tion reduce the number of external components
required while controlling inrush currents. The output
voltage can be set from VVIN to 20V with an external
resistive voltage-divider. The regulator controls the out-
put voltage and the power delivered to the output by
modulating the duty cycle (D) of the internal power
MOSFET in each switching cycle. The duty cycle of the
MOSFET is approximated by:
where VAVDD is the output voltage of the step-up regulator.
PWM Controller Block
An error amplifier compares the signal at FB1 to 1.25V
and changes the COMP output. The voltage at COMP
sets the peak inductor current. As the load varies, the
error amplifier sources or sinks current to the COMP
output accordingly to produce the inductor peak cur-
rent necessary to service the load. To maintain stability
at high duty cycles, a slope compensation signal is
summed with the current-sense signal.
DVV
V
AVDD VIN
AVDD
≈−
RA RB V
V
OUT
FB
=× −
⎛
⎝
⎜⎞
⎠
⎟
2
1
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 19
MAX17014
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the current-
feedback signal and the slope compensation exceed the
COMP voltage, the controller resets the flip-flop and turns
off the MOSFET. Since the inductor current is continuous,
a transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the inductor
then becomes the difference between the output voltage
and the input voltage. This discharge condition forces
the current through the inductor to ramp back down,
transferring the energy stored in the magnetic field to the
output capacitor and the load. The MOSFET remains off
for the rest of the clock cycle.
Step-Up Regulator Internal
p-Channel MOSFET Pass Switch
The MAX17014 includes an integrated 120mΩhigh-
voltage p-channel MOSFET to allow true shutdown of
the step-up converter output (AVDD). This switch is typi-
cally connected in series between the step-up regula-
tor’s Schottky catch diode and its output capacitors. In
addition to allowing step-up output to discharge com-
pletely when disabled, this switch also controls the
startup inrush current into the step-up regulator’s out-
put capacitors.
When EN2 is low, SUI is internally pulled up to SWI
through an internal 1kΩresistor. Once EN2 is high and
the step-down regulator is in regulation, the MAX17014
starts pulling down SUI with a 30µA internal current
source. The internal p-channel MOSFET turns on and
connects the cathode of the step-up regulator Schottky
catch diode to the step-up regulator load capacitors,
when VSUI falls below the turn-on threshold of the
MOSFET. When VSUI reaches (VSWI - 5V), the step-up
regulator and the positive charge pump are enabled
and initiate a soft-start routine.
Soft-Start
The step-up regulator achieves soft-start by linearly
ramping up its internal current limit. The soft-start termi-
nates when the output reaches regulation or the full
current limit has been reached. The current limit rises
from zero to the full current limit in approximately 3ms.
The soft-start feature effectively limits the inrush current
during startup (see the Step-Up Regulator Soft-Start
(Heavy Load) waveforms in the
Typical Operating
Characteristics
).
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to GND with the
midpoint connected to FBP. The number of charge-
pump stages and the setting of the feedback divider
determine the output voltage of the positive charge-
pump regulator. The charge pump includes a high-side
p-channel MOSFET (P1) and a low-side n-channel
MOSFET (N1) to control the power transfer as shown in
Figure 3.
Low-Cost Multiple-Output
Power Supply for LCD TVs
20 ______________________________________________________________________________________
REF
1.25V
OSC
ERROR
AMPLIFIER
P1
N1
DRVP
C19
C22
D5
C23
C20
C21
GNDP
SUP
FBP
POSITIVE CHARGE-PUMP REGULATOR
INPUT
SUPPLY
OUTPUT
MAX17014
Figure 3. Positive Charge-Pump Regulator Block Diagram
During the first half-cycle, N1 turns on and charges fly-
ing capacitors C20 and C21 (Figure 3). During the sec-
ond half cycle, N1 turns off and P1 turns on, level
shifting C20 and C21 by VSUP volts. If the voltage
across C23 plus a diode drop (VOUT + VD) is smaller
than the level-shifted flying capacitor voltage (VC20 +
VSUP), charge flows from C20 to C23 until the diode
(D5) turns off. The amount of charge transferred to the
output is determined by the error amplifier that controls
N1’s on-resistance.
The positive charge-pump regulator’s startup can be
delayed by connecting an external capacitor from
DEL2 to GND. An internal constant-current source
begins charging the DEL2 capacitor when EN2 is logic-
high, and the step-down regulator reaches regulation.
When the DEL2 voltage exceeds VREF, the positive
charge-pump regulator is enabled. Each time it is
enabled, the positive charge-pump regulator goes
through a soft-start routine by ramping up its internal
reference voltage from 0 to 1.25V in 128 steps. The
soft-start period is 3ms (typ) and FBP fault detection is
disabled during this period. The soft-start feature effec-
tively limits the inrush current during startup.
Negative Charge-Pump Regulator
The negative charge-pump regulator is typically used to
generate the negative supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to REF with the
midpoint connected to FBN. The number of charge-
pump stages and the setting of the feedback divider
determine the output of the negative charge-pump reg-
ulator. The charge-pump controller includes a high-side
p-channel MOSFET (P2) and a low-side n-channel
MOSFET (N2) to control the power transfer as shown in
Figure 4.
During the first half cycle, P2 turns on, and flying
capacitor C13 charges to VSUP minus a diode drop
(Figure 4). During the second half cycle, P2 turns off,
and N2 turns on, level shifting C13. This connects C13
in parallel with reservoir capacitor C12. If the voltage
across C12 minus a diode drop is greater than the volt-
age across C13, charge flows from C12 to C13 until the
diode (D3) turns off. The amount of charge transferred
from the output is determined by the error amplifier,
which controls N2’s on-resistance.
The negative charge-pump regulator is enabled when
EN1 is logic-high and the step-down regulator reaches
regulation. Each time it is enabled, the negative
charge-pump regulator goes through a soft-start rou-
tine by ramping down its internal reference voltage
from 1.25V to 250mV in 102 steps. The soft-start period
is 3ms (typ) and FBN fault detection is disabled during
this period. The soft-start feature effectively limits the
inrush current during startup.
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 21
P2
N2
DRVN
GND1
IN
FBN
NEGATIVE CHARGE-PUMP REGULATOR
INPUT
SUPPLY
OUTPUT
REF
MAX17014
C12
C13
R2
R1
D3
REF
0.25V
OSC
ERROR
AMPLIFIER
Figure 4. Negative Charge-Pump Regulator Block Diagram
MAX17014
High-Voltage Switch Control
The MAX17014’s high-voltage switch control block
(Figure 5) consists of two high-voltage p-channel
MOSFETs: Q1, between SRC and GON and Q2, between
GON and DRN. The switch control block is enabled when
VDLP exceeds VREF. Q1 and Q2 are controlled by CTL
and MODE. There are two different modes of operation
(see the
Typical Operating Characteristics
).
Low-Cost Multiple-Output
Power Supply for LCD TVs
22 ______________________________________________________________________________________
MODE
CTL
DLP
SRC
GON
DRN
VREF
SUI DONE
8μA
REF
Q1
Q4
Q3
R
2R
R
50μA
SWITCH CONTROL
THR
9R
R
VL
VL /2
1.25kΩ
SHDN
FAULT
Q5
MAX17014
6kΩ
Q2
Figure 5. Switch Control
Select the first mode by connecting MODE to VL. When
CTL is logic-high, Q1 turns on and Q2 turns off, con-
necting GON to SRC. When CTL is logic-low, Q1 turns
off and Q2 turns on, connecting GON to DRN. GON
can then be discharged through a resistor connected
between DRN and GND or AVDD. Q2 turns off and
stops discharging GON when VGON reaches 10 times
the voltage on THR.
When VMODE is less than 0.8 x VVL, the switch control
block works in the second mode. The rising edge of
VCTL turns on Q1 and turns off Q2, connecting GON to
SRC. An internal n-channel MOSFET, Q3, between
MODE and GND is also turned on to discharge an
external capacitor between MODE and GND. The
falling edge of VCTL turns off Q3, and an internal 50µA
current source starts charging the MODE capacitor.
Once VMODE exceeds VVL/4, the switch control block
turns off Q1 and turns on Q2, connecting GON to DRN.
GON can then be discharged through a resisor con-
nected between DRN and GND or AVDD. Q2 turns off
and stops discharging GON when VGON reaches 10
times the voltage on THR.
The switch control block is disabled and DLP is held
low when EN1 or EN2 is low or the IC is in a fault state.
Operational Amplifiers
The MAX17014 has two operational amplifiers. The
operational amplifiers are typically used to drive the
LCD backplane (VCOM) or the gamma-correction
divider string. They feature ±150mA output short-circuit
current, 100V/µs slew rate, and 20MHz, -3dB band-
width. While the op amp is a rail-to-rail input and output
design, its accuracy is significantly degraded for input
voltages within 2V of its supply rails (OVIN, OGND).
Short-Circuit Current Limit and Input Clamp
The operational amplifiers limit short-circuit current to
approximately ±150mA (-250mA) if the output is direct-
ly shorted to OVIN (OGND). If the short-circuit condition
persists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-
shutdown threshold, an internal thermal sensor immedi-
ately sets the thermal-fault latch, shutting off all the IC’s
outputs. The device remains inactive until the input volt-
age is cycled. The operational amplifiers have 4V input
clamp structures in series with a 500Ωresistance
(Figure 6).
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 23
NEG1
POS1
OVIN
OUT1
NEG2
POS2
OUT2
OGND
OP AMP INPUT CLAMP STRUCTURE
500Ω
±4V
MAX17014
500Ω
±4V
Figure 6. Op Amp Input Clamp Structure
MAX17014
Driving Pure Capacitive Load
The operational amplifiers are typically used to drive
the LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation. As the operational amplifier’s capaci-
tive load increases, the amplifier’s bandwidth decreas-
es and gain peaking increases. A 5Ωto 50Ωsmall
resistor placed between OUT_ and the capacitive load
reduces peaking, but also reduces the gain. An alter-
native method of reducing peaking is to place a series
RC network (snubber) in parallel with the capacitive
load. The RC network does not continuously load the
output or reduce the gain. Typical values of the resistor
are between 100Ωand 200Ω, and the typical value of
the capacitor is 10nF.
Linear Regulator (VL)
The MAX17014 includes an internal linear regulator. VIN
is the input of the linear regulator. The input voltage
range is between 8V and 16.5V. The output voltage is set
to 5V. The regulator powers the internal MOSFET drivers,
PWM controllers, charge-pump regulators, and logic cir-
cuitry. The total external load capability is 25mA. Bypass
VL to GND with a minimum 1µF ceramic capacitor.
Reference Voltage (REF)
The reference output is nominally 1.25V, and can
source at least 50µA (see the
Typical Operating
Characteristics
). VL is the input of the internal reference
block. Bypass REF with a 0.22µF ceramic capacitor
connected between REF and GND.
Frequency Selection (FSEL)
The step-down regulator and step-up regulator use the
same internal oscillator. The FSEL input selects the
switching frequency. Table 3 shows the switching fre-
quency based on the FSEL connection. High-frequency
(1.2MHz) operation optimizes the application for the
smallest component size, trading off efficiency due to
higher switching losses. Low-frequency (600kHz) oper-
ation offers the best overall efficiency at the expense of
component size and board space.
Power-Up Sequence
The step-down regulator starts up when the MAX17014’s
internal reference voltage (REF) is above its undervolt-
age lockout (UVLO) threshold and EN1 is logic-high.
Once the step-down regulator reaches regulation, the
FB2 fault-detection circuit and the negative charge-
pump delay block are enabled. An 8µA current source
at DEL1 charges CDEL1 linearly. The negative charge-
pump regulator soft-starts when VDEL1 reaches VREF.
FBN fault detection is enabled once the negative
charge-pump soft-start is done.
The step-up regulator, p-channel MOSFET pass switch,
and positive charge-pump startup sequence begin
when the step-down regulator reaches regulation and
EN2 is logic-high. An 8µA current source at DEL2
charges CDEL2 linearly and the p-channel MOSFET
pass switch is enabled when VDEL2 reaches VREF. A
30µA current source pulls down on SUI, slowly turning
on the p-channel MOSFET switch between SWI and
SWO. The step-up regulator, positive charge pump,
and the delay block for the high-voltage switch starts
when the SWI to SUI voltage difference (VSWI - VSUI)
reaches the SUI-done threshold (5V, typ). An 8µA cur-
rent source charges CDLP linearly and when VDLP
reaches VREF, the high-voltage switch is enabled and
GON can be controlled by CTL.
The FB1 fault-detection circuit is enabled after the step-
up regulator reaches regulation, and similarly the FBP
fault-detection circuit is enabled after the positive charge
pump reaches regulation. For nondelayed startups,
capacitors can be omitted from DEL1, DEL2, and DLP.
When their current sources pull the floating pins above
their thresholds, the associated outputs start.
Power-Down Control
The MAX17014 disables the step-up regulator, positive-
charge-pump regulator input switch control block,
delay block, and high-voltage switch control block
when EN2 is logic-low, or when the fault latch is set.
The step-down regulator and negative charge-pump
regulator are disabled only when EN1 is logic-low or
when the fault latch is set.
Low-Cost Multiple-Output
Power Supply for LCD TVs
24 ______________________________________________________________________________________
Table 3. Frequency Selection
FSEL SWITCHING FREQUENCY (kHz)
VIN 1200
GND 600
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 25
DLP
TIME
TIME
TIME
TIME
TIME
VL/REF
VIN
NEGATIVE
CHARGE-PUMP
REGULATOR
OUTPUT
POSITIVE
CHARGE-PUMP
REGULATOR
OUTPUT
BUCK OUTPUT
EN1
VIN UVLO
DEL2 STARTS CHARGING WHEN
EN2 IS HIGH AND THE BUCK
SOFT-START IS FINISHED.
AVDD
REF
tSS
DEL1
SUI_DONE
SUI
REF
VGON FLOATING
EN2
REF
DEL2
VGON
tSS
tSS
VGON DEPENDS ON CTL
Figure 7. Power-Up Sequence
MAX17014
Fault Protection
During steady-state operation, if any output of the four
regulators (step-down regulator, step-up regulator,
positive charge-pump regulator, and negative charge-
pump regulator) does not exceed its respective fault-
detection threshold, the MAX17014 activates an inter-
nal fault timer. If any condition or the combination of
conditions indicates a continuous fault for the fault timer
duration (50ms, typ), the MAX17014 triggers a non-
latching output undervoltage fault. After triggering, the
MAX17014 turns off for 160ms (typ) and then restarts
according to the EN1 and EN2 logic states. If, after
restarting, another 50ms fault timeout occurs, the
MAX17014 shuts down for 160ms again, and then
restarts. The restart sequence is repeated 3 times and
after the 50ms fault timeout, the MAX17014 shuts down
and latches off. Once the fault condition is removed,
toggle either EN1 or EN2, or cycle the input voltage to
clear the fault latch and restart the supplies.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the MAX17014.
When the junction temperature exceeds TJ= +160°C, a
thermal sensor immediately activates the fault protec-
tion, which shuts down all the outputs except the refer-
ence and latches off, allowing the device to cool down.
Once the device cools down by at least approximately
15°C, cycle the input voltage to clear the fault latch and
restart the MAX17014.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of TJ= +150°C.
Design Procedure
Step-Down Regulator
Inductor Selection
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
resistance (RDC). The following equation includes a
constant, LIR, which is the ratio of peak-to-peak induc-
tor ripple current to DC load current. A higher LIR value
allows smaller inductance, but results in higher losses
and higher ripple. A good compromise between size
and losses is typically found at about 20% to 50% rip-
ple-current to load-current ratio (LIR):
where IOUT(MAX) is the maximum DC load current, and
the switching frequency fSW is 1.2MHz when FSEL is
connected to VL or 0.6MHz when FSEL is connected to
GND. The exact inductor value is not critical and can
be adjusted to make trade-offs among size, cost, and
efficiency. Lower inductor values minimize size and
cost, but they also increase the output ripple and
reduce the efficiency due to higher peak currents. On
the other hand, higher inductor values increase effi-
ciency, but at some point resistive losses due to extra
turns of wire exceed the benefit gained from lower AC
current levels.
The inductor’s saturation current must exceed the peak
inductor current. The peak current can be calculated by:
The inductor’s DC resistance should be low for good
efficiency. Find a low-loss inductor having the lowest
possible DC resistance that fits in the allotted dimen-
sions. Ferrite cores are often the best choice. Shielded-
core geometries help keep noise, EMI, and switching
waveform jitter low.
Considering the typical operating circuit in Figure 1, the
maximum load current (IOUT(MAX)) is 2A with a 3.3V
output and a typical 12V input voltage. Choosing an
LIR of 0.4 at this operating point:
At that operating point, the ripple current and the peak
current are:
Input Capacitors
The input filter capacitors reduce peak currents drawn
from the power source and reduce noise and voltage
ripple on the input caused by the regulator’s switching.
They are usually selected according to input ripple cur-
rent requirements and voltage rating, rather than
capacitance value. The input voltage and load current
determine the RMS input ripple current (IRMS):
II VVV
V
RMS OUT
OUT VIN OUT
VIN
=× ×−
()
IA
AA
OUT PEAK_
..=+ =2077
2239
IVVV
MHz H A
OUT RIPPLE_
..
.. .=×−
()
××
≈
33 12 33
12 26 12 077
μ
LVVV
V MHz A H
OUT =×−
()
×××
≈
33 12 33
12 1 2 2 0 4 26
..
..
.μ
II
I
OUT PEAK OUT MAX OUT RIPPLE
_()
_
=+
2
IVVV
fL V
OUT RIPPLE OUT VIN OUT
SW OUT VIN
_=×−
()
××
LVVV
V f I LIR
OUT OUT IN OUT
IN SW OUT MAX
=×−
()
×× ×
()
Low-Cost Multiple-Output
Power Supply for LCD TVs
26 ______________________________________________________________________________________
The worst case is IRMS = 0.5 x IOUT, which occurs at
VVIN = 2 x VOUT.
For most applications, ceramic capacitors are used
because of their high ripple current and surge current
capabilities. For optimal circuit long-term reliability,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current corresponding
to the maximum load current.
Output Capacitor Selection
Since the MAX17014’s step-down regulator is internally
compensated, it is stable with any reasonable amount
of output capacitance. However, the actual capacitance
and equivalent series resistance (ESR) affect the regu-
lator’s output ripple voltage and transient response. The
rest of this section deals with how to determine the out-
put capacitance and ESR needs according to the
ripple-voltage and load-transient requirements.
The output voltage ripple has two components: varia-
tions in the charge stored in the output capacitor, and
the voltage drop across the capacitor’s ESR caused by
the current into and out of the capacitor:
where IOUT_RIPPLE is defined in the
Inductor Selection
of the
Step-Down Regulator
section, COUT is the output
capacitance, and RESR_OUT is the ESR of the output
capacitor COUT. In Figure 1’s circuit, the inductor ripple
current is 0.77A. If the voltage-ripple requirement of
Figure 1’s circuit is ±1% of the 3.3V output, then the
total peak-to-peak ripple voltage should be less than
66mV. Assuming that the ESR ripple and the capacitive
ripple each should be less than 50% of the total peak-
to-peak ripple, then the ESR should be less than 43mΩ
and the output capacitance should be more than 2.43µF
to meet the total ripple requirement. A 22µF capacitor
with ESR (including PCB trace resistance) of 10mΩis
selected for the standard application circuit in Figure 1,
which easily meets the voltage-ripple requirement.
The step-down regulator’s output capacitor and ESR can
also affect the voltage undershoot and overshoot when
the load steps up and down abruptly. The step-down
regulator’s transient response is typically dominated by
its loop response and the time constant of its internal
integrator. However, excessive inductance or insufficient
output capacitance can degrade the natural transient
response. Calculating the ideal transient response of
the inductor and capacitor, which assumes an ideal
response from the regulator, can ensure that these
components do not degrade the IC’s natural response.
The ideal undershoot and overshoot have two compo-
nents: the voltage steps caused by ESR, and the voltage
sag and soar due to the finite capacitance and the induc-
tor current slew rate. Use the following formulas to check
if the ESR is low enough and the output capacitance is
large enough to prevent excessive soar and sag.
The amplitude of the ESR step is a function of the load
step and the ESR of the output capacitor:
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor
value, the input-to-output voltage differential, and the
maximum duty cycle:
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor
value, and the output voltage:
Keeping the full-load overshoot and undershoot less
than 3% ensures that the step-down regulator’s natural
integrator response dominates. Given the component
values in the circuit of Figure 1 and assuming a full 2A
step load transient, the voltage step due to capacitor
ESR is negligible. The voltage sag and soar are 44.3mV
and 71.6mV, or a little over 1% and 2%, respectively.
Rectifier Diode
The MAX17014’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 2A Schottky diode
works well in the MAX17014’s step-down regulator.
Step-Up Regulator
Inductor Selection
The inductance value, peak current rating, and series
resistance are factors to consider when selecting the
inductor. These factors influence the converter’s effi-
ciency, maximum output load capability, transient
response time, and output voltage ripple. Physical size
and cost are also important factors to be considered.
VLI
CV
OUT SOAR OUT OUT
OUT OUT
_
()
=×
××
Δ2
2
VLI
CV DV
OUT SAG OUT OUT
OUT VIN MIN MAX OUT
_
()
()
=×
×× ×−
()
Δ2
2
VIR
OUT ESR STEP OUT ESR OUT__ _
=×Δ
VI
Cf
OUT RIPPLE C OUT RIPPLE
OUT SW
_() _
=××8
VIR
OUT RIPPLE ESR OUT RIPPLE ESR OUT_() _ _
=×
VV V
OUT RIPPLE OUT RIPPLE ESR OUT RIPPLE C__()_()
=+
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 27
MAX17014
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the cur-
rent ripple and therefore reduce the peak current,
which decreases core losses in the inductor and I2R
losses in the entire power path. However, large induc-
tor values also require more energy storage and more
turns of wire, which increase physical size and can
increase I2R losses in the inductor. Low inductance val-
ues decrease the physical size but increase the current
ripple and peak current. Finding the best inductor
involves choosing the best compromise among circuit
efficiency, inductor size, and cost.
The equations used here include a constant, LIR, which
is the ratio of the inductor peak-to-peak ripple current to
the average DC inductor current at the full-load current.
The best trade-off between inductor size and circuit effi-
ciency for step-up regulators generally has an LIR
between 0.2 and 0.5. However, depending on the AC
characteristics of the inductor core material and ratio of
inductor resistance to other power path resistances, the
best LIR can shift up or down. If the inductor resistance
is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extremely
thin high-resistance inductors are used, as is common
for smaller LCD panel applications, the best LIR can
increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
Calculate the approximate inductor value using the
typical input voltage (VVIN), the maximum output cur-
rent (IAVDD(MAX)), the expected efficiency (ηTYP) taken
from an appropriate curve in the
Typical Operating
Characteristics
, and an estimate of LIR based on the
above discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VVIN(MIN) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from an appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX17014’s LX1 current limit should exceed IAVDD_PEAK
and the inductor’s DC current rating should exceed
IVIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.05Ωseries resistance.
Considering the typical operating circuit in Figure 1, the
maximum load current (IAVDD(MAX)) is 1.5A with a 16V
output and a typical 12V input voltage. Choosing an
LIR of 0.25 and estimating efficiency of 90% at this
operating point:
Using the circuit’s minimum input voltage (10.8V) and
estimating efficiency of 90% at that operating point:
The ripple current and the peak current are:
Output Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and dis-
charging of the output capacitance, and the ohmic rip-
ple due to the capacitor’s ESR:
and:
VIR
AVDD RIPPLE ESR AVDD PEAK ESR AVDD_() _ _
≈
VI
C
VV
Vf
AVDD RIPPLE C AVDD
AVDD
AVDD VIN
AVDD SW
_()
≈−
⎛
⎝
⎜⎞
⎠
⎟
VV V
AVDD RIPPLE AVDD RIPPLE C AVDD RIPPLE ESR__()_()
=+
IA
AA
PEAK =+ ≈247 062
2278...
IVV V
H V MHz A
RIPPLE =×−
()
×× ≈
10 8 16 10 8
47 16 12 062
..
..
.
μ
IAV
VA
VIN DCMAX(, )
.
..
.=×
×≈
15 16
10 8 0 9 247
LV
V
VV
A MHz H
AVDD =⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟≈
12
16
16 12
15 12
090
025 47
2
..
.
..μ
III
AVDD PEAK VIN DCMAX AVDD RIPPLE
_(,)
_
=+
2
IVVV
LVf
AVDD RIPPLE
VIN MIN AVDD VIN MIN
AVDD AVDD SW
_
() ()
=×−
()
××
IIV
V
VIN DCMAX AVDD MAX AVDD
VIN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
I f LIR
AVDD VIN
AVDD
AVDD VIN
AVDD MAX SW
TYP
=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
2
()
η
Low-Cost Multiple-Output
Power Supply for LCD TVs
28 ______________________________________________________________________________________
where IAVDD_PEAK is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output voltage ripple is typically dominated by
VAVDD_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be
considered. Note that all ceramic capacitors typically
have large temperature coefficient and bias voltage
coefficients. The actual capacitor value in circuit is typi-
cally significantly less than the stated value.
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input supply and reduces noise injection into
the IC. A 22µF ceramic capacitor is used in the typical
operating circuit (Figure 1) because of the high source
impedance seen in typical lab setups. Actual applica-
tions usually have much lower source impedance since
the step-up regulator often runs directly from the output
of another regulated supply. Typically, the input capaci-
tance can be reduced below the values used in the typi-
cal operating circuit.
Rectifier Diode
The MAX17014’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider from
the output (VAVDD) to GND with the center tap connect-
ed to FB1 (see Figure 1). Select R4 in the 10kΩto 50kΩ
range. Calculate R3 with the following equation:
where VFB1, the step-up regulator’s feedback set point,
is 1.25V. Place R4 and R3 close to the IC.
Loop Compensation
Choose RCOMP (R5 in Figure 1) to set the high-frequen-
cy integrator gain for fast transient response. Choose
CCOMP (C17 in Figure 1) to set the integrator zero to
maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient response waveforms.
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest number
of charge-pump stages that meet the output requirement.
The number of positive charge-pump stages is given by:
where nPOS is the number of positive charge-pump
stages, VGON is the output of the positive charge-pump
regulator, VSUP is the supply voltage of the charge-
pump regulators, VDis the forward voltage drop of the
charge-pump diode, and VDROPOUT is the dropout
margin for the regulator. Use VDROPOUT = 300mV.
The number of negative charge-pump stages is given by:
where nNEG is the number of negative charge-pump
stages and VGOFF is the output of the negative charge-
pump regulator.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VAVDD and the first stage of the
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
stage to VOUT or another available supply. If the first
charge-pump stage is powered from VOUT, then the
above equations become:
nVV V
VV
NEG GOFF DROPOUT OUT
SUP D
=−+ +
−×2
nVV V
VV
POS GON DROPOUT OUT
SUP D
=+−
−×2
nVV
VV
NEG GOFF DROPOUT
SUP D
=−+
−×2
nVV V
VV
POS GON DROPOUT AVDD
SUP D
=+−
−×2
CVC
IR
COMP AVDD AVDD
AVDD MAX COMP
≈×
××1250 ()
RVV C
LI
COMP VIN AVDD AVDD
AVDD AVDD MAX
≈×× ×
×
125
()
RR V
V
AVDD
FB
34 1
1
=× −
⎛
⎝
⎜⎞
⎠
⎟
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 29
MAX17014
Flying Capacitors
Increasing the flying capacitors (connected to DRVN
and DRVP) value lowers the effective source impedance
and increases the output-current capability. Increasing
the capacitance indefinitely has a negligible effect on
output-current capability because the internal switch
resistance and the diode impedance place a lower limit
on the source impedance. A 0.1µF ceramic capacitor
works well in most low-current applications. The flying
capacitor’s voltage rating must exceed the following:
where n is the stage number in which the flying capaci-
tor appears.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where COUT_CP is the output capacitor of the charge
pump, ILOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple.
Output Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from the
SRC output to GND with the center tap connected to
FBP (Figure 1). Select the lower resistor of divider R17
in the 10kΩto 30kΩrange. Calculate the upper resis-
tor, R16, with the following equation:
where VFBP = 1.25V (typ).
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R2 in the 20kΩto 50kΩrange.
Calculate R1 with the following equation:
where VFBN = 250mV, VREF = 1.25V. Note that REF can
only source up to 50µA, using a resistor less than 20kΩ
for R1 results in higher bias current than REF can supply.
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of respective high-current loops
by placing each DC-DC converter’s inductor,
diode, and output capacitors near its input capaci-
tors and its LX_ and GND_ pins. For the step-down
regulator, the high-current input loop goes from the
positive terminal of the input capacitor to the IC’s IN
pin, out of LX2, to the inductor, to the positive termi-
nals of the output capacitors, reconnecting the out-
put capacitor and input capacitor ground terminals.
The high-current output loop is from the inductor to
the positive terminals of the output capacitors, to
the negative terminals of the output capacitors, and
to the Schottky diode (D2). For the step-up regula-
tor, the high-current input loop goes from the posi-
tive terminal of the input capacitor to the inductor,
to the IC’s LX1 pin, out of GND1, and to the input
capacitor’s negative terminal. The high-current out-
put loop is from the positive terminal of the input
capacitor to the inductor, to the output diode (D1),
to the positive terminal of the output capacitors,
reconnecting between the output capacitor and
input capacitor ground terminals. Connect these
loop components with short, wide connections.
Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to
reduce resistance and inductance.
Create a power ground island for the step-down reg-
ulator, consisting of the input and output capacitor
grounds and the diode ground. Connect all these
together with short, wide traces or a small ground
plane. Similarly, create a power ground island
(GND1) for the step-up regulator, consisting of the
input and output capacitor grounds and the GND1
pin. Create a power ground island (CPGND) for the
positive and negative charge pumps, consisting of
SUP and output (SRC, VGOFF) capacitor grounds,
and negative charge-pump diode ground. Connect
CPGND ground plane to GND1 ground plane
together with wide traces. Maximizing the width of
the power ground traces improves efficiency and
reduces output voltage ripple and noise spikes.
• Create an analog ground plane (GND) consisting of
the GND pin, all the feedback divider ground con-
nections, the COMP and DEL capacitor ground
connections, and the device’s exposed backside
pad. Connect GND1 and GND islands by connect-
ing the two ground pins directly to the exposed
backside pad. Make no other connections between
the GND1 and GND ground planes.
RR VV
VV
FBN GOFF
REF FBN
12=× −
−
RR V
V
GON
FBP
17 16 1=× −
⎛
⎝
⎜
⎞
⎠
⎟
CI
fV
OUT CP LOAD CP
OSC RIPPLE CP
__
_
≥2
VnV
CX SUP
>×
Low-Cost Multiple-Output
Power Supply for LCD TVs
30 ______________________________________________________________________________________
• Place all feedback voltage-divider resistors as
close to their respective feedback pins as possible.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up switch-
ing noise. Care should be taken to avoid running
any feedback trace near LX1, LX2, DRVP, or DRVN.
• Place VIN pin, VL pin, and REF pin bypass capaci-
tors as close to the device as possible. The ground
connection of the VL bypass capacitor should be
connected directly to the GND pin with a wide trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX1 and LX2 nodes while
keeping them wide and short. Keep the LX1 and
LX2 nodes away from feedback nodes (FB1, FB2,
FBP, and FBN) and analog ground. Use DC traces
as a shield, if necessary.
Refer to the MAX17014 evaluation kit for an example of
proper board layout.
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 31
LX2
REF
FB1
LX1 LX1
GND
COMP
VIN
OUT
AVDD
FSEL
FB2
OUT
ON/OFF
ON/OFF
VL
VIN VIN
GON
OVIN
OGND
VL
REF
BST
GON
DRN
CTL
SWI
GON CONTROL
DRVN
FBN
CPGND
REF
DRVP
FBP
SUP
SRC
GND1 GND1
NEG2
OUT2
VCOM1
DEL1
DEL2
EN1
EN2
NEG1
OUT1
SWI
SWO
SUI
POS1
THR
POS2
DLP
MODE
AVDD
VCOM2
SWI
SRC
AVDD
IN2 IN2
LX2
GOFF
MAX17014
EP
Simplified Operating Circuit
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
32 ______________________________________________________________________________________
TOP VIEW
MAX17014
THIN QFN
(7mm x 7mm)
13
14
15
16
17
18
19
20
21
22
23
24
SUP
DRVN
GND
FBN
REF
DEL1
N.C.
OUT
FB2
BST
LX2
LX2
48
47
46
45
44
43
42
41
40
39
38
37
12345678910
11 12
NEG1
OGND
OUT2
POS2
NEG2
OVIN
SWO
FB1
SUI
SWI
LX1
LX1
DRVP
CPGND
FBP
SRC
GON
DRN
DLP
CTL
MODE
THR
OUT1
POS1
36 35 34 33 32 31 30 29 28 27 26 25
IN2
IN2
VIN
FSEL
DEL2
VL
COMP
EN2
EN1
GND
GND1
GND1
Pin Configuration
Chip Information
TRANSISTOR COUNT: 15,362
PROCESS: BiCMOS
MAX17014
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
32, 44, 48L QFN.EPS
e
L
e
L
A1 A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2
(NE-1) X e
(ND-1) X e
e
C
L
C
L
C
L
C
L
k
PACKAGE OUTLINE
21-0144
2
1
F
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
Low-Cost Multiple-Output
Power Supply for LCD TVs
______________________________________________________________________________________ 33
MAX17014
Low-Cost Multiple-Output
Power Supply for LCD TVs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
34
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
21-0144
2
2
F
32, 44, 48, 56L THIN QFN, 7x7x0.8mm