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LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

LMC7101, LMC7101Q-Q1 Tiny Low-Power Operational Amplifier

With Rail-to-Rail Input and Output

1 Features 3 Description

The LMC7101 device is a high-performance CMOS

1• Tiny 5-Pin SOT-23 Package Saves operational amplifier available in the space-saving 5-

Space—Typical Circuit Layouts Take Half the pin SOT-23 tiny package. This makes the LMC7101

Space of 8-Pin SOIC Designs ideal for space- and weight-critical designs. The

• Ensured Specifications at 2.7-V, 3-V, 5-V, 15-V performance is similar to a single amplifier of the

Supplies LMC6482 and LMC6484 types, with rail-to-rail input

and output, high open-loop gain, low distortion, and

• Typical Supply Current 0.5 mA at 5 V low-supply currents.

• Typical Total Harmonic Distortion of 0.01% at 5 V The main benefits of the tiny package are most

• 1-MHz Gain Bandwidth apparent in small portable electronic devices, such as

• Similar to Popular LMC6482 and LMC6484 mobile phones, pagers, notebook computers,

• Rail-to-Rail Input and Output personal digital assistants, and PCMCIA cards. The

tiny amplifiers can be placed on a board where they

• Temperature Range –40°C to 125°C are needed, thus simplifying board layout.

(LMC7101Q-Q1)

Device Information(1)

2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)

• Mobile Communications LMC7101, SOT-23 (5) 2.90 mm × 1.60 mm

• Notebooks and PDAs LMC7101Q-Q1

• Battery Powered Products (1) For all available packages, see the orderable addendum at

the end of the data sheet.

• Sensor Interface

• Automotive Applications (LMC7101Q-Q1)

Example Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

Table of Contents

7.1 Overview................................................................. 20

1 Features.................................................................. 17.2 Functional Block Diagram....................................... 20

2 Applications ........................................................... 17.3 Feature Description................................................. 20

3 Description............................................................. 17.4 Device Functional Modes........................................ 21

4 Revision History..................................................... 28 Application and Implementation ........................ 22

5 Pin Configuration and Functions......................... 38.1 Application Information............................................ 22

6 Specifications......................................................... 48.2 Typical Application ................................................. 23

6.1 Absolute Maximum Ratings ...................................... 49 Power Supply Recommendations...................... 25

6.2 ESD Ratings: LMC7101............................................ 410 Layout................................................................... 25

6.3 ESD Ratings: LMC7101Q-Q1................................... 410.1 Layout Guidelines ................................................. 25

6.4 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 25

6.5 Thermal Information.................................................. 511 Device and Documentation Support................. 26

6.6 Electrical Characteristics: 2.7 V................................ 511.1 Documentation Support ........................................ 26

6.7 DC Electrical Characteristics: 3 V ............................ 611.2 Related Links ........................................................ 26

6.8 DC Electrical Characteristics: 5 V............................. 711.3 Community Resource............................................ 26

6.9 DC Electrical Characteristics: 15 V .......................... 811.4 Trademarks........................................................... 26

6.10 AC Electrical Characteristics: 5 V........................... 911.5 Electrostatic Discharge Caution............................ 26

6.11 AC Electrical Characteristics: 15 V......................... 911.6 Glossary................................................................ 26

6.12 Typical Characteristics.......................................... 10 12 Mechanical, Packaging, and Orderable

7 Detailed Description............................................ 20 Information........................................................... 26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (March 2013) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 22

Product Folder Links: LMC7101 LMC7101Q-Q1

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LMC7101Q-Q1

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

5 Pin Configuration and Functions

DBV Package

5-Pin SOT-23

Top View

Pin Functions

PIN TYPE DESCRIPTION

NO. NAME

1 OUTPUT O Output

2 V+P Positive Supply

3 INPUT+ I Noninverting Input

4 INPUT– I Inverting Input

5 V–P Negative Supply

Product Folder Links: LMC7101 LMC7101Q-Q1

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Difference input voltage ±Supply Voltage

Voltage at input and output pins (V+) + 0.3, (V–) – 0.3 V

Supply voltage (V+– V–) 16 V

Current at input pin –5 5 mA

Current at output pin(3) –35 35 mA

Current at power supply pin 35 mA

Lead temperature (soldering, 10 sec.) 260 °C

Junction temperature(4) 150 °C

Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the TI Sales Office or Distributors for availability and specifications.

(3) Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in

exceeding the maximum allowed junction temperature at 150°C.

(4) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly into a PC board.

6.2 ESD Ratings: LMC7101 VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V

Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: LMC7101Q-Q1 VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 ±1000 V

Machine model (MM) ±200

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).(1)

MIN MAX UNIT

Supply voltage, V+2.7 15.5 V

LMC7101AI, LMC7101BI –40 85 °C

Junction Temperature, TJLMC7101Q-Q1 –40 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Product Folder Links: LMC7101 LMC7101Q-Q1

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

6.5 Thermal Information LMC7101

THERMAL METRIC(1) DBV (SOT-23) UNIT

5 PINS

RθJA Junction-to-ambient thermal resistance 170.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 124.7 °C/W

RθJB Junction-to-board thermal resistance 30.8 °C/W

ψJT Junction-to-top characterization parameter 17.7 °C/W

ψJB Junction-to-board characterization parameter 30.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.6 Electrical Characteristics: 2.7 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 2.7 V, V–= 0 V, VCM = VO= V+/ 2 and RL> 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

VOS Input offset voltage average drift 0.11 6 9 9 mV

V+= 2.7 V

TCVOS Input offset voltage 1 μV/°C

IBInput bias current –40°C ≤TJ≤125°C 1 64 64 1000 pA

IOS Input offset current –40°C ≤TJ≤125°C 0.5 32 32 2000 pA

RIN Input resistance >1 Tera Ω

0 V ≤VCM ≤2.7 V

CMRR Common-mode rejection ratio 70 55 50 50 dB

V+= 2.7 V

0 0 0 0 V

Input common mode voltage

VCM For CMRR ≥50 dB

range 3 2.7 2.7 2.7 V

V+= 1.35 V to 1.65 V

PSRR Power supply rejection ratio 60 50 45 45 dB

V–= –1.35 V to –1.65 V

VCM = 0

CIN Common-mode input capacitance 3 pF

RL= 2 kΩ2.45 2.15 2.15 2.15

VOOutput swing, min V

RL= 10 kΩ2.68 2.64 2.64 2.64

RL= 2 kΩ0.25 0.5 0.5 0.5

VOOutput swing, max V

RL= 10 kΩ0.025 0.06 0.06 0.06

0.5 0.81 0.81 0.81

ISSupply current mA

–40°C ≤TJ≤125°C 0.5 0.95 0.95 0.95

SR Slew rate(3) 0.7 V/μs

GBW Gain-bandwidth product 0.6 MHz

(1) Typical values represent the most likely parametric normal.

(2) When operated at temperature between –40°C and 85°C, the LMC7101Q-Q1 will meet LMC7101BI specifications.

(3) V+= 15 V. Connected as a voltage follower with a 10-V step input. Number specified is the slower of the positive and negative slew

rates. RL= 100 kΩconnected to 7.5 V. Amplifier excited with 1 kHz to produce VO= 10 VPP.

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

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6.7 DC Electrical Characteristics: 3 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 3 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

4 7 7

VOS Input offset voltage mV

–40°C ≤TJ≤125°C 0.11 6 9

TCVOS Input offset voltage average drift 1 μV/°C

IBInput current –40°C ≤TJ≤125°C 1 64 64 1000 pA

IOS Input offset current –40°C ≤TJ≤125°C 0.5 32 32 2000 pA

RIN Input resistance >1 Tera Ω

0 V ≤VCM ≤3 V

CMRR Common-mode rejection ratio 74 64 60 60 db

V+= 3 V

0 0 0 0

Input common-mode voltage

VCM For CMRR ≥50 dB V

range 3.3 3 3 3

V+= 1.5 V to 7.5 V

PSRR Power supply rejection ratio 80 68 60 60 dB

V–= –1.5 V to –7.5 V

VO= VCM = 0

CIN Common-mode input capacitance 3 pF

RL= 2 kΩ2.8 2.6 2.6 2.6

VOOutput swing, min V

RL= 600 Ω0.2 0.4 0.4 0.4

RL= 2 kΩ2.7 2.5 2.5 2.5

VOOutput swing, max V

RL= 600 Ω0.37 0.6 0.6 0.6

0.81 0.81 0.81

ISSupply current mA

–40°C ≤TJ≤125°C 0.5 0.95 0.95 0.95

(1) Typical values represent the most likely parametric normal.

(2) When operated at temperature between –40°C and 85°C, the LMC7101Q-Q1 will meet LMC7101BI specifications.

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

6.8 DC Electrical Characteristics: 5 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

0.11 3 7 7

V+= 5 V

VOS Input offset voltage mV

0.11 5 9 9

V+= 5 V, –40°C ≤TJ≤125°C

Input offset voltage

TCVOS 1μV/°C

average drift

IBInput current –40°C ≤TJ≤125°C 1 64 64 1000 pA

IOS Input offset current –40°C ≤TJ≤125°C 0.5 32 32 2000 pA

RIN Input resistance >1 Tera Ω

0 V ≤VCM ≤5 V

LMC7101Q-Q1 at 125°C 82 65 60 60

0.2 V ≤VCM ≤4.8 V

Common-mode

CMRR db

0 V ≤VCM ≤5 V

rejection ratio LMC7101Q-Q1 at 125°C 82 60 55 55

0.2 V ≤VCM ≤4.8 V

–40°C ≤TJ≤125°C

V+= 5 V to 15 V 82 70 65 65

V–= 0 V, VO= 1.5 V

Positive power supply

+PSRR dB

V+= 5 V to 15 V

rejection ratio 82 65 62 62

V–= 0 V, VO= 1.5 V

–40°C ≤TJ≤125°C

V–= –5 V to –15 V 82 70 65 65

V+= 0 V, VO= –1.5 V

Negative power supply

–PSRR dB

V–= –5 V to –15 V

rejection ratio 82 65 62 62

V+= 0 V, VO= –1.5 V

–40°C ≤TJ≤125°C

For CMRR ≥50 dB –0.3 –0.2 –0.2 –0.2 V

For CMRR ≥50 dB –0.3 0 0 0.2

Input common-mode –40°C ≤TJ≤125°C

VCM voltage range 5.3 5.2 5.2 5.2 V

–40°C ≤TJ≤125°C 5.3 5 5 4.8

Common-mode input

CIN 3 pF

capacitance

RL= 2 kΩ4.9 4.7 4.7 4.7 V

RL= 2 kΩ, –40°C ≤TJ≤125°C 4.9 4.6 4.6 4.54

0.1 0.18 0.18 0.18 V

–40°C ≤TJ≤125°C 0.1 0.24 0.24 0.28

VOOutput swing RL= 600 Ω4.7 4.5 4.5 4.5 V

RL= 600 Ω, –40°C ≤TJ≤125°C 4.7 4.24 4.24 4.28

0.3 0.5 0.5 0.5 V

–40°C ≤TJ≤125°C 0.3 0.65 0.65 0.8

VO= 0 V 24 24 16 16 16

Sourcing mA

VO= 0 V 24 24 11 11 9

–40°C ≤TJ≤125°C

Output short circuit

ISC current VO= 5 V 19 11 11 11

Sinking mA

VO= 5 V 19 7.5 7.5 5.8

–40°C ≤TJ≤125°C

0.5 0.85 0.85 0.85

ISSupply current mA

–40°C ≤TJ≤125°C 0.5 1 1 1

(1) Typical values represent the most likely parametric normal.

(2) When operated at temperature between –40°C and 85°C, the LMC7101Q-Q1 will meet LMC7101BI specifications.

Product Folder Links: LMC7101 LMC7101Q-Q1

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

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6.9 DC Electrical Characteristics: 15 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 15 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

VOS Input offset voltage 0.11 mV

Input offset voltage

TCVOS 1μV/°C

average drift

IBInput current –40°C ≤TJ≤125°C 1 64 64 1000 pA

IOS Input offset current –40°C ≤TJ≤125°C 0.5 32 32 2000 pA

RIN Input resistance >1 Tera Ω

0 V ≤VCM ≤15 V

LMC7101Q-Q1 at 125°C 82 70 65 65

0.2 V ≤VCM ≤14.8 V

Common-mode

CMRR dB

0 V ≤VCM ≤15 V

rejection ratio LMC7101Q-Q1 at 125°C 82 65 60 60

0.2 V ≤VCM ≤14.8 V

–40°C ≤TJ≤125°C

V+= 5 V to 15 V 82 70 65 65

V–= 0 V, VO= 1.5 V

Positive power supply

+PSRR dB

V+= 5 V to 15 V

rejection ratio 82 65 62 62

V–= 0 V, VO= 1.5 V

–40°C ≤TJ≤125°C

V–= –5 V to –15 V 82 70 65 65

V+= 0 V, VO= –1.5 V

Negative power

–PSRR dB

V–= –5 V to –15 V

supply rejection ratio 82 65 62 62

V+= 0 V, VO= –1.5 V

–40°C ≤TJ≤125°C

V+= 5 V –0.3 –0.2 –0.2 –0.2

For CMRR ≥50 dB V

V+= 5 V

Input common-mode -0.3 0 0 0.2

For CMRR ≥50 dB

VCM voltage range –40°C ≤TJ≤125°C

15.3 15.2 15.2 15.2 V max

–40°C ≤TJ≤125°C 15.3 15 15 14.8

RL= 2 kΩ340 80 80 80

Sourcing RL= 2 kΩ340 40 40 30

–40°C ≤TJ≤125°C V/mV

RL= 2 kΩ24 15 15 15

Large signal voltage

AVgain(3) Sinking RL= 2 kΩ24 10 10 4

–40°C ≤TJ≤125°C

Sourcing 300 34 34 34

RL= 600 ΩV/mV

Sinking 15 6 6 6

CIN Input capacitance 3 pF

V+= 15 V 14.7 14.4 14.4 14.4

RL= 2 kΩ

V+= 15 V 14.7 14.2 14.2 14.2

RL= 2 kΩ

–40°C ≤TJ≤125°C

0.16 0.32 0.32 0.32 V

–40°C ≤TJ≤125°C 0.16 0.45 0.45 0.45

VOOutput swing V+= 15 V 14.1 13.4 13.4 13.4

RL= 600 Ω

V+= 15 V 14.1 13 13 12.85

RL= 600 Ω

–40°C ≤TJ≤125°C

0.5 1 1 1 V

–40°C ≤TJ≤125°C 0.5 1.3 1.3 1.5

(1) Typical values represent the most likely parametric normal.

(2) When operated at temperature between –40°C and 85°C, the LMC7101Q-Q1 will meet LMC7101BI specifications.

(3) V+= 15 V, VCM = 1.5 V and RLconnect to 7.5 V. For sourcing tests, 7.5 V ≤VO≤12.5 V. For sinking tests, 2.5 V ≤VO≤7.5 V.

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

DC Electrical Characteristics: 15 V (continued)

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 15 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

VO= 0 V 50 30 30 30

Sourcing VO= 0 V 50 20 20 20

–40°C ≤TJ≤125°C

Output short circuit

ISC mA

current(4) VO= 12 V 50 30 30 30

Sinking VO= 12 V 50 20 20 20

–40°C ≤TJ≤125°C

1.5 1.5 1.5

ISSupply current 0.8 mA

–40°C ≤TJ≤125°C 1.71 1.71 1.75

(4) Do not short circuit output to V+when V+is greater than 12 V or reliability will be adversely affected.

6.10 AC Electrical Characteristics: 5 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI

PARAMETER TEST CONDITIONS TYP(1) UNIT

LIMIT(2) LIMIT(2)

f = 10 kHz, AV= –2

THD Total harmonic distortion 0.01%

RL= 10 kΩ, VO= 4 VPP

SR Slew rate 1 V/μs

GBW Gain bandwidth product 1 MHz

(1) Typical values represent the most likely parametric normal.

(2) All limits are specified by testing or statistical analysis.

6.11 AC Electrical Characteristics: 15 V

Unless otherwise specified, all limits specified for TJ= 25°C, V+= 15 V, V–= 0 V, VCM = 1.5 V, VO= V+/ 2 and RL= 1 MΩ.

LMC7101AI LMC7101BI LMC7101Q-Q1(2)

PARAMETER TEST CONDITIONS TYP(1) UNIT

MIN MAX MIN MAX MIN MAX

0.5 0.5 0.5

V+= 15 V V/μs

SR Slew rate(3) 1.1 min

0.4 0.4 0.4

V+= 15 V, –40°C ≤TJ≤125°C

Gain-bandwidth

GBW 1.1 MHz

V+= 15 V

product

φmPhase margin 45 deg

GmGain margin 10 dB

Input-referred voltage

enf = 1 kHz, VCM = 1 V 37

noise

Input-referred current

Inf = 1 kHz 1.5

noise

f = 10 kHz, AV= –2

Total harmonic RL= 10 kΩ

THD 0.01%

distortion VO= 8.5 VPP

(1) Typical values represent the most likely parametric normal.

(2) When operated at temperature between –40°C and 85°C, the LMC7101Q-Q1 will meet LMC7101BI specifications.

(3) V+= 15 V. Connected as a voltage follower with a 10-V step input. Number specified is the slower of the positive and negative slew

rates. RL= 100 kΩconnected to 7.5 V. Amplifier excited with 1 kHz to produce VO= 10 VPP.

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6.12 Typical Characteristics

6.12.1 Typical Characteristics: 2.7 V

V+= 2.7 V, V–=0V,TA= 25°C, unless otherwise specified.

Figure 1. Open Loop Frequency Response Figure 2. Input Voltage vs Output Voltage

Figure 3. Gain and Phase vs Capacitance Load Figure 4. Gain and Phase vs Capacitance Load

Figure 5. dVOS vs Supply Voltage Figure 6. dVOS vs Common Mode Voltage

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Typical Characteristics: 2.7 V (continued)

Figure 7. Sinking Current vs Output Voltage Figure 8. Sourcing Current vs Output Voltage

6.12.2 Typical Characteristics: 3 V

V+=3V,V–=0V,TA= 25°C, unless otherwise specified.

Figure 9. Open Loop Frequency Response Figure 10. Input Voltage vs Output Voltage

Figure 12. Sourcing Current vs Output Voltage

Figure 11. Input Voltage Noise vs Input Voltage

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Typical Characteristics: 3 V (continued)

Figure 13. Sinking Current vs Output Voltage Figure 14. CMRR vs Input Voltage

6.12.3 Typical Characteristics: 5 V

V+=5V,V–=0V,TA= 25°C, unless otherwise specified.

Figure 16. Input Voltage vs Output Voltage

Figure 15. Open Loop Frequency Response

Figure 17. Input Voltage Noise vs Input Voltage Figure 18. Sourcing Current vs Output Voltage

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SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

Typical Characteristics: 5 V (continued)

Figure 20. CMRR vs Input Voltage

Figure 19. Sinking Current vs Output Voltage

6.12.4 Typical Characteristics: 15 V

V+= +15 V, V–=0V,TA= 25°C, unless otherwise specified.

Figure 21. Open Loop Frequency Response Figure 22. Input Voltage vs Output Voltage

Figure 24. Sourcing Current vs Output Voltage

Figure 23. Input Voltage Noise vs Input Voltage

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Typical Characteristics: 15 V (continued)

Figure 25. Sinking Current vs Output Voltage Figure 26. CMRR vs Input Voltage

Figure 27. Supply Current vs Supply Voltage Figure 28. Input Current vs Temperature

Figure 29. Output Voltage Swing vs Supply Voltage Figure 30. Input Voltage Noise vs Frequency

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Typical Characteristics: 15 V (continued)

Figure 31. Positive PSRR vs Frequency Figure 32. Negative PSRR vs Frequency

Figure 33. CMRR vs Frequency Figure 34. Open Loop Frequency Response at –40°C

Figure 35. Open Loop Frequency Response at 25°C Figure 36. Open Loop Frequency Response at 85°C

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Typical Characteristics: 15 V (continued)

Figure 38. Gain and Phase vs Capacitive Load

Figure 37. Maximum Output Swing vs Frequency

Figure 39. Gain and Phase vs Capacitive Load Figure 40. Output Impedance vs Frequency

Figure 42. Slew Rate vs Supply Voltage

Figure 41. Slew Rate vs Temperature

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Typical Characteristics: 15 V (continued)

Figure 43. Inverting Small Signal Pulse Response Figure 44. Inverting Small Signal Pulse Response

Figure 45. Inverting Small Signal Pulse Response Figure 46. Inverting Large Signal Pulse Response

Figure 47. Inverting Large Signal Pulse Response Figure 48. Inverting Large Signal Pulse Response

Product Folder Links: LMC7101 LMC7101Q-Q1

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

Typical Characteristics: 15 V (continued)

Figure 49. Noninverting Small Signal Pulse Response Figure 50. Noninverting Small Signal Pulse Response

Figure 51. Noninverting Small Signal Pulse Response Figure 52. Noninverting Large Signal Pulse Response

Figure 53. Noninverting Large Signal Pulse Response Figure 54. Noninverting Large Signal Pulse Response

Product Folder Links: LMC7101 LMC7101Q-Q1

LMC7101

LMC7101Q-Q1

www.ti.com

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

Typical Characteristics: 15 V (continued)

Figure 55. Stability vs Capacitive Load Figure 56. Stability vs Capacitive Load

Figure 57. Stability vs Capacitive Load Figure 58. Stability vs Capacitive Load

Figure 59. Stability vs Capacitive Load Figure 60. Stability vs Capacitive Load

Product Folder Links: LMC7101 LMC7101Q-Q1

IN–

IN+

OUT

V+

V–

–

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

7 Detailed Description

7.1 Overview

The LMC7101 is a single channel, low-power operational amplifier available in a space-saving SOT-23 package,

offering rail-to-rail input and output operation across a wide range of power supply configurations. The

LMC7101Q-Q1 is the automotive Q-grade variant.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Benefits of the LMC7101 Tiny Amplifier

7.3.1.1 Size

The small footprint of the SOT-23-5 packaged tiny amplifier, (0.12 × 0.118 inches, 3.05 × 3 mm) saves space on

printed circuit boards, and enable the design of smaller electronic products. Because they are easier to carry,

many customers prefer smaller and lighter products.

7.3.1.2 Height

The 0.056 inches (1.43 mm) height of the tiny amplifier makes is suitable for use in a wide range of portable

applications in which a thin profile is required.

7.3.1.3 Signal Integrity

Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier

package, the tiny amplifier can be placed closer to the signal source, thus reducing noise pickup and increasing

signal integrity. The tiny amplifier can also be placed next to the signal destination, such as a buffer, for the

reference of an analog-to-digital converter.

7.3.1.4 Simplified Board Layout

The tiny amplifier can simplify board layout in several ways. Avoid long PCB traces by correctly placing amplifiers

instead of routing signals to a dual or quad device.

By using multiple tiny amplifiers instead of duals or quads, complex signal routing and possibly crosstalk can be

reduced.

7.3.1.5 Low THD

The high open-loop gain of the LMC7101 amp allows it to achieve very low audio distortion—typically 0.01% at

10 kHz with a 10-kΩload at 5-V supplies. This makes the tiny amplifier an excellent for audio, modems, and low

frequency signal processing.

7.3.1.6 Low Supply Current

The typical 0.5-mA supply current of the LMC7101 extends battery life in portable applications, and may allow

the reduction of the size of batteries in some applications.

Product Folder Links: LMC7101 LMC7101Q-Q1

LMC7101

LMC7101Q-Q1

www.ti.com

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

Feature Description (continued)

7.3.1.7 Wide Voltage Range

The LMC7101 is characterized at 15 V, 5 V and 3 V. Performance data is provided at these popular voltages.

This wide voltage range makes the LMC7101 a good choice for devices where the voltage may vary over the life

of the batteries.

7.4 Device Functional Modes

7.4.1 Input Common Mode

7.4.1.1 Voltage Range

The LMC7101 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage.

Figure 61 shows an input voltage exceeding both supplies with no resulting phase inversion of the output.

The absolute maximum input voltage is 300-mV beyond either rail at room temperature. Voltages greatly

exceeding this maximum rating, as in Figure 62, can cause excessive current to flow in or out of the input pins,

thus adversely affecting reliability.

An input voltage signal exceeds the LMC7101 power supply A ±7.5-V input signal greatly exceeds the 3-V supply in Figure 63

voltages with no output phase inversion. causing no phase inversion due to RI.

Figure 61. Input Voltage Figure 62. Input Signal

Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input

resistor as shown in Figure 63.

Figure 63. RIInput Current Protection for

Voltages Exceeding the Supply Voltage

Product Folder Links: LMC7101 LMC7101Q-Q1

1 IN 2 f

1 1

2 R C 2 R C

p p

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers must

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Rail-to-Rail Output

The approximate output resistance of the LMC7101 is 180-Ωsourcing and 130-Ωsinking at VS= 3 V and 110-Ω

sourcing and 80-Ωsinking at VS= 5 V. Using the calculated output resistance, maximum output voltage swing

can be estimated as a function of load.

8.1.2 Capacitive Load Tolerance

The LMC7101 can typically directly drive a 100-pF load with VS= 15 V at unity gain without oscillating. The unity

gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of

operational amplifiers. The combination of the output impedance and the capacitive load of the operational

amplifier induces phase lag, which results in either an underdamped pulse response or oscillation.

Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 64. This simple

technique is useful for isolating the capacitive input of multiplexers and A/D converters.

Figure 64. Resistive Isolation

of a 330-pF Capacitive Load

8.1.3 Compensating for Input Capacitance When Using Large Value Feedback Resistors

When using very large value feedback resistors, (usually > 500 kΩ) the large feed back resistance can react with

the input capacitance due to transducers, photo diodes, and circuit board parasitics to reduce phase margins.

The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor

(as in Figure 65), Cfis first estimated by Equation 1 and Equation 2, which typically provides significant

overcompensation.

(1)

R1CIN ≤R2Cf(2)

Printed circuit board stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum

value for CFmay be different. The values of CFmust be checked on the actual circuit (refer to CMOS Quad

Operational Amplifier (SNOSBZ3) for a more detailed discussion).

Product Folder Links: LMC7101 LMC7101Q-Q1

–

OUT

V+

V–

LMC7101

LMC7101Q-Q1

www.ti.com

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

Application Information (continued)

Figure 65. Cancelling the Effect of Input Capacitance

8.2 Typical Application

Figure 66 shows a high input impedance noninverting circuit. This circuit gives a closed-loop gain equal to the

ratio of the sum of R1 and R2 to R1 and a closed-loop 3-dB bandwidth equal to the amplifier unity-gain

frequency divided by the closed-loop gain. This design has the benefit of a very high input impedance, which is

equal to the differential input impedance multiplied by loop gain. (Open loop gain/Closed loop gain.) In DC

coupled applications, input impedance is not as important as input current and its voltage drop across the source

resistance. The amplifier output will go into saturation if the input is allowed to float, which may be important if

the amplifier must be switched from source to source.

Figure 66. Example Application

Product Folder Links: LMC7101 LMC7101Q-Q1

VDD

Gain = 1 + R /R

2 1

= 101 (as shown)

V (mV)

V (V)

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

Typical Application (continued)

8.2.1 Design Requirements

For this example application, the supply voltage is 5 V, and 100 × ±5% of noninverting gain is necessary. The

signal input impedance is approximately 10 kΩ.

8.2.2 Detailed Design Procedure

Use the equation for a noninverting amplifier configuration; G = 1 + R2 / R1, set R1 to 10 kΩ, and R2 to 99 × the

value of R1, which would be 990 kΩ. Replacing the 990-kΩresistor with a more readily available 1-MΩresistor

will result in a gain of 101, which is within the desired gain tolerance. The gain-frequency characteristic of the

amplifier and its feedback network must be such that oscillation does not occur. To meet this condition, the

phase shift through amplifier and feedback network must never exceed 180° for any frequency where the gain of

the amplifier and its feedback network is greater than unity. In practical applications, the phase shift must not

approach 180° because this is the situation of conditional stability. The most critical case occurs when the

attenuation of the feedback network is zero.

8.2.3 Application Curve

Figure 67. Output Response

Product Folder Links: LMC7101 LMC7101Q-Q1

LMC7101

LMC7101Q-Q1

www.ti.com

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

9 Power Supply Recommendations

For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing

10-nF to 1-µF capacitors as close as possible to the operational-amplifier power supply pins. For single supply

configurations, place a capacitor between the V+and V–supply pins. For dual supply configurations, place one

capacitor between V+and ground, and place a second capacitor between V–and ground. Bypass capacitors

must have a low ESR of less than 0.1 Ω.

10 Layout

10.1 Layout Guidelines

Care must be taken to minimize the loop area formed by the bypass capacitor connection between supply pins

and ground. A ground plane underneath the device is recommended; any bypass components to ground must

have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding

supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the

power-supply inductance and provide a more stable power supply.

The feedback components must be placed as close as possible to the device to minimize stray parasitics.

10.2 Layout Example

Figure 68. LMC7101 Example Layout

Product Folder Links: LMC7101 LMC7101Q-Q1

LMC7101

LMC7101Q-Q1

SNOS719G –SEPTEMBER 1999–REVISED SEPTEMBER 2015

www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

For additional information, see LMC660 CMOS Quad Operational Amplifier (SNOSBZ3).

11.2 Related Links

Table 1 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LMC7101 Click here Click here Click here Click here Click here

LMC7101Q-Q1 Click here Click here Click here Click here Click here

11.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMC7101 LMC7101Q-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 19-Feb-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC7101AIM5 NRND SOT-23 DBV 5 1000 Non-RoHS

& Green Call TI Call TI -40 to 85 A00A

LMC7101AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A00A

LMC7101AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A00A

LMC7101BIM5 NRND SOT-23 DBV 5 1000 Non-RoHS

& Green Call TI Call TI -40 to 85 A00B

LMC7101BIM5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A00B

LMC7101BIM5X NRND SOT-23 DBV 5 3000 Non-RoHS

& Green Call TI Call TI -40 to 85 A00B

LMC7101BIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A00B

LMC7101QM5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AT6A

LMC7101QM5X/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AT6A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 19-Feb-2021

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC7101AIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101AIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101BIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101BIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101BIM5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101QM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMC7101QM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC7101AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0

LMC7101AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LMC7101BIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0

LMC7101BIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMC7101BIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0

LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LMC7101QM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMC7101QM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/E 09/2019

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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