© 2011 Semiconduc tor Component s Indus tries ,LLC .
October-2017,R ev 2 Publication Order Number:
FPF1321/D
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Switch
FPF1320 / FPF1321
IntelliMAX™ Dual-Input Single-Output Advanced Power
Switch with True Reverse-Current Blocking
Features
DISO Load Sw itches
Input Supply Operating Range: 1.5 V ~ 5.5 V
RON 50 mΩ at VIN=3.3 V Per Channel (Typical)
True Reverse-Current Blocking (TRCB)
Fixed Slew Rate Controlled 130 µs for < 1 µF COUT
ISW: 1.5 A Per Channel (Maximum)
Quick Discharge Feature on FPF1321
Logic CMOS IO Meets JESD76 Standard for GPI O
Interfac e and Related Pow er Supply Requirements
ESD Protected:
-Human Body Model: >6 kV
-Charged Device Model: >1.5 kV
-IEC 61000-4-2 Air Discharge: >15 kV
-IEC 61000-4-2 Contact Discharge: >8 kV
Applications
Smart phones / Tablet PCs
Portable Devices
Near Field Communication (NFC) Capable
SIM Card Power Supply
Description
The FPF1320/21 is a Dual-Input Single-Output (DISO)
load sw itch consisting of two sets of slew -rate
controlled, low on-resistance, P-channel MOSFET
sw itches and integrate d ana log f eatures . The s lew-rate-
controlled turn-on c harac teristic prevents inrush current
and the res u ltin g ex cessive v oltage dr o op on the power
rails. The input voltage range operates from 1.5 V to
5.5 V to align w ith the requirements of low -voltage
portable device pow er rails. FPF1320/21 performs
seamless power-source transitions between tw o input
power rails using the SEL pin with advanced break-
before-make operation.
FPF1320/21 has a TRCB function to block unwanted
reverse current from output to input during ON/OFF
states. The sw itch is controlled by logic inputs of the
SEL and EN pins, which are capable of interfacing
directly w ith low -voltage control signals (GPIO).
FPF1321 has 65 Ω on-chip load resistor for output quick
dis char ge when EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP,
6-bu mp, w ith 0.5 mm pitch. FPF1321B is available in
1.0 mm x 1. 5 mm WLCSP, 6-bump, 0.5 mm pitch w ith
backside laminate.
Ordering Information
Part N umbe r
Top
Mark Channel
Switch Per
Channel (Typ.
)
at 3.3 VIN
Reverse
Current
Blocking
Output
Discharge
Rise
Time (tR)
Package
FPF1320UCX QS DISO 50 mΩ Yes NA 130 µs 1.0 mm X 1.5 mm
Wafer-Lev el Chip-
Scale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch
FPF1321UCX QT DISO 50 mΩ Yes 65 Ω 130 µs
FPF1321BUCX QT DISO 50 mΩ Yes 65 Ω 130 µs
1.0 mm X 1.5 mm
Wafer-Level Chip-
Scale Package
(WLCSP) 6-Bumps,
0.5 mm Pitc h w ith
Backside Laminate
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Application Diagram
C
OUT
FPF1320/21
V
IN
AV
OUT
V
IN
BGND
C
IN1
ENSEL
V
IN
_A
V
IN
_B
C
IN2
Block D iagr am
Turn-On Slew Rate
Controlled Driver
FPF1320/21
Output Discharge
(Optinal)
V
IN
A
SEL
V
OUT
GND
TRCB
V
IN
BTRCB
CONTROL
LOGIC
Turn-On Slew Rate
Controlled Driver
EN
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Pin Configuration
Figure 3. Pin Configuration i n Package View with Pin 1 Indi cator
A1 A2
B1 B2
C1 C2
V
IN
A
V
IN
B
GND
V
OUT
EN
SEL
A2 A1
B2 B1
C2 C1
V
IN
A
V
IN
BGND
V
OUT
EN
SEL
T op Vi ew Bottom Vi ew
Figure 4. Pin Assignments
Pin De scription
Pi n # Name Description
A1
EN
Enable input. Active HIGH. There is an internal pull-down resistor at the EN pin.
B1 SEL Input power selection inputs. See Table 1. There are internal pull-down resistors at the
SEL pins.
A2
V
IN
A
Supply Input. I nput to the power switch A.
B2
V
OUT
Sw itch output
C1
GND
Ground
C2
V
IN
B
Supply Input. I nput to pow er sw itch B.
Tab le 1. Trut h Table
SEL
EN
S witc h A
S witc h B
V
OUT
Status
LOW
HIGH
ON
OFF
V
IN
A
V
IN
A Selected
HIGH HIGH OFF ON VINB VINB Selected
X LOW OFF OFF Floating for FPF1320
GND for FPF 1321 Both Switches are OFF
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operab le above th e r eco mme nded operati ng cond iti ons and s tres sing the parts to these lev els is not rec o mmend ed.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reli ability.
The abs olute max imum ratings ar e s tres s ratings only.
Symbol
Parameters
Min.
Max.
Unit
V
IN
V
IN
A, V
IN
B, V
SEL
, V
EN
, V
OUT
to GND
-0.3
6
V
I
SW
M axim um Continuous Switch C urrent per Channel
1.5
A
P
D
Total Pow er Dissipation at T
A
=25°C
1.2
W
T
STG
Operating and Storage Junction Temperature
-65
150
°C
ΘJA Thermal Resistance, Junction-to-Ambient
(1 in.2 Pad of 2-oz. Copper)
85(1)
°C/W
110(2)
ESD Electrostatic Discharge
Capability
Human Body Model, JESD22-A114
6.0
kV
Charged Device Model, JESD22-C101
1.5
Air Discharge (VINA, VINB to GND),
IEC61000-4-2 System Level 15.0
Contact Discharge (VINA, VINB to
GND), IEC61000-4-2 System Level 8.0
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Meas ured us ing 2S2P JEDEC PCB cold-plate method.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend ex ceeding them or designing to Absolute Maximum Ratings.
Symbol Parameters Min. Max. Unit
V
IN
Input Voltage on V
IN
A, V
IN
B
1.5
5.5
V
T
A
Ambient Operating Temperature
-40
85
°C
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Electr ical C haracte r istics
VINA=VINB=1.5 to 5.5 V, TA=-40 to 85°C unless otherwise noted. Typical values are at VINA=VINB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Min.
Typ.
Max.
Unit
Basic Op e rat ion
V
IN
A, V
IN
B
Input Voltage
1.5
5.5
V
ISD Shutdown Current SEL=HIGH or LOW, EN=GND,
VOUT=GND, V INA=VINB=5.5 V 5 µA
IQ Quiescent Current
I
OUT
=0mA, SEL=HIGH or LOW,
EN=HIGH, VINA=VINB=5.5 V 12 22 μA
RON On-Resistance
VINA=VINB=5.5 V, IOUT=200 mA,
TA=25°C 42 60
mΩ
VINA=VINB=3.3 V, IOUT=200 mA,
TA=25°C 50
V
IN
A=V
IN
B=1.8 V, I
OUT
=200 mA,
TA=25°C to 85°C 80
VINA=VINB=1.5 V, IOUT=200 mA,
TA=25°C 170
VIH SEL, EN Input Logic High
Voltage VINA, VINB=1.5 V – 5.5 V 1.15 V
VIL
SEL, EN Input Logic Low
Voltage VINA, VINB=1.8 V – 5.5 V 0.65 V
SEL, EN Input Logic Low
Voltage VINA, VINB=1.5 V – 1.8 V 0.60
VDROOP_OUT Output Voltage Droop w hile
Channel Switching from
Higher Input Voltage Lower
Input Voltage(3)
VINA=3.3 V, VINB=5 V, Switching from
VINA VINB, RL=150 Ω, COUT=1 µF 100 mV
ISEL/IEN
Input Leakage a t S EL and
EN Pin 1.2 μA
RSEL_PD/REN_PD Pull-Down Resistance at
S EL o r EN Pin 7 MΩ
RPD Output Pull-Dow n
Resistance SEL=HIGH or LOW, EN=GND,
IFORCE=20 mA, TA=25°C, FPF1321 65 Ω
True R everse Current B locking
V
T_RCB
RCB Protection Tr ip Point
V
OUT
- V
IN
A or V
IN
B
45
mV
VR_RCB
RCB Protection Release
Trip Point VINA or VINB -VOUT 25 mV
IRCB VINA or VINB Current During
RCB VOUT=5.5 V, VINA or VINB=Short to
GND 9 15 μA
tRCB_ON RCB Response Time w hen
Device is ON(3) VINA or VINB=5 V, VOUTVINA,B=100 mV 5 µs
Conti nued on the fol lowi ng page…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Elect rical C har acter istics (Continued)
VINA=VINB= 1.5 to 5.5 V, T A=-40 to 85°C unless otherwise noted. Typical values ar e at V INA=VINB=3.3 V and TA=25°C.
Symbol Parameters Condition Min. Typ. Max. Unit
Dyn am ic Char acte r is t ics
t
DON
Turn-On Delay(4)
VINA or VINB=3.3 V, R L=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: LOW HIGH
120
μs
t
R
V
OUT
Ris e Time(4)
130
μs
t
ON
Turn-On Time(6)
250
μs
t
DOFF
Turn-Off Delay(4)
VINA or VINB=3.3 V, R L=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW
15
μs
t
F
V
OUT
Fall Time(4)
320
μs
t
OFF
Turn-Off Time(7)
335
μs
t
DOFF
Turn-Off Delay(4,5)
VINA or VINB =3.3 V, RL=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW,
Output Discharge Mode, FPF1321
6
μs
t
F
V
OUT
Fall Time(4,5)
110
μs
tOFF Turn-Off Time
(5,7)
116 μs
tTRANR Transition Time
LOW HIGH(4) VINA=3.3 V, VINB=5 V,
Switching from VINA VINB,
SEL: LOW HIGH, EN: HIGH,
RL=150 Ω, CL=1 µF, TA=25°C
3 μs
tSLH Sw itch-Over Rising Delay
(4)
1 μs
tTRANF Transition Time
HIGH LOW(4) VINA=3.3 V, VINB=5 V,
Switching from VINB VINA,
SEL: HIGH LOW, EN: HIGH,
RL=150 Ω, C=1 µF, TA=25°C
45 μs
tSHL Sw itch-Over Falling D elay(4) 5 μs
Notes:
3. This parameter is guaranteed by des ign and c harac terization; not produc tion tes ted.
4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 5.
5. FPF1321 output discharge is enabled during off.
6. tON=tR + tDON.
7. tOFF=tF + tDOFF.
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
T iming Diagram
V
IN
A
Turn-on and V
IN
A
V
IN
B
SEL
EN
V
OUT
5V
3.3V
5V
3.3V
5V
HI
HI
LO
LO
t
DON
t
R
LO
GND GND
Switching from V
IN
A
to V
IN
BShutdown
50%
10%
90%
50% 50%
t
DOFF
t
F
t
SHL
t
SLH
t
TRANF
t
TRANR
V
DROOP
Output discharge
of FPF1321
10%
90% 90% 90%
10%
Shutdown
50%
LO
Switching from V
IN
B
to V
IN
A
Figure 5. Dynamic Behavior Timing Diagram
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Typical
Characteristics
Figure 6. Suppl y Current vs. Temperature
Figure 7. Suppl y Current vs. Supply Voltage
Figure 8. Shutdown Current vs. Temperature
Figure 9. Shutdown Current vs. Supply Voltage
Figure 10. R
ON
vs. Temperature
Figure 11. R
ON
vs. Supply Voltage
C ontinued on the follo win g pag e…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Typical
Characteristics
Figure 12. V
IL
vs. Temperature
Figure 13. V
IL
vs. Supply Voltage
Figure 14. V
IH
vs. Temperature
Figure 15. V
IH
vs. Supply Voltage
Figure 16. V
IH
/ V
IL
vs. Supply Voltage
Figure 17. R
SEL_PD
and R
EN_PD
vs. Temperature
C ontinued on the follo win g pag e…
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10
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Typical
Characteristics
Figure 18. R
SEL_PD
and R
EN_PD
vs. Supply Voltage
Figure 19. t
DON
and t
DOFF
vs. Temperature
Figure 20. t
R
and t
F
with FPF1320 vs. Temperature
Figure 21. t
R
and t
F
with FPF1321 vs. Temperature
Figure 22. Transition Time vs. Temperature
Figure 23. Switch Over Time vs. Temperature
C ontinued on the follo win g pag e…
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11
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Typical
Characteristics
Figure 24. TRCB Tr ip and Release vs. Temperature
Figure 25. I
RCB
vs. Tempera ture
Figure 26. R
PD
with F PF1321 vs. Temperature
Figure 27. Turn-On Response
(VINA=3.3 V, CIN=1 µF, C OUT=1 µF, RL=150 Ω,
SEL=LOW)
Figure 28. Turn-Off Response with FPF1320
(VINA=3.3 V, CIN=1 µF, C OUT=1 µF, RL=150 Ω,
SEL=LOW)
Figure 29. Turn-Off Response with FPF1321
(VINA=3.3 V, CIN=1 µF, C OUT=1 µF, RL=150 Ω,
SEL=LOW)
C ontinued on the follo win g pag e…
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12
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Sw itch
Typical
Characteristics
Figure 30. Power Source Transition from 3.3 V to 5 V
(VINA=3.3 V, VINB=5 V, CIN=1 µF, COUT=1 µF,
RL=150 Ω)
Figure 31. Power Source Transition from 5 V to 3.3
V
(VINA=3.3 V, VINB=5 V, CIN=1 µF, COUT=1 µF,
RL=150 Ω)
Figure 32. TRCB During Off (VINA=VINB=Floating,
VOUT=5V, CIN=1 µF, COUT=1 µF, EN=LOW, No RL) Figure 33. TRCB During On (VINA=5 V, VOUT=6 V,
CIN=1 µF, C OUT=1 µF, EN=HIGH, No RL)
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Switch
Operation and Application D e scription
The FPF1320 and FPF13 21 are dual-input single-output
power multiplexer sw itches w ith controlled turn-on and
seamless power s ourc e trans ition. Th e c ore is a 50 mΩ
P-channel MOSFET and controller capable of
functioning over a w ide input operating range of 1.5 V to
5.5 V per channel. The EN and SEL pins are active-
HIGH, GPIO/CMOS-compatible input. They control the
state of the switch and input power source selection,
respectively. TRCB functionality blocks unw anted
reverse current during both ON and OFF states w hen
hi gher VOUT than VINA or VINB is applied. FPF1321 has a
65 Ω output discharge path during off.
Input Capacito r
To limit t he volt age dro p on the input su pply c aused by
trans ient inrus h curr ent when the switch turns on into a
discharged load capac itor; a capacitor must be placed
between the VINA or VIN B pins to the GND pin. At least
1 µF c era mic c apaci tor, CIN, placed clos e to th e pins, is
usually sufficient. Higher-value CIN can be used to
reduce more the v oltage drop.
Inrush C urr en t
Inrush current occurs when the device is turned on.
Inr ush c urr ent is dep end ent on output capac itance and
slew rate control capability, as expressed by:
LOAD
R
INITIALIN
OUTINRUSH
I
tVV
CI +
−
×=
(1)
where:
COUT: Output capacitance;
tR: Slew rate or rise time at VOUT;
VIN: Input voltage, VINA or VINB;
VINITIAL: Initial voltage at COUT, us ually GND; and
ILOAD: Load cur rent.
Higher inrush c urrent c auses h igher in put v o ltage drop,
depen din g on the distrib uted in put res is ta nce an d i nput
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130 µs of slew rate capability under
3.3 VIN at 1 µF of COUT and 150 Ω of R
L so inrush
current and input v oltage drop can be minimized.
Power Source Selec tio n
Input pow er source selection can be controlled by the
SEL pin. When SEL is LOW, output is pow ered from
VINA w hile SEL is HIGH, VINB is pow ering output. The
SEL signal is ignored during device OFF.
Output V oltage Dro p dur ing T ransitio n
Output voltage drop usually occurs during input pow er
source transition period from low voltage to high
voltage. The drop is highly dependent on output
capac itanc e and load cur rent.
FPF1320/1 adopts an advanced break-before-make
control, w hich can result in minimized output voltage
drop during the transition time.
Output Capacito r
Capacitor COUT of at least 1 µF is hi ghly rec o mmen ded
between the VOUT and G ND pins to achieve minimized
output voltage drop during input power source transition.
This capac itor also prevents paras itic board inductanc e.
True Reverse-Cu r rent Blocki ng
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switc h is on or of f.
Board L ay out
For bes t p erf or manc e, a ll trac es s hou ld be as s hort as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
normal and shor t-circuit operat ion . Wide trac es or large
copper planes for power pins (VINA, VIN B, VOUT and
GND) minimize the parasitic electrical effects and the
thermal impedance.
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14
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Switch
Physical Dimensions
Figure 34. 6-Ball, 1.0 x 1.5 mm, Wafer-Level Chip-Scale Package (WLCSP)
Product-Spe cific Dime nsions
Product D E X Y
FPF1320UCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
FPF1321UCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
FPF1321BUCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
Pac kage dr awin gs ar e pr ovi ded as a ser vice t o cus tomer s c onside r ing ON Semiconduc tor components. D r awin gs may c hange in
any manner withou t noti ce. Pl ea s e note the r evisio n and /or date on the dr aw in g and c onta c t a ON Semiconductor r epr es en tati ve to
ver ify or obtain the most r ecent r evision. Package specifications do not expand the term s of ON Sem iconductor’s worldwide term s and
conditions, specifically the warr anty therein, which covers ON Sem iconductor products.
BOTTOM VIEW
SIDE VIEWS
RECOMMENDED LAND PATTERN
BALL A1
INDEX AREA
SEATING PLANE
A1
F
(NSMD PAD TYPE)
(Ø0.350)
SOLDER MASK
OPENING
(X) ±0.018
(Y) ±0.018
(Ø0.250)
Cu Pad
0.06 C
0.05 C
E
D
F
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
0.03 C
2X
0.03 C
2X
Ø0.315 +/- .025
6X
12
A
B
C
0.332±0.018
0.250±0.025
D
E
(1.00)
(0.50)
0.005 C A B
0.50
0.50
1.00
0.625
0.539
TOP VIEW
B
A
C
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output A dvanced Pow er Switch
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